Sample records for wafer scale liga

  1. A Batch Wafer Scale LIGA Assembly and Packaging Technique vai Diffusion Bonding

    SciTech Connect

    Christenson, T.R.; Schmale, D.T.

    1999-01-27

    A technique using diffusion bonding (or solid-state welding) has been used to achieve batch fabrication of two- level nickel LIGA structures. Interlayer alignment accuracy of less than 1 micron is achieved using press-fit gauge pins. A mini-scale torsion tester was built to measure the diffusion bond strength of LIGA formed specimens that has shown successful bonding at temperatures of 450"C at 7 ksi pressure with bond strength greater than 100 Mpa. Extensions to this basic process to allow for additional layers and thereby more complex assemblies as well as commensurate packaging are discussed.

  2. The influence of wafer elasticity on acoustic waves during LIGA development.

    SciTech Connect

    Ting, Aili

    2003-12-01

    During acoustically stimulated LIGA development, a wafer receives sound waves from both sides at a wide variety of incidence angles that vary in time depending on the orientation of the wafer relative to the multiple transducers that are typically actuated in a periodic sequence. It is important to understand the influence of these variables on the transmission of energy through the wafer as well as the induced motion of the wafer itself because these processes impact the induced acoustic streaming of the fluid within features, the mechanism presently thought responsible for enhanced development of LIGA features. In the present work, the impact of wafer elasticity on LIGA development is investigated. Transmission waves, wafer bending waves, and the related concepts such as critical bending frequency, mechanical impedance, coincidence, and resonance, are discussed. Supercritical-frequency incident waves induce supersonic bending waves in the wafer. Incident wave energy is channeled into three components, transmitted, reflected and energy deposited to the wafer, depending on the wafer material, thickness and wave incidence angle. Results show at normal incidence for a 1-mm PMMA wafer, about 47% of the wave energy is deposited in the wafer. The wafer gains almost half of the incident energy, a result that agrees well with the Bankert et a1 measurements. In LIGA development, transmitted waves may sometimes produce strong acoustic motion of the developer on the wafer backside, especially for the so-called coincidence case in which almost all incident wave energy transfers to the backside. Wafer bending waves cause wafer oscillation at high frequency, promoting the development process, but features shaking may weaken their attachments to the substrate. Resonance is not likely for the entire wafer, but may occur in short and wide wafer feature columns, which are least likely to break away from the substrate, perhaps resulting in good agitation of the fluid in adjacent feature cavities.

  3. A radix-8 wafer scale FFT processor

    Microsoft Academic Search

    Earl E. Swartzlander Jr.; Vijay K. Jain; Hiroomi Hikawa

    1992-01-01

    Wafer Scale Integration promises radical improvements in the performance of digital signal processing systems. This paper describes the design of a radix-8 systolic (pipeline) fast Fourier transform processor for implementation with wafer scale integration. By the use of the radix-8 FFT butterfly wafer that is currently under development, continuous data rates of 160 MSPS are anticipated for FFTs of up

  4. Design automation for wafer scale integration

    SciTech Connect

    Donlan, B.J.

    1986-01-01

    Wafer scale integration (WSI) is a technique for implementing large digital systems on a single wafer. This thesis describes a system of design automation tools developed to aid in the implementation of wafer scale integrated systems. An overview of wafer scale integration is given with fabrication details and yield considerations discussed. The Wafer architectural Design Language (WDL) used to describe and specify a system architecture to the development system is introduced along with a compiler that translates the high level WDL description into net lists and other internal data bases. Interactive placement tools used to map the system architecture onto the functional die sites on a wafer are described. A very fast line probe router was developed to perform the custom wafer level routing need to personalize each wafer. Router data structures, algorithms, techniques, and results are discussed in detail. Sample wafer scale architectures and the result of their WSI implementations are shown. Also presented is the Wafer Transmission Module (WTM) a packaging technology related to wafer scale integration.

  5. Wafer scale architecture for an FFT processor

    Microsoft Academic Search

    V. K. Jain; H. A. Nienhaus; D. L. Landis; S. Al-Arian; C. E. Alvarez

    1989-01-01

    A description is given of research on a WSI FFT processor. Attention is focused on the design methodology, architecture, and sparing strategy and restructuring. The basic cells utilized are the MSA and the coefficient ROM. The wafer thus has only two types of cell, making the algorithm highly suitable for restructable wafer-scale integration (WSI) design. The restructuring algorithm is discussed

  6. Wafer Level Chip Scale Packaging

    Microsoft Academic Search

    Michael Töpper

    \\u000a Wafer Level Packaging (WLP) based on redistribution is the key technology which is evolving to System in Package (SiP) and\\u000a Heterogeneous Integration (HI) by 3-D packaging using Through Silicon Vias (TSV). Materials and process technologies are key\\u000a for a reliable WLP. It is not only the choice for the right polymer or metal but the interfaces could be even more

  7. A wafer-scale 3-D circuit integration technology

    Microsoft Academic Search

    James A. Burns; Brian F. Aull; Chenson K. Chen; Chang-Lee Chen; Craig L. Keast; Jeffrey M. Knecht; V. Suntharalingam; K. Warner; P. W. Wyatt; D.-R. W. Yost

    2006-01-01

    The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances.

  8. Restructurable VLSI-a demonstrated wafer-scale technology

    Microsoft Academic Search

    PETER W. WYATT; JACK I. RAFFEL

    1989-01-01

    Restructurable VLSI (RVLSI) is an approach to wafer-scale integration which has been demonstrated by building six different monolithic silicon, wafer-scale chips for signal processing applications. It is based on the implementation of redundancy by laser microwelding on a finished, tested, packaged wafer. The concept of RVLSI is discussed, the chips built to data are reviewed, and some of the major

  9. Parallel Assembly of LIGA Components

    SciTech Connect

    Christenson, T.R.; Feddema, J.T.

    1999-03-04

    In this paper, a prototype robotic workcell for the parallel assembly of LIGA components is described. A Cartesian robot is used to press 386 and 485 micron diameter pins into a LIGA substrate and then place a 3-inch diameter wafer with LIGA gears onto the pins. Upward and downward looking microscopes are used to locate holes in the LIGA substrate, pins to be pressed in the holes, and gears to be placed on the pins. This vision system can locate parts within 3 microns, while the Cartesian manipulator can place the parts within 0.4 microns.

  10. A generic architecture for wafer-scale neuromorphic systems

    SciTech Connect

    Raffel, J.I.; Mann, J.R.; Berger, R.; Soares, A.M.; Gilbert, S.L. (MIT, Lexington, MA (USA); Spectrix Corp., Evanston, IL (USA))

    1989-01-01

    The massive parallelism and high fan-out characteristics of neural networks impose interconnection requirements that are too extreme for IC-implementation; wafer-scale integration, however, interconnects many circuits on a wafer, thereby eliminating wirebonds, package pins, and external printed-circuit wiring. A generic wafer-scale device for neural networks has been devised which employs multiplying D/A converters for programmable synapses and operational amplifiers for summing nodes. Upon fabrication of each such wafer, laser cuts and links may be used to both define network connectivity and furnish defect-avoidance for the improvement of production yields. 7 refs.

  11. Wafer level chip scale packaging (WL-CSP): an overview

    Microsoft Academic Search

    Philip Garrou

    2000-01-01

    Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing. Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP's when

  12. Wafer-Scale Fabrication of Plasmonic Crystals from Patterned Silicon Templates Prepared by Nanosphere Lithography

    E-print Network

    Wafer-Scale Fabrication of Plasmonic Crystals from Patterned Silicon Templates Prepared Supporting Information ABSTRACT: By combining nanosphere lithography with template stripping, silicon wafers then replicated in gold by metal evaporation, resulting in wafer-scale hexagonal gratings for plasmonic

  13. Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

    NASA Astrophysics Data System (ADS)

    Mieda, Eiko; Maeda, Tatsuro; Miyata, Noriyuki; Yasuda, Tetsuji; Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki; Aoki, Takeshi; Yamamoto, Taketsugu; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko; Ogawa, Arito; Kikuchi, Toshiyuki; Kunii, Yasuo

    2015-03-01

    We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

  14. Wafer-scale aluminum nano-plasmonics

    NASA Astrophysics Data System (ADS)

    George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

    2014-09-01

    The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

  15. Wafer-Scale Modeling of Pattern Effect in Oxide Chemical Mechanical Polishing

    E-print Network

    Boning, Duane S.

    1 Wafer-Scale Modeling of Pattern Effect in Oxide Chemical Mechanical Polishing Dennis Oumaa of the die location on the wafer, thus a combined wafer/die pattern dependent polish- ing model is required stage modeling methodology which accounts for both wafer-scale variation and within-die pattern

  16. LIGA Micromachining

    NSDL National Science Digital Library

    This YouTube video, created by Southwest Center for Microsystems Education (SCME), provides an overview of the LIGA (Lithography, Electroplating, and Molding) technique for micromachining. The lecture runs for 7:25 seconds and describes LIGA as part of micromachining fabrication, including lithography, process, and post-process steps. More information can be found on the SCME website. 

  17. Liga developer apparatus system

    DOEpatents

    Boehme, Dale R. (Pleasanton, CA); Bankert, Michelle A. (San Francisco, CA); Christenson, Todd R. (Albuquerque, NM)

    2003-01-01

    A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

  18. Zinc Oxide Nanowires Low-Temperature Wafer-Scale Production of

    E-print Network

    Yang, Peidong

    Zinc Oxide Nanowires Low-Temperature Wafer-Scale Production of ZnO Nanowire Arrays** Lori E. Greene aqueous conditions. We present data for arrays on four-inch (ca. 10 cm) silicon wafers and two) wafer to form a 50­200-nm thick film of crystal seeds. Between coatings, the wafer was annealed at 1508C

  19. Wafer scale packaging for a MEMS video scanner

    NASA Astrophysics Data System (ADS)

    Helsel, Mark P.; Barger, Jon; Wine, David W.; Osborn, Thor D.

    2001-04-01

    Miniaturized scanners have proven their usefulness in a host of applications including video display, bar code reading, image capture, laser printing and optical switching. In order for these applications to reach fruition, however, the MEMS scanner component must be packaged in a manner that is compatible with the volume manufacturing capabilities of the technology. This paper describes a process that was developed to package an SVGA resolution (800 X 600) biaxial video scanner. The scanner is designed for a head mounted display product, targeted to the medical and industrial markets. The scanner is driven magnetically on one axis and capacitively on the other axis. The first level wafer scale package described here incorporates the capacitive drive electrodes into the mounting substrate. The substrate wafer and the device wafer are then bonded using a glass frit sealing technique. Finally, the scanner and substrate are hermetically sealed into a metal can at reduced pressure.

  20. The Ultra CSPTM wafer scale package

    Microsoft Academic Search

    P. Elenius

    1998-01-01

    There has been a significant amount of work over the past 5 years on chip scale packaging. The majority of this work has been an extension of conventional IC packaging technology utilizing either wire bonders and\\/or TAB type packaging technology. Handling discrete devices during the IC packaging for these type of CSPs has resulted in a relatively high cost for

  1. Comparison of Wafer Scale Integration with VLSI Packaging Approaches

    Microsoft Academic Search

    C. Neugebauer; R. Carlson

    1987-01-01

    A comparison is made of various high-density packaging approaches, including printed wiring board, thick-film hybrids, and wafer scale integration (WSI). Criteria include power dissipation, density, delays, and cost. It is concluded that thin-film hybrids using state-of-the-art VLSI chips have the potential for WSI density and performance. The requirement for fault tolerance, additional levels of metallization, excess power dissipation, process conservatism

  2. Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors

    E-print Network

    Zhou, Chongwu

    Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display Applications compatibility. Here in this paper, we report our progress on wafer-scale processing of separated nanotube thin-film transistors (SN-TFTs) for display applications, including key technology components such as wafer

  3. Wafer-scale Micromolding of Unitary Polymeric Microstructures with Simultaneously Formed Functional

    E-print Network

    ): a 4 inch wafer scale, a unit array of 15 mm in diameter, a magnified snow-flake array, and a single master structures in 4-inch wafer scale 15mm 1mm wafer to molded 1µm dimple features. The fabricated unitary structure is mechanically rigid

  4. Wafer-scale fabrication of nanoapertures using corner lithography

    NASA Astrophysics Data System (ADS)

    Burouni, Narges; Berenschot, Erwin; Elwenspoek, Miko; Sarajlic, Edin; Leussink, Pele; Jansen, Henri; Tas, Niels

    2013-07-01

    Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated—based on a theoretical foundation including a statistical analysis—with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures.

  5. Wafer-scale fabrication of nanoapertures using corner lithography.

    PubMed

    Burouni, Narges; Berenschot, Erwin; Elwenspoek, Miko; Sarajlic, Edin; Leussink, Pele; Jansen, Henri; Tas, Niels

    2013-07-19

    Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated--based on a theoretical foundation including a statistical analysis--with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures. PMID:23792365

  6. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

  7. Nickel Micro-spike for Micro-scale Biopsy using LiGA Process

    NASA Astrophysics Data System (ADS)

    Kim, Gilsub; Park, Sunkil; Koo, Kyo-In; Choi, Hyun-Min; Jung, Myeong-Jun; Song, Si-Young; Bang, Seoung-Min; Cho, Dongil ``Dan''

    2007-01-01

    In this paper, biopsy tools are developed for minimally invasive tissue sampling using the LiGA (Lithographie Galvanoformung Abformung) process. The micro-spike is composed of two barbed-shanks and a body. The shank of the micro-spike is between 2 mm ˜ 3 mm and the opening gap is approximately 350 ?m between the shanks. The micro-spike is integrated with the conventional catheter, for medical diagnostics. Tissue samples were extracted from the anesthetized pigs using biopsy catheters in vivo, and observed with hematoxylin and eosin (H&E) staining. The amount of extracted sample is sufficient to diagnose abnormal cells.

  8. Wafer-Scale High-Throughput Ordered Growth of Vertically Aligned ZnO Nanowire

    E-print Network

    Wang, Zhong L.

    Wafer-Scale High-Throughput Ordered Growth of Vertically Aligned ZnO Nanowire Arrays Yaguang Wei aligned ZnO nanowire (NW) arrays with high throughput and low cost at wafer scale without using cleanroom with the photoresist SU-8. ZnO NWs are selectively grown through the holes via a low- temperature hydrothermal method

  9. MRS Spring Meeting, April 26, 2000, San Francisco, CA Using Wafer-Scale Patterns for CMP Analysis

    E-print Network

    Boning, Duane S.

    MRS Spring Meeting, April 26, 2000, San Francisco, CA Using Wafer-Scale Patterns for CMP Analysis Clara, CA ABSTRACT A new set of wafer-scale patterns has been designed for analysis and modeling of key the planarization capability of a CMP process using simple measurements on wafer scale patterns. We examine means

  10. Pressure Waves Induced by Megasonic Agitation in a LIGA Development Tank

    SciTech Connect

    Aili Ting

    2002-08-01

    Megasonic agitation is used to improve the uniformity of the LIGA{sup 1} development process. To investigate the acoustic wave fields induced by megasonic agitation, we compute wave fields for a development tank containing a submerged wafer and for a typical trench-like feature on the wafer face. This separate treatment of these two problems is advantageous, because the length scales of the tank and the feature differ by three to four orders of magnitude. A spectral method based on Green's functions is used to construct the acoustic wave field, avoiding the alternative of solving partial differential equations over the entire domain. The total acoustic wave field is obtained by superposing of the primary wave field and the first reflected wave field, which are computed in sequence without any need for iterations. The wafer interference to the wave field is treated directly by a priori recognition of shadow regions in the primary field and a concept of boundary of dependence in the reflected field. Unlike a divergent wave field produced by ultrasonic agitation, results show that the wave field in the tank becomes narrowly focused at megasonic frequencies such that the most effective agitation is confined in a region directly above the acoustic source; this numerical expectation has been verified analytically and further confirmed experimentally by Sandia's LIGA Group.{sup [13]} The amplitude of the focused wave pressure is proportional to square root of the wave frequency. The wave pattern in a feature cavity also depends strongly on the orientation of the wafer and the aspect ratio of the cavity. It is concluded that the LIGA development process will be greatly accelerated, if the orientation and the location of the immersed wafer is arranged so that the wafer spends more time in the focused wave field of high frequency agitation.

  11. Wafer-scale arrays of epitaxial ferroelectric nanodiscs and nanorings.

    PubMed

    Han, Hee; Ji, Ran; Park, Yong Jun; Lee, Sung Kyun; Le Rhun, Gwenael; Alexe, Marin; Nielsch, Kornelius; Hesse, Dietrich; Gösele, Ulrich; Baik, Sunggi

    2009-01-01

    Wafer-scale arrays of well-ordered Pb(Zr(0.2)Ti(0.8))O3 nanodiscs and nanorings were fabricated on the entire area (10 mm x 10 mm) of the SrRuO3 bottom electrode on an SrTiO3 single-crystal substrate using the laser interference lithography (LIL) process combined with pulsed laser deposition. The shape and size of the nanostructures were controlled by the amount of PZT deposited through the patterned holes and the temperature of the post-crystallization steps. X-ray diffraction and transmission electron microscopy confirmed that (001)-oriented PZT nanostructures were grown epitaxially on the SrRuO3(001) bottom electrode layer covering the (001)-oriented single-crystal substrate. The domain structures of PZT nano-islands were characterized by reciprocal space mapping using synchrotron x-ray radiation. Ferroelectric properties of each PZT nanostructure were characterized by scanning force microscopy in the piezoresponse mode. PMID:19417246

  12. 498 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 4, JULY 2009 Wafer-Scale Growth and Transfer of Aligned

    E-print Network

    Zhou, Chongwu

    498 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 4, JULY 2009 Wafer-Scale Growth and Transfer, and Subhasish Mitra, Senior Member, IEEE Abstract--Experimental demonstration of wafer-scale growth of well-aligned, dense, single-walled carbon nanotubes on 4 ST- cut quartz wafers is presented. We developed a new carbon

  13. Laser removal of Aluminum links for applications in wafer scale integrated circuits 

    E-print Network

    Parikh, Harshavadan B.

    1987-01-01

    LASER REMOVAL OF ALUMINUM LINKS FOR APPLICATIONS IN WAFER SCALE INTEGRATED CIRCUITS A Thesis by HARSHAVADAN B. PARIKH Submitted to the Graduate College of Texas A&M University in partial fulfillment of the requirement for the degree... of MASTER OF SCIENCE May 1987 Major Subject: Electrical Engineering LASER REMOVAL OF ALUMINUM LINKS FOR APPLICATIONS IN WAFER SCALE INTEGRATED CIRCUITS A Thesis HARSHAVADAN B. PARIKH Approved ss to style snd content by: M. H, Weichold (Chairman...

  14. Fault-tolerant wafer-scale architectures for VLSI

    Microsoft Academic Search

    Donald S. Fussell; Peter J. Varman

    1982-01-01

    The basic problem which limits both yields and chip sizes is the fact that circuits created using current design techniques will not function correctly in the presence of even a single flaw of sufficient size anywhere on the chip. In this work we examine the problem of constructing chips up to the size of a wafer which operate correctly despite

  15. Towards wafer scale inductive determination of magnetostatic and dynamic parameters of magnetic thin films and multilayers

    E-print Network

    Sievers, Sibylle; Nass, Paul; Serrano-Guisan, Santiago; Pasquale, Massimo; Schumacher, Hans Werner

    2013-01-01

    We investigate an inductive probe head suitable for non-invasive characterization of the magnetostatic and dynamic parameters of magnetic thin films and multilayers on the wafer scale. The probe is based on a planar waveguide with rearward high frequency connectors that can be brought in close contact to the wafer surface. Inductive characterization of the magnetic material is carried out by vector network analyzer ferromagnetic resonance. Analysis of the field dispersion of the resonance allows the determination of key material parameters such as the saturation magnetization MS or the effective damping parameter Meff. Three waveguide designs are tested. The broadband frequency response is characterized and the suitability for inductive determination of MS and Meff is compared. Integration of such probes in a wafer prober could in the future allow wafer scale in-line testing of magnetostatic and dynamic key material parameters of magnetic thin films and multilayers.

  16. Simple approach to wafer-scale self-cleaning antireflective silicon surfaces.

    PubMed

    Qi, Dianpeng; Lu, Nan; Xu, Hongbo; Yang, Bingjie; Huang, Chunyu; Xu, Miaojun; Gao, Liguo; Wang, Zhouxiang; Chi, Lifeng

    2009-07-21

    A simple approach to wafer-scale self-cleaning antireflective hierarchical silicon structures is demonstrated. By employing the KOH etching and silver catalytic etching, pyramidal hierarchical structures were generated on the crystalline silicon wafer, which exhibit strong antireflection and superhydrophobic properties after fluorination. Furthermore, a flexible superhydrophobic substrate was fabricated by transferring the hierarchical Si structure to the NOA 63 film with UV-assisted imprint lithography. This method is of potential application in optical, optoelectronic, and wettability control devices. PMID:19537739

  17. 100GHz Transistors from Wafer-Scale Epitaxial Graphene

    Microsoft Academic Search

    Y.-M. Lin; C. Dimitrakopoulos; K. A. Jenkins; D. B. Farmer; H.-Y. Chiu; A. Grill; Ph. Avouris

    2010-01-01

    The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon

  18. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

  19. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

  20. Wafer-scale metasurface for total power absorption, local field enhancement and single

    E-print Network

    Wafer-scale metasurface for total power absorption, local field enhancement and single molecule. Effective electric and magnetic currents supported by SIOM metasurface We perform electromagnetic simulations of a 1 m × 1 m area that models the SEM image of the SIOM metasurface shown as Figure S1a

  1. Wafer-scale metasurface for total power absorption, local field enhancement and

    E-print Network

    Wafer-scale metasurface for total power absorption, local field enhancement and single molecule molecules. Thin layers containing metal nanostructures (``metasurfaces'') can achieve near-total power areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible

  2. Wafer-scale fabrication of high-aspect ratio nanochannels based on edge-lithography technique

    PubMed Central

    Xie, Quan; Zhou, Qing; Xie, Fei; Sang, Jianming; Wang, Wei; Zhang, Haixia Alice; Wu, Wengang; Li, Zhihong

    2012-01-01

    This paper introduced a wafer-scale fabrication approach for the preparation of nanochannels with high-aspect ratio (the ratio of the channel depth to its width). Edge lithography was used to pattern nanogaps in an aluminum film, which was functioned as deep reactive ion etching mask thereafter to form the nanochannel. Nanochannels with aspect ratio up to 172 and width down to 44 nm were successfully fabricated on a 4-inch Si wafer with width nonuniformity less than 13.6%. A microfluidic chip integrated with nanometer-sized filters was successfully fabricated by utilizing the present method for geometric-controllable nanoparticle packing. PMID:22396721

  3. Control of wafer-scale non-uniformity in chemical-mechanical planarization by face-up polishing

    E-print Network

    Mau, Catherine (Catherine K.)

    2008-01-01

    Chemical-mechanical planarization (CMP) is a key process in the manufacture of ultra-large-scale-integrated (ULSI) semiconductor devices. A major concern in CMP is non-uniform planarization, or polishing, at the wafer-scale ...

  4. Low-energy silicon-on-insulator ion implanted gratings for optical wafer scale testing

    NASA Astrophysics Data System (ADS)

    Loiacono, Renzo; Reed, Graham T.; Mashanovich, Goran Z.; Gwilliam, Russell M.; Lulli, Giorgio; Feldesh, Ran; Jones, Richard

    2011-01-01

    Silicon photonics shows tremendous potential for the development of the next generation of ultra fast telecommunication, tera-scale computing, and integrated sensing applications. One of the challenges that must be addressed when integrating a "photonic layer" onto a silicon microelectronic circuit is the development of a wafer scale optical testing technique, similar to that employed today in integrated electronics industrial manufacturing. This represents a critical step for the advancement of silicon photonics to large scale production technology with reduced costs. In this work we propose the fabrication and testing of ion implanted gratings in sub micrometer SOI waveguides, which could be applied to the implementation of optical wafer scale testing strategies. An extinction ratio of over 25dB has been demonstrated for ion implanted Bragg gratings fabricated by low energy implants in submicron SOI rib waveguides with lengths up to 1mm. Furthermore, the possibility of employing the proposed implanted gratings for an optical wafer scale testing scheme is discussed in this work.

  5. Wafer-scale growth of silicon microwire arrays for photovoltaics

    Microsoft Academic Search

    Adele C Tamboli; Christopher T Chen; Emily L Warren; Daniel B Turner-Evans; Michael D Kelzenberg; Nathan S Lewis; Harry A Atwater

    2011-01-01

    Silicon microwire arrays have recently demonstrated their potential for low cost, high efficiency photovoltaics. These high aspect ratio, radial junction wire arrays allow for the absorption of nearly all the incident sunlight while enabling efficient carrier extraction in the radial direction. One of the remaining challenges to make this technology commercially viable is scaling up of the microwire array growth.

  6. Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments.

    PubMed

    Bomer, Johan G; Prokofyev, Alexander V; van den Berg, Albert; Le Gac, Séverine

    2014-12-01

    We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the microchannels, and alignment precision. Experiments on lipid bilayers with electrophysiological recordings using a model pore-forming polypeptide are demonstrated. PMID:25284632

  7. A wafer-scale CMOS APS imager for medical X-ray applications

    Microsoft Academic Search

    L. Korthout; D. Verbugt; J. Timpert; A. Mierop; W. de Haan; W. Maes; J. de Meulmeester; W. Muhammad; B. Dillen; H. Stoldt; I. Peters; E. Fox

    This paper presents a wafer-scale 77.3mm x 145mm 3-side buttable CMOS APS image sensor intended for use as one imager tile of an X-ray mammography detector. The final 232 mm x 290 mm detector comprises 2x3 butted CMOS tiles, a fiber optic plate with scintillator, and readout electronics. The CMOS imager design targets, architecture and evaluation results are presented.

  8. Development of wafer-scale cooling\\/heating thermoelectric arrays using thin-film superlattice devices

    Microsoft Academic Search

    R. Alley; K. Coonley; P. Addepalli; E. Siivola; M. Mantini; R. Venkatasubramanian

    2002-01-01

    Thin-film superlattice thermoelectric material was used to fabricate 2-inch wafer scale thermoelectric module arrays. These arrays employ a promising thermoelectric device technology that exhibits a significant enhancement in the thermoelectric device figure of merit (ZT) at 300 K, cooling\\/heating power densities in excess of 100 Watts\\/cm2, and response times significantly faster than bulk devices. To power and characterize these devices,

  9. Wafer scale interdigitated nanoelectrode devices functionalized using a MEMS-based deposition system.

    PubMed

    Martinez-Rivas, A; Carcenac, F; Saya, D; Séverac, C; Nicu, L; Vieu, C

    2012-03-16

    This paper reports on a methodology to elaborate interdigitated nanoelectrode devices (INDs) at the wafer scale, relying on a mix-and-match process which combines proximity optical lithography and electron beam lithography. An optimum exposure dose allowed fabricating nanodevices, at the wafer level, with a successful yield of 97%. The final devices are bonded onto conventional TO-8 packages. Electrical characterization in a short-circuited nanoelectrode is performed, revealing a 230 µ? cm resistivity value at 23?°C. A MEMS-based spotter made of cantilevers (called Bioplume) has been used to obtain precise functionalization of the INDs with sub-picoliter volume solutions. These INDs are the basis of multiple tunnel junction nanodevices, intended to serve as novel highly sensitive nanobiosensors. PMID:22361922

  10. 200 mm wafer-scale epitaxial transfer of single crystal Si on glass by anodic bonding of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Teh, W. H.; Trigg, Alastair; Tung, C. H.; Kumar, R.; Balasubramanian, N.; Kwong, D. L.

    2005-08-01

    We report a low-temperature (350 °C) anodic bonding followed by grind/etch-back method for a 200 mm wafer-scale epitaxial transfer of ultrathin (1.9 kÅ) single crystalline Si on Pyrex glass. Standard back-end-of-line 3 kÅ SiN/3 kÅ undoped silicon glass passivating films were used as the buffer layers between the silicon-on-insulator wafer and the glass wafer. The quality and strain-free state of the transferred transparent Si film to glass was characterized by cross-sectional transmission electron microscopy, x-ray diffraction (XRD), and high-resolution XRD. Complete removal of the bulk Si after bonding was ascertained by Auger electron spectroscopy spectra and depth profiling. Strong adhesion between the transferred film and the glass wafer was verified by standard tape adhesion tests. This process will pave the way for future generations of Si-based microelectronics including bioelectronics.

  11. Microfluidic design and fabrication of wafer-scale varifocal liquid lens

    NASA Astrophysics Data System (ADS)

    Lee, Jeong-Yub; Choi, Seung-Tae; Lee, Seung-Wan; Kim, Woonbae

    2009-08-01

    Microfluidic design and fabrication was developed for wafer-scale varifocal liquid lens which is slim less than 0.9mm. The liquid-filled varifocal lens has advanced functions such as auto macro and focusing to obtain a high quality of image. This varifocal lens is similar to human eye and it consists of main Si frame which has penetrated inner hole, upside-bonded PDMS (polydimethylsiloxane) elastomer membrane, downside-bonded glass plate and optical fluid confined by these structures. Si frame, which has a circular hole for tunable lens chamber, several holes for actuator chamber and micro-fluidic channels between chambers, is fabricated using thin Si wafer and microelectromechanical system (MEMS) processes. When optical fluid is filled the internal cavity by conventional injection, void trapping which degrades optical performance or filling impossibility happens because of high aspect ratio between lens diameter and thickness for slim liquid lens. To prevent these problems, we developed wafer-based microfabrications of seal line dispensing, accurate dropping of optical fluid, pressing & bonding process in vacuum and UV sealant curing. Afterward, electro-active polymer actuators, which push the optical fluid to change the lens shape, was attached on the PDMS membrane of liquid lens wafer and sawing process of 9.4mm*9.0mm chip size followed. Finally, the varifocal liquid lens which is slim less than 0.6mm thickness (0.9mm included actuators), tunable more than 20diopter changes of refractive power, guaranteed reliability of 300,000 repetitions and suitable for mass production, was realized.

  12. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    PubMed

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits. PMID:19086836

  13. A Wafer-Scale Etching Technique for High Aspect Ratio Implantable MEMS Structures

    PubMed Central

    Bhandari, R; Negi, S; Rieth, L.; Solzbacher, F

    2010-01-01

    Microsystem technology is well suited to batch fabricate microelectrode arrays, such as the Utah electrode array (UEA), intended for recording and stimulating neural tissue. Fabrication of the UEA is primarily based on the use of dicing and wet etching to achieve high aspect ratio (15:1) penetrating electrodes. An important step in the array fabrication is the etching of electrodes to produce needle-shape electrodes with sharp tips. Traditional etching processes are performed on a single array, and the etching conditions are not optimized. As a result, the process leads to variable geometries of electrodes within an array. Furthermore, the process is not only time consuming but also labor-intensive. This report presents a wafer-scale etching method for the UEA. The method offers several advantages, such as substantial reduction in the processing time, higher throughput and lower cost. More importantly, the method increases the geometrical uniformity from electrode to electrode within an array (1.5 ± 0.5 % non-uniformity), and from array to array within a wafer (2 ± 0.3 % non-uniformity). Also, the etching rate of silicon columns, produced by dicing, are studied as a function of temperature, etching time and stirring rate in a nitric acid rich HF-HNO3 solution. These parameters were found to be related to the etching rates over the ranges studied and more-importantly affect the uniformity of the etched silicon columns. An optimum etching condition was established to achieve uniform shape electrode arrays on wafer-scale. PMID:20706618

  14. Precision manufacturing using LIGA

    SciTech Connect

    Jackson, K.H.; Malek, C.K. [Center for X-ray Optics, Lawrence Berkeley Laboratory, Berkeley, CA 94720 (United States)] [Center for X-ray Optics, Lawrence Berkeley Laboratory, Berkeley, CA 94720 (United States); Bonivert, W.D.; Hruby, J.M.; Hachman, J.T. [Materials Synthesis Department, Sandia National Laboratory, Livermore, CA 94551 (United States)] [Materials Synthesis Department, Sandia National Laboratory, Livermore, CA 94551 (United States); Brennen, R.A.; Wiberg, D.; Hecht, M.H. [Center for Space Microelectronics Technology, Jet Propulsion Laboratory, Pasadena, CA 91109-8099 (United States)] [Center for Space Microelectronics Technology, Jet Propulsion Laboratory, Pasadena, CA 91109-8099 (United States)

    1996-09-01

    Our objective is the fabrication of small high-precision parts using LIGA, which can be used in a variety of industrial applications. LIGA is a combination of deep x-ray lithography, electroplating, and replication processes that enables the fabrication of microstructures with vertical dimensions several millimeters high, lateral dimensions in the micrometer range, and submicron tolerances. On beamline 10.3.2, at the Advanced Light Source (ALS), the Center for X-ray Optics (CXRO) has built an end station suitable for LIGA. The ALS is an excellent source of radiation for this application. The CXRO, in close collaboration with Sandia National Laboratory and the Jet Propulsion Laboratory, has developed the other essential process steps of mask making, resist development, x-ray exposure, and electroplating. This technology provides a powerful tool for mass production and miniaturization of mechanical systems into a dimensional regime not accessible by traditional manufacturing operations. We will present several applications that exploit the characteristics of the LIGA process: the fabrication of magnetic laminations for a high precision stepping motor; miniature octopole lens for advanced e-beam lithography; high-aspect-ratio x-ray collimating grids for astronomy; and microscopic tumblers for nuclear security. {copyright} {ital 1996 American Institute of Physics.}

  15. Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

    PubMed Central

    Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

    2014-01-01

    In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32?A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50?kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

  16. Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

    NASA Astrophysics Data System (ADS)

    Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

    2014-01-01

    In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices.

  17. Face-to-face transfer of wafer-scale graphene films

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene.

  18. Received 1 May 2013 | Accepted 26 Jul 2013 | Published 3 Sep 2013 Atomic layer lithography of wafer-scale

    E-print Network

    Park, Namkyoo

    of wafer-scale nanogap arrays for extreme confinement of electromagnetic waves Xiaoshu Chen1,*, Hyeong-induced electron tunnelling. This intriguing regime, however, has not been readily accessible to experimentalists a nanometre-scale gap between two metal surfaces2,4,16. Point-like nanometric junctions have been created

  19. Stress analysis of lead-free solders with under bump metallurgy in a wafer level chip scale package

    Microsoft Academic Search

    S. C. Tseng; R. S. Chen; C. C. Lio

    2006-01-01

    The wafer level chip scale assembly (WLCSP) has increasingly become popular due to its compact, wafer scale assembly. In a WLCSP assembly, the under bump metallurgy (UBM) connecting the solder joints and the chip is crucial for the assembly reliability. This study focuses on a WLCSP with 96.5Sn3.5Ag\\/95.5Sn3.8Ag0.7Cu solder joints and Ti\\/Cu\\/Ni UBM on a 2–layer microvia build-up electric board.

  20. Advancing quasi-freestanding epitaxial graphene electronics through integration of wafer scale hexagonal boron nitride dielectrics

    NASA Astrophysics Data System (ADS)

    Bresnehan, Michael S.; Hollander, Matthew J.; Marucci, Rebecca L.; LaBella, Michael; Trumbull, Kathleen A.; Cavalero, Randal; Snyder, David W.; Robinson, Joshua A.

    2012-09-01

    A key limitation to graphene based electronics is graphene's interaction with dielectric interfaces. SiO2 and various high-k gate dielectrics can introduce scattering from charged surface states, impurities, and surface optical phonons; degrading the transport properties of graphene. Hexagonal boron nitride (h-BN) exhibits an atomically smooth surface that is expected to be free of dangling bonds, leading to an interface that is relatively free of surface charge traps and adsorbed impurities. Additionally, the decreased surface optical phonon interaction from h-BN is expected to further reduce scattering. While h-BN gated graphene FETs have been demonstrated on a small scale utilizing CVD grown or exfoliated graphene, integrating quasi-freestanding epitaxial graphene (QFEG) with h-BN gate dielectrics on a wafer scale has not been explored. We present results from the first large scale CVD growth of h-BN and its subsequent transfer to a 75mm QFEG wafer. The effects of growth conditions on the thickness and quality of the h-BN film and its potential and limitations as a gate dielectric to QFEG are discussed. The introduction of charged impurities during the transfer process resulted in an average degradation in mobility of only 9%. Despite the slight degradation, we show that h-BN is highly beneficial compared to high-k dielectrics when the charged impurity concentration of QFEG is below 5x1012cm-2. Here we show improvements in mobility of >3x and intrinsic cutoff frequency of >2x compared to HfO2.

  1. High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity.

    PubMed

    Kang, Kibum; Xie, Saien; Huang, Lujie; Han, Yimo; Huang, Pinshane Y; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-04-30

    The large-scale growth of semiconducting thin films forms the basis of modern electronics and optoelectronics. A decrease in film thickness to the ultimate limit of the atomic, sub-nanometre length scale, a difficult limit for traditional semiconductors (such as Si and GaAs), would bring wide benefits for applications in ultrathin and flexible electronics, photovoltaics and display technology. For this, transition-metal dichalcogenides (TMDs), which can form stable three-atom-thick monolayers, provide ideal semiconducting materials with high electrical carrier mobility, and their large-scale growth on insulating substrates would enable the batch fabrication of atomically thin high-performance transistors and photodetectors on a technologically relevant scale without film transfer. In addition, their unique electronic band structures provide novel ways of enhancing the functionalities of such devices, including the large excitonic effect, bandgap modulation, indirect-to-direct bandgap transition, piezoelectricity and valleytronics. However, the large-scale growth of monolayer TMD films with spatial homogeneity and high electrical performance remains an unsolved challenge. Here we report the preparation of high-mobility 4-inch wafer-scale films of monolayer molybdenum disulphide (MoS2) and tungsten disulphide, grown directly on insulating SiO2 substrates, with excellent spatial homogeneity over the entire films. They are grown with a newly developed, metal-organic chemical vapour deposition technique, and show high electrical performance, including an electron mobility of 30 cm(2) V(-1) s(-1) at room temperature and 114 cm(2) V(-1) s(-1) at 90 K for MoS2, with little dependence on position or channel length. With the use of these films we successfully demonstrate the wafer-scale batch fabrication of high-performance monolayer MoS2 field-effect transistors with a 99% device yield and the multi-level fabrication of vertically stacked transistor devices for three-dimensional circuitry. Our work is a step towards the realization of atomically thin integrated circuitry. PMID:25925478

  2. Wafer scale nano-membranes supported on a silicon microsieve using thin-film transfer technology

    NASA Astrophysics Data System (ADS)

    Unnikrishnan, Sandeep; Jansen, Henri; Berenschot, Erwin; Elwenspoek, Miko

    2008-06-01

    A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independent of the thin film, which is later transferred onto it by fusion bonding, thus providing flexibility in design and processing steps. Using this thin-film transfer technique, nano-membranes down to 50 nm thickness are fabricated. The fabrication of different kinds of membranes made of inorganic, metallic and polymer materials is presented here. Apart from dense nano-membranes, perforated membranes are fabricated using this modular approach. One of the main areas of interest for such membranes is in fluidics, where the low thickness and high strength of the supported nano-membranes are a big advantage.

  3. Wafer-scale, three-dimensional helical porous thin films deposited at a glancing angle

    NASA Astrophysics Data System (ADS)

    Huang, Zhifeng; Bai, Fan

    2014-07-01

    Minimization of helices opens a door to impose novel functions derived from the dimensional shrinkage of optical, mechanical and electronic devices. Glancing angle deposition (GLAD) enables one to deposit three-dimensional helical porous thin films (HPTFs) composed of separated spiral micro/nano-columns. GLAD integrates a series of advantageous features, including one-step deposition, wafer-scale production with mono-handedness of spirals, flexible engineering of spiral materials and dimensions, and the adaption to various kinds of substrates. Herein, we briefly review the fabrication of HPTFs by GLAD, specific growth mechanisms, physical properties in structures, mechanics and chiral optics, and the emerging applications in green energy. A prospective outlook is presented to illuminate some promising developments in enantioselection, bio-dynamic analyses, wirelessly-controlled drug delivery and mass production.

  4. C-and L-band erbium-doped waveguide lasers with wafer-scale silicon nitride cavities

    E-print Network

    Reif, Rafael

    C- and L-band erbium-doped waveguide lasers with wafer-scale silicon nitride cavities Purnawirman,1 obtain output powers of up to 5 mW and show lasing at widely spaced wavelengths within both the C and L bands of the erbium gain spectrum (1536, 1561, and 1596 nm). © 2013 Optical Society of America OCIS

  5. Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

    E-print Network

    Shaver, David C.

    In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on ...

  6. Deposition of wafer-scale single-component and binary nanocrystal superlattice thin films via dip-coating.

    PubMed

    Gaulding, E Ashley; Diroll, Benjamin T; Goodwin, E D; Vrtis, Zachary J; Kagan, Cherie R; Murray, Christopher B

    2015-05-01

    Single-component and binary nanocrystal superlattices are assembled over wafer-scale areas using the dip-coating method. A series of measurements are performed to confirm superlattice assembly. This study demonstrates the versatility of dip-coating in depositing a diverse set of nanocrystal materials and superlattice structures, while combining large-area deposition with nanoscale control. PMID:25820834

  7. High speed wafer scale bulge testing for the determination of thin film mechanical properties

    NASA Astrophysics Data System (ADS)

    Orthner, M. P.; Rieth, L. W.; Solzbacher, F.

    2010-05-01

    A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50-150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 ?m in width comprised of 720±10 nm thick low pressure chemical vapor deposited silicon nitride with ˜20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to ˜8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (˜350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young's modulus was estimated for the films assuming a Poisson's ratio of v =0.25. Calculations to determine Young's modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young's modulus for the smaller membranes. The deflection measurements of three 1200×1200 ?m2 Si3N4-x membranes were taken at increased pressures (>25 kPa) to increase nonlinearity and better determine Young's modulus. This pressure-deflection data were fit to an analytical solution and Young's modulus estimated to be 257±3 GPa, close to those previously reported in literature.

  8. Wafer-Scale Monolayer Films of Semiconducting Metal Dichalcogenides for High-Performance Electronics

    NASA Astrophysics Data System (ADS)

    Xie, Saien; Kang, Kibum; Huang, Lujie; Han, Yimo; Huang, Pinshane; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-03-01

    Two-dimensional semiconducting transition metal dichalcogenides (TMDs) have shown their potential in electronics, optoelectronic and valleytronis. However, large-scale growth methods reported to date have only produced materials with limited structural and electrical uniformity, hindering further technological applications. Here we present a 4-inch scale growth of continuous monolayer molybdenum disulfide (MoS2) and tungsten disulfide (WS2) films that show excellent structural and electrical uniformity over the entire wafer using metal-organic chemical vapor deposition. The resulting monolayer films show high mobility of 30 cm2/Vs at room temperature, as well as the phonon-limited transport for MoS2, regardless of the channel length and device location. They allow for the batch fabrication of monolayer MoS2 field effect transistors with a 99% yield, which display spatially-uniform n-type transistor operation with a high on/off ratio. We further demonstrate the multi-level growth and fabrication of vertically-stacked monolayer MoS2 films and devices, which could enable the development of novel three-dimensional circuitry and device integration.

  9. Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy.

    PubMed

    Wang, Dongxing; Zhu, Wenqi; Best, Michael D; Camden, Jon P; Crozier, Kenneth B

    2013-01-01

    The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures ("metasurfaces") can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

  10. Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy

    NASA Astrophysics Data System (ADS)

    Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

    2013-10-01

    The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (``metasurfaces'') can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent.

  11. Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy

    PubMed Central

    Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

    2013-01-01

    The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (“metasurfaces”) can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

  12. Atomic layer lithography of wafer-scale nanogap arrays for extreme confinement of electromagnetic waves

    NASA Astrophysics Data System (ADS)

    Chen, Xiaoshu; Park, Hyeong-Ryeol; Pelton, Matthew; Piao, Xianji; Lindquist, Nathan C.; Im, Hyungsoon; Kim, Yun Jung; Ahn, Jae Sung; Ahn, Kwang Jun; Park, Namkyoo; Kim, Dai-Sik; Oh, Sang-Hyun

    2013-09-01

    Squeezing light through nanometre-wide gaps in metals can lead to extreme field enhancements, nonlocal electromagnetic effects and light-induced electron tunnelling. This intriguing regime, however, has not been readily accessible to experimentalists because of the lack of reliable technology to fabricate uniform nanogaps with atomic-scale resolution and high throughput. Here we introduce a new patterning technology based on atomic layer deposition and simple adhesive-tape-based planarization. Using this method, we create vertically oriented gaps in opaque metal films along the entire contour of a millimetre-sized pattern, with gap widths as narrow as 9.9?Å, and pack 150,000 such devices on a 4-inch wafer. Electromagnetic waves pass exclusively through the nanogaps, enabling background-free transmission measurements. We observe resonant transmission of near-infrared waves through 1.1-nm-wide gaps (?/1,295) and measure an effective refractive index of 17.8. We also observe resonant transmission of millimetre waves through 1.1-nm-wide gaps (?/4,000,000) and infer an unprecedented field enhancement factor of 25,000.

  13. High throughput ultralong (20 cm) nanowire fabrication using a wafer-scale nanograting template.

    PubMed

    Yeon, Jeongho; Lee, Young Jae; Yoo, Dong Eun; Yoo, Kyoung Jong; Kim, Jin Su; Lee, Jun; Lee, Jeong Oen; Choi, Seon-Jin; Yoon, Gun-Wook; Lee, Dong Wook; Lee, Gi Seong; Hwang, Hae Chul; Yoon, Jun-Bo

    2013-09-11

    Nanowires are being actively explored as promising nanostructured materials for high performance flexible electronics, biochemical sensors, photonic applications, solar cells, and secondary batteries. In particular, ultralong (centimeter-long) nanowires are highly attractive from the perspective of electronic performance, device throughput (or productivity), and the possibility of novel applications. However, most previous works on ultralong nanowires have issues related to limited length, productivity, difficult alignment, and deploying onto the planar substrate complying with well-matured device fabrication technologies. Here, we demonstrate a highly ordered ultralong (up to 20 cm) nanowire array, with a diameter of 50 nm (aspect ratio of up to 4,000,000:1), in an unprecedented large (8 in.) scale (2,000,000 strands on a wafer). We first devised a perfectly connected ultralong nanograting master template on the whole area of an 8 in. substrate using a top-down approach, with a density equivalent to that achieved with e-beam lithography (100 nm). Using this large-area, ultralong, high-density nanograting template, we developed a fast and effective method for fabricating up to 20 cm long nanowire arrays on a plastic substrate, composed of metal, dielectric, oxide, and ferroelectric materials. As a suggestion of practical application, a prototype of a large-area aluminum wire grid polarizer was demonstrated. PMID:23899099

  14. A wafer-scale backplane-assisted resonating nanoantenna array SERS device created by tunable thermal dewetting nanofabrication

    NASA Astrophysics Data System (ADS)

    Chang, Te-Wei; Ranjan Gartia, Manas; Seo, Sujin; Hsiao, Austin; Logan Liu, Gang

    2014-04-01

    A tunable lithography-less nanofabrication process using a metal thin-film thermal dewetting technique has been developed to fabricate wafer-scale and uniform plasmonic substrates at low cost for optimal performance in surface enhanced Raman scattering (SERS) applications. The relationship between the tunable parameters of this process and the corresponding optical and plasmonic characteristic is investigated both experimentally and theoretically to understand the deterministic design of an optimal SERS device with a three-dimensional plasmonic nanoantenna structure. The enhancement of SERS using various nanoplasmonic particle sizes, structure lengths, lateral hot spot spacings and resonating effects are examined and demonstrated. We achieve a uniform optimal enhancement factor of 1.38 × 108 on a 4 in wafer-scale SERS substrate with a backplane-assisted resonating nanoantenna array design. Sensitive environmental nitrate sensing, vitamin detection and oligonucleotide identification are demonstrated on the high-performance SERS device.

  15. Electronic and optoelectronic devices based on chirality-enriched wafer-scale single-wall carbon nanotube thin films

    NASA Astrophysics Data System (ADS)

    Gao, Weilu; He, Xiaowei; Xie, Lijuan; Zhang, Qi; Haroz, Erik; Doorn, Stephen K.; Kono, Junichiro

    2015-03-01

    The unique and rich material properties of single-wall carbon nanotubes (SWCNTs) make them attractive for nano-electronic and optoelectronic applications. Slight changes in tube diameter and wrapping angle, defined by the chirality indices (n, m), can dramatically modify the bandstructure, which can be utilized for designing devices with tailored properties. However, it remains to be a challenge to fabricate macroscopic, single-chirality devices. Here, we introduce a simple way of producing chirality-enriched wafer-scale SWCNT films by combining recently developed solution-based polymer-modified sorting method and vacuum filtration. The produced thin films can be easily transferred onto any substrate to have a CMOS compatible wafer. We fabricated a transistor of (6,5)-enriched SWCNTs with an on/off ratio >103. Large-scale photothermoelectric-effect-based and photovoltaic-effect-based photodetectors made of (6,6)- and (6,5)-enriched films, respectively, will also be discussed.

  16. Wafer-scale coplanar waveguide slot-coupled Ka-band patch antenna for electronic scanning array of a future satellite communications system

    Microsoft Academic Search

    Steven D. Keller; Steven J. Weiss; Ronald G. Polcawich; Daniel C. Judy

    2008-01-01

    This paper discussed about the successful simulated and measured data of the wafer-scale CPW slot-coupled Ka-band patch antenna presented above strongly advocate its candidacy for future integration with a MEMS-switched control board. Since it is a single-layer embodiment of the slot-coupling feed method, the total system weight is minimized and the complexity of the wafer-scale fabrication process is reduced. This,

  17. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon, E-mail: dadembyora@mosfet.t.u-tokyo.ac.jp, E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); JST-CREST, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Yokoyama, Masafumi; Nakane, Ryosho [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Li, Jian; Kao, Yung-Chung [IntelliEPI, Inc., 1250 E. Collins Blvd., Richardson, Texas 75081 (United States)

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300?mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700?cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  18. Wafer-scale arrayed p-n junctions based on few-layer epitaxial GaTe

    NASA Astrophysics Data System (ADS)

    Yuan, Xiang; Tang, Lei; Hu, Weida; Xiu, Faxian

    2015-03-01

    Two dimensional (2D) materials have showed appealing applications in electronics and optoelectronics. Gapless graphene presents ultra-broadband and fast photoresponse while the 2D semiconducting MoS2 and GaTe exhibit highly sensitive and tunable responsivity to the visible light. However, the device yield and its repeatability call for a further improvement of 2D materials to render large-scale uniformity. Here we report a layer-by-layer growth of the wafer-scale GaTe by molecular beam epitaxy. To develop the arrayed p-n junctions, the few-layer GaTe was grew on three-inch Si wafers. The resultant diodes reveal good rectifying characteristics and photoresponse with maximum photodetection responsivity of 2.74 A/W and photovoltaic external quantum efficiency up to 62%. The photocurrent reaches saturation very fast within 22 ?s and shows no sign of device degradation after 1.37 million cycles of operation. Most strikingly, such high performance has been achieved across the entire wafer, making the volume production of devices accessible. Finally, several photo-images was acquired by using these photodiodes with a reasonable contrast and resolution, demonstrating for the first time the potential for these 2D technology coming into the real life.

  19. A MICRO STENCILING PROCESS FOR WAFER SCALE METALLIZATION OF PLASTIC SUBSTRATES

    E-print Network

    :1 to 15:1 were fabricated using ICP etching of silicon. The stenciling process was demonstrated, the wafer was etched using the ICP Bosch etching process. SU-8 was found to be resilient in the Bosch was used to check the adhesion of the metals to the various plastics. #12;Results Using ICP etching we were

  20. LIGA for Boomerang

    NASA Astrophysics Data System (ADS)

    Lawes, Ronald A.; Arthur, Graham G.

    2004-04-01

    Boomerang is a 3GeV synchrotron radiation accelerator, currently being constructed in the State of Victoria, Australia. The outline design of two beamlines, suitable for the fabrication of MEMS devices using the LIGA process, is presented, along with an estimate of the exposure doses throughout the resist. The most commonly used resist is PMMA, which requires a minimum dose of about 4500 J/cm3 for accurate microstructure definition. Exposure with such a dose, in resist thicknesses of several hundred microns, can take hours. Fortunately, SU-8 resist is becoming more widely used as the minimum dosage required is about 35 J/cm3, leading to exposure times of only a few minutes. Although Boomerang will shorten exposure times due to its higher irradiance at the substrate, the full benefits may not be realizable due to excessive resist heating. Heating effects have been simulated and suggest that helium cooling will be essential if the glass transition temperature of the resist (100°C for PMMA, 50°C for SU-8) and thermal distortion of the mask are to be avoided. The parameters chosen in this study of the future performance of Boomerang have been inserted into a cost model. The model shows that Boomerang exposure can become competitive with other exposure methods, particularly where large quantities of devices with deep structures are required.

  1. Activities of LIGA and Nano LIGA Technologies at BSRF

    Microsoft Academic Search

    F. Yi; J. Zhang; C. Xie; D. Wang; D. Chen

    2006-01-01

    Beijing Synchrotron Radiation Facility (BSRF ) is a partly dedicated synchrotron radiation ( SR) source operated in either parasitic or dedicated mode. LIGA research at BSRF started from 1993 and focused in the first two steps of deep X-ray lithography and electroplating. Scanning exposure chamber of deep X-ray lithography was first built in 1996 on a 3W1 wiggler beamline with

  2. 200 mm wafer-scale substrate transfer of 0.13 ?m Cu/low-k (Black Diamond™) dual-damascene interconnection to glass substrates

    NASA Astrophysics Data System (ADS)

    Teh, W. H.; Kumar, R.; Kwong, D. L.

    2005-07-01

    We report a low-temperature (350 °C) pulsed-voltage anodic bonding followed by grind/etch-back method for 200 mm wafer-scale substrate transfer of 0.13?mCu/low-k (Black Diamond™) dual-damascene interconnection to glass substrates. Standard back-end-of-line (BEOL) 3kÅSiN/3kÅ undoped Si glass passivating films were used as buffer layers between donor wafer and glass wafer to facilitate the bonding. We demonstrate removal of the silicon bulk layer to leave behind a transparent (˜1.25?m thick) 0.13?m BEOL circuit on a 1-mm-thick glass wafer. The quality of the mechanical and electrical integrity of the deep submicron BEOL circuit is confirmed by focused ion beam-scanning electron microscopy microscopy and I-V characterization on via chain test structures. This technique has potential applications for bioelectronics and optoelectronics integration schemes.

  3. Fabrication method for chip-scale-vacuum-packages based on a chip-to-wafer-process

    NASA Astrophysics Data System (ADS)

    Bauer, J.; Weiler, D.; Ruß, M.; Heß, J.; Yang, P.; Voß, J.; Arnold, N.,; Vogt, H.

    2010-10-01

    This paper introduces a simple vacuum packaging method which is based on a Chip-to-Wafer process. The MEMS-device is provided with an electroplated solder frame. A Si-lid with the same solder frame is mounted on each die of the wafer using a flip chip process. The same materials for lid and substrate are used in order to reduce the mechanical stress due to the same thermal coefficients of expansion. The resulting cavity between die and lid can be evacuated and hermetically sealed with an eutectic soldering process. The feasibility of the method is demonstrated with an infrared focal plane array (IR-FPA). In this case, the Si-lid acts as an optical window and contains an anti reflective layer for the 8-14 ?m wavelength area on both sides. The long-term vacuum stability is supported by a getter film inside the package. This method simplifies the sawing process and has the additional cost benefit that it is possible to package only known good dies.

  4. Wafer-scale synthesis of thickness-controllable MoS2 films via solution-processing using a dimethylformamide/n-butylamine/2-aminoethanol solvent system.

    PubMed

    Yang, Jaehyun; Gu, Yeahyun; Lee, Eunha; Lee, Hyangsook; Park, Sang Han; Cho, Mann-Ho; Kim, Yong Ho; Kim, Yong-Hoon; Kim, Hyoungsub

    2015-05-14

    The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates. PMID:25946575

  5. Miniature Inchworm Actuators Fabricated by Use of LIGA

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok

    2003-01-01

    Miniature inchworm actuators that would have relatively simple designs have been proposed for applications in which there are requirements for displacements of the order of microns or tens of microns and for the ability to hold their positions when electric power is not applied. The proposed actuators would be members of the class of microelectromechanical systems (MEMS), but would be designed and fabricated following an approach that is somewhat unusual for MEMS. Like other MEMS actuators, the proposed inchworm actuators could utilize thermoplastic, bimetallic, shape-memory-alloy, or piezoelectric actuation principles. The figure depicts a piezoelectric inchworm actuator according to the proposal. As in other inchworm actuators, linear motion of an extensible member would be achieved by lengthening and shortening the extensible member in synchronism with alternately clamping and releasing one and then the other end of the member. In this case, the moving member would be the middle one; the member would be piezoelectric and would be shortened by applying a voltage to it. The two outer members would also be piezoelectric; the release of the clamps on the upper or lower end would be achieved by applying a voltage to the electrodes on the upper or lower ends, respectively, of these members. Usually, MEMS actuators cannot be fabricated directly on the side walls of silicon wafers, yet the geometry of this actuator necessitates such fabrication. The solution, according to the proposal, would be to use the microfabrication technique known by the German acronym LIGA - "lithographie, galvanoformung, abformung," which means lithography, electroforming, molding. LIGA involves x-ray lithography of a polymer film followed by selective removal of material to form a three-dimensional pattern from which a mold is made. Among the advantages of LIGA for this purpose are that it is applicable to a broad range of materials, can be used to implement a variety of designs, including those of structures >1 mm high, affords submicron precision, and is amenable to mass production at relatively low unit cost. Fabrication of the proposed actuators would involve some technological risks - in particular, in the integration of electrode connection lines and placement of actuator elements. It will also be necessary to perform an intensive study of the feasibility of growing piezoelectric crystals onto LIGA molds.

  6. Integration of hexagonal boron nitride with quasi-freestanding epitaxial graphene: toward wafer-scale, high-performance devices.

    PubMed

    Bresnehan, Michael S; Hollander, Matthew J; Wetherington, Maxwell; LaBella, Michael; Trumbull, Kathleen A; Cavalero, Randal; Snyder, David W; Robinson, Joshua A

    2012-06-26

    Hexagonal boron nitride (h-BN) is a promising dielectric material for graphene-based electronic devices. Here we investigate the potential of h-BN gate dielectrics, grown by chemical vapor deposition (CVD), for integration with quasi-freestanding epitaxial graphene (QFEG). We discuss the large scale growth of h-BN on copper foil via a catalytic thermal CVD process and the subsequent transfer of h-BN to a 75 mm QFEG wafer. X-ray photoelectron spectroscopy (XPS) measurements confirm the absence of h-BN/graphitic domains and indicate that the film is chemically stable throughout the transfer process, while Raman spectroscopy indicates a 42% relaxation of compressive stress following removal of the copper substrate and subsequent transfer of h-BN to QFEG. Despite stress-induced wrinkling observed in the films, Hall effect measurements show little degradation (<10%) in carrier mobility for h-BN coated QFEG. Temperature dependent Hall measurements indicate little contribution from remote surface optical phonon scattering and suggest that, compared to HfO(2) based dielectrics, h-BN can be an excellent material for preserving electrical transport properties. Graphene transistors utilizing h-BN gates exhibit peak intrinsic cutoff frequencies >30 GHz (2.4× that of HfO(2)-based devices). PMID:22545808

  7. Wafer-scale synthesis of thickness-controllable MoS2 films via solution-processing using a dimethylformamide/n-butylamine/2-aminoethanol solvent system

    NASA Astrophysics Data System (ADS)

    Yang, Jaehyun; Gu, Yeahyun; Lee, Eunha; Lee, Hyangsook; Park, Sang Han; Cho, Mann-Ho; Kim, Yong Ho; Kim, Yong-Hoon; Kim, Hyoungsub

    2015-05-01

    The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates.The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates. Electronic supplementary information (ESI) available: Optical microscopy image of the spin-coated film, thermogravimetric data of the spin-coating solution, Raman spectra after first- and second-annealing, and AFM images of selected MoS2 films. See DOI: 10.1039/c5nr01486g

  8. Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

    PubMed

    Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

    2014-11-25

    Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers. PMID:25365786

  9. Epitaxial (100) iridium on A-plane sapphire: A system for wafer-scale diamond heteroepitaxy

    NASA Astrophysics Data System (ADS)

    Dai, Z.; Bednarski-Meinke, C.; Loloee, R.; Golding, B.

    2003-06-01

    Large-scale heteroepitaxial growth of diamond depends critically on the development of a suitable lattice-matched buffer layer and substrate system. Epitaxial (100) iridium films have been grown on terraced, vicinal a-plane (112¯0) ?-Al2O3 (sapphire) by electron-beam evaporation. The epitaxial relationship, Ir(100)//Al2O3(112¯0) with Ir[011]//Al2O3[11¯00], was determined by x-ray diffraction and electron backscattering diffraction analysis. For a 300-nm thickness of Ir, a (200) rocking curve yielded a linewidth of 0.21°, and the film exhibited a macrostepped surface with low pinhole density. This Ir/sapphire system provides a basis for large-area growth of (100) heteroepitaxial diamond.

  10. 1144 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 10, OCTOBER 2007 Wafer-Level Modular Testing of Core-Based SoCs

    E-print Network

    Chakrabarty, Krishnendu

    2007 Wafer-Level Modular Testing of Core-Based SoCs Sudarshan Bahukudumbi, Student Member, IEEECs. To reduce packaging cost and the test cost for pack- aged chips, wafer-level testing (wafer sort) is used constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can

  11. Silicon Wafer Epitaxy

    NSDL National Science Digital Library

    This Quicktime animation shows an optional process for creating silicon epitaxial wafers. The animations shows a trichlorosilane gas being injected which creates a monocrystaline film atop the preexisting wafer. This is the seventh animation in a series of how silicon wafers are created. The previous animation showing silicon wafer polishing can be seen here.The next and final animation in this sequence about silicon wafer laser inspection can be seen here.

  12. Large-area, wafer-scale epitaxial growth of germanium on silicon and integration of high-performance transistors

    NASA Astrophysics Data System (ADS)

    Ghosh, Swapnadip

    Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the ˜105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress simulation shows that the oval air gaps around the SiO2 template can reduce the thermal stress by 50% and help reduce the DD. We have then compared the structural and electrical characteristics of n-type Ge films with its p-type counter parts. In n-type Ge, the DD decreases from ˜109cm-2 near the Ge-Si interface to ˜105 cm-2 at the film surface. In contrast, we observe 5x107 cm-2 TDD at the film surface in p-type Ge. The full width at half-maximum for our n-type Ge(004) XRD peak is ~70% narrower than that of p-type Ge. As a stringent test of the dislocation reduction, we have also fabricated and characterized high-carrier-mobility MOSFETs on GoS substrates. We also report p- and n-MOSFETs with microeff of 401 and 940 cm2/V-s and a subthreshold slope of 100 and 200 mV/decade, respectively. These effective mobilities show an exceptional 82 and 30% improvement over that of conventional Si channel MOSFETs. We also investigate the optical quality of ultra-low DD GoS film by measuring photoluminescence (PL). The n-type Ge PL main peak shows pronounced tensile-strain (x0.8%) than that of p-type which is an indicator of direct BG shrinking at the \\Gcy band-edge. Going beyond epitaxial engineering and device fabrication, we have also recently demonstrated a scalable path to create a 2D array of Ge quantum dots (QDs) on responsive SiGe substrates based on elastic mechanical deformation and subsequent SiGe compositional redistribution, coupled with MBE growth. For large-scale manufacturing of single-electron transistors, we have also demonstrated that a spatially structured elastic compressive stress to the SiGe substrate with thermally annealing leads to a compositional redistribution of Si and Ge in the near-surface region of SiGe substrates, forming a 2D array of Ge-depleted nanoscale regions. Based on these latest findings, we have also begun to chart a future direction for my research group, where one can explore new advanced device architectures, such as Si-compatible, optically actuated, Ge-quantum dot-based field effect transistors.

  13. Optical measurement of LIGA milliengine performance

    SciTech Connect

    Dickey, F.M.; Holswade, S.C.; Christenson, T.R.; Garcia, E.J.; Polosky, M.A.

    1997-12-31

    Understanding the parameters that affect the performance of milliscale and microscale actuators is essential to the development of optimized designs and fabrication processes, as well as the qualification of devices for commercial applications. This paper discusses the development of optical techniques for motion measurements of LIGA fabricated milliengines. LIGA processing permits the fabrication of precision millimeter-sized machine elements that cannot be fabricated by conventional miniature machining techniques because of their small feature sizes. In addition, tolerances of 1 part in 10{sup 3} to 10{sup 4} may be maintained in millimeter sized components with this processing technique. Optical techniques offer a convenient means for measuring long term statistical performance data and transient responses needed to optimize designs and manufacturing techniques. Optical techniques can also be used to provide feedback signals needed for control and sensing of the state of the machine. Optical probe concepts and experimental data obtained using a milliengine developed at Sandia National Laboratories are presented.

  14. Wafer-scale synthesis of defect-negligible monolayer graphene at reduced temperature on hydrogen-rich evaporated (111) copper films

    NASA Astrophysics Data System (ADS)

    Tao, Li; Holt, Milo; Chou, Harry; Lee, Jongho; Ruoff, Rodney S.; Akinwande, Deji

    2012-02-01

    In contrast to commercially available copper foils, evaporated copper film on wafer scale supporting substrates holds great promise in chemical vapor deposition (CVD) of graphene for direct integration into device manufacturing processes. Monolayer graphene with negligible defects (<5%) was synthesized on evaporated copper films at temperatures < 900 ^oC using hydrogen-free methane precursor that has not been previously reported. In this work, high-quality monolayer graphene obtained on evaporated copper film was likely enabled by the distinct properties of hydrogen-rich (111) preferred crystal orientation as indicated by X-ray diffraction (XRD) and electron back scattering diffraction (EBSD). The distinct difference in the crystal orientation of copper films versus foils resulted in dissimilar interplay with the precursor gas, as confirmed by time-of-flight secondary ion mass spectroscopy (TOF-SIMS). This study demonstrates experimental evidence for differences in the growth dynamics of CVD graphene on copper film versus conventional foils.

  15. Laser LIGA for serpentine Ni microstructures

    Microsoft Academic Search

    Hengyi Jin; Erol C. Harvey; Jason P. Hayes; Muralidhar K. Ghantasala; Andrew J. Dowling; Matthew Solomon; Sam T. Davies

    2001-01-01

    A pulsed excimer laser (248 nm) based LIGA-like process is presented for the fabrication of Ni serpentine microstructures, such as those that might be used for micro-heaters. The structures were produced on both Cu (60 micrometers ) clad PCB and on Cu\\/Ti (up to 4 micrometers \\/15 nm) sputtered Si (100) substrates. The substrates were coated with a Laminar dry

  16. Multiwire slurry wafering demonstrations

    Microsoft Academic Search

    C. P. Chen

    1978-01-01

    Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m\\/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of

  17. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 ?m SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  18. Scheduling semiconductor wafer fabrication

    Microsoft Academic Search

    LAWRENCE M. WEIN

    1988-01-01

    The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer

  19. Silicon Wafer Polishing

    NSDL National Science Digital Library

    This Quicktime animation demostrates the final polishing and cleaning processes required for creating semiconductor devices and integrated circuits. This animation is the sixth in a series of how silicon wafers are created. The previous animation showing silicon wafer lapping can be seen here. The next animation in this sequence about the optional silicon wafer epitaxy process can be seen here.

  20. Silicon Wafer Lapping

    NSDL National Science Digital Library

    This Quicktime animation shows how the machining process of "lapping" removes controlled amounts of silicon from a wafer in order to ensure flatness of the silicon wafer. This process removes particles and improves the quality of the wafer after they are cut. This animation is the fifth in a series of how silicon wafers are created.The previous animation showing silicon ingot edge profiling can be seen here.The next animation in this sequence about silicon wafer polishing can be seen here.

  1. High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth.

    PubMed

    Miao, Xin; Chabak, Kelson; Zhang, Chen; K Mohseni, Parsian; Walker, Dennis; Li, Xiuling

    2015-05-13

    Wafer-scale defect-free planar III-V nanowire (NW) arrays with ?100% yield and precisely defined positions are realized via a patterned vapor-liquid-solid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 10(4), 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 × 1.5 cm(2) chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics. PMID:25494481

  2. Semiconductor Wafer Bonding

    Microsoft Academic Search

    U. Gosele; Q.-Y. Tong

    1998-01-01

    When mirror-polished, flat, and clean wafers of almost any material are brought into contact at room temperature, they are locally attracted to each other by van der Waals forces and adhere or bond. This phenomenon is referred to as wafer bonding. The most prominent applications of wafer bonding are silicon-on-insulator (SOI) devices, silicon-based sensors and actuators, as well as optical

  3. Micro-grippers for assembly of LIGA parts

    SciTech Connect

    Feddema, J.; Polosky, M.; Christenson, T.; Spletzer, B.; Simon, R.

    1997-12-31

    This paper describes ongoing testing of two microgrippers for assembly of LIGA (Lithographie Galvanoformung Abformung) parts. The goal is to place 100 micron outside diameter (OD) LIGA gears with a 50 micron inner diameter hole onto pins ranging from 35 to 49 microns. The first micro gripper is a vacuum gripper made of a 100 micron OD stainless steel tube. The second micro gripper is a set of tweezers fabricated using the LIGA process. Nickel, Permalloy, and copper materials are tested. The tweezers are actuated by a collet mechanism which is closed by a DC linear motor.

  4. Modeling and analysis of 96.5Sn3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board

    Microsoft Academic Search

    John H. Lau; S.-W. R. Lee

    2002-01-01

    In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive

  5. Cantilevered multilevel LIGA devices and methods

    DOEpatents

    Morales, Alfredo Martin (Pleasanton, CA); Domeier, Linda A. (Danville, CA)

    2002-01-01

    In the formation of multilevel LIGA microstructures, a preformed sheet of photoresist material, such as polymethylmethacrylate (PMMA) is patterned by exposure through a mask to radiation, such as X-rays, and developed using a developer to remove the exposed photoresist material. A first microstructure is then formed by electroplating metal into the areas from which the photoresist has been removed. Additional levels of microstructure are added to the initial microstructure by covering the first microstructure with a conductive polymer, machining the conductive polymer layer to reveal the surface of the first microstructure, sealing the conductive polymer and surface of the first microstructure with a metal layer, and then forming the second level of structure on top of the first level structure. In such a manner, multiple layers of microstructure can be built up to allow complex cantilevered microstructures to be formed.

  6. Miniature Scroll Pumps Fabricated by LIGA

    NASA Technical Reports Server (NTRS)

    Wiberg, Dean; Shcheglov, Kirill; White, Victor; Bae, Sam

    2009-01-01

    Miniature scroll pumps have been proposed as roughing pumps (low - vacuum pumps) for miniature scientific instruments (e.g., portable mass spectrometers and gas analyzers) that depend on vacuum. The larger scroll pumps used as roughing pumps in some older vacuum systems are fabricated by conventional machining. Typically, such an older scroll pump includes (1) an electric motor with an eccentric shaft to generate orbital motion of a scroll and (2) conventional bearings to restrict the orbital motion to a circle. The proposed miniature scroll pumps would differ from the prior, larger ones in both design and fabrication. A miniature scroll pump would include two scrolls: one mounted on a stationary baseplate and one on a flexure stage (see figure). An electromagnetic actuator in the form of two pairs of voice coils in a push-pull configuration would make the flexure stage move in the desired circular orbit. The capacitance between the scrolls would be monitored to provide position (gap) feedback to a control system that would adjust the drive signals applied to the voice coils to maintain the circular orbit as needed for precise sealing of the scrolls. To minimize power consumption and maximize precision of control, the flexure stage would be driven at the frequency of its mechanical resonance. The miniaturization of these pumps would entail both operational and manufacturing tolerances of <1 m. Such tight tolerances cannot be achieved easily by conventional machining of high-aspect-ratio structures like those of scroll-pump components. In addition, the vibrations of conventional motors and ball bearings exceed these tight tolerances by an order of magnitude. Therefore, the proposed pumps would be fabricated by the microfabrication method known by the German acronym LIGA ( lithographie, galvanoformung, abformung, which means lithography, electroforming, molding) because LIGA has been shown to be capable of providing the required tolerances at large aspect ratios.

  7. Dopant Dose Metrology for Ultra-Shallow Implanted Wafers using Electron-Induced X-Ray Spectrometry at Pattern-Size Scale

    SciTech Connect

    Staub, Pierre-F.; Hombourger, Chrystel [CAMECA, 103 Bd. St-Denis, 92403, Courbevoie cedex (France)

    2005-09-09

    In the past few years a new technique has been developed and optimized at Cameca to achieve the precise dose monitoring of ultra-shallow implants thanks to Low Energy X-Ray Emission Spectrometry. An instrument is now proposed, called Shallow Probe, for both Factory and Laboratory applications, allying high throughput (a few wafers per hour for full 300mm-200mm wafer mapping), high precision and stability (sub 1%) as well as high spatial resolution to address cheap-size measurements (<60{mu}m)

  8. Dopant Dose Metrology for Ultra-Shallow Implanted Wafers using Electron-Induced X-Ray Spectrometry at Pattern-Size Scale

    NASA Astrophysics Data System (ADS)

    Staub, Pierre-F.; Hombourger, Chrystel

    2005-09-01

    In the past few years a new technique has been developed and optimized at Cameca to achieve the precise dose monitoring of ultra-shallow implants thanks to Low Energy X-Ray Emission Spectrometry. An instrument is now proposed, called Shallow Probe, for both Factory and Laboratory applications, allying high throughput (a few wafers per hour for full 300mm-200mm wafer mapping), high precision and stability (sub 1%) as well as high spatial resolution to address cheap-size measurements (<60?m).

  9. Wafer characteristics via reflectometry

    SciTech Connect

    Sopori, Bhushan L. (Denver, CO)

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  10. From Wafer to Package

    NSDL National Science Digital Library

    This website includes an animation of finished wafer to packaged integrated Circuits. Objective: Describe the wafer to packaged device process steps. This simulation is from Module 075 of the Process & Equipment III Cluster of the MATEC Module Library (MML). You will find the animation under the heading "Process & Equipment III." To view other clusters or for more information about the MML visit http://matec.org/ps/library3/process_I.shtmlKey

  11. Wafer scale micromachine assembly method

    DOEpatents

    Christenson, Todd R. (Albuquerque, NM)

    2001-01-01

    A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.

  12. Stable wafer-carrier system

    SciTech Connect

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  13. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam [1366 Technologies] [1366 Technologies

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

  14. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  15. Recent Developments in Microsystems Fabricated by the Liga-Technique

    NASA Technical Reports Server (NTRS)

    Schulz, J.; Bade, K.; El-Kholi, A.; Hein, H.; Mohr, J.

    1995-01-01

    As an example of microsystems fabricated by the LIGA-technique (x-ray lithography, electroplating and molding), three systems are described and characterized: a triaxial acceleration sensor system, a micro-optical switch, and a microsystem for the analysis of pollutants. The fabrication technologies are reviewed with respect to the key components of the three systems: an acceleration sensor, and electrostatic actuator, and a spectrometer made by the LIGA-technique. Aa micro-pump and micro-valve made by using micromachined tools for molding and optical fiber imaging are made possible by combining LIGA and anisotropic etching of silicon in a batch process. These examples show that the combination of technologies and components is the key to complex microsystems. The design of such microsystems will be facilitated is standardized interfaces are available.

  16. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  17. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  18. Wafer Nanotopography Effects on CMP: Experimental Validation of Modeling Methods , Duane S. Boning1

    E-print Network

    Boning, Duane S.

    Wafer Nanotopography Effects on CMP: Experimental Validation of Modeling Methods Brian Lee1 , Duane length scale on unpatterned silicon wafers. Chemical mechanical polishing (CMP) of de- posited or grown films (e.g., oxide or nitride) on such wafers can generate undesirable film thin- ning which can

  19. Dual-Wavelength Vertical-Cavity Surface-Emitting Laser Arrays Fabricated by Nonplanar Wafer Bonding

    E-print Network

    Bowers, John

    Dual-Wavelength Vertical-Cavity Surface-Emitting Laser Arrays Fabricated by Nonplanar Wafer Bonding active regions integrated on a common mirror by nonplanar wafer bonding. WDM systems and next and electrical functionality. Fabricating these highly versatile chips requires wafer-scale integration

  20. Wafer-to-wafer bonding for microstructure formation

    Microsoft Academic Search

    MARTIN A. SCHMIDT

    1998-01-01

    Wafer-to-wafer bonding processes for microstructure fabrication are categorized and described. These processes have an impact in packaging and structure design. Processes are categorized into direct bonds, anodic bonds, and bonds with intermediate layers. Representative devices using wafer-to-wafer bonding are presented. Processes and methods for characterization of a range of bonding methods are discussed. Opportunities for continued development are outlined

  1. Etching Of Semiconductor Wafer Edges

    DOEpatents

    Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

    2003-12-09

    A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

  2. Medical Device Wafer Singulation

    Microsoft Academic Search

    A. Teng; F. Wilhelmsen

    2007-01-01

    Singulation can be the most damaging step in electronic manufacturing where individual dice are freed from a brittle silicon wafer. So much torque and force is applied to the silicon during this process that if precautionary steps are not taken, the freed die may exhibit low strength due to chipping damage. For medical devices, this is particularly a problem because

  3. Fine grinding of silicon wafers

    Microsoft Academic Search

    Z. J Pei; Alan Strasbaugh

    2001-01-01

    Silicon wafers are used for the production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. As one of such processes, surface grinding of silicon wafers has attracted attention among various investigators and a limited number of articles can be found in the literature. However, no published articles are available regarding fine grinding of

  4. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  5. Prediction of etching-shape anomaly due to distortion of ion sheath around a large-scale three-dimensional structure by means of on-wafer monitoring technique and computer simulation

    NASA Astrophysics Data System (ADS)

    Kubota, Tomohiro; Ohtake, Hiroto; Araki, Ryosuke; Yanagisawa, Yuuki; Iwasaki, Takuya; Ono, Kohei; Miwa, Kazuhiro; Samukawa, Seiji

    2013-10-01

    A system for predicting distortion of a profile during plasma etching was developed. The system consists of a combination of measurement and simulation. An ‘on-wafer sheath-shape sensor’ for measuring the plasma-sheath parameters (sheath potential and thickness) on the stage of the plasma etcher was developed. The sensor has numerous small electrodes for measuring sheath potential and saturation ion-current density, from which sheath thickness can be calculated. The results of the measurement show reasonable dependence on source power, bias power and pressure. Based on self-consistent calculation of potential distribution and ion- and electron-density distributions, simulation of the sheath potential distribution around an arbitrary 3D structure and the trajectory of incident ions from the plasma to the structure was developed. To confirm the validity of the distortion prediction by comparing it with experimentally measured distortion, silicon trench etching under chlorine inductively coupled plasma (ICP) was performed using a sample with a vertical step. It was found that the etched trench was distorted when the distance from the step was several millimetres or less. The distortion angle was about 20° at maximum. Measurement was performed using the on-wafer sheath-shape sensor in the same plasma condition as the etching. The ion incident angle, calculated as a function of distance from the step, successfully reproduced the experimentally measured angle, indicating that the combination of measurement by the on-wafer sheath-shape sensor and simulation can predict distortion of an etched structure. This prediction system will be useful for designing devices with large-scale 3D structures (such as those in MEMS) and determining the optimum etching conditions to obtain the desired profiles.

  6. Atomic scale fabrication of dangling bond structures on hydrogen passivated Si(0 0 1) wafers processed and nanopackaged in a clean room environment

    NASA Astrophysics Data System (ADS)

    Kolmer, Marek; Godlewski, Szymon; Zuzak, Rafal; Wojtaszek, Mateusz; Rauer, Caroline; Thuaire, Aurélie; Hartmann, Jean-Michel; Moriceau, Hubert; Joachim, Christian; Szymonski, Marek

    2014-01-01

    Specific surfaces allowing the ultra-high vacuum (UHV) creation of electronic interconnects and atomic nanostructures are required for the successful development of novel nanoscale electronic devices. Atomically flat and reconstructed Si(0 0 1):H surfaces are serious candidates for that role. In this work such Si:H surfaces were prepared in a cleanroom environment on 200 mm silicon wafers with a hydrogen bake and were subsequently bonded together to ensure the surface protection, and allow their transportation and storage for several months in air. Given the nature of the bonding, which was hydrophobic with weak van der Waals forces, we were then able to de-bond them in UHV. We show that the quality of the de-bonded Si:H surface enables the "at will" construction of sophisticated and complex dangling bond (DB) nanostructures by atomically precise scanning tunneling microscope (STM) tip induced desorption of hydrogen atoms. The DB structures created on slightly doped Si:H samples were characterized by scanning tunneling microscopy and spectroscopy (STM/STS) performed at 4 K. Our results demonstrate that DB nanostructures fabricated on UHV de-bonded Si(0 0 1):H wafers could be directly incorporated in future electronics as interconnects and parts of nanoscale logic circuits.

  7. Improvement of depth of focus control using wafer geometry

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sangmin; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Veeraraghavan, Sathish; Kim, JH; Awasthi, Amartya; Byeon, Jungho; Mueller, Dieter; Sinha, Jaydeep

    2015-03-01

    For several decades, the semiconductor industry has been controlling site flatness of the starting wafer material by defining tight specs on industry-standard site flatness metrics such as SFQR (Site Frontsurface-referenced least sQuares/Range) and ESFQR (Edge Site Frontsurface-referenced least sQuares/Range) that scale with technology nodes. The need for controlling site flatness of the starting material stems from previous research that shows that site flatness directly impacts lithography defocus. The wafer flatness variation changes significantly due to wafer processing downstream such as CMP, etch, and film deposition. Hence, for 2X nm and smaller technology nodes with very stringent focus process windows, it is critical to control wafer flatness variations at critical steps along the semiconductor process flow. In this paper, the capability of an interferometer-based patterned wafer metrology tool to predict lithography defocus is validated by comparison to scanner leveling data. The patterned wafer metrology tool is used to characterize the impact of near-edge flatness changes on the critical dimension (CD) of the contact holes due to different edge CMP process conditions. The results of the characterization illustrate how a site flatness specification or threshold can be developed for critical patterning steps. The paper also illustrates how the patterned wafer metrology tool can be used to identify processes causing site flatness variations. Finally, the site flatness variation at these processes can be monitored using the pattern wafer metrology tool to detect process drifts and excursion before patterning.

  8. Wafer level warpage characterization of 3D interconnect processing wafers

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2012-03-01

    We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 ?m after thinning down to the nominal thickness of 75 ?m and 50 ?m. The measurement precision is better than 2 um.

  9. Multi-Wafer Virtual Probe: Minimum-Cost Variation Characterization by Exploring Wafer-to-Wafer Correlation

    E-print Network

    Li, Xin

    Multi-Wafer Virtual Probe: Minimum-Cost Variation Characterization by Exploring Wafer-to-Wafer In this paper, we propose a new technique, referred to as Multi- Wafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Towards this goal, a novel Bayesian

  10. Ulnar Impaction Syndrome: Ulnar Shortening vs. Arthroscopic Wafer Procedure

    PubMed Central

    Smet, Luc De; Vandenberghe, Lore; Degreef, Ilse

    2014-01-01

    The outcome of ulnar shortenings was compared with that of arthroscopic wafer resections for ulnar impaction (or abutment) syndrome in patients with a positive ulnar variance. The outcome was measured by DASH score, visual analog scale for pain, and working incapacity. The mean DASH score in the ulnar shortening group was 26; in the wafer group it was 36. The VAS scores were respectively 4.4 and 4.6. The working incapacity was 7?months in the ulnar shortening group and 6.1 months in the wafer group. The differences between the two groups were not statistically significant. PMID:25032075

  11. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  12. Microsample tensile testing of LIGA nickel for MEMS applications

    Microsoft Academic Search

    K. J Hemker; H Last

    2001-01-01

    Electro-deposited LIGA Ni components are being considered for use in a number of microelectromechanical systems (MEMS) and applications. The metrology of these components and their non-equilibrium microstructures play an important role in determining the mechanical response of these structures. Microsample testing has proven to be a reliable way of measuring the elastic and plastic tensile properties of these 100–200 ?m

  13. Micro injection molding for mass production using LIGA mold inserts

    Microsoft Academic Search

    Takanori Katoh; Ryuichi Tokuno; Yanping Zhang; Masahiro Abe; Katsumi Akita; Masaharu Akamatsu

    2008-01-01

    Micro molding is one of key technologies for mass production of polymer micro parts and structures with high aspect ratios.\\u000a The authors developed a commercially available micro injection molding technology for high aspect ratio microstructures (HARMs)\\u000a with LIGA-made mold inserts and pressurized CO2 gasses. The test inserts made of nickel with the smallest surface details of 5 ?m with structural height

  14. Low temperature full wafer adhesive bonding of structured wafers

    Microsoft Academic Search

    F. Niklaus; H. Andersson; P. Enoksson; G. Stemme

    2001-01-01

    In this paper, we present a technology for void free low temperature full wafer adhesive bonding of structured wafers. Benzocyclobutene (BCB) is used as the intermediate bonding material. BCB bonds well with various materials and does not release significant amounts of by-products during the curing process. Thus void-free bond interfaces can be achieved. Cured BCB coatings have an excellent resistance

  15. MIT Microsystems Technology LaboratoriesMIT Microsystems Technology LaboratoriesDavid White, Duane Boning and Aaron GowerDavid White, Duane Boning and Aaron Gower Characterization of Endpoint and Wafer LevelCharacterization of Endpoint and Wafer Level

    E-print Network

    Boning, Duane S.

    Boning and Aaron GowerDavid White, Duane Boning and Aaron Gower Characterization of Endpoint and Wafer LevelCharacterization of Endpoint and Wafer Level NonNon--Uniformity using InUniformity using In and Aaron Gower Outline of PresentationOutline of Presentation ·· Overview: Wafer Scale Endpoint Uniformity

  16. Wafer to wafer overlay control algorithm implementation based on statistics

    NASA Astrophysics Data System (ADS)

    Lee, Byeong Soo; Kang, Young Seog; Kong, Jeong Heung; Hwang, Hyun Woo; Song, Myeong Gyu

    2015-03-01

    For mass production of DRAM device, a stable and effective overlay control becomes more and more important as DRAM design rule shrinks. Existent technologies were already applied to overcome this situation. Nevertheless, we are still suffered from tight overlay margin and forced to move from lot-based to wafer-based overlay control. However, the wafer-based control method requires a huge amount of measurement resource. In this paper, we present the insight for the wafer-based overlay correction with optimal measurement resource which is suitable for mass production. The experiment which is the wafer-based overlay correction by several statistical analyses carried out for 2X nm node DRAM. Among them, linear regression is a strong candidate for wafer-based overlay control, which improved up to 0.8 nm of maximum overlay.

  17. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  18. Role of oxide thickening in fatigue crack initiation in LIGA nickel MEMS thin films

    E-print Network

    Shan, Wanliang

    Role of oxide thickening in fatigue crack initiation in LIGA nickel MEMS thin films W.L. Shan a 2012 Accepted 16 October 2012 Available online 24 October 2012 Keywords: LIGA Ni MEMS thin films Oxide micro-electro-mechanical-systems (MEMS) structures. & 2012 Elsevier B.V. All rights reserved. 1

  19. Mask registration and wafer overlay

    NASA Astrophysics Data System (ADS)

    Lee, Chulseung; Bang, Changjin; Kim, Myoungsoo; Kang, Hyosang; Lee, Dohwa; Jeong, Woonjae; Lim, Ok-Sung; Yoon, Seunghoon; Jung, Jaekang; Laske, Frank; Parisoli, Lidia; Roeth, Klaus-Dieter; Robinson, John C.; Jug, Sven; Izikson, Pavel; Dinu, Berta; Widmann, Amir; Choi, DongSub

    2010-03-01

    Overlay continues to be one of the key challenges for lithography in advanced semiconductor manufacturing. It becomes even more challenging due to the continued shrinking of the device node. Some low k1 techniques, such as Double Exposure and Double Patterning also add additional loss of the overlay margin due to the fact that the single layer pattern is created based on more than 1 exposure. Therefore, the overlay between 2 exposures requires very tight overlay specification. Mask registration is one of the major contributors to wafer overlay, especially field related overlay. We investigated mask registration and wafer overlay by co-analyzing the mask data and the wafer overlay data. To achieve the accurate cohesive results, we introduced the combined metrology mark which can be used for both mask registration measurement as well as for wafer overlay measurement. Coincidence of both metrology marks make it possible to subtract mask signature from wafer overlay without compromising the accuracy due to the physical distance between measurement marks, if we use 2 different marks for both metrologies. Therefore, it is possible to extract pure scanner related signatures, and to analyze the scanner related signatures in details to in order to enable root cause analysis and ultimately drive higher wafer yield. We determined the exact mask registration error in order to decompose wafer overlay into mask, scanner, process and metrology. We also studied the impact of pellicle mounting by comparison of mask registration measurement pre-pellicle mounting and post-pellicle mounting in this investigation.

  20. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    SciTech Connect

    Bajikar, Sateesh S.; DeCarlo, Francesco; Song, Joshua J.

    1998-05-22

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized from pyromellitic anhydride and oxydianiline (PMDA-ODA).

  1. Advanced Modelling of Silicon Wafer Solar Cells

    NASA Astrophysics Data System (ADS)

    Peters, Marius; Fajun, Ma; Siyu, Guo; Hoex, Bram; Blaesi, Benedikt; Glunz, Stefan; Aberle, Armin; Luther, Joachim

    2012-10-01

    Modelling of solar cells today is general practice in research and widely-used in industry. Established modelling software is typically limited to one dimension and/or to small scales. Additionally, novel effects, like, e.g., the use of diffractive structures or luminescent materials, are not established. In this paper we discuss how the combination of different modelling techniques can be used to overcome these limitations. In this context two examples are presented. The first example concerns the combination of the open source simulation software PC1D with circuit modelling to investigate the effect of local shunts on the global characteristics of a silicon wafer solar cell. For the investigated example (4.5 cm2 cell area) we find that a local point shunt reduces the solar cell efficiency by 4% relative. The second example concerns the modelling of diffractive gratings for thin silicon wafer solar cells. For this purpose, we use the rigorous coupled wave analysis to simulate Sentaurus technical computer-aided design (TCAD) is combined with the rigorous coupled wave analysis, a method to solve Maxwell's equations for periodic structures. Here we show that a grating can be used to improve the absorption in a thin silicon wafer solar cell considerably.

  2. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    PubMed

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

  3. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    NASA Astrophysics Data System (ADS)

    Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

    2014-08-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

  4. Spinner For Etching Of Semiconductor Wafers

    NASA Technical Reports Server (NTRS)

    Lombardi, Frank

    1989-01-01

    Simple, inexpensive apparatus coats semiconductor wafers uniformly with hydrofluoric acid for etching. Apparatus made in part from small commercial electric-fan motor. Features bowl that collects acid. Silicon wafer placed on platform and centered on axis; motor switched on. As wafer spins, drops of hydrofluoric acid applied from syringe. Centrifugal force spreads acid across wafer in fairly uniform sheet.

  5. Wafer-Level Thermocompression Bonds

    E-print Network

    Tsau, Christine H.

    Thermocompression bonding of gold is a promising technique for achieving low temperature, wafer-level bonding without the application of an electric field or complicated pre-bond cleaning procedure. The presence of a ductile ...

  6. Computational Modeling in Plasma Processing for 300 mm Wafers

    NASA Technical Reports Server (NTRS)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  7. LIGA-based microsystem manufacturing:the electrochemistry of through-mold depostion and material properties.

    SciTech Connect

    Kelly, James J. (Sandia National Laboratories, Livermore, CA); Goods, Steven Howard (Sandia National Laboratories, Livermore, CA)

    2005-06-01

    The report presented below is to appear in ''Electrochemistry at the Nanoscale'', Patrik Schmuki, Ed. Springer-Verlag, (ca. 2005). The history of the LIGA process, used for fabricating dimensional precise structures for microsystem applications, is briefly reviewed, as are the basic elements of the technology. The principal focus however, is on the unique aspects of the electrochemistry of LIGA through-mask metal deposition and the generation of the fine and uniform microstructures necessary to ensure proper functionality of LIGA components. We draw from both previously published work by external researchers in the field as well as from published and unpublished studies from within Sandia.

  8. Wafer characteristics via reflectometry and wafer processing apparatus and method

    DOEpatents

    Sopori, Bhushan L. (Denver, CO)

    2007-07-03

    An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

  9. Selective area growth of InP in shallow trench isolation on large scale Si(001) wafer using defect confinement technique

    NASA Astrophysics Data System (ADS)

    Merckling, C.; Waldron, N.; Jiang, S.; Guo, W.; Richard, O.; Douhard, B.; Moussa, A.; Vanhaeren, D.; Bender, H.; Collaert, N.; Heyns, M.; Thean, A.; Caymax, M.; Vandervorst, W.

    2013-07-01

    Heterogeneous integration of III-V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III-V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III-V virtual substrates on large-scale Si substrates.

  10. Fabrication of Spiral Micro-Coil Utilizing LIGA Process

    NASA Astrophysics Data System (ADS)

    Shimada, Osamu; Kusumi, Shinji; Mekaru, Harutaka; Sato, Noriaki; Shimizu, Masami; Yamashita, Michiru; Hattori, Tadashi

    We developed a method for fabricating a three-dimensional spiral micro-inductor with high inductance using the LIGA process. The spiral inductor created had a diameter of 0.5mm, and a length of 1mm. The width of the spiral line was 10µm, the pitch was 20µm, and the number of turns was 15. It was made of plated copper. The master was a brass round bar coated with PMMA resist. Deep X-ray lithography was employed to fabricate a master for a metallic mold at the NewSUBARU synchrotron radiation facility, University of Hyogo. The inductor core was made of resin by injection molding. It has a spiral micro flute on the surface. We chose the worm injection molding technique in order to avoid the parting line across the spiral line. The worm injection molding was the method─for demolding the work such as that used in loosening a screw.

  11. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R. (Berkeley, CA)

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  12. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  13. Exploration of optical and electronic parameters of lithium thiogallate (LiGaS2)

    Microsoft Academic Search

    Victor V. Atuchin; Ludmila I. Isaenko; Valeriy G. Kesler; Zheshuai Lin; S. I. Lobanov

    2011-01-01

    Electronic and optical properties of the infrared crystal LiGaS2 are studied by both experimental and theo- retical methods. Based on the X-ray photoelectron spectros- copy measurements, the electronic structures of Ga 3d orbi- tals are corrected by the GGA+U methods. Linear and nonlinear optical parameters of LiGaS2 are determined by the first-principles theory and compared with earlier pub- lished experimental

  14. Wafer-level vacuum packaging technology based on selective electroplating

    NASA Astrophysics Data System (ADS)

    Topart, Patrice A.; Leclair, Sebastien; Alain, Christine; Jerominek, Hubert

    2004-01-01

    A novel concept for low-cost, wafer-level packaging of MEMS is proposed and applied to vacuum packaging of INO"s 160x120 pixel uncooled bolometric focal plane arrays, FPAs, based on vanadium oxide thermistor material. A wafer-scale metallic tray composed of several tens of micropackages is electroplated by using the thick resist SU-8 as a micromold. FPA dies and infrared windows are then soldered to the main tray by flip-chip bonding. Contrary to the conventional wafer to wafer bonding approach, assembly and vacuum sealing steps are dissociated. For this purpose, each micropackage is equipped with a pump-out hole for outgassing under vacuum and at elevated temperature prior to vacuum sealing. The process flow for fabrication of micropackages is described. The influence of DC and pulse plating conditions on the stress and properties of deposited nickel packages was investigated. Results on the selective electroplating of indium solder on antireflection-coated IR window wafers and the formation of a solderable layer around the chip are presented.

  15. Impacts of reticle and wafer elasticity control on overall alignment management strategy

    NASA Astrophysics Data System (ADS)

    Morita, Etsuya; Kawakubo, Masaharu; Leung, Frank C.; McNamara, Sean J.; Parry, Joseph T.

    1998-06-01

    Maintaining projection-aligners' stage grids-is critical for maximum overlay performance of production lithography. It seems that, particularly in the U.S., the industry has chosen the 'artifact-wafer' strategy as the standard technique to achieve this goal. This paper is intended to identify problems in overlay management using artifact wafers and to provide solutions to address the issues. One of the major sources that degrade accuracy in overlay management is the expansion/shrinkage of wafers and reticles. Both wafers and reticles expand during printing due to the heat delivered from the illumination source. The amount of the expansion tends to increase as the power of the illumination source increases per industry's demand on higher throughput. Wafers and reticles expand/shrink also due to environmental temperature change. The significance of wafer expansion/shrinkage in this mode has tended to be neglected. This is probably because, since it is measured and compensated by the 2nd print alignment, wafer scaling in the first print does not impact overlay performance evaluated at the shot center. Wafer expansion/shrinkage, however, does cause intra-shot scaling errors in overlay. And more importantly, since artifact wafers serve as absolute stage-grid-references, their expansion/shrinkage directly impact accuracy of overlay management. Reticle expansion/shrinkage due to temperature difference between where the reticles were created and where they are used along with reticle manufacturing errors causes inaccuracy in intra- shot performance evaluation. As product design rules continues to tighten, the intra-shot overlay performance can no longer be neglected. The impacts of reticle- and wafer-elasticity on total overlay management will be discussed. Multiple techniques to address the elasticity issues will be demonstrated. The discussion will conclude with recommendations for generation and usage of the artifact wafers.

  16. Smoother Scribing of Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Danyluk, S.

    1986-01-01

    Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

  17. NREL Core Program; Session: Wafer Silicon (Presentation)

    SciTech Connect

    Wang, Q.

    2008-04-01

    This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

  18. Silicon Wafer Processing Dr. Seth P. Bates

    E-print Network

    Colton, Jonathan S.

    Silicon Wafer Processing Dr. Seth P. Bates Applied Materials Summer, 2000 Objective To provide from blank silicon wafers. Goals The Transfer Plan provides a curriculum covering the process of manufacturing integrated circuits from the silicon wafer blanks, using the equipment manufactured by Applied

  19. APPLIED PHYSICS REVIEWSFOCUSED REVIEW Adhesive wafer bonding

    E-print Network

    Salama, Khaled

    APPLIED PHYSICS REVIEWS­FOCUSED REVIEW Adhesive wafer bonding F. Niklausa Microsystem Technology 9 February 2006 Wafer bonding with intermediate polymer adhesives is an important fabrication-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive

  20. Wafer-to-Wafer Alignment for Three-Dimensional Integration: A Review

    Microsoft Academic Search

    Sang Hwui Lee; Kuan-Neng Chen; James Jian-Qiang Lu

    2011-01-01

    This paper presents a review of the wafer-to-wafer alignment used for 3-D integration. This technology is an im- portant manufacturing technique for advanced microelectronics and microelectromechanical systems, including 3-D integrated circuits, advanced wafer-level packaging, and microfluidics. Commercially available alignment tools provide prebonding wafer-to-wafer misalignment tolerances on the order of 0.25 µm. However, better alignment accuracy is required for increasing demands

  1. A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

    NASA Astrophysics Data System (ADS)

    Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

    2013-03-01

    The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

  2. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  3. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Astrophysics Data System (ADS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-02-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  4. Full chip implant correction with wafer topography OPC modeling in 2x nm bulk technologies

    NASA Astrophysics Data System (ADS)

    Michel, J.-C.; Le Denmat, J.-C.; Sungauer, E.; Robert, F.; Yesilada, E.; Armeanu, A.-M.; Entradas, J.; Sturtevant, J. L.; Do, T.; Granik, Y.

    2013-09-01

    Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted overexposure by wafer topography with technology node downscaling evolution [1], [2]. Starting from 2xnm technology nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer topography which can cause drastic pattern degradation [2], [3]. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a consequence, computational lithography solutions are currently under development in order to correct wafer topographical effects on mask [3]. For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer stack. In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC flow for chip scale mask correction is presented with quality and run time penalty analysis.

  5. Low temperature wafer direct bonding

    Microsoft Academic Search

    Qin-Yi Tong; Giho Cha; Roman Gafiteanu; Ulrich Gosele

    1994-01-01

    A pronounced increase of interface energy of room temperature bonded hydrophilic Si\\/Si, Si\\/SiO2, and SiO2\\/SiO 2 wafers after storage in air at room temperature, 150°C for 10-400 h has been observed. The increased number of OH groups due to a reaction between water and the strained oxide and\\/or silicon at the interface at temperatures below 110°C and the formation of

  6. An aluminum resist substrate for microfabrication by LIGA.

    SciTech Connect

    Kelly, James J.; Boehme, Dale R.; Hauck, Cheryl A. (Lawrence Berkeley National Laboratory, Berkeley, CA); Yang, Chu-Yeu Peter; Hunter, Luke L.; Griffiths, Stewart K.; McLean, Dorrance E.; Aigeldinger, Georg; Hekmaty, Michelle A.; Hachman, John T.; Losey, Matthew W.; Skala, Dawn M.; Korellis, John S.; Friedmann, Thomas Aquinas (Sandia National Laboratories, Albuquerque, NM); Yang, Nancy Y. C.; Lu, Wei-Yang

    2005-04-01

    Resist substrates used in the LIGA process must provide high initial bond strength between the substrate and resist, little degradation of the bond strength during x-ray exposure, acceptable undercut rates during development, and a surface enabling good electrodeposition of metals. Additionally, they should produce little fluorescence radiation and give small secondary doses in bright regions of the resist at the substrate interface. To develop a new substrate satisfying all these requirements, we have investigated secondary resist doses due to electrons and fluorescence, resist adhesion before exposure, loss of fine features during extended development, and the nucleation and adhesion of electrodeposits for various substrate materials. The result of these studies is a new anodized aluminum substrate and accompanying methods for resist bonding and electrodeposition. We demonstrate successful use of this substrate through all process steps and establish its capabilities via the fabrication of isolated resist features down to 6 {micro}m, feature aspect ratios up to 280 and electroformed nickel structures at heights of 190 to 1400 {micro}m. The minimum mask absorber thickness required for this new substrate ranges from 7 to 15 {micro}m depending on the resist thickness.

  7. Wafer bonding for three dimensional (3D) integration

    NASA Astrophysics Data System (ADS)

    Kwon, Yongchai

    2003-10-01

    Wafer scale 3D integration is recognized as an emerging technology to increase the performance of ICs. When bonding with processed ICs, the bonding process must be compatible with IC back-end processing. The fraction of bonded area was examined by optical inspection and BCB was selected as the baseline glue after achieving reproducible void-free bonding. Bond strength at the glue interface of bonded wafers was quantified by four-point bending. Using four point bending, the following effects of BCB glue on the bonding integrity were evaluated; (1) employment of adhesion promoter, (2) BCB glue thickness and (3) material stack. When the adhesion promoter is used, bond strength increases at both BCB bonds of 2.6 mum and 0.4 mum. These results also demonstrate that BCB glue thickness affects the bond strength at the glue interface with thicker glue layers corresponding to higher bond strength. The decrease in bond strength observed for thin BCB is due to a decrease of plastic dissipation energy, Gplastic, which is proportional to BCB thickness. In both bonded wafer pairs that include a PECVD oxide deposited silicon wafer and a glass wafer, bond strengths are linearly proportional to BCB thickness. With these results, the relationship between Gplastic , and bond breaking energy, Gtip, and BCB thickness, t is observed to be Gplastic ? 0.3 · Gtip · t. The effects of thermal cycling on bond strength and residual stress at the interface between BCB and a PECVD oxide, and the thermal stability of BCB were evaluated by four point bending and wafer curvature measurements. Stress relaxation of the PECVD oxide layer during thermal cycling leads to a decrease in the deformation energy due to residual stress, G residual, and to an increase in bond strength. In thermal cycling performed at temperatures of 350 and 400°C, it is observed that the relaxation of residual stress occurs predominantly during the first thermal cycle. Conclusively, the BCB process for wafer-to-wafer bonding applications is stabilized after four cycles at a temperature of 400°C. Thermal cycling performed at a temperature 450°C leads to cohesive failure within the BCB layer with low bond strength (<0.5 J/m2).

  8. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    DOEpatents

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  9. Wafer level reliability for high-performance VLSI design

    NASA Technical Reports Server (NTRS)

    Root, Bryan J.; Seefeldt, James D.

    1987-01-01

    As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

  10. Wafer-Level Packaging of Micromechanical Resonators

    Microsoft Academic Search

    Paul Jayachandran Joseph; Pejman Monajemi; Farrokh Ayazi; Paul A. Kohl

    2007-01-01

    An approach to low-cost, wafer-level packaging of microelectromechanical systems (MEMS), e.g., microresonators, is reported. The process does not require wafer-to-wafer bonding and can be applied to a wide range of MEMS devices. A sacrificial polymer-placeholder is first patterned on top of the MEMS component of interest, followed by overcoating with a low dielectric constant polymer overcoat. The sacrificial polymer decomposes

  11. Effect of Wafer Bow and Etch Patterns in Direct Wafer Bonding

    E-print Network

    Spearing, S. Mark

    Direct wafer bonding has been identified as an en-abling technology for microelectromechanical systems (MEMS). As the complexity of devices increase and the bonding of multiple patterned wafers is required, there is a need ...

  12. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  13. In-Situ Optical Wafer Temperature Measurement

    NASA Astrophysics Data System (ADS)

    Adams, Bruce; Schietinger, Chuck

    2003-09-01

    The need for increasingly tighter process control is eminently apparent as semiconductor device dimensions become smaller and wafers larger. Today "Thermal Budgets" are shrinking and ramp rates are increasing throughout wafer processing. Wafer temperature is perhaps the most universally critical process variable in front-end integrated circuits (IC) manufacturing. The use of pyrometry and optical lightpipes continues to gain widespread acceptance as the standard temperature control method in many processes. Lightpipes are used for controlling temperature in chemical vapor deposition (CVD), rapid thermal processing (RTP), epitaxial film growth (EPI) and physical vapor deposition (PVD). Optical thermometry offers numerous advantages over other forms of wafer temperature measurement. This paper presents the current strengths and limitations in optical wafer temperature measurement. Many factors continue to drive the measurement technology. As IC junctions become shallower, thermal budget concerns drive process temperatures down. Processing time and ramp rates continue to shorten in particular for implant anneals. Increasingly, process control requires complete thermal histories of wafers throughout IC manufacturing. These factors and new materials (copper and low-? dielectrics) push tool manufactures and pyrometer vendors toward lower temperatures while still requiring high sensitivity, and accuracy. The accuracy of most in-situ optical temperature measurement continues to be dominated by uncertainty in wafer emissivity. Factors that limit accuracy, e.g., from wafer to wafer and from tool to tool, and advances in the technology are discussed.

  14. A method to maintain wafer alignment precision during adhesive wafer bonding

    Microsoft Academic Search

    Frank Niklaus; Peter Enoksson; Edvard Kälvesten; Göran Stemme

    2003-01-01

    In this paper, a novel method is presented that prevents aligned wafers from shifting relative to each other during adhesive bonding. The attainable pre-bond wafer alignment accuracy on commercially available bonding equipment is typically 2–5?m. However, in adhesive wafer bonding, the intermediate adhesive material must exist in a liquid-like state to wet the wafer surfaces and thereby achieve bonding. When

  15. Wafer level embedding technology for 3D wafer level embedded package

    Microsoft Academic Search

    Aditya Kumar; Xia Dingwei; Vasarla Nagendra Sekhar; Sharon Lim; Chin Keng; Gaurav Sharma; Vempati Srinivas Rao; Vaidyanathan Kripesh; John H. Lau; Dim-Lee Kwong

    2009-01-01

    This paper presents the development of wafer level embedding process for a three dimensional (3D) embedded micro wafer level package (EMWLP). Wafer level embedding process was carried out by using compression molding machine and low-cost granular epoxy molding compound (EMC). Various molding process parameters such as molding time and temperature and three EMCs of different CTEs were analyzed to achieve

  16. JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 20, NO. 4, AUGUST 2011 885 Wafer-to-Wafer Alignment for Three-Dimensional

    E-print Network

    Salama, Khaled

    JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 20, NO. 4, AUGUST 2011 885 Wafer-to-Wafer Alignment-Qiang Lu, Fellow, IEEE Abstract--This paper presents a review of the wafer-to-wafer alignment used for 3-D and microelectromechanical systems, including 3-D integrated circuits, advanced wafer-level packaging, and microfluidics

  17. On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs Mottaqiallah Taouil1

    E-print Network

    Kuzmanov, Georgi

    On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs Mottaqiallah Taouil1 Said, and lower power consumption compared to planar ICs. Fabricating these 3D-SICs using Wafer-to- Wafer (W2W) stacking has several advantages including: high throughput, thin wafer and small die handling, and high TSV

  18. On Optimizing Test Cost for Wafer-to-Wafer 3D-Stacked ICs Mottaqiallah Taouil Said Hamdioui

    E-print Network

    Kuzmanov, Georgi

    On Optimizing Test Cost for Wafer-to-Wafer 3D-Stacked ICs Mottaqiallah Taouil Said Hamdioui to manufacture such 3D-SICs. Wafer-to-Wafer (W2W) stacking seems the most favorable approach when high manufacturing throughput, thinned wafers and small die handling is required. However, efficient and optimal test

  19. The evolution of silicon wafer cleaning technology

    Microsoft Academic Search

    Werner Kern

    1990-01-01

    The purity of wafer surfaces is an essential requisite for the successful fabrication of VLSI and ULSI silicon circuits. Wafer cleaning chemistry has remained essentially unchanged in the past 25 years and is based on hot alkaline and acidic hydrogen peroxide solutions, a process known as RCA Standard Clean. This is still the primary method used in the industry. What

  20. Designing a mechanism to cleave silicon wafers

    E-print Network

    Figueroa, Victor, 1982-

    2004-01-01

    A device was designed and manufactured to precisely cleave silicon wafers. Two vacuum chucks were designed to support a 150 mm diameter silicon wafer and cleave it by providing a pure moment at a pre-etched v-notch while ...

  1. Mechanical and metallographic characterization of LIGA fabricated nickel and 80%Ni20%Fe Permalloy

    Microsoft Academic Search

    T. R. Christenson; T. E. Buchheit; D. T. Schmale; R. J. Bourcier

    1998-01-01

    A table top servohydraulic load frame equipped with a laser displacement measurement system was constructed for the mechanical characterization of LIGA fabricated electroforms. A drop in tensile specimen geometry which includes a pattern to identify gauge length via laser scanning has proven to provide a convenient means to monitor and characterize mechanical property variations arising during processing. In addition to

  2. Mechanical property evaluation and failure analysis of cantilevered LIGA nickel microposts

    Microsoft Academic Search

    Lyndon S. Stephens; Kevin W. Kelly; Seshu Simhadri; Andy B. McCandless; E. I. Meletis

    2001-01-01

    An experimental apparatus has been built to measure the elastic modulus and bending strength (modulus of rupture) of LIGA nickel posts. The apparatus uses the static cantilever beam bending approach to measure mechanical properties in a direction parallel to the growth direction. Experimental results are presented for two sets of largely identical posts constructed using an overplating method. One set

  3. Methane production using resin-wafer electrodeionization

    DOEpatents

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  4. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Rhee, S. S.

    1979-01-01

    Several aspects of silicon wafer surface texturizing were studied. A low cost cleaning method that utilizes recycled Freon in an ultrasonic vapor degreaser to remove organic and inorganic contaminants from the surface of silicon wafers as received from silicon suppliers was investigated. The use of clean dry air and high throughout wafer batch drying techniques was shown to lower the cost of wafer drying. A two stage texturizing process was examined for suitability in large scale production. Also, an in-depth gettering study with the two stage texturizing process was performed for the enhancement of solar cell efficiency, minimization of current versus voltage curve dispersion, and improvement in process reproducibility. The 10% efficiency improvement goal was exceeded for the near term implementation of flat plate photovoltaic cost reduction.

  5. The Imaging Properties of a Silicon Wafer X-Ray Telescope

    NASA Technical Reports Server (NTRS)

    Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

    1994-01-01

    Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

  6. Enhancing the Reliability of Wafer Level Packaging by Using Solder Joints Layout Design

    Microsoft Academic Search

    Chang-Ming Liu; Chang-Chun Lee; Kuo-Ning Chiang

    2006-01-01

    During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint shape prediction methods have been incorporated as a

  7. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  8. A bulk silicon dissolved wafer process for microelectromechanical devices

    Microsoft Academic Search

    Yogesh B. Gianchandani; Khalil Najafi

    1992-01-01

    A single-sided bulk silicon dissolved wafer process that has been used to fabricate several different micromechanical structures is described. It involves the simultaneous processing of a glass wafer and a silicon wafer, which are eventually bonded together electrostatically. The silicon wafer is then dissolved to leave heavily boron doped devices attached to the glass substrate. Overhanging features can be fabricated

  9. Fabricating capacitive micromachined ultrasonic transducers with wafer-bonding technology

    Microsoft Academic Search

    Yongli Huang; A. Sanli Ergun; E. Haeggstrom; Mohammed H. Badi; B. T. Khuri-Yakub

    2003-01-01

    Introduces a new method for fabricating capacitive micromachined ultrasonic transducers (CMUTs) that uses a wafer bonding technique. The transducer membrane and cavity are defined on an SOI (silicon-on-insulator) wafer and on a prime wafer, respectively. Then, using silicon direct bonding in a vacuum environment, the two wafers are bonded together to form a transducer. This new technique, capable of fabricating

  10. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  11. Everything Wafers: A Guide to Semiconductor Substrates

    NSDL National Science Digital Library

    This website contains information on characteristics and properties of semiconductor wafers. Topics include types of substrates, process dependent characteristics, properties of semiconductors, cleaving, etching and other topics, along with related terms and links.

  12. Image quality and wafer level optics

    NASA Astrophysics Data System (ADS)

    Dagan, Y.; Humpston, G.

    2010-05-01

    Increasing demand from consumers to integrate camera modules into electronic devices, such as cell phones, has driven the cost of camera modules down very rapidly. Now that most cell phones include at least one camera, consumers are starting to ask for better image quality - without compromising on the cost. Wafer level optics has emerged over the past few years as an innovative technology enabling simultaneous manufacturing of thousands of lenses, at the wafer level. Using reflow-compatible materials to manufacture these lenses permits a reduction in the cost and size of camera module, thus answering the market demand for lowering the cost. But what about image quality? The author will present image quality analysis that was conducted for both VGA and megapixel camera resolutions. Comparison between conventional camera modules and wafer level camera modules shows wafer level technology brings equivalent, if not better, image quality performance compared to conventional camera modules.

  13. Wafer Backside Anisotropic Wet Etching of Silicon

    NSDL National Science Digital Library

    This animation, created by Southwest Center for Microsystems Education (SCME), illustrates how the "wafer backside anisotropic wet etching of silicon is used to form the pressure sensor chamber." Further information and resources can be found on the SCME website.

  14. Wafer Inspection Technology For Submicron Devices

    NASA Astrophysics Data System (ADS)

    Okamoto, Kazunori; Yoshitome, Shokichi

    1989-07-01

    As processes advance into production of submicron devices, reducing defect density to an acceptable level is becoming a more difficult task. To deal with this problem, new wafer inspection technologies have been developed. The new systems can inspect dense patterned wafers to identify particles and process defects. An improvement over manual inspection is realized in defect sensitivity, inspection speed, and consistency of results. The technologies available for automatic wafer inspection have different capabilities. Therefore, to take advantage of each technology, the methods for system utilization must be considered. The methods involve identification of killer defects and determining the problem cause and required corrective action. This paper will focus on typical defects found in a submicron manufacturing facility. An evaluation of new wafer inspection technology will be described. Examples will be given to illustrate how inspection technology can be applied to solve problems in a production line.

  15. A Novel Bonding Method for Ionic Wafers

    Microsoft Academic Search

    M. M. R. Howlader; Tadatomo Suga; Moon J. Kim

    2007-01-01

    A novel method for bonding sapphire, quartz, and glass wafers with silicon using the modified surface activated bonding (SAB) method is described. In this method, the mating surfaces were cleaned and simultaneously coated with nano-adhesion Fe layers using a low energy argon ion beam. The optical images show that the entire area of the 4-in wafers of LiNbO3\\/Si was bonded.

  16. Effects of wafer thermostability and wafer-holding materials on optical loss in GaAs annealing

    E-print Network

    Byer, Robert L.

    Effects of wafer thermostability and wafer-holding materials on optical loss in GaAs annealing Y. S for publication 13 February 1998 A periodic structure of bonded GaAs wafers has been proposed for quasi lead to unacceptably high optical losses. When commercial semi-insulating GaAs wafers were bonded

  17. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  18. Porous solid ion exchange wafer for immobilizing biomolecules

    SciTech Connect

    Arora, Michelle B. (Woodridge, IL); Hestekin, Jamie A. (Morton Grove, IL); Lin, YuPo J. (Naperville, IL); St. Martin, Edward J. (Libertyville, IL); Snyder, Seth W. (Lincolnwood, IL)

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  19. Fabrication and Preliminary Results for LiGA Fabricated Nickel Micro Gas Chromatograph Columns

    Microsoft Academic Search

    Abhinav Bhushan; Dawit Yemane; Edward B. Overton; Jost Goettert; Michael C. Murphy

    2007-01-01

    High aspect ratio nickel microfluidic columns were fabricated using the LiGA technique. The 2-m-long 50-mum-wide high aspect ratio columns will be the separation component of a handheld gas chromatograph device for detecting semivolatile and volatile compounds. As a first step, 600-mum-deep electrodeposited nickel columns were fabricated. The serpentine columns were sealed and pressure-flow rate characteristics compared with the theoretical values.

  20. A LigA Three-Domain Region Protects Hamsters from Lethal Infection by Leptospira interrogans

    PubMed Central

    Coutinho, Mariana L.; Choy, Henry A.; Kelley, Melissa M.; Matsunaga, James; Babbitt, Jane T.; Lewis, Michael S.; Aleixo, Jose Antonio G.; Haake, David A.

    2011-01-01

    The leptospiral LigA protein consists of 13 bacterial immunoglobulin-like (Big) domains and is the only purified recombinant subunit vaccine that has been demonstrated to protect against lethal challenge by a clinical isolate of Leptospira interrogans in the hamster model of leptospirosis. We determined the minimum number and location of LigA domains required for immunoprotection. Immunization with domains 11 and 12 was found to be required but insufficient for protection. Inclusion of a third domain, either 10 or 13, was required for 100% survival after intraperitoneal challenge with Leptospira interrogans serovar Copenhageni strain Fiocruz L1-130. As in previous studies, survivors had renal colonization; here, we quantitated the leptospiral burden by qPCR to be 1.2×103 to 8×105 copies of leptospiral DNA per microgram of kidney DNA. Although renal histopathology in survivors revealed tubulointerstitial changes indicating an inflammatory response to the infection, blood chemistry analysis indicated that renal function was normal. These studies define the Big domains of LigA that account for its vaccine efficacy and highlight the need for additional strategies to achieve sterilizing immunity to protect the mammalian host from leptospiral infection and its consequences. PMID:22180800

  1. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    None

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

  2. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  3. Thermal Behavior of Large-Diameter Silicon Wafers during High-Temperature Rapid Thermal Processing in Single Wafer Furnace

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Yokoyama, Ichiro; Kang, Kitaek; Takahashi, Nobuaki

    2002-07-01

    Thermal behavior of 200-mm- and 300-mm-diameter Si (100) wafers during high-temperature rapid thermal processing (RTP) in a single wafer furnace (SWF) is investigated as a function of temperature, pressure, process time, wafer handling method and speed. Significant elastic wafer shape deformation was observed during wafer temperature ramp-up. Slip generation was frequently observed in wafers processed above 1050°C. Size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in reducing defect generation during RTP at the given process conditions. Highly reproducible, slip-free RTP results were achieved in 200-mm- and 300-mm-diameter Si (100) wafers processed at 1100°C by optimizing the wafer handling method and speed.

  4. Semiconducting wafer form shaping with an electric discharge machine

    NASA Astrophysics Data System (ADS)

    Yang, Yu-Tung

    1988-09-01

    Gallium can be used as a temporary glue for semiconducting wafer mounting. The good electric contact between the electrode, the gallium layer, and the semiconducting wafer makes the spark cutting and the semiconducting wafer form shaping much easier. After wafer spark cutting, the residual gallium can be easily removed by a cotton swab from the surface of the wafer in warm isopropyl alcohol (IPA). Also, in this report, improved circuitry of the electric discharge machine for easy and economical construction is described. Gallium arsenide wafers have been form shaped by the present method.

  5. Laser furnace and method for zone refining of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

    1988-01-01

    A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

  6. Slip-Free Rapid Thermal Processing in Single Wafer Furnace

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-06-01

    Defect generation phenomena in Si wafers during atmospheric pressure rapid thermal processing (RTP) in a single wafer furnace (SWF) are investigated as a function of temperature, process time, wafer handling method and speed. The size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in controlling defect generation during RTP under given process conditions. Highly reproducible slip-free RTP results were achieved in 200-mm-diameter Si wafers processed at 1100°C for 60 s (up to 5 times) by optimizing the wafer handling method and speed.

  7. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ?50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (? 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu-precipitates (upto 50 nm) compresses Si-lattice to facilitate Si-XII/III

  8. Effect of wafer geometry on lithography chucking processes

    NASA Astrophysics Data System (ADS)

    Turner, Kevin T.; Sinha, Jaydeep K.

    2015-03-01

    Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

  9. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  10. A new optical technique for monitoring wafer curvature and stress during copper damascene processing

    NASA Astrophysics Data System (ADS)

    Boye, Carol A.; Carpio, Ronald; Woodring, Jennifer; Owen, David M.

    2004-05-01

    Initial characterization of the damascene process was obtained with the new coherent gradient sensing (CGS) interferometer on 200 and 300 mm wafers. The current study represents an extension of earlier work by taking advantage of the greater spatial resolution and data density of the CGS technique relative to more typical non-contact capacitance or laser scanning techniques. The comprehensiveness of the data provides insight into the uniformity of curvature and stress across the wafer. Measurements using the CGS technique were completed at multiple processing steps with principal emphasis being placed upon 300 mm dual damascene processing. It is shown that the greatest changes in wafer stress/topography occur as the wafer progresses through PVD barrier/seed, copper plate, copper anneal, and copper CMP. Of special interest in these studies is the formation of non-visual mechanical defects at a die level scale. Such measurements of valuable wafer properties are useful in not only process development, but also in process monitoring.

  11. Geometry control of recrystallized silicon wafers for solar applications

    E-print Network

    Ruggiero, Christopher W

    2009-01-01

    The cost of manufacturing crystalline silicon wafers for use in solar cells can be reduced by eliminating the waste streams caused by sawing ingots into individual wafers. Professor Emanuel Sachs has developed a new method ...

  12. Micro-machined dielectrically isolated (MMDI) wafer technology [SOI

    Microsoft Academic Search

    W. Cantarini; S. Lizotte; S. Ahmed

    1998-01-01

    This paper describes a new economical alternative to costly bonded silicon-on-insulator (BSOI) wafers in which dielectrically isolated wafers are fabricated from single bulk silicon wafers. Initial processing involves trench etching through a single wafer to a predefined depth using micro-machining tools. The trenches are filled with an insulator to provide lateral dielectric isolation. Standard semiconductor processing is performed. The back

  13. Low-temperature full wafer adhesive bonding

    Microsoft Academic Search

    Frank Niklaus; Peter Enoksson; Edvard Kälvesten; Göran Stemme

    2001-01-01

    We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 µm and 18 µm. The tested polymer materials were benzocyclobutene (BCB)

  14. Wafer Bonded Subwavelength Metallo-Dielectric Laser

    E-print Network

    Fainman, Yeshaiahu

    . Date of current version June 28, 2011. This work was supported by the Defense Advanced Research Projects Agency, the National Science Foundation (NSF), the NSF Center for Integrated Access Networks Wafer Bonded Metallo-Dielectric Laser #12;reported by a few research groups [4]­[9], but integration

  15. Defect detection in patterned wafers using multichannel Scanning Electron Microscope

    E-print Network

    Cohen, Israel

    Defect detection in patterned wafers using multichannel Scanning Electron Microscope Maria Zontak using Scanning Electron Microscope (SEM) images. A wafer is irradiated with a focused beam of electrons s t r a c t Recent computational methods of wafer defect detection often inspect Scanning Electron

  16. NEW OR IMPRO VED DEVICES. DIRECT STEPPING ON WAFERS

    E-print Network

    Paris-Sud XI, Université de

    667 NEW OR IMPRO VED DEVICES. DIRECT STEPPING ON WAFERS P. PARRENS and P. TIGREAT (*) CEA-CENG LETI parameters such as wafer reflectivity, numerical aperture of the lens, spatial coherence of illumination. - Direct stepping on wafers has become a well-known and accepted technique after many recent publications

  17. Spatial Estimation of Wafer Measurement Parameters Using Gaussian Process Models

    E-print Network

    Makris, Yiorgos

    Spatial Estimation of Wafer Measurement Parameters Using Gaussian Process Models Nathan Kupp, Ke) are collected to monitor the health-of-line and to make wafer scrap decisions preceding final test. These measurements are typically sampled spatially across the surface of the wafer from between-die scribe line sites

  18. Enhanced Design Flow and Optimizations for Multi-Project Wafers

    E-print Network

    Zelikovsky, Alexander

    1 Enhanced Design Flow and Optimizations for Multi-Project Wafers Andrew B. Kahng Ion I. Mandoiu Xu and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW of mask tooling among up to tens of designs. However, MPW reticle floorplanning and wafer dicing introduce

  19. Automatic Clustering of Wafer Spatial Signatures Wangyang Zhang

    E-print Network

    Li, Xin

    1 Automatic Clustering of Wafer Spatial Signatures Wangyang Zhang 1 , Xin Li 1 , Sharad Saxena 2 of wafer spatial signatures to aid yield improvement. Our proposed methodology is based on three steps. First, we apply sparse regression to automatically capture wafer spatial signatures by a small number

  20. Integrating Through-Wafer Interconnects With Active Devices and Circuits

    Microsoft Academic Search

    Jim Jozwiak; Richard G. Southwick; III; Vaughn N. Johnson; William B. Knowlton; Amy J. Moll

    2008-01-01

    Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside

  1. MECHANICAL STRENGTH OF SILICON WAFERS AND ITS MODELLING

    Microsoft Academic Search

    G. Coletti; C. J. J. Tool; L. J. Geerligs

    Mechanical strength measurements of multicrystall ine Si wafers are carried out with a ring -on-ring test geometry. This geometry is very sensitive to the surface of the wafers rather than the edge. The measurements reveal the great importance of the saw damage on the mechanical stability of as-cut as well as textured wafers. The initial surface defects make a big

  2. Strength of Si Wafers with Microcracks: A Theoretical Model (Poster)

    SciTech Connect

    Rupnowski, P.; Sopori, B.

    2008-05-01

    A new analytical expression that takes into account the surface, edge, and bulk properties of a wafer has been proposed to describe the strength of the brittle materials. A new proposed fracture-mechanics numerical simulation successfully predicted the strength of the cast silicon wafers. It has been shown that the predicted wafer strength distribution agrees well with the available experimental results.

  3. Automated reticle inspection data analysis for wafer fabs

    Microsoft Academic Search

    Derek Summers; Gong Chen; Bryan Reese; Trent Hutchinson; Marcus Liesching; Hai Ying; Russell Dover

    2008-01-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the

  4. Automated reticle inspection data analysis for wafer fabs

    Microsoft Academic Search

    Derek Summers; Gong Chen; Bryan Reese; Trent Hutchinson; Marcus Liesching; Hai Ying; Russell Dover

    2009-01-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the

  5. Spectral Hole-burning Properties of LiGa 5O 8:Co 2+ Nanocrystallites

    Microsoft Academic Search

    Baran Yildirim; Hans Riesen

    2010-01-01

    Properties of persistent spectral holes in the 4A2(F)?4T1(P) transition in nanocrystalline (20–100 nm) powders and in single crystals of LiGa5O8:Co2+ have been investigated. It appears that for the investigated samples, the hole-burning efficiency is higher and spectral diffusion more pronounced in the nanocrystalline sample. Holes can efficiently be erased by exposure to 532 nm light but the 4A2(F)?4T1(P) luminescence appears

  6. Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Shi, Fang Frank

    Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances. Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported. Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure mechanism. The kinetic and thermodynamic analysis of the annealing-induced interfacial transformation process has been performed based upon the temporal measurements of interface electrical conductivity and micromorphologies. Finally, the feasibility of using the combination of low-temperature grown amorphous alpha-(Ga, As) materials and wafer-bonding technology to fabricate GaSb semiconductor on GaAs substrates to potentially create GaSb-on-insulator structure has been demonstrated.

  7. Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force

    Microsoft Academic Search

    Minoru Sudou; Hidekuni Takao; Kazuaki Sawada; Makoto Ishida

    2007-01-01

    This paper reports about a novel wafer-level integration technique of discrete surface mount devices (SMDs). It enables wafer-level mounting of plural kinds of SMDs on a silicon (Si)-wafer using vibration and gravity force. Deep holes with 400-m depth are formed on the surface of a Si-wafer by deep reactive ion etching process after general integrated circuit process for positioning of

  8. Observation of silicon wafer emissivity in rapid thermal processing chambers for pyrometric temperature monitoring

    Microsoft Academic Search

    J. Nulman; S. Antonio; W. Blonigan

    1990-01-01

    The emissivity of silicon wafers in a rapid thermal processing chamber has been measured as a function of the wafer temperature. Wafers with different surface roughness and layers have been studied. For transparent wafers, both sides of the wafer affect the emissivity. This emissivity is not only affected by surface roughness, but also by the layers deposited on the wafer.

  9. Sensors and Achcators A, 43 (1994) 22X29 223 Low-temperature silicon wafer-to-wafer bonding using gold at

    E-print Network

    Grigoriev, Alexei

    1994-01-01

    Sensors and Achcators A, 43 (1994) 22X29 223 Low-temperature silicon wafer-to-wafer bonding using and actuator systems of high complexity bemme commercially viable when realized as a multi-wafer device in which the mechanical functions are distributed over different wafers and one of the wafers is dedicated

  10. Experimental investigation of three-dimensional interconnect processing wafers

    NASA Astrophysics Data System (ADS)

    Ku, Yi-sha; Chang, Po-Yi; Shen, Chris

    2012-10-01

    The use and enhancement of a semi-automated wafer characterization tool, a dual channel capacitive sensor module, is demonstrated by implementing a new measurement algorithm for metallization process control. This tool is capable of measuring the deposited metal film thickness induced bow and warpage in a full wafer surface scan. The nondestructive solution can measure Cu metal film thickness with a total measurement uncertainty of 0.18 ?m (1?). The stress conversion map can be obtained based on the modified Stoney's formula and the capacitance-displacement technique. A wafer thinning process was also performed to characterize the warpage/bow of 8-in. wafers, which continues to increase as wafer thicknesses are reduced from 725 to 300 ?m. There was a linear relationship between the wafer warpage and bow and the square of the inverse of the thickness. Metrology results from actual 3-D interconnect processing wafers are presented.

  11. Equipment for On-Wafer Testing From 220 to 325 GHz

    NASA Technical Reports Server (NTRS)

    Samoska, Lorene; Peralta, Alejandro; Dawson, Douglas; Lee, Karen; Boll, Greg; Oleson, Chuck

    2006-01-01

    A system of electronic instrumentation, constituting the equivalent of a two-port vector network analyzer, has been developed for use in on-wafer measurement of key electrical characteristics of semiconductor devices at frequencies from 220 to 325 GHz. A prior system designed according to similar principles was reported in Equipment for On-Wafer Testing at Frequencies Up to 220 GHz (NPO-20760), NASA Tech Briefs, Vol. 25, No. 11 (November 2001), page 42. As one would expect, a major source of difficulty in progressing to the present higher-frequency-range system was the need for greater mechanical precision as wavelengths shorten into the millimeter range, approaching the scale of mechanical tolerances of prior systems. The system (see figure) includes both commercial off-the-shelf and custom equipment. As in the system of the cited prior article, the equipment includes test sets that are extended versions of commercial network analyzers that function in a lower frequency range. The extension to the higher frequency range is accomplished by use of custom frequency-extension modules that contain frequency multipliers and harmonic mixers. On-wafer measurement is made possible by waveguide wafer probes that were custom designed and built for this wavelength range, plus an on-wafer calibration substrate designed for use with these probes. In this case, the calibration substrate was specially fabricated by laser milling. The system was used to make the first on-wafer measurements of a semiconductor device in the frequency range from 220 to 320 GHz. Some of the measurement results showed that the device had gain.

  12. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL); St. Martin, Edward (Libertyville, IL); Arora, Michelle (Woodridge, IL); de la Garza, Linda (Woodridge, IL)

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  13. Comparison of On-Wafer Calibrations

    Microsoft Academic Search

    Dylan F. Williams; Roger B. Marks; Andrew Davidson

    1991-01-01

    A powerful new verification technique determines the measurement accuracy of scattering parameter calibrations. The technique determines the relative reference impedance, reference plane offset, and the worst-case measurement deviations of any calibration from a benchmark calibration. The technique is applied to several popular on-wafer scattering parameter calibrations, and the deviations between those calibrations and the thru-reflect line calibration are quantified.

  14. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  15. Lateral field emission diodes using SIMOX wafer

    Microsoft Academic Search

    Jung-Hyeon Park; Hyung-Il Lee; Heung-Sik Tae; Jeung-Soo Huh; Jung-Hee Lee

    1997-01-01

    Lateral field emission diodes were fabricated by using separation by implantation of oxygen (SIMOX) wafer and their current-voltage characteristics (I-V) were analyzed. Applying conventional photolithography and local oxidation of silicon (LOGOS) process, we fabricated single-crystalline lateral silicon field emitters with very sharp cathode and anode tips and very short cathode to anode spacing ranging from 0.3 to 0.8 ?m as

  16. "Performance Of A Wafer Stepper With Automatic Intra-Die Registration Correction."

    NASA Astrophysics Data System (ADS)

    van den Brink, M. A.; Wittekoek, S.; Linders, H. F. D.; van Hout, F. J.; George, R. A.

    1987-01-01

    An evaluation of a wafer stepper with the new improved Philips/ASM-L phase grating alignment system is reported. It is shown that an accurate alignment system needs an accurate X-Y-0 wafer stage and an accurate reticle Z stage to realize optimum overlay accuracy. This follows from a discussion of the overlay budget and an alignment procedure model. The accurate wafer stage permits high overlay accuracy using global alignment only, thus eliminating the throughput penalty of align-by-field schemes. The accurate reticle Z stage enables an intra-die magnification control with respect to the wafer scale. Various overlay data are reported, which have been measured with the automatic metrology program of the stepper. It is demonstrated that the new dual alignment system (with the external spatial filter) has improved the ability to align to weakly reflecting layers. The results are supported by a Fourier analysis of the alignment signal. Resolution data are given for the PAS 2500 projection lenses, which show that the high overlay accuracy of the system is properly matched with submicron linewidth control. The results of a recently introduced 20mm i-line lens with a numerical aperture of 0.4 (Zeiss 10-78-58) are included.

  17. Investigation of intrinsic gettering for germanium doped Czochralski silicon wafer

    NASA Astrophysics Data System (ADS)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Wang, Weiyan; Zeng, Yuheng; Que, Duanlin

    2007-06-01

    The intrinsic gettering (IG) effects in a germanium-doped Czochralski (GCz) silicon wafer have been investigated through a processing simulation of dynamic random access memory making and an evaluation on IG capability for copper contamination. It has been suggested that both the good quality defect-free denuded zones (DZs) and the high-density bulk microdefect (BMD) regions could be generated in GCz silicon wafer during device fabrication. Meanwhile, it was also indicated that the tiny oxygen precipitates were hardly presented in DZs of silicon wafer with the germanium doping. Furthermore, it was found in GCz silicon wafer that the BMDs were higher in density but smaller in size in contrast to that in conventional Cz silicon wafer. Promoted IG capability for metallic contamination was therefore induced in the germanium-doped Cz silicon wafer. A mechanism of the germanium doping on oxygen precipitation in Cz silicon was discussed, which was based on the hypothesis of germanium-related complexes.

  18. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  19. Resonance ultrasonic vibrations for crack detection in photovoltaic silicon wafers

    Microsoft Academic Search

    W. Dallas; O. Polupan; S. Ostapenko

    2007-01-01

    The resonance ultrasonic vibrations (RUV) technique is adapted for non-destructive crack detection in full-size silicon wafers for solar cells. The RUV methodology relies on deviation of the frequency response curve of a wafer, ultrasonically stimulated via vacuum coupled piezoelectric transducer, with a periphery crack versus regular non-cracked wafers as detected by a periphery mounted acoustic probe. Crack detection is illustrated

  20. Automatic saw-mark detection in multicrystalline solar wafer images

    Microsoft Academic Search

    Wei-Chen Li; Du-Ming Tsai

    2011-01-01

    This paper presents a method of automatic defect inspection for the photovoltaic industry, with a special focus on multicrystalline solar wafers. It presents a machine vision-based scheme to automatically detect saw-mark defects in solar wafer surfaces. A saw-mark defect is a severe flaw that occurs when a silicon ingot is cut into wafers. Early detection of saw-mark defects in the

  1. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M. (Antioch, CA)

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  2. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  3. Micro-miniature gas chromatograph column disposed in silicon wafers

    SciTech Connect

    Yu, C.M.

    2000-05-30

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  4. Wafer Signature Analysis of IDDQ Test Data Sagar S. Sabade D. M. H. Walker

    E-print Network

    Walker, Duncan M. "Hank"

    Wafer Signature Analysis of IDDQ Test Data Sagar S. Sabade D. M. H. Walker Department of Computer. The concept of wafer signature is proposed. A wafer signature is obtained by sorting all IDDQ readings on a wafer for a vector. A break or jump in the wafer signature is considered to indicate defective chips

  5. Free-standing CVD diamond wafers for thermal management by d.c. arc jet technology

    Microsoft Academic Search

    K. J Gray; H Windischmann

    1999-01-01

    Because of the unfavorable mechanical properties of diamond, the source and type of stresses present must be identified and controlled at every stage of the CVD diamond deposition process in order to develop a high-yield, large-wafer-scale fabrication process. In this paper, we report on the types of defect and stress encountered in free-standing CVD diamond films deposited by d.c. arc

  6. Electrooptic shutter devices utilizing PLZT ceramic wafers

    SciTech Connect

    Thornton, A.L.

    1981-01-01

    Optical transparency was achieved in lead zirconate-titanate ferroelectric ceramics by substituting moderate amounts of the element lanthanum (8 to 12%) for lead. These compositions exhibit the quadratic (Kerr) electrooptic effect. The excellent optical qualities of these materials (designated PLZT) has permitted the practical utilization of their electrooptic properties in a number of devices. All of these devices utilize the classic Kerr cell arrangement. A PLZT wafer with optical axis oriented at 45/sup 0/ with respect to the axes of polarization is sandwiched between crossed polarizers. Application of an electric field via an interdigital array of electrodes on opposing wafer surfaces forces the PLZT material into a tetragonal state with the resulting induced birefringence proportional to the square of the applied electric field. Hence, the electrooptic wafer provides a retardation of light so that a component is passed by the second crossed polarizer to achieve an ON or open state. Maximum transmission is achieved when the retardation is half-wave. Shutter devices developed by Sandia and those in continuing development are described with respect to operational characteristics and physical configuration. The devices range in size from very small apertures of 50 ..mu..m x 2 mm with center-to-center repeat dimensions of 125 ..mu..m - to very large - apertures of 15.2 cm in single pieces and mosaics with apertures of 15.2 cm x 20.3 cm. Major efforts have centered on shutter development for the protection of aircrew from eye-damaging weapon effects. Other devices are also described which: provide eye protection for welders, protect vidicon tubes, function as page composers for holographic memories serve as large aperture photographic shutters, provide stereoscopic three-dimensional TV displays, and serve as data links in a fiber-optic transmission path.

  7. Microsystems and wafer processes for volume production of highly reliable fiber optic components for telecom and datacom-application

    Microsoft Academic Search

    H. L. Althaus; W. Gramann; K. Panzer

    1998-01-01

    In realizing an efficient volume production of highly reliable active fiberoptic components the microsystem-technique was one of the most important factors. Micro-mechanical methods allow large scale fabrication of micro optical silicon lenses with methods, machines and materials using standard semiconductor wafer technology. With micromechanical processes, such as anodic bonding of optical components and special solder bonding techniques, it is possible

  8. Wafer-level optical interconnection network layout

    NASA Astrophysics Data System (ADS)

    Hornak, Lawrence A.; Tewksbury, Stuart K.; Weidman, Timothy W.; Kwock, Elizabeth W.

    1990-08-01

    Two important issues will greatly influence the success of mapping optical interconnections into future waferlevel distributed computing systems: (1), the scalability of active optical devices with cointegration along side ULSI components, and (2), the scalability of optical networks and components to the wafer level. If these criteria can be met, planar integrated and free-space optics can potentially provide a very high performance communication network within the multi-wafer environment. With the predominantly planar geometry and processing of waferlevel circuits, process compatible integrated planar optical interconnections are especially attractive for providing network passive connectivity. As with their electrical counterparts, spatial, as well as time division multiplexing of optical interconnections is desirable, given that layout and area constraints are not too severe. Therefore here, emphasis is shifted away from the individual behavior of traditional long distance lightwave single mode waveguides towards the collective system behaviour (i.e. density, coupling, layout, etc.) of large dense arrays of multimode optical waveguides. In this paper, initial experimental optical coupling results are presented for arrays of multimode polysilyne polymer waveguides, both for straight configurations and for arrays with radial right angle bend layouts.

  9. Thermal spray and cold spray analysis of density, porosity, and tensile Specimens for use with LIGA applications

    SciTech Connect

    DECKER,MERLIN K.; SMITH,MARK F.

    2000-02-01

    This analysis provides a preliminary investigation into using Twin-Wire Arc Thermal Spray and Cold Spray as material deposition processes for LIGA applications. These spray material processes were studied to make an initial determination of their potential as alternatives to producing mechanical parts via the electroplating process. Three materials, UltraMachinable{reg_sign} Stainless Steel, BondArc{reg_sign}, and aluminum, were sprayed using Thermal Spray. Only aluminum was sprayed using the Cold Spray process. Following the spray procedure, the test specimens were released from a copper mold and then tested. Three tests, density, tensile strength, and porosity, were performed on the specimens to determine the spray effect on material properties. Twin-Wire Arc Thermal Spray did not demonstrate adequate deposition properties and does not appear to be a good process candidate for LIGA. However, Cold Spray yielded better density results and warrants further investigation to analyze the minimum feature size produced by the process.

  10. Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

    2014-01-01

    This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

  11. Wafer-level filling of microfabricated atomic vapor cells based on thin-film deposition and photolysis of cesium azide

    SciTech Connect

    Liew, Li-Anne; Moreland, John; Gerginov, Vladislav [Electromagnetics Division, National Institute of Standards and Technology, Boulder, Colorado 80305 (United States); Time and Frequency Division, National Institute of Standards and Technology, Boulder, Colorado 80305 (United States)

    2007-03-12

    The thin-film deposition and photodecomposition of cesium azide are demonstrated and used to fill arrays of miniaturized atomic resonance cells with cesium and nitrogen buffer gas for chip-scale atomic-based instruments. Arrays of silicon cells are batch fabricated on wafers into which cesium azide is deposited by vacuum thermal evaporation. After vacuum sealing, the cells are irradiated with ultraviolet radiation, causing the azide to photodissociate into pure cesium and nitrogen in situ. This technology integrates the vapor-cell fabrication and filling procedures into one continuous and wafer-level parallel process, and results in cells that are optically transparent and chemically pure.

  12. 75 FR 76952 - Grant of Authority for Subzone Status; Lam Research Corporation (Wafer Fabrication Equipment...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-12-10

    ...Subzone Status; Lam Research Corporation (Wafer Fabrication Equipment) Fremont, Newark...establish a special-purpose subzone at the wafer fabrication equipment manufacturing and...to the manufacturing and distribution of wafer fabrication equipment at the...

  13. Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence

    E-print Network

    it is convenient to texture monocrystalline silicon wafers with a (100) surface orientation through alkaline etchImaging crystal orientations in multicrystalline silicon wafers via photoluminescence H. C. Sio, Z crystallization of amorphous silicon: Controlled nanosecond studies in the dynamic transmission electron

  14. A Model for the Silicon Wafer Bonding Process

    Microsoft Academic Search

    R. Stengl; T. Tan; U. Gösele

    1989-01-01

    The bonding speed (or contact wave velocity) of silicon and fused quartz wafers has been measured as a function of temperature. The results show that the bonding process stops to operate at temperatures above 90°C and 320°C for fused quartz and bare silicon wafers, respectively. By comparing our results to infrared spectra obtained from silica gel we develop a tentative

  15. Shock performance study of solder joints in wafer level packages

    Microsoft Academic Search

    Amarinder Singh Ranouta; Xuejun Fan; Qiang Han

    2009-01-01

    In this paper, an integrated testing, finite element modeling and failure analysis approach for drop test reliability of wafer level packages is developed to examine the shock performance of large array wafer level packages. For standard JEDEC drop test, it has been found that corner component group (group A) failed first for 12 times 12 array packages. This is different

  16. Effects of Wafer Emissivity on Rapid Thermal Processing Temperature Measurement

    NASA Astrophysics Data System (ADS)

    Chen, D. H.; DeWitt, D. P.; Tsai, B. K.; Kreider, K. G.; Kimes, W. A.

    2003-09-01

    Lightpipe radiation thermometers (LPRTs) are widely used to measure wafer temperatures in rapid thermal processing (RTP) tools. To use blackbody-calibrated LPRTs to infer the wafer temperature, it is necessary to build a model to predict the effective emissivity accounting for the wafer and chamber radiative properties as well as geometrical features of the chamber. The uncertainty associated with model-corrected temperatures can be investigated using test wafers instrumented with thin-film thermocouples (TFTCs) on which the LPRT target spot has been coated with films of different emissivity. A finite-element model of the wafer-chamber arrangement was used to investigate the effects of Pt spot (?s = 0.25) and Au spot (?s = 0.05) on the temperature distribution of test wafers with spectral emissivities of 0.65 and 0.84. The effects of the shield reflectivity and the cool lightpipe (LP) tip on the wafer temperature were evaluated. A radiance analysis method was developed, and a comparison of model-based predictions with experimental observations was made on a 200 mm diameter wafer in the NIST RTP test bed. The temperature rises caused by the low-emissivity spot were predicted and the cooling effect of the LP tip was determined. The results of the study are important for developing the model-based corrections for temperature measurements and related uncertainties using LPRTs in semiconductor thermal processes.

  17. Dispatching in an integrated circuit wafer fabrication line

    Microsoft Academic Search

    Pravin K. Johri

    1989-01-01

    Wafer Fabrication has been described as the most complicated manufacturing environment existing today. This paper describes a method used to dispatch lots in one of AT&T's Wafer Fabrication Clean Rooms. The objective is to minimize idle time on important facilities in the clean room. For each lot in the clean room, the method indicates the slack time the lot can

  18. Wafer-level microfluidic cooling interconnects for GSI

    Microsoft Academic Search

    Bing Dang; Paul Joseph; Muhannad Bakir; Todd Spencer; Paul Kohl; James Meindl

    2005-01-01

    We present a novel CMOS compatible approach to fabricate on-chip microfluidic cooling channels using a spin-on sacrificial polymer material at wafer level. Deep trenches (>100 ?m) etched into the backside of an IC wafer were successfully filled up by a single spin coating step with a high viscosity sacrificial polymer. A porous overcoat material allows the decomposition of the polymer

  19. Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint

    SciTech Connect

    Rupnowski, P.; Sopori, B.

    2008-05-01

    This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

  20. Effect of mechanical surface damage on Silicon wafer strength

    Microsoft Academic Search

    Daisuke Echizenya; Hiroo Sakamoto; Katsuhiko Sasaki

    2011-01-01

    Solar power generation using polycrystalline silicon wafers has been rapidly growing in recent years. As a result, it is required to understand the strength characteristics of polycrystalline silicon wafers in order to enhance their quality. Scratches and material defects should be taken into consideration when strength characteristics of polycrystalline silicon are evaluated, since it is a brittle material. In this

  1. QUANTIFYING SURFACE DAMAGE BY MEASURING MECHANICAL STRENGTH OF SILICON WAFERS

    Microsoft Academic Search

    G. Coletti; C. J. J. Tool; L. J. Geerligs

    Ring on ring test geometry reveals the great importance of the saw damage on the mechanical stability of as-cut and textured wafers. The initial surface defects make big and unexpected differences in the strength after a standard industrial acid etch. The measuring technique is very sensitive to the surface of the wafers rather than the edge. The influence of bulk

  2. Wafer fab conversion through theory of constraint project management techniques

    Microsoft Academic Search

    J. Fritz; J. Benjamin; R. Rerick

    1999-01-01

    Summary form only given. The drive for manufacturing on larger diameter wafers has been strong for the past few years and is projected to continue. Although the benefits of running production on larger diameter wafers has long been established throughout the industry, the capital investment to start a 300 mm or 200 mm fab from scratch can be difficult to

  3. Wafer Probe Station, Low Noise Amplifiers, and Wideband Feed Developments

    E-print Network

    Weinreb, Sander

    Wafer Probe Station, Low Noise Amplifiers, and Wideband Feed Developments S. Weinreb, A. Akgiray-ridge flared horn wideband feeds #12;Wafer Fabrication of LNA's and Other Radiometer Components 20-Sep-2011 of Millions Field Environment Phased- Array Feeds 0.7-1.8 15K/50K 300K 800,000 Noise SKA Mid 15m Dishes 0

  4. Hermetic wafer bonding based on rapid thermal processing , Liwei Lin

    E-print Network

    Lin, Liwei

    Hermetic wafer bonding based on rapid thermal processing Mu Chiao* , Liwei Lin Berkeley Sensor 94720-1740, USA Abstract Hermetic wafer bonding based on rapid thermal processing (RTP) has been are accomplished when the aluminum bonding solder is 150 mm wide and 4.5 mm thick. Furthermore, it is found

  5. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, Gary S. (Los Alamos, NM)

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  6. Thermal modeling of a wafer in a rapid thermal processor

    Microsoft Academic Search

    Jean-Marie Dilhac; Nicolas Nolhier; Christian Ganibal; Christine Zanchi

    1995-01-01

    A model, using geometric optics, has been developed to calculate the illumination of a wafer inside a rapid thermal processor. The main parameters of the model are: the processing chamber geometry, the lamp number and location, the reflector characteristics, and the wafer temperature. Each incident light component, i.e., direct or reflected, is identified, its contribution to the illumination of the

  7. Height Inspection of Wafer Bumps Without Explicit 3-D Reconstruction

    Microsoft Academic Search

    Mei Dong; Ronald Chung; Edmund Y. Lam; Kenneth S. M. Fung

    2010-01-01

    Die bonding in the semiconductor industry requires placement of solder bumps not on PCBs but on wafers. Such wafer bumps, which are much miniaturized from their counterparts on printed circuit boards (PCBs), require their heights meet rigid specifications. Yet the small size, the lack of texture, and the mirror-like nature of the bump surface make the inspection task a challenge.

  8. Wafer-scale integration-a fault-tolerant procedure

    Microsoft Academic Search

    RUSSELL C. AUBUSSON; IVOR CATT

    1978-01-01

    Considers a new approach to full-slice technology in relation to existing procedures for achieving this goal. Under external control a chain of good chips is created to form a long serial memory from an array of identical chips on a full slice. Bad chips are automatically bypassed without requiring any pre- or post-programming of the metallization and without any prior

  9. Wafer Scale Encapsulation of Large Lateral Deflection MEMS Structures

    Microsoft Academic Search

    A. B. Graham; M. Messana; P. Hartwell; J. Provine; S. Yoneoka; B. Kim; R. Melamud; R. T. Howe; T. W. Kenny

    2009-01-01

    Packaging of microelectromechanical systems (MEMS) is a critical step in the transition from product development to production. This paper presents a robust, hermetically-sealed encapsulation method that can accommodate many traditional MEMS devices by allowing large lateral deflection structures within a clean environment. Using the new technology described in this paper, trench widths ranging from 1 mum to 100 mum were

  10. Microstructure of AuSn Wafer Bonding for RF-MEMS Packaging

    Microsoft Academic Search

    Jian Cai; Qian Wang; Xiaogang Li; Woonbae Kim; Shuidi Wang; Junsik Hwang; Changyoul Moon

    2005-01-01

    RF-MEMS is one of the most potential applications for MEMS products. Eutectic solder wafer bonding is one of the attractive methods for RF-MEMS wafer level packaging. A process of gold-tin hermetical wafer bonding was developed in SAIT, Korean. Different UBM systems and thin films of gold-tin were deposited on cap wafer, RF-MEMS device wafer and substrate wafer (if needed). The

  11. ITS-90 calibration of radiation thermometers for RTP using wire/thin-film thermocouples on a wafer

    NASA Astrophysics Data System (ADS)

    Meyer, C. W.; DeWitt, D. P.; Kreider, K. G.; Lovas, F. J.; Tsai, B. K.

    2001-01-01

    Light-pipe radiation thermometers (LPRTs) are the sensor system of choice in RTP tools. They can be calibrated against blackbodies with an uncertainty (k=1) less than 0.3 °C. In an RTP tool, however, account must be made for wafer emissivity and wafer-chamber interreflections, or else temperature measurement uncertainties will be orders of magnitude higher. We have used two complementary approaches for accomplishing this: 1) in situ calibration using high-accuracy wire/thin-film thermocouples calibrated on the International Temperature Scale of 1990 (ITS-90) and 2) developing optical models to estimate the effective emissivity of the wafer ?eff when used in the radiation environment of the RTP tool. The temperature measurement uncertainty of LPRTs using either technique is 2.1 °C or less.

  12. Reduction of Thermal Conductivity in Wafer-Bonded Silicon

    SciTech Connect

    ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

    2006-11-27

    Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

  13. Wafer Inspection in the Photolithography Process

    NSDL National Science Digital Library

    This is a description for a learning module from Maricopa Advanced Technology Education Center. This PDF describes the module; access may be purchased by visiting the MATEC website. In this module, your learners begin to master the sensitive after develop inspection (ADI) methods that follow photolithography. MATEC describes macro- and micro-inspection techniques and distinguishes qualitative (inspection) from quantitative (metrology) methods. The chief focus is on teaching learners to examine wafers under an optical microscope; a simulated microscope is also provided in a computer-based training (CBT) format. The module covers edge bead inspection and provides extensive practice in flash boundary inspection, including evaluating Nikon crosses, overlay boxes, scanning electronic microscope features, resolution bars, Verniers, and product identification numbers.

  14. Piezoresistive stress sensors on (110) silicon wafers

    NASA Technical Reports Server (NTRS)

    Kang, Y. L.; Suhling, J. C.; Jaeger, R. C.

    1992-01-01

    Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

  15. MAPPER alignment sensor evaluation on process wafers

    NASA Astrophysics Data System (ADS)

    Vergeer, N.; Lattard, L.; de Boer, G.; Couweleers, F.; Dave, D.; Pradelles, J.; Bustos, J.

    2013-03-01

    MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing. In order to reduce costs and to minimize the footprint of this tool a new alignment sensor has been developed; based on technologies used for DVD optical heads. A wafer with an alignment mark is scanned with the sensor, resulting in an intensity pattern versus position. From this pattern the mark position can be calculated. Evaluations have been made over the performance of this type of sensor using different mark designs at several lithography process steps for FEOL and BEOL manufacturing. It has been shown that sub-nanometer reproducibility (3? std) of alignment mark readings can be achieved while being robust against various process steps.

  16. Capacitive micromachined ultrasonic transducers with through-wafer interconnects

    NASA Astrophysics Data System (ADS)

    Zhuang, Xuefeng

    Capacitive micromachined ultrasonic transducer (CMUT) is a promising candidate for making ultrasound transducer arrays for applications such as 3D medical ultrasound, non-destructive evaluation and chemical sensing. Advantages of CMUTs over traditional piezoelectric transducers include low-cost batch fabrication, wide bandwidth, and ability to fabricate arrays with broad operation frequency range and different geometric configurations on a single wafer. When incorporated with through-wafer interconnects, a CMUT array can be directly integrated with a front-end integrated circuit (IC) to achieve compact packaging and to mitigate the effects of the parasitic capacitance from the connection cables. Through-wafer via is the existing interconnect scheme for CMUT arrays, and many other types of micro-electro-mechanical system (MEMS) devices. However, to date, no successful through-wafer via fabrication technique compatible with the wafer-bonding method of making CMUT arrays has been demonstrated. The through-wafer via fabrication steps degrade the surface conditions of the wafer, reduce the radius of curvature, thus making it difficult to bond. This work focuses on new through-wafer interconnect techniques that are compatible with common MEMS fabrication techniques, including both surface-micromachining and direct wafer-to-wafer fusion bonding. In this dissertation, first, a through-wafer via interconnect technique with improved characteristics is presented. Then, two implementations of through-wafer trench isolation are demonstrated. The through-wafer trench methods differ from the through-wafer vias in that the electrical conduction is through the bulk silicon instead of the conductor in the vias. In the first implementation, a carrier wafer is used to provide mechanical support; in the second, mechanical support is provided by a silicon frame structure embedded inside the isolation trenches. Both implementations reduce fabrication complexity compared to the through-wafer via process, and result in low series resistance and small parasitic capacitance. Two-dimensional CMUT arrays incorporating trench-isolated interconnects show high output pressure (2.9 MPa), wide bandwidth (95%), small pulse-echo amplitude variation (sigma = 6.6% of the mean amplitude), and excellent element yield (100% in 16x16-element array). Volumetric ultrasound imaging was demonstrated by flip-chip bonding one of the fabricated 2D arrays to a custom-designed IC. An important added benefit of the trench-isolated interconnect is the capability to realize flexible arrays. A flexible 2D CMUT array is demonstrated by filling the trenches with polydimethylsiloxane (PDMS). The results presented in this dissertation show that through-wafer trench-isolation is a viable solution for providing electrical interconnects to CMUT elements. These techniques are potentially useful for providing through-wafer interconnects to many other types of MEMS sensors and actuators because of their post-process nature. The results also show that 2D CMUT arrays fabricated using wafer-bonding deliver good performance.

  17. Assessment of patients’ quality of life after haemorrhoidectomy using the LigaSure device

    PubMed Central

    Leksowski, Krzysztof

    2015-01-01

    Introduction Haemorrhoids are small anatomical structures within the anal canal that are involved in the proper functioning of the lower gastrointestinal tract. Factors favouring the development of haemorrhoidal disease are insufficient physical activity, prolonged sitting and hence a shortage of physical activity, as well as poor diet which lacks adequate amounts of fibre. The main symptom of this disease is bleeding with bright red blood just after defecation. Haemorrhoidal disease occurs when the ligamentous apparatus comes loose and the internal haemorrhoidal plexus translocates down, whereas haemorrhoids enlarge and move out of the anal canal. Haemorrhoidal disease treatment includes conservative, instrumental and surgical therapy. Aim To assess treatment and satisfaction in particular life domains after haemorrhoidectomy. Material and methods The research was undertaken in the General, Thoracic and Vascular Surgery Clinic of the 10th Military Clinical Hospital with Polyclinic in Bydgoszcz among 50 patients treated due to haemorrhoids and operated on in the period 2007–2008. The study evaluated quality of patients’ life after haemorrhoidectomy by Ferguson's method using a LigaSure appliance. Results The study investigated whether patients perceived a difference before and after surgery. The research proved that patients can describe disease symptoms and know the risk factors for haemorrhoids. In the studied group patients are able to describe characteristic signs of haemorrhoidal disease and also indicate differences in everyday life before and after the surgery. They can also describe and classify the pain before and 1 year after the haemorrhoidectomy, which was statistically significantly lower already 3 months after the operation. Conclusions Conducted examinations showed that sick people in the precise way were able to determine manifestations and know risk factors of the prevalence of disease hemorrhoidal. Operated sick people indicated the difference in quality of the life both before, as well as after the undergone treatment. After the operation of the haemorrhoids with method of Ferguson using LigaSure apparatus operated sick persons could distinguish and classify pain before the treatment as well as in a year after which was statistically characteristically lower already after three months from treatment. PMID:25960796

  18. Extraction and Analysis of Noise Parameters of On Wafer HEMTs up to 26.5 GHz

    SciTech Connect

    Caddemi, Alina; Crupi, Giovanni; Macchiarella, Alessio [Dipartimento di Fisica della Materia e Ingegneria Elettronica, University of Messina, Salita Sperone 31, 98166-Messina (Italy)

    2009-04-23

    This paper presents a procedure for extracting the four noise parameters of on wafer scaled HEMTs based on AlGaAs/GaAs heterostructure. This procedure relies on 50-{omega} noise figure measurements up to 26.5 GHz by determining the equivalent temperatures associated to the intrinsic resistances of the small signal equivalent circuit. The non-quasi-static effect associated to the gate-drain resistance R{sub gd} is accounted for by the noise model. A good agreement between measured and simulated noise figure is obtained and scaling of the noise parameters is reported.

  19. Optima XE Single Wafer High Energy Ion Implanter

    SciTech Connect

    Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny [Axcelis Technologies, Inc. 108 Cherry Hill Drive, Beverly, MA 01915 (United States)

    2008-11-03

    The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

  20. Wafer-level vacuum/hermetic packaging technologies for MEMS

    NASA Astrophysics Data System (ADS)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  1. Calibration wafer for temperature measurements in RTP tools

    NASA Astrophysics Data System (ADS)

    Kreider, K. G.; DeWitt, D. P.; Tsai, B. K.; Lovas, F. J.; Allen, D. W.

    1998-11-01

    Rapid thermal processing (RTP) is a key technology that is used to produce integrated circuits at lower cost and reduced thermal budgets. One of the limiting factors in expanding the use of RTP is the accuracy of temperature measurements of the wafer during processing. We are developing a wafer for calibrating radiometric temperature measurements in RTP tools. The calibration wafer incorporates thin-film thermocouples with platinum/palladium (Pt/Pd) wire thermocouples welded to thin-film pads at the periphery of the 200 mm wafers. We have reduced the uncertainty of the temperature measurements up to 1200 K with this system. This has been accomplished by reducing the uncertainty due to the thermocouple itself and due to reduction of heat transfer near the junction.We report results of NIST calibrations of radiometers using Pt/Pd wire thermocouples welded to the thin films on the wafer and of calibrated type K thermocouples. The thin-film thermocouples were sputter deposited from high purity Pt, Pd and Rh. These thin-film thermocouples were calibrated by comparison with Pt/Pd wire thermocouples in a specially designed test cell at temperatures up to 1150 K. Radiometric temperature measurements were made on the calibration wafer in the NIST RTP sensor test bed, using a commercial radiometer, and compared to those obtained from the thermocouple measurements. A model is presented to account for errors in the radiometric measurements due to stray radiation from the heating lamps, reflection of wafer emission from the chamber walls, and wafer emissivity. The calibrated type K thermocouples indicated temperature measurements within 4 K of both the Rh/Pt and Pt/Pd thermocouples on the 200 mm calibration wafer between 1000 K and 1150 K. The Pt/Pd thin films proved less durable than the Rh/Pt thin films and the limitations of these systems are discussed.

  2. The influence of feature sidewall tolerance on minimum absorber thickness for LIGA x-ray masks

    SciTech Connect

    S. K. Griffiths; J. M. Hruby; A. Ting

    1999-02-01

    Minimizing mask absorber thickness is an important practical concern in producing very small features by the LIGA process. To assist in this minimization, the authors have developed coupled numerical models describing both the exposure and development of a thick PMMA resist. The exposure model addresses multi-wavelength, one-dimensional x-ray transmission through multiple beam filters, through the mask substrate and absorber, and the subsequent attenuation and photon absorption in the PMMA resist. The development model describes one-dimensional dissolution of a feature and its sidewalls, taking into account the variation in absorbed dose through the PMMA thickness. These exposure and development models are coupled in a single interactive code, permitting the automated adjustment of mask absorber thickness to yield a prescribed sidewall taper or dissolution distance. They have used this tool to compute the minimum required absorber thickness yielding a prescribed sidewall tolerance for exposures performed at the ALS, SSRL and NSLS synchrotron sources. Results are presented as a function of the absorbed dose for a range of the prescribed sidewall tolerance, feature size, PMMA thickness, mask substrate thickness and the development temperature.

  3. Monitoring Dielectric Thin-Film Production on Product Wafers Using Infrared Emission Spectroscopy

    SciTech Connect

    NIEMCZYK,THOMAS M.; ZHANG,SONGBIAO; HAALAND,DAVID M.

    2000-12-18

    Monitoring of dielectric thin-film production in the microelectronics industry is generally accomplished by depositing a representative film on a monitor wafer and determining the film properties off line. One of the most important dielectric thin films in the manufacture of integrated circuits is borophosphosilicate glass (BPSG). The critical properties of BPSG thin films are the boron content, phosphorus content and film thickness. We have completed an experimental study that demonstrates that infrared emission spectroscopy coupled with multivariate analysis can be used to simultaneous y determine these properties directly from the spectra of product wafers, thus eliminating the need of producing monitor wafers. In addition, infrared emission data can be used to simultaneously determine the film temperature, which is an important film production parameter. The infrared data required to make these determinations can be collected on a time scale that is much faster than the film deposition time, hence infrared emission is an ideal candidate for an in-situ process monitor for dielectric thin-film production.

  4. Power-scalable 1.57 microm mode-locked semiconductor disk laser using wafer fusion.

    PubMed

    Saarinen, Esa J; Puustinen, Janne; Sirbu, Alexei; Mereuta, Alexandru; Caliman, Andrei; Kapon, Eli; Okhotnikov, Oleg G

    2009-10-15

    We report the first (to our knowledge) wafer-fused high-power passively mode-locked semiconductor disk laser operating at 1.57 microm wavelength. An InP-based active medium was fused with GaAs/AlGaAs distributed Bragg reflector on a 2 inch wafer level, resulting in an integrated monolithic gain mirror. An intracavity wedged diamond heat-spreader capillary bonded to the gain chip provides efficient heat removal from the gain structure without disturbing the spectrum of the mode-locked laser. The laser produces over 0.6 W of average output power at 15 degrees C with 16 ps pulse width. The total output power accounting for all output beams emerging from the cavity was 0.86 W. The results reveal an essential advantage of wafer fusion processing of disparate materials over monolithically grown InP-based gain structures and demonstrate the high potential of this technique for power scaling of long-wavelength semiconductor disk lasers. PMID:19838252

  5. Residual Stress Analysis in Thin Device Wafer Using Piezoresistive Stress Sensor

    Microsoft Academic Search

    Aditya Kumar; Xiaowu Zhang; Qing Xin Zhang; Ming Chinq Jong; Guanbo Huang; Lee Wen Sheng Vincent; Vaidyanathan Kripesh; Charles Lee; John H. Lau; Dim Lee Kwong; Venky Sundaram; Rao R. Tummula; Georg Meyer-Berg

    2011-01-01

    In this paper, piezoresistive stress sensors have been used to analyze the residual stress in thin device wafers. For the analysis, device wafers having piezoresistive stress sensors were fabricated. The stress sensors were then calibrated to determine the piezoresistive coefficients. The analysis of residual stress in device wafers was carried out after thinning the device wafers to three different thicknesses

  6. USING VARIATION DECOMPOSITION ANALYSIS TO DETERMINE THE EFFECT OF PROCESS ON WAFER AND DIELEVEL UNIFORMITY IN

    E-print Network

    Boning, Duane S.

    USING VARIATION DECOMPOSITION ANALYSIS TO DETERMINE THE EFFECT OF PROCESS ON WAFER­ AND DIE an understanding of the trade­offs in wafer and die­level uniformity, and their interaction, as functions the measured variation into wafer, die, wafer­die interaction and residual components, we have determined

  7. Stresa, Italy, 25-27 April 2007 NOVEL BONDING TECHNOLOGIES FOR WAFER-LEVEL TRANSPARENT

    E-print Network

    Boyer, Edmond

    Stresa, Italy, 25-27 April 2007 NOVEL BONDING TECHNOLOGIES FOR WAFER-LEVEL TRANSPARENT PACKAGING costs of most devices. Aligned wafer bonding techniques for Wafer-level packaging (WLP) demonstrates presents well understood wafer bonding and bond alignment technologies as well as high-volume proven

  8. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R. (Albuquerque, NM); Jones, Howland D. T. (Albuquerque, NM); Kelly, Michael J. (Albuquerque, NM); Medernach, John W. (Albuquerque, NM); Stevenson, Joel O. (Albuquerque, NM); Tsao, Sylvia S. (Albuquerque, NM)

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  9. Due-date based scheduling and control policies in a multiproduct semiconductor wafer fabrication facility

    Microsoft Academic Search

    Yeong-Dae Kim; Jung-Ug Kim; Seung-Kil Lim; Hong-Bae Jun

    1998-01-01

    This paper focuses on lot release control and scheduling problems in a semiconductor wafer fab producing multiple products that have different due dates and different process flows. For lot release control, it is necessary to determine the type of a wafer lot and the time to release wafers into the wafer fab, while it is necessary to determine sequences of

  10. System Validation of ASML wafer stepper System Validation IN4387 Group 2

    E-print Network

    Mousavi, Mohammad

    System Validation of ASML wafer stepper System Validation IN4387 Group 2 A. Delawari (anton;1 Introduction For the next generation of the wafer stepper, ultraviolet light is used to project the desired layout onto the wafer surface. Due to the absorption of ultraviolet light by the atmosphere, the wafer

  11. A study of defects on EUV masks using blank inspection, patterned mask inspection, and wafer inspection

    E-print Network

    A study of defects on EUV masks using blank inspection, patterned mask inspection, and wafer wafer inspection. The printable blank defect density excluding particles and patterns is 0.63/cm2 . Mask inspection is shown to have better sensitivity than wafer inspection. The sensitivity of wafer inspection

  12. Penetration of plasma into the wafer-focus ring gap in capacitively coupled plasmas

    E-print Network

    Kushner, Mark

    Penetration of plasma into the wafer-focus ring gap in capacitively coupled plasmas Natalia Y the edge of the wafer and wafer terminating structures, such as focus rings. The intended purpose of these structures is to make the reactant fluxes uniform to the edge of the wafer and so prevent a larger than

  13. Bonding silicon-on-insulator to glass wafers for integrated bio-electronic Hyun S. Kima)

    E-print Network

    Eom, Chang Beom

    layer after wafer bonding. The quality of the single crystalline Si thin film on the glass wafers hasBonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits Hyun S. Kima April 2004; accepted 28 July 2004) We report a method for bonding silicon-on-insulator wafers onto glass

  14. 9nm node wafer defect inspection using visible light

    NASA Astrophysics Data System (ADS)

    Zhou, Renjie; Edwards, Chris; Popescu, Gabriel; Goddard, Lynford L.

    2014-04-01

    Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

  15. Wafer-Based Nanostructure Manufacturing for Integrated Nanooptic Devices

    NASA Astrophysics Data System (ADS)

    Wang, Jian Jim; Chen, Lei; Tai, Stephen; Deng, Xuegong; Sciortino, Paul F.; Deng, Jiandong; Liu, Feng

    2005-02-01

    The authors have developed a nanomanufacturing platform based on wafer-level nanoreplication with mold and nanopattern transfer by nanolithography. The nanoreplication process, which is based on imprinting a single-layer spin-coated ultraviolet (UV)-curable resist, achieved good nanopatterning fidelity and on-wafer uniformity with high throughput. Some manufacturing issues of the nanoreplication process, such as the impact of wafer and mold surface particles on nanoreplication yield, are also discussed. Nano-optic devices, such as,quarter-wave plates and polarizers, were manufactured with the nanomanufacturing platform. An average wafer-level optical performance yield of 86% was achieved. The developed technology is applied for high-throughput and low-cost manufacturing nanostructure-based optical devices and integrated optical devices.

  16. Embedded Ultrasonics NDE with Piezoelectric Wafer Active Sensors

    Microsoft Academic Search

    Victor Giurgiutiu

    2003-01-01

    The use of piezoelectric wafer active sensors (PWAS) for embedded ultrasonic nondestructive evaluation (NDE) is described. PWAS structure and principle of operation are presented. The interaction between PWAS and ultrasonic Lamb waves is modeled and analyzed, and excitation \\

  17. High Throughput, Noncontact System for Screening Silicon Wafers Predisposed to Breakage During Solar Cell Production

    SciTech Connect

    Sopori, B.; Rupnowski, P.; Basnyat, P.; Mehta, V.

    2011-01-01

    We describe a non-contact, on-line system for screening wafers that are likely to break during solar cell/module fabrication. The wafers are transported on a conveyor belt under a light source, which illuminates the wafers with a specific light distribution. Each wafer undergoes a dynamic thermal stress whose magnitude mimics the highest stress the wafer will experience during cell/module fabrication. As a result of the stress, the weak wafers break, leaving only the wafers that are strong enough to survive the production processes. We will describe the mechanism of wafer breakage, introduce the wafer system, and discuss the results of the time-temperature (t-T) profile of wafers with and without microcracks.

  18. Silicon Wafer Bonding by Modified Surface Activated Bonding Methods

    Microsoft Academic Search

    Chenxi Wang; E. Higurashi; T. Suga

    2007-01-01

    8-inch Si-Si wafer bonding at room temperature is performed by means of two modified surface activated bonding (SAB) methods respectively, namely the SAB with nano-adhesion layer and sequential plasma activated bonding (SPAB). And post-annealing processes in atmospheric air utilized do not aim to improve the bonding strength, but to investigate void formation if the bonded wafers heated in subsequent heated

  19. Wafer-level radiation testing for hardness assurance

    Microsoft Academic Search

    M. R. Shaneyfelt; K. L. Hughes; J. R. Schwank; F. W. Sexton; D. M. Fleetwood; P. S. Winokur; E. W. Enlow

    1991-01-01

    To implement the qualified manufacturers list (QML) approach to hardness assurance in a practical and cost-effective manner, one must identify technology parameters that affect radiation hardness and bring them under statistical process control. To aid this effort, the authors have developed a wafer-level test system to map test-structure and IC response across a wafer. This system permits current-voltage and charge-pumping

  20. Materials integration for high-performance photovoltaics by wafer bonding

    Microsoft Academic Search

    James Michael Zahler

    2005-01-01

    The fundamental efficiency limit for state of the art triple-junction photovoltaic devices is being approached. By allowing integration of non-lattice-matched materials in monolithic structures, wafer bonding enables novel photovoltaic devices that have a greater number of subcells to improve the discretization of the solar spectrum, thus extending the efficiency limit of the devices. Additionally, wafer bonding enables the integration of

  1. Stress measurement of thin wafer using reflection grating method

    Microsoft Academic Search

    Chi Seng Ng; Anand K. Asundi

    2010-01-01

    Flatness\\/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature\\/flatness is thus necessary to ensure reliability of device

  2. GHz on-silicon-wafer probing calibration methods

    Microsoft Academic Search

    Arthur Fraser; Reed Gleason; E. W. Strid

    1988-01-01

    Three calibration\\/correction techniques for on-silicon-wafer S-parameter measurements to 18 GHz were assessed by comparing calibration standards on sapphire and silicon. The effect of these techniques was evaluated by measuring large and small devices, connected to large and small pads. Equivalent circuit models for the calibration standards on silicon are presented. In addition, a new technique for on-wafer S-parameter measurements of

  3. A micro chemical analyzing system integrated on a silicon wafer

    Microsoft Academic Search

    S. Nakagawa; S. Shoji; M. Esashi

    1990-01-01

    The fabrication of a three-way valve on a silicon wafer by micromachining techniques is presented. The valve consists of two silicon wafers, a pyrex glass, and a piezoelectric actuator. This three-way valve can control gas flow or liquid flow with voltage applied to the actuator. The liquid flow can be controlled from 0.1 ?l \\/min to 70 ?l\\/min. The results

  4. An ultraprecision stage for alignment of wafers in advanced microlithography

    Microsoft Academic Search

    Chang-Woo Lee; Seung-Woo Kim

    1997-01-01

    We present an ultraprecision stage specially designed to align wafers for the microlithography of integrated circuit patterns of sub-0.3 ?m design rules. The whole stage mechanism is composed of two individually operating xy?-stages: a global stage to provide initial coarse alignment of wafers in stepping mode; and a micro stage to produce fine controlability in nanometer range. The global stage

  5. A low cost wafer-level MEMS packaging technology

    Microsoft Academic Search

    P. Monajemi; F. Ayazi; P. J. Joseph; P. A. Kohl

    2005-01-01

    This paper presents a low-cost low-temperature packaging technique for wafer-level encapsulation of MEMS devices fabricated on any arbitrary substrate. The packaging process presented here does not involve wafer bonding and can be applied to a wide variety of MEMS devices after their fabrication sequence is completed. Our technique utilizes thermal decomposition of a sacrificial polymeric material through a polymer overcoat

  6. Optimized features allocation technique for improved automated alignment of wafers

    NASA Astrophysics Data System (ADS)

    Parshin, Michael; Zalevsky, Zeev

    2009-02-01

    In this paper we present a new fuzzy logic based approach for automatic optimized features allocation. The technique is used for improved automatic alignment and classification of silicon wafers and chips that are used in the electronic industry. The proposed automatic image processing approach was realized and experimentally demonstrated in real industrial application with typical wafers. The automatic features allocation and grading supported the industrial requirements and could replace human expert based inspection that currently is performed manually.

  7. Blood loss associated with radical cystectomy: A prospective, randomized study comparing impact LigaSure vs. stapling device?

    PubMed Central

    Thompson, Ian M.; Kappa, Stephen F.; Morgan, Todd M.; Barocas, Daniel A.; Bischoff, Carl J.; Keegan, Kirk A.; Stratton, Kelly L.; Clark, Peter E.; Resnick, Matthew J.; Smith, Joseph A.; Cookson, Michael S.; Chang, Sam S.

    2014-01-01

    Objectives Radical cystectomy (RC) is associated with significant blood loss and transfusion requirement. We performed a prospective, randomized trial to compare blood loss, operative time, and cost using 2 different and commonly employed approaches to tissue ligation and division during RC: mechanical (stapler device) and electrosurgical (heat-sealing device). Methods and materials Eighty patients undergoing RC for urothelial bladder carcinoma were randomized to use of either an Endo GIA Stapler or Impact LigaSure device for tissue ligation and division. Primary outcomes were blood loss, operative time, and device costs. Data were analyzed with Wilcoxon rank sum test and Welch 2-sample t test. Results There were no significant demographic or preoperative differences between the cohorts. Mean estimated blood loss was similar between the electrosurgical (687 ml) and stapler (708 ml) arms (P = 0.850). There were no significant differences between cohorts when comparing operative times or transfusion requirement. There was a significant increase in the mean number of adjunctive suture ligatures used in the stapling device arm (3.0 vs. 1.5, P = 0.047). Total device costs were significantly lower with the LigaSure compared with the GIA Stapler ($625.00 vs. $1490.10, P < 0.001). There were no complications attributable to either device. Conclusions This prospective, randomized study demonstrates no significant difference in blood loss, transfusion requirement, or safety between mechanical vs. electrosurgical control of the vascular pedicles. The LigaSure device, however, is significantly less costly than the GIA Stapler and required fewer additional measures for hemostasis. PMID:24054870

  8. A high throughput, noncontact system for screening silicon wafers predisposed to breakage during solar cell production

    Microsoft Academic Search

    Bhushan Sopori; Przemyslaw Rupnowski; Prakash Basnyat; Vishal Mehta

    2011-01-01

    We describe a non-contact, on-line system for screening wafers that are likely to break during solar cell\\/module fabrication. The wafers are transported on a conveyor belt under a light source, which illuminates the wafers with a specific light distribution. Each wafer undergoes a dynamic thermal stress whose magnitude mimics the highest stress the wafer will experience during cell\\/module fabrication. As

  9. Auto Defect Classification (ADC) Value for Patterned Wafer Inspection Systems in PLY Within a High Volume Wafer Manufacturing Fabrication Facility

    E-print Network

    Durniak, John

    2010-05-14

    The purpose of this investigation is to demonstrate value for Auto Defect Classification (ADC) for patterned wafer inspection systems within a high volume manufacturing fabrication in the Process Limited Yield (PLY) defect area. Process excursions...

  10. Application of EEM fluorescence spectroscopy in understanding of the "LIGA" phenomenon in the Bay of Biscay (France)

    NASA Astrophysics Data System (ADS)

    Parot, Jérémie; Susperregui, Nicolas; Rouaud, Vanessa; Dubois, Laurent; Anglade, Nathalie; Parlanti, Edith

    2014-05-01

    Marine mucilage is present in all oceans over the world, and in particular in the Mediterranean Sea and in the Pacific Ocean. Surface water warming and hydrodynamic processes can favor the coalescence of marine mucilage, large marine aggregates representing an ephemeral and extreme habitat for biota. DOM is a heterogeneous, complex mixture of compounds, including extracellular polymeric substances (EPS), with wide ranging chemical properties and it is well known to interact with pollutants and to affect their transport and their fate in aquatic environment. The LIGA French research program focuses on tracing colloidal dissolved organic matter (DOM) sources and cycling in the Bay of Biscay (South Western French coast). This ephemeral phenomenon (called "LIGA" in the South West of France) has been observed more than 750 times since 2010. It presents a great ecological impact on marine ecosystems and has been shown to be concomitant with the development of pathogen organisms. A one-year intensive survey of fluorescent DOM was undertaken. From April 2013 until May 2014, water samples were monthly collected from the Adour River (main fresh water inputs) and from 2 sites in the Bay of Biscay at 3 depths of the water column (surface water, at the maximum of chlorophyll-a, and deep water). Moreover, intensified samplings took place from the appearance of the phenomenon twice a week during 4 weeks. UV/visible absorbance and excitation emission matrix (EEM) fluorescence spectroscopy combined with PARAFAC and PCA analyses have been used to characterize colloidal DOM in the Bay of Biscay in order to estimate DOM sources as well as spatial and temporal variability of DOM properties. The preliminary results, obtained for about 70 samples of this survey, have already highlighted spatial and temporal variations of DOM optical properties and a peculiar fluorescent component (exc300nm/em338nm) was detected while the LIGA phenomenon arises. The appearance of this specific fluorescence signal seems to be correlated with high freshwater and terrestrial DOM inputs combined with physical forcing (flows, swell) as well as a rise in temperature and sunshine. This work already allowed us to identify different sources of colloidal DOM in the Bay of Biscay and highlighted a specific fingerprint of the LIGA phenomenon. The combination of EEM fluorescence spectroscopy with PARAFAC and PCA analyses appears thus to be a very powerful tool for the long term monitoring of such a phenomenon and would be very useful for a better understanding of the biogeochemical processes in marine environments and of the marine colloidal DOM ecodynamics.

  11. Performance of Ultra Hard Carbon Wear Coatings on Microgears Fabricated by Liga

    SciTech Connect

    Ager III, J.W.; Brown, I.G.; Christenson, T.R.; Dugger, M.T.; Follstaedt, D.M.; Knapp, J.A.; Monteiro, O.R.

    1998-12-18

    Stiction and friction are of concern for the reliable, long-term application of Ni-alloy micromachines. We have found that the application of a 30-70 nm hard carbon coating produces a significant reduction in the friction coefficient and wear rate of electroformed Ni substrates in reciprocating sliding contact under simulated MEMS operating conditions. To evaluate the performance of coated components, a series of 70-pm-thick microgears ranging in diameter from 0.2 to 2.2 mm were fabricated from electroformed Ni via standard LIGA processes and fixtured on posts in preparation for the coating procedure. A pulsed vacuum- arc deposition process was used to deposit a carbon coating on the gears with the plasma incident at a shallow angle to the gears' top surface. A sample bias of -2 keV was used in order to produce a coating with relatively low stress and good adhesion while maintaining high hardness. This coating process is known to be somewhat comformal to the component surfaces. The coating uniformity, particularly in the high-aspect-ratio areas between the gear teeth, was evaluated with micro-Raman spectroscopy. It is shown that the coating can be applied uniformly on the top gear surface. Between the gear teeth the coating was the same thickness as on top of the gear down to a point 50 ~m below the top surface. Below that point (i.e. between 50 and 70 Lm), the coating thickness is somewhat thinner, but is still present. These results demonstrate that it is possible to a deposit hard carbon coating on microgears to reduce friction and wear in micromachines.

  12. Testing specification for the wafer screening of the ABCD3T chip, Version V1.3, 1 December, 2000 Testing specification for the wafer screening

    E-print Network

    California at Santa Cruz, University of

    Page 1 Testing specification for the wafer screening of the ABCD3T chip, Version V1.3, 1 December, 2000 Testing specification for the wafer screening Project Name: ABCD3T ASIC Version: V1.3, 1 December, 2000 #12;Page 2 Testing specification for the wafer screening of the ABCD3T chip, Version V1.3, 1

  13. Incorporating BCNU wafers into malignant glioma treatment: European case studies.

    PubMed

    Balossier, Anne; Dörner, Lutz; Emery, Evelyne; Heese, Oliver; Mehdorn, H Maximilian; Menei, Philippe; Singh, Jagmohan

    2010-01-01

    Carmustine (BCNU: N,N'-bis[2-chloroethyl]-N-nitrosourea) wafers are a local chemotherapeutic agent for the treatment of malignant glioma. They avoid the problems of high toxicity and short half-life associated with systemic delivery, and can bridge the traditional 'treatment gap' between surgery and subsequent conventional chemo- or radiotherapy. Clinical trials have demonstrated significant improvements in survival and quality of life for patients after complete tumour resection and BCNU wafer implantation. In practice, clinicians may use BCNU wafers in conjunction with other radio- and chemotherapies, in order to maximize the chance of a beneficial patient outcome. The purpose of these case reports is to exemplify how four experienced European clinicians employ BCNU wafers for the management of malignant glioma, and to illustrate how BCNU wafers can be effectively incorporated into treatment regimens. Four patients are described in whom BCNU wafers were implanted during the course of treatment for glioblastoma multiforme, the most severe and common type of malignant glioma. These include three patients with recurrent disease, and a single patient with a newly diagnosed tumour. All four patients received additional radio- and chemotherapy as appropriate. Treatment was well tolerated and patient survival from diagnosis ranged from 56 to 132 weeks. This compared favourably with the survival of approximately 58 weeks seen in the recent EORTC-NCIC clinical trial of combined radiotherapy with concomitant and adjuvant temozolomide. BCNU wafers are an effective means of increasing survival and quality of life in patients diagnosed with malignant glioma, and are a valuable addition to the overall multimodal treatment strategy for these tumours. PMID:20155992

  14. An investigation of microstructure and mechanical properties of UV-LIGA nickel thin films electroplated in different electrolytes

    NASA Astrophysics Data System (ADS)

    Tang, Jun; Wang, Hong; Guo, XinQiu; Liu, Rui; Dai, XuHan; Ding, Guifu; Yang, ChunSheng

    2010-02-01

    Different electrolytes are used to fabricate nickel structures in MEMS devices by the LIGA or UV-LIGA process to meet different requirements. In order to investigate the microstructure and mechanical properties of nickel thin films electroplated in different electrolytes, four sets of nickel specimens were fabricated in different electrolytes: sulfamate bath with both saccharine and butynediol added (type A-I); sulfamate bath with saccharine added (type A-II); watts bath with saccharine added (type B); and chloride bath with saccharine added (type C). The function of these additives was to obtain the stress-free nickel films. The specimens were measured in our uniaxial tensile test system; their surface morphology and fractography, microstructure and texture were studied by SEM, TEM and XRD, respectively. The results show that the four sets of specimens have different mechanical properties and microstructures. The tensile strength of type A-II, type C and type A-I specimens increases with decreasing grain size, which is in accordance with the Hall-Petch law. In contrast, type B specimens have the highest value of ultimate tensile strength and elongation, but with the largest grain size among all the specimens. The XRD results show that there is no preferred orientation in type B while others have a preferred orientation in (2 0 0) along the growth direction. This might be the reason for the difference between type B and other types.

  15. RELAXED SIGE ON INSULATOR FABRICATED VIA WAFER BONDING AND LAYER TRANSFER: ETCH-BACK AND SMART-CUT ALTERNATIVES

    E-print Network

    RELAXED SIGE ON INSULATOR FABRICATED VIA WAFER BONDING AND LAYER TRANSFER: ETCH-BACK AND SMART.25. The substrate is bonded to an oxidized Si handle wafer, and the Si backside of the SiGe wafer is ground. Various, for the Smart-cut approach, the CMPed SiGe wafer is transferred onto an oxidized Si handle wafer. In particular

  16. Positive Photolithography Process Procedure with Shipley's 1813 Lithography consists of the following basic steps: Wafer preparation, photo resist

    E-print Network

    Kassegne, Samuel Kinde

    of the following basic steps: Wafer preparation, photo resist Coating, soft baking, exposing to UV light, post-exposure baking, and developing. 1. Prepare Wafer I. Simple Cleaning To remove contaminants from the wafer surface. a. Clean all equipment (wafer holders, tweezers, etc.) with acetone to avoid wafer contamination. b

  17. Negative Photolithography Process Procedure with SU -8 Lithography consists of the following basic steps: Wafer preparation, photoresist

    E-print Network

    Kassegne, Samuel Kinde

    steps: Wafer preparation, photoresist coating, softbaking, exposing to UV light, post-exposure baking, and developing. 1. Prepare Wafer I. Simple Cleaning To remove contaminants from the wafer surface. a. Clean all equipment (wafer holders, tweezers, etc.) with acetone to avoid wafer contamination. b. Cover the surface

  18. Effect of anion on micro\\/nano-tribological properties of ultra-thin imidazolium ionic liquid films on silicon wafer

    Microsoft Academic Search

    Wenjie Zhao; Min Zhu; Yufei Mo; Mingwu Bai

    2009-01-01

    Four kinds of room temperature ionic liquids (RTILs), as a new kind of lubricant for micro\\/nano-electromechanical system, with the same imidazolium cation but carrying different anions including hexafluorophosphate, tetrafluoroborate, nitrate and perchlorate were synthesized and these nano-scale films were prepared on single-crystal silicon wafer by dip-coating method. Atomic force microscopy was used to examine the morphologies of the films and

  19. Very high magnification optical characterization of global and local distortion of Si wafers after laser spike annealing

    Microsoft Academic Search

    Woo Sik Yoo; T. Ueda; T. Ishigaki; K. Kang

    2009-01-01

    The understanding of macro- and micro-scale wafer shape changes during device fabrication process steps is becoming very critical in developing and optimizing advanced technology node devices in which new materials such as Ni, NiPt and\\/or Ge are introduced. We have developed a non-contact, in-line process and\\/or material property monitoring method which uses various forms (reflection, diffraction, interference and scattering) of

  20. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    NASA Astrophysics Data System (ADS)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  1. Interpretation of stresses in thin films from wafer shape

    NASA Astrophysics Data System (ADS)

    Jachim, Anton F.

    In general, thin films deposited during semiconductor manufacturing exhibit intrinsic stress. If these stresses are not controlled, they can lead to failure of electronic devices by a variety of mechanisms. To some extent, film stress can be controlled by deposition process variation or annealing. But, in order to accurately control film stress, it must be accurately measured. Most film stress measurements are based on Stoney's equation. However, when in-plane film stress gradients are present, Stones equation is not an accurate stress-curvature relationship. A method of calculating plane film stress based on out-of-plane wafer displacements has been formulated using an inverse finite element model. The inverse model resolves graded film stresses and also includes the orthotropic elastic properties of single crystal silicon. Using simulation, the model has been tested with several virtual cases. It was also used in a case where an analytical relationship between film stress and wafer displacement was known. To evaluate the inverse model's ability to resolve a stress gradient experimentally, a gradient was induced into one film by local heating. The wafer shape was measured by a laser-scanning, curvature-based stress mapping tool, before and after deposition, as well as after heating. The inverse model was used to determine film stress from the measured wafer shape. The resulting film stress was then applied to a displacement-based finite element model, which successfully reproduced the measured wafer shape. However, the inverse model has not been verified by a comprehensive experimental testing program.

  2. Wafer heating mechanisms in a molecular gas, inductively coupled plasma: in situ, real time wafer surface measurements and three-dimensional thermal modeling

    SciTech Connect

    Titus, M. J.; Graves, D. B. [Department of Chemical Engineering, University of California, Berkeley, California 94720 (United States)

    2008-09-15

    The authors report measurements and modeling of wafer heating mechanisms in an Ar/O{sub 2} inductively coupled plasma (ICP). The authors employed a commercially available on-wafer sensor system (PlasmaTemp developed by KLA-Tencor) consisting of an on-board electronics module housing battery power and data storage with 30 temperature sensors embedded onto the wafer at different radial positions. This system allows for real time, in situ wafer temperature measurements. Wafer heating mechanisms were investigated by combining temperature measurements from the PlasmaTemp sensor wafer with a three-dimensional heat transfer model of the wafer and a model of the ICP. Comparisons between pure Ar and Ar/O{sub 2} discharges demonstrated that two additional wafer heating mechanisms can be important in molecular gas plasmas compared to atomic gas discharges. The two mechanisms are heating from the gas phase and O-atom surface recombination. These mechanisms were shown to contribute as much as 60% to wafer heating under conditions of low bias power. This study demonstrated how the 'on-wafer' temperature sensor not only yields a temperature profile distribution across the wafer, but can be used to help determine plasma characteristics, such as ion flux profiles or plasma processing temperatures.

  3. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, Theodoer F. (31843 Miwok Trail, P.O. Box 1453, Evergreen, CO 80439)

    1995-01-01

    Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

  4. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  5. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    SciTech Connect

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  6. Characterizing SOI Wafers By Use Of AOTF-PHI

    NASA Technical Reports Server (NTRS)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  7. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  8. Bonding of silicon wafers for silicon-on-insulator

    NASA Astrophysics Data System (ADS)

    Maszara, W. P.; Goetz, G.; Caviglia, A.; McKitterick, J. B.

    1988-11-01

    This paper describes a version of the bond-and-etchback silicon-on-insulator (BESOI) technique of Lasky (1986) and Shimbo et al. (1986) for creating a generic silicon-on-insulator (SOI) wafer. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophililc surfaces contacteed face-to-face, and the strength of the bonds created between bonded wafers was measured using a specially developed quantitative method based on crack propagation theory. The strength of the bonding was found to increase dramatically with the bonding temperature and to be independent of the bonding time. A model is proposed to explain three distinct phases of bonding in the temperature domain.

  9. Minority lifetime degradation of silicon wafers after electric zone melting

    NASA Astrophysics Data System (ADS)

    Wu, M. C.; Yang, C. F.; Lan, C. W.

    2015-06-01

    The degradation of minority lifetime of mono- and multi-crystalline silicon wafers after electric zone melting, a simple and contamination-free process, was investigated. The thermal-stress induced dislocations were responsible to the degradation; however, the grain size also played a crucial role. It was believed that the grain boundaries helped the relaxation of thermal stress, so that the degradation was reduced as the grain size decreased. In addition to lifetime mapping and etch pit density, photoluminescence mapping was also used to examine the electrically active defects after zone melting. Factors affecting lifetime degradation of silicon wafers after electric zone melting were examined. Small-grain multi-crystalline wafers showed better lifetime after zone melting. Twining area showed better lifetime. The formation of new grains relaxed the thermal stress mitigating lifetime degradation.

  10. Wafer based mask characterization for double patterning lithography

    NASA Astrophysics Data System (ADS)

    de Kruif, Robert; Bubke, Karsten; Janssen, Gert-Jan; van der Heijden, Eddy; Fochler, Jörg; Dusa, Mircea; Peters, Jan Hendrik; de Haas, Paul; Connolly, Brid

    2008-04-01

    Double Patterning Technology (DPT) is considered the most acceptable solution for 32nm node lithography. Apart from the obvious drawbacks of additional exposure and processing steps and therefore reduced throughput, DPT possesses a number of additional technical challenges. This relates to exposure tool capability, the actual applied process in the wafer fab but also to mask performance. This paper will focus on the latter. We will report on the performance of a two-reticle set based on a design developed to study the impact of mask global and local placement errors on a DPT dual line process. For 32 nm node lithography using DPT a reticle to reticle overlay contribution target of <= 1.5nm has been proposed. Reticle based measurements have shown that this proposed target can be met for standard overlay features and dedicated DPT features. In this paper we will present experimental intra field overlay wafer data resulting from the earlier mentioned reticle set. The reticles contain a 13x19 array of modules comprising various standard overlay features such as ASML overlay gratings and bar-in-bar overlay targets. Furthermore the modules contain split 40nm half pitch DPT features. The reticles have been exposed on an ASML XT:1700i on several wafers in multiple fields. Reticle to reticle overlay contribution has been studied in resist (double exposure) and using the IMEC dual line process (DPT). We will show that the reticle to reticle overlay contribution on the wafer is smaller than 1.5nm (1x). We will compare the wafer data with the reticle data, study the correlation and show that reticle to reticle overlay contribution based single mask registration measurements can be used to qualify the reticle to reticle overlay contribution on wafer.

  11. Toward 300 mm wafer-scalable high-performance polycrystalline chemical vapor deposited graphene transistors.

    PubMed

    Rahimi, Somayyeh; Tao, Li; Chowdhury, Sk Fahad; Park, Saungeun; Jouvray, Alex; Buttress, Simon; Rupesinghe, Nalin; Teo, Ken; Akinwande, Deji

    2014-10-28

    The largest applications of high-performance graphene will likely be realized when combined with ubiquitous Si very large scale integrated (VLSI) technology, affording a new portfolio of "back end of the line" devices including graphene radio frequency transistors, heat and transparent conductors, interconnects, mechanical actuators, sensors, and optical devices. To this end, we investigate the scalable growth of polycrystalline graphene through chemical vapor deposition (CVD) and its integration with Si VLSI technology. The large-area Raman mapping on CVD polycrystalline graphene on 150 and 300 mm wafers reveals >95% monolayer uniformity with negligible defects. About 26,000 graphene field-effect transistors were realized, and statistical evaluation indicates a device yield of ? 74% is achieved, 20% higher than previous reports. About 18% of devices show mobility of >3000 cm(2)/(V s), more than 3 times higher than prior results obtained over the same range from CVD polycrystalline graphene. The peak mobility observed here is ? 40% higher than the peak mobility values reported for single-crystalline graphene, a major advancement for polycrystalline graphene that can be readily manufactured. Intrinsic graphene features such as soft current saturation and three-region output characteristics at high field have also been observed on wafer-scale CVD graphene on which frequency doubler and amplifiers are demonstrated as well. Our growth and transport results on scalable CVD graphene have enabled 300 mm synthesis instrumentation that is now commercially available. PMID:25198884

  12. Wafer CD variation for random units of track and polarization

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

    2012-03-01

    After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle MTT and wafer intra-field MTT is shown for ENG process without polarization. The influence of different exposure conditions - with and without polarization of scanner laser source - on the average CD value for isolated and dense structures is demonstrated.

  13. Single incision cholecystectomy using a clipless technique with LigaSure in a resource limited environment: The Bahamas experience

    PubMed Central

    Downes, Ross O.; McFarlane, Michael; Diggiss, Charles; Iferenta, James

    2015-01-01

    Background Scarless/single-incision laparoscopic cholecystectomy (SILC) is a new procedure. It affords a superior cosmetic outcome when compared to conventional laparoscopic cholecystectomy. We examine the application of this technique using LigaSure via a clipless method. The present study looks at the experience of a single surgeon using this method with initial evaluation of the safety, feasibility, affordability, and benefits of this procedure. Methods Twenty-eight patients underwent transumbilical SILC at Doctors Hospital from January to December, 2014. The cohort included both emergency and elective patients. There was no difference in the preoperative work-up as indicated. To perform the operation, a 2–2.5-cm linear incision was made through the umbilicus and the single port platform utilized. A 10 mm 30-degree laparoscope, a 5 mm LigaSure and straight instruments were used to perform the laparoscopic cholecystectomy procedure. Results All patients except two were operated on successfully. Conversion was considered the placement of an additional epigastric/Right upper quadrant (RUQ) port. The conversion rate to standard LC was 7%. No patient was converted to open cholecystectomy. In the 28 successfully completed patients, the median duration of the operation was 38.5 min and estimated operative blood loss was 24 ml. Patients were commenced on liquid diet immediately on being fully conscious and after return to the ward with an estimated time of 6 h. The mean postoperative hospital stay was 1.4 days. Follow-up visits were conducted for all patients at 2-weeks intervals and continued for 6 weeks after surgery where possible. Two patients developed wound infections. All patients were satisfied with the good cosmetic effect of the surgery. The total satisfaction rate was 100%. Conclusions SILC is a safe and feasible technique for operating with scarless outcomes and reducing perioperative discomfort at the same time. The GelPOINTTM is a safe and feasible platform to be used. The procedure can be accomplished using regular instruments and laparoscope. Curved instruments and a bariatric length laparoscope may make the procedure easier and result in greater time saving. The addition of LigaSure™ decreases the complexity of the operation, decreases operative time and blood loss. The technique is economical in a resource-limited environment. PMID:25958050

  14. Scales

    SciTech Connect

    Murray Gibson

    2007-04-27

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain — a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  15. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    NASA Astrophysics Data System (ADS)

    Qiusheng, Y.; Senkai, C.; Jisheng, P.

    2015-03-01

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  16. Low-temperature vacuum hermetic wafer-level package for uncooled microbolometer FPAs

    Microsoft Academic Search

    S. Garcia-Blanco; P. Topart; Y. Desroches; J. S. Caron; F. Williamson; C. Alain; H. Jerominek

    2008-01-01

    Micro-Electro-Mechanical Systems (MEMS) packaging constitutes most of the cost of such devices. For the integration of MEMS with microelectronics systems to be widespread, a drastic reduction of the overall price is required. Wafer-level-packaging allows a fundamental reduction of the packaging cost by combining wafer-level microfabrication techniques with wafer-to-wafer bonding. To achieve the vacuum atmosphere required for the operation of many

  17. The large-area One-per-wafer ZTJ and ZTJM solar cells from Emcore

    Microsoft Academic Search

    Benjamin Cho; M. A. Stan; P. Patel; T. Varghese; G. Ramirez; D. Aiken; R. Lutz; N. Fatemi; P. Sharps

    2011-01-01

    The One-per-wafer denotes a single cell design for a large-area cell on a 100-mm diameter (4”) Ge wafer. As a result, the total area of this cell is on the order of ?60cm2, which is twice as large as most conventional two-per-wafer solar cells. The silicon bypass diode design for the One-per-wafer cell has successfully passed electrical screening after forward

  18. Analysis of stresses and breakage of crystalline silicon wafers during handling and transport

    Microsoft Academic Search

    Xavier F. Brun; Shreyes N. Melkote

    2009-01-01

    A significant challenge in using thinner and larger crystalline silicon wafers for solar cell manufacture is the reduced yield due to higher wafer breakage rates. At a given process step, wafer\\/cell breakage depends on the stresses produced in the wafer\\/cell due to prior processing, handling and\\/or transport and on the presence of structural defects such as cracks. Specifically, analysis of

  19. Konstanz, Germany: Sunways Secures Wafer Supply from LDK Solar

    Microsoft Academic Search

    Sunways AG has completed funding for the expansion of its Arnstadt cell production capacity. The expansion will accommodate the first wafer shipments expected to be received under the cooperation agreement with LDK Solar in the second half of the year. The 10 year agreement with the Chinese manufacturer will significantly improve the cost of materials situation at Sunways. The company

  20. Curvature measurement system of Si-wafer using circular gratings

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    2010-03-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. However, due to the prevalence of surface flatness measurement systems that flooded the market, the cycle time for curvature measurement system has become one of the critical factors for the user to consider. A simple and rapid whole-field curvature measurement system using a novel a computer aided phase shift reflection grating method has been developed and discussed in the previous publications. Laterals gratings in horizontal has vertical directions are needed in order to realize the curvature information on the wafer in both directions. In this paper, with same system setup, circular grating is being projected on to the specimen to measure the curvature distribution of the wafer. With the aid of coordinate-transform method and the digital phase-shifting technique, the digital images of reflected gratings are processed automatically and analyzed in the polar coordinate system. Unlike vertical or horizontal line gratings, the utilization of the circular gratings in radial shearing method provides curvature information in all directions, not only in one. Further, only four phase shifted images are captured and the measurement cycle time is thus reduced by half.

  1. Curvature measurement system of Si-wafer using circular gratings

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    2009-12-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. However, due to the prevalence of surface flatness measurement systems that flooded the market, the cycle time for curvature measurement system has become one of the critical factors for the user to consider. A simple and rapid whole-field curvature measurement system using a novel a computer aided phase shift reflection grating method has been developed and discussed in the previous publications. Laterals gratings in horizontal has vertical directions are needed in order to realize the curvature information on the wafer in both directions. In this paper, with same system setup, circular grating is being projected on to the specimen to measure the curvature distribution of the wafer. With the aid of coordinate-transform method and the digital phase-shifting technique, the digital images of reflected gratings are processed automatically and analyzed in the polar coordinate system. Unlike vertical or horizontal line gratings, the utilization of the circular gratings in radial shearing method provides curvature information in all directions, not only in one. Further, only four phase shifted images are captured and the measurement cycle time is thus reduced by half.

  2. A robust production control policy for VLSI wafer fabrication

    Microsoft Academic Search

    SHELDON X. C. LOU; PATRICK W. KAGER

    1989-01-01

    The authors present control policy for shop-level scheduling in a semiconductor wafer fabrication facility. The policy is designed to reduce the work in process in the shop floor and to follow the production plan as closely as possible. It is also robust against random interference such as machine breakdowns. The flow rate control policy is compared with two other approaches

  3. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    SciTech Connect

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

  4. Single-wafer cluster tool performance: an analysis of throughput

    Microsoft Academic Search

    T. L. Perkinson; P. K. McLarty; R. S. Gyurcsik

    1994-01-01

    Cluster tools gained greater acceptance over the past several years, although concerns still exist over the throughput these tools can achieve. This paper presents an analysis of the relationship between process times, transport times, and maximum throughput in an individual cluster tool. Theoretical models which quantify the time required to process both an individual wafer and a lot in a

  5. Characterizing the LSI Yield Equation from Wafer Test Data

    Microsoft Academic Search

    Sharad C. Seth; Vishwani D. Agrawal

    1984-01-01

    The results of production test on LSI wafers are analyzed to determine the parameters of the yield equation. Recognizing that a physical defect on a chip can produce several logical faults, the number of faults per defect is assumed to be a random variable with Poisson distribution. The analysis provides a relationship between the yield of the tested fraction of

  6. Crack propagation and fracture in silicon wafers under thermal stress

    PubMed Central

    Danilewsky, Andreas; Wittge, Jochen; Kiefl, Konstantin; Allen, David; McNally, Patrick; Garagorri, Jorge; Elizalde, M. Reyes; Baumbach, Tilo; Tanner, Brian K.

    2013-01-01

    The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing. PMID:24046487

  7. Wafer-Level Encapsulation and Sealing of Electrostatic HARPSS Transducers

    Microsoft Academic Search

    Siavash Pourkamali; Farrokh Ayazi

    2007-01-01

    This paper reports on a thin-film wafer-level encapsulation technique for packaging and CMOS integration of MEMS sensors and actuators fabricated through the HARPSS process. This approach takes advantage of the stationary parts of the micromechanical device itself for encapsulation of its sensitive moving parts, and therefore can be performed without addition of extensive processing steps. Encapsulated high frequency capacitive silicon

  8. MECHANICAL STRESS TESTS ON MC-SI WAFERS WITH MICROCRACKS

    Microsoft Academic Search

    Jörgen Gustafsson; Hanna Larsson; Hans Jørgen Solheim; Tobias Boström

    Micro crack detection and mechanical twist tests have been performed on as-cut wafers for solar cell production. A relation between the mechanical strength and crack length has been suggested. There is no indication of growth of crack length from repeated stress tests below the critical stress. It was found that edge cracks are more critical than interior cracks of same

  9. ASAP applications of simulation modeling in a wafer fab

    Microsoft Academic Search

    Kishore Potti; A. Gupta

    2002-01-01

    The authors define 4 levels of complexity in simulation modeling: the ability of the models to predict bottlenecks in the fab, capability of the model to be used for strategic applications such as cycle time reduction, the simulation of complex dispatch rules using the model, and the capability of the model to predict operational output of the wafer fab that

  10. Vibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements

    E-print Network

    Kao, Imin

    Vibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements I. Kao (PI), S the yield per crystal and to reduce the cost. In this paper, the vibration model of wiresaw system of vibration indicate the interference of excitation and natural frequencies in the vibration patterns

  11. Carrier lifetime of silicon wafers doped by neutron transmutation

    Microsoft Academic Search

    T Maekawa; S Inoue; A Aiura; A Usami

    1986-01-01

    Radiation damage in wafers cut from neutron transmutation doped float-zone silicon crystals has been studied by using minority carrier lifetime and conductivity measurements. The isochronal annealing behaviour of the lifetime is characterised by three regions in the temperature range from 480 to 1160 degrees C. For the samples annealed in the temperature region I where the recovery of conductivity is

  12. Influence of wafer fabrication technology on wire bond process

    Microsoft Academic Search

    Chew Pei Yi

    2010-01-01

    Wire bond process is the main area bringing the package into functionality as it plays the main role into connecting between chip and lead frame. Therefore, the main concern in this process is the bond ability and reliability of the process. This paper will mainly discuss on the remaining challenges of wafer fabrication technology towards wire bond process. Therefore, a

  13. Application of a wafer development process to mask making

    Microsoft Academic Search

    Gaston Lee; Celine Berger; Christian Burgel; Axel Feicke; Rusty Cantrell; Martin Tschinkl

    2005-01-01

    Recently, the design of integrated circuits has become more and more complicated due to higher circuit densities. In particular for logic applications, the design is no longer uniform but combines different kinds of circuits into one mask layout resulting in stringent criteria for both wafer and photomask manufacturing. Photomask CD uniformity control and defectivity are two key criteria in manufacturing

  14. Application of a wafer development process to mask making

    NASA Astrophysics Data System (ADS)

    Lee, Gaston; Berger, Celine; Burgel, Christian; Feicke, Axel; Cantrell, Rusty; Tschinkl, Martin

    2005-06-01

    Recently, the design of integrated circuits has become more and more complicated due to higher circuit densities. In particular for logic applications, the design is no longer uniform but combines different kinds of circuits into one mask layout resulting in stringent criteria for both wafer and photomask manufacturing. Photomask CD uniformity control and defectivity are two key criteria in manufacturing today"s high-end reticles, and they are both strongly impacted by the mask developing process. A new photomask develop tool (ACT-M) designed by Tokyo Electron Limited (TEL) has been installed at the Advanced Mask Technology Center (AMTC) in Dresden, Germany. This ACT-M develop tool is equipped with a standard NLD nozzle as well as an SH nozzle which are both widely used in wafer developing applications. The AMTC and TEL used the ACT-M develop tool to adapt wafer puddle develop technology to photomask manufacturing, in an attempt to capture the same optimum CD control enjoyed by the wafer industry. In this study we used the ACT-M develop tool to examine CD uniformity, local loading and defect control on P-CAR and N-CAR photomasks exposed with 50keV e-beam pattern generators. Results with both nozzle types are reported. CD uniformity, loading, and defectivity results were sufficient to meet 65-nm technology node requirements with these nozzles and tailored made develop recipes for photomask processing.

  15. Wafer yield prediction by the Mahalanobis-Taguchi system

    Microsoft Academic Search

    M. Asada

    2001-01-01

    The distribution of yield from the production lines is concentrated at a high-yield area and tapers down to the lower-yield area. Production management would find it useful if the yield of individual wafers could be forecast. The yield is determined by the variability of electrical characteristics and dust. In this study, only the variability of electrical characteristics was discussed. One

  16. Characteristics of PhotoMechanical Device Using PLZT Wafer

    Microsoft Academic Search

    Lei Liang; Shaoping Wang; Feng Cao

    2006-01-01

    In order to avoid electromagnetic disturbance, photostrictive ceramics becomes promising material to realize the optic-signal transmission and photostriction. This paper studies the dynamic characteristics of PLZT, investigates its optical bend and addresses its influence factors so as to provide the theoretical base of PLZT wafer for optical drive. Whereas the stretch of PLZT is only 1mum irradiated by ultraviolet light

  17. 2000-A\\/1-m? power MOSFETs in wafer repair technique

    Microsoft Academic Search

    M. Stoisiek; H. Schwarzbauer; W. Kiffe

    1990-01-01

    Power MOSFETs with a current capability of up to several thousand amperes and hence an active device area significantly exceeding the typical IC chip size can be realized only if a wafer repair technique is used. A suitable technique has been developed and used to realize circular power MOSFETs with a diameter of 3 cm. The devices are suited to

  18. Two-layer model for photomodulated thermoreflectance of semiconductor wafers

    E-print Network

    Mandelis, Andreas

    diagnostics in semiconducting wafers and several theoretical models have been developed in order to improve-layer model which can, in principle, be used for quantitative analysis of experimental data obtained from PMTR which considers plasma and thermal effects, in order to describe the behavior

  19. Electronic Defect and Contamination Monitoring in Si Wafers Using Spectrally Integrated Photocarrier Radiometry

    E-print Network

    Mandelis, Andreas

    boron-doped silicon wafers with iron concentration 1011 cm-3 on a baseline of 5 109 cm-3 have been electronic defects and contamination in silicon wafers is presented. Amplitude and phase imaging contrast. Available electronically February 21, 2006. Contamination and crystal defects in semiconductor wafers have

  20. Full-field wafer level thin film stress measurement by phase-stepping shadow Moire´

    Microsoft Academic Search

    Kuo-Shen Chen; Terry Yuan-Fang Chen; Chia-Cheng Chuang; I.-K. Lin

    2004-01-01

    A wafer topography measurement system has been designed and demonstrated based on shadow Moire´. Three-step phase-stepping and phase unwarping techniques are also incorporated to enhance the system resolution. Wafer curvatures or bows can be achieved by analyzing the Moire´ fringe patterns and film stress can be obtained subsequently by transforming this wafer curvature using a conversion equation such as Stoney's

  1. Durability and Survivability of Piezoelectric Wafer Active Sensors on Metallic Structure

    E-print Network

    Giurgiutiu, Victor

    Durability and Survivability of Piezoelectric Wafer Active Sensors on Metallic Structure Bin Lin,inexpensive,noninvasive,elasticwavegenerators/receptorsthatcanbe easily affixed to a structure. Piezoelectric wafer active sensor installation on the health with various environmental conditions on piezoelectric wafer active sensors for structural health monitoring

  2. Modeling of hydrophilic wafer bonding by molecular dynamics simulations David A. Litton and Stephen H. Garofalinia)

    E-print Network

    Garofalini, Stephen H.

    Modeling of hydrophilic wafer bonding by molecular dynamics simulations David A. Litton and Stephen for publication 31 December 2000 The role of moisture in hydrophilic wafer bonding was modeled using molecular Institute of Physics. DOI: 10.1063/1.1351538 I. INTRODUCTION Wafer bonding technology takes advantage

  3. Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests

    E-print Network

    Makris, Yiorgos

    Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests Ke of wafer-level measurements has recently attracted increased attention. Exist- ing approaches for capturing spatial correlation modeling of wafer- level analog/RF tests to handle such effects and, thereby

  4. Company Overview Negevtech is an innovative company specializing in high-resolution wafer inspection for

    E-print Network

    Adler, Joan

    Company Overview Negevtech is an innovative company specializing in high-resolution wafer inspection for controlling yields in semiconductor wafer processing. Founded in 2000 by prominent experts in electro-optics and image processing, Negevtech's mission is to bring a new look to IC wafer inspection

  5. Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs

    E-print Network

    Salama, Khaled

    Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs J Montopolis Drive, Austin TX 78741 Abstract -- Electrical and mechanical impacts of wafer bonding and thinning interconnect structures. This procedure permits evaluation of bonding and thinning integrity without inter-wafer

  6. Elsevier Science 1 Front-to back-side overlay optimization after wafer bonding for

    E-print Network

    Technische Universiteit Delft

    Elsevier Science 1 Front- to back-side overlay optimization after wafer bonding for 3D integration; accepted date here Abstract Wafer bonding consists in transferring the device to a new substrate, flipping a technique that makes possible to qualify the wafer bonding in order to know and realize the best achievable

  7. Improved Wafer-level Spatial Analysis for IDDQ Limit Setting Sagar Sabade D. M. H. Walker

    E-print Network

    Walker, Duncan M. "Hank"

    Improved Wafer-level Spatial Analysis for IDDQ Limit Setting Sagar Sabade D. M. H. Walker methodology for estimating the upper bound on the IDDQ of defect free chips by using wafer level spatial data. Such a methodology accounts for the change in IDDQ due to process variations across wafers

  8. wafer bonding approach allows point de-fects and potentially also waveguides to be

    E-print Network

    Zhuang, Xiaowei

    188 wafer bonding approach allows point de- fects and potentially also waveguides to be introduced parallel to the layers by proper lithography. In addition, wafer bonding can incorporate a layer that acts implica- tions? In principle, the combination of li- thography, etching, and wafer bonding could

  9. Multilevel nanoimprint lithography with submicron alignment over 4 in. Si wafers

    E-print Network

    Multilevel nanoimprint lithography with submicron alignment over 4 in. Si wafers Wei Zhanga that multilevel nanoimprint lithography NIL with submicron alignment over an entire 4 in. Si wafer can be achieved in ten consecutive tests of multilevel NIL. The multilevel alignment was achieved by aligning the wafer

  10. Theoretical calculation of the acoustic force on a patterned silicon wafer during megasonic cleaning

    E-print Network

    Deymier, Pierre

    Theoretical calculation of the acoustic force on a patterned silicon wafer during megasonic wafer immersed in water subjected to a megasonic beam. The method of calculation is based on a Green as a function of frequency and the angle the incident megasonic beam makes with the wafer surface

  11. Mechanically flexible thin-film transistors that use ultrathin ribbons of silicon derived from bulk wafers

    E-print Network

    Rogers, John A.

    wafers S. Mack, M. A. Meitl, A. J. Baca, Z.-T. Zhu, and J. A. Rogersa Department of Materials Science created by lithographic patterning and anisotropic etching of bulk silicon 111 wafers. Devices described top-down methods5­11 generate semicon- ductor wires, ribbons, and sheets from wafer based sources

  12. Supplemental Information for "Variations in properties of atomic force microscope cantilevers fashioned from the same wafer"

    E-print Network

    Chan, Derek Y C

    fashioned from the same wafer" Grant B. Webber1,2 , Geoffrey W. Stevens1 , Franz Grieser2 , Raymond R microscopy of 101 V-shaped cantilevers derived from the same wafer as received from the manufacturer by the thermal method and optical microscopy of 101 V-shaped cantilevers derived from the same wafer as received

  13. Silicon Wafer Transport in a High Vacuum, Microgravity Environment Nick Pfeiffer(1)

    E-print Network

    Chapman, Glenn H.

    Silicon Wafer Transport in a High Vacuum, Microgravity Environment Nick Pfeiffer(1) , Glenn H environment of space using silicon wafer substrates. Handling of these 37 g, 200 mm diameter by 0.5 mm thick are studying a system based upon magnetic levitation for the transport and fixturing of wafers in the orbital

  14. A Material Removal Model for CMP Based on the Contact Mechanics of Pad, Abrasives, and Wafer

    E-print Network

    Müftü, Sinan

    A Material Removal Model for CMP Based on the Contact Mechanics of Pad, Abrasives, and Wafer Dinçer, Massachusetts 02115, USA Applied pressure in chemical mechanical polishing CMP is shared by the two-body pad­wafer and the three-body pad­abrasive­ wafer contacts. The fraction of applied pressure transferred through

  15. Comparison of Wafer-level Spatial IDDQ Estimation Methods: NNR versus NCR Sagar S. Sabade*

    E-print Network

    Walker, Duncan M. "Hank"

    Comparison of Wafer-level Spatial IDDQ Estimation Methods: NNR versus NCR Sagar S. Sabade* D. M. H in IDDQ at the wafer level for estimating fault-free IDDQ of a chip are proposed. This paper compares two its sensitivity is a topic of research in recent years [1][2]. Several methods that use wafer

  16. FIELD-USABLE SHARPLESS WAFERS FOR JOSEPHSON EFFECT DEVICES AT MILLIMETER WAVES (*)

    E-print Network

    Boyer, Edmond

    195 FIELD-USABLE SHARPLESS WAFERS FOR JOSEPHSON EFFECT DEVICES AT MILLIMETER WAVES (*) J. EDRICH, Colorado 80302, USA Résumé. 2014 On montre comment des « Sharpless wafers » modifiés peuvent etre utilisés dommage. Abstract. 2014 It is shown how modified Sharpless wafers can be used for point contact Josephson

  17. Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand

    E-print Network

    Zelikovsky, Alexander

    Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand Andrew B. Kahng, Ion Mandoiu leads to dramatic increases in mask costs. In response to this trend, multiple project wafers (MPW) have in this context: reticle design under demand uncertainty and on- demand wafer dicing. Preliminary experiments

  18. A Progl-am for Simulation of Semiconductol-Wafer Fabrication

    E-print Network

    Resende, Mauricio G. C.

    A Progl-am for Simulation of Semiconductol- Wafer Fabrication 34auricio G.C. Resende Operation5 for discrete event simulation of a semiconductor wafer fab is presented, Jhclrogram is designed to serve This paper describes a C implementation of a simulation model of a semiconductor wafer fab. The program

  19. Characterization of Endpoint and Wafer Level Non-Uniformity using In-situ Thermography

    E-print Network

    Boning, Duane S.

    Characterization of Endpoint and Wafer Level Non-Uniformity using In-situ Thermography David White polish to extract spatial endpoint uniformity and polish rate uniformity across the wafer. IR images characteristics of wafer level polishing to be extracted from the thermal pad signatures [1,2,3]. Such in

  20. Scalable Wafer Bonding for Active Photonic Devices on Silicon John E. Bowersa

    E-print Network

    Bowers, John

    Scalable Wafer Bonding for Active Photonic Devices on Silicon John E. Bowersa , Hyundai Parka interest in low cost and high volume integration of photonic devices on silicon wafers. One of the main reasons is the possibility of integration of photonic and electronic devices on silicon wafers through

  1. Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques

    E-print Network

    Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques Gianni-insulator include SIMOX, Ge condensation and wafer bonding. In this paper, a brief introduction of each method is presented, with a detailed discussion of wafer bonding approaches for strained Si, SiGe, and Ge on

  2. Megasonic cleaning of wafers in electrolyte solutions: Possible role of electro-acoustic and cavitation effects

    E-print Network

    Deymier, Pierre

    Megasonic cleaning of wafers in electrolyte solutions: Possible role of electro Keywords: Wafer Cleaning Electrolyte Megasonic Electro-acoustic Cavitation Pressure amplitude a b s t r a c t Investigations have been conducted on the feasibility of removal of particles from silicon wafers in elec

  3. A custom computing solution to automated visual inspection of silicon wafers

    E-print Network

    A custom computing solution to automated visual inspection of silicon wafers Peter Athanas, Lynn discontinuities on silicon wafer surfaces. The discontinuities typically manifest themselves as minute scratches, fissures, or fractures. #12;2. SILICON WAFER INSPECTION The inspection task examined here relates

  4. Integration of Self-Assembled Three-Dimensional Photonic Crystals onto Structured Silicon Wafers

    E-print Network

    Jonsson, Fredrik

    Integration of Self-Assembled Three-Dimensional Photonic Crystals onto Structured Silicon Wafers silica spheres (diameter of 890 nm), self-assembled in hydrophilic trenches of silicon wafers by using a spatial selectivity of opal crystallization without special treatment of the wafer surface, a filling

  5. Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers for PV Cells

    SciTech Connect

    Guthrey, H.; Gorman, B.; Al-Jassim, M.

    2011-01-01

    As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay ({mu}PCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

  6. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  7. Electrical characterization of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Kang, Sunggun

    Silicon-on-Insulator (SOI) metal oxide semiconductor field effect transistors (MOSFET) have become a common subject in the semiconductor community due to enhanced performance such as simple processing, excellent scalability, sharp subthreshold characteristics, minimum short-channel effects, and reduced hot electron degradation. Since these films are used for devices, it is necessary to know the SOI film quality with simple and nondestructive methods. In this study, surface photovoltage (SPV) measurements, pseudo-MOSFET characterization, and capacitance-voltage (C-V) are used. Literature review and simulations show that material properties of SOI wafers can have significant effects on the device and circuit performance such as floating body effects, switching speed, leakage current, and noise characteristics. SPV results show the surface charges of SOI wafers to increase with frequency in the low frequency region, with several interface components acting in opposing directions. Iron contaminated wafers show increased surface charges due to a high density of interface states. The efficacy of surface passivation is clearly shown by measuring the effective generation lifetime as a function of time after applying the liquid to the pseudo-MOSFET surface. A more controlled method is the additional top gate controlling either the upper or lower silicon film surface, separately. C-V measurements for some SOI wafers show a leaky buried oxide (BOX) and high density of interface states. SOI wafers can exhibit quite different breakdown voltage before and after removing the Si layer, indicating that the gate current flows through weaker current paths in the BOX beyond the gate area. Transmission electron microscopy (TEM) images display smooth interfaces and a clean BOX, regardless of the breakdown voltage.

  8. Wafer-level packaging with compression-controlled seal ring bonding

    DOEpatents

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  9. Height inspection of wafer bumps without explicit 3D reconstruction

    NASA Astrophysics Data System (ADS)

    Dong, Mei; Chung, Ronald; Zhao, Yang; Lam, Edmund Y.

    2006-02-01

    The shrunk dimension of electronic devices leads to more stringent requirement on process control and quality assurance of their fabrication. For instance, direct die-to-die bonding requires placement of solder bumps not on PCB but on the wafer itself. Such wafer solder bumps, which are much miniaturized from the counterparts on PCB, still need to have their heights meet the specification, or else the electrical connection could be compromised, or the dies be crushed, or even the manufacturing equipments be damaged. Yet the tiny size, typically tens of microns in diameter, and the textureless and mirror nature of the bumps pose great challenge to the 3D inspection process. This paper addresses how a large number of such wafer bumps could have their heights massively checked against the specification. We assume ball bumps in this work. We propose a novel inspection measure about the collection of bump heights that possesses these advantages: (1) it is sensitive to global and local disturbances to the bump heights, thus serving the bump height inspection purpose; (2) it is invariant to how individual bumps are locally displaced against one another on the substrate surface, thus enduring 2D displacement error in soldering the bumps onto the wafer substrate; and (3) it is largely invariant to how the wafer itself is globally positioned relative to the imaging system, thus having tolerance to repeatability error in wafer placement. This measure makes use of the mirror nature of the bumps, which used to cause difficulty in traditional inspection methods, to capture images of two planes. One contains the bump peaks and the other corresponds to the substrate. With the homography matrices of these two planes and fundamental matrix of the camera, we synthesize a matrix called Biplanar Disparity Matrix. This matrix can summarize the bumps' heights in a fast and direct way without going through explicit 3D reconstruction. We also present a design of the imaging and illumination setup that allows the measure to be revealed in two images, and how the inspection measure could be estimated from the image data so acquired. Both synthetic and real data experimental results are shown to illustrate the effectiveness of the proposed system.

  10. Measurement and modeling of time- and spatial-resolved wafer surface temperature in inductively coupled plasmas

    SciTech Connect

    Hsu, C. C.; Titus, M. J.; Graves, D. B. [Department of Chemical Engineering, University of California at Berkeley, Berkeley, California 94720 (United States)

    2007-05-15

    The transient temperature profile across a commercial wafer temperature sensor device in an inductively coupled Ar plasma is reported. The measured temperatures are compared to model predictions, based on a coupled plasma-wafer model. The radial temperature profile is the result of the radial profile in the ion energy flux. The ion energy flux profile is obtained by combining the Langmuir probe measurement, the ion wall flux probe measurement, and a plasma model. A methodology to estimate the ion flux profile using the sensor measurements has been validated by combining the plasma measurements, the wafer temperature measurements, and the plasma-wafer model. It is shown that with minimal heat transfer between the wafer and the chuck, the initial transient wafer temperature profile after plasma ignition can be used to estimate the ion energy flux profile across the wafer.

  11. Design of Single-Wafer Furnace and Its Rapid Thermal Processing Applications

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kuribayashi, Hiromitsu; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-11-01

    A resistively heated, vacuum- and atmospheric-pressure-compatible, single-wafer furnace (SWF) system is designed to improve the operational flexibility of conventional furnaces and the productivity of single-wafer rapid thermal processing (RTP) systems. The heat source design and system operation concepts are described. The temperature measurement/control techniques and thermal characteristics of the heat source are described. The heat transfer mechanism between the heat source and Si wafer is discussed. Temperature and process uniformity in SWF were demonstrated in TiSi formation, implant annealing and thin-oxide formation. The defect-generation phenomenon in Si wafers during atmospheric pressure RTP in a SWF system is investigated as a function of temperature, process time, wafer handling method and speed. Highly repeatable slip-free RTP results were achieved in 200-mm-diameter Si wafers processed at 1100°C for 60 s (up to 5 times) through the optimization of the wafer handling method and speed.

  12. Influence of the bonding front propagation on the wafer stack curvature

    SciTech Connect

    Navarro, E. [SOITEC—Parc Technologique des Fontaines, 38190 Bernin (France); SIMaP—Grenoble-INP, 1340 rue de la Piscine, 38402 St. Martin d'Hères (France); Bréchet, Y. [SIMaP—Grenoble-INP, 1340 rue de la Piscine, 38402 St. Martin d'Hères (France); Barthelemy, A.; Radu, I. [SOITEC—Parc Technologique des Fontaines, 38190 Bernin (France); Pardoen, T. [Institute of Mechanics, Materials and Civil Engineering (iMMC), Université catholique de Louvain, B-1348 Louvain-la-Neuve (Belgium); Raskin, J.-P. [Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM), Université catholique de Louvain, B-1348 Louvain-la-Neuve (Belgium)

    2014-08-11

    The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

  13. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    SciTech Connect

    Daix, N., E-mail: dai@zurich.ibm.com; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J. [IBM Research - Zürich, Säumerstrasse 4, CH-8803 Rüschlikon (Switzerland); Hartmann, J. M. [CEA, LETI 17, rue des Martyrs, F-38054 Grenoble (France); Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D. [IBM T. J. Watson Research Center, 1101 Kitchawan Rd., Route 134 Yorktown Heights, New York 10598 (United States)

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup ?2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  14. Elevated temperature tensile\\/creep test of UV-LIGA nickel thin film for design of high-density micro connector

    Microsoft Academic Search

    Yoshitada Isono; Junichi Tada; T. Watanabe; TosFnori Unno; Toshiyuki Toriyama; Susumu Sugiyama

    2003-01-01

    This paper describes mechanical properties of UV-LIGA Ni films at elevated temperatures for design of a high-density micro connector. A compact tensile tester operated under a scanning probe microscope (SPM) was newly developed, and it characterized a stress-strain relation and creep behavior of the Ni films at temperatures ranging from 300 K to 573 K. 600 ?m-long, 15 ?m-thick and

  15. DoseSim: Microsoft-Windows graphical user interface for using synchrotron x-ray exposure and subsequent development in the LIGA process

    Microsoft Academic Search

    P. Meyer; J. Schulz; L. Hahn

    2003-01-01

    The LIGA process, which combines x-ray lithography with electroplating and moulding, is a technique used worldwide for the fabrication of high aspect ratio microstructures. In the first step (x-ray lithography), a resist layer is applied to a metal-coated substrate, which is then patterned by shadow printing through an x-ray mask with synchrotron radiation. The second step consists in dissolving the

  16. New formation technology for a plasma display panel barrier-rib structure using a precise metal mold fabricated by the UV-LIGA process

    NASA Astrophysics Data System (ADS)

    Son, Seung-Hyun; Park, Yong-Suk; Choi, Sie-Young

    2002-01-01

    We present a new formation technology for a plasma display panel (PDP) barrier-rib structure by which we can obtain a barrier-rib with a high aspect ratio and reduce the manufacturing cost. Firstly, a precise metal mould is manufactured for massively replicating the PDP barrier-rib construction using the UV-LIGA process with a thick negative photoresist (SU-8 50: Microchem Corp). The proposed sequence includes several processes: amorphous silicon as an adhesion layer; dipping into xylene and n-butyl acetate after the development of SU-8; two step removal of the SU-8 layer; rip-off process, etc. The proposed processes produce a copper mould with a high aspect ratio, good surface roughness and a uniform thickness. Secondly, a PDP barrier-rib structure is formed using the roll-pressing method with a reusable metal mould fabricated by the proposed UV-LIGA process. This is a very simple and inexpensive method consisting of printing the barrier-rib paste, drying, roll-pressing and firing. Consequently, by combining the UV-LIGA and roll-pressing processes, the desired barrier-rib shapes can be made with a high aspect ratio and various dimensions. The combination of the UV-LIGA and roll-pressing processes also demonstrates the possibility of achieving two major goals in the barrier-rib processes; i.e., developing a barrier-rib structure with a high aspect ratio that can be applied to high-definition televisions, and reducing the manufacturing cost.

  17. Abstract--Novel technologies like substrate transfer technology can introduce severe topography on otherwise flat silicon wafers.

    E-print Network

    Technische Universiteit Delft

    on otherwise flat silicon wafers. Since optical lithography is usually performed on ultra flat wafers, the alignment system is not optimized for high topography wafers. In this work, an experimental procedure is presented to measure the alignment offset of an ASML PAS5000/50 waferstepper on high topography wafers

  18. Influence of gas composition on wafer temperature in a tungsten chemical vapor deposition reactor: Experimental measurements, model

    E-print Network

    Rubloff, Gary W.

    Influence of gas composition on wafer temperature in a tungsten chemical vapor deposition reactor 13 April 2000; accepted 23 October 2000 Experimental measurements of wafer temperature in a single-wafer, lamp-heated chemical vapor deposition system were used to study the wafer temperature response to gas

  19. USING VARIATION DECOMPOSITION ANALYSIS TO DETERMINE THE EFFECT OF PROCESS ON WAFER-AND DIE-LEVEL UNIFORMITY IN

    E-print Network

    Boning, Duane S.

    USING VARIATION DECOMPOSITION ANALYSIS TO DETERMINE THE EFFECT OF PROCESS ON WAFER- AND DIE an understanding of the trade-offs in wafer and die-level uniformity, and their interaction, as functions the measured variation into wafer, die, wafer-die interaction and residual components, we have determined

  20. Wafer-bonded single-crystal silicon slot waveguides and ring resonators Ryan M. Briggs,a

    E-print Network

    Atwater, Harry

    Wafer-bonded single-crystal silicon slot waveguides and ring resonators Ryan M. Briggs,a Michael by bonding thin Si-on-insulator wafers. After removing the Si substrate and buried oxide from one side process uses room-temperature covalent wafer bonding to transfer the Si device layer of a SOI wafer onto

  1. Block-level Designs of Die-to-Wafer Bonded 3D ICs and Their Design Quality Tradeoffs

    E-print Network

    Lim, Sung Kyu

    Block-level Designs of Die-to-Wafer Bonded 3D ICs and Their Design Quality Tradeoffs Krit the footprint of the dies in the stack are different. This happens in case of die-to-wafer bonding, which for the dies that have the identical footprint. The main motivation behind this is to allow wafer- to-wafer

  2. Photostimulated near-infrared persistent luminescence as a new optical read-out from Cr3+-doped LiGa5O8

    PubMed Central

    Liu, Feng; Yan, Wuzhao; Chuang, Yen-Jun; Zhen, Zipeng; Xie, Jin; Pan, Zhengwei

    2013-01-01

    In conventional photostimulable storage phosphors, the optical information written by x-ray or ultraviolet irradiation is usually read out as a visible photostimulated luminescence (PSL) signal under the stimulation of a low-energy light with appropriate wavelength. Unlike the transient PSL, here we report a new optical read-out form, photostimulated persistent luminescence (PSPL) in the near-infrared (NIR), from a Cr3+-doped LiGa5O8 NIR persistent phosphor exhibiting a super-long NIR persistent luminescence of more than 1,000?h. An intense PSPL signal peaking at 716?nm can be repeatedly obtained in a period of more than 1,000?h when an ultraviolet-light (250–360?nm) pre-irradiated LiGa5O8:Cr3+ phosphor is repeatedly stimulated with a visible light or a NIR light. The LiGa5O8:Cr3+ phosphor has promising applications in optical information storage, night-vision surveillance, and in vivo bio-imaging. PMID:23532003

  3. Denuded zone in Czochralski silicon wafer with high carbon content

    NASA Astrophysics Data System (ADS)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

    2006-12-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

  4. Single Wafer Furnace and Its Thermal Processing Applications

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kuribayashi, Hiromitsu; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-07-01

    A resistively heated, vacuum and atmospheric pressure compatible, single wafer furnace (SWF) system is proposed to improve operational flexibility of conventional furnaces and productivity of single wafer rapid thermal processing (RTP) systems. The design concept and hardware configuration of the SWF system are described. The temperature measurement/control techniques and thermal characteristics of the SWF system are described. Typical process results in TiSi formation, implant anneal and thin oxide formation using the SWF system are reported. Due to the vertically stacked, dual chamber configuration and steady state temperature control, very flexible operation with a high throughput at a minimal power consumption (<3.5 kW per process chamber at 1150°C) was realized. Many thermal processes used in furnaces and RTP systems can easily be converted to SWF processes without decreasing cost performance and/or deteriorating process results by using the SWF system.

  5. Slumping of Si wafers at high temperature

    NASA Astrophysics Data System (ADS)

    Mika, M.; Jankovsky, O.; Simek, P.; Lutyakov, O.; Havlikova, R.; Sofer, Z.; Hudec, R.; Pina, L.; Inneman, A.; Sveda, L.; Marsikova, V.

    2013-05-01

    Space X-ray imaging telescopes have delivered unique observations that have been significantly contributing to many important discoveries of current astrophysics. For future telescopes with a larger collecting area and a better angular resolution, the limiting factor is their X-ray reflecting mirror array. Therefore, for a successful construction of future lightweight and highly reflecting X-ray mirrors, new cost-effective technologies and progressive materials are needed. Currently, the very promising materials are silicon foils which are commercially produced on a large scale. We focused on the plastic deformation of thin monocrystalline silicon foils, which was necessary for the precise thermal forming of the foils to 3D shapes. To achieve the plastic deformation, we applied forced slumping at temperatures from 1200 to 1400°C. The final shapes and the surface quality of the foils were measured using a Taylor Hobson contact profilometer and examined with an Atomic Forced Microscopy. We studied the effects of temperature, applied slumping force, heattreatment time, crystal orientation, and furnace atmosphere on the shape and surface quality of the formed foils.

  6. Electrophoretic Photoresist Application for High Topography Wafer Surfaces

    Microsoft Academic Search

    James Tajadod; Henry Hendriks; John Klocke; Antonio Morales; Heather Rapuano

    As wafer surfaces become topographically more challenging, achieving uniform resist coatings in deep vias, over high mesas, and three-dimensional (3-D) features may no longer be possible using conventional, solvent based, spin-coated liquid photoresist (LPR). Thinning of the resist on the high areas and pooling of the resist in the deep areas are common problems. Electrophoretic photoresist (EPR) may be used

  7. White beam topography of 300 mm Si wafers

    Microsoft Academic Search

    A. N. Danilewsky; J. Wittgea; A. Rack; T. Weitkamp; R. Simon; T. Baumbach; P. McNally

    2008-01-01

    Synchrotron X-ray topography is well suited for a detailed characterisation of the real structure of single crystals and devices\\u000a based on single crystalline materials. The nature and distribution of dislocations, stacking faults, inclusions etc. as well\\u000a as long range strain from processing are of high interest especially in semiconductor wafers and electronic devices. To overcome\\u000a the limitations of the classical

  8. Micromachined planar inductors on silicon wafers for MEMS applications

    Microsoft Academic Search

    Chong H. Ahn; Mark G. Allen

    1998-01-01

    This paper describes three micromachined planar inductors (a spiral type, a solenoid type, and a toroidal meander type) with electroplated nickel-iron permalloy cores which have been realized on a silicon wafer using micromachining techniques. The electrical properties among the fabricated inductors are compared and the related fabrication issues are discussed, with emphasis on the low-temperature CMOS-compatible process, the high current-carrying

  9. Performance limiting micropipe defects in silicon carbide wafers

    Microsoft Academic Search

    Philip G. Neudeck; Anthony J. Powell

    1994-01-01

    Reports on the characteristics of a major defect in mass-produced silicon carbide wafers which severely limits the performance of silicon carbide power devices. Micropipe defects originating in 4H- and 6H-SiC substrates were found to cause pre-avalanche reverse-bias point failures in most epitaxially-grown pn junction devices of 1 mm2 or larger in area. Until such defects are significantly reduced from their

  10. Three-dimensional shared memory fabricated using wafer stacking technology

    Microsoft Academic Search

    K. W. Lee; T. Nakamura; T. Ono; Y. Yamada; T. Mizukusa; H. Hashimoto; K. T. Park; H. Kurino; M. Koyanagi

    2000-01-01

    We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the

  11. Adhesive wafer bonding with photosensitive polymers for MEMS fabrication

    Microsoft Academic Search

    Erkan Cakmak; Viorel Dragoi; Elliott Capsuto; Craig McEwen; Eric Pabo

    2010-01-01

    Adhesive wafer bonding is a technique that uses an intermediate layer (typically a polymer) for bonding two substrates. The\\u000a main advantages of using this approach are: low temperature processing (maximum temperatures lower than 400°C), surface planarization\\u000a and tolerance to particles contamination (the intermediate layer can incorporate particles with the diameter in the layer\\u000a thickness range). The main bonding layers properties

  12. On-wafer calibration using space-conservative (SOLT) standards

    Microsoft Academic Search

    M. Imparato; T. Weller; L. Dunleavy

    1999-01-01

    In this paper the accuracy of on-wafer calibration using space-conservative (SOLT) standards is evaluated. The calibration approach relies on measurement-based standard definitions. Results are presented using CPW standards with 50 and 300 micron offsets, over the range from .045-65 GHz. In comparing to a multi-line TRL, the magnitude of the difference between the S-parameters is less than 0.05 up to

  13. Sputter deposition of SiC coating on silicon wafers

    NASA Technical Reports Server (NTRS)

    Robson, M. T.; Blue, C. A.; Warrier, S. G.; Lin, R. Y.

    1992-01-01

    A study is conducted of the effect of substrate temperature during coating on the properties of coated SiC films on Si wafers, using a scratch test technique. While specimen temperature during coating has little effect on deposition rate, it significantly affects the durability of the coating. Scratch test damage to both film coating and substrate decreased with increasing deposition temperature, perhaps due to the rapid diffusion of the deposited atoms.

  14. Influence of plasma treatment and cleaning on vacuum wafer bonding

    Microsoft Academic Search

    Wei Bo Yu; Cher Ming Tan; Jun Wei; Shu Sheng Deng; Mui Ling Nai

    2003-01-01

    Direct wafer bonding was performed in vacuum. We compared two kinds of bonding, Si to Si and Si to SiO2, in three different circumstances: Bonded in vacuum only, bonded in vacuum after plasma treatment and bonded in vacuum after plasma treatment and RCA1 cleaning. From the comparison of the bonding strength, we found that in both cases, Si-Si and Si-SiO2,

  15. Electrooptic wafer beam deflector in LiTaO3

    Microsoft Academic Search

    Jun Li; Hsing C. Cheng; Matthew J. Kawas; David N. Lambeth; T. E. Schlesinger; Daniel D. Stancil

    1996-01-01

    A novel electrooptic beam deflector is reported based on ferroelectric domain inversion extending through the thickness of a Z-cut LiTaO3 wafer. The selective domain inversion is achieved by electric-field poling assisted by proton exchange, rather than proton exchange followed by rapid thermal annealing. The deflection sensitivity of the device was measured to be 5.0 mrad\\/KV. This is 93% of the

  16. Surface micromachined tunable resonant cavity LED using wafer bonding

    Microsoft Academic Search

    Gina L. Christenson; Alex T. Tran; Zuhua Zhu; Yu-Hwa Lo; Minghwei Hong; J. P. Mannaerts; Rajaram J. Bhat

    1997-01-01

    Surface micromachining and wafer bonding techniques have been integrated to fabricate a dual-use resonant cavity tunable LED\\/photodetector operating at 1.5 micrometers . The device has a tuning range of 75 nm, and a spectral linewidth of 4 nm, with an extinction ratio of greater than 20 dB throughout the tuning range. The device has potential applications in WDM networks and

  17. Capacitive micromachined ultrasonic transducers with through-wafer interconnects

    Microsoft Academic Search

    Xuefeng Zhuang

    2008-01-01

    Capacitive micromachined ultrasonic transducer (CMUT) is a promising candidate for making ultrasound transducer arrays for applications such as 3D medical ultrasound, non-destructive evaluation and chemical sensing. Advantages of CMUTs over traditional piezoelectric transducers include low-cost batch fabrication, wide bandwidth, and ability to fabricate arrays with broad operation frequency range and different geometric configurations on a single wafer. When incorporated with

  18. Stress measurement of thin wafer using reflection grating method

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand K.

    2010-08-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this research, the system is calibrated with reference to stress measurement equipment from KLA-Tencor. Some initial results based on a joint project with Infineon Technologies are re-examined. The stress distribution of the wafers are derived with the aid of Stoney's equation. Finally, the results from our proposed system are compared and contrasted with data obtained from KLA-Tencor equipment.

  19. Wafer inspection as alternative approach to mask defect qualification

    NASA Astrophysics Data System (ADS)

    Holfeld, Christian; Katzwinkel, Frank; Seifert, Uwe; Mothes, Andreas; Peters, Jan Hendrik

    2007-10-01

    Defect inspection is one of the major challenges in the manufacturing process of photomasks. The absence of any printing defect on patterned mask is an ultimate requirement for the mask shop, and an increasing effort is spent in order to detect and subsequently eliminate these defects. Current DUV inspection tools use wavelengths five times or more larger than the critical defect size on advanced photomasks. This makes the inspectability of high-end mask patterns (including strong OPC and small SRAF's) and sufficient defect sensitivity a real challenge. The paper evaluates the feasibility of inspecting the printed wafer as an alternative way for the high-sensitivity defect inspection of photomasks. Defects originating in the mask can efficiently be filtered as repeated defects in the various dies on wafer. Using a programmed-defect mask of 65-nm technology, a reliable detection of the printing defects was achieved with an optimized inspection process. These defects could successfully be traced back to the photomask in a semi-automated process in order to enable a following repair step. This study shows that wafer inspection is able to provide a full defect qualification of advanced photomasks with the specific advantage of assessing the actual printability of arbitrary defects.

  20. Gate-Oxide-Integrity Characteristics of Vacancy-rich Wafer Compared with Crystal-Originated-Pits-free Wafer as a Function of Oxide Thickness

    NASA Astrophysics Data System (ADS)

    Lee, Ki-Sang; Cho, Won-Ju; Lee, Bo-Young; Yoo, Hak-Do

    2000-07-01

    The dielectric breakdown of oxides with various thickness between 5-70 nm on Czochralski (CZ)-grown silicon wafer had been investigated. To observe the effects of crystal-originated-particle (COP), vacancy-rich wafers and COP-free wafers were compared. In breakdown voltage (BV) measurement, breakdown fractions of vacancy-rich wafers were increased with the increase of oxide thickness (tOX) and showed a maximum value at the tOX range of 10-20 nm. On the other hand, COP-free wafers showed few breakdowns over all the range of tOX. Furthermore, time dependent dielectric breakdown (TDDB) of the vacancy-rich wafers showed higher extrinsic breakdowns than that of the COP-free wafers in the tOX below 20 nm. For the intrinsic breakdown, two groups showed the same charge-to-breakdown (QBD) along the strength of injection current over all the range of tOX. Especially, only in case of vacancy-rich wafer, abnormal increase of current, i.e., hump phenomena, was observed in the range of electric field below the Fowler-Nordheim (F-N) tunneling.

  1. Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers

    E-print Network

    Salama, Khaled

    Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive advantage of copper-to-copper (Cu-to-Cu) bonding with the increased adhesion strength and robustness of dielectric adhesive bonding using benzocyclobutene (BCB) is discussed. Critical processing challenges

  2. Penetration of plasma into the wafer-focus ring gap in capacitively coupled plasmas

    SciTech Connect

    Babaeva, Natalia Y.; Kushner, Mark J. [Iowa State University, Department of Electrical and Computer Engineering, 104 Marston Hall, Ames, Iowa 50011 (United States)

    2007-06-01

    In plasma etching equipment for microelectronics fabrication, there is an engineered gap between the edge of the wafer and wafer terminating structures, such as focus rings. The intended purpose of these structures is to make the reactant fluxes uniform to the edge of the wafer and so prevent a larger than desired edge exclusion where useful products cannot be obtained. The wafer-focus ring gap (typically<1 mm) is a mechanical requirement to allow for the motion of the wafer onto and off of the substrate. Plasma generated species can penetrate into this gap and under the beveled edge of the wafer, depositing films and possibly creating particles which produce defects. In this paper, we report on a computational investigation of capacitively coupled plasma reactors with a wafer-focus ring gap. The penetration of plasma generated species (i.e., ions and radicals) into the wafer-focus ring gap is discussed. We found that the penetration of plasma into the gap and under the wafer bevel increases as the size of the gap approaches and exceeds the Debye length in the vicinity of the gap. Deposition of, for example, polymer by neutral species inside the gap and under the wafer is less sensitive to the size of the gap due the inability of ions, which might otherwise sputter the film, to penetrate into the gap.

  3. Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

    NASA Astrophysics Data System (ADS)

    Turner, K. T.; Vukkadala, P.; Veeraraghavan, S.; Sinha, J. K.

    2014-04-01

    Controlling overlay errors resulting from wafer processing, such as film deposition, is essential for meeting overlay budgets in future generations of devices. Out-of-plane distortions induced on the wafer due to processing are often monitored through high-resolution wafer geometry measurements. While such wafer geometry measurements provide information about the wafer distortion, mechanics models are required to connect such measurements to overlay errors, which result from in-plane distortions. The aim of this paper is to establish fundamental connections between the out-ofplane distortions that are characterized in wafer geometry measurements and the in-plane distortions on the wafer surface that lead to overlay errors. First, an analytical mechanics model is presented to provide insight into the connection between changes in wafer geometry and overlay. The analytical model demonstrates that the local slope of the change in wafer shape induced by the deposition of a residually stressed film is related to the induced overlay for simple geometries. Finite element modeling is then used to consider realistic wafer geometries and assess correlations between the local slope of the wafer shape change induced by the deposition of a stressed film and overlay. As established previously, overlay errors only result when the stresses in the film are non-uniform, thus the finite element study considers wafers with several different nonuniform residual stress distributions. Correlation between overlay and a metric based on a corrected wafer slope map is examined. The results of the modeling and simulations are discussed and compared to recently published experimental results.

  4. Highly uniform growth of 2-inch GaN wafers with a multi-wafer HVPE system

    NASA Astrophysics Data System (ADS)

    Liu, Nanliu; Wu, Jiejun; Li, Wenhui; Luo, Ruihong; Tong, Yuzhen; Zhang, Guoyi

    2014-02-01

    A new nozzle structure was developed in an improved multi-wafer hybrid vapor phase epitaxy (IHVPE) system by adding an inner dilution gas (ID) pipe between V and III groups gas channels. Experimental results showed that the thickness distribution of 2-inch GaN layer depended strongly on the flow rate of ID gas. The uniformity of film can arrive at ±3-4% by optimizing ID gas, which was better than that of ±30% grown in the old conventional multi-wafer hybrid vapor phase epitaxy (CHVPE) system. Meanwhile, the crystal quality and surface morphology were also greatly improved for GaN film by using the new reactor structure. The FWHM values of (002) and (102) were reduced from 342? and 806? to 207? and 254?, respectively. AFM result of surface roughness (RMS, 10 ?m×10 ?m) of GaN layer was also lowered from 1.226 nm to 0.798 nm. It was partly because of the suppression of parasitic polycrystalline deposition due to the ID gas. This simple and economic method could provide an effective solution to simultaneously fabricate multiple GaN wafer with good thickness uniformity, high crystal quality and low cost.

  5. Innovative imaging technology opens new horizon to wafer inspection for advanced DRAM products

    Microsoft Academic Search

    M. Richter; C. Mata; A. Gratch; C. Fouquet

    2004-01-01

    Automated optical wafer inspection was introduced in the beginning of 90's when wafer fabrication entered the 200 mm wafer and sub-micron processing era in order to perform yield monitoring during ramp-up and volume production. Two technologies, Brightfield (BF) and Darkfield (DF) were adapted by the semiconductor industry. However, their evolution rapidly lagged behind the stringent demand for increased sensitivity at

  6. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

    1979-01-01

    A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

  7. Contactless determination of the carrier mobility sum in silicon wafers using combined photoluminescence and photoconductance measurements

    NASA Astrophysics Data System (ADS)

    Hameiri, Ziv; Rougieux, Fiacre; Sinton, Ron; Trupke, Thorsten

    2014-02-01

    A contactless method to determine the carrier mobility sum in silicon wafers, based on a comparison between photoluminescence and photoconductance measurements is presented. The method is applied to monocrystalline silicon wafers and the results are found to be in good agreement with well-established mobility models and another measurement method. The potential of the proposed method to determine the carrier mobility sum of multicrystalline and compensated silicon wafers is then demonstrated.

  8. Kerf-free wafering: Technology overview and challenges for thin PV manufacturing

    Microsoft Academic Search

    Francois J. Henley

    2010-01-01

    Eliminating high absorber material loss while allowing thin and ultra-thin crystalline silicon PV has been a “Holy Grail” of the crystalline silicon PV industry for decades. Generally called “kerf-free wafering”, the fundamental approach is to substitute slurry saws with an alternative waste-free wafering technology. Ideally, the technology would also eliminate the difficulty to process thin to ultra-thin wafers inherent to

  9. Plasma-assisted InP-to-Si low temperature wafer bonding

    Microsoft Academic Search

    Donato Pasquariello; Klas Hjort

    2002-01-01

    The applicability of wafer bonding as a tool to integrate the dissimilar material system InP-to-Si is presented and discussed with recent examples of InP-based optoelectronic devices on Si. From there, the lowering of annealing temperature in wafer bonding by plasma-assisted bonding is the essence of this review paper. Lower annealing temperatures would further launch wafer bonding as a competitive technology

  10. An improved calibration technique for on-wafer large-signal transistor characterization

    Microsoft Academic Search

    Andrea Ferrero; Umberto Pisani

    1993-01-01

    The on-wafer measurement of complex quantities and absolute power levels of active devices is truly significant for nonlinear device characterization and modeling. An original procedure, which allows one to perform both the vector and the power calibrations at the RF wafer probe tips used for on-wafer measurement of two-port devices, is presented. The measurement system is based on an automatic

  11. Resonance Ultrasonic Vibrations for in-line crack detection in silicon wafers and solar cells

    Microsoft Academic Search

    A. Monastyrskyi; S. Ostapenko; O. Polupan; H. Maeckel; M. A. Vazquez

    2008-01-01

    The Resonance Ultrasonic Vibrations (RUV) technique was developed for in-line non-destructive crack detection in full-size silicon wafers and solar cells. The RUV methodology relies on deviation of the resonance frequency response curve measured on a wafer with peripheral or bulk millimeter-length crack and on identical non-cracked wafers. Three RUV frequency curve crack detection criteria were identified: (1) shift of the

  12. Wafer-level hermetic packaged microaccelerometer with fully differential BiCMOS interface circuit

    Microsoft Academic Search

    Hyoungho Ko; Sangjun Park; Byoungdoo Choi; Ahra Lee; Dong-il “Dan” Cho

    2007-01-01

    This paper presents a microaccelerometer with wafer-level packaged MEMS sensing element with fully differential, continuous-time BiCMOS interface circuit. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the sacrificial bulk micromachining (SBM) process. To protect the silicon structure of the sensing element and to enhance the reliability, a wafer level hermetic packaging process is achieved, using

  13. A Material Removal Model for CMP Based on the Contact Mechanics of Pad, Abrasives, and Wafer

    Microsoft Academic Search

    Dinc?er Bozkaya; Sinan Mu?ftu?

    2009-01-01

    Applied pressure in chemical mechanical polishing CMP is shared by the two-body pad-wafer and the three-body pad-abrasive- wafer contacts. The fraction of applied pressure transferred through the particle contacts is a significant factor as most of the material removal is due to abrasive particles trapped in the pad-wafer interface. In this work, the contact of a rough, deformable pad and

  14. Determination of wafer center position during the transfer process by using the beam-breaking method

    NASA Astrophysics Data System (ADS)

    Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

    2014-09-01

    A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human-machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions.

  15. The optimization of CD uniformity and measurement on mask and wafer

    NASA Astrophysics Data System (ADS)

    Choi, Yongkyoo; Kim, Munsik; Han, Oscar

    2007-05-01

    As pattern size is shrinking, required mask CD specification is tighter and its effect on wafer patterning is more severe. To enhance the device performance, wafer CD uniformity should be enhanced and controlled by mask global CD uniformity. Mask global CD uniformity usually can be enhanced by mask process and optimal fogging effect correction. To enhance the mask global CD uniformity on mask, resist process and FEC (Fogging Effect Correction), reliable CD measurement tool and methods are necessary. Recently, group CD using OCD(Spectroscopic Ellipsometer) or AIMS(Aerial Image Measurement and Simulation) is used to represent global CD variation on mask. These methods are removing local CD variation on mask. Because local CD variation on wafer is large compared with the effect of local CD variation of mask, global CD uniformity can be measured with suppressed local CD variation [1]. In this paper, local CD variation of mask and wafer is evaluated, and area CD and smoothing methods are used to measure CD on mask and wafer, and the correlation of global CD of mask and field CD of wafer are evaluated. By these methods, CD measurement repeatability can be enhanced to get closer correlation of mask and wafer. Close correlation makes fine CD correction on mask to get better field CD uniformity on wafer. And the repeatability of field to field CD uniformity of wafer is evaluated according to measurement tool of CD-SEM and scatterometry.

  16. A practical approach to LWIR wafer-level optics for thermal imaging systems

    NASA Astrophysics Data System (ADS)

    Symmons, Alan; Pini, Ray

    2013-06-01

    The development and implementation of wafer level packaging for commercial microbolometers has opened the pathway towards full wafer-based thermal imaging systems. The next challenge in development is moving from discrete element LWIR imaging systems to a wafer based optical system, similar to lens assemblies found in cell phone cameras. This paper will compare a typical high volume thermal imaging design manufactured from discrete lens elements to a similar design optimized for manufacture through a wafer based approach. We will explore both performance and cost tradeoffs as well as review the manufacturability of all designs.

  17. How accurate are rapid prototyped (RP) final orthognathic surgical wafers? A pilot study.

    PubMed

    Shqaidef, Abedalrahman; Ayoub, Ashraf F; Khambay, Balvinder S

    2014-09-01

    Computer packages have been introduced to simulate the movements of the jaw in three dimensions to facilitate planning of treatment. After final 3-dimensional virtual planning, a rapid prototype wafer can be manufactured and used in theatre. Our aim was to assess the accuracy of rapid prototyping of virtual wafers derived from laser scanned dental models using CAD/CAM software. Upper and lower plaster models from 10 orthognathic patients, the articulated models, and the conventional wafers were scanned. The virtual wafers were made from CAD/CAM software, and printed on a stereolithographic printer. We also scanned the articulated models with rapid prototype wafers in place. The validity of the final rapid prototype wafer was measured by the accuracy with which upper and lower models related to one another. The absolute mean error of the rapid prototype wafer when aligned with the dental models was 0.94 (0.09) mm. The absolute distance of the 2 models articulated by conventional and rapid prototype wafers ranged from 0.04 - 1.73mm. The rapid prototype wafers were able to orientate the upper and lower dental models with an absolute mean error of 0.94 (0.09) mm, but it ranged from 0.04-1.73mm. PMID:24933576

  18. Improvements in 0.5-micron production wafer steppers

    NASA Astrophysics Data System (ADS)

    Luehrmann, Paul F., Jr.; de Mol, Chris G. M.; van Hout, Frits J.; George, Richard A.; van der Putten, Harrie B.

    1991-07-01

    i-line wafer steppers have become the tool of choice for submicron production of advanced integrated circuits. These tools are now being extended to provide the required resolution, linewidth control, and overlay performance for devices with 16 Mb packing densities. To achieve this a manufacturing environment, suitable control procedures should be designed to minimize process and equipment variations. The primary goal of this paper is to characterize and quantify the ability of current generation steppers to meet or exceed the 100 nm AA (single machine) and the 175 nm BC (stepper to any other stepper in a production area) overlay requirements for half-micron production. For this, an overlay experiment using one reference and 12 randomly selected steppers was performed. Two Point through the lens alignment was used to reference wafer to reticle. Stages with three interferometrically controlled axes having both standard and enhanced resolution were used in the experiment. Features to improve stage positioning and overlay accuracy are discussed. To generate the required data, accurately calibrated reference wafers are used. The results were compared with a metrology model, which was used to optimize the matching of stepper lens and stage grid distortions so that optimum matching performance is achieved. The results then clearly predict whether all steppers meet the stringent overlay requirements for half-micron lithography in a production environment. In addition, experimental results show half-micron resolution performance with a number of commercially available i-line photoresists. Lens performance as affected by a phase-shifted reticle tooling are also examined to determine its potential benefit to 0.5 micron and sub-0.5 micron production.

  19. Alternative fabrication process for edgeless detectors on 6 in. wafers

    NASA Astrophysics Data System (ADS)

    Kalliopuska, Juha; Eränen, Simo; Virolainen, Tuula

    2011-05-01

    VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150 ?m thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 5×5 and 1×1 cm2 edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.4×1.4 cm2 Medipix2 edgeless pixel detectors were also fabricated.This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100 ?m from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50-70 nA/cm2 and 580-660 pF/cm2 at, respectively, 40 V reverse bias for the p-on-n. For the n-on-n design these parameters were 116-118 nA/cm2 and 930-960 pF/cm2. The breakdown voltages were above 150 V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13-28 V.

  20. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  1. Advanced Ceramic Wafer Seals Demonstrated at 2000 deg. F

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Durable, high-temperature sliding seals are required in advanced hypersonic engines and around movable control surfaces on future vehicles. These seals must operate at temperatures of 2000 to 2500 F, limit hot gas flow, remain resilient for multiple cycles, and resist scrubbing damage against rough surfaces. Current seal designs do not meet these demanding requirements, so the NASA Glenn Research Center is developing advanced seals and preload devices to overcome these shortfalls. An advanced ceramic wafer seal design and two silicon nitride compression spring designs were evaluated in a series of compression, scrub, and flow tests.

  2. Network analyzer calibration for cryogenic on-wafer measurements

    SciTech Connect

    Hietala, V.M.; Housel, M.S.; Caldwell, R.B.

    1994-04-01

    A cryogenic probe station for on-wafer microwave measurements has been developed at Sandia National Laboratories to explore the basic device physics and characterize advanced components for low-temperature applications. The station was designed to operate over a temperature range of 20 to 300 K with a frequency range of DC to 50 GHz. Due to the vacuum and the low temperature environment, the use of microwave probes and the calibration of network analyzer measurements are somewhat elaborate. This paper presents guidelines for probe use and calibration in this environment.

  3. Sulfur passivation techniques for III-V wafer bonding

    NASA Astrophysics Data System (ADS)

    Jackson, Michael James

    The use of direct wafer bonding in a multijunction III-V solar cell structure requires the formation of a low resistance bonded interface with minimal thermal treatment. A wafer bonded interface behaves as two independent surfaces in close proximity, hence a major source of resistance is Fermi level pinning common in III-V surfaces. This study demonstrates the use of sulfur passivation in III-V wafer bonding to reduce the energy barrier at the interface. Two different sulfur passivation processes are addressed. A dry sulfur passivation method that utilizes elemental sulfur vapor activated by ultraviolet light in vacuum is compared with aqueous sulfide and native oxide etch treatments. Through the addition of a sulfur desorption step in vacuum, the UV-S treatment achieves bondable surfaces free of particles contamination or surface roughening. X-ray photoelectron spectroscopy measurements of the sulfur treated GaAs surfaces find lower levels of oxide and the appearance of sulfide species. After 4 hrs of air exposure, the UV-S treated GaAs actually showed an increase in the amount of sulfide bonded to the semiconductor, resulting in less oxidation compared to the aqueous sulfide treatment. Large area bonding is achieved for sulfur treated GaAs / GaAs and InP / InP with bulk fracture strength achieved after annealing at 400 °C and 300 °C respectively, without large compressive forces. The electrical conductivity across a sulfur treated 400 °C bonded n-GaAs/n-GaAs interface significantly increased with a short anneal (1-2 minutes) at elevated temperatures (50--600 °C). Interfaces treated with the NH4OH oxide etch, on the other hand, exhibited only mild improvement in accordance with previously published studies in this area. TEM and STEM images revealed similar interfacial microstructure changes with annealing for both sulfur treated and NH4OH interfaces, whereby some areas have direct semiconductor-semiconductor contact without any interfacial layer. Fitting the observed temperature dependence of zero bias conductance using a model for tunneling through a grain boundary reveals that the addition of sulfur at the interface lowered the interfacial energy barrier by 0.2 eV. The interface resistance for these sulfur-treated structures is less than 0.03 O·cm 2 at room temperature. These results emphasize that sulfur passivation techniques reduce interface states that otherwise limit the implementation of wafer bonding for high efficiency solar cells and other devices.

  4. Creating a single twin boundary between two CdTe (111) wafers with controlled rotation angle by wafer bonding

    SciTech Connect

    Sun, Ce; Lu, Ning; Wang, Jinguo; Lee, Jihyung; Peng, Xin; Kim, Moon J., E-mail: moonkim@utdallas.edu [Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, Texas 75080 (United States); Klie, Robert F. [Department of Physics, University of Illinois at Chicago, Chicago, Illinois 60607 (United States)] [Department of Physics, University of Illinois at Chicago, Chicago, Illinois 60607 (United States)

    2013-12-16

    The single twin boundary with crystallographic orientation relationship (1{sup ¯}1{sup ¯}1{sup ¯})//(111) [01{sup ¯}1]//[011{sup ¯}] was created by wafer bonding. Electron diffraction patterns and high-resolution transmission electron microscopy images demonstrated the well control of the rotation angle between the bonded pair. At the twin boundary, one unit of wurtzite structure was found between two zinc-blende matrices. High-angle annular dark-field scanning transmission electron microscopy images showed Cd- and Te-terminated for the two bonded portions, respectively. The I-V curve across the twin boundary showed increasingly nonlinear behavior, indicating a potential barrier at the bonded twin boundary.

  5. Patterning of photocleavable zwitterionic polymer brush fabricated on silicon wafer.

    PubMed

    Kamada, Tomohiro; Yamazawa, Yuka; Nakaji-Hirabayashi, Tadashi; Kitano, Hiromi; Usui, Yuki; Hiroi, Yoshiomi; Kishioka, Takahiro

    2014-11-01

    Brushes of a polymer, namely poly(carboxymethylbetaine) (PCMB), were fabricated on silicon wafers by reversible addition-fragmentation chain-transfer (RAFT) polymerization using a surface-confined RAFT agent having an aromatic group at its bottom. The polymer brush showed effective suppression of the non-specific adsorption of bovine serum albumin (BSA) and adhesion of fibroblasts (3T3 cells). In contrast, BSA and 3T3 cells significantly adsorbed on and adhered to positively or negatively charged polymer brushes fabricated by the same procedure. Upon UV irradiation at 193 nm, the thickness of the PCMB brush with an aromatic group at its bottom decreased significantly whereas PCMB prepared using a surface-confined RAFT agent without an aromatic group needed a much higher irradiation dose to afford a comparable decrease in thickness. These results indicate a preferential cleavage of the PCMB brush due to photodecomposition of the phenyl group at the bottom. BSA and 3T3 cells non-specifically adsorbed on and adhered to the UV irradiation-induced hollow spaces, respectively. Furthermore, a designed pattern with a resolution of 5 ?m was successfully made on the PCMB brush above the silicon wafer by simple UV irradiation. These results suggest that the surface-confined aromatic RAFT agent will be quite useful for simple photolithography in biomedical fields. PMID:25466462

  6. Calibration of wafer surface inspection systems using spherical silica nanoparticles.

    PubMed

    Germer, Thomas A; Wolters, Christian; Brayton, Don

    2008-03-31

    Silica nanospheres with diameters ranging from 60 nm to 269 nm are investigated as an alternative to polystyrene spheres for calibrating laser-scattering-based wafer surface inspection systems, since they are less susceptible to changes upon ultraviolet exposure. Polystyrene and silica spheres were classified by differential mobility analysis before being deposited onto bare silicon wafers, and scattered signals were measured by two commercial tools using 488 nm and 355 nm laser light. The instrument signals were modeled by integrating a theoretically-determined differential cross section over the collection geometry of each tool, and the predicted signals were compared to the measured signals. The resulting calibrations, whether performed using the polystyrene spheres, the silica spheres, or both, were found to be equivalent and to meet industry requirements, provided the index of refraction of the silica spheres was allowed to be a floating parameter. The indices were found to be 1.413 and 1.421 at 488 nm and 355 nm, respectively, consistent with a void fraction of 11.4%. PMID:18542566

  7. Transfer printing and micro-scale hybrid materials systems

    Microsoft Academic Search

    Matthew Alexander Meitl

    2007-01-01

    Micro- and nano-scale engineering, especially as it applies to integrated circuits, has impacted society in revolutionary ways. These integrated circuits are characterized by huge numbers of small electronic devices manufactured on semiconductor wafers. Some emerging technologies will require assemblies of these micro\\/nano-devices on substrates that are very different from semiconductor wafers in terms of processing schemes and properties. Integration of

  8. Treatment of wastewater containing nano-scale silica particles by dead-end microfiltration: evaluation of pretreatment methods

    Microsoft Academic Search

    Jill R. Pan; Chihpin Huang; W. Jiang; Chiahsin Chen

    2005-01-01

    Chemical mechanical polishing (CMP) is the process to planarize wafer in the IC manufacturing. In the process, a large amount of ultra pure water is used to clean the surface of the wafer, which generates large quantity of wastewater containing high concentration of nano-scale silica particles. The wastewater is generally treated with the traditional coagulation\\/sedimentation process, producing large quantity of

  9. Development and implementation of PWQ on patterned wafer darkfield inspection systems

    Microsoft Academic Search

    Uwe Streller; Kay Wendt; Arno Wehner; Jens Goeckeritz; Markus Gahr; Martin Tuckermann; Jennifer Kopp; Monica Hellerqvist

    2009-01-01

    Process Window Qualification (PWQ) is a well-established wafer inspection technique used to qualify the design of mask sets and to characterize lithography process windows. While PWQ typically employs a broadband brightfield inspector, novel techniques for patterned wafer darkfield inspection have proven to provide sufficient sensitivity along with noise suppression benefits for lithography layers. This paper describes the introduction and implementation

  10. Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer Fabrication

    Microsoft Academic Search

    HONG CHEN; J. MICHAEL HARRISON; AVI MANDELBAUM; ANN VAN ACKERE; LAWRENCE M. WEIN

    1988-01-01

    This paper concerns performance modeling of semiconductor manufacturing operations. More specifically, it focuses on queueing network models for an analysis of wafer fabrication facilities. The congestion problems that plague wafer fabrication facilities are described in general terms, and several years' operating data from one particular facility are summarized. A simple queueing network model of that facility is constructed, and the

  11. 150 mm InP-to-Silicon Direct Wafer Bonding for Silicon Photonic Integrated Circuits

    E-print Network

    Bowers, John

    successfully wafer-bonded to a prepatterned silicon-on- insulator (SOI) substrate (001) intimately-V wafer horizontal slide during room-temperature mating. A highly efficient vertical outgassing channel reactions plus trapped air to be absorbed by the buried oxide (BOX) layer of the SOI substrate. Benefiting

  12. Damage Identification in Aging Aircraft Structures with Piezoelectric Wafer Active Sensors

    E-print Network

    Giurgiutiu, Victor

    Damage Identification in Aging Aircraft Structures with Piezoelectric Wafer Active Sensors VICTOR: Piezoelectric wafer active sensors can be applied to aging aircraft structures to monitor the onset and progress-geometry specimens, and then tested on realistic aging-aircraft panels with seeded cracks and corrosion

  13. Crack detection in single-crystalline silicon wafers using impact testing

    Microsoft Academic Search

    C. Hilmersson; D. P. Hess; W. Dallas; S. Ostapenko

    2008-01-01

    This paper presents acoustic measurements obtained by mechanically exciting vibratory modes in single-crystalline silicon wafers with hairline periphery cracks of different type and location. The data presented shows a dependence of natural frequencies, peak amplitudes and damping levels of four audio vibration modes in the frequency range up to 1000Hz on crack type and crack location. Data from defective wafers

  14. Stress diagnostics and crack detection in full-size silicon wafers using resonance ultrasonic vibrations

    Microsoft Academic Search

    Anton Byelyayev

    2005-01-01

    Non-destructive monitoring of residual elastic stress in silicon wafers is a matter of strong concern for modern photovoltaic industry. The excess stress can generate cracks within the crystalline structure, which further may lead to wafer breakage. Cracks diagnostics and reduction in multicrystalline silicon, for example, are ones of the most important issues in photovoltaics now. The industry is intent to

  15. Carrier-density-wave transport property depth profilometry using spectroscopic photothermal radiometry of silicon wafers I

    E-print Network

    Mandelis, Andreas

    radiometry of silicon wafers I: Theoretical aspects Derrick Shaughnessy and Andreas Mandelisa) Photothermal monitoring of contami- nation or implantation layers in silicon wafers, by varying the optical absorption, the photo- thermal radiometric technique relies on the collection of black body radiation from a sample

  16. Low target power wafer sputtering regime identified during magnetron tantalum barrier physical vapor deposition

    SciTech Connect

    Stout, Phillip J.; Denning, Dean J.; Michaelson, Lynne M.; Bagchi, Sandeep; Zhang Da; Ventzek, Peter L. G. [Freescale Semiconductor, Inc., 3501 Ed Bluestein Boulevard, Austin Texas 78721 (United States)

    2005-07-15

    A wafer sputtering regime has been identified during tantalum barrier deposition using a magnetron physical vapor deposition (MPVD) tool. The MPVD tools are designed to operate at high target powers (tens of kW) where the highly directed energetic metal (athermal metal) is the dominant metal species incident on the wafer. Although athermal metal gives better coverage than neutral metal (thermal) due to the narrower range of incident strike angles to the wafer, shadowing by the feature geometries is still a concern. Having available a wafer sputter regime or 'resputter' regime in a PVD tool allows for redistribution of metal from horizontal surfaces in the feature exposed to the plasma to vertical surfaces in the feature. The key in obtaining a wafer sputter regime is the operation of the plasma source in a range that the wafer bias power is effective at generating a sufficient self-bias for sputtering to occur. Discussed are modeling results which predict the wafer sputtering regime and the experimental confirmation that the low target power wafer sputter regime exists. The identified sputter regime in MPVD is such that there is a net deposition of metal at the field. Metal thickness reduction does occur at the trench and via bottoms where much of the unionized metal is being shadowed yielding a lower deposition to sputtering ratio compared to the field.

  17. Modeling of Power and Energy Transduction of Embedded Piezoelectric Wafer Active Sensors for Structural Health Monitoring

    E-print Network

    Giurgiutiu, Victor

    1 Modeling of Power and Energy Transduction of Embedded Piezoelectric Wafer Active Sensors a systematic investigation of power and energy transduction in piezoelectric wafer active sensors (PWAS the PWAS design guideline for PWAS sensing and power harvesting applications. Finally we considered

  18. Finite element analysis of deflection and residual stress on machined ultra-thin silicon wafers

    NASA Astrophysics Data System (ADS)

    Tian, Y. B.; Zhou, L.; Zhong, Z. W.; Sato, H.; Shimizu, J.

    2011-10-01

    The demand for ultra-thin silicon wafers has escalated in recent years with the rapid development of miniaturized electronic devices. Residual stress generated in the thinning process has a great influence on the machining quality of ultra-thin wafers. This work has developed a 2D axisymmetric finite element (FE) model to predict the deflection and full-field residual stress of ground ultra-thin wafers. The FE model consists of two-layer structures, i.e. a damage layer induced by the thinning process and a bulk silicon crystal layer without defects. A series of uniform in-plane strains is applied to the damage layer to simulate machining-generated initial stress. A full-field residual stress distribution in a machined ultra-thin wafer is predicted with the developed FE model after the initial stress is released. Based on the FE model, effects of wafer geometrical dimensions and loaded initial strain (or stress) on the maximum compressive/tensile residual stress and the maximum wafer deflection are revealed. The model is finally verified by comparing the simulated wafer deflection with the measured value. Based on this work, the deflection and residual stress of a machined ultra-thin wafer can be conveniently predicted.

  19. The optimization of CD uniformity and measurement on mask and wafer

    Microsoft Academic Search

    Yongkyoo Choi; Munsik Kim; Oscar Han

    2007-01-01

    As pattern size is shrinking, required mask CD specification is tighter and its effect on wafer patterning is more severe. To enhance the device performance, wafer CD uniformity should be enhanced and controlled by mask global CD uniformity. Mask global CD uniformity usually can be enhanced by mask process and optimal fogging effect correction. To enhance the mask global CD

  20. 3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces.

    E-print Network

    Salama, Khaled

    3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces. Journal: 2008 Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces Jian-Qiang Lu1 , J. Jay Mc approaches to 3D integration using adhesive, metal, and metal/adhesive as the bonding interfaces

  1. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbrecher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-01-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  2. Propagation of resist heating mask error to wafer level

    NASA Astrophysics Data System (ADS)

    Babin, S. V.; Karklin, Linard

    2006-10-01

    As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the mask error budget - the resist heating CD error. In simulation of exposure using a stepper, variable MEEF was considered.

  3. Effects of wafer impedance on the monitoring and control of ion energy in plasma reactors

    SciTech Connect

    Sobolewski, Mark A. [National Institute of Standards and Technology, Gaithersburg, Maryland 20899-8362 (United States)

    2006-09-15

    Ion kinetic energy in plasma reactors is controlled by applying radio-frequency (rf) substrate bias, but the efficiency and reproducibility of such control will be affected if the wafer being processed has a significant electrical impedance. Here, the effects of wafer impedance were studied by modeling and electrical measurements. Models of wafer impedance were proposed and tested by comparing model predictions to measured electrical wave forms. The tests were performed in an inductively coupled plasma reactor in 50% Ar, 50% CF{sub 4} gas at a pressure of 1.33 Pa (10 mTorr), rf bias frequencies of 0.1-10 MHz, rf bias amplitudes of 20-300 V, and inductive source powers of 100-500 W. At high bias frequencies, the dominant contribution to the wafer impedance was the capacitance of the gap between the wafer and its chuck. At low bias frequencies, however, a resistance associated with the contact between the wafer and the chuck became significant. Electrical wave forms and ion energy distributions were most sensitive to wafer impedance at low bias frequencies and low bias amplitudes. At low bias frequencies, model predictions indicate that the wafer impedance produces an undesirable variation in surface potential, sheath voltage, and ion energy across the wafer surface. Because it neglects wafer impedance effects, a technique that analyzes electrical wave forms to determine ion currents, sheath voltages, and ion energy distributions was found to suffer significant errors at low bias frequencies and amplitudes. Nevertheless, the technique provided accurate results at moderate to high bias frequency and amplitude.

  4. Effects of Lightpipe Proximity on Si Wafer Temperature in Rapid Thermal Processing Tools

    NASA Astrophysics Data System (ADS)

    Kreider, K. G.; Chen, D. H.; DeWitt, D. P.; Kimes, W. A.; Tsai, B. K.

    2003-09-01

    Lightpipe radiation thermometers (LPRTs) are used as temperature monitoring sensors in most rapid thermal processing (RTP) tools for semiconductor fabrication. These tools are used for dopant anneal, gate oxide formation, and other high temperature processing. In order to assure uniform wafer temperatures during processing these RTP tools generally have highly reflecting chamber walls to promote a uniform heat flux on the wafer. Therefore, only minimal disturbances in the chamber reflectivity are permitted for the sensors, and the small 2 mm diameter sapphire lightpipe is generally the temperature sensor of choice. This study was undertaken to measure and model the effect of LPRT proximity on the wafer temperature. Our experiments were performed in the NIST RTP test bed using a NIST thin-film thermocouple (TFTC) calibration wafer. We measured the spectral radiance temperature with the center lightpipe and compared these with the TFTC junctions and with the three LPRTs at the mid-radius of the wafer. We measured LPRT outputs from a position flush with the reflecting plate to within 2 mm of the stationary wafer under steady-state conditions with wafer-to-cold plate separation distances of 6 mm, 10 mm and 12.5 mm. Depressions in the wafer temperature up to 25 °C were observed. A finite-element radiation model of the wafer-chamber-lightpipe was developed to predict the temperature depression as a function of proximity distance and separation distance. The experimental results were compared with those from a model that accounts for lightpipe geometry and radiative properties, wafer emissivity and chamber cold plate reflectivity.

  5. A universal process development methodology for complete removal of residues from 300mm wafer edge bevel

    NASA Astrophysics Data System (ADS)

    Randall, Mai; Linnane, Michael; Longstaff, Chris; Ueda, Kenichi; Winter, Tom

    2006-03-01

    Many yield limiting, etch blocking defects are attributed to "flake" type contamination from the lithography process. The wafer edge bevel is a prime location for generation of this type of defect. Wafer bevel quality is not readily observed with top down or even most off axis inspection equipment. Not all chemistries are removed with one "universal" cleaning process. IC manufacturers must maximize usable silicon area as well. These requirements have made traditional chemical treatments to clean the wafer edge inadequate for many chemistry types used in 193nm processing. IBM has evaluated a method to create a robust wafer bevel and backside cleaning process. An August Technology AXi TM Series advanced macro inspection tool with E20 TM edge inspection module has been used to check wafer bevel cleanliness. Process impact on the removal of post apply residues has been investigated. The new process used backside solvent rinse nozzles only and cleaned the wafer bevel completely. The use of the topside edge solvent clean nozzles was eliminated. Thickness, wet film defect measurements (wet FM), and pattern wafer defect monitors showed no difference between the new backside rinse edge bead removal process and the process of record. Solvent topside edge bead removal of both bottom anti-reflective coatings and resist materials showed better cut width control and uniformity. We conclude that the topside solvent edge bead removal nozzle can be removed from the process. Backside solvent rinse nozzles can clean the backside of the wafer, the wafer bevel, and can wrap to the front edge of the wafer to provide a uniform edge bead removal cut width that is not sensitive to coater module tolerances. Recommendations are made for changes to the typical preventive maintenance procedures.

  6. Enhanced Wafer Matching Heuristics for 3-D ICs Vasilis F. Pavlidis, Hu Xu, and Giovanni De Micheli

    E-print Network

    De Micheli, Giovanni

    Enhanced Wafer Matching Heuristics for 3-D ICs Vasilis F. Pavlidis, Hu Xu, and Giovanni De Micheli.demicheli}@epfl.ch Pre-bond test has been identified as a vital step for the wafer level integration of 3-D ICs [1], [2 the profit obtained by wafer- to-wafer (W2W) matching, where the speed of the resulting 3-D cir- cuits

  7. Relaxed SiGe-on-insulator fabricated via wafer bonding and etch back Gianni Taraschi,a)

    E-print Network

    Relaxed SiGe-on-insulator fabricated via wafer bonding and etch back Gianni Taraschi,a) Thomas A was performed to deposit a strained Si etch stop layer followed by a Si0.75Ge0.25 layer. The wafers were bonded to oxidized Si handle wafers, and the wafer pairs were annealed. The backsides of the SiGe virtual substrates

  8. Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs

    E-print Network

    Chakrabarty, Krishnendu

    Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs Sudarshan Bahukudumbi.kacprowicz@intel.com Abstract--Wafer-level test during burn-in (WLTBI) has re- cently emerged as a promising technique to reduce result in high cost [1], [5]. Wafer level burn-in (WLBI) has recently emerged as an enabling technology

  9. 2236 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 16, NO. 12, DECEMBER 1998 Wafer-Fused Optoelectronics for Switching

    E-print Network

    2236 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 16, NO. 12, DECEMBER 1998 Wafer-Fused Optoelectronics, Senior Member, IEEE, and John E. Bowers, Fellow, IEEE Abstract-- Wafer fusion technique for realization, optical waveguide components, wafer bonding. I. INTRODUCTION MAJOR requirements for optical packet

  10. Contact Model for a Pad Asperity and a Wafer Surface in the Presence of Abrasive Particles for Chemical Mechanical Polishing

    E-print Network

    Müftü, Sinan

    Contact Model for a Pad Asperity and a Wafer Surface in the Presence of Abrasive Particles April 9-13, 2007. In CMP the interface of the polishing-pad and the wafer is filled with liquid slurry the pad asperites and the wafer. Therefore, it is necessary to understand the relative contributions

  11. Wafer-level Spatial and Flush Delay Analysis for IDDQ Estimation Sagar S. Sabade Duncan M. Walker

    E-print Network

    Walker, Duncan M. "Hank"

    Wafer-level Spatial and Flush Delay Analysis for IDDQ Estimation Sagar S. Sabade Duncan M. Walker between IDDQ and a second parameter like speed [16], temperature [17], and die position on a wafer [18 median IDDQ for all chips that passed all tests or failed only IDDQ test at the wafer level and had

  12. 2-dimensional ion velocity distributions measured by laser-induced fluorescence above a radio-frequency biased silicon wafer

    E-print Network

    California at Los Angles, University of

    -frequency biased silicon wafer Nathaniel B. Moore,1,a) Walter Gekelman,1,b) Patrick Pribyl,1,c) Yiting Zhang,2,d cm diameter, 2.2 MHz-biased silicon wafer in a commercial inductively coupled plasma processing along the surface of the wafer by utilizing a planar laser sheet from a pulsed, tunable dye laser

  13. 432 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 17, NO. 3, AUGUST 2004 Image-Based Wafer Navigation

    E-print Network

    Rivlin, Ehud

    432 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 17, NO. 3, AUGUST 2004 Image-Based Wafer- portant information. We present a new method for navigation on wafers that is based on localization of microscopic eye-point im- ages using a previously acquired wafer map. It is fast enough for in-line microscopy

  14. Generation of SWNTs on Si Wafer by Alcohol Catalytic CVD Shigeo Maruyama, Shohei Chiashi and Yuhei Miyauchi

    E-print Network

    Maruyama, Shigeo

    Generation of SWNTs on Si Wafer by Alcohol Catalytic CVD Shigeo Maruyama, Shohei Chiashi and Yuhei possible. We tried to generate SWNTs on Si wafer by ACCVD technique. Zeolite particles supporting Fe/Co catalysts were dispersed in ethanol, and this dispersion liquid (about 1 ) was dropped onto a Si wafer (10

  15. An Algorithm to Convert Wafer to Calendar-Based Preventive Maintenance Schedules for Semiconductor Manufacturing Systems1

    E-print Network

    Fernandez, Emmanuel

    An Algorithm to Convert Wafer to Calendar-Based Preventive Maintenance Schedules for Semiconductor schedules based on the count of wafers processed into equivalent calendar PM schedules. These equivalent a discrete mathematical model and an algorithm to convert from wafer-count targets into equivalent calendar

  16. Streaming and removal forces due to second-order sound field during megasonic cleaning of silicon wafers

    E-print Network

    Deymier, Pierre

    wafers P. A. Deymiera) Department of Materials Science and Engineering, University of Arizona, Tucson/fluid interface for two systems of importance in the technology of megasonic cleaning of silicon wafers. The first and a viscous fluid, namely water. The second system accounts for the finite thickness of silicon wafers

  17. 78 FR 61389 - Sanyo Solar of Oregon, LLC, Wafer Slicing and Quality Control Operations, Including On-Site...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-10-03

    ...TA-W-82,703] Sanyo Solar of Oregon, LLC, Wafer Slicing and Quality Control Operations...workers of Sanyo Solar of Oregon, LLC, Wafer Slicing and Quality Control Operations...engaged in the production of polysilicon wafers and included workers who supplied...

  18. Stresa, Italy, 26-28 April 2006 PARASITIC EFFECTS REDUCTION FOR WAFER-LEVEL PACKAGING OF RF-MEMS

    E-print Network

    Boyer, Edmond

    Stresa, Italy, 26-28 April 2006 PARASITIC EFFECTS REDUCTION FOR WAFER-LEVEL PACKAGING OF RF-MEMS J plays a very important role. In this work, a wafer-level packaging process has been investigated and optimized in order to minimize electrical parasitic effects. The package concept used is based on a wafer

  19. Lee, et al., "Wafer Nanotopography Effects..." MRS Spring Meeting April 20011 Brian Lee, Duane S. Boning (MIT)

    E-print Network

    Boning, Duane S.

    Lee, et al., "Wafer Nanotopography Effects..." MRS Spring Meeting ­ April 20011 Brian Lee, Duane SJiang Sun (Philips Semiconductor) Michael Lacy (Lam Research) #12;Lee, et al., "Wafer Nanotopography Effects..." MRS Spring Meeting ­ April 20012 "Nanotopography" refers to wafer surface variations with: 1. Lateral

  20. Evaluation of the Technical Feasibility and Effective Cost of Various Wafer Thicknesses for the Manufacture of Solar Cells

    NASA Technical Reports Server (NTRS)

    1979-01-01

    Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.

  1. Failure analysis of wafer-level reliability testing failure

    NASA Astrophysics Data System (ADS)

    Oh, Chong K.; Neo, Soh P.; Bi, Jian H.; Wu, Zong M.; Goh, Lian C.; Redkar, Shailesh

    1999-08-01

    Wafer-level reliability (WLR) testing is an important tool that is used during the productization phase to investigate the reliability performance of devices and materials before full qualification cycle. The rapid nature of the WLR testing permits the process engineer to evaluate process variation and to obtain almost instantaneous feedback about its reliability impact. Fast reliability feedback is essential to help the process engineer build reliability into our product during the productization phase. Understand the root cause and failure mechanism after WLR testing, failure analysis plays a very important role. This paper describes the fundamental requirements for failure analysis equipment needed, the failure analysis and preparatory techniques used to locate the failure sites and cases study will be presented.

  2. Microhardness of sputter-deposited zirconia films on silicon wafers

    SciTech Connect

    Pakala, M.; Walls, H.; Lin, R.Y. [Univ. of Cincinnati, OH (United States). Dept. of Materials Science and Engineering

    1997-06-01

    Calcia-stabilized zirconia films were deposited on the surface of silicon <111> wafers using radio frequency (rf) magnetron sputter deposition. Deposition was conducted at substrate temperatures that varied in the range of 80--900 C. X-ray diffractometry results showed that all the films consisted of cubic zirconia. The fracture surface morphology and etched surfaces of the films were studied using scanning electron microscopy (SEM). Depending on the deposition temperature, the structure of the film was either columnar or equiaxed. The transition temperature from the columnar structure to the equiaxed structure was at a ratio of deposition temperature to melting temperature of {approximately}0.42. The microhardness of the films was evaluated using a developed model that is based on the plastic zone analysis below a diamond (Vickers) indentor. From this model, the microhardness was found to increase as the deposition temperature increased, which was probably because the hardness of ceramic materials decreases as the defect concentration increases.

  3. Visible luminescence from silicon wafers subjected to stain etches

    NASA Technical Reports Server (NTRS)

    Fathauer, R. W.; George, T.; Ksendzov, A.; Vasquez, R. P.

    1992-01-01

    Etching of Si in a variety of solutions is known to cause staining. These stain layers consist of porous material similar to that produced by anodic etching of Si in HF solutions. In this work, photoluminescence peaked in the red from stain-etched Si wafers of different dopant types, concentrations, and orientations produced in solutions of HF:HNO3:H2O was observed. Luminescence is also observed in stain films produced in solutions of NaNO2 in HF, but not in stain films produced in solutions of CrO3 in HF. The luminescence spectra are similar to those reported recently for porous Si films produced by anodic etching in HF solutions. However, stain films are much easier to produce, requiring no special equipment.

  4. A Wafer Transfer Technology for MEMS Adaptive Optics

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean V.

    2001-01-01

    Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

  5. Characterization of semiconductor surface-emitting laser wafers

    SciTech Connect

    Gourley, P.L.; Vawter, G.A.; Brennan, T.M.; Hammons, B.E.

    1990-01-01

    The development of epitaxial semiconductor surface-emitting lasers has begun in recent years. These lasers are ultra-short (few {mu}m) Fabry-Perot resonators comprising epitaxial multilayer semiconductor mirrors and quantum well active regions. The resonators are single crystals grown along the lasing axis by molecular beam epitaxy (MBE) or chemical vapor deposition (CVD). They offer significant advances over conventional cleaved, edge-emitting lasers for creating lasers with single elements of 2 dimensional arrays, low beam divergence, engineered active regions, single longitudinal modes, and improved temperature characteristics. To realize the high potential of these new laser structures, techniques for characterizing the laser wafer after growth and between fabrication steps must be developed. In this paper we discuss several optical techniques that we have developed for this emerging surface-emitting laser technology.

  6. Chemical strategies for die/wafer submicron alignment and bonding.

    SciTech Connect

    Martin, James Ellis; Baca, Alicia I.; Chu, Dahwey; Rohwer, Lauren Elizabeth Shea

    2010-09-01

    This late-start LDRD explores chemical strategies that will enable sub-micron alignment accuracy of dies and wafers by exploiting the interfacial energies of chemical ligands. We have micropatterned commensurate features, such as 2-d arrays of micron-sized gold lines on the die to be bonded. Each gold line is functionalized with alkanethiol ligands before the die are brought into contact. The ligand interfacial energy is minimized when the lines on the die are brought into registration, due to favorable interactions between the complementary ligand tails. After registration is achieved, standard bonding techniques are used to create precision permanent bonds. We have computed the alignment forces and torque between two surfaces patterned with arrays of lines or square pads to illustrate how best to maximize the tendency to align. We also discuss complex, aperiodic patterns such as rectilinear pad assemblies, concentric circles, and spirals that point the way towards extremely precise alignment.

  7. Advanced laser mask repair in the current wafer foundry environment

    NASA Astrophysics Data System (ADS)

    Robinson, Tod; Yi, Daniel; LeClaire, Jeff; White, Roy; Bozak, Ron; Archuletta, Mike

    2010-09-01

    Contrary to the prior assumptions of its technical demise, deep UV (DUV) femtosecond pulsed laser repair of photomasks is continuing to mature and improve as a technology. Similar to the optical enhancements that allow for 193 nm wavelength light to continue being used down to the 32, or even in some cases 22 nm, node, the process regimes for this type of laser repair continue to expand as new processes are discovered. This work reviews the qualification of repair performance for production at a major wafer foundry site. In addition advances are shown in the area of through-pellicle repair (TRP) process development. These advances include the preferential (versus surrounding reference mask structures) removal of soft defects and the capability to remove or manipulate particles on top of a flat absorber region with no detectable removal of the absorber. These developments will further demonstrate the progressive decoupling of the laser repair spot size from the minimum technology node for laser repair.

  8. Long persistent near infrared luminescence nanoprobes LiGa5O8:Cr3+-PEG-OCH3 for in vivo imaging

    NASA Astrophysics Data System (ADS)

    Fu, Xiaoyan; Liu, Chunlin; Shi, Junpeng; Man, Huizi; Xu, Jia; Zhang, Hongwu

    2014-09-01

    The Cr3+-doped LiGa5O8 nanoparticles (LGNPs) with long-persistent near-infrared phosphorescence were obtained through a sol-gel approach followed by heat treatment at 800 °C in air. The obtained results reveal that the nanoparticles with an average diameter of 100 nm are well defined and have pure structure of LiGa5O8. After illumination for 3 min using a 254 nm UV lamp, the LGNPs exhibit strong near-infrared peak at ca. 720 nm belonging to tissue transparency window which can last for more than 1 h. Via surface modified with PEG-5000-OCH3, the LGNPs-PEG-OCH3 exhibit excellent biocompatibility and low toxicity. Under in vitro pre-excitation using a 254 nm UV lamp for 3 min, the in vivo distribution of the LGNPs-PEG-OCH3 in the abdomen can be detected in real time for more than 1 h. All the results indicate that the LGNPs-PEG-OCH3 can be used as potential nanoprobes to realize in vivo, real time and long time imaging with high sensitivity.

  9. Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers Used for PV Cells: Preprint

    SciTech Connect

    Guthrey, H.; Gorman, B.; Al-Jassim, M.

    2011-07-01

    As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay (uPCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

  10. Intrinsic Gettering in Nitrogen-Doped and Hydrogen-Annealed Czochralski-Grown Silicon Wafers

    NASA Astrophysics Data System (ADS)

    Goto, Hiroyuki; Pan, Lian-Sheng; Tanaka, Masafumi; Kashima, Kazuhiko

    2001-06-01

    The properties of nitrogen-doped and hydrogen-annealed Czochralski-grown silicon (NHA-CZ-Si) wafers were investigated in this study. The quality of the subsurface was investigated by monitoring the generation lifetime of minority carriers, as measured by the capacitance-time measurements of a metal oxide silicon capacitor (MOS C-t). The intrinsic gettering (IG) ability was investigated by determining the nickel concentration on the surface and in the subsurface as measured by graphite furnace atomic absorption spectrometry (GFAAS) after the wafer was deliberately contaminated with nickel. From the results obtained, the generation lifetimes of these NHA-CZ-Si wafers were determined to be almost the same as, or a little longer than those of epitaxial wafers, and the IG ability was proportional to the total volume of oxygen precipitates [i.e., bulk micro defects (BMDs)], which was influenced by the oxygen and nitrogen concentrations in the wafers. Therefore, it is suggested that the subsurface of the NHA-CZ-Si wafers is of good quality and the IG capacity is controllable by the nitrogen and oxygen concentrations in the wafers.

  11. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss

    PubMed Central

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-01-01

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180??m) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping. PMID:24820403

  12. Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

    NASA Technical Reports Server (NTRS)

    Okojie, Robert S. (Inventor)

    2002-01-01

    A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

  13. Comparison of simulation and wafer results for shadowing and flare effect on EUV alpha demo tool

    NASA Astrophysics Data System (ADS)

    Moon, James; Kim, Cheol-Kyun; Nam, Byoung-Sub; Nam, Byong-Ho; Lim, Chang-Moon; Yim, Donggyu; Park, Sung-Ki

    2009-12-01

    In this study, in order to accurately predict the shadowing and flare effect of EUVL, we compared and analyzed the wafer and simulation result of the shadowing and flare effect of the EUV alpha demo tool at IMEC. Flare distribution of the EUV Alpha Demo tool was measured and was used in simulation tool to simulate several test case wafer result. Also, shadowing effect of the in-house created mask was measured and compared with simulation result to match the predictability of the simulation tool. Shadowing test comparison of wafer to simulation showed that simulation with resist model showing better overall fitness to actual wafer result. Both aerial and resist model simulation result was within 2.33nm to wafer result. Measured wafer CD to simulation CD comparison for flare showed that average error RMS of 3 test cases was 0.52, 2.05 and 3.47 nm for each test case respectively. In order to have higher accuracy for flare simulation, larger diameter size for flare profile is necessary. Also from shadow test, resist model better fit the wafer trend than using only the aerial image for simulating shadowing effect. EUV tool showed very promising result for sub 30nm DRAM critical layer printing ability and with proper flare and shadowing correction, reasonable result is expected for sub 30 and beyond critical layers of DRAM using EUV lithography. Further work will be done to compensate flare and shadowing effect of EUV.

  14. Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010

    SciTech Connect

    Lorenz, A.

    2011-06-01

    1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

  15. Validation of thermodesorption method for analysis of semi-volatile organic compounds adsorbed on wafer surface.

    PubMed

    Hayeck, Nathalie; Gligorovski, Sasho; Poulet, Irène; Wortham, Henri

    2014-05-01

    To prevent the degradation of the device characteristics it is important to detect the organic contaminants adsorbed on the wafers. In this respect, a reliable qualitative and quantitative analytical method for analysis of semi-volatile organic compounds which can adsorb on wafer surfaces is of paramount importance. Here, we present a new analytical method based on Wafer Outgassing System (WOS) coupled to Automated Thermal Desorber-Gas chromatography-Mass spectrometry (ATD-GC-MS) to identify and quantify volatile and semi-volatile organic compounds from 6", 8" and 12" wafers. WOS technique allows the desorption of organic compounds from one side of the wafers. This method was tested on three important airborne contaminants in cleanroom i.e. tris-(2-chloroethyl) phosphate (TCEP), tris-(2-chloroisopropyl) phosphate (TCPP) and diethyl phthalate (DEP). In addition, we validated this method for the analysis and quantification of DEP, TCEP and TCPP and we estimated the backside organic contamination which may contribute to the front side of the contaminated wafers. We are demonstrating that WOS/ATD-GC-MS is a suitable and highly efficient technique for desorption and quantitative analysis of organophosphorous compounds and phthalate ester which could be found on the wafer surface. PMID:24720963

  16. Lyophilised wafers as a drug delivery system for wound healing containing methylcellulose as a viscosity modifier.

    PubMed

    Matthews, K H; Stevens, H N E; Auffret, A D; Humphrey, M J; Eccleston, G M

    2005-01-31

    Lyophilised wafers have potential as drug delivery systems for suppurating wounds. A dual series of wafers made from low molecular weight sodium alginate (SA) and xanthan gum (XG) respectively, modified with high molecular weight methylcellulose (MC) were produced. The swelling and flow properties of these wafers on model suppurating surfaces were both qualitatively and quantitatively investigated. The wafers instantaneously adhered to the surfaces, absorbing water and transforming from glassy, porous solids to highly viscous gels. The rate at which this occurred varied for the series studied with clear distinctions between the behaviour of SA and XG systems. For SA wafers there was a distinct relationship between the flow-rate and MC content. Increased amounts of MC decreased the rate at which the SA wafers flowed across a model gelatine surface. Flow rheometry was used to quantify the effect of increased MC content on both series of wafers and for the SA series, highlighted a substantial increase in apparent viscosity as a function of incremental increases in MC content. These results reflected those from the gelatine model. Observations of the reluctance of a swollen, unmodified XG wafer to flow compared with the relative ease of unmodified, low molecular weight SA was attributed to the yield stress characteristic of xanthan gels. XG is known to exhibit complex, loosely bound network structures in solution via the association of helical backbone structures. The inclusion of sodium fluorescein as a visible model for a soluble drug highlighted the potential of lyophilised wafers as useful drug delivery systems for suppurating wounds. PMID:15652198

  17. Meso-scale machining capabilities and issues

    SciTech Connect

    BENAVIDES,GILBERT L.; ADAMS,DAVID P.; YANG,PIN

    2000-05-15

    Meso-scale manufacturing processes are bridging the gap between silicon-based MEMS processes and conventional miniature machining. These processes can fabricate two and three-dimensional parts having micron size features in traditional materials such as stainless steels, rare earth magnets, ceramics, and glass. Meso-scale processes that are currently available include, focused ion beam sputtering, micro-milling, micro-turning, excimer laser ablation, femto-second laser ablation, and micro electro discharge machining. These meso-scale processes employ subtractive machining technologies (i.e., material removal), unlike LIGA, which is an additive meso-scale process. Meso-scale processes have different material capabilities and machining performance specifications. Machining performance specifications of interest include minimum feature size, feature tolerance, feature location accuracy, surface finish, and material removal rate. Sandia National Laboratories is developing meso-scale electro-mechanical components, which require meso-scale parts that move relative to one another. The meso-scale parts fabricated by subtractive meso-scale manufacturing processes have unique tribology issues because of the variety of materials and the surface conditions produced by the different meso-scale manufacturing processes.

  18. Low temperature solder process to join a copper tube to a silicon wafer

    NASA Astrophysics Data System (ADS)

    Versteeg, Christo; Scarpim de Souza, Marcio

    2014-06-01

    With the application for wafer level packages, which could be Complementary Metal-Oxide-Semiconductor (CMOS) based, and which requires a reduced atmosphere, a copper tube connection to a vacuum pump and the package is proposed. The method evaluated uses laser assisted brazing of a solder, to join the copper tube to a silicon wafer. The method was applied to a silicon wafer coated with a metallic interface to bond to the solder. The hermeticity of the joint was tested with a helium leak rate tester and the bonding energy thermal extent was verified with a thin layer of indium that melted wherever the substrate temperature rose above its melting temperature.

  19. W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

    NASA Technical Reports Server (NTRS)

    Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

    1997-01-01

    Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

  20. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sang Min; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Vukkadala, Pradeep; Awasthi, Amartya; Kim, J. H.; Veeraraghavan, Sathish; Choi, DongSub; Huang, Kevin; Dighe, Prasanna; Lee, Cheouljung; Byeon, Jungho; Dey, Soham; Sinha, Jaydeep

    2015-03-01

    Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes - which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.