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1

A Batch Wafer Scale LIGA Assembly and Packaging Technique vai Diffusion Bonding  

SciTech Connect

A technique using diffusion bonding (or solid-state welding) has been used to achieve batch fabrication of two- level nickel LIGA structures. Interlayer alignment accuracy of less than 1 micron is achieved using press-fit gauge pins. A mini-scale torsion tester was built to measure the diffusion bond strength of LIGA formed specimens that has shown successful bonding at temperatures of 450"C at 7 ksi pressure with bond strength greater than 100 Mpa. Extensions to this basic process to allow for additional layers and thereby more complex assemblies as well as commensurate packaging are discussed.

Christenson, T.R.; Schmale, D.T.

1999-01-27

2

Design automation for wafer scale integration  

SciTech Connect

Wafer scale integration (WSI) is a technique for implementing large digital systems on a single wafer. This thesis describes a system of design automation tools developed to aid in the implementation of wafer scale integrated systems. An overview of wafer scale integration is given with fabrication details and yield considerations discussed. The Wafer architectural Design Language (WDL) used to describe and specify a system architecture to the development system is introduced along with a compiler that translates the high level WDL description into net lists and other internal data bases. Interactive placement tools used to map the system architecture onto the functional die sites on a wafer are described. A very fast line probe router was developed to perform the custom wafer level routing need to personalize each wafer. Router data structures, algorithms, techniques, and results are discussed in detail. Sample wafer scale architectures and the result of their WSI implementations are shown. Also presented is the Wafer Transmission Module (WTM) a packaging technology related to wafer scale integration.

Donlan, B.J.

1986-01-01

3

A wafer scale dynamic thermal scene generator  

Microsoft Academic Search

As a prototype WSTA (wafer scale transducer array), a wafer scale dynamic thermal scene generator is being developed to generate a controllable infrared (IR) image for use in calibrating IR detector arrays. The basic array consists of two cell types, one being a thermal pixel containing a poly Si resistor sitting on a suspended oxide bridge. The second cell contains

G. H. Chapman; M. Parameswaran; M. J. Syrzycki

1992-01-01

4

Wafer-scale graphene integrated circuit.  

PubMed

A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance. PMID:21659599

Lin, Yu-Ming; Valdes-Garcia, Alberto; Han, Shu-Jen; Farmer, Damon B; Meric, Inanc; Sun, Yanning; Wu, Yanqing; Dimitrakopoulos, Christos; Grill, Alfred; Avouris, Phaedon; Jenkins, Keith A

2011-06-10

5

Wafer-scale micro-optics fabrication  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

Voelkel, Reinhard

2012-07-01

6

Wafer scale synthesis of bilayer graphene film  

NASA Astrophysics Data System (ADS)

The discovery of electric field induced bandgap opening in bilayer graphene paves the way for making semiconducting graphene without aggressive size scaling, or using expensive substrates. Despite intensive research, synthesizing homogeneous bilayer graphene in large size has proven extremely challenging, and the size of bilayer graphene was limited to micrometer scale by exfoliation Here we demonstrate homogeneous bilayer graphene films over at least square inch area, synthesized by chemical vapor deposition on copper foil and subsequently transferred to arbitrary substrates. Bilayer coverage of over 99% is confirmed by spatially resolved Raman spectroscopy. The result is further supported by electrical transport measurements on bilayer graphene transistors with dual-gate configuration, where field induced bandgap opening is observed in 98% of the devices. The size of our bilayer graphene film is only limited by the synthesis apparatus and can be readily scaled up, thus enabling wafer scale graphene electronics and photonics.

Lee, Kyunghoon; Lee, Seunghyun; Zhong, Zhaohui

2011-03-01

7

Wafer-scale charge isolation technique  

DOEpatents

An apparatus and method are described which improve the performance of charge-coupled devices (CCD) in the presence of ionizing radiation. The invention is a wafer scale charge isolation technique which inhibits or reduces the flow of electrons created by the passage of ionizing radiation in the bulk regions of a silicon CCD. The technique has been tested in a device designed for operating in the infra-red wavelength band. The technique prevents charge from reaching the active charge collection volume of a pixel in a CCD.

Colella, N.J.; Kimbrough, J.R.

1994-12-31

8

Wafer-scale Mitochondrial Membrane Potential Assays  

PubMed Central

It has been reported that mitochondrial metabolic and biophysical parameters are associated with degenerative diseases and the aging process. To evaluate these biochemical parameters, current technology requires several hundred milligrams of isolated mitochondria for functional assays. Here, we demonstrate manufacturable wafer-scale mitochondrial functional assay lab-on-a-chip devices, which require mitochondrial protein quantities three orders of magnitude less than current assays, integrated onto 4” standard silicon wafer with new fabrication processes and materials. Membrane potential changes of isolated mitochondria from various well-established cell lines such as human HeLa cell line (Heb7A), human osteosarcoma cell line (143b) and mouse skeletal muscle tissue were investigated and compared. This second generation integrated lab-on-a-chip system developed here shows enhanced structural durability and reproducibility while increasing the sensitivity to changes in mitochondrial membrane potential by an order of magnitude as compared to first generation technologies. We envision this system to be a great candidate to substitute current mitochondrial assay systems.

Lim, Tae-Sun; Davila, Antonio; Zand, Katayoun; Douglas, Wallace C.; Burke, Peter J.

2012-01-01

9

Wafer level chip scale packaging (WL-CSP): an overview  

Microsoft Academic Search

Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing. Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP's when

Philip Garrou

2000-01-01

10

Partitioning and Redundancy Model for Wafer-Scale Integrated Circuits.  

National Technical Information Service (NTIS)

A general, architecture independent model to calculate the required amount of redundancy and the necessary degree of partitioning of the circuit to achieve a maximum efficiency are presented. In wafer scale integration, a certain amount of redundancy is r...

M. F. Beusekamp

1991-01-01

11

A test methodology for wafer scale system  

Microsoft Academic Search

To efficiently access and control on-chip design for test (DFT) circuitry, a standard test interface is required. A uniform testing interface is defined for each functional cell, with built-in self-test incorporated whenever possible. Use of a standard interface will reduce test complexity and costs by allowing entire wafer probing by a common standardized probe card, irrespective of the number of

David L. Landis

1992-01-01

12

A Wafer-Scale Packaging for RF DMTL Phase Shifter  

Microsoft Academic Search

In this paper, a wafer-scale gold-to-gold thermo-compression bonding packaging based on an RF distributed MEMS transmission line (DMTL) phase shifter is proposed. The DMTL phase shifter, based on a coplanar waveguide (CPW), has symmetrical saw-shaped structures in the CPW signal line under the MEMS bridge and an insulation layer in the middle of the structures. Two Si wafers are bonded

Jin Luikui; Wu Qun; Tang Kai; He Xunjun; Yang Guohui; Fu Jiahui

2008-01-01

13

Wafer-scale synthesis and transfer of graphene films.  

PubMed

We developed means to produce wafer scale, high-quality graphene films as large as 3 in. wafer size on Ni and Cu films under ambient pressure and transfer them onto arbitrary substrates through instantaneous etching of metal layers. We also demonstrated the applications of the large-area graphene films for the batch fabrication of field-effect transistor (FET) arrays and stretchable strain gauges showing extraordinary performances. Transistors showed the hole and electron mobilities of the device of 1100 +/- 70 and 550 +/- 50 cm(2)/(V s) at drain bias of -0.75 V, respectively. The piezo-resistance gauge factor of strain sensor was approximately 6.1. These methods represent a significant step toward the realization of graphene devices in wafer scale as well as application in optoelectronics, flexible and stretchable electronics. PMID:20044841

Lee, Youngbin; Bae, Sukang; Jang, Houk; Jang, Sukjae; Zhu, Shou-En; Sim, Sung Hyun; Song, Young Il; Hong, Byung Hee; Ahn, Jong-Hyun

2010-02-10

14

A strategy to prepare wafer scale bismuth compound superstructures.  

PubMed

Epitaxial wafer scale superstructures of bismuth compounds are synthesized. Single crystalline ?-Bi2O3 films are obtained by sputtering amorphous BiOx onto (001)-oriented strontium titanate with a buffer layer, followed by thermal crystallization. This is used as the precursor for the growth of the superstructures. The superstructures of bismuth compounds reveal anisotropic physical properties that are related to their unique morphology. PMID:23754697

Guo, Chuan Fei; Zhang, Jianming; Wang, Meng; Tian, Ye; Liu, Qian

2013-06-10

15

Wafer scale production of carbon nanotube scanning probe tips for atomic force microscopy  

Microsoft Academic Search

A methodology is developed to enable wafer scale fabrication of single-walled carbon nanotube (SWNT) tips for atomic force microscopy. Catalyst selectively placed onto 375 prefabricated Si tips on a wafer is made possible by a simple patterning technique. Chemical vapor deposition on the wafer scale leads to the growth of SWNTs protruding from more than 90% of the Si tips.

Erhan Yenilmez; Qian Wang; Robert J. Chen; Dunwei Wang; Hongjie Dai

2002-01-01

16

Wafer-scale fabrication of penetrating neural microelectrode arrays  

NASA Astrophysics Data System (ADS)

In order to have an efficient neural interface, uniformity and predictability of electrodes electrical, and mechanical characteristics are desired. Furthermore, the electrodes should have small active sites to selectively record or stimulate neural signals. Also, there should be close geometrical match between the electrode array and the targeted tissue for long-term stability. Currently the Utah electrode array (UEA) is in either constant electrode length (UEA) or varying length configurations (Utah slant electrode array: USEA). The current processes used to fabricate the UEAs impose limitations in the tolerances of the electrode array geometry. Furthermore, the flat architecture of the UEA and convoluted geometry of the targeted tissue results in poor coupling between the two "mating" surfaces, leading in active electrode tips that are not in proximity to the neuronal tissue. Therefore, a robust, flexible and high precision fabrication technology is needed that can produce (a) uniformly shaped microelectrodes (b) small and uniformly exposed active tip sites and (c) convoluted electrode arrays for better geometrical match. This dissertation presents a wafer-scale fabrication process for both the UEA and the USEA. A wafer-scale etching method has been developed and optimum etching conditions are established to achieve uniform shape electrode arrays. Also, the etching rate of silicon columns, produced by dicing, is studied as a function of temperature, etching time and stirring rate in the acid solution. Furthermore, a novel photoresist based masking technique for procuring extremely small active area has been developed on wafer-scale. In this technique, the tip exposure is controlled by varying the spin speed during photoresist coating. The technique allows fabrication of uniformly exposed tip lengths, over a range of 30 to 350 microm in length. Lastly, a novel array fabrication technique is developed for building a variety of neural interface devices having complex three-dimensional geometries using variable depth dicing and wet etching. The wafer-scale technique results in fabrication of highly controlled electrode shape, size and tip exposure which inturn allows better controllability in the electrical characteristics (impedance) of the electrode array. The uniformity in electrode impedance would lead to better understanding of observed variations in physiological results.

Bhandari, Rajmohan

17

Liga developer apparatus system  

DOEpatents

A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

Boehme, Dale R. (Pleasanton, CA); Bankert, Michelle A. (San Francisco, CA); Christenson, Todd R. (Albuquerque, NM)

2003-01-01

18

Wafer scale interdigitated nanoelectrode devices functionalized using a MEMS-based deposition system  

Microsoft Academic Search

This paper reports on a methodology to elaborate interdigitated nanoelectrode devices (INDs) at the wafer scale, relying on a mix-and-match process which combines proximity optical lithography and electron beam lithography. An optimum exposure dose allowed fabricating nanodevices, at the wafer level, with a successful yield of 97%. The final devices are bonded onto conventional TO-8 packages. Electrical characterization in a

A Martinez-Rivas; F Carcenac; D Saya; C Séverac; L Nicu; C Vieu

2012-01-01

19

Activities of LIGA and Nano LIGA Technologies at BSRF  

NASA Astrophysics Data System (ADS)

Beijing Synchrotron Radiation Facility (BSRF ) is a partly dedicated synchrotron radiation ( SR) source operated in either parasitic or dedicated mode. LIGA research at BSRF started from 1993 and focused in the first two steps of deep X-ray lithography and electroplating. Scanning exposure chamber of deep X-ray lithography was first built in 1996 on a 3W1 wiggler beamline with very hard X-ray and high X-ray density. We used the system for the research of LIGA deep X-ray lithography for many years, and found that the wiggler beamline does not meet the LIGA deep X-ray lithography for its disadvantages of small and bad uniform X-ray spot of 30mm on the wafer in horizontal and the very high X-ray power density on the wafer which causes the distortion of resist structures by the large heat load on the resist. In 2001 we used a bending magnet beamline (3B1) as deep X-ray lithography instead of wiggler beamline. The 3B1 beamline is divided to be 3B1B as LIGA deep X-ray lithography and 3B1A as nano X-ray lithography. The electroplating is used to make the mechanical parts and mold insert with nickel and copper materials for different applications.

Yi, F.; Zhang, J.; Xie, C.; Wang, D.; Chen, D.

2006-04-01

20

Lead-free wafer level-chip scale package: assembly and reliability  

Microsoft Academic Search

This paper discusses the reliability testing results of a lead-free version of the micro SMD, National Semiconductor's Wafer Level-Chip Scale Package (WL-CSP). The micro SMD, a true wafer scale package has proven to be highly adaptable in the conventional assembly process, requiring no special considerations during the surface mount assembly operation. The current micro SMD utilizes standard Sn\\/Pb solder bumps

V. Patwardhan; N. Kelkar; L. Nguyen

2002-01-01

21

Nickel Micro-spike for Micro-scale Biopsy using LiGA Process  

NASA Astrophysics Data System (ADS)

In this paper, biopsy tools are developed for minimally invasive tissue sampling using the LiGA (Lithographie Galvanoformung Abformung) process. The micro-spike is composed of two barbed-shanks and a body. The shank of the micro-spike is between 2 mm ~ 3 mm and the opening gap is approximately 350 ?m between the shanks. The micro-spike is integrated with the conventional catheter, for medical diagnostics. Tissue samples were extracted from the anesthetized pigs using biopsy catheters in vivo, and observed with hematoxylin and eosin (H&E) staining. The amount of extracted sample is sufficient to diagnose abnormal cells.

Kim, Gilsub; Park, Sunkil; Koo, Kyo-In; Choi, Hyun-Min; Jung, Myeong-Jun; Song, Si-Young; Bang, Seoung-Min; Cho, Dongil ``Dan''

2007-01-01

22

100GHz Transistors from Wafer-Scale Epitaxial Graphene  

Microsoft Academic Search

The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon

Y.-M. Lin; C. Dimitrakopoulos; K. A. Jenkins; D. B. Farmer; H.-Y. Chiu; A. Grill; Ph. Avouris

2010-01-01

23

A wafer-scale 170000-gate FFT processor with built-in test circuits  

Microsoft Academic Search

The wafer-scale 170,000-gate fast Fourier transform (FFT) processor described consists of individual repeatable building blocks, each of which contains a processing element (PE) and interconnection wiring. The PE consists of a multiplier accumulator and its built-in self-test circuits. The wafer system is reconfigured by connected active blocks after block self-diagnosis. Blocks are connected using a programmable contact-hole mask. The processor

Koichi Yamashita; Akinori Kanasugi; Shinpei Hijiya; Gensuke Goto; Nobutake Matsumura; T. Shirato

1988-01-01

24

Wafer-Scale Manufacturing of Bulk Shape-Memory-Alloy Microactuators Based on Adhesive Bonding of Titanium–Nickel Sheets to Structured Silicon Wafers  

Microsoft Academic Search

This paper presents a concept for the wafer-scale manufacturing of microactuators based on the adhesive bonding of bulk shape-memory-alloy (SMA) sheets to silicon microstructures. Wafer-scale integration of a cold-state deformation mechanism is provided by the deposition of stressed films onto the SMA sheet. A concept for heating of the SMA by Joule heating through a resistive heater layer is presented.

Stefan Braun; Niklas Sandstrom; GÖran Stemme; Wouter van der Wijngaart

2009-01-01

25

Wafer scale integration of micro-optic and optoelectronic elements by polymer UV reaction molding  

NASA Astrophysics Data System (ADS)

A replication technique allowing for the wafer scale integration of microoptical elements is presented and illustrated by various examples. The technique is based on polymer UV reaction moulding using a modified contact mask aligned where mask and wafer are replaced by the replication tool and an arbitrary substrate, respectively. The technology takes advantage of the high precision and adjustment accuracy of photolithography equipment. The replication masters are nickel shims, etched Silicon wafers or uv-transparent fused silica tools. The latter ones allow for replication on opaque substrates. Additionally, polymer elements with unique properties can be obtained by the combination of replication and resist technology using partially transparent replication tools. Wafer scale hybrid integration of microoptical subsystems is accomplished by replication of polymer elements like lenses, lens arrays, micro prisms etc. onto semiconductor wafers containing detectors or VCSELs, or by combining microoptical elements on both sides of a glass wafer. The use of thin layers of uv cured polymers on inorganic substrates results in good thermal and mechanical stability compare to all-polymer devices.

Dannberg, Peter; Bierbaum, Ralf; Erdmann, Lars; Braeuer, Andreas H.

1999-04-01

26

Bio/chemical microsystem designed for wafer scale testing  

NASA Astrophysics Data System (ADS)

We have designed a bio/chemical microsystem for online monitoring of glucose concentrations during fermentation. The system contains several passive microfluidic components including an enzyme reactor, a flow lamination part and a detector. Detection is based on the reaction of hydrogen peroxide, that is produced from glucose in an enzyme reactor, with luminol. This chemiluminescent reaction generates light that is detected by an integrated back-side contacted photodiode array. Various tests during fabrication are outlined with the emphasis on microwave detected photo conductance decay. The presented microsystem has both fluidic and electrical connection points accessible from the backside. This allows simultaneous testing of both fluidic and electrical parts before dicing the wafer.

Jorgensen, Anders M.; Mogensen, Klaus B.; Rong, Weimin; Telleman, Pieter; Kutter, Joerg P.

2001-04-01

27

New challenges for 300 mm Si technology: 3D interconnects at wafer scale by aligned wafer bonding  

Microsoft Academic Search

A new alignment technique is proposed for wafer level 3D interconnects fabrication: the SmartView®. This original procedure is using alignment keys located in the bonding interface and enables an alignment precision of 1?m. The method uses two top–bottom microscope pairs for observing the alignment keys and a minimal Z-axis travel during wafer alignment procedure. After the alignment procedure, the wafers

V. Dragoi; P. Lindner; M. Tischler; C. Schaefer

2002-01-01

28

DynAMITe: a wafer scale sensor for biomedical applications  

NASA Astrophysics Data System (ADS)

In many biomedical imaging applications Flat Panel Imagers (FPIs) are currently the most common option. However, FPIs possess several key drawbacks such as large pixels, high noise, low frame rates, and excessive image artefacts. Recently Active Pixel Sensors (APS) have gained popularity overcoming such issues and are now scalable up to wafer size by appropriate reticule stitching. Detectors for biomedical imaging applications require high spatial resolution, low noise and high dynamic range. These figures of merit are related to pixel size and as the pixel size is fixed at the time of the design, spatial resolution, noise and dynamic range cannot be further optimized. The authors report on a new rad-hard monolithic APS, named DynAMITe (Dynamic range Adjustable for Medical Imaging Technology), developed by the UK MI-3 Plus consortium. This large area detector (12.8 cm × 12.8 cm) is based on the use of two different diode geometries within the same pixel array with different size pixels (50 ?m and 100 ?m). Hence the resulting device can possess two inherently different resolutions each with different noise and saturation performance. The small and the large pixel cameras can be reset at different voltages, resulting in different depletion widths. The larger depletion width for the small pixels allows the initial generated photo-charge to be promptly collected, which ensures an intrinsically lower noise and higher spatial resolution. After these pixels reach near saturation, the larger pixels start collecting so offering a higher dynamic range whereas the higher noise floor is not important as at higher signal levels performance is governed by the Poisson noise of the incident radiation beam. The overall architecture and detailed characterization of DynAMITe will be presented in this paper.

Esposito, M.; Anaxagoras, T.; Fant, A.; Wells, K.; Konstantinidis, A.; Osmond, J. P. F.; Evans, P. M.; Speller, R. D.; Allinson, N. M.

2011-12-01

29

Study on Board Level Drop Reliability of Wafer Level Chip Scale Package with Leadfree Solder  

Microsoft Academic Search

Wafer level chip scale package (WLCSP) is a promising packaging technology to accommodate the demand for small, portable handheld electronic. This bare-die bumped package is able to offer significant area savings, improve package electrical parasitics and power dissipation performance over substrate-based BGA packages. However, its board level reliability especially mechanical performance under shock impact is a great concern for handheld

Zhang Xueren; Zhu Wenhui; P. Edith; Tan Hien Boon

2008-01-01

30

Thermal-Electrical Co-simulation for Wafer-level Chip Scale Package Maximum Bearing Current  

Microsoft Academic Search

As the trend of smaller and higher density packaging technology developing, the wafer-level chip scale package (WLCSP) is becoming the popular choice for device assembly. While many high performance chip often with high power, the power dissipation through the chip also leads to higher die temperatures. With the redistribution layer of the WLCSP getting more narrow and thinner, in order

Rui-Yu; Shu-Qiang Zhang; Chang-Lin Yeh; Chi-Sheng Chung; Chih-Pin Hung

2008-01-01

31

Rotary electrostatic micromirror switches using wafer-scale processing and assembly  

Microsoft Academic Search

The design, micromachining process, wafer-scale assembly, and experimental characterization of our rotary electrostatic micromirrors for optical switching applications are reported in this paper. Some of the proposed microelectromechanical systems (MEMS) optical switches utilize surface-micromachined thin films as the reflection micromirrors which might result in optical degradation due to dynamic warping. Some of these devices fabricated by bulk micromachining highly rely

Ching-Chen Tu; Kuohao Fanchiang; Cheng-Hsien Liu

2006-01-01

32

Uniformity study of wafer-scale InP-to-silicon hybrid integration  

Microsoft Academic Search

In this paper we study the uniformity of up to 150 mm in diameter wafer-scale III–V epitaxial transfer to the Si-on-insulator\\u000a substrate through the O2 plasma-enhanced low-temperature (300°C) direct wafer bonding. Void-free bonding is demonstrated by the scanning acoustic\\u000a microscopy with sub-?m resolution. The photoluminescence (PL) map shows less than 1 nm change in average peak wavelength,\\u000a and even improved

Di Liang; David C. Chapman; Youli Li; Douglas C. Oakley; Tony Napoleone; Paul W. Juodawlkis; Chad Brubaker; Carl Mann; Hanan Bar; Omri Raday; John E. Bowers

2011-01-01

33

Wafer-scale replication and testing of micro-optical components for VCSELs  

NASA Astrophysics Data System (ADS)

VCSELs (Vertical-Cavity Surface-Emitting Lasers) emit circularly symmetric beams vertical to the substrate; the small footprint of the active area (around 400 um2) enables the simultaneous fabrication of several thousand devices on a single wafer. Micro-optical components can modify the free-space optical properties of VCSELs for applications such as fiber-coupling in transceiver modules, illumination purposes, or beam profiling in sensing applications. However, the alignment of a laser towards a lens, for example, is expensive when performed separately for each device. Here we demonstrate a wafer-scale replication process to realise microlenses directly on top of the undiced VCSEL wafers. The process combines uv-casting and lithography to achieve material-free bonding pads and dicing lines. Several examples of lenses and gratings are given. An organically modified sol-gel material (ORMOCER) has been used as lens material. The micro-optical components on the wafer show good stability while sawing and bonding, where temperatures up to 220°C may occur. We have compared refractive lenses on top of the VCSELs with lenses on glass substrates. The lenses on the glass wafers were illuminated from the back-side by a planar wave. Spot diameters around 1.2 um and focal lengths of 30 um to 100 um were measured depending on the radii of curvature. On the VCSELs the lenses showed a strong influence on the transversal mode behaviour.

Gimkiewicz, Christiane; Moser, Michael; Obi, Samuel; Urban, Claus; Pedersen, Joern S.; Thiele, Hans; Zschokke, Christian; Gale, Michael T.

2004-09-01

34

A wafer-scale 170000-gate FFT processor with built-in test circuits  

NASA Astrophysics Data System (ADS)

The wafer-scale 170,000-gate fast Fourier transform (FFT) processor described consists of individual repeatable building blocks, each of which contains a processing element (PE) and interconnection wiring. The PE consists of a multiplier accumulator and its built-in self-test circuits. The wafer system is reconfigured by connected active blocks after block self-diagnosis. Blocks are connected using a programmable contact-hole mask. The processor performs parallel 16-bit, eight-point complex FFTs and is implemented with 725 I/O pads in triple-metal 2.3-micron p-well CMOS technology on a 4-in. wafer. It is mounted by controlled-collapse bonding facedown on a 11.8 x 11.8-sq cm substrate.

Yamashita, Koichi; Kanasugi, Akinori; Hijiya, Shinpei; Goto, Gensuke; Matsumura, Nobutake

1988-04-01

35

Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates  

NASA Astrophysics Data System (ADS)

Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2 O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of 1 ?m, are larger than 800 MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors, which paves the way for high-performance graphene devices and circuits.

Pan, Hong-Liang; Jin, Zhi; Ma, Peng; Guo, Jian-Nan; Liu, Xin-Yu; Ye, Tian-Chun; Li, Jia; Dun, Shao-Bo; Feng, Zhi-Hong

2011-12-01

36

Wafer-scale fabrication of magneto-photonic structures in Bismuth Iron Garnet thin film  

Microsoft Academic Search

In this paper we report on a reproducible technological process for wafer-scale fabrication of different photonic structures in Bismuth Iron Garnet (BIG: Bi3Fe5O12) thin films: two-dimensional magneto-photonic crystals (PhC), ring circulators, Bragg gratings or ridge waveguides. Different fabrication techniques such as Ion Beam Etching (IBE), Focused Ion Beam (FIB) etching, wet chemical etching and Reactive Ion etching are compared. The

L. Magdenko; E. Popova; M. Vanwolleghem; C. Pang; F. Fortuna; T. Maroutian; P. Beauvillain; N. Keller; B. Dagens

2010-01-01

37

On-Chip High Variable Inductor Using Wafer-Level Chip-Scale Package Technology  

Microsoft Academic Search

In this paper, the authors propose an on-chip high-Q variable inductor embedded in wafer-level chip-scale package (WL-CSP). The variable inductor has a metal plate and a spiral inductor fabricated by the WL-CSP technology. The metal plate can be moved by a microelectromechanical systems (MEMS) actuator, and the inductance is varied according to the position of the metal plate. At the

Kenichi Okada; Hirotaka Sugawara; Hiroyuki Ito; Kazuhisa Itoi; Masakazu Sato; Hiroshi Abe; Tatsuya Ito; Kazuya Masu

2006-01-01

38

A parametric solder joint reliability model for wafer level-chip scale package  

Microsoft Academic Search

The micro-SMD is a Wafer Level-Chip-Scale Package (WL-CSP) designed to have external dimensions equal to that of the silicon device. This new package type extends flip-chip packaging technology to standard surface mount technology. The package has been successfully targeted for low pin count (less than 30), high volume applications such as cellular phones, hand-held PDAs, etc. Since the WL-CSP is

J. Pitarresi; S. Chaparala; B. Sammakia; L. Nguyen; V. Patwardhan; L. Zhang; N. Kelkar

2002-01-01

39

Constrained collapse solder joint formation for wafer-level-chip-scale packages to achieve reliability improvement  

Microsoft Academic Search

Wafer-level-chip-scale-packages (WLCSP) are rapidly proving to be the package of choice for portable electronics applications. National Semiconductor's micro SMD package family has been a front-runner in the development of this package type. These packages have a proven reliability in the lower pin-count range (up to 36 I\\/O) when used in conjunction with standard surface mount assembly (SMT). However, extending this

V. Patwardhan; H. Nguyen; L. Zhang; N. Kelkar; L. Nguyen

2004-01-01

40

Wafer scale interdigitated nanoelectrode devices functionalized using a MEMS-based deposition system.  

PubMed

This paper reports on a methodology to elaborate interdigitated nanoelectrode devices (INDs) at the wafer scale, relying on a mix-and-match process which combines proximity optical lithography and electron beam lithography. An optimum exposure dose allowed fabricating nanodevices, at the wafer level, with a successful yield of 97%. The final devices are bonded onto conventional TO-8 packages. Electrical characterization in a short-circuited nanoelectrode is performed, revealing a 230 µ? cm resistivity value at 23?°C. A MEMS-based spotter made of cantilevers (called Bioplume) has been used to obtain precise functionalization of the INDs with sub-picoliter volume solutions. These INDs are the basis of multiple tunnel junction nanodevices, intended to serve as novel highly sensitive nanobiosensors. PMID:22361922

Martinez-Rivas, A; Carcenac, F; Saya, D; Séverac, C; Nicu, L; Vieu, C

2012-02-24

41

Silicon hybrid wafer scale integration interconnect performance evaluation at RF frequencies  

NASA Astrophysics Data System (ADS)

The RF electrical characteristics of hybrid wafer scale integration (WSI) interconnections on silicon-polyimide-aluminum and silicon-benzocyclobutene-aluminum substrates have been evaluated. The silicon wafer substrates were five in in diameter, and each contained an identical set of 200 photolithographically patterned dielectric and aluminum interconnect test structures. The aluminum conductors were 2.5-microns thick, and half of the test structure conductors were 10-microns wide, while the remainder were 25-microns wide. Measurements between 5 kHz and 220 MHz confirmed the expected transmission line behavior manifested by the longer interconnections. The coupling levels in the 400 line/cm density structures are low, but nevertheless significant, especially when digital logic applications requiring low-noise margins are anticipated. More important were the attenuation effects manifested by the longer aluminum interconnections when they were combined with low-impedence matched terminations.

Lyke, James C., Jr.; Kolesar, Edward S., Jr.

42

Wafer scale interdigitated nanoelectrode devices functionalized using a MEMS-based deposition system  

NASA Astrophysics Data System (ADS)

This paper reports on a methodology to elaborate interdigitated nanoelectrode devices (INDs) at the wafer scale, relying on a mix-and-match process which combines proximity optical lithography and electron beam lithography. An optimum exposure dose allowed fabricating nanodevices, at the wafer level, with a successful yield of 97%. The final devices are bonded onto conventional TO-8 packages. Electrical characterization in a short-circuited nanoelectrode is performed, revealing a 230 µ? cm resistivity value at 23?°C. A MEMS-based spotter made of cantilevers (called Bioplume) has been used to obtain precise functionalization of the INDs with sub-picoliter volume solutions. These INDs are the basis of multiple tunnel junction nanodevices, intended to serve as novel highly sensitive nanobiosensors.

Martinez-Rivas, A.; Carcenac, F.; Saya, D.; Séverac, C.; Nicu, L.; Vieu, C.

2012-03-01

43

200 mm wafer-scale epitaxial transfer of single crystal Si on glass by anodic bonding of silicon-on-insulator wafers  

SciTech Connect

We report a low-temperature (350 deg. C) anodic bonding followed by grind/etch-back method for a 200 mm wafer-scale epitaxial transfer of ultrathin (1.9 kA) single crystalline Si on Pyrex glass. Standard back-end-of-line 3 kA SiN/3 kA undoped silicon glass passivating films were used as the buffer layers between the silicon-on-insulator wafer and the glass wafer. The quality and strain-free state of the transferred transparent Si film to glass was characterized by cross-sectional transmission electron microscopy, x-ray diffraction (XRD), and high-resolution XRD. Complete removal of the bulk Si after bonding was ascertained by Auger electron spectroscopy spectra and depth profiling. Strong adhesion between the transferred film and the glass wafer was verified by standard tape adhesion tests. This process will pave the way for future generations of Si-based microelectronics including bioelectronics.

Teh, W.H.; Trigg, Alastair; Tung, C.H.; Kumar, R.; Balasubramanian, N.; Kwong, D.L. [Semiconductor Process Technologies Laboratory, Institute of Microelectronics (IME), 11 Science Park Road, Singapore Science Park II, Singapore 117685 (Singapore)

2005-08-15

44

Transformable functional nanoscale building blocks with wafer-scale silicon nanowires.  

PubMed

Through the fusion of electrostatics and mechanical dynamics, we demonstrate a transformable silicon nanowire (SiNW) field effect transistor (FET) through a wafer-scale top-down approach. By felicitously taking advantage of the proposed electrostatic SiNW-FET with mechanically movable SiNWs, all essential logic gates, including address decoders, can be monolithically integrated into a single device. The unification of various functional devices, such as pn-diodes, FETs, logic gates, and address decoders, can therefore eliminate the complex fabrication issues associated with nanoscale integration. These results represent a step toward the creation of multifunctional and flexible nanoelectronics. PMID:21254772

Choi, Sung-Jin; Ahn, Jae-Hyuk; Han, Jin-Woo; Seol, Myeong-Lok; Moon, Dong-Il; Kim, Sungho; Choi, Yang-Kyu

2011-01-21

45

Wafer-scale microdevice transfer\\/interconnect: its application in an AFM-based data-storage system  

Microsoft Academic Search

We have developed a robust, CMOS back end of the line (BEOL) compatible, wafer-scale device transfer, and interconnect method for batch fabricating systems on chip that are especially suitable for MEMS or VLSI-MEMS applications. We have applied this method to transfer arrays of 4096 free-standing cantilevers with good cantilever flatness control and high-density vertical electrical interconnects to the receiver wafer

Michel Despont; Ute Drechsler; R. Yu; H. B. Pogge; P. Vettiger

2004-01-01

46

A Wafer-Scale Etching Technique for High Aspect Ratio Implantable MEMS Structures  

PubMed Central

Microsystem technology is well suited to batch fabricate microelectrode arrays, such as the Utah electrode array (UEA), intended for recording and stimulating neural tissue. Fabrication of the UEA is primarily based on the use of dicing and wet etching to achieve high aspect ratio (15:1) penetrating electrodes. An important step in the array fabrication is the etching of electrodes to produce needle-shape electrodes with sharp tips. Traditional etching processes are performed on a single array, and the etching conditions are not optimized. As a result, the process leads to variable geometries of electrodes within an array. Furthermore, the process is not only time consuming but also labor-intensive. This report presents a wafer-scale etching method for the UEA. The method offers several advantages, such as substantial reduction in the processing time, higher throughput and lower cost. More importantly, the method increases the geometrical uniformity from electrode to electrode within an array (1.5 ± 0.5 % non-uniformity), and from array to array within a wafer (2 ± 0.3 % non-uniformity). Also, the etching rate of silicon columns, produced by dicing, are studied as a function of temperature, etching time and stirring rate in a nitric acid rich HF-HNO3 solution. These parameters were found to be related to the etching rates over the ranges studied and more-importantly affect the uniformity of the etched silicon columns. An optimum etching condition was established to achieve uniform shape electrode arrays on wafer-scale.

Bhandari, R; Negi, S; Rieth, L.; Solzbacher, F

2010-01-01

47

Wafer-scale high-throughput ordered growth of vertically aligned ZnO nanowire arrays.  

PubMed

This article presents an effective approach for patterned growth of vertically aligned ZnO nanowire (NW) arrays with high throughput and low cost at wafer scale without using cleanroom technology. Periodic hole patterns are generated using laser interference lithography on substrates coated with the photoresist SU-8. ZnO NWs are selectively grown through the holes via a low-temperature hydrothermal method without using a catalyst and with a superior control over orientation, location/density, and as-synthesized morphology. The development of textured ZnO seed layers for replacing single crystalline GaN and ZnO substrates extends the large-scale fabrication of vertically aligned ZnO NW arrays on substrates of other materials, such as polymers, Si, and glass. This combined approach demonstrates a novel method of manufacturing large-scale patterned one-dimensional nanostructures on various substrates for applications in energy harvesting, sensing, optoelectronics, and electronic devices. PMID:20681617

Wei, Yaguang; Wu, Wenzhuo; Guo, Rui; Yuan, Dajun; Das, Suman; Wang, Zhong Lin

2010-09-01

48

Materials for LIGA products  

Microsoft Academic Search

The LIGA process which is based on a combination of deep lithography and replication processes, allows one to generate three dimensional microstructures from metals, polymers, glasses and ceramic materials. Accordingly, application specific materials can be chosen for a wide variety of LIGA microdevices to be utilized for example in information and communication technology, chemical engineering, automation and robotics, environmental engineering

W. Ehrfeld; M. Abraham; U. Ehrfeld; M. Lacher; H. Lehr

1994-01-01

49

Wafer scale imprint uniformity evaluated by LSPR spectroscopy: a high volume characterization method for nanometer scale structures.  

PubMed

We exploit the localized surface-plasmon resonance (LSPR) of terahertz gold gammadion structures for wafer scale critical dimension metrology of nanostructures. The proposed characterization method, LSPR spectroscopy, is based on optical transmission measurements and is benchmarked against numerical simulations of imprinted structures characterized by atomic force microscopy. There is a fair agreement between the two methods and the simulations enable the translation of optical spectra to critical dimensions of the physical structures, a concept known from scatterometry. The results demonstrate the potential of LSPR spectroscopy as an alternative characterization method to scanning electron microscopy, atomic force microscopy and scatterometry. PMID:22948403

Jeppesen, Claus; Lindstedt, Daniel Nilsson; Vig, Asger Laurberg; Kristensen, Anders; Mortensen, N Asger

2012-09-05

50

Wafer scale imprint uniformity evaluated by LSPR spectroscopy: a high volume characterization method for nanometer scale structures  

NASA Astrophysics Data System (ADS)

We exploit the localized surface-plasmon resonance (LSPR) of terahertz gold gammadion structures for wafer scale critical dimension metrology of nanostructures. The proposed characterization method, LSPR spectroscopy, is based on optical transmission measurements and is benchmarked against numerical simulations of imprinted structures characterized by atomic force microscopy. There is a fair agreement between the two methods and the simulations enable the translation of optical spectra to critical dimensions of the physical structures, a concept known from scatterometry. The results demonstrate the potential of LSPR spectroscopy as an alternative characterization method to scanning electron microscopy, atomic force microscopy and scatterometry.

Jeppesen, Claus; Nilsson Lindstedt, Daniel; Laurberg Vig, Asger; Kristensen, Anders; Asger Mortensen, N.

2012-09-01

51

Stress analysis of lead-free solders with under bump metallurgy in a wafer level chip scale package  

Microsoft Academic Search

The wafer level chip scale assembly (WLCSP) has increasingly become popular due to its compact, wafer scale assembly. In a WLCSP assembly, the under bump metallurgy (UBM) connecting the solder joints and the chip is crucial for the assembly reliability. This study focuses on a WLCSP with 96.5Sn3.5Ag\\/95.5Sn3.8Ag0.7Cu solder joints and Ti\\/Cu\\/Ni UBM on a 2–layer microvia build-up electric board.

S. C. Tseng; R. S. Chen; C. C. Lio

2006-01-01

52

Wafer-scale fabrication of silicon nanowire arrays with controllable dimensions  

NASA Astrophysics Data System (ADS)

A novel and facile method was successfully developed to fabricate wafer-scale Si nanowire arrays with well-controlled sizes through the in-situ porous anodic alumina (PAA) template-assisted wet-etching process. The diameter and filling ratio (inter-wire spacing) of the as-prepared Si nanowires are determined by the size and density of pores in the in-situ PAA templates, which can be tailored independently by adjusting the anodization voltages and the immersion time of PAA templates in phosphoric acid. The length of Si nanowires can be more than one hundred micrometers long, which is controlled by adjusting the wet-etching time. Moreover, this method is compatible with complex Si surface topology for creating desirable 3-dimensional hybrid micro/nano-structures. Such Si nanowire arrays exhibit ultralow reflectance and interesting wettability that are of great importance to photovoltaics and thermal management applications.

Wang, Wei; Li, Dan; Tian, Miao; Lee, Yung-Cheng; Yang, Ronggui

2012-09-01

53

Wafer scale nano-membranes supported on a silicon microsieve using thin-film transfer technology  

NASA Astrophysics Data System (ADS)

A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independent of the thin film, which is later transferred onto it by fusion bonding, thus providing flexibility in design and processing steps. Using this thin-film transfer technique, nano-membranes down to 50 nm thickness are fabricated. The fabrication of different kinds of membranes made of inorganic, metallic and polymer materials is presented here. Apart from dense nano-membranes, perforated membranes are fabricated using this modular approach. One of the main areas of interest for such membranes is in fluidics, where the low thickness and high strength of the supported nano-membranes are a big advantage.

Unnikrishnan, Sandeep; Jansen, Henri; Berenschot, Erwin; Elwenspoek, Miko

2008-06-01

54

Overview of LIGA Microfabrication  

NASA Astrophysics Data System (ADS)

This paper is an overview of the LIGA technique, an increasingly accepted approach for fabricating metal, ceramic or plastic microdevices. The LIGA technique was invented in Germany in the early 1980s and the acronym derives from the words LIthographie, Galvanoformung, Abformung meaning Lithography, Electroplating, and Molding in English. The paper is presented as an abbreviated set of annotated overheads used for the conference presentation and some summary remarks.

Hruby, Jill

2002-08-01

55

Effect of UBM and BCB layers on the thermo-mechanical reliability of wafer level chip scale package (WLCSP)  

Microsoft Academic Search

Cracking of the silicon chip of a wafer level chip scale package (WLCSP) is encountered during a thermal cycle test (TCT). This paper attempts to examine the failure mechanism. Both numerical and experimental efforts were devoted to investigate the problem. A series of finite element models with different combinations of material properties and geometric configurations were developed. The results showed

Y. S. Chan; S. W. Ricky Lee; F. Song; C. C. Jeffery Lo; T. Jiang

2009-01-01

56

Wafer-scale nanopatterning and translation into high-performance piezoelectric nanowires.  

PubMed

The development of a facile method for fabricating one-dimensional, precisely positioned nanostructures over large areas offers exciting opportunities in fundamental research and innovative applications. Large-scale nanofabrication methods have been restricted in accessibility due to their complexity and cost. Likewise, bottom-up synthesis of nanowires has been limited in methods to assemble these structures at precisely defined locations. Nanomaterials such as PbZr(x)Ti(1-x)O(3) (PZT) nanowires (NWs)--which may be useful for nonvolatile memory storage (FeRAM), nanoactuation, and nanoscale power generation--are difficult to synthesize without suffering from polycrystallinity or poor stoichiometric control. Here, we report a novel fabrication method which requires only low-resolution photolithography and electrochemical etching to generate ultrasmooth NWs over wafer scales. These nanostructures are subsequently used as patterning templates to generate PZT nanowires with the highest reported piezoelectric performance (d(eff) ? 145 pm/V). The combined large-scale nanopatterning with hierarchical assembly of functional nanomaterials could yield breakthroughs in areas ranging from nanodevice arrays to nanodevice powering. PMID:20939584

Nguyen, Thanh D; Nagarah, John M; Qi, Yi; Nonnenmann, Stephen S; Morozov, Anatoli V; Li, Simonne; Arnold, Craig B; McAlpine, Michael C

2010-10-12

57

Assembly of LIGA using Electric Fields  

SciTech Connect

The goal of this project was to develop a device that uses electric fields to grasp and possibly levitate LIGA parts. This non-contact form of grasping would solve many of the problems associated with grasping parts that are only a few microns in dimensions. Scaling laws show that for parts this size, electrostatic and electromagnetic forces are dominant over gravitational forces. This is why micro-parts often stick to mechanical tweezers. If these forces can be controlled under feedback control, the parts could be levitated, possibly even rotated in air. In this project, we designed, fabricated, and tested several grippers that use electrostatic and electromagnetic fields to grasp and release metal LIGA parts. The eventual use of this tool will be to assemble metal and non-metal LIGA parts into small electromechanical systems.

FEDDEMA, JOHN T.; WARNE, LARRY K.; JOHNSON, WILLIAM A.; OGDEN, ALLISON J.; ARMOUR, DAVID L.

2002-04-01

58

Cascading wafer-scale integrated graphene complementary inverters under ambient conditions.  

PubMed

The fundamental building blocks of digital electronics are logic gates which must be capable of cascading such that more complex logic functions can be realized. Here we demonstrate integrated graphene complementary inverters which operate with the same input and output voltage logic levels, thus allowing cascading. We obtain signal matching under ambient conditions with inverters fabricated from wafer-scale graphene grown by chemical vapor deposition (CVD). Monolayer graphene was incorporated in self-aligned field-effect transistors in which the top gate overlaps with the source and drain contacts. This results in full-channel gating and leads to the highest low-frequency voltage gain reported so far in top-gated CVD graphene devices operating in air ambient, A(v) ? -5. Such gain enabled logic inverters with the same voltage swing of 0.56 V at their input and output. Graphene inverters could find their way in realistic applications where high-speed operation is desired but power dissipation is not a concern, similar to emitter-coupled logic. PMID:22793169

Rizzi, Laura Giorgia; Bianchi, Massimiliano; Behnam, Ashkan; Carrion, Enrique; Guerriero, Erica; Polloni, Laura; Pop, Eric; Sordan, Roman

2012-07-13

59

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy.  

PubMed

The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures ("metasurfaces") can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

Wang, Dongxing; Zhu, Wenqi; Best, Michael D; Camden, Jon P; Crozier, Kenneth B

2013-10-04

60

Wafer-scale pattern transfer of metal nanostructures on polydimethylsiloxane (PDMS) substrates via holographic nanopatterns.  

PubMed

In this paper, we report on a cost-effective and simple, nondestructive pattern transfer method that allows the fabrication of metallic nanostructures on a polydimethylsiloxane (PDMS) substrate on a wafer scale. The key idea is to use holographic nanopatterns of a photoresist (PR) layer as template structures, where a metal film is directly deposited in order to replicate the nanopatterns of the PR template layer. Then, the PDMS elastomer is molded onto the metal film and the metal/PDMS composite layer is directly peeled off from the PR surface. Many metallic materials including Ti, Al, and Ag were successfully nanopatterned on PDMS substrates by the pattern transfer process with no use of any adhesion promoter layer or coating. In case of Au that has poor adhesion to PDMS material, a salinization of the metal surface with 3-(aminopropyl)-triethoxysilane (APTES) monolayer promoted the adhesion and led to successful pattern transfer. A series of adhesion tests confirmed the good adhesion of the transferred metal films onto the molded PDMS substrates, including scotch-tape and wet immersion tests. The inexpensive and robust pattern transfer approach of metallic nanostructures onto transparent and flexible PDMS substrates will open the new door for many scientific and engineering applications such as micro-/nanofluidics, optofluidics, nanophotonics, and nanoelectronics. PMID:23020206

Du, Ke; Wathuthanthri, Ishan; Liu, Yuyang; Xu, Wei; Choi, Chang-Hwan

2012-10-10

61

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy  

NASA Astrophysics Data System (ADS)

The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (``metasurfaces'') can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent.

Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

2013-10-01

62

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy  

PubMed Central

The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (“metasurfaces”) can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent.

Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

2013-01-01

63

High throughput ultralong (20 cm) nanowire fabrication using a wafer-scale nanograting template.  

PubMed

Nanowires are being actively explored as promising nanostructured materials for high performance flexible electronics, biochemical sensors, photonic applications, solar cells, and secondary batteries. In particular, ultralong (centimeter-long) nanowires are highly attractive from the perspective of electronic performance, device throughput (or productivity), and the possibility of novel applications. However, most previous works on ultralong nanowires have issues related to limited length, productivity, difficult alignment, and deploying onto the planar substrate complying with well-matured device fabrication technologies. Here, we demonstrate a highly ordered ultralong (up to 20 cm) nanowire array, with a diameter of 50 nm (aspect ratio of up to 4,000,000:1), in an unprecedented large (8 in.) scale (2,000,000 strands on a wafer). We first devised a perfectly connected ultralong nanograting master template on the whole area of an 8 in. substrate using a top-down approach, with a density equivalent to that achieved with e-beam lithography (100 nm). Using this large-area, ultralong, high-density nanograting template, we developed a fast and effective method for fabricating up to 20 cm long nanowire arrays on a plastic substrate, composed of metal, dielectric, oxide, and ferroelectric materials. As a suggestion of practical application, a prototype of a large-area aluminum wire grid polarizer was demonstrated. PMID:23899099

Yeon, Jeongho; Lee, Young Jae; Yoo, Dong Eun; Yoo, Kyoung Jong; Kim, Jin Su; Lee, Jun; Lee, Jeong Oen; Choi, Seon-Jin; Yoon, Gun-Wook; Lee, Dong Wook; Lee, Gi Seong; Hwang, Hae Chul; Yoon, Jun-Bo

2013-08-09

64

Electrical characterization of wafer-scale epitaxial graphene and its RF applications  

Microsoft Academic Search

High-performance graphene field-effect transistors are fabricated on two-inch graphene-on-SiC wafers. Epitaxial graphene was synthesized on SiC wafers by thermal annealing to form one to two layers of graphene. The graphene transistors possess high current density of > 1mA\\/µm, and a cut- off frequency of 170 GHz is achieved for graphene FETs with a gate length of 90 nm. These results

Yu-Ming Lin; Keith A. Jenkins; John Ott; Christos Dimitrakopoulos; Damon B. Farmer; Yanqing Wu; Alfred Grill; Phaedon Avouris

2011-01-01

65

Wafer scale synthesis of dense aligned arrays of single-walled carbon nanotubes  

Microsoft Academic Search

Here we present an easy one-step approach to pattern uniform catalyst lines for the growth of dense, aligned parallel arrays\\u000a of single-walled carbon nanotubes (SWNTs) on quartz wafers by using photolithography or polydimethylsiloxane (PDMS) stamp\\u000a microcontact printing (µCP). By directly doping an FeCl3\\/methanol solution into Shipley 1827 photoresist or polyvinylpyrrolidone (PVP), various catalyst lines can be well-patterned\\u000a on a wafer

Weiwei Zhou; Christopher Rutherglen; Peter J. Burke

2008-01-01

66

Observation of silicon front surface topographs of an ultralarge-scale-integrated wafer by synchrotron x-ray plane wave  

Microsoft Academic Search

Surface roughness and undulation of unpatterned silicon wafers are serious issues for ultralarge-scale-integrated circuit devices, even after fine mechanochemical polishing. It has never been clarified whether the undulations exist only on the surface or also exist inside the bulk crystal. We produced grazing incident diffraction topographs at three x-ray photon energies, with penetration depths estimated to be 3.85 nm, 4.78

Yoshifumi Suzuki; Yoshimitsu Tsukasaki; Kentaro Kajiwara; Seiji Kawado; Satoshi Iida; Yoshinori Chikaura

2004-01-01

67

Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies  

Microsoft Academic Search

The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by

John Lau; Chris Chang; S. W. Ricky Lee

2000-01-01

68

Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies  

Microsoft Academic Search

The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by

John H. Lau; Chris Chang; S.-W. R. Lee

2001-01-01

69

Optimal design towards enhancement of board-level thermomechanical reliability of wafer-level chip-scale packages  

Microsoft Academic Search

In this paper we study board-level thermomechanical reliability of a wafer-level chip-scale package subjected to an accelerated thermal cycling test condition. Different control factors are considered for a robust design towards enhancement of the thermal fatigue resistance of solder joints. These factors include diameter, pitch, and standoff of the solder joints, size of the solder connection opening on the die

Yi-shao Lai; Tong Hong Wang

2007-01-01

70

Effects of microvia build-up layers on the solder joint reliability of a wafer level chip scale package (WLCSP)  

Microsoft Academic Search

The effect of a 2-layer microvia build-up printed circuit board (PCB) on the solder joint reliability of a wafer level chip scale package (WLCSP) assembly subject to thermal cycling is investigated in this study. The 62Sn-2Ag-36Pb solder joints are assumed to be: (1) an elastic material; (2) an elastic-plastic material; and (3) a creep material described by the Garofalo-Arrhenius creep

John H. Lau; S.-W. R. Lee

2001-01-01

71

A low-power, small-area voltage reference array for a wafer-scale prototyping platform  

Microsoft Academic Search

A programmable voltage reference used in an advanced wafer-scale hierarchical voltage regulation circuit is presented. The novel arborescence structure of the voltage regulation system is described and the requirements for the voltage reference derived. The proposed programmable voltage reference is based on beta-multiplier architecture, implemented in 0.18 ?m CMOS technology with a very small area of 0.0014 mm2. It provides

Nicolas Laflamme-Mayer; Olivier Valorge; Yves Blaquière; Mohamad Sawan

2010-01-01

72

Toward wafer-scale fabrication and 3D integration of micro-solid oxide fuel cells for portable energy  

NASA Astrophysics Data System (ADS)

Pathways to scaling up the power and voltage output of on-chip micro-solid oxide fuel cells (?SOFC) have been investigated. ?SOFC arrays consisting of one thousand three hundred and thirty-two (1332) membranes have been lithographically fabricated on 4" wafers. The membranes, with widths of ~150 ?m, are comprised of 15-nm-thick La0.6Sr0.4Co0.8F0.2O3 (LSCF) or 100-nm-thick porous Pt cathodes, 75-nm-thick Y0.15Z0.85O1.93 (YSZ) electrolytes, and 100-nm-thick porous Pt anodes. Yield of fabrication is greater than 99% and only a few membranes failed after annealing at 500 °C. However, to reduce resistive loss, a current collector or a much thicker LSCF needs to be implemented if using LSCF as the cathode material on 4" wafers. Prototype components of ?SOFC stacks for scaling up output voltage are also presented. The stacks require only two components - namely, a ?SOFC plate and a bipolar separator - to form a repeating unit for the stacks. Flow channels and through silicon vias are integrated in the components. Challenges in fabrication and direction for further improvement for these approaches are discussed. The preliminary results suggest potential for further exploration into wafer-scale processing of fuel cell device structures for portable energy.

Lai, Bo-Kuai; Johnson, Alex C.; Tsuchiya, Masaru; Ramanathan, Shriram

2010-04-01

73

Wafer-scale near-perfect ordered porous alumina on substrates by step and flash imprint lithography.  

PubMed

Nanoporous anodic aluminum oxide (AAO) has been widely used for the development of various functional nanostructures. So far, highly ordered AAO on substrates could only be prepared using a nanoindentation method via hard stamping and lithographic techniques that are not scalable to a wafer-scale. Here we report on a step and flash imprint lithography (SFIL)-based method to fabricate a near-perfect ordered AAO with square and hexagonal lattice configuration on silicon substrate over 4 in. wafer areas. SFIL was used to prepattern a polymer mask layer, and wet-etching process was employed to transfer the nanopatterns to aluminum (Al) films, thus creating ordered nanoindentation on the Al surface. The ordered nanoindentation guides the growth of nanochannels in the anodization step to create the ordered nanoporous structures. The proposed wafer-scale process is compatible with standard semiconductor fabrication and offers substantial advantages over conventional Al patterning methods in terms of patterning areas, throughput, process simplicity, and process robustness, allowing up to 10 000 imprints or pattern transfer to the Al films. PMID:20411953

Kustandi, Tanu Suryadi; Loh, Wei Wei; Gao, Han; Low, Hong Yee

2010-05-25

74

Scaling up antimonide wafer production: innovation and challenges for epitaxy ready GaSb and InSb substrates  

NASA Astrophysics Data System (ADS)

In this paper we describe the growth and characterization of antimonide based compound semiconductor substrates. The Czochralski technique has been used to grow single crystals of 4" InSb and 4" GaSb with dislocation densities of <20/cm2 and <100/cm2, respectively. Epitaxy ready wafer surfaces have been characterized by surface microscopy and spectroscopic ellipsometry, revealing sub-nanometer levels of surface roughness (rms) and oxide coverage in the 10-50 Angstrom range. GaSb wafers with thinner oxides (<20 Angstroms) have been developed and quality assessments made by epitaxial growth testing. Surface morphology evaluations indicate high levels of surface quality, comparable to pretreated variants of the same substrate type. We also illustrate current crystal growth systems and ingot forms, and discuss the challenges associated with scaling present InSb and GaSb technologies to deliver larger substrate formats.

Furlong, Mark J.; Martinez, Rebecca; Amirhaghi, Sasson; Small, David; Smith, Brian; Mowbray, Andrew

2011-05-01

75

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays  

NASA Astrophysics Data System (ADS)

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 ?m is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 ?m × 25 ?m that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of ?3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu–Sn solid–liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

2013-09-01

76

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking  

PubMed Central

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-01-01

77

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.  

PubMed

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

78

A network flow approach to the wafer scale integration of VLSI arrays  

NASA Astrophysics Data System (ADS)

An algorithm is described for reconfiguring a 2-dimensional VLSI array on a silicon wafer that has some faulty cells. The functional cells of the array are interconnected in order to simulate a fault-free array of smaller size, where the interconnection wires are routed inside horizontal and vertical channels, according to the Manhattan model. The concept of simulation distance is introduced, and it is shown to be related to the length of the longest interconnection wire. The algorithm makes use of network flow techniques in order to find wiring with minimum simulation distance. This results in a practical heuristic for minimum simulation distance. This results in a practical heuristic for minimizing the maximum wire length. The complexity and performance of this algorithm are also discussed in the paper.

Codenotti, B.; Tamassia, R.

1985-06-01

79

Wafer-scale integration of group III-V lasers on silicon using transfer printing of epitaxial layers  

NASA Astrophysics Data System (ADS)

The hard-drive and electronic industries can benefit by using the properties of light for power transfer and signalling. However, the integration of silicon electronics with lasers remains a challenge, because practical monolithic silicon lasers are not currently available. Here, we demonstrate a strategy for this integration, using an elastomeric stamp to selectively release and transfer epitaxial coupons of GaAs to realize III-V lasers on a silicon substrate by means of a wafer-scale printing process. Low-threshold continuous-wave lasing at a wavelength of 824 nm is achieved from Fabry-Pérot ridge waveguide lasers operating at temperatures up to 100 °C. Single and multi-transverse mode devices emit total optical powers of >60 mW and support modulation bandwidths of >3 GHz. This fabrication strategy opens a route to the low-cost integration of III-V photonic devices and circuits on silicon and other substrates.

Justice, John; Bower, Chris; Meitl, Matthew; Mooney, Marcus B.; Gubbins, Mark A.; Corbett, Brian

2012-09-01

80

C- and L-band erbium-doped waveguide lasers with wafer-scale silicon nitride cavities.  

PubMed

We report on integrated erbium-doped waveguide lasers designed for silicon photonic systems. The distributed Bragg reflector laser cavities consist of silicon nitride waveguide and grating features defined by wafer-scale immersion lithography and a top erbium-doped aluminum oxide layer deposited as the final step in the fabrication process. The resulting inverted ridge waveguide yields high optical intensity overlap with the active medium for both the 0.98 ?m pump (89%) and 1.5 ?m laser (87%) wavelengths with a pump-laser intensity overlap of >93%. We obtain output powers of up to 5 mW and show lasing at widely spaced wavelengths within both the C and L bands of the erbium gain spectrum (1536, 1561, and 1596 nm). PMID:23862218

Purnawirman; Sun, J; Adam, T N; Leake, G; Coolbaugh, D; Bradley, J D B; Shah Hosseini, E; Watts, M R

2013-06-01

81

Wafer-scale processing technology for monolithically integrated GaSb thermophotovoltaic device array on semi-insulating GaAs substrate  

NASA Astrophysics Data System (ADS)

This paper presents the entire fabrication and processing steps necessary for wafer scale monolithic integration of series interconnected GaSb devices grown on semi-insulating GaAs substrates. A device array has been fabricated on complete 50 mm (2 inch) diameter wafer using standard photolithography, wet chemical selective etching, dielectric deposition and single-sided metallization. For proof of concept of the wafer-scale feasibility of this process, six large-area series interconnected GaSb p-n junction thermophotovoltaic cells with each cell consisting of 24 small-area devices have been fabricated and characterized for its electrical connectivity. The fabrication process presented in this paper can be used for optoelectronic and electronic device technologies based on GaSb and related antimonide based compound semiconductors.

Kim, Jung Min; Dutta, Partha S.; Brown, Eric; Borrego, Jose M.; Greiff, Paul

2013-06-01

82

Tapered LIGA HARMs  

NASA Astrophysics Data System (ADS)

The standard LIGA process takes advantage of the use of x-ray lithography to produce mold inserts with nearly vertical sidewall; the typical slope of patterns produced by x-ray lithography of polymethylmethacrylate is 0.1%. This lack of significant taper (draft angle) greatly increases the difficulty associated with ejecting parts during demolding. In this paper, a procedure is described to fabricate a mold insert with tapered features having a height of approximately 1 mm and lateral dimensions of approximately 300 mum. A set of six oblique exposures of a thick layer of SU-8 (an EPON epoxy based negative tone resist) is used to create hexagonal posts with a 3° draft angle. An electroforming process is used to fabricate a nickel mold insert with the tapered features. This mold insert is used to injection mold tapered polymer high aspect ratio microstructures. The dimensions of the SU-8 tapered structures (as well as the mold insert) are within 4 mum of desired/predicted values.

Turner, Ryan; Desta, Yohannes; Kelly, Kevin; Zhang, Jian; Geiger, Emil; Cortez, Steve; Mancini, Derrick C.

2003-05-01

83

LIGA Micromachining Activities and Presentation  

NSDL National Science Digital Library

The Southwest Center for Microsystems Education is a Regional Advanced Technology Education Center funded in part by the National Science Foundation. This page provides a powerpoint presentation as well as instructor and participant guides for the LIGA Micromachining Simulation Kit. An order form is provided to order this kit complete with most of the materials needed to simulate the lithography and electroforming steps of the LIGA process. Visitors are encouraged to create an account and login in order to access the full set of resources.

2011-10-11

84

Activities of LIGA and Nano LIGA Technologies at BSRF  

Microsoft Academic Search

Beijing Synchrotron Radiation Facility (BSRF ) is a partly dedicated synchrotron radiation ( SR) source operated in either parasitic or dedicated mode. LIGA research at BSRF started from 1993 and focused in the first two steps of deep X-ray lithography and electroplating. Scanning exposure chamber of deep X-ray lithography was first built in 1996 on a 3W1 wiggler beamline with

F. Yi; J. Zhang; C. Xie; D. Wang; D. Chen

2006-01-01

85

Integrated Platform for Testing MEMS Mechanical Properties at the Wafer Scale by the IMaP Methodology.  

National Technical Information Service (NTIS)

A new instrument to accurately and verifiably measure mechanical properties across an entire microelectromechanical systems (MEMS) wafer is under development. We have modified the optics on a conventional microelectronics probe station to enable three-dim...

M. P. de Boer N. F. Smith N. D. Masters M. B. Sinclair E. J. Pryputniewicz

2001-01-01

86

Wafer-scale graphene/ferroelectric hybrid devices for low-voltage electronics  

NASA Astrophysics Data System (ADS)

Preparing graphene and its derivatives on functional substrates may open enormous opportunities for exploring the intrinsic electronic properties and new functionalities of graphene. However, efforts in replacing SiO2 have been greatly hampered by a very low sample yield of the exfoliation and related transferring methods. Here, we report a new route in exploring new graphene physics and functionalities by transferring large-scale chemical-vapor deposition single-layer and bilayer graphene to functional substrates. Using ferroelectric Pb(Zr0.3Ti0.7)O3 (PZT), we demonstrate ultra-low-voltage operation of graphene field effect transistors within ±1 V with maximum doping exceeding 1013 cm- 2 and on-off ratios larger than 10 times. After polarizing PZT, switching of graphene field effect transistors are characterized by pronounced resistance hysteresis, suitable for ultra-fast non-volatile electronics.

Zheng, Yi; Ni, Guang-Xin; Bae, Sukang; Cong, Chun-Xiao; Kahya, Orhan; Toh, Chee-Tat; Kim, Hye Ri; Im, Danho; Yu, Ting; Ahn, Jong Hyun; Hong, Byung Hee; Özyilmaz, Barbaros

2011-01-01

87

Wafer-scale laser lithography. I. Pyrolytic deposition of metal microstructures. [For ultra-large scale integrated circuits  

SciTech Connect

Mechanisms for laser-driven pyrolytic deposition of micron-scale metal structures on crystalline silicon have been studied. Models have been developed to predict temporal and spatial propeties of laser-induced pyrolytic deposition processes. An argon ion laser-based apparatus has been used to deposit metal by pyrolytic decomposition of metal alkyl and carbonyl compounds, in order to evaluate the models. These results of these studies are discussed, along with their implications for the high-speed creation of micron-scale metal structures in ultra-large scale integrated circuit systems. 4 figures.

Herman, I.P.; Hyde, R.A.; McWilliams, B.M.; Weisberg, A.H.; Wood, L.L.

1982-01-01

88

Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)  

Microsoft Academic Search

The creep analyses of solder-bumped wafer level chip scale packages (WLCSP) on build-up printed circuit boards (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the conventional PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder

John H. Lau; S.-W. R. Lee

2000-01-01

89

Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)  

Microsoft Academic Search

The creep analyses of solder-bumped wafer level chip scale package (WLCSP) on build-up printed circuit board (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints

John H. Lau; S.-W. R. Lee

2002-01-01

90

Wafer-scale microdevice transfer\\/interconnect: from a new integration method to its application in an afm-based data-storage system  

Microsoft Academic Search

We have developed a robust, CMOS back end of the line (BEOL) compatible, wafer-scale device transfer and interconnect method for batch fabricating system on chip (SOC) that are especially suitable for MEMS or VLSI-MEMS applications. We have applied this method to transfer arrays of 4096 freestanding cantilevers with good cantilever flatness control and high-density vertical electrical interconnects to the receiver

M. Despont; U. Drechsler; R. Yu; H. B. Pogge; P. Vettiger

2003-01-01

91

Modeling electrodeposition for LIGA microdevice fabrication  

SciTech Connect

To better understand and to help optimize the electroforming portion of the LIGA process, we have developed one and two-dimensional numerical models describing electrode-position of metal into high aspect-ratio molds. The one-dimensional model addresses dissociation, diffusion, electromigration, and deposition of multiple ion species. The two-dimensional model is limited to a single species, but includes transport induced by forced flow of electrolyte outside the mold and by buoyancy associated with metal ion depletion within the mold. To guide model development and to validate these models, we have also conducted a series of laboratory experiments using a sulfamate bath to deposit nickel in cylindrical molds having aspect ratios up to twenty-five. The experimental results indicate that current densities well in excess of the diffusion-limited currents may still yield metal deposits of acceptable morphology. However, the numerical models demonstrate that such large ion fluxes cannot be sustained by convection within the mold resulting from flow across the mold top. Instead, calculations suggest that the observed enhancement of transport probably results from natural convection within the molds, and that buoyancy-driven flows may be critical to metal ion transport even in micron-scale features having very large aspect ratios. Taking advantage of this enhanced ion transport may allow order-of-magnitude reductions in electroforming times for LIGA microdevice fabrication. 42 refs., 14 figs., 1 tab.

Griffiths, S.K.; Nilson, R.H.; Bradshaw, R.W. [and others

1998-02-01

92

Wafer Scale Distributed Radio.  

National Technical Information Service (NTIS)

Modem silicon technology offers ultrafast transistors, with fT > 200 GHz in today's 45nm CMOS and fT > 300 GHz in SiGe. While extremely fast, these transistors suffer from several limitations which affect the performance of high dynamic range analog and R...

A. M. Niknejad B. Nikolic E. Alon J. Rabaey

2009-01-01

93

MUSE - a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer-scale integration. Technical report  

SciTech Connect

This report describes an architecture for a highly parallel system of computational processors specialized for real-time adaptive antenna nulling computations with many degrees of freedom, which we call MUSE (Matrix Update Systolic Experiment), and a specific realization of MUSE for 64 degrees of freedom. Each processor uses the CORDIC algorithm and has been designed as a single integrated circuit. Ninety-six such processors working together can update the 64-element nulling weights based on 300 new observations in only 6.7 milliseconds. This is equivalent to 2.88 Giga-ops for a conventional processor. The computations are accurate enough to support 50 decibel of signal-to-noise improvement in a sidelobe canceller. The connectivity between processors is quite simple and permits MUSE to be realized on a single large wafer, using restructurable VLSI (Very Large Scale Integration). The complete design of such a wafer is described.

Rader, C.M.; Allen, D.L.; gLASCO , D.B.; Woodward, C.E.

1990-05-18

94

Photoluminescence of Single GaN/InGaN Nanorod Light Emitting Diode Fabricated on a Wafer Scale  

NASA Astrophysics Data System (ADS)

Nanorod arrays were fabricated on a blue InGaN/GaN single quantum well (QW) LED wafer using nanoimprint lithography. A regular hexagonal lattice of nanorods was made at a pitch of 2 ?m producing single quantum disks in the nanorods with diameter of ˜400 nm. Time integrated micro-photoluminescence was performed to investigate the emission properties of top down processed single nanorods at 4.2 K. Micro-photoluminescence maps were made to study the spatial isolation of the photoluminescence emission, showing a good contrast ratio between nanorods. Excitation power dependent studies show screening of the quantum confined Stark effect for both the unprocessed wafer and the single nanorod. At low excitation powers, localised states appearing as sharp peaks in the photoluminescence spectrum were visible with a density of approximately four peaks per nanorod.

Chan, Christopher C. S.; Zhuang, YiDing; Reid, Benjamin P. L.; Jia, Wei; Holmes, Mark J.; Alexander-Webber, Jack A.; Nakazawa, Shingo; Shields, Philip A.; Allsopp, Duncan W. E.; Taylor, Robert A.

2013-08-01

95

A practical, flip-chip, multi-layer pre-encapsulation technology for wafer-scale underfill  

Microsoft Academic Search

This paper describes the conception, development, and application of a novel materials set and methodology for fabricating assembly-ready flip chips pre-encapsulated, at the wafer level, with a low coefficient of thermal expansion (CTE) underfill. This technology is unique in that it addresses a key challenge currently facing the high density interconnect (HDI) electronics industry-how to produce cost-effectively, in a streamlined

Robert V. Burress; M. Albert Capote; Yong-Joon Lee; Howard A. Lenos; Jeffrey F. Zamora

2001-01-01

96

A 5 mm ×5 mm ×1.37 mm hermetic FBAR duplexer for PCS handsets with wafer-scale packaging  

Microsoft Academic Search

We describe the design and measured performance of a 5 mm ×5 mm ×1.37 mm antenna duplexer for the U.S. PCS band (Tx: 1850-1910 MHz, Rx: 1930-1990 MHz) for cellular handsets based on FBAR (film acoustic resonator) technology. The FBARs are fabricated in a silicon-based IC process technology and are hermetically sealed in a wafer-level packaging process. Two dice, Tx

P. D. Bradley; R. Ruby; A. Barfknecht; F. Geefay; C. Han; G. Gan; Y. Oshmyansky

2002-01-01

97

Computer simulation for estimation of dislocation multiplication due to gravitational stress: challenges and opportunities toward slip-free 300-mm-diameter silicon wafers for ultralarge-scale integr  

Microsoft Academic Search

Considering the coming 300-mm-dia Si wafer era (beyond 0.25 - 0.18 micrometers design rule in MOS devices), occurrence of slip dislocations along directions due to gravitational stress at supporting jigs is still one of the biggest crucial issues in manufacturing ultra-large-scale- integration circuits. This paper describes how to predict slip dislocation onset under gravitational stress upon heat- treating 300-mm-dia wafers.

Hirofumi Shimizu; Seiichi Isomae; Kyoko Minowa; Tomomi Satoh

1997-01-01

98

Laser wafering for silicon solar.  

SciTech Connect

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

99

Producing LIGA-competitive microcomponents  

NASA Astrophysics Data System (ADS)

This paper presents a new technique to investigate deep microfeatures, and an alternative process to produce micro components. Micro-EDM and focused ion beam micromachining were combined to directly fabricate the mold features. The first process was to remove the bulk material while the later was to produce intricate details and improve the surface integrity. To investigate the effects of ion beam parameters on the mold material, nickel beryllium blocks were first ground, polished then mechanically clamped together. A focused ion beam using Ga+ ions was used to produce deep microfeatures at the block interfaces, after which the blocks were separated and the in-situ cross sections were examined. The parameters used were varied in the ranges of 30-50 kV accelerating voltage, 2-150 nC/micrometers 2 dose, and 5-7000 pA beam current by either dry sputtering or gas-assisted etching. LIGA-competitive features were achieved. Selection of Ni-Be was made sine its mechanical properties were superior to those of pure nickel used in the LIGA process. This ensured a longer mold life when one repeatedly injecting a hot/abrasive polymer to the mold cavity to fabricate 3D micro components in production. Feature obtained with Ni-Be had surface finish approximately 10 nm, accuracy < micrometers , and aspect ratio > 10. Preliminary work showed the success of this technique with micro molded plastics components.

Hung, Wayne N.; Ali, Mohammed Y.; Yuan, Shu

2000-08-01

100

Highly uniform 300 mm wafer-scale deposition of single and multilayered chemically derived graphene thin films.  

PubMed

The deposition of atomically thin highly uniform chemically derived graphene (CDG) films on 300 mm SiO(2)/Si wafers is reported. We demonstrate that the very thin films can be lifted off to form uniform membranes that can be free-standing or transferred onto any substrate. Detailed maps of thickness using Raman spectroscopy and atomic force microscopy height profiles reveal that the film thickness is very uniform and highly controllable, ranging from 1-2 layers up to 30 layers. After reduction using a variety of methods, the CDG films are transparent and electrically active with FET devices yielding high mobilities of approximately 15 cm(2)/(V s) and sheet resistance of approximately 1 kOmega/sq at approximately 70% transparency. PMID:20050640

Yamaguchi, Hisato; Eda, Goki; Mattevi, Cecilia; Kim, Hokwon; Chhowalla, Manish

2010-01-26

101

Silicon Wafer Epitaxy  

NSDL National Science Digital Library

This Quicktime animation shows an optional process for creating silicon epitaxial wafers. The animations shows a trichlorosilane gas being injected which creates a monocrystaline film atop the preexisting wafer. This is the seventh animation in a series of how silicon wafers are created. The previous animation showing silicon wafer polishing can be seen here.The next and final animation in this sequence about silicon wafer laser inspection can be seen here.

2009-10-19

102

Fast and robust hydrogen sensors based on discontinuous palladium films on polyimide, fabricated on a wafer scale  

NASA Astrophysics Data System (ADS)

Fast hydrogen sensors based on discontinuous palladium (Pd) films on supporting polyimide layers, fabricated by a cost-efficient and full-wafer compatible process, are presented. The films, deposited by electron-beam evaporation with a nominal thickness of 1.5 nm, consist of isolated Pd islands that are separated by nanoscopic gaps. On hydrogenation, the volume expansion of Pd brings initially separated islands into contact which leads to the creation of new electrical pathways through the film. The supporting polyimide layer provides both sufficient elasticity for the Pd nanoclusters to expand on hydrogenation and a sufficiently high surface energy for good adhesion of both film and contacting electrodes. The novel order of the fabrication processes involves a dicing step prior to the Pd deposition and stencil lithography for the patterning of microelectrodes. This allows us to preserve the as-deposited film properties. The devices work at room temperature, show response times of a few seconds and have a low power consumption of some tens of nW.

Kiefer, T.; Villanueva, L. G.; Fargier, F.; Favier, F.; Brugger, J.

2010-12-01

103

Fast and robust hydrogen sensors based on discontinuous palladium films on polyimide, fabricated on a wafer scale.  

PubMed

Fast hydrogen sensors based on discontinuous palladium (Pd) films on supporting polyimide layers, fabricated by a cost-efficient and full-wafer compatible process, are presented. The films, deposited by electron-beam evaporation with a nominal thickness of 1.5 nm, consist of isolated Pd islands that are separated by nanoscopic gaps. On hydrogenation, the volume expansion of Pd brings initially separated islands into contact which leads to the creation of new electrical pathways through the film. The supporting polyimide layer provides both sufficient elasticity for the Pd nanoclusters to expand on hydrogenation and a sufficiently high surface energy for good adhesion of both film and contacting electrodes. The novel order of the fabrication processes involves a dicing step prior to the Pd deposition and stencil lithography for the patterning of microelectrodes. This allows us to preserve the as-deposited film properties. The devices work at room temperature, show response times of a few seconds and have a low power consumption of some tens of nW. PMID:21098952

Kiefer, T; Villanueva, L G; Fargier, F; Favier, F; Brugger, J

2010-11-23

104

Measurement Sites for Wafer Map Visualization and Process Monitoring  

NASA Astrophysics Data System (ADS)

This paper proposes measurement site selection to visualize a wafer characterization map and also monitor wafer-to-wafer and batch-to-batch variation. In the manufacturing line of thin film devices such as large-scale integrated circuits, magnetic heads of hard disk drives and thin-film-transistor substrates of liquid-crystal projectors, several critical dimensions are generally measured and monitored for quality control. To monitor wafer-to-wafer and batch-to-batch variation, engineers control average and standard deviation of measured dimensions as statistical process control. To monitor characterization across a wafer, the engineers observe an sculptured surface as a wafer map. The paper presents a selection method to decide measurement sites across a wafer for both of the wafer map visualization and the process monitoring and examines their accuracies experimentally.

Ono, Makoto; Hayashi, Hirohito; Kondo, Akira; Hamaguchi, Daisuke; Kaneko, Shun'ichi

105

Scheduling semiconductor wafer fabrication  

Microsoft Academic Search

The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer

LAWRENCE M. WEIN

1988-01-01

106

Silicon Wafer Polishing  

NSDL National Science Digital Library

This Quicktime animation demostrates the final polishing and cleaning processes required for creating semiconductor devices and integrated circuits. This animation is the sixth in a series of how silicon wafers are created. The previous animation showing silicon wafer lapping can be seen here. The next animation in this sequence about the optional silicon wafer epitaxy process can be seen here.

2009-10-21

107

Hydrophobic silicon wafer bonding  

Microsoft Academic Search

Silicon wafers with hydrophilic surfaces can be bonded at room temperature (RT). This has been attributed to the presence of OH groups on the mating surfaces that form hydrogen bonds between the two wafers.19 Hydrophobic Si wafers prepared by a dip in diluted HF without subsequent water rinse have shown a similar RT bonding performance.3 Dispersion van der Waals forces

Q.-Y. Tong; E. Schmidt; U. Gösele; M. Reiche

1994-01-01

108

Silicon Wafer Lapping  

NSDL National Science Digital Library

This Quicktime animation shows how the machining process of "lapping" removes controlled amounts of silicon from a wafer in order to ensure flatness of the silicon wafer. This process removes particles and improves the quality of the wafer after they are cut. This animation is the fifth in a series of how silicon wafers are created.The previous animation showing silicon ingot edge profiling can be seen here.The next animation in this sequence about silicon wafer polishing can be seen here.

2010-02-08

109

Microdisplay wafer-flatness metrology by optical interferometry  

Microsoft Academic Search

We report a microdisplay wafer-flatness metrology technique based on digital high-pass filtering of topography data obtained from a commercial optical interferometer. This technique dis- criminates against both wafer-scale bow\\/warp and pixel-scale roughness to reveal die-scale flatness variations that are the most relevant to microdisplay gap uniformity. We report flatness measurements of a variety of live and test silicon wafers supporting

Christopher M. Walker; Mark Handschy

2001-01-01

110

Semiconductor Wafer Bonding  

Microsoft Academic Search

When mirror-polished, flat, and clean wafers of almost any material are brought into contact at room temperature, they are locally attracted to each other by van der Waals forces and adhere or bond. This phenomenon is referred to as wafer bonding. The most prominent applications of wafer bonding are silicon-on-insulator (SOI) devices, silicon-based sensors and actuators, as well as optical

U. Gosele; Q.-Y. Tong

1998-01-01

111

Modeling and analysis of 96.5Sn3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board  

Microsoft Academic Search

In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive

John H. Lau; S.-W. R. Lee

2002-01-01

112

PERFORATED WAFER FUEL ELEMENTS  

Microsoft Academic Search

A method of compacting perforated wafers from a mixture of stainless ; steel and 30 wt.% UOâ its described. A die containing 68 core pins was ; constructed tc compact wafers 5\\/8 in. square, 1\\/4 in. thick containing 68 holes. ; These holes are 0.068 in. in diameter and the distance between adjacent holes is ; 0.012 in. From results

H. S. Kalish; E. N. Mazza; G. Zuromsky

1954-01-01

113

Semiconductor wafer bonding  

Microsoft Academic Search

When mirror-polished, flat, and clean wafers are brought into contact, they are locally attracted to each other and adhere or bond. This phenomenon is known as semiconductor wafer bonding. Different adhesion forces (van der Waals forces, hydrogen bonding) are the reason for the bonding effect at room temperature. The different bonding mechanisms acting in dependence on the surface conditions (hydrophilic,

M. Reiche

2006-01-01

114

Wafer scale micromachine assembly method  

DOEpatents

A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.

Christenson, Todd R. (Albuquerque, NM)

2001-01-01

115

Mechanical properties of wear tested LIGA nickel.  

SciTech Connect

Strength, friction, and wear are dominant factors in the performance and reliability of materials and devices fabricated using nickel based LIGA and silicon based MEMS technologies. However, the effects of frictional contacts and wear on long-term performance of microdevices are not well-defined. To address these effects on performance of LIGA nickel, we have begun a program employing nanoscratch and nanoindentation. Nanoscratch techniques were used to generate wear patterns using loads of 100, 200, 500, and 990 {micro}N with each load applied for 1, 2, 5, and 10 passes. Nanoindentation was then used to measure properties in each wear pattern correcting for surface roughness. The results showed a systematic increase in hardness with applied load and number of nanoscratch passes. The results also showed that the work hardening coefficient determined from indentation tests within the wear patterns follows the results established from tensile tests, supporting use of a nanomechanics-based approach for studying wear.

Jungk, John Michael (University of Minnesota, Minneapolis, MN); Prasad, Somuri V. (Sandia National Laboratories, Albuquerque, NM); Gerberich, William W. (University of Minnesota, Minneapolis, MN); Moody, Neville Reid; Kennedy, Marian S. (Washington State University, Pullman, WA); Bahr, David F. (Washington State University, Pullman, WA)

2005-03-01

116

Optical measurement of LIGA milliengine performance  

SciTech Connect

Understanding the parameters that affect the performance of milliscale and microscale actuators is essential to the development of optimized designs and fabrication processes, as well as the qualification of devices for commercial applications. This paper discusses the development of optical techniques for motion measurements of LIGA fabricated milliengines. LIGA processing permits the fabrication of precision millimeter-sized machine elements that cannot be fabricated by conventional miniature machining techniques because of their small feature sizes. In addition, tolerances of 1 part in 10{sup 3} to 10{sup 4} may be maintained in millimeter sized components with this processing technique. Optical techniques offer a convenient means for measuring long term statistical performance data and transient responses needed to optimize designs and manufacturing techniques. Optical techniques can also be used to provide feedback signals needed for control and sensing of the state of the machine. Optical probe concepts and experimental data obtained using a milliengine developed at Sandia National Laboratories are presented.

Dickey, F.M.; Holswade, S.C.; Christenson, T.R.; Garcia, E.J.; Polosky, M.A.

1997-12-31

117

Cyanoacrylate bonding of thick resists for LIGA  

NASA Astrophysics Data System (ADS)

The MicroSystems Engineering Team ((mu) SET) at Louisiana State University, in close collaboration with the Center for Advanced Microstructures and Devices, has successfully completed the lithography and electroplating steps of the LIGA process sequence using cyanoacrylate to bond a PMMA resist layer to a nickel surface. Nickel microstructures 300 micrometers in height have been electroplated. Tests were performed which indicate that the bond between cyanoacrylate and nickel is much stronger than the bond between PMMA and nickel.

Rogers, James G.; Marques, Christophe; Kelly, Kevin W.; Sangishetty, Venkat; Khan-Malek, Chantal

1996-09-01

118

Industrial applications for LIGA-fabricated micro heat exchangers  

NASA Astrophysics Data System (ADS)

One of the well-known benefits of micro scale is enhanced heat transfer. This fact provides the motivation for fabricating a variety of micro heat exchangers using derivatives of the LIGA micromachining process. These heat exchangers can be made of polymers, nickel (electroplated or electroless), or ceramics (Si3N4 and alumina are presently being investigated). These heat exchangers are envisioned for applications such as gas turbine blades, mechanical seals and/or bearings, boilers, condensers, radiators, evaporators, electronic component cooling, and catalytic converters. In this paper, methods to fabricate an array of heat exchangers for different applications are described. In addition, simple analytic models that illustrate the motivation for fabricating micro cross flow heat exchanges are shown to compare favorably with experimental heat transfer results.

Kelly, Kevin W.; Harris, Chad; Stephens, Lyndon S.; Marques, Christophe; Foley, Dan

2001-10-01

119

Wafer characteristics via reflectometry  

SciTech Connect

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Sopori, Bhushan L. (Denver, CO)

2010-10-19

120

SOD wafer technology  

Microsoft Academic Search

Silicon-on-diamond (SOD) structured wafer with 4-inch diameter was fabricated by the technologies of CVD diamond deposition, Si wafer bonding and thinning. Diamond thin film with high quality and low interface state density was uniformly deposited on Silicon (001) substrate, continuous H+ ion bombardment to as-grown film surface under DC bias was performed to decrease the intrinsic tensile stress in the

C. Z. Gu; Y. Sun; J. K. Jia; Z. S. Jin

2003-01-01

121

From Wafer to Package  

NSDL National Science Digital Library

This website includes an animation of finished wafer to packaged integrated Circuits. Objective: Describe the wafer to packaged device process steps. This simulation is from Module 075 of the Process & Equipment III Cluster of the MATEC Module Library (MML). You will find the animation under the heading "Process & Equipment III." To view other clusters or for more information about the MML visit http://matec.org/ps/library3/process_I.shtmlKey

2012-11-21

122

Micro-grippers for assembly of LIGA parts.  

National Technical Information Service (NTIS)

This paper describes ongoing testing of two microgrippers for assembly of LIGA (Lithographie Galvanoformung Abformung) parts. The goal is to place 100 micron outside diameter (OD) LIGA gears with a 50 micron inner diameter hole onto pins ranging from 35 t...

J. Feddema M. Polosky T. Christenson B. Spletzer R. Simon

1997-01-01

123

Injection molding of LIGA and LIGA-similar microstructures using filled and unfilled thermoplastics  

NASA Astrophysics Data System (ADS)

Micromolding is a key technology for the economic production of micro-components for microsystems. It is applied in several microstructuring techniques including the LIGA process which was invented and developed at Forschungszentrum Karlsruhe. Injection molding of multiple-use LIGA tool inserts produced by deep-etch x-ray lithography and electroforming allows the economic production of components for most applications using microsystems technology. Such microstructures are produced in small and large series and commercialized by Forschungszentrum Karlsruhe and the microParts Company, Dormund, Germany, cooperating within the framework of a license agreement. Special molding machines are applied for the production of single- or multi-stepped microstructures of a few micrometers in lateral dimension and structural details in the submicrometer range. Maximum aspect ratios of several ten up to 600 are achieved. In contrast to compact disc production, the machines are equipped with a special control unit, by means of which tool temperature is often kept above the melting temperatures of the plastics processed during injection. Evacuation of the tool cavity is required for the complete filling of the microstructurized nest area of the mold. Cycle time is mainly determined by the heating and cooling of the whole molding tool. Recently, novel techniques were developed for the production of ceramic LIGA or LIGA-similar microstructures at Forschungszentrum Karlsruhe, where further development of the LIGA technique has been performed for more than a decade. Using lost plastic microstructures and sometimes even metal tools, microstructures are made of structural (e.g., aluminum oxide, zirconium oxide) and functional ceramics (e.g., PZT). Current development activities are aimed at producing lost plastic molds for metal microstructures by injection molding. Molding tests with conductively filled thermoplastics have been carried out to manufacture lost molds for e.g. spin nozzles.

Ruprecht, Robert; Bacher, Walter; Hausselt, Juergen H.; Piotter, Volker

1995-09-01

124

RF W-band wafer-to-wafer transition  

Microsoft Academic Search

Multiwafer silicon designs must provide an avenue for electrical signals to flow from wafer to wafer. For this purpose, a two-layer electrical bond is proposed to provide electrical connection between two coplanar waveguides printed on the adjacent faces of two vertically stacked silicon wafers. In addition to serving as a versatile low-temperature thermocompression wafer bond, loss of approximately 0.1 dB

Katherine J. Herrick; Linda P. B. Katehi

2001-01-01

125

Micro-grippers for assembly of LIGA parts  

SciTech Connect

This paper describes ongoing testing of two microgrippers for assembly of LIGA (Lithographie Galvanoformung Abformung) parts. The goal is to place 100 micron outside diameter (OD) LIGA gears with a 50 micron inner diameter hole onto pins ranging from 35 to 49 microns. The first micro gripper is a vacuum gripper made of a 100 micron OD stainless steel tube. The second micro gripper is a set of tweezers fabricated using the LIGA process. Nickel, Permalloy, and copper materials are tested. The tweezers are actuated by a collet mechanism which is closed by a DC linear motor.

Feddema, J.; Polosky, M.; Christenson, T.; Spletzer, B.; Simon, R.

1997-12-31

126

Prediction of etching-shape anomaly due to distortion of ion sheath around a large-scale three-dimensional structure by means of on-wafer monitoring technique and computer simulation  

NASA Astrophysics Data System (ADS)

A system for predicting distortion of a profile during plasma etching was developed. The system consists of a combination of measurement and simulation. An ‘on-wafer sheath-shape sensor’ for measuring the plasma-sheath parameters (sheath potential and thickness) on the stage of the plasma etcher was developed. The sensor has numerous small electrodes for measuring sheath potential and saturation ion-current density, from which sheath thickness can be calculated. The results of the measurement show reasonable dependence on source power, bias power and pressure. Based on self-consistent calculation of potential distribution and ion- and electron-density distributions, simulation of the sheath potential distribution around an arbitrary 3D structure and the trajectory of incident ions from the plasma to the structure was developed. To confirm the validity of the distortion prediction by comparing it with experimentally measured distortion, silicon trench etching under chlorine inductively coupled plasma (ICP) was performed using a sample with a vertical step. It was found that the etched trench was distorted when the distance from the step was several millimetres or less. The distortion angle was about 20° at maximum. Measurement was performed using the on-wafer sheath-shape sensor in the same plasma condition as the etching. The ion incident angle, calculated as a function of distance from the step, successfully reproduced the experimentally measured angle, indicating that the combination of measurement by the on-wafer sheath-shape sensor and simulation can predict distortion of an etched structure. This prediction system will be useful for designing devices with large-scale 3D structures (such as those in MEMS) and determining the optimum etching conditions to obtain the desired profiles.

Kubota, Tomohiro; Ohtake, Hiroto; Araki, Ryosuke; Yanagisawa, Yuuki; Iwasaki, Takuya; Ono, Kohei; Miwa, Kazuhiro; Samukawa, Seiji

2013-10-01

127

W-band LiGA fabricated klystron  

Microsoft Academic Search

Klystrino-W-band klystron was proposed by scientists at SLAC to satisfy recent applications in advanced accelerators, medical treatment, radars and communications. LiGA (a German acronym for lithographe, galvanoformung, and abformung) is introduced in the fabrication of klystrino for the first time in the history of microwave tube fabrication. The cold test experiments show that LiGA fabrication yields best surface smoothness compared

Liqun Song

2002-01-01

128

A smart material microamplification mechanism fabricated using LIGA  

NASA Astrophysics Data System (ADS)

A unique microamplification mechanism formed through the merging of smart material and microelectromechanical system concepts is presented. This microamplification device increases the useful actuation stroke of piezoceramic material through the amplification of piezoceramic strain. The technology demonstrated has utility as a microactuation mechanism for driving micropiezomotors, hearing aid transducers and precision optical switches. The microamplifier, approximately 0964-1726/7/1/012/img1, is composed of electroplated nickel and was constructed using LIGA. An overview of microactuator system requirements and the advantages of scaling the flexure based amplifier illustrates the utility of the new device. The microamplifier is a radically scaled version of a mesoscopic mechanism. An analytical discussion of the operation is presented along with a finite-element analysis of the static and dynamic properties of the microlever. The analytical study is used to develop the operation principles and expected performance of the microamplifier. Experimental static and dynamic testing results are presented that confirm the analytical study. The mechanism has a mean amplification ratio of 5.48, an elastic stroke range of 8 0964-1726/7/1/012/img2m and a fundamental frequency of 82 kHz.

Pokines, Brett J.; Garcia, Ephrahim

1998-02-01

129

Ureteric Injury due to the Use of LigaSure  

PubMed Central

Background. LigaSure is a bipolar clamping device used in open and laparoscopic surgeries for producing haemostasis in vascular pedicles up to 7?mm in diameter (“Covidien LigaSure technology: consistent, reliable, trusted vessel sealing,” 2012). The use of LigaSure has made securing haemostasis and tissue dissection relatively easy especially in laparoscopic surgery; however, if not used with care it can cause damage to the surrounding structures through lateral spread of energy. Case Report. This case report discusses the induction of a thermal ureteral injury associated with the use of LigaSure. An 80-year-old gentleman was operated for bowel cancer. LigaSure was used for securing haemostasis and tissue dissection. Postoperatively, he was found to have damage to the right ureter secondary to lateral spread of energy from the jaws of LigaSure with high abdominal drain output. Conclusion. Judicious and careful use of electrosurgical devices should be done to prevent inadvertent damage to the surrounding structures. Early recognition and involvement of a urologist can prevent long-term complications.

Gilkison, William

2013-01-01

130

Wafer level warpage characterization of 3D interconnect processing wafers  

NASA Astrophysics Data System (ADS)

We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 ?m after thinning down to the nominal thickness of 75 ?m and 50 ?m. The measurement precision is better than 2 um.

Chang, Po-Yi; Ku, Yi-Sha

2012-03-01

131

Interferometry for wafer dimensional metrology  

NASA Astrophysics Data System (ADS)

Wafer shape and thickness variation are important parameters in the IC manufacturing process. The thickness variation, also called flatness, enters the depth-of-focus budget of microlithography, and also affects film thickness uniformity in the CMP processing. The shape mainly affects wafer handling, and may also require some depth-of-focus if the wafer shape is not perfectly flattened by chucking. In the progression of technology nodes to smaller feature sizes, and hence smaller depth-of-focus of the lithography tool, the requirement for the PV-flatness over stepper exposure sites is becoming progressively tighter, and has reached 45nm for the next technology node of 45nm half pitch. Consequently, in order to be gauge-capable the flatness metrology tool needs to provide a measurement precision of the order of 1nm. Future technology nodes will require wafers with even better flatness and metrology tools with better measurement precision. For the last several years the common capacitive tools for wafer dimensional metrology have been replaced by interferometric tools with higher sensitivity and resolution. In the interferometric tools the front and back surface figure of the wafer is measured simultaneously while the wafer is held vertically in its intrinsic shape. The thickness variation and shape are then calculated from these single-sided maps. The wafer shape, and hence each wafer surface figure, can be tens of microns, necessitating a huge dynamic range of the interferometer when considering the 1nm measurement precision. Furthermore, wafers are very flexible, and hence very prone to vibrations as well as bending. This presentation addresses these special requirements of interferometric wafer measurements, and discusses the system configuration and measurement performance of WaferSightTM, KLA-Tencor's interferometric dimensional metrology tool for 300mm wafers for current and future technology nodes.

Freischlad, Klaus; Tang, Shouhong; Grenfell, Jim

2007-09-01

132

Wafer-scale high-throughput ordered arrays of Si and coaxial Si/Si(1-x)Ge(x) wires: fabrication, characterization, and photovoltaic application.  

PubMed

We have developed a method combining lithography and catalytic etching to fabricate large-area (uniform coverage over an entire 5-in. wafer) arrays of vertically aligned single-crystal Si nanowires with high throughput. Coaxial n-Si/p-SiGe wire arrays are also fabricated by further coating single-crystal epitaxial SiGe layers on the Si wires using ultrahigh vacuum chemical vapor deposition (UHVCVD). This method allows precise control over the diameter, length, density, spacing, orientation, shape, pattern and location of the Si and Si/SiGe nanowire arrays, making it possible to fabricate an array of devices based on rationally designed nanowire arrays. A proposed fabrication mechanism of the etching process is presented. Inspired by the excellent antireflection properties of the Si/SiGe wire arrays, we built solar cells based on the arrays of these wires containing radial junctions, an example of which exhibits an open circuit voltage (V(oc)) of 650 mV, a short-circuit current density (J(sc)) of 8.38 mA/cm(2), a fill factor of 0.60, and an energy conversion efficiency (?) of 3.26%. Such a p-n radial structure will have a great potential application for cost-efficient photovoltaic (PV) solar energy conversion. PMID:21749059

Pan, Caofeng; Luo, Zhixiang; Xu, Chen; Luo, Jun; Liang, Renrong; Zhu, Guang; Wu, Wenzhuo; Guo, Wenxi; Yan, Xingxu; Xu, Jun; Wang, Zhong Lin; Zhu, Jing

2011-07-22

133

Effectiveness of LigaSure diathermy coagulation in liver surgery.  

PubMed

The principal cause of perioperative morbidity and mortality following hepatic resection is excessive intraoperative hemorrhage. This study evaluates the operative use of the LigaSure device in sealing ductal structures during major and minor hepatic resections. Patients were analyzed between June 1994 and December 2005, comparing 89 randomly selected cases undergoing hepatic resections using the clamp-crushing technique with LigaSure electrocautery and hepatic inflow occlusion where appropriate with 70 patients undergoing various hepatic resections using the clamp-crushing technique alone with hepatic inflow occlusion where appropriate. Intraoperative blood loss and perioperative blood transfusion requirements were significantly less for patients in the LigaSure group. LigaSure-assisted hepatic resection was generally performed more quickly than the conventional clamp-crushing technique. The overall maximum postoperative AST, ALT, and bilirubin serum levels were similar in the two groups, as was the incidence of major postoperative complications. The LigaSure device in this randomized study is safe and simple to use, resulting in less perioperative blood loss and transfusion requirement during hepatic parenchymal transection. PMID:18802881

Chiappa, Antonio; Bertani, Emilio; Biffi, Roberto; Zbar, Andrew P; Viale, Giuseppe; Pruneri, Giancarlo; Bellomi, Massimo; Venturino, Marco; Andreoni, Bruno

2008-01-01

134

Augmented reality for wafer prober  

NASA Astrophysics Data System (ADS)

The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

Gilgenkrantz, Pascal

2011-02-01

135

Wafer sampling by regression for systematic wafer variation detection  

Microsoft Academic Search

In-line measurements are used to monitor semiconductor manufacturing processes for excessive variation using statistical process control (SPC) chart techniques. Systematic spatial wafer variation often occurs in a recognizable pattern across the wafer that is characteristic of a particular manufacturing step. Visualization tools are used to associate these patterns with specific manufacturing steps preceding the measurement. Acquiring the measurements is an

Byungsool Moon; James McNames; Bruce Whitefield; Paul Rudolph; Jeff Zola

2005-01-01

136

Solder joint reliability of a polymer reinforced wafer level package  

Microsoft Academic Search

Wafer level packages (WLPs) have demonstrated a very clear cost-advantage vs traditional wire-bond technologies, especially for small components that have a high number of dice and I\\/O per wafer. Ultra CSP® is a WLP developed by the Kulicke & Soffa Flip Chip Division (formally Flip Chip Technologies). Typical products utilizing the Ultra chip scale package (CSP) have 5×5 or less

Deok-hoon Kim; Peter Elenius; Michael Johnson; Scott Barrett

2002-01-01

137

Osmolarity, a Key Environmental Signal Controlling Expression of Leptospiral Proteins LigA and LigB and the Extracellular Release of LigA  

Microsoft Academic Search

The high-molecular-weight leptospiral immunoglobulin-like repeat (Lig) proteins are expressed only by virulent low-passage forms of pathogenic Leptospira species. We examined the effects of growth phase and environmental signals on the expression, surface exposure, and extracellular release of LigA and LigB. LigA was lost from stationary-phase cells, while LigB expression was maintained. The loss of cell-associated LigA correlated with selective release

James Matsunaga; Yolanda Sanchez; Xiaoyi Xu; David A. Haake

2005-01-01

138

Analysis of wafer stresses during millisecond thermal processing  

SciTech Connect

A flash lamp has been used to uniformly anneal large wafers with diameters approaching 100 mm. The equipment applies a pulse, with duration of 3-20 ms, resulting in large transient thermal gradients in the wafer. In this paper, we present separate models of the thermal reaction of this process and its effect upon the mechanical behavior, in order to predict stresses and shape changes, and to capture practical phenomenon. We further use the model to follow changes in the expected response consequent on altering process conditions, such as preheating and pulse duration, as well as exploring important issues associated with scaling to large wafer sizes. This work presents an initial description of the thermomechanical response of wafers to flash lamp annealing in the millisecond time regime and is therefore fundamental to the use of this technique in the fabrication of semiconductor devices.

Smith, M. P.; Seffen, K. A.; McMahon, R. A.; Voelskow, M.; Skorupa, W. [Department of Engineering, University of Cambridge, Trumpington Street, Cambridge CB2 1PZ (United Kingdom); Forschungszentrum Rossendorf, P.O. Box 510119, D-01314 Dresden (Germany)

2006-09-15

139

MEMS Wafer-level Packaging Technology Using LTCC Wafer  

NASA Astrophysics Data System (ADS)

This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature co-fired ceramic (LTCC) wafer, in which multi-layer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of micro electro mechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (-40°C×30min/+125°C×30min) by diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection methods; The electrical connection is established by porous Au bumps, which are a part of Au vias exposed in wet-etched cavities on the LTCC wafer. 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

Mohri, Mamoru; Esashi, Masayoshi; Tanaka, Shuji

140

GaAs wafer overlay performance affected by annealing heat treatment: II  

NASA Astrophysics Data System (ADS)

Further analysis on how wafer distortion affecting the overlay performance during annealing treatment in GaAs wafer fabrication was conducted quantitatively using MONO-LITH software. The experimental results were decomposed as wafer translation, scaling at X and Y direction, rotation and orthogonality. The grid residual was used to describe non- correctable distortion of the wafers, which fits the equations given below: Residual equals Measured - Modeled, which is not a modeled component. The Vector Map displays distribution of error vectors over the wafer or field for various components or overall effect. Based on the component analysis that the misalignment caused by translation and scaling can be compensated by heat treatment if the wafer is placed at a favorable orientation. This can help mitigate the effects of substrate quality in manufactory.

Liu, Ying; Black, Iain

2002-07-01

141

Bipolar IC Wafer Process Technology,  

National Technical Information Service (NTIS)

The paper introduces Fuji Electric's wafer process technology for bipolar IC's. The processes are classified into two types of 8 micrometer rule characterized by high-current output and high voltage, and 4 micrometer rule characterized by high frequency a...

K. Meguro Y. Nagayasu O. Sasaki

1988-01-01

142

Wafer handling and placement tool  

DOEpatents

A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

Witherspoon, Linda L. (22 Cottonwood La., Los Lunas, NM 87031)

1988-01-05

143

Slip-free processing of 300 mm silicon batch wafers  

NASA Astrophysics Data System (ADS)

Under gravitational and thermal constraints of integrated-circuit (IC) process technology, 300-mm-diam silicon wafers can deform via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the upper yield point of the silicon material. The material attributes, such as oxygen content and the state of oxygen aggregation, are taken into account. The theoretical approach allows the calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. Plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design. Deformation due to gravitational forces can be prevented through appropriate equipment design. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulation of ``what if?'' experiments, and initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.

Fischer, A.; Richter, H.; Kürner, W.; Kücher, P.

2000-02-01

144

Wafer-level optics enables low cost camera phones  

NASA Astrophysics Data System (ADS)

To meet market demand and enable the proliferation of camera phones for developing countries, manufacturers must be able to meet requirements for camera modules that are reduced in size and cost. Conventional camera-module technology is heading towards an asymptote, where the optics no longer scale with the required size, performance, and cost. Using wafer-level techniques and reflow compatible materials to manufacture the optics together with wafer-level chip scale packaging (WLCSP) of image sensors enables manufacturing of smaller-size, lower-cost, reflow-compatible camera modules. Focusing on VGA resolution, this paper will present a comparison between optical modules that were built using conventional technology and wafer-level technology.

Dagan, Yehudit

2009-02-01

145

Wafer sampling by regression for systematic wafer variation detection  

NASA Astrophysics Data System (ADS)

In-line measurements are used to monitor semiconductor manufacturing processes for excessive variation using statistical process control (SPC) chart techniques. Systematic spatial wafer variation often occurs in a recognizable pattern across the wafer that is characteristic of a particular manufacturing step. Visualization tools are used to associate these patterns with specific manufacturing steps preceding the measurement. Acquiring the measurements is an expensive and slow process. The number of sites measured on a wafer must be minimized while still providing sufficient data to monitor the process. We address two key challenges to effective wafer-level monitoring. The first challenge is to select a small sample of inspection sites that maximize detection sensitivity to the patterns of interest, while minimizing the confounding effects of other types of wafer variation. The second challenge is to develop a detection algorithm that maximizes sensitivity to the patterns of interest without exceeding a user-specified false positive rate. We propose new sampling and detection methods. Both methods are based on a linear regression model with distinct and orthogonal components. The model is flexible enough to include many types of systematic spatial variation across the wafer. Because the components are orthogonal, the degree of each type of variation can be estimated and detected independently with very few samples. A formal hypothesis test can then be used to determine whether specific patterns are present. This approach enables one to determine the sensitivity of a sample plan to patterns of interest and the minimum number of measurements necessary to adequately monitor the process.

Moon, Byungsool; McNames, James; Whitefield, Bruce; Rudolph, Paul; Zola, Jeff

2005-05-01

146

Low-temperature silicon wafer-to-wafer bonding using gold at eutectic temperature  

Microsoft Academic Search

Micromechanical smart sensor and actuator systems of high complexity bemme commercially viable when realized as a multi-wafer device in which the mechanical functions are distributed over different wafers and one of the wafers is dedicated to contain the readout circuits. The individually-processed wafers can be assembled using wafer-to-wafer bonding and can be combined to one single functional electro-mechanical unit using

K. D. Wise

1994-01-01

147

Fabrication of LIGA mold inserts using a modified procedure  

NASA Astrophysics Data System (ADS)

The LIGA process, invented in Germany and being further developed at Louisiana State University can be used to economically mass produce high aspect ratio microstructures (HARM) by molding. The template, or mold insert, is required to mold microstructure and is fabricated by a two step sequence of x-ray lithography and electroplating. A modified version of the LIGA process has been used to produce a mold insert. A sheet of PMMA is first patterned using x-ray lithography. After the lithography process is completed, the PMMA sheet is clamped to a nickel substrate and a subsequent electroplating step produces a mold insert. This processing sequence eliminates the need to establish a chemical bond between the resist and the substrate. The electroplated HARM were used as a mold insert in subsequent molding experiments. One mold insert which was fabricated is presented, along with the results of molding experiments using a similar insert.

Galhotra, Vikas; Marques, Christophe; Desta, Yohannes M.; Kelly, Kevin W.; Despa, Mircea; Pendse, Ajit; Collier, John

1996-09-01

148

Micro injection molding for mass production using LIGA mold inserts  

Microsoft Academic Search

Micro molding is one of key technologies for mass production of polymer micro parts and structures with high aspect ratios.\\u000a The authors developed a commercially available micro injection molding technology for high aspect ratio microstructures (HARMs)\\u000a with LIGA-made mold inserts and pressurized CO2 gasses. The test inserts made of nickel with the smallest surface details of 5 ?m with structural height

Takanori Katoh; Ryuichi Tokuno; Yanping Zhang; Masahiro Abe; Katsumi Akita; Masaharu Akamatsu

2008-01-01

149

Molding of three dimensional microstructures by the LIGA process  

Microsoft Academic Search

The authors report that the use of a resist layer, which can be structurized either by plastic molding or by deep-etch X-ray lithography, in addition to the LIGA process allows the fabrication of stepped microstructures. This technique is based on the combination of a high-molecular base layer made of polymethyl methacrylate (PMMA) with an internal adhesion promoter and a low-molecular

M. Harmening; W. Bacher; P. Bley; A. El-Kholi; H. Kalb; B. Kowanz; W. Menz; A. Michel; J. Mohr

1992-01-01

150

Microsample tensile testing of LIGA nickel for MEMS applications  

Microsoft Academic Search

Electro-deposited LIGA Ni components are being considered for use in a number of microelectromechanical systems (MEMS) and applications. The metrology of these components and their non-equilibrium microstructures play an important role in determining the mechanical response of these structures. Microsample testing has proven to be a reliable way of measuring the elastic and plastic tensile properties of these 100–200 ?m

K. J Hemker; H Last

2001-01-01

151

LIGA fabrication of X-ray Nickel lenses  

Microsoft Academic Search

Nickel refractive planar lenses generating line and point X-ray spots were fabricated by LIGA technology. The optimum parameters of the lenses were simulated for a kinoform lens profile and an X-ray energy range from 100 keV to 1 MeV. The focusing elements of the lens are characterised by an aspect ratio of about 200 and a side-wall roughness of less

V. Nazmov; E. Reznikova; A. Snigirev; I. Snigireva; M. DiMichiel; M. Grigoriev; J. Mohr; B. Matthis; V. Saile

2005-01-01

152

LIGA process: sensor construction techniques via X-ray lithography  

Microsoft Academic Search

The LIGA (from the German Lithographie, Galvanoformung, Abformung) method, based on deep-etch X-ray lithography, electroforming and molding processes, is described. This microfabrication technique makes it possible to generate devices with minimal lateral dimensions in the micrometer range and structural heights of several hundred micrometers from metallic and plastic materials. In contrast to orientation-dependent etching of monocrystalline silicon, there are no

W. Ehrfeld; F. Gotz; D. Munchmeyer; W. Schelb; D. Schmidt

1988-01-01

153

One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications  

Microsoft Academic Search

The ability to align and bond with precision, one micron or less, two silicon wafers or a silicon wafer to another substrate is becoming a critical issue for a variety of semiconductor applications. For CMOS devices this technology will be applied for chip-scale packaging and also for advanced 3-D interconnect processes. In the microelectromechanical systems (MEMS) arena, accurate alignment of

A. R. Mirza

2000-01-01

154

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Vosen, S.R.

1999-07-27

155

W-band LiGA fabricated klystron  

NASA Astrophysics Data System (ADS)

Klystrino-W-band klystron was proposed by scientists at SLAC to satisfy recent applications in advanced accelerators, medical treatment, radars and communications. LiGA (a German acronym for lithographe, galvanoformung, and abformung) is introduced in the fabrication of klystrino for the first time in the history of microwave tube fabrication. The cold test experiments show that LiGA fabrication yields best surface smoothness compared with an alternative way EDM (Electrical Discharge Machining). Resultantly LiGA fabricated klystrino has the smallest wall loss which maximizes the circuit efficiency of the output structure. A multiple-gap coupled cavity is motivated to be employed as the klystrino output cavity for maximizing the efficiency. Klytrino is simulated by 1-D, 2-D and 3-D simulation codes. Particularly a complete klystrino is simulated intensively using 2-D MAGIC Particle-in-Cell (PIC) code either for beam absence or beam presence. Many simulation techniques are developed such as model transformation from 3-D to 2-D, circuit parameter simulation, dispersion characteristic analysis, pre bunched electron beam mode and so on. Klystrino, as a 3-D structure, is modeled by 3-D MAFIA for analyzing the cold circuit properties. 3-D MAGIC is explored to simulate klystrino for the actual structure analysis and actual beam interaction process observation.

Song, Liqun

2002-01-01

156

Wafer bonding of 75 mm diameter GaP to AlGaInP-GaP light-emitting diode wafers  

Microsoft Academic Search

The AlGaInP\\/GaP wafer-bonded transparent-substrate (TS) light-emitting diodes (LEDs) have been shown to exhibit luminous efficiencies\\u000a exceeding many conventional lightning sources including 60 W incandescent sources. This paper will demonstrate the feasibility\\u000a of scaling wafer bonding technology to 75 mm diameter wafers and some of the unique challenges associated with this scaling.\\u000a The quality and uniformity of bonding were characterized via

I.-H. Tan; D. A. Vanderwater; J.-W. Huang; G. E. Hofler; F. A. Kish; E. I. Chen; T. D. Ostentowski

2000-01-01

157

Injection molding using high-aspect-ratio microstructure mold inserts produced by LIGA technique  

NASA Astrophysics Data System (ADS)

The (mu) SET research group at LSU is developing the three-step LIGA process to inexpensively manufacture high aspect ratio microstructure (HARMs). The first two steps of the process (lithography and electroplating) produce a metallic mold insert that is used as a template for molding microstructure. This paper focuses on injection molding of thermoplastics to produce surfaces covered with HARMs hundreds of micrometers in height, tens of micrometers in width, and separated by gaps on the order of tens of micrometers. Injecting plastic into the narrow, high aspect ratio gaps existing in the HARMs mold inserts (micromolding) offers a set of challenges different from classical injection molding of larger scale parts. This paper provides results of a series of injection molding experiments using a commercially available injection molding machine. Replication of the HARMs was achieved by increasing the injection speed, elevating the tool temperature, and venting the mold cavity. Electron microscopy was used to investigate and assess the molding results.

Despa, Mircea S.; Kelly, Kevin W.; Collier, John R.

1998-09-01

158

Study of hybrid orientation structure wafer  

NASA Astrophysics Data System (ADS)

Two types of 5 ?m thick hybrid orientation structure wafers, which were integrated by (110) or (100) orientation silicon wafers as the substrate, have been investigated for 15-40 V voltage ICs and MEMS sensor applications. They have been obtained mainly by SOI wafer bonding and a non-selective epitaxy technique, and have been presented in China for the first time. The thickness of BOX SiO2 buried in wafer is 220 nm. It has been found that the quality of hybrid orientation structure with (100) wafer substrate is better than that with (110) wafer substrate by “Sirtl defect etching of HOSW".

Kaizhou, Tan; Jing, Zhang; Shiliu, Xu; Zhengfan, Zhang; Yonghui, Yang; Jun, Chen; Tao, Liang

2011-06-01

159

Aluminium Gettering in Silicon Wafers  

NASA Astrophysics Data System (ADS)

The effect of an evaporated thick aluminium paper on electrical properties of multicrystalline and gold contaminated FZ monocrystalline silicon wafers was investigated. By means of minority carrier diffusion length measurements and Deep Level Transient Spectroscopy, it was deduced that the material improvements observed after annealing at 900°C are due to gettering of metallic impurities in the Al-Si alloyed layer.

Martinuzzi, S.; Porre, O.; Périchaud, I.; Pasquinelli, M.

1995-09-01

160

Characterization of silicon-on-insulator wafers  

NASA Astrophysics Data System (ADS)

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Park, Ki Hoon

161

Adhesive wafer bonding for MEMS applications  

Microsoft Academic Search

Low temperature wafer bonding is a powerful technique for MEMS\\/MOEMS devices fabrication and packaging. Among the low temperature processes adhesive bonding focuses a high technological interest. Adhesive wafer bonding is a bonding approach using an intermediate layer for bonding (e.g. glass, polymers, resists, polyimides). The main advantages of this method are: surface planarization, encapsulation of structures on the wafer surface,

Viorel Dragoi; Thomas Glinsner; Gerald Mittendorfer; Bernhard Wieder; Paul Lindner

2003-01-01

162

NREL Core Program; Session: Wafer Silicon (Presentation)  

SciTech Connect

This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

Wang, Q.

2008-04-01

163

Wafer Probing Issues at Millimeter Wave Frequencies  

Microsoft Academic Search

With increased wafer probing activity at millimeter wave frequencies, and the maturing of wafer probing technology itself, new issues have arisen. Many of these issues involve phenomena which, although present at lower frequencies, do not cause significant perturbation at measured data below 40 GHz. At higher frequencies wafer probe systems begin to experience the effects of phenomena such as surface

Edward M. Godshalk

1992-01-01

164

High-Throughput RFIC Wafer Testing  

Microsoft Academic Search

This paper surveys the state of RFIC wafer testing as performed on production floors today, and the trends and expectations for the future. Currently, most RF chips sold as known-good die (KGD) and relatively complex RFICs are tested at-speed at the wafer level. RF wafer testing is used to reduce the cost of scrap at the next level of packaging,

Eric W. Strid

2001-01-01

165

Development of wafer level packaged scanning micromirrors  

Microsoft Academic Search

This paper presents design, simulation and fabrication of a wafer level packaged Microelectromechanical Systems (MEMS) scanning mirror. In particular we emphasize on the process development and materials characterization of In- Ag solder for a new wafer level hermetic\\/vacuum package using low temperature wafer bonding technology. The micromirror is actuated with an electrostatic comb actuator and operates in resonant torsional mode.

Aibin Yu; Chengkuo Lee; Li Ling Yan; Qing Xin Zhang; Seung Uk Yoon; John H. Lau

2008-01-01

166

Cloning and Molecular Characterization of an Immunogenic LigA Protein of Leptospira interrogans  

PubMed Central

A clone expressing a novel immunoreactive leptospiral immunoglobulin-like protein A of 130 kDa (LigA) from Leptospira interrogans serovar pomona type kennewicki was isolated by screening a genomic DNA library with serum from a mare that had recently aborted due to leptospiral infection. LigA is encoded by an open reading frame of 3,675 bp, and the deduced amino acid sequence consists of a series of 90-amino-acid tandem repeats. A search of the NCBI database found that homology of the LigA repeat region was limited to an immunoglobulin-like domain of the bacterial intimin binding protein of Escherichia coli, the cell adhesion domain of Clostridium acetobutylicum, and the invasin of Yersinia pestis. Secondary structure prediction analysis indicates that LigA consists mostly of beta sheets with a few alpha-helical regions. No LigA was detectable by immunoblot analysis of lysates of the leptospires grown in vitro at 30°C or when cultures were shifted to 37°C. Strikingly, immunohistochemistry on kidney from leptospira-infected hamsters demonstrated LigA expression. These findings suggest that LigA is specifically induced only in vivo. Sera from horses, which aborted as a result of natural Leptospira infection, strongly recognize LigA. LigA is the first leptospiral protein described to have 12 tandem repeats and is also the first to be expressed only during infection. Thus, LigA may have value in serodiagnosis or as a protective immunogen in novel vaccines.

Palaniappan, Raghavan U. M.; Chang, Yung-Fu; Jusuf, S. S. D.; Artiushin, S.; Timoney, John F.; McDonough, Sean P.; Barr, Steve C.; Divers, Thomas J.; Simpson, Kenneth W.; McDonough, Patrick L.; Mohammed, Hussni O.

2002-01-01

167

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Astrophysics Data System (ADS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-02-01

168

MEMS Wafer-Level Packaging with Conductive Vias and Wafer Bonding  

Microsoft Academic Search

Micromachined accelerometers were packaged at wafer-level using both via-last and via-first approaches. In the via-last approach, a through-hole etched cap wafer was bonded to a micromachined device wafer using glass frit. Interconnections from the bond pads on the device wafer to the top of the cap wafer were made through the holes using sputter-deposition of metals. The bonded pair was

C. H. Yun; J. R. Martin; T. Chen; D. Davis

2007-01-01

169

RF-MEMS wafer-level packaging using through-wafer via technology  

Microsoft Academic Search

This paper presents wafer-level packaging (WLP) solution for RF-MEMS applications based on through-wafer via (TWV) technology in high-resistivity silicon (HRS). A pre-processed HRS capping wafer containing recesses and vertical Cu-plated TWV interconnect is, after alignment, bonded to the RF-MEMS wafer providing environmental protection and easy signal access. Optionally, cavities can be formed simultaneously with TWV in the capping wafer, which

J. Tian; J. Iannacci; S. Sosin; R. Gaddi; M. Bartek

2006-01-01

170

Enhanced adhesion for LIGA microfabrication by using a buffer layer  

DOEpatents

The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

Bajikar, Sateesh S. (San Jose, CA); De Carlo, Francesco (Darien, IL); Song, Joshua J. (Naperville, IL)

2001-01-01

171

Wafer Manufacturing and Slicing Using Wiresaw  

NASA Astrophysics Data System (ADS)

Wafer manufacturing (or wafer production) refers to a series of modern manufacturing processes of producing single-crystalline or poly-crystalline wafers from crystal ingot (or boule) of different sizes and materials. The majority of wafers are single-crystalline silicon wafers used in microelectronics fabrication although there is increasing importance in slicing poly-crystalline photovoltaic (PV) silicon wafers as well as wafers of different materials such as aluminum oxide, lithium niobate, quartz, sapphire, III-V and II-VI compounds, and others. Slicing is the first major post crystal growth manufacturing process toward wafer production. The modern wiresaw has emerged as the technology for slicing various types of wafers, especially for large silicon wafers, gradually replacing the ID saw which has been the technology for wafer slicing in the last 30 years of the 20th century. Modern slurry wiresaw has been deployed to slice wafers from small to large diameters with varying wafer thickness characterized by minimum kerf loss and high surface quality. The needs for slicing large crystal ingots (300 mm in diameter or larger) effectively with minimum kerf losses and high surface quality have made it indispensable to employ the modern slurry wiresaw as the preferred tool for slicing. In this chapter, advances in technology and research on the modern slurry wiresaw manufacturing machines and technology are reviewed. Fundamental research in modeling and control of modern wiresaw manufacturing process are required in order to understand the cutting mechanism and to make it relevant for improving industrial processes. To this end, investigation and research have been conducted for the modeling, characterization, metrology, and control of the modern wiresaw manufacturing processes to meet the stringent precision requirements of the semiconductor industry. Research results in mathematical modeling, numerical simulation, experiments, and composition of slurry versus wafer quality are presented. Summary and further reading are also provided.

Kao, Imin; Chung, Chunhui; Moreno Rodriguez, Roosevelt

172

GEM-type detectors using LIGA and etchable glass technologies  

SciTech Connect

Gas electron multipliers (GEMS) have been made by a deep X-ray lithography technique (LIGA process) using synchrotron radiation on polymethylmethacrylate (PMMA) and by UV processes using a UV etchable glass. Gain, stability and rate capability for these detectors are described.The LIGA detectors described consist of PMMA sheets of various thicknesses, 125mm to 350mm, and have 150mm x 150mm square holes spaced with a pitch of 300mm. Thin copper electrodes are plated on the top and bottom surfaces using a Damascene method, followed by electroless plating of the copper onto a palladium-tin base layer. For various thicknesses of PMMA measurements have been made of absolute gain vs. voltage, time stability of gain, and rate capability. The operating gas mixture was usually Ar/CO2 (70/30) gas, but some tests were also done using P10 gas. We also made GEM-like detectors using the UV etchable glass called Foturan, patterned by exposure to UV light and subsequent etching. A few measurements using these detectors will be reported, including avalanche gain and time stability.

Ahn, S.K.; Kim, J.G.; Perez-Mendez, V.; Chang, S.; Jackson, K.H.; Kadyk, J.A.; Wenzel, W.A.; Cho, G.

2001-11-02

173

Characterization of Sidewall and Planar Surfaces of Electroformed LIGA Parts  

SciTech Connect

The nature of surfaces and the way they interact with each other during sliding contact can have a direct bearing on the performance of a microelectromechanical (MEMS) device. Therefore, a study was undertaken to characterize the surfaces of LIGA fabricated Ni and Cu components. Sidewall and planar surfaces were examined by scanning electron microscopy (SEM) and atomic force microscopy (AFM). Surface roughness was quantified using the AFM. Post-processing (e.g. lapping, removal of polymer film) can profoundly influence the morphology of LIGA components. Edge rounding and smearing of ductile materials during lapping can result in undesirable sidewall morphologies. By judicious selection of AFM scan sizes, the native roughness ({approximately}10 nm RMS) can be distinguished from that arising due to post processing, e.g. scratches, debris, polymer films. While certain processing effects on morphology such as those due to lapping or release etch can be controlled, the true side wall morphology appears to be governed by the morphology of the polymer mold or by the electroforming process itself, and may be much less amenable to modification.

PRASAD,SOMURI V.; HALL,AARON C.; DUGGER,MICHAEL T.

2000-10-01

174

Low temperature, high strength, wafer-to-wafer bonding  

SciTech Connect

This paper reports on high strength bonds which can be formed between portions of silicon wafer coated with reflowed BPSG at temperatures as low as 160[degrees]C. Both a novel modified cantilever beam analysis, and crude physical methods attest to the strength of the bonds formed. Strong bonds between thermal oxides also have been observed, indicating that neither boron nor phosphorous are essential to the process. Preparation cleanliness may be the key to low temperature, high strength bonding,. Recent work in the glass sol-gel area supports the hypothesis that this process is the result of a low temperature condensation reaction.reaction.

Fleming, J.G.; Roherty-Osmun, E.; Godshall, N.A. (Sandia National Labs., Albuquerque, NM (United States))

1992-11-01

175

LIGA-based microsystem manufacturing:the electrochemistry of through-mold depostion and material properties.  

SciTech Connect

The report presented below is to appear in ''Electrochemistry at the Nanoscale'', Patrik Schmuki, Ed. Springer-Verlag, (ca. 2005). The history of the LIGA process, used for fabricating dimensional precise structures for microsystem applications, is briefly reviewed, as are the basic elements of the technology. The principal focus however, is on the unique aspects of the electrochemistry of LIGA through-mask metal deposition and the generation of the fine and uniform microstructures necessary to ensure proper functionality of LIGA components. We draw from both previously published work by external researchers in the field as well as from published and unpublished studies from within Sandia.

Kelly, James J. (Sandia National Laboratories, Livermore, CA); Goods, Steven Howard (Sandia National Laboratories, Livermore, CA)

2005-06-01

176

Wafer bonding for three dimensional (3D) integration  

NASA Astrophysics Data System (ADS)

Wafer scale 3D integration is recognized as an emerging technology to increase the performance of ICs. When bonding with processed ICs, the bonding process must be compatible with IC back-end processing. The fraction of bonded area was examined by optical inspection and BCB was selected as the baseline glue after achieving reproducible void-free bonding. Bond strength at the glue interface of bonded wafers was quantified by four-point bending. Using four point bending, the following effects of BCB glue on the bonding integrity were evaluated; (1) employment of adhesion promoter, (2) BCB glue thickness and (3) material stack. When the adhesion promoter is used, bond strength increases at both BCB bonds of 2.6 mum and 0.4 mum. These results also demonstrate that BCB glue thickness affects the bond strength at the glue interface with thicker glue layers corresponding to higher bond strength. The decrease in bond strength observed for thin BCB is due to a decrease of plastic dissipation energy, Gplastic, which is proportional to BCB thickness. In both bonded wafer pairs that include a PECVD oxide deposited silicon wafer and a glass wafer, bond strengths are linearly proportional to BCB thickness. With these results, the relationship between Gplastic , and bond breaking energy, Gtip, and BCB thickness, t is observed to be Gplastic ? 0.3 · Gtip · t. The effects of thermal cycling on bond strength and residual stress at the interface between BCB and a PECVD oxide, and the thermal stability of BCB were evaluated by four point bending and wafer curvature measurements. Stress relaxation of the PECVD oxide layer during thermal cycling leads to a decrease in the deformation energy due to residual stress, G residual, and to an increase in bond strength. In thermal cycling performed at temperatures of 350 and 400°C, it is observed that the relaxation of residual stress occurs predominantly during the first thermal cycle. Conclusively, the BCB process for wafer-to-wafer bonding applications is stabilized after four cycles at a temperature of 400°C. Thermal cycling performed at a temperature 450°C leads to cohesive failure within the BCB layer with low bond strength (<0.5 J/m2).

Kwon, Yongchai

2003-10-01

177

Bonded wafer substrates for integrated detector arrays  

SciTech Connect

Bonded wafer substrates have been made which are optimized for integrating high energy particle detector arrays with their readout electronics. The detectors are processed in the handle wafer, which is a 300 [mu]m thick, high resistivity, <111> crystal orientation silicon wafer. This wafer is bonded to a primary wafer using a low temperature process that does not affect the detector material. The support electronics are processed in the remnant of the primary wafer, which is a submicron thick <100> crystal orientation silicon film formed by a bond-and-etchback procedure. These two device materials are isolated from each other by a radiation hardened dielectric film. The integrated process is based on a low temperature, radiation hardened VLSI CMOS process which is also shown not to seriously affect the detector material.

Wang, J.J.; King, E.E.; Leonov, P.; Huang, D.H. (Advanced Research and Applications Corp., Sunnyvale, CA (United States)); Thompson, P.; Godbey, D. (Naval Research Lab., Washington, DC (United States))

1993-10-01

178

Accurate surface profilometry of ultrathin wafers  

NASA Astrophysics Data System (ADS)

Geometric characterization of 50 mm diameter, 50 µm thick single-crystal Si(1 1 1) wafers has been performed using complementary methods: industry-standard capacitance measurements of warp and total thickness variation (TTV), and a technique we term scanned chromatic confocal profilometry (SCCP). We compare the measurements made by the two techniques and demonstrate the limitations of capacitance measurements when applied to ultrathin wafers. The two-dimensional SCCP measurements are shown to enhance the description of wafer thickness variations beyond that generated by the standard test method. We discuss a Fourier transform-based analysis and show it to be useful in wafer quality assessment. Adding a summary of spatial frequencies in a wafer's thickness map to the conventional measures of warp and TTV provides a more complete summary of the salient features of a wafer's geometry.

Weeks, A. E.; Litwin, D.; Galas, J.; Surma, B.; Piatkowski, B.; MacLaren, D. A.; Allison, W.

2007-09-01

179

PROGRESS IN COPPER-BASED WAFER BONDING  

Microsoft Academic Search

This article discusses a method of wafer-to-wafer bonding using metallic copper as the bonding medium. This method is commonly known as thermo-compression bonding. Bonding process is described and characterization results are presented. Reliability issues related to voids formation in the bonded layer is discussed. A survey on progress of copper-based wafer bonding and its application for 3-D ICs is included.

Chuan Seng Tan

180

Ag-Sn Fluxless Wafer Bonding Technology  

Microsoft Academic Search

Wafer bonding technology is important for most MEMS devices' packaging, especially for RF-MEMS devices. Different materials systems, such as Au-Sn, Au-In, have been developed for wafer bonding. A new bonding system, using Ag-Sn, is investigated in this paper. Comparing to well developed Au-Sn bonding (typically bonding temperature of 280degC ), Ag-Sn would provide a potentially lower temperature, lower cost wafer-level

XiaoGang Ji; Jian Cai; YoonChul Sohn; Qian Wang; Woonbae Kim

2006-01-01

181

Macroporous-based micromachining on full wafers  

Microsoft Academic Search

This paper reports on a technique of macroporous-based micromachining for full wafers. A 3.6kW xenon lamp of whose intensity can be varied is employed to generate electronic holes during the etching. In order to apply a uniform electric field to whole 3in. wafer, a mesh electrode is formed on the backside of the wafer after implantation of an n+ layer.

H. Ohji; S. Izuo; P. J. French; K. Tsutsumi

2001-01-01

182

Si Wafer Bonding with Ta Silicide Formation  

NASA Astrophysics Data System (ADS)

Bonded SOI wafers with a Ta silicide layer are fabricated. The 0.08-?m-thick Ta film sputtered on an oxidized Si wafer is bonded to another Si wafer with a native oxide. When the wafers are uniformly bonded by pulse-field-assisted bonding, Ta silicide forms at the interface. The buried Ta silicide layer is 0.12 ?m thick and the sheet resistance is 9 ?/\\Box. From a SIMS analysis, Ta decreases rapidly in Si. This proves that a pure SOI layer for devices can be obtained.

Fukuroda, Atsushi; Sugii, Toshihiro; Arimoto, Yoshihiro; Ito, Takashi

1991-10-01

183

The Transition to Optical Wafer Flatness Metrology  

NASA Astrophysics Data System (ADS)

As optical lithography requirements drive wafer flatness toward increasing levels of perfection, the industry is faced with a need to transition from current standard practice. In this paper we present a historical perspective on starting material dimensional metrology, leading to the current standard for wafer manufacturing quality control, capacitance-based wafer flatness metrology. We then investigate the market and technical factors that compel a transition to optical flatness metrology. Comparative data (from advanced 300mm wafers) between capacitive and optical flatness measurement tools permits us to conclude that the industry transition to optical dimensional metrology can occur without disruption of accepted manufacturing baselines.

Valley, John F.; Poduje, Noel

2003-09-01

184

Fabrication of LIGA mold insert using Ni-PTFE composite micro-electroforming  

NASA Astrophysics Data System (ADS)

The LIGA process, which combines deep X-ray lithography with electroforming and polymer molding, is a main fabrication method for producing MEMS. And hot embossing is one of the main processing techniques for polymer microfabrication, which helps the LIGA (UV-LIGA) technology to achieve low cost mass production. And electroforming of LIGA mold insert with lower surface energy and friction coefficient is required for demolding process during hot embossing to obtain better polymer replicas. In this paper, the Ni-PTFE compound material mold inserts is fabricated by special treated galvanic bath and operation conditions. And the results show that it is a robust Ni-PTFE composite micro-electroforming and basically changes the interaction property when demolding for producing high quality polymer replicas.

Guo, Yuhua; Liu, Gang; Xiong, Ying; Zhu, Xuelin; Jun, Wang; Tian, Yangchao

2006-04-01

185

UV-LIGA Microfabrication of 220 GHz Sheet Beam Amplifier Gratings with SU-8 Photoresists.  

National Technical Information Service (NTIS)

Microfabrication techniques have been developed using ultraviolet photolithography (UV-LIGA) with SU-8 photoresists to create advanced sheet beam amplifier circuits for the next generation of vacuum electron traveling wave amplifiers in the 210-220 GHz (G...

B. Levush C. D. Joye J. P. Calame M. Garven

2010-01-01

186

RF–MEMS wafer-level packaging using through-wafer interconnect  

Microsoft Academic Search

In this paper, development of a wafer-level packaging (WLP) process suitable for RF–MEMS applications is presented. The packaging concept is based on a high-resistivity silicon capping substrate that is wafer-level bonded to an RF–MEMS device wafer providing MEMS device protection and vertical electrical signal interconnect. The capping substrate contains Cu-plated through-wafer electrical vias and optional through-substrate cavities allowing for hybrid

J. Tian; S. Sosin; J. Iannacci; R. Gaddi; M. Bartek

2008-01-01

187

Stress Voiding During Wafer Processing  

SciTech Connect

Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

Yost, F.G.

1999-03-01

188

Development on integrated passive devices using wafer level package technologies  

Microsoft Academic Search

In recent years, as the demand for ever-smaller electronic systems grows, Industry trends are seeking ways to increase IC integration levels and to reduce the size and weight of IC packages. The explosive expansion of mobile electronic terminals generates strong demand for high-performance, cost-effective and miniaturized RF modules providing desired wireless connectivity. The chip scale package (CSP) and wafer-level packaging

Byeung-Gee Kim; Yun-Mook Park; Jun-Kyu Lee; In-Soo Kang

2010-01-01

189

Techniques for the evaluation of outgassing from polymeric wafer pods  

Microsoft Academic Search

In recent years there has been increasing interest in using wafer-level isolation environments or pods (microenvironments) to provide a more controllable, cleaner wafer environment during wafer processing. It has been shown that pods can be effective in reducing the amount of particulate contamination on wafers during manufacturing. However, there have also been studies that indicate that pods and wafer boxes

D. C. McIntyre; A. Liang; S. M. Thornberg; S. F. Bender; R. D. Lujan; R. S. Blewer; W. D. Bowers

1994-01-01

190

Overall Wafer Effectiveness (OWE): A Novel Industry Standard for Wafer Productivity  

Microsoft Academic Search

Overall equipment efficiency (OEE) is an index that is widely used to measure equipment performance for semiconductor manufacturing. However, little research has been done to address productivity from the perspective of wafer exposure performance. This study aims to propose a novel standard, overall wafer effectiveness (OWE), to evaluate the effectiveness of wafer exposure rather than only considering tool productivity. Furthermore,

Chen-Fu Chien; Chia-Yu Hsu; Hong-Shing Chou; Chih-Wei Lin

2006-01-01

191

LIGA fabrication of nanocrystalline Ni–W alloy micro specimens from ammonia-citrate bath  

Microsoft Academic Search

Ammonia-citrate bath has been investigated for the deposition of nano crystalline Ni–W alloy micro components using the LIGA\\u000a process. First the bath stability and deposit characteristics were studied. Fabrication of micro specimens were then carried\\u000a out on silicon substrates covered with novolac as well as thick PMMA resist for LIGA. Effects of different parameters like\\u000a current density, nickel ion and

A. S. M. A. Haseeb; K. Bade

2008-01-01

192

Low-loss LIGA-micromachined conductor-backed coplanar waveguide.  

SciTech Connect

A mesoscale low-loss LIGA-micromachined conductor-backed coplanar waveguide is presented. The 517 {micro}m lines are the tallest uniplanar LIGA-fabricated microwave transmission lines to date, as well as the first to be constructed of copper rather than nickel. The conductor-backed micromachined CPW on quartz achieves a measured attenuation of 0.064 dB/cm at 15.5 GHz.

Forman, Michael A.

2004-12-01

193

Single wafer process to generate reliable swing  

NASA Astrophysics Data System (ADS)

Swing curve generation is an important and common exercise in the design, characterization, and optimization of photolithography processes. The development of a robust anti-reflective strategy for a given process often necessitates multiple experimental iterations of the swing curve generation. The traditional methodology for generating a photoresist thickness swing curve plot is time and silicon intensive; usually involving processing and metrology on a dozen or more wafers. In addition, the resulting curve often can convolve systematic and random wafer-wafer effects due to other track/resist/scanner related variables. In some cases, such as very low reflectivity underlying substrate the signal to noise ratio is poor enough to effectively mask the sinusoidal swing behavior from visibility. In this paper, we present a new methodology to generate a swing curve by using a single wafer. The critical point of this method is to generate a temperature gradient on the wafer during the initial step of photoresist dispense and coating. Since the resist viscosity is inversely proportional to the temperature, a significant resist thickness variation can be produced across the wafer, which can easily encompass one swing period of thickness or more. The resulting resist thickness signature across the wafer is seen to be very repeatable, such that a companion wafer can be measured at multiple positions corresponding to CD metrology lcoations on the patterned wafer. The possibility of deconvolving systematic across wafer CD variability due to other process variables is discussed by characterizing a control wafer with conventional uniform resist thickness. Our experiments for I-line and DUV resists indicated that this method not only provides reliable swing curves but also saves photoresist, silicon, and time both for engineering and machine. Moreover, this methodology represents an improved signal to noise ratio such that makes it particularly useful for ARC thickness/composition optimization. Several examples utilizing this method will be presented.

Gu, Yiming; Zhu, Cynthia; Sturtevant, John L.

2003-05-01

194

Formation and combustion characteristics of elephantgrass and energycane wafers  

NASA Astrophysics Data System (ADS)

Elephantgrass (Pennisetum purpureum Schum.) and energycane (Saccharum Spp.) are two cane type grasses. These are tall-growing perennial bunchgrasses that produce long hardened stems and grow in the tropics and subtropics. Traditionally, they have been used for forage and, in some regions, have been randomly burned on fields or disposed of uselessly. However, these plants have high dry matter yield and, thus, are excellent candidates as energy crops. Elephantgrass and energycane have been used for direct combustion in their loose form in large-scale applications. Several problems, many of which were attributed to their low bulk density, were encountered with using the materials. Consequently, this project was initiated to investigate the formation and combustion characteristics of the two materials in the form of small compact units called wafers. A hydraulic press that applied axial stresses on the material in four different dies was used. A load cell and a displacement transducer were utilized to measure the stresses and material detection. Wafer quality was evaluated using a tumbler built according to the American Society of Agricultural Engineers standards. In addition, a small stove was built to test wafer combustion. Thermocouples were used to measure temperatures during combustion. All the data gathered was transferred to a computer using a data acquisition system. It was found that the stress-deformation and stress-density relationships of elephantgrass and energycane were of exponential nature. Compaction energy required, which was calculated from the area under the force-deformation curves, ranged from 0.1 to 0.3% of their energy content. It was also found that wafer quality (durability) was mainly a function of wafer size and its final (relaxed) density in addition to material stem-to-leaf ratio and its crude protein content. Wafers possessed poor ignition quality but once ignited, they burned satisfactorily. The results indicated that sufficient and uniform combustion air distribution and a stove lining were critical factors in burning these materials. Further, the findings revealed that it may not be recommended to use elephantgrass or energycane in large-scale applications due to their high slagging index. Nonetheless, using them in small-scale applications may be possible. Elephantgrass was generally a better candidate for such an application.

Mofleh, Mohamad I.

195

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs  

Microsoft Academic Search

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and\\/or burn-in parts in wafer form. After the parts are

Eugene M. Chow; David K. Fork; Christopher L. Chua; Koenraad Van Schuylenbergh; Thomas Hantschel

2009-01-01

196

Influence of inulin modification and flour type on the sensory quality of prebiotic wafer crackers  

Microsoft Academic Search

An inulin syrup made from Jerusalem artichoke tubers, either in its commercial form or after ultrafiltration, was freeze-dried and used as a prebiotic ingredient in the small-scale manufacture of wafer crackers. The flours used for the preparation of wafer batters were from wheat, rye or spelt wheat, or 1:1 combinations of wheat flour and rye flour or wheat flour and

Steffi Hempel; Annette Jacob; Harald Rohm

2007-01-01

197

Evaluation of protective immunity of Leptospira immunoglobulin like protein A (LigA) DNA vaccine against challenge in hamsters  

Microsoft Academic Search

We demonstrated earlier that immunization with recombinant Leptospira immunoglobulin like protein A (LigA) induced significant protection against virulent Leptospira interrogans serovar Pomona challenge in hamsters. However, the protective immune mechanism remains unclear. In the present study we demonstrated the protective efficacy of a LigA DNA vaccine and evaluated the immune mechanism underlying the protection against leptospirosis in hamsters. The LigA

Syed M. Faisal; WeiWei Yan; Chia-Sui Chen; Raghavan U. M. Palaniappan; Sean P. McDonough; Yung-Fu Chang

2008-01-01

198

Methanol steam reformer on a silicon wafer  

Microsoft Academic Search

A study of the reforming rates, heat transfer and flow through a methanol reforming catalytic microreactor fabricated on a silicon wafer are presented. Packed bed microchannel reactors were fabricated using silicon DRIE, followed by wafer bonding. The reactor bed was subsequently filled with catalyst particles. Thermal control is achieved through on-chip resistive heaters, whereby methanol steam reforming reactions were studied

Hyung Gyu Park; Jonathan A. Malen; W. Thomas Piggott; Jeffrey D. Morse; Ralph Greif; Costas P. Grigoropoulos; Mark A. Havstad; Ravi Upadhye

2006-01-01

199

Capacity planning for development wafer fab expansion  

Microsoft Academic Search

The simulation model described offers many different opportunities for increasing understanding of a development wafer fab. The results of simulation runs must be analyzed with an understanding of the effect of randomness on the model. Multiple random number runs might be required to confirm a model result. Simulation models can account for dynamic interactions between wafers, tools and operators. The

W. Chou; J. Everton

1996-01-01

200

Substrate bonding techniques for CMOS processed wafers  

NASA Astrophysics Data System (ADS)

Transferring a CMOS circuit to a foreign substrate can be accomplished by bonding a processed silicon wafer to the substrate and subsequently thinning the silicon wafer. This paper presents both anodic bonding and adhesive bonding and evaluates their potential for circuit transfer.

van der Groen, S.; Rosmeulen, M.; Baert, K.; Jansen, P.; Deferm, L.

1997-09-01

201

Frame vibration suppression for wafer transfer system  

Microsoft Academic Search

The rapid development of the Integrated Circuit (IC) manufacturing equipment industry requires greater efficiency for wafer transfer. However, the faster wafer transfer robot moves, the bigger the force applied on its support frame is, and also the bigger vibration aroused on the frame because of the low stiffness of the support frame. Meanwhile, some IC equipment are ultra-high sensitive to

Yanjie Liu; Mingyue Wu; Guobao Xu; Lining Sun

2011-01-01

202

Wafer-Level ANA Calibrations at NIST  

Microsoft Academic Search

The National Institute of Standards and Technology has begun a program supporting on-wafer scattering parameter measurements. In contrast to many previous NIST endeavors, this program seeks to transfer methodology into industrial measurement laboratories. The subject of this paper is the development of calibration techniques and algorithms, rather than physical standards, for the measurement of on-wafer scattering parameters. In particular, we

Roger Marks; Kurt Phillips

1989-01-01

203

LSA project perspective of wafering technology  

NASA Astrophysics Data System (ADS)

The economics and techniques for eliminating wafering as a part of ingot technology in the production of silicon sheets for photovoltaic applications are considered. Technical progress in both ingot and non-ingot technologies for the low cost solar array project is described in the context of process economics. The critical areas of research in wafering are delineated and their payoff potential discussed.

Koliwad, K. M.

1982-02-01

204

Molecular dynamics simulations of silicon wafer bonding  

Microsoft Academic Search

Molecular dynamics simulations based on a modified Stillinger-Weber potential are used to investigate the elementary steps of bonding two Si(0 0 1) wafers. The energy dissipation and thus the dynamic bonding behaviour are controlled by the transfer rates for the kinetic energy. The applicability of the method is demonstrated by studying the interaction of perfect wafer surfaces (UHV conditions). First

D. Conrad; K. Scheerschmidt; U. Gösele

1995-01-01

205

Cryogenic wafer prober for Josephson devices  

SciTech Connect

A wafer probing system has been built for the testing of Josephson junction devices at helium temperature. A mechanism moves a probe card from one position to another on a two inch wafer while immersed in liquid helium. The mechanism is actuated by shafts which connect to stepper motors positioned above the helium dewar. A positioning accuracy of + or - 50 ..mu..m at the probe tips is achieved. The replaceable probe card is all ceramic and carries 120 rigidly mounted palladium-alloy needles, arranged in signal-ground pairs and positioned in an array which matches the pad design of the particular device under test. Controlled impedance transmission lines are maintained all the way to the wafer's surface. A computer interface is included so that probing of a whole wafer can be conducted under software control. The system is intended for routine testing of Josephson devices in wafer form as well as for testing very large numbers of individual junctions.

Geary, J.; Vella-Coleiro, G.

1983-05-01

206

Switchable static friction of piezoelectric composite--silicon wafer contacts  

NASA Astrophysics Data System (ADS)

The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and a silicon wafer counter surface rests solely on the matrix region of the piezocomposite surface. When actuated, the piezoelectric ceramic fibers protrude from the surface and the wafer rests solely on these protrusions. A threefold decrease in engineering static friction coefficient upon actuation of the piezocomposite was observed: from ?* = 1.65 to ?* = 0.50. These experimental results could be linked to the change in contact surface area and roughness using capillary adhesion theory, which relates the adhesive force to the number and size of the contacting asperities for the different surface states.

van den Ende, D. A.; Fischer, H. R.; Groen, W. A.; van der Zwaag, S.

2013-04-01

207

Yield-driven multi-project reticle design and wafer dicing  

NASA Astrophysics Data System (ADS)

The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies has lead to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such low volume designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle design and wafer dicing introduce complexities not encountered in typical, single-project wafers. Recent works on wafer dicing adopt some assumptions to reduce the problem complexity. Although using one or more assumptions makes the problem solvable, the feasibility or performance of the solutions may be degraded. Also, the delay cost associated with schedule alignment was ignored in all previous works. In this paper we propose a general MPW flow including four main steps: (1) schedule-aware project partitioning (2) multi-project reticle floorplanning, (3) wafer shot-map definition, and (4) wafer dicing plan definition. Our project partitioner provides the best trade-off between the mask cost and delay cost. Our reticle floorplaner can automatically clone a design to better fit given production volumes. The round wafer shot-map definition step allows extracting functional dies from partially printed reticle images. Finally, our dicing planner allows multiple side-to-side dicing plans for different wafers and image rows/columns within a wafer. Experiments on industry testcases show that our methods outperform significantly not only previous methods in the literature, but also reticle floorplans manually designed by experienced engineers.

Kahng, Andrew B.; Mandoiu, Ion; Xu, Xu; Zelikovsky, Alex

2005-11-01

208

Universal segregation growth approach to wafer-size graphene from non-noble metals.  

PubMed

Graphene has been attracting wide interests owing to its excellent electronic, thermal, and mechanical performances. Despite the availability of several production techniques, it is still a great challenge to achieve wafer-size graphene with acceptable uniformity and low cost, which would determine the future of graphene electronics. Here we report a universal segregation growth technique for batch production of high-quality wafer-scale graphene from non-noble metal films. Without any extraneous carbon sources, 4 in. graphene wafers have been obtained from Ni, Co, Cu-Ni alloy, and so forth via thermal annealing with over 82% being 1-3 layers and excellent reproducibility. We demonstrate the first example of monolayer and bilayer graphene wafers using Cu-Ni alloy by combining the distinct segregation behaviors of Cu and Ni. Together with the easy detachment from growth substrates, we believe this facile segregation technique will offer a great driving force for graphene research. PMID:21128676

Liu, Nan; Fu, Lei; Dai, Boya; Yan, Kai; Liu, Xun; Zhao, Ruiqi; Zhang, Yanfeng; Liu, Zhongfan

2010-12-03

209

EFECTO DE LA GEOMETRÍA DEL MOLDE EN EL ELECTROFORMADO DE MICROPIEZAS POR UV-LIGA EFFECT OF MOLD GEOMETRY IN MICROPARTS ELECTROFORMING BY UV-LIGA  

Microsoft Academic Search

UV-LIGA is a versatile technique which allows the fabrication of metal parts with high aspect ratio (height \\/ width) through the combination of a photolithographic processing of a polymer and the electroforming of a metal inside the cavities engraved in the polymer. This low-cost technique is used in a variety of areas including microfluidic, optics, instrumentation, plastic molding and telecommunications,

JUAN C. GAVIRIA VILLA; JOHNATAN M. CASTELBLANCO; LUZ M. OCAMPO CARMONA; SERGIO LOPERA

2009-01-01

210

New laser scanning techniques for wafer inspection  

NASA Astrophysics Data System (ADS)

A laser scanning system designed for inspection of patterned wafers is described. This system addresses the inspection needs for 64 Mb (0.35 micrometers ) and 256 Mb (0.25 micrometers ) DRAM process technologies. The system is capable of detecting contaminant particles and planar pattern defects on memory and logic devices. The throughput of the system is designed for 30 wafers (200 mm in diameter) per hour. The beam at 488 nm is brought to a focal spot and is scanned on the wafer surface using an acousto-optic deflector (AOD). The entire wafer is scanned under oblique illumination in narrow strips in a serpentine fashion. The specular beam is collected and processed in, what we have named, the autoposition sensor (APS) to servo- lock the height position of the wafer during the scan. The system utilizes multiple independent collection channels positioned around the scan line and it is possible to select the polarization of the collected light for enhanced signal-to-background ratio. The engineering tradeoffs for realizing a system with high throughput and sensitivity are formulated and discussed. Calculations ilustrating scattering from submicron size particles under various polarization conditions are shown. These results lead to optimum design for collection optics. The APS channel is described and illustrated by results indicating that it is possible to keep the surface height of the wafer constant to within 0.4 micrometers in the presence of large changes in topography and wafer reflectivity. Results obtained from a range of production wafers demonstrating detection of 0.1 micrometers anomalies on bare wafer, 0.3 micrometers on memory devices, and 0.4 micrometers on random logic structures are presented.

Nikoonahad, Mehrdad; Leslie, Brian C.; Stokowski, Stanley E.; Trafas, Brian M.; Wells, Keith B.

1995-09-01

211

Three wafer stacking for 3D integration.  

SciTech Connect

Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

2011-11-01

212

Development of megasonic cleaning for silicon wafers  

NASA Astrophysics Data System (ADS)

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Mayer, A.

1980-09-01

213

Metal Enhanced Fluorescence on Silicon Wafer Substrates.  

PubMed

We report on the fluorescence enhancement induced by silver island film (SIF) deposited on a silicon wafer. The model immunoassay was studied on silvered and unsilvered wafers. The fluorescence brightness of Rhodamine Red X increased about 300% on the SIF, while the lifetime was reduced by several fold and the photostability increased substantially. We discuss potential uses of silicon wafer substrates in multiplex assays in which the fluorescence is enhanced due to the SIF, and the multiplexing is achieved by using micro transponders. PMID:19137060

Gryczynski, I; Matveeva, E G; Sarkar, P; Bharill, S; Borejdo, J; Mandecki, W; Akopova, I; Gryczynski, Z

2008-10-01

214

Enhancing the Reliability of Wafer Level Packaging by Using Solder Joints Layout Design  

Microsoft Academic Search

During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint shape prediction methods have been incorporated as a

Chang-Ming Liu; Chang-Chun Lee; Kuo-Ning Chiang

2006-01-01

215

Image quality and wafer level optics  

NASA Astrophysics Data System (ADS)

Increasing demand from consumers to integrate camera modules into electronic devices, such as cell phones, has driven the cost of camera modules down very rapidly. Now that most cell phones include at least one camera, consumers are starting to ask for better image quality - without compromising on the cost. Wafer level optics has emerged over the past few years as an innovative technology enabling simultaneous manufacturing of thousands of lenses, at the wafer level. Using reflow-compatible materials to manufacture these lenses permits a reduction in the cost and size of camera module, thus answering the market demand for lowering the cost. But what about image quality? The author will present image quality analysis that was conducted for both VGA and megapixel camera resolutions. Comparison between conventional camera modules and wafer level camera modules shows wafer level technology brings equivalent, if not better, image quality performance compared to conventional camera modules.

Dagan, Y.; Humpston, G.

2010-04-01

216

Everything Wafers: A Guide to Semiconductor Substrates  

NSDL National Science Digital Library

This website contains information on characteristics and properties of semiconductor wafers. Topics include types of substrates, process dependent characteristics, properties of semiconductors, cleaving, etching and other topics, along with related terms and links.

2012-11-29

217

Silicon wafer bonding through RF dielectric heating  

Microsoft Academic Search

This paper presents a new silicon wafer bonding process based on radio-frequency (RF) heating of an intermediate dielectric layer. The method uses a capacitive RF field to heat a dielectric interlayer up to its glass transition temperature and permanently join two wafers. A 500W 14MHz source was used to deliver RF power to the substrates. A 5cm diameter 300?m thick

Andrey Bayrashev; Babak Ziaie

2003-01-01

218

Experiment on microstructure fabrication with UV-LIGA technology  

NASA Astrophysics Data System (ADS)

The field of micro electromechanical systems (MEMS), particularly micro sensors and transducers, has been expanding over recent years, and the production of these devices continue to grow up. With SU-8 photoresist, the technology of UV-LIGA has been developed as an important method of fabrication micro structures. The process consisting of photolithographic and microelectroforming were studied in this paper. Orthogonal experimental design were applied in research. From experiment it can be concluded that the soft bake temperature and time was the key factor of the structure quality. When the photoresist thickness ranged from 120 to 340µm, the soft bake temperature and time was 90 and 50~120 minutes, that means the perfect image. The best post expose bake temperature was 85 95 with less 40 minutes bake. In order to obtain the suitable parameters of the various thickness photoresist, an artificial neural network (ANN) with 3 layers were built. The ANN were trained based on orthogoality experiment using back propagation algorithm. Compared to the experiment results, the prediction error was less than 2.0%, which proved that the ANN was effective. The characteristics of the microelectroforming process were analysed systematically. The results showed that the mass transfer is the control factors of microelectroforming process. During the developing of the photoresist, ultrasonic stirring could shorten the developing time and improve the micro mould quality effectively.The lithographic and microelectroforming process of the fabrication of high resolute micro structure was optimized.

Zheng, Xiaohu

2008-12-01

219

A bulk silicon dissolved wafer process for microelectromechanical devices  

Microsoft Academic Search

A single-sided bulk silicon dissolved wafer process that has been used to fabricate several different micromechanical structures is described. It involves the simultaneous processing of a glass wafer and a silicon wafer, which are eventually bonded together electrostatically. The silicon wafer is then dissolved to leave heavily boron doped devices attached to the glass substrate. Overhanging features can be fabricated

Yogesh B. Gianchandani; Khalil Najafi

1992-01-01

220

Full-wafer loss measurements of silicon ridge waveguides  

Microsoft Academic Search

We present full-wafer loss data for ridge waveguides for three different geometries fabricated on 150 mm silicon-on- insulator wafers. Full-wafer testing was made possible by a vertically coupled, automated test system. Keywords-silicon; integrated photonics; waveguide; full wafer; grating coupler

Michael Gould; Jing Li; Tom Baehr-Jones; Michael Hochberg

2011-01-01

221

Metal-assisted homogeneous etching of single crystal silicon: A novel approach to obtain an ultra-thin silicon wafer  

NASA Astrophysics Data System (ADS)

Homogeneous etching of silicon is achieved through one-step metal-assisted chemical etching (MACE), which offers a simple route to obtain the ultra-thin silicon wafer with thickness below 50 ?m. The surface of the ultra-thin silicon wafer obtained by this method is smooth at the nanometer scale, and its surface roughness is around 10 nm. The homogenous etching mechanism is discussed in terms of the hole injection principle. It's found that the introduction of a high concentration of H2O2 facilitates the uniform distribution of the holes injected on the silicon surface, causing the homogeneous etching of the silicon. Meanwhile, the thinning is uniform across a large wafer area, and ultra thin silicon wafers up to 4 in. in diameter were obtained. Furthermore, any thickness of silicon wafer within 30-180 ?m can be obtained by modulating the etching process accurately.

Bai, Fan; Li, Meicheng; Song, Dandan; Yu, Hang; Jiang, Bing; Li, Yingfeng

2013-05-01

222

Surface Impurities Encapsulated by Silicon Wafer Bonding  

NASA Astrophysics Data System (ADS)

Wafer bonding techniques are shown to provide an important addition to methods used for the detection of residual impurities on the surfaces of polished and cleaned silicon wafers. Impurities were encapsulated in the interface made by wafer bonding, and analyzed by SIMS depth profiling. Significant concentrations of H, C, N, O, F and Cl were detected. The concentration of these elements did not change after two hour wafer bonding anneals in the range of 200°C to 800°C. For anneals at 1000°C and above both the diffusion of H and C from the bonded interface, and the aggregation of N and O were observed. It was confirmed by IR absorption and HR-TEM that oxygen in CZ crystals outdiffuses into the bonded interface and produces an SiO2 layer. Low-oxygen FZ wafers were used as a reference comparison. Elements such as F and Cl contained in the chemicals used to clean the wafers remained fixed at the bonded interface for the entire temperature range tested.

Abe, Takao; Uchiyama, Atsuo; Yoshizawa, Katsuo; Nakazato, Yasuaki; Miyawaki, Mamoru; Ohmi, Tadahiro

1990-12-01

223

Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies  

Microsoft Academic Search

The important method of bonding wafers to wafers or die to wafers has been discussed in an earlier chapter. In this chapter, we will examine the formation and filling of through-silicon vias (TSVs) and the post-bond process of thinning waferto-wafer pairs to further process TSVs and build metallization on the final exposed surface. In the section on wafer thinning, the

Sharath Hosali; Greg Smith; Larry Smith; Susan Vitkavage; Sitaram Arkalgud

224

A MEMS-Based Micro Biopsy Actuator for the Capsular Endoscope Using LiGA Process  

NASA Astrophysics Data System (ADS)

This paper presents a LiGA (German acronym for LIthografie, Galvanoformung, Abformung) based micro biopsy actuator for the capsular endoscope. The proposed fabricated actuator aims to extract sample tissues inside small gastric intestines, that cannot be reached by conventional biopsy. The actuator size is 10 mm in diameter and 1.8 mm in length. The mechanism is of a slider-crank type. The actuator consists of trigger, rotational module, and micro biopsy tool. The core components are fabricated using the LiGA process, for overcoming the limitations in accuracy of conventional precision machining.

Park, Sunkil; Koo, Kyo-In; Kim, Gil-Sub; Bang, Seoung Min; Song, Si Young; Chu, Chong Nam; Jeon, Doyoung; Cho, Dongil ``Dan''

2007-01-01

225

Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics  

SciTech Connect

Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

None

2010-01-15

226

Wafer-fused semiconductor radiation detector  

DOEpatents

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

2002-01-01

227

Combustion synthesis of LiGa and LiAl intermetallic alloys  

NASA Astrophysics Data System (ADS)

LiAl and LiGa intermetallic alloys have been synthesized using the simultaneous combustion mode of combustion synthesis. LiAl intermetallic is potentially suitable as a temper alloy for producing aluminum-lithium alloys and as an anodic material for high-energy batteries. LiGa can be used as a reduction alloy to recover valuable reactive metals from molten salt effluent in actinide recovery technology. The effects of particle size, preignition heating rate, and theoretical green density on the ignition and combustion temperatures have been studied in an effort to more precisely control the synthesis reaction of these intermetallics. A lithium particle size of -20 /xm was found to be suitable when the combustion synthesis reaction was conducted at a high heating rate (>1.0 cC/s) and a moderate green density (55 to 65 pct theoretical). Preignition diffusion is suggested as the cause for low exothermic heat release at high green densities. A combustion temperature above the melting point of the LiGa intermetallic compound can be achieved under optimized conditions. However, the exothermicity and, therefore, the adiabatic temperature is too low for either LiAl or LiGa to be produced by the propagating mode of combustion synthesis.

Pritchett, S. R.; Mishra, B.; Moore, J. J.

1995-02-01

228

Combination of a fluidic microoscillator and micro-actuator in LIGA-technique for medical application  

Microsoft Academic Search

In this paper for the first time a modular built dynamic microsystem consisting of a combination of two separately fully functional fluidic devices fabricated by the LIGA-technique is presented. One of the two devices is a fluidic micro-oscillator, which needs only one fluid supply to generate an oscillating fluid jet at its two output ports. The other device is a

Ute Gebhard; Herbert Hein; E. Just; P. Ruther

1997-01-01

229

Bandpass filters made by LIGA for the THZ region: Manufacturing and testing  

NASA Astrophysics Data System (ADS)

LIGA including deep X-ray lithography has been used to form cross patterns in free-standing foils of different thickness between 20 and 2000 ?m. The patterns show bandpass filter behaviors for wavelengths in the 300-800 ?m region. Transmittances as high as 99% were achieved, for both, a mercury lamp and the ANKA storage ring in the THz-mode.

Nazmov, V.; Reznikova, E.; Mathis, Y.-L.; Mathuni, J.; Müller, A.; Rudych, P.; Last, A.; Saile, V.

2009-05-01

230

[Effect of using dosated ligating apparatus LigaSure during operative interventions on the abdominal organs].  

PubMed

There was summarized the experience of application of energetic platform, named "Force triad", manufactured by Valleylab firm, which secures electric vascular ligating regime "LigaSure" of second generation, while performing operative interventions on abdominal organs. Variants of the application regimes, depending on the vessels diameter and concomitant diseases presence, were summarized. PMID:23888718

Sukhin, I A; Ambrush, O O; Bilylovets', O M; Honchar, I V; Ihnat'ieva, O K; Kocherha, N V

2013-04-01

231

Recruiting and Integrating Personnel in a Sporting Organization. Case Study: Liga Economistului, 2010-2011 Season  

Microsoft Academic Search

The paper presents how the recruitment and integration process of personnel was managed in Liga Economistului, a football championship in college sport. Sporting organizations, like for example leagues, clubs, associations, federations or teams, may find themselves in the situation of selecting and integrating personnel in order to fulfil needs or demands induced by participating athletes or teams, managerial structures, fans

Vlad ROSCA

2011-01-01

232

Simple tilt and height location monitoring of wafers  

NASA Astrophysics Data System (ADS)

Good alignment is needed in various wafer processes. Reflectometry is a well-established technique that continues to be widely used to monitor the thickness of wafer thin films. The use of a reflectometer was investigated to detect incorrect tilt and height of wafer placement. We found that it could be used in the spectroscopic or the monochromatic mode and provided results whether the wafer was bare or coated. We also found that the technique was somewhat more sensitive to tilt of bare wafers, and more sensitive to height displacements of coated wafers.

Ng, Tuck Wah; Tay, Arthur E. B.

2006-05-01

233

Calculation of emissivity of Si wafers  

SciTech Connect

A computer-software, Emissivity, has been developed to calculate the emissivity ({epsilon}) of silicon wafers of any surface morphology, for a given temperature and dopant concentration. The software uses a combination of ray- and wave-optics approaches to include the interference and the polarization effects necessary for multilayer surface coatings and multi-reflections within thin wafers. The refractive index and the absorption coefficient are calculated as a function of temperature and dopant concentration using an empirical model for an indirect bandgap semiconductor. The results of this model are compared with conventional emissivity calculations and experimental data.

Sopori, B.; Chen, W.; Madjdpour, J.; Ravindra, N.M.

1999-11-12

234

Optical metrology of semiconductor wafers in lithography  

NASA Astrophysics Data System (ADS)

This paper presents a concise description of 3 optical measurement systems that play a critical role in optical lithography of semiconductor devices. A level sensor and alignment sensor are described that are used to measure, respectively, wafer height variations and the wafer location prior to resist exposure. The third sensor is an angle-resolved scatterometer that is used to measure the shape (CD) and placement (Overlay) of the resist patterns. It will be shown how these sensors deal with the common challenge of realizing sub-nm precision on a large variety of product stacks in the presence of process variations.

den Boef, Arie J.

2013-06-01

235

Total x-ray power measurements in the Sandia LIGA program.  

SciTech Connect

Total X-ray power measurements using aluminum block calorimetry and other techniques were made at LIGA X-ray scanner synchrotron beamlines located at both the Advanced Light Source (ALS) and the Advanced Photon Source (APS). This block calorimetry work was initially performed on the LIGA beamline 3.3.1 of the ALS to provide experimental checks of predictions of the LEX-D (LIGA Exposure- Development) code for LIGA X-ray exposures, version 7.56, the version of the code in use at the time calorimetry was done. These experiments showed that it was necessary to use bend magnet field strengths and electron storage ring energies different from the default values originally in the code in order to obtain good agreement between experiment and theory. The results indicated that agreement between LEX-D predictions and experiment could be as good as 5% only if (1) more accurate values of the ring energies, (2) local values of the magnet field at the beamline source point, and (3) the NIST database for X-ray/materials interactions were used as code inputs. These local magnetic field value and accurate ring energies, together with NIST database, are now defaults in the newest release of LEX-D, version 7.61. Three dimensional simulations of the temperature distributions in the aluminum calorimeter block for a typical ALS power measurement were made with the ABAQUS code and found to be in good agreement with the experimental temperature data. As an application of the block calorimetry technique, the X-ray power exiting the mirror in place at a LIGA scanner located at the APS beamline 10 BM was measured with a calorimeter similar to the one used at the ALS. The overall results at the APS demonstrated the utility of calorimetry in helping to characterize the total X-ray power in LIGA beamlines. In addition to the block calorimetry work at the ALS and APS, a preliminary comparison of the use of heat flux sensors, photodiodes and modified beam calorimeters as total X-ray power monitors was made at the ALS, beamline 3.3.1. This work showed that a modification of a commercially available, heat flux sensor could result in a simple, direct reading beam power meter that could be a useful for monitoring total X-ray power in Sandia's LIGA exposure stations at the ALS, APS and Stanford Synchrotron Radiation Laboratory (SSRL).

Malinowski, Michael E. (Sandia National Laboratories, Livermore, CA); Ting, Aili (Sandia National Laboratories, Livermore, CA)

2005-08-01

236

Wafer bonding of wide bandgap materials  

NASA Astrophysics Data System (ADS)

Wafer bonding is a powerful technique for integration of materials. It enables creation of junctions and structures not attainable by the epitaxial growth due to lattice mismatch. Wafer bonding may involve no intermediate layer and allow the joined wafers to be stable at elevated temperatures. Atomically smooth and flat wafers of almost any material spontaneously bond to each other even at room temperature, although further annealing might be required to increase the strength of bonding. High values of surface roughness make the bonding process more challenging. In this case, high temperature combined with applied stress is an effective route for a successful process. The goal of the current work was to assess the potential of pressure assisted wafer bonding technique applied to diamond/silicon and silicon carbide/silicon carbide systems, where the wafer surface smoothness was limited. Polished and unpolished (100) highly oriented diamond (HOD) films with an RMS roughness of 5 nm and 150 nm, respectively, as well as polished, polycrystalline diamond films with an RMS roughness of 15 nm were bonded to single-side polished silicon in ultra high vacuum at 32 MPa of applied uniaxial pressure. Successful fusion of unpolished HOD and polished polycrystalline diamond was observed at temperatures as low as 950°C while bonding of polished HOD to silicon was achieved at 850°C. Fusion of polished polycrystalline diamond to silicon resulted in the formation of a non-uniform bonded interface. An abrupt boundary between the two wafers existed only in some regions of the interface, while other regions contained an up to 40 nm thick amorphous interlayer consisting of C, Si and O. A local phase transformation of diamond to graphite near the diamond surface asperities followed by inter-diffusion of C and Si has been suggested. Fusion of polished HOD to Si resulted in the formation of the abrupt interface between the wafers, in the areas away from the diamond grain boundaries. Voids, partially filled with amorphous material, were observed at the fused interface near the diamond grain boundaries. Diamond polishing defects, potential out-diffusion of hydrogen from diamond and oxygen from Si are believed to have contributed to the observed non-uniformity of the bonded interface. SiC wafers with an RMS roughness of 2 run were successfully bonded at temperatures as low as 800°C. Cross-section transmission electron microscopy (XTEM) of specimens bonded at 1100°C revealed an atomically abrupt interface between the bonded wafers without any intermediate layer between them. The bonded SiC retained its high crystalline quality; no extended defects emanating from the interface were observed within the sampling region. Electrical measurements showed that azimuthal orientation of the bonded couple significantly influences the electrical character of the junction. A low resistance Ohmic interface can be created by high temperature fusion of aligned 6H-SiC/6H-SiC wafers.

Yushin, Gleb Nikolayevich

237

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder  

NASA Astrophysics Data System (ADS)

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

238

Reliability enhancement of wafer level packaging using solder ball layout methodology  

Microsoft Academic Search

In the design and manufacturing process of electric packaging, solder joint are generated with a variety of methods to provide both mechanical and electrical connection for applications such as flip chip, wafer level packaging, fine pitch ball grid array (BGA), and chip scale packaging (CSP). Solder joint shape prediction method has been incorporated as a design tool to enhance the

Chang-Ming Liu; Kuo-Ning Chiang

2005-01-01

239

Solder bumps layout design and reliability enhancement of wafer level packaging  

Microsoft Academic Search

In the design and manufacturing process of electric packaging, solder joint are generated with a variety of methods to provide both mechanical and electrical connection for applications such as flip chip, wafer bevel packaging, fine pitch ball grid array (BGA), and chip scale packaging (CSP). Solder joint shape prediction method has been incorporated as a design tool to enhance the

Chang-Ming Liu; Kuo-Ning Chiang

2003-01-01

240

Solder fatigue of Wafer Level package assemblies. Comparison with flip chip BGA’S  

Microsoft Academic Search

In this paper the solder fatigue of WLCSP (wafer level chip scale packages) assemblies is studied and a comparison with flip chip BGA is made. Previous works have already shown that for BGA, the most critical parameters are size, thickness, and underfill. We have evaluated both by thermal cycling and by simulations the effect of thickness and underfill in the

Charles Regard; Christian Gautier; Hélène Frémont; Alexandre Val; Frédéric Roullier; Patrice Schwindenhammer; Patrick Poirier

2008-01-01

241

Integration of a low stress photopatternable silicone into a wafer level package  

Microsoft Academic Search

This paper describes a novel wafer level package using a silicone under the bump (SUB) design. The SUB architecture is designed to access the elastomeric qualities of silicones to reduce stresses on solder joints in a chip scale package. Poor reliability of the solder joints frequently arises from stresses generated by the mismatch in coefficient of thermal expansion between the

G. Gardner; B. Harkness; E. Ohare; H. Meynen; M. Vanden Bulcke; M. Gonzalez; E. Beyne

2004-01-01

242

Influence of Silicon on Insulator Wafer Stress Properties on Placement Accuracy of Stencil Masks  

Microsoft Academic Search

The issue of placement control is one of the key challenges of stencil mask technology. A high placement accuracy can only be achieved with a precise control of mechanical stress on a global and local scale. For this reason, the stress properties of the mask blank material -typically silicon on insulator (SOI) wafers- have to be known and adjusted properly.

Frank-Michael Kamm; Albrecht Ehrmann; Herbert Schäfer; Werner Pamler; Rainer Käsmaier; Jörg Butschke; Reinhard Springer; Ernst Haugeneder; Hans Löschner

2002-01-01

243

Separation between Surface and Volume Decay Times of Photoconductivity in p-Type Silicon Wafers  

Microsoft Academic Search

Excess photocarriers excited in silicon wafers are annihilated both in surface and volume regions independently of each other. When a photoconductive decay curve obtained with the microwave-detected photoconductive decay method is concave in semi-logarithmic scale, those two decay times in the different regions can be separately derived from the experimental data on assuming two independent exponential functions for the annihilation

Chusuke Munakata; Takumi Suzuki

2006-01-01

244

Wafer-level package interconnect options  

Microsoft Academic Search

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare

Jayaprakash Balachandran; Steven Brebels; Geert Carchon; Maarten Kuijk; Walter De Raedt; Bart K. J. C. Nauwelaers; Eric Beyne

2006-01-01

245

Contactless magnetically levitated silicon wafer transport system  

Microsoft Academic Search

A new magnetically levitated wafer transport system is developed for the semiconductor fabrication process to get rid of the particle and oil contaminations that normally exist in conventional transport systems. The transport system consists of levitation, stabilization tracks, and a propelling system. Stabilities needed for levitation in the transport system are achieved by an antagonistic property produced in the tracks

K. H. Park; S. K. Lee; J. H. Yi; S. H. Kim; Y. K. Kwak; I. A. Wang

1996-01-01

246

Methanol Steam Reformer on a Silicon Wafer  

SciTech Connect

A study of the reforming rates, heat transfer and flow through a methanol reforming catalytic microreactor fabricated on a silicon wafer are presented. Comparison of computed and measured conversion efficiencies are shown to be favorable. Concepts for insulating the reactor while maintaining small overall size and starting operation from ambient temperature are analyzed.

Park, H; Malen, J; Piggott, T; Morse, J; Sopchak, D; Greif, R; Grigoropoulos, C; Havstad, M; Upadhye, R

2004-04-15

247

Scanning holographic scatterometer for wafer surface inspection  

NASA Astrophysics Data System (ADS)

The semiconductor industry requires ever smaller semiconductor structures with faster response times and more function per unit area of each chip. In addition, the industry is changing from 200 mm to 300 mm diameter wafers with fewer defects and rapid detection at all processing stages. To meet these needs, defect data must be processed in near-real-time to expedite correction of processing problems at the earliest possible stage. Under a Small Business Innovation Research (SBIR) program, sponsored by the Air Force Manufacturing Technology Division at Wright Laboratory, Dayton, Ohio, Sentec Corporation has developed a revolutionary technology for contaminant particle detection on unpatterned semiconductor wafers. A key to the Sentec technology is detection, not of the intensity of backscattered energy from particles or defects, but of the amplitude of the electro-magneitc field of this backscattered energy. This new technology will allow the detection of particles that are significantly smaller than those which can be reliably located using current scatterometers. The technical concepts for a stand-alone particle detection tool have been created. It uses a continuous scanning mechanism to perform high-speed examinations of target wafers. This tool, also, has the capability of quantifying the microroughness or background haze of a subject wafer and presenting that information separate from the contamination particle data. During the course of this project, three patent applications were filed.

Klooster, Alex; Marks, James; Hanson, Kael; Sawatari, Takeo

2004-05-01

248

Rapid isothermal processing of silicon wafers  

Microsoft Academic Search

The reduction in the size of semiconductor devices has not only increased their speed and the number that can be fitted on a chip but has also led to the need for very accurately controlled thermal processing of the semiconductor wafers. Conventional furnaces are used as standard in IC processing but now, however, alternative rapid isothermal processing technologies are gaining

S. S. Gill

1986-01-01

249

Laser cutting of CVD diamond wafers  

Microsoft Academic Search

CVD diamond has many outstanding physical properties. Because of its extreme hardness, this material is difficult to cut and polish and laser cutting and shaping is a technology of choice. Thick polycrystalline diamond layers were deposited by microwave plasma enhanced chemical vapor deposition on silicon substrates. After synthesis, the silicon substrate was dissolved in an acid mixture and diamond wafer

Hana Chmelickova; Milan Vanecek; Jan Rosa; Martin Stranyanek

2005-01-01

250

Innovative optical alignment technique for CMP wafers  

Microsoft Academic Search

Detecting position of the wafers such as after CMP process is critical theme of current and forthcoming IC manufacturing. The alignment system must be with high accuracy for any process. To satisfy such requirements, we have studied and analyzed factors that have made alignment difficult. From the result of the studies, we have developed new optical alignment techniques which improve

Ayako Sugaya; Yuho Kanaya; Shinichi Nakajima; Tadashi Nagayama; Naomasa Shiraishi

2002-01-01

251

Release of arsenic from semiconductor wafers  

SciTech Connect

The production of integrated circuits and other semiconductor devices requires the introduction of impurities or dopants into the crystal lattice of a silicon substrate. This doping or junction formation is achieved through one of two processes: thermal diffusion or ion implantation. Ion implantation, the more contemporary and more accurate of the two processes, accomplishes junction formation by bombarding selected areas of the silicon wafer with a beam of dopantions. Inorganic arsenic, which is regulated by the Occupational Health and Safety Administration (OSHA) as a carcinogen, is frequently used as dopant material. Silicon wafers are found to emit inorganic arsenic following ion implantation. Data collected during this experiment demonstrate that arsenic is released over a 3.5-hour period following implantation and that the total amount of arsenic emitted may approach 6.0 ..mu..g per 100 wafers processed within 4 hours after implantation. The discovery and quantification of this phenomenon suggest that newly implanted silicon wafers are a potential source of arsenic contamination-a source that may impact both the quality of the work environment and the integrated circuit product.

Ungers, L.J.; Jones, J.H.; McIntyre, A.J.; McHenry, C.R.

1985-08-01

252

Release of arsenic from semiconductor wafers.  

PubMed

The production of integrated circuits and other semiconductor devices requires the introduction of impurities or dopants into the crystal lattice of a silicon substrate. This "doping" or junction formation is achieved through one of two processes: thermal diffusion or ion implantation. Ion implantation, the more contemporary and more accurate of the two processes, accomplishes junction formation by bombarding selected areas of the silicon wafer with a beam of dopant ions. Inorganic arsenic, which is regulated by the Occupational Health and Safety Administration (OSHA) as a carcinogen, is frequently used as dopant material. Silicon wafers are found to emit inorganic arsenic following ion implantation. Data collected during this experiment demonstrate that arsenic is released over a 3.5-hour period following implantation and that the total amount of arsenic emitted may approach 6.0 micrograms per 100 wafers processed within 4 hours after implantation. The discovery and quantification of this phenomenon suggest that newly implanted silicon wafers are a potential source of arsenic contamination--a source that may impact both the quality of the work environment and the integrated circuit product. PMID:4050678

Ungers, L J; Jones, J H; McIntyre, A J; McHenry, C R

1985-08-01

253

Low-temperature full wafer adhesive bonding  

Microsoft Academic Search

We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 µm and 18 µm. The tested polymer materials were benzocyclobutene (BCB)

Frank Niklaus; Peter Enoksson; Edvard Kälvesten; Göran Stemme

2001-01-01

254

Silicon waveguides produced by wafer bonding  

SciTech Connect

X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 {mu}m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides to excite single guided modes at typical x-ray energies.

Poulsen, M.; Jensen, F.; Bunk, O.; Feidenhans'l, R.; Breiby, D.W. [Department of Micro and Nanotechnology, Technical University of Denmark, Oersteds Plads, DK-2800 Kgs. Lyngby (Denmark) and Materials Research Department, Risoe National Laboratory, Frederiksborgvej 399, DK-4000 Roskilde (Denmark); DANCHIP, Technical University of Denmark, Oersteds Plads, DK-2800 Kgs. Lyngby (Denmark); Materials Research Department, Risoe National Laboratory, Frederiksborgvej 399, DK-4000 Roskilde (Denmark); Danish Polymer Centre, Risoe National Laboratory, Frederiksborgvej 399, DK-4000 Roskilde (Denmark)

2005-12-26

255

Waveguide probe tackles V-band on-wafer tests  

Microsoft Academic Search

As millimeter-wave MMIC processes mature, requirements for manufacturing process control and product performance testing drive the need for V-band on-wafer testing. Semiconductor wafer probes for RF measurements are outlined, as well as commercial wafer probes based on the 1.85-mm coaxial connector supporting on-wafer device measurements up to 65 GHz. A waveguide architecture requiring the development of a waveguide-to-coplanar -waveguide (CPW)

Keith Jones; Ed Godshalk

1990-01-01

256

Wafer-level hermetic packaging technology for MEMS using anodically-bondable LTCC wafer  

Microsoft Academic Search

This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature cofired ceramic (LTCC) wafer, in which electrical feedthroughs and passive components can be embedded. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of heat shock (?40 °C\\/+150 °C, 30 min\\/30 min) by diaphragm method. The width of seal rings necessary for hermetic

Shuji Tanaka; Sakae Matsuzaki; Mamoru Mohri; Atsushi Okada; Hideyuki Fukushi; Masayoshi Esashi

2011-01-01

257

Automated reticle inspection data analysis for wafer fabs  

Microsoft Academic Search

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the

Derek Summers; Gong Chen; Bryan Reese; Trent Hutchinson; Marcus Liesching; Hai Ying; Russell Dover

2008-01-01

258

Automated reticle inspection data analysis for wafer fabs  

Microsoft Academic Search

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the

Derek Summers; Gong Chen; Bryan Reese; Trent Hutchinson; Marcus Liesching; Hai Ying; Russell Dover

2009-01-01

259

Wafer LMC accuracy improvement by adding mask model  

NASA Astrophysics Data System (ADS)

Mask effect will be more sensitive for wafer printing in high-end technology. For advance only using current wafer model can not predict real wafer behavior accurately because it do not concern real mask performance (CD error, corner rounding..). Generally, we use wafer model to check whether our OPC results can satisfy our requirements (CD target). Through simulation on post-OPC patterns by using wafer model, we can check whether these post-OPC patterns can meet our target. Hence, accuracy model can help us to predict real wafer printing results and avoid OPC verification error. To Improve simulation verification accuracy at wafer level and decrease false alarm. We must consider mask effect like corner rounding and line-end shortening...etc in high-end mask. UMC (United Microelectronics Corporation) has cooperated with Brion and DNP to evaluate whether the wafer LMC (Lithography Manufacturability Check) (Brion hot spots prediction by simulation contour) accuracy can be improved by adding mask model into LMC verification procedure. We combine mask model (DNP provide 45nm node Poly mask model) and wafer model (UMC provide 45nm node Poly wafer model) then build up a new model that called M-FEM (Mask Focus Energy Matrix model) (Brion fitting M-FEM model). We compare the hotspots prediction between M-FEM model and baseline wafer model by LMC verification. Some different hotspots between two models were found. We evaluate whether the hotspots of M-FEM is more close to wafer printing results.

Lo, Wei Cyuan; Cheng, Yung Feng; Chen, Ming Jui; Haung, Peter; Chang, Stephen; Tsujimoto, Eiji

2010-03-01

260

Strength of Si Wafers with Microcracks: A Theoretical Model (Poster)  

SciTech Connect

A new analytical expression that takes into account the surface, edge, and bulk properties of a wafer has been proposed to describe the strength of the brittle materials. A new proposed fracture-mechanics numerical simulation successfully predicted the strength of the cast silicon wafers. It has been shown that the predicted wafer strength distribution agrees well with the available experimental results.

Rupnowski, P.; Sopori, B.

2008-05-01

261

Development of quasi half coax lines for wafer level packaging  

Microsoft Academic Search

A 50 ohm micromachined interconnect is designed, fabricated, and measured as a broadband interconnect that is compatible with the standard thickness of wafers. It is developed in two applications: a transition from a commercially available 1 mm connector launch assembly to wafer based systems and an interconnect within wafer level designs. S-parameter measured data is shown for coaxially launched structures

S. R. Banerjee; R. F. Drayton

2005-01-01

262

Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections  

Microsoft Academic Search

Packaging is an emerging technology for microsystem integration. The silicon-on-insulator (SOI) wafer has been extensively employed for micromachined devices for its reliable fabrication steps and robust structures. This research reports a packaging approach for silicon-on- insulator-micro-electro-mechanical system (SOI-MEMS) devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling

Chiung-Wen Lin; Hsueh-An Yang; Wei Chung Wang; Weileun Fang

2007-01-01

263

Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force  

Microsoft Academic Search

This paper reports about a novel wafer-level integration technique of discrete surface mount devices (SMDs). It enables wafer-level mounting of plural kinds of SMDs on a silicon (Si)-wafer using vibration and gravity force. Deep holes with 400-m depth are formed on the surface of a Si-wafer by deep reactive ion etching process after general integrated circuit process for positioning of

Minoru Sudou; Hidekuni Takao; Kazuaki Sawada; Makoto Ishida

2007-01-01

264

Optical Cluster Eye fabricated on wafer-level  

NASA Astrophysics Data System (ADS)

Wafer-level optics is considered as a cost-effective approach to miniaturized cameras, because fabrication and assembly are carried out for thousands of lenses in parallel. However, in most cases the micro-optical fabrication process is not mature enough to reach the required accuracy of the optical elements, which may have complex profiles and sags in the mm-scale. Contrary, the creation of microlens arrays is well controllable so that we propose a multi aperture system called ''Optical Cluster Eye'' which is based on conventional micro-optical fabrication techniques. The proposed multi aperture camera consists of many optical channels each transmitting a segment of the whole field of view. The design of the system provides the stitching of the partial images, so that a seamless image is formed and a commercially available image sensor can be used. The system can be fabricated on wafer-level with high yield due to small aperture diameters and low sags. The realized optics has a lateral size of 2.2 × 2.9 mm2, a total track length of 1.86 mm, and captures images at VGA video resolution.

Meyer, Julia; Brückner, Andreas; Leitel, Robert; Dannberg, Peter; Bräuer, Andreas; Tünnermann, Andreas

2011-08-01

265

Optical Cluster Eye fabricated on wafer-level.  

PubMed

Wafer-level optics is considered as a cost-effective approach to miniaturized cameras, because fabrication and assembly are carried out for thousands of lenses in parallel. However, in most cases the micro-optical fabrication process is not mature enough to reach the required accuracy of the optical elements, which may have complex profiles and sags in the mm-scale. Contrary, the creation of microlens arrays is well controllable so that we propose a multi aperture system called "Optical Cluster Eye" which is based on conventional micro-optical fabrication techniques. The proposed multi aperture camera consists of many optical channels each transmitting a segment of the whole field of view. The design of the system provides the stitching of the partial images, so that a seamless image is formed and a commercially available image sensor can be used. The system can be fabricated on wafer-level with high yield due to small aperture diameters and low sags. The realized optics has a lateral size of 2.2 × 2.9 mm2, a total track length of 1.86 mm, and captures images at VGA video resolution. PMID:21935117

Meyer, Julia; Brückner, Andreas; Leitel, Robert; Dannberg, Peter; Bräuer, Andreas; Tünnermann, Andreas

2011-08-29

266

Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology  

NASA Astrophysics Data System (ADS)

Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances. Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported. Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure mechanism. The kinetic and thermodynamic analysis of the annealing-induced interfacial transformation process has been performed based upon the temporal measurements of interface electrical conductivity and micromorphologies. Finally, the feasibility of using the combination of low-temperature grown amorphous alpha-(Ga, As) materials and wafer-bonding technology to fabricate GaSb semiconductor on GaAs substrates to potentially create GaSb-on-insulator structure has been demonstrated.

Shi, Fang Frank

267

Determining photoresist coat sensitivities of 300-mm wafers  

NASA Astrophysics Data System (ADS)

This paper presents preliminary data on 300 nm wafer coatings by comparing photoresist coats on 150 nm, 200 mm and 300 mm wafers. Conventional methods of applying photoresist have ben prove effective on wafers with diameters up to 200 nm. How well 150 mm and 200 mm coating processes apply to 300 mm substrates is the focus of this paper. Spin speed versus photoresists thickness curves will be reviewed for all three wafer sizes.Additionally, two major coating uniformity factors, photoresist and cool plate temperature, will be studied for 200 mm and 300 mm wafers.

Crowell, Robert M.

1998-06-01

268

TOPICAL REVIEW: Wafer level packaging of MEMS  

NASA Astrophysics Data System (ADS)

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass-Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review.

Esashi, Masayoshi

2008-07-01

269

A W-band wafer probe  

Microsoft Academic Search

A W-band (75-110 GHz) wafer probe was successfully designed and built. The probe uses a ridge-trough waveguide as a transition from a rectangular waveguide input to the coplanar waveguide (CPW) used on the probe board output. Typical insertion loss and return loss figures were 3.5 dB and better than 13 dB, respectively. Losses were minimized in the CPW probe board

Edward M. Godshalk

1993-01-01

270

Wafer probing at W-band  

Microsoft Academic Search

A W-band (75-110 GHz) wafer probe is presented. The probe uses ridge-trough waveguide to transition from a rectangular waveguide input to coplanar waveguide used on the probe board output. Research was conducted on radiation loss and moding in coplanar waveguide to minimize insertion loss and maintain a coplanar mode. The probe is shown to work successfully and data is presented

Edward M. Godshalk

1993-01-01

271

VLED for Si wafer-level packaging  

NASA Astrophysics Data System (ADS)

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-02-01

272

3D EM Characterization of Wafer Probes  

Microsoft Academic Search

The following paper describes a method to characterize wafer probes using a 3D EM simulator. Rather than following the traditional method of building a custom test fixture for different probe setups and measuring the S-parameters, this 3D EM characterization method yields multi-port S-parameters of a specific probe structure by utilizing simulations. For a standard characterization, the S-parameters can be a

Hanyi Ding; Randy Wolf; John Ferrario

2001-01-01

273

New calibration simplifies MMIC wafer probing  

Microsoft Academic Search

MMAVERIC (MMIC Metrology with Automatic Verification in Time), a novel technique for performing wafer-probe calibration, is described. MMAVERIC flow graphs describe systematic errors in terms of power flow; errors arise from imperfections in response tracking, directivity, source and load matches, and isolation. One-port and two-port calibrations are discussed. It is noted that MMAVERIC is fast and requires very little hardware

H. B. Sequeira; M. W. Trippe; R. Jakhete

1988-01-01

274

A 5 Gbps Wafer-Level Tester  

Microsoft Academic Search

This paper describes an economical approach to highspeed testing of high-density wafer-level packaged logic devices. The solution assumes that the devices to be tested have built-in self-test features, thereby reducing the complexity of functional testing required. This also reduces the need for expensive automated test equipment (ATE). A stand alone miniature tester is developed and connected to the top of

A. M. Majid; David C. Keezer; J. V. Karia

2005-01-01

275

Infrared spectroscopy of bonded silicon wafers  

Microsoft Academic Search

Infrared spectra of multiple frustrated total internal reflection and transmission for silicon wafers obtained by direct bonding\\u000a in a wide temperature range (200–1100C) are studied. Properties of the silicon oxide layer buried at the interface are investigated\\u000a in relation to the annealing temperature. It is shown that the thickness of the SiO2 layer increases from 4.5 to 6.0 nm as

A. G. Milekhin; C. Himcinschi; M. Friedrich; K. Hiller; M. Wiemer; T. Gessner; S. Schulze; D. R. T. Zahn

2006-01-01

276

Etching methodologies in ?111?-oriented silicon wafers  

Microsoft Academic Search

New methodologies in anisotropic wet-chemical etching of ?111?-oriented silicon, allowing useful process designs combined with smart mask-to-crystal-orientation-alignment are presented in this paper. The described methods yield smooth surfaces as well as high-quality plan-parallel beams and membranes. With a combination of pre-etching and wall passivation, structures can be etched at different depths in a wafer. Designs, using the ?111?-crystal orientation, supplemented

R. Edwin Oosterbroek; J. W. Berenschot; H. V. Jansen; A. J. Nijdam; G. Pandraud; A. van den Berg; M. C. Elwenspoek

2000-01-01

277

On the evolution of wafer level cameras  

NASA Astrophysics Data System (ADS)

The introduction of small cost effective cameras based on CMOS image sensor technology has played an important role in the revolution in mobile devices of the last 10 years. Wafer-based optics manufacturing leverages the same fabrication equipment used to produce CMOS sensors. The natural integration of these two technologies allows the mass production of very low cost surface mount cameras that can fit into ever thinner mobile devices. Nano Imprint Lithography (NIL) equipment has been adapted to make precision aspheres that can be stacked using wafer bonding techniques to produce multi-element lens assemblies. This, coupled with advances in mastering technology, allows arrays of lenses with prescriptions not previously possible. A primary motivation for these methods is that it allows the consolidation of the supply chain. Image sensor manufacturers envision creating optics by simply adding layers to their existing sensor fabrication lines. Results thus far have been promising. The current alternative techniques for creating VGA cameras are discussed as well as the prime cost drivers for lens to sensor integration. Higher resolution cameras face particularly difficult challenges, but can greatly simplify the critical tilt and focus steps needed to assemble cameras that produce quality images. Finally, we discuss the future of wafer-level cameras and explore several of the novel concepts made possible by the manufacturing advantages of photolithography.

Welch, H.

2011-02-01

278

Fabrication of cone-like microstructure using UV LIGA-like for light guide plate application  

Microsoft Academic Search

The microlens array is usually formed by thermal reflow of polymer disks and can be one microstructure of the light guide\\u000a plate (LGP). Here, we propose an ultraviolet (UV) backside exposure technology to fabricate the photoresist cone-like microstructure\\u000a on the PMMA substrate at room temperature and then use UV LIGA-like process to transfer the microstructure for the application\\u000a of 3.6 in.

C. K. ChungK; K. L. Sher; Y. J. Syu; C. C. Cheng

2010-01-01

279

Diamond-like nanocomposite coatings for LIGA-fabricated nickel alloy parts.  

SciTech Connect

A commercial plasma enhanced chemical vapor deposition (PECVD) technique with planetary substrate rotation was used to apply a thin (200-400 nm thick) conformal diamond-like carbon (DLC) coating (known as a diamond-like nanocomposite (DLN)) on LIGA fabricated Ni-Mn alloy parts. The PECVD technique is known to overcome the drawbacks associated with the line-of-sight nature of physical vapor deposition (PVD) and substrate heating inherent with traditional chemical vapor deposition (CVD). The purpose of the present study is to characterize the coverage, adhesion, and tribological (friction and wear) behavior of DLN coatings applied to planar and sidewall surfaces of small featured LIGA Ni-Mn fabricated parts, e.g. 280 {micro}m thick sidewalls. Friction and wear tests were performed in dry nitrogen, dry air, and air with 50% RH at Hertzian contact pressures ranging from 0.3 to 0.6 GPa. The friction coefficient of bare Ni-Mn alloy was determined to be 0.9. In contrast, low friction coefficients ({approx}0.02 in dry nitrogen and {approx}0.2 in 50% RH air) and minimal amount of wear were exhibited for the DLN coated LIGA Ni-Mn alloy parts and test coupons. This behavior was due to the ability of the coating to transfer to the rubbing counterface providing low interfacial shear at the sliding contact; resultantly, coating one surface was adequate for low friction and wear. In addition, a 30 nm thick titanium bond layer was determined to be necessary for good adhesion of DLN coating to Ni-Mn alloy substrates. Raman spectroscopy and cross-sectional SEM with energy dispersive x-ray analysis revealed that the DLN coatings deposited by the PECVD with planetary substrate rotation covered both the planar and sidewall surfaces of LIGA fabricated parts, as well as narrow holes of 300 {micro}m (0.012 inch) diameter.

Prasad, Somuri V.; Scharf, Thomas W.

2005-03-01

280

Radiation chemistry of poly(lactides) as new polymer resists for the LIGA process  

Microsoft Academic Search

Recently poly(lactides) have been discovered to be a promising new polymer family for applications in the LIGA (the German acronym for Lithography, Galvanoplating and Plastic moulding, German: Abforming) process, as they show a considerably enhanced sensitivity and reduced tensile stress corrosion with respect to the standard poly(methyl-methacrylate) (PMMA) resist. The irradiation chemistry was studied by Fourier-transform infrared and mass spectrometry.

O. Wollersheim; H. Zumaque; J. Hormes; J. Langen; P. Hoessel; L. Haussling; G. Hoffmann

1994-01-01

281

Rapid replication of polymeric and metallic high aspect ratio microstructures using PDMS and LIGA technology  

Microsoft Academic Search

This paper present a method of rapid replication of polymeric high aspect ratio microstructures (HARMs) and a method of rapid\\u000a reproduction of metallic micromold inserts for HARMs using polydimethylsiloxane (PDMS) casting and standard LIGA processes.\\u000a A high aspect ratio (HAR) metallic micromold insert, featuring a variety of test microstructures made of electroplated nickel\\u000a with 15:1 height-to-width ratio for 300 ?m

K. Kim; J.-B. Lee; H. Manohara; Y. Desta; M. Murphy; C. H. Ahn

2002-01-01

282

A Transdermal Drug Delivery System Based on LIGA Technology and Soft Lithography  

NASA Astrophysics Data System (ADS)

This report presents a transdermal drug delivery system based on LIGA fabricated microparts. It is a portable device combining a magnetically actuated micro gear pump with a microneedle array. The fluidic behaviour of the system is analyzed in order to predict its performance according to the dimension of the microparts and then compared to experimental data. The manufacturing process of both micropump and microneedle array are described.

Matteucci, Marco; Perennes, Frederic; Marmiroli, Benedetta; di Fabrizio, Enzo

2007-01-01

283

The study on the compound x-ray refractive lens using LIGA technique  

Microsoft Academic Search

A theoretical method of focusing X-rays by the compound X-ray refractive lens is presented in this paper. The authors report their resent theoretical results including the material selection and structure parameters for such a device. As an example, a compound X-ray refractive lens with PMMA material is designed. The detailed fabrication process of the PMMA compound lens by LIGA technology

Jingqiu Liang; Zichun Le; Liangqiang Peng; Weibiao Wang; Weihua Lan; Anjie Ming; Futing Yi; Jian Ye; Bisheng Quan; Jinsong Yao; Ming Xuan; Lijun Wang

2004-01-01

284

Microstructuring characteristics of a chemically amplified photoresist synthesized for ultra-thick UV-LIGA applications  

Microsoft Academic Search

The thick-film photoresists are essential to fabricate high-aspect-ratio microstructures by the UV-LIGA process. However, current thick-film photoresists have some weaknesses including a thickness of only up to 100 µm, a poor line-width resolution and difficulty in being stripped. Consequently, a new type of thick-film photoresist is required. This work presents a novel positive-tone MMA\\/TBMA photoresist, formed by combining copolymerization and

Chii-Rong Yang; Gen-Wen Hsieh; Yu-Sheng Hsieh; Yu-Der Lee

2004-01-01

285

Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size  

NASA Astrophysics Data System (ADS)

For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.

Kim, Hee Yeoun; Yang, Chungmo; Park, Jae Hong; Jung, Ho; Kim, Taehyun; Kim, Kyung Tae; Lim, Sung Kyu; Lee, Sang Woo; Mitchell, Jay; Hwang, Wook Joong; Lee, Kwyro

2013-06-01

286

A LigA Three-Domain Region Protects Hamsters from Lethal Infection by Leptospira interrogans  

PubMed Central

The leptospiral LigA protein consists of 13 bacterial immunoglobulin-like (Big) domains and is the only purified recombinant subunit vaccine that has been demonstrated to protect against lethal challenge by a clinical isolate of Leptospira interrogans in the hamster model of leptospirosis. We determined the minimum number and location of LigA domains required for immunoprotection. Immunization with domains 11 and 12 was found to be required but insufficient for protection. Inclusion of a third domain, either 10 or 13, was required for 100% survival after intraperitoneal challenge with Leptospira interrogans serovar Copenhageni strain Fiocruz L1-130. As in previous studies, survivors had renal colonization; here, we quantitated the leptospiral burden by qPCR to be 1.2×103 to 8×105 copies of leptospiral DNA per microgram of kidney DNA. Although renal histopathology in survivors revealed tubulointerstitial changes indicating an inflammatory response to the infection, blood chemistry analysis indicated that renal function was normal. These studies define the Big domains of LigA that account for its vaccine efficacy and highlight the need for additional strategies to achieve sterilizing immunity to protect the mammalian host from leptospiral infection and its consequences.

Coutinho, Mariana L.; Choy, Henry A.; Kelley, Melissa M.; Matsunaga, James; Babbitt, Jane T.; Lewis, Michael S.; Aleixo, Jose Antonio G.; Haake, David A.

2011-01-01

287

Interferometric total thickness variation measurement of glass wafer  

NASA Astrophysics Data System (ADS)

Total thickness variation (TTV) is one of the important specifications of glass wafer. Glass wafers are thin and transparent parallel plates. In order to measure a flat surface by interferometer, at least one reference flat of same size is required. And the interference between two reflected wavefronts by the front and rear surfaces of the glass wafer also exists. Therefore interferometric measurements of thin glass wafers are not easy. So TTV is mainly measured not by interferometer, but by thickness gauge devices. But these devices measure only the TTV of several positions of glass wafer and don't measure the whole area. To measure the whole area or sufficient points, it requires more time. We developed a relatively simple and inexpensive interferometric TTV measurement method using Haidinger interferometer. This method can be applied to large glass wafers without large reference flat.

Song, Jae-Bong; Lee, Hoi-Youn; Lee, Yun-Woo; Lee, In-Won

2007-11-01

288

Waveguide probe tackles V-band on-wafer tests  

NASA Astrophysics Data System (ADS)

As millimeter-wave MMIC processes mature, requirements for manufacturing process control and product performance testing drive the need for V-band on-wafer testing. Semiconductor wafer probes for RF measurements are outlined, as well as commercial wafer probes based on the 1.85-mm coaxial connector supporting on-wafer device measurements up to 65 GHz. A waveguide architecture requiring the development of a waveguide-to-coplanar -waveguide (CPW) transmission to send test signals from a wafer of interest to an automatic vector network analyzer is suggested. Waveguide-to-CPW transition characteristics are assessed, and a commercial V-band wafer probe with ground-signal-ground contact configuration for low common-lead inductance is described. The probe's specified performance includes maximum insertion loss of 5 dB from 50 to 75 GHz.

Jones, Keith; Godshalk, Ed

1990-10-01

289

Drop test reliability of wafer level chip scale packages  

Microsoft Academic Search

The reliability of the two different types of WL-CSP components being reflow-soldered with a near eutectic Sn3.8Ag0.7Cu and eutectic SnPb solder pastes on Ni(P)\\/Au-and OSP-coated multilayer printed wiring boards have been investigated by employing the standard drop test, statistical failure analyses, fractography and microstructural characterization methods. A significant difference in the reliability performance of the components was observed: the components

Mikko Alajoki; Luu Nguyen; Jorma Kivilahti

2005-01-01

290

Low frequency noise spectroscopy of SOI wafers  

NASA Astrophysics Data System (ADS)

Low Frequency Noise (LFN) is important in analog and digital circuits. In analog circuits it affects the performance of low-noise amplifiers and the phase noise of voltage-controlled oscillators. In digital circuits it becomes more important as the supply voltage is reduced and it degrades substrate noise coupling. Low-frequency noise is due to interactions of the channel carriers with oxide/semiconductor interface traps and oxide charges. It is very dependent on the quality of the oxide/semiconductor interface and noise measurements can give important information about such interfaces and defects. Silicon-on-insulator Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have two oxide/semiconductor interfaces: the top interface between the gate oxide and the active silicon (Si) layer and the bottom interface between the buried oxide and the active Si layer. The bottom interface is generally worse than the top interface. Most LFN measurements are made after MOSFET fabrication, but it is desirable to characterize such materials without fabricating devices. In this thesis we discuss Silicon-On-Insulator (SOI) low-frequency noise and interface trap density measurements using a Ground-Signal-Ground (GSG) and circular pseudo MOSFET structure with minimum fabrication. The pseudo MOSFET (Psi-MOSFET) is a simple, yet powerful, device to characterize various aspects of SOI wafers and is routinely used for incoming wafer inspection to determine material parameters. This device comes in point contact and mercury probe (HgFET) configurations. The point-contact pseudo MOSFET simply requires two probes on an SOI wafer. However, the contact geometry is poorly defined leading to questions in the interpretation of the ID-VG data. The HgFET has the advantage of well-defined source/drain contacts, but it has an Hg/Si interface and all the vagaries that accompany metal/Si contacts, where barrier heights change with time due to surface state changes. For reproducible measurements we use deposited metal electrodes on the SOI wafer forming Schottky barrier source/drain contacts, and using the substrate as the gate. Two configurations of electrodes are proposed: the GSG arrangement and the circular pattern. Both designs allow performing of low frequency noise and frequency response measurements. This is the first time the pseudo MOSFET has been used for such measurements.

Kushner, Vadim

291

Assembly and Hermetic Encapsulation of Wafer Level Secondary Batteries  

Microsoft Academic Search

A new technology was developed for the construction and hermetic encapsulation of chip-size secondary lithium-ion batteries on a wafer-level plane. To reduce the size of the package and improve the handling and assembly of miniature batteries, we established a wafer-level process that combines foil processing of Li batteries and wafer technologies for battery contacts and encapsulation. Parylene and thin-film metal

K. Marquardt; R. Hahn; T. Luger; H. Reichl

2006-01-01

292

Wafer Temperature Measurement and Control During Laser Spike Annealing  

Microsoft Academic Search

Sub-melt millisecond annealing technologies have been widely accepted for current and future IC fabrication. Real-time temperature control, both within wafer and from wafer-to-wafer, is one of the key challenges that must be addressed for the successful introduction of any millisecond annealing technology into a production environment. In this paper, we show results from a novel pyrometry approach that measures the

Shaoyin Chen; J. Hebb; A. Jain; S. Shetty; Yun Wang

2007-01-01

293

Cerebral edema associated with Gliadel wafers: Two case studies  

PubMed Central

While the introduction of carmustine wafers (Gliadel wafers) into the tumor resection cavity has been shown to be a beneficial therapy for malignant glioma, it is recognized that clinically significant cerebral edema is a potential adverse effect. Following are two clinical case reports demonstrating profound cerebral edema associated with implantation of Gliadel wafers. As a result, one of these individuals had premature death. A brief literature review is provided to assist in explaining the mechanisms by which clinically significant cerebral edema may develop.

Weber, Emil L.; Goebel, Eric A.

2005-01-01

294

Wafer-to-Wafer Bonding Techniques: From MEMS Packaging to IC Integration Applications  

Microsoft Academic Search

Device stacking and packaging on wafer-level plays a key role for the continuous miniaturization, expansion of functionality and reduction of production costs of MEMS and MCMs. The field of applications for integrated devices and MEMS is huge and the packaging requirements for the different systems are versatile. Driven by the automotive industry, extensive research and development in the field of

R. Pelzer; H. Kirchberger; P. Kettner

2005-01-01

295

Micro-miniature gas chromatograph column disposed in silicon wafers  

DOEpatents

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Yu, Conrad M. (Antioch, CA)

2000-01-01

296

Micro-miniature gas chromatograph column disposed in silicon wafers  

SciTech Connect

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Yu, C.M.

2000-05-30

297

Resolution and sensitivity of wafer-level multi-aperture cameras  

NASA Astrophysics Data System (ADS)

The scaling limits of multi-aperture systems have been widely discussed from an information-theoretical standpoint. While these arguments are valid as an upper limit, the real-world performance of systems for mobile devices remains restricted by optical aberrations. We argue that aberrations can be more easily controlled with certain architectures of multi-aperture systems, especially those manufactured on wafer scale (wafer-level optics, WLO). We complement our analysis with measurements of one single- and one multi-aperture WLO camera. We examine both sharpness and sensitivity, giving measurements of modulation transfer function and temporal noise, and showing that multi-aperture systems can indeed reduce size without compromising performance.

Oberdörster, Alexander; Lensch, Hendrik P. A.

2013-01-01

298

LIGA-fabricated two-dimensional quadrupole array and scroll pump for miniature gas chromatograph/mass spectrometer  

NASA Astrophysics Data System (ADS)

A 3X3 array of hyperboloid quadrupole mass filters with a 3 mm pole length was fabricated using the LIGA (LIthographic Galvanoformung and Abformung) process. Electrical connectivity and spatial orientation are established by bonding the pole array to a low temperature co-fired ceramic (LTCC) substrate. A miniature scroll pump for vacuum pumping with a scroll height of 3 mm was also fabricated using the LIGA process. New LIGA fabrication steps (e.g. expose and developed freestanding PMMA, compression bonding of electroplating base and PMMA, low-stress electroplated films) have been developed to fabricate ultra thick PMMA molds with high aspect ratios (70:1) and high precision. Computational analysis was performed to estimate the miniature scroll pump performance characteristics.

Wiberg, Dean V.; Myung, Nosang V.; Eyre, Beverley; Shcheglov, Kirill; Orient, Otto J.; Moore, Eric; Munz, Philip

2003-07-01

299

Mask qualification strategies in a wafer fab  

NASA Astrophysics Data System (ADS)

Having consistent high quality photo masks is one of the key factors in lithography in the wafer fab. Combined with stable exposure- and resist processes, it ensures yield increases in production and fast learning cycles for technology development and design evaluation. Preventive controlling of incoming masks and quality monitoring while using the mask in production is essential for the fab to avoid yield loss or technical problems caused by mask issues, which eventually result in delivery problems to the customer. In this paper an overview of the procedures used for mask qualification and production release, for both logic and DRAM, at Infineon Dresden is presented. Incoming qualification procedures, such as specification checks, incoming inspection, and inline litho process window evaluation, are described here. Pinching and electrical tests, including compatibility tests for mask copies for high volume products on optimized litho processes, are also explained. To avoid mask degradation over lifetime, re-inspection checks are done for re-qualification while using the mask in production. The necessity of mask incoming inspection and re-qualification, due to the repeater printing from either the processing defects of the original mask or degrading defects of being used in the fab (i.e. haze, ESD, and moving particles, etc.), is demonstrated. The need and impact of tight mask specifications, such as CD uniformity signatures and corresponding electrical results, are shown with examples of mask-wafer CD correlation.

Jaehnert, Carmen; Kunowski, Angela

2007-05-01

300

Mechanisms for room temperature direct wafer bonding  

NASA Astrophysics Data System (ADS)

Reducing the temperature needed for high strength bonding which was and is driven by the need to reduce effects of coefficient of thermal expansion mismatch, reduce thermal budgets, and increase throughput has led to the development of plasma treatment procedures capable of bonding Si wafers below 300 °C with a bond strength equivalent to Si bulk. Despite being widely used, the physical and chemical mechanisms enabling low temperature wafer bonding have remained poorly understood. We developed an understanding of the beneficial surface modifications by plasma and a model based on short range low temperature diffusion through bonding experiments combined with results from spectroscopic ellipsometry, depth resolving Auger electron spectroscopy, and transmission electron microscopy measurements. We also present experimental results showing that even at room temperature reasonable bond strength can be achieved. We conclude that the gap closing mechanism is therefore a process which balances the lowering of the total energy by minimizing the sum of the free surface energy (maximizing the contact area between the surfaces) and strain energy in the oxide at the bond interface.

Plach, T.; Hingerl, K.; Tollabimazraehno, S.; Hesser, G.; Dragoi, V.; Wimplinger, M.

2013-03-01

301

Flexural testing of board mounted wafer level packages for handheld devices  

Microsoft Academic Search

With the growing proliferation of wafer-level-chip-scale-packages (WLCSP), the target applications are increasingly focused on hand-held devices and consumer applications like cellular phones, pagers, PDA's etc. Packages in this family, like National Semiconductor's micro SMD package, have proven reliability in thermal cycling, humidity and bias testing, and are generally rated at moisture sensitivity lever 1 (MSL-1). As applications continue to require

V. Patwardhan; D. Chin; S. Wong; E. Rey; N. Kelkar; L. Nguyen

2005-01-01

302

GaAs wafer for passive mode locking and compression of energetic Q-switched pulses  

Microsoft Academic Search

We show experimentally that by use of an appropriately coated GaAs wafer as output coupler, either self-started passive mode locking or pulse width compression of Q-switched pulses of diode-pumped solid-state (DPSS) lasers can be achieved. Mode-locked pulses with duration in the picosecond time scale have been routinely generated in various Nd-doped DPSS lasers. Pulse width compression of the Q-switched pulses

D. Y. Tang; J. Kong; S. P. Ng

2006-01-01

303

Monolithically integrated thin film III-V\\/Si solar panel on wafer for active power management  

Microsoft Academic Search

We have demonstrated a monolithically integrated solar panel on Si that allows scaling of cell output voltage on the wafer level. Our design also incorporates integrated bypass diodes and the possible incorporation of CMOS for active power management at the materials integration level. In addition, we have demonstrated the first GaAsP\\/SiGe dual junction solar cell on Si that provides the

Arthur J. Pitera; John Hennessy; Andrew C. Malonis; E. A Fitzgerald; S. A. Ringel

2011-01-01

304

Wafer level hermetic package and device testing of a SOI-MEMS switch for biomedical applications  

Microsoft Academic Search

We have designed a wafer level chip scale package for a bi-stable SOI-MEMS dc switch using a silicon-glass hermetic seal with through the lid feedthroughs. Bonded at 365 °C, 230 V and 250 kg, they pass the fine\\/gross leak test after thermal cycling and mechanical shock\\/vibration according to MIL-STD-833, fulfilling the requirements for biomedical applications. The measured shear strength is

Rogier A. M. Receveur; Michael Zickar; Cornel Marxer; Vincent Larik; Nicolaas F. de Rooij

2006-01-01

305

Computational Assessment of the Effects of Temperature on Wafer-Level Component Boards in Drop Tests  

Microsoft Academic Search

The drop reliability of wafer-level chip-scale package (WL-CSP) component boards used in portable devices was studied by employing mechanical shock loads (JESD22-B111 standard) at different temperatures. The drop tests were carried out at room temperature (23 degC), 75 degC, 100 degC, and 125 degC. The elevated temperatures were achieved by integrated heater elements in the components. The number of drops-to-failure

Jue Li; Toni T. Mattila; Jorma K. Kivilahti

2009-01-01

306

A micro-undulator fabricated by LIGA processes  

SciTech Connect

An undulator of period 1 mm has been designed as part of a series of studies toward table-top synchrotron radiation sources. The undulator consists of a silver conductor embedded in poles and substrate of nickel-iron. Computations predict a field pattern of appropriate strength and quality if the current can be prevented from shunting from the silver across the nickel-iron poles, either through insulation or through slotted poles. A ten-scale model has been fabricated and measured; a full-scale model has also been constructed by conventional machining techniques, but has not yet been measured.

Turner, L.R.; Nassiri, A.; Mills, F.E. [and others

1995-08-01

307

Fabrication of high-aspect-ratio electrode array by combining UV-LIGA with micro electro-discharge machining  

Microsoft Academic Search

In this paper, the combination of UV-LIGA with the Micro electro-discharge machining (Micro-EDM) process was investigated\\u000a to fabricate high-aspect-ratio electrode array, and an easy and rapid process for fabricating ultra-thick SU-8 microstructures\\u000a up to millimeter depth was described. First, the modified UV-LIGA process was used to fabricate the copper hole array, and\\u000a then the hole array electrode was employed as

Yang-Yang Hu; D. Zhu; N. S. Qu; Y. B. Zeng; P. M. Ming

2009-01-01

308

Microstructuring characteristics of a chemically amplified photoresist synthesized for ultra-thick UV-LIGA applications  

NASA Astrophysics Data System (ADS)

The thick-film photoresists are essential to fabricate high-aspect-ratio microstructures by the UV-LIGA process. However, current thick-film photoresists have some weaknesses including a thickness of only up to 100 µm, a poor line-width resolution and difficulty in being stripped. Consequently, a new type of thick-film photoresist is required. This work presents a novel positive-tone MMA/TBMA photoresist, formed by combining copolymerization and chemically amplification (CA) for use in the ultra-thick UV-LIGA process. An MMA/TBMA photoresist film with a thickness of 500 µm is easily achieved. For MMA/TBMA photoresist layers with thicknesses from 100 µm to 500 µm, an exposure dose from 80 to 100 mJ cm-2 per micron is required to remove all of the exposed photoresist, revealing that the selectivity between radiated and non-radiated zones during a long development process is sufficiently high; the sidewall verticality and aspect ratio of the microstructure are excellent; stress-induced cracks are not observed in the non-radiated zones after development. MMA/TBMA photoresist is demonstrated to fabricate open microstructures with aspect ratios of at least 10 and close microstructures with aspect ratios of not more than 10, such values of aspect ratio are still sufficient for most ultra-thick mold applications. Moreover, MMA/TBMA photoresist can undergo erosion by acidic electrolyte and easily be stripped using usual organic solvents. These findings demonstrate that MMA/TBMA photoresist has the potential to replace SU-8 resist in the ultra-thick UV-LIGA process.

Yang, Chii-Rong; Hsieh, Gen-Wen; Hsieh, Yu-Sheng; Lee, Yu-Der

2004-08-01

309

UV-LIGA microfabrication of 220 GHz sheet beam amplifier gratings with SU-8 photoresists  

NASA Astrophysics Data System (ADS)

Microfabrication techniques have been developed using ultraviolet photolithography (UV-LIGA) with SU-8 photoresists to create advanced sheet beam amplifier circuits for the next generation of vacuum electron traveling wave amplifiers in the 210-220 GHz (G-band) frequency regime. We describe methods that have led to successfully fabricated millimeter wave circuits, including applying ultra-thick SU-8 photoresist layers on copper, copper electroforming solutions, and the challenging removal of the SU-8 photoresists. A table of experimental liquid SU-8 removal chemistries and results is also presented.

Joye, Colin D.; Calame, Jeffrey P.; Garven, Morag; Levush, Baruch

2010-12-01

310

Brain content of glycosphingolipids after oral administration of monosialogangliosides GM1 and LIGA20 to rats  

Microsoft Academic Search

Natural (GM1) and semisynthetic [113-Neu-5-AcGgOse4-2-D-erythro-1,3-dihydroxy-2-dichloroacetylamide-4-trans-octadecene (LIGA20)] glycosphingolipids, given parenterally, protect neurones against glutamate-induced death without producing\\u000a the side effects typical of glutamate receptor antagonists. Chronic glutamate-related neurotoxicity (e.g., in recurring strokes\\u000a in elderly hypertensive patients, and in Parkinson disease) could be prevented also by glycosphingolipids treatment, but this\\u000a therapeutic intervention will require a protracted administration of orally active glycosphingolipids. Here

A. Polo; G. Kirschner; A. Guidotti; E. Costa

1994-01-01

311

The 300 mm silicon wafer — a cost and technology challenge  

Microsoft Academic Search

The conversion to 300 mm wafers is strictly cost driven. Cost, capability and timing are still the major challenges during this shaky transition phase. Looking back to 1995, industry consortia decided that the next wafer size would be 300 mm and all major Si manufacturers started to invest in costly 300 mm pilot lines. Even during the recent recession, they

Peter O. Hahn

2001-01-01

312

Metrology of 300 mm silicon wafers: Challenges and results  

Microsoft Academic Search

Challenging requirements have to be met by metrology tools for 300 mm wafers and technology generations <=0.25 mum in near future. Measurement equipment for some specific wafer parameters presently operates already at its limits and will not be able to meet the future requirements. New tools therefore were or are currently developed. The future requirements are outlined and examples for

P. Wagner

1998-01-01

313

Surface-Defect Detection System for Patterned Wafers.  

National Technical Information Service (NTIS)

A high-speed, highly sensitive surface-defect detection system for semiconductor patterned wafers suitable for use in factory environments has been developed. The system detects submicron surface defects and inspects a six-inch wafer in 30min. The system ...

H. Tanaka T. Oshige Y. Miyazaki H. Ichimura T. Tomoda

1990-01-01

314

Wafer back side inspection applications for yield protection and enhancement  

Microsoft Academic Search

Semiconductor manufacturers employ various techniques and tools to detect and identify the physical defects that limit product and process yields. Most of these techniques focus on measuring the front side of the semiconductor wafer where the devices are manufactured. Attention to defectivity on the wafer backside has been minimal. Two possible reasons are the lack of suitable equipment and methods,

Lesley A. Cheema; Leonard J. Olmer; Oliver D. Patterson; S. S. Lopez; M. B. Burns

2002-01-01

315

500 GHz GaAs MMIC sampling wafer probe  

Microsoft Academic Search

A 500 GHz bandwidth GaAs MMIC sampling wafer probe is reported which incorporates a mechanical flexure and a micromachined GaAs IC for time domain on-wafer measurements. The GaAs IC incorporates a novel high speed pulse sharpener and a two-diode sampling bridge with a micromachined GaAs tip.

M. S. Shakouri; A. Black; B. A. Auld; D. M. Bloom

1993-01-01

316

100 GHz wafer probes based on photoconductive sampling  

Microsoft Academic Search

The authors fabricated optoelectronic wafer probes with both free-space and fiber-optic input, and they adapted microwave error correction techniques to allow calibrated measurements with the new probes. Photoconductive switches on the probe tip define stimulus pulses and sampling intervals, and signals are transferred to and from the wafer under test by coplanar waveguide transmission lines and plated contact bumps. Vector

M. D. Feuer; S. C. Shunk; P. R. Smith; M. C. Nuss; N. H. Law

1993-01-01

317

Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint  

SciTech Connect

This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

Rupnowski, P.; Sopori, B.

2008-05-01

318

Alternative facility layouts for semiconductor wafer fabrication facilities  

Microsoft Academic Search

Semiconductor wafer fabrication facilities are widely acknowledged to be among the most complicated industrial systems from a production planning and control point of view. The design of most wafer fabrication facilities has followed the process layout, where similar machines are located together. This feeds to complex, reentrant product flows through the facility. In this paper, we examine the effects on

Christopher D. Geiger; Rieko Hase; Christos G. Takoudis; Reha Uzsoy

1997-01-01

319

P/N Inp Solar Cells on Ge Wafers.  

National Technical Information Service (NTIS)

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick ...

S. Wojtczuk S. Vernon E. A. Burke

1994-01-01

320

Development of wafer bonded vertical cavity surface emitting lasers  

Microsoft Academic Search

This thesis describes the development of wafer bonded vertical cavity surface emitting lasers. By employing a reactive low temperature bonding technique, we have successfully demonstrated oxide-defined 850 nm vertical- cavity surface-emitting lasers (VCSELs) on silicon substrates. In this dissertation the design, fabrication, characterization, and applications of wafer bonded vertical cavity surface emitting lasers have been studied. The reactive low temperature

Yanyan Xiong

2001-01-01

321

Height Inspection of Wafer Bumps Without Explicit 3-D Reconstruction  

Microsoft Academic Search

Die bonding in the semiconductor industry requires placement of solder bumps not on PCBs but on wafers. Such wafer bumps, which are much miniaturized from their counterparts on printed circuit boards (PCBs), require their heights meet rigid specifications. Yet the small size, the lack of texture, and the mirror-like nature of the bump surface make the inspection task a challenge.

Mei Dong; Ronald Chung; Edmund Y. Lam; Kenneth S. M. Fung

2010-01-01

322

A Model for the Silicon Wafer Bonding Process  

Microsoft Academic Search

The bonding speed (or contact wave velocity) of silicon and fused quartz wafers has been measured as a function of temperature. The results show that the bonding process stops to operate at temperatures above 90°C and 320°C for fused quartz and bare silicon wafers, respectively. By comparing our results to infrared spectra obtained from silica gel we develop a tentative

R. Stengl; T. Tan; U. Gösele

1989-01-01

323

Design of sealed cavity microstructures formed by silicon wafer bonding  

Microsoft Academic Search

Three fabrication issues related to the design and fabrication of micromechanical devices using sealed cavities within bonded silicon wafers are discussed. The first concerns the resultant residual gas pressure within a sealed cavity between two bonded wafers after bonding and a high-temperature anneal. The second concerns the prediction of plastic deformation in capping layers of single-crystal silicon over sealed cavities.

Michael A. Huff; Alex D. Nikolich; Martin A. Schmidt

1993-01-01

324

Light scatter from defects on chemically-mechanically polished wafers  

Microsoft Academic Search

Detection and reduction of defects on chemically-mechanically polished (CMP) wafers are important concerns in semiconductor manufacturing. The physical and light scattering characteristics of typical CMP wafer surface defects including roughness, dishing, particles, and scratches are investigated in this dissertation. A new scatterometer is developed for the light scattering study. The system measured \\

Ping Ding

2000-01-01

325

Interferometric metrology of wafer nanotopography for advanced CMOS process integration  

NASA Astrophysics Data System (ADS)

According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

Valley, John F.; Koliopoulos, Chris L.; Tang, Shouhong

2001-12-01

326

Reduction of Thermal Conductivity in Wafer-Bonded Silicon  

SciTech Connect

Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

2006-11-27

327

MAPPER alignment sensor evaluation on process wafers  

NASA Astrophysics Data System (ADS)

MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing. In order to reduce costs and to minimize the footprint of this tool a new alignment sensor has been developed; based on technologies used for DVD optical heads. A wafer with an alignment mark is scanned with the sensor, resulting in an intensity pattern versus position. From this pattern the mark position can be calculated. Evaluations have been made over the performance of this type of sensor using different mark designs at several lithography process steps for FEOL and BEOL manufacturing. It has been shown that sub-nanometer reproducibility (3? std) of alignment mark readings can be achieved while being robust against various process steps.

Vergeer, N.; Lattard, L.; de Boer, G.; Couweleers, F.; Dave, D.; Pradelles, J.; Bustos, J.

2013-03-01

328

High density and through wafer copper interconnections and solder bumps for MEMS wafer-level packaging  

Microsoft Academic Search

This paper proposes an innovative process combining the electroforming of high-density and through-wafer copper interconnections and solder bumps for advanced MEMS packaging. Vias with the diameter of 30 to 100 ?m were etched through on a 4-inch and 550 ?m-thick silicon substrate by ICP-DRIE process for an aspect ratio up to 18.3. MRTV1 silicon rubber layer was employed for substrates

C.-J. Lin; M.-T. Lin; S.-P. Wu; F.-G. Tseng

2004-01-01

329

Bubble-Free Silicon Wafer Bonding in a Non-Cleanroom Environment  

Microsoft Academic Search

Bubble-free bonding of 4-inch silicon wafers on either silicon or quartz wafers is achieved outside a cleanroom. Two wafers are stacked horizontally in a rack with the two mirror-polished surfaces facing each other. In order to avoid wafer contact during hydrophilization, cleaning, and drying, the wafers are separated in the rack by teflon spacers introduced at the wafer edges. After

R. Stengl; K.-Y. Ahn; U. Gösele

1988-01-01

330

An all-glass chip-scale MEMS package with variable cavity pressure  

Microsoft Academic Search

A dielectric, chip-scale MEMS packaging method is discussed. The packaging method uses wafer-to-wafer bonding of micromachined glass wafers with a reflowed, glass, sealing ring. The glass wafers are micromachined and have metal and silicon structures patterned on them with metal and fluidic feedthroughs. A variety of getters and sealing designs are disclosed to vary the pressure of the microcavity by

Douglas Sparks; Jacob Trevino; Sonbol Massoud-Ansari; Nader Najafi

2006-01-01

331

Separation between Surface and Volume Decay Times of Photoconductivity in p-Type Silicon Wafers  

NASA Astrophysics Data System (ADS)

Excess photocarriers excited in silicon wafers are annihilated both in surface and volume regions independently of each other. When a photoconductive decay curve obtained with the microwave-detected photoconductive decay method is concave in semi-logarithmic scale, those two decay times in the different regions can be separately derived from the experimental data on assuming two independent exponential functions for the annihilation of excess carriers. The separation procedure can be completed using a commercially available computer code. The surface decay times vary from more than 95 to 13 ?s when the p-type silicon wafer rinsed with a hydrofluoric acid solution is kept exposed to the room air, while the volume decay times of around 1.7 ?s thus obtained are almost constant and quite reasonable in comparison with the theoretically expected one.

Munakata, Chusuke; Suzuki, Takumi

2006-09-01

332

7Li Spin-Lattice Relaxation at Low Temperatures in a Superionic Conductor ?-LiGa  

NASA Astrophysics Data System (ADS)

In order to investigate the Li+ ionic diffusion and the electronic states in a mixed conductor ?-LiGa with high Li+ ionic diffusibility and electron/hole conductivity, 7Li NMR linewidth and spin-lattice relaxation measurements have been performed in 44.0, 47.0, and 50.0 at. % Li ?-LiGa samples at 10.03 MHz in the temperature range between 10 and 320 K. The onset temperature TMN=70 K of the motional narrowing in 50.0 at. % sample has been determined from the temperature dependence of the linewidth. The Li+ ionic diffusion is found to contribute to the spin-lattice relaxation rate 1/T1 down to ˜0.5 TMN even below TMN where the motional narrowing does not occur. The high diffusibility of Li+ ions has been proved from a microscopic point of view. At low temperatures, the relations 1/T1T=3.5× 10-4, 3.8× 10-4, and 5.1× 10-4 s-1 K-1 are observed in 44.0, 47.0, and 50.0 at. % Li samples, respectively. The density of states of conduction electrons at the Fermi level in these compounds becomes higher with increasing Li content, which is consistent with the predictions by band calculations.

Endou, Shigeki; Ohno, Takashi; Kishimoto, Yutaka; Nishioka, Daisuke; Michihiro, Yoshitaka; Kawasaki, Yu; Ideta, Yukiichi; Kuriyama, Kazuo; Hamanaka, Hiromi; Yahagi, Masahito

2009-10-01

333

Mechanical and metallographic characterization of LIGA fabricated nickel and 80%Ni-20%Fe Permalloy  

SciTech Connect

A table top servohydraulic load frame equipped with a laser displacement measurement system was constructed for the mechanical characterization of LIGA fabricated electroforms. A drop in tensile specimen geometry which includes a pattern to identify gauge length via laser scanning has proven to provide a convenient means to monitor and characterize mechanical property variations arising during processing. In addition to tensile properties, hardness and metallurgical data were obtained for nickel deposit specimens of current density varying between 20 and 80 mA/cm{sup 2} from a sulfamate based bath. Data from 80/20 nickel-iron deposits is also presented for comparison. As expected, substantial mechanical property differences from bulk metal properties are observed as well as a dependence of material strength on current density which is supported by grain size variation. While elastic modulus values of the nickel electrodeposit are near 160 GPa, yield stress values vary by over 60%. A strong orientation in the metal electrodeposits as well as variations in nucleating and growth morphology present a concern for anisotropic and geometry dependent mechanical properties within and between different LIGA components.

Christenson, T.R.; Buchheit, T.E.; Schmale, D.T. [Sandia National Labs., Albuquerque, NM (United States); Bourcier, R.J. [Corning Inc., NY (United States). Photonic Technologies Div.

1998-04-13

334

Comparison of lateral thermal damage of the human peritoneum using monopolar diathermy, Harmonic scalpel and LigaSure  

PubMed Central

Background New hemostatic technologies are often employed in open and laparoscopic surgery to reduce duration of surgery and complications. Monopolar diathermy, Harmonic scalpel and LigaSure are routinely used in open and laparoscopic surgery for tissue cutting and hemostasis. We compared lateral thermal damage following in vivo application of 3 commonly used instruments. Methods We used monopolar diathermy, Harmonic scalpel and LigaSure to coagulate and divide the peritoneum of patients who underwent median laparotomy. After anesthesia, median supraumbilical laparotomy was performed, and the peritoneum of each patient was coagulated using different devices. Using light microscopy and morphometric imaging analysis, the width of tissue lateral thermal damage was measured from the point of the peritoneal incision. Results We included 100 patients in our study. After a peritoneal incision, the mean lateral thermal damage of monopolar diathermy, Harmonic scalpel (output power 3), Harmonic scalpel (output power 5) and LigaSure were 215.79 ?m, 90.42 ?m, 127.48 ?m and 144.18 ?m, respectively. Conclusion The degree of lateral thermal spread varied by instrument type, power setting and application time. LigaSure and Harmonic scalpel were the safest and most efficient methods of tissue coagulation. Monopolar diathermy resulted in the greatest degree of thermal damage in tissues.

Druzijanic, Nikica; Pogorelic, Zenon; Perko, Zdravko; Mrklic, Ivana; Tomic, Snjezana

2012-01-01

335

X-ray transmission lenses by deep x-ray lithography and LIGA technique: first results and fundamental limits  

NASA Astrophysics Data System (ADS)

Today's dimensionality of microtechnology enables the fabrication of precise objects, like diffraction limited x- ray transmission optics. Based on deep x-ray/LIGA technology, first results are presented concerning the fabrication and modelling of parabolic and massive-serial focalizing x-ray transmission lenses in PMMA, as opposed to standard grazing incidence reflection optics. The theoretical performance limitations of such optical systems are derived and stem from fundamental physical properties like the anomalous dispersion properties of the used materials. Parabolic x-ray transmission lenses are limited to very small numerical apertures, but behave optically like any ideal transmission lens would do. The advantages of deep x-ray LIGA technology are its favorable surface roughness and inherent precision. Unlike silicon micromachining, LIGA technique profits from a larger choice of possible materials. The importance of low-Z compounds like Lithium or Be/B is pointed out, together with necessary new techniques in the framework of LIGA, like electroplating from organic solutions.

Kupka, Roland K.; Bouamrane, Faycal; Roulliay, Marc; Megtert, Stephan

1999-03-01

336

Extraction and Analysis of Noise Parameters of On Wafer HEMTs up to 26.5 GHz  

NASA Astrophysics Data System (ADS)

This paper presents a procedure for extracting the four noise parameters of on wafer scaled HEMTs based on AlGaAs/GaAs heterostructure. This procedure relies on 50-? noise figure measurements up to 26.5 GHz by determining the equivalent temperatures associated to the intrinsic resistances of the small signal equivalent circuit. The non-quasi-static effect associated to the gate-drain resistance Rgd is accounted for by the noise model. A good agreement between measured and simulated noise figure is obtained and scaling of the noise parameters is reported.

Caddemi, Alina; Crupi, Giovanni; Macchiarella, Alessio

2009-04-01

337

A simple and scalable route to wafer-size patterned graphene  

PubMed Central

Producing large-scale graphene films with controllable patterns is an essential component of graphene-based nanodevice fabrication. Current methods of graphene pattern preparation involve either high cost, low throughput patterning processes or sophisticated instruments, hindering their large-scale fabrication and practical applications. We report a simple, effective, and reproducible approach for patterning graphene films with controllable feature sizes and shapes. The patterns were generated using a versatile photocoupling chemistry. Features from micrometres to centimetres were fabricated using a conventional photolithography process. This method is simple, general, and applicable to a wide range of substrates including silicon wafers, glass slides, and metal films.

Liu, Li-Hong; Zorn, Gilad; Castner, David G.; Solanki, Raj; Lerner, Michael M.

2013-01-01

338

Optima XE Single Wafer High Energy Ion Implanter  

SciTech Connect

The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny [Axcelis Technologies, Inc. 108 Cherry Hill Drive, Beverly, MA 01915 (United States)

2008-11-03

339

Study of temperature distributions in wafer exposure process  

NASA Astrophysics Data System (ADS)

During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

Lin, Zone-Ching; Wu, Wen-Jang

340

AlN wafers fabricated by hydride vapor phase epitaxy  

SciTech Connect

The authors report on AlN wafers fabricated by hydride vapor phase epitaxy (HVPE). AlN thick layers were grown on Si substrates by HVPE. Growth rate was up to 60 microns per hour. After the growth of AlN layers, initial substrates were removed resulting in free-standing AlN wafers. The maximum thickness of AlN layer was about 1 mm. AlN free-standing single crystal wafers with a thickness ranging from 0.05 to 0.8 mm were studied by x-ray diffraction, transmission electron microscopy, optical absorption, and cathodoluminescence.

Nikolaev, A.; Nikitina, I.; Zubrilov, A.; Mynbaeva, M.; Melnik, Y.; Dmitriev, V.

2000-07-01

341

ELID supported grinding of thin sapphire wafers  

NASA Astrophysics Data System (ADS)

Sapphire material is, due to its crystal structure, difficult to machine in an economic way. There is a request for thin, i.e. below 0.2 mm thickness, sub surface damage free wafers to produce sensor elements. ELID -- electrolytic in process dressing -- is an innovative high end grinding technology, using small grain sizes, which enable to manufacture surfaces in a quality that is close to polished. ELID grinding requires exactly aligned machining parameters of the grinding process. To grind sapphire the material's behavior is additionally to be considered. Studies on the necessary oxide layer on the grinding wheel and influences on its build-up process will be presented. The presentation shows the results of comparing grinding experiments on different -- c-plane and r-plane -- sapphire materials. Different tool specifications are used. Infeed and grinding velocity are varied and the results on wear, removal rate and surface quality are shown. The process parameters the stiffness of the machine, the grinding forces and pressure are evaluated. The ELID grinding is compared in its results to conventional grinding steps. The material removal rate on sapphire is relatively small due to the extreme hardness of sapphire. The achieved excellent surface roughness will be discussed.

Makarenko, Igor; Vogt, Christian; Rascher, Rolf; Sperber, Peter; Stirner, Thomas

2010-05-01

342

Temperature rise of the mask-resist assembly during LIGA exposure.  

SciTech Connect

Deep X-ray lithography on PMMA resist is used in the LIGA process. The resist is exposed to synchrotron X-rays through a patterned mask and then is developed in a liquid developer to make high aspect ratio microstructures. The limitations in dimensional accuracies of the LIGA generated microstructure originate from many sources, including synchrotron and X-ray physics, thermal and mechanical properties of mask and resist, and from the kinetics of the developer. This work addresses the thermal analysis and temperature rise of the mask-resist assembly during exposure in air at the Advanced Light Source (ALS) synchrotron. The concern is that dimensional errors generated at the mask and the resist due to thermal expansion will lower the accuracy of the lithography. We have developed a three-dimensional finite-element model of the mask and resist assembly that includes a mask with absorber, a resist with substrate, three metal holders, and a water-cooling block. We employed the LIGA exposure-development software LEX-D to calculate volumetric heat sources generated in the assembly by X-ray absorption and the commercial software ABAQUS to calculate heat transfer including thermal conduction inside the assembly, natural and forced convection, and thermal radiation. at assembly outer and/or inner surfaces. The calculations of assembly maximum temperature. have been compared with temperature measurements conducted at ALS. In some of these experiments, additional cooling of the assembly was produced by forced nitrogen flow ('nitrogen jets') directed at the mask surface. The temperature rise in the silicon mask and the mask holder comes directly from the X-ray absorption, but nitrogen jets carry away a significant portion of heat energy from the mask surface, while natural convection carries away negligibly small amounts energy from the holder. The temperature rise in PMMA resist is mainly from heat conducted from the silicon substrate backward to the resist and from the inner cavity air forward to the resist, while the X-ray absorption is only secondary. Therefore, reduction of heat flow conducted from both substrate and cavity air to the resist is essential. An improved water-cooling block is expected to carry away most heat energy along the main heat conductive path, leaving the resist at a favorable working temperature.

Ting, Aili

2004-11-01

343

Cohesive zone model for direct silicon wafer bonding  

NASA Astrophysics Data System (ADS)

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Kubair, D. V.; Spearing, S. M.

2007-05-01

344

Efficient data transmission from silicon wafer strip detectors  

SciTech Connect

An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

1991-01-01

345

Efficient data transmission from silicon wafer strip detectors  

SciTech Connect

An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

1991-12-31

346

Nanoscale friction and wear properties of silicon wafer under different lubrication conditions  

NASA Astrophysics Data System (ADS)

The nanoscale friction and wear properties of single crystal silicon wafer under different lubrication conditions are studied in this paper. The experiments were performed with Si3N4 ball sliding on the surface of silicon wafer under four different lubrication conditions: dry friction, water lubrication, hydrogen peroxide lubrication and the static hydrogen peroxide dry friction. The results from the experiments have been analyzed showing the different friction and wear properties of the silicon wafer in different lubrication conditions. It is concluded that the wear rates under the water lubrication and under the hydrogen peroxide lubrication are both small, the chemical reactions are facilitated by the mechanical processes when the load and the sliding speed reach certain levels. This is mainly resulted by the enhanced lubricant performance with the formed silicon hydroxide Si(OH)4 film. Under the water lubrication, the wear is found in a way of material removed in molecule scale. Under the hydrogen peroxide lubrication, the wear is mainly caused by the spalling of micro-cracks. Under the dry friction condition, the wear is found being adhesive wear. And under the static peroxide dry friction, the wear is prevailing adhesive wear. These results are essential and valuable to the development of the efficient and environmental-friendly slurry for the chemical mechanical polishing (CMP) process.

Chen, Xiaochun; Zhao, Yongwu; Wang, Yongguang; Zhou, Hailan; Ni, Zhifeng; An, Wei

2013-10-01

347

Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

2012-11-01

348

Monitoring Dielectric Thin-Film Production on Product Wafers Using Infrared Emission Spectroscopy  

SciTech Connect

Monitoring of dielectric thin-film production in the microelectronics industry is generally accomplished by depositing a representative film on a monitor wafer and determining the film properties off line. One of the most important dielectric thin films in the manufacture of integrated circuits is borophosphosilicate glass (BPSG). The critical properties of BPSG thin films are the boron content, phosphorus content and film thickness. We have completed an experimental study that demonstrates that infrared emission spectroscopy coupled with multivariate analysis can be used to simultaneous y determine these properties directly from the spectra of product wafers, thus eliminating the need of producing monitor wafers. In addition, infrared emission data can be used to simultaneously determine the film temperature, which is an important film production parameter. The infrared data required to make these determinations can be collected on a time scale that is much faster than the film deposition time, hence infrared emission is an ideal candidate for an in-situ process monitor for dielectric thin-film production.

NIEMCZYK,THOMAS M.; ZHANG,SONGBIAO; HAALAND,DAVID M.

2000-12-18

349

Power-scalable 1.57 microm mode-locked semiconductor disk laser using wafer fusion.  

PubMed

We report the first (to our knowledge) wafer-fused high-power passively mode-locked semiconductor disk laser operating at 1.57 microm wavelength. An InP-based active medium was fused with GaAs/AlGaAs distributed Bragg reflector on a 2 inch wafer level, resulting in an integrated monolithic gain mirror. An intracavity wedged diamond heat-spreader capillary bonded to the gain chip provides efficient heat removal from the gain structure without disturbing the spectrum of the mode-locked laser. The laser produces over 0.6 W of average output power at 15 degrees C with 16 ps pulse width. The total output power accounting for all output beams emerging from the cavity was 0.86 W. The results reveal an essential advantage of wafer fusion processing of disparate materials over monolithically grown InP-based gain structures and demonstrate the high potential of this technique for power scaling of long-wavelength semiconductor disk lasers. PMID:19838252

Saarinen, Esa J; Puustinen, Janne; Sirbu, Alexei; Mereuta, Alexandru; Caliman, Andrei; Kapon, Eli; Okhotnikov, Oleg G

2009-10-15

350

Automated reticle inspection data analysis for wafer fabs  

NASA Astrophysics Data System (ADS)

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-03-01

351

Automated reticle inspection data analysis for wafer fabs  

NASA Astrophysics Data System (ADS)

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

352

Automated reticle inspection data analysis for wafer fabs  

NASA Astrophysics Data System (ADS)

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2008-10-01

353

Nanoindentation tests on diamond-machined silicon wafers  

Microsoft Academic Search

Nanoindentation tests were performed on ultraprecision diamond-turned silicon wafers and the results were compared with those of pristine silicon wafers. Remarkable differences were found between the two kinds of test results in terms of load-displacement characteristics and indent topologies. The machining-induced amorphous layer was found to have significantly higher microplasticity and lower hardness than pristine silicon. When machining silicon in

Jiwang Yan; Hirokazu Takahashi; Jun'ichi Tamaki; Xiaohui Gai; Hirofumi Harada; John Patten

2005-01-01

354

Thin Film Encapsulation for Secondary Batteries on Wafer Level  

Microsoft Academic Search

This paper presents results concerning the realization and characterization of thin film encapsulated wafer-level batteries. Initially, the technology concept for the construction and hermetic encapsulation of chip-size lithium-ion secondary batteries on wafer level is introduced. Parylene and thin-film metal deposition was used for hermetic encapsulation of the batteries. With this technology, battery sizes between 1 mm2 and 1 cm2, and

K. Marquardt; R. Hahn; T. Lugerl; H. Reichl

2006-01-01

355

Novel analytical methods for the characterization of oral wafers  

Microsoft Academic Search

This study aims at compensating the lack of adequate methods for the characterization of the novel dosage forms buccal wafers by applying recent advanced analytical techniques. Fast-dissolving oral wafers need special methods for assessing their properties in drug development and quality control. For morphologic investigations, scanning electron microscopy (SEM) and near-infrared chemical imaging (NIR-CI) were used. Differences in the distribution

Verena Garsuch; Jörg Breitkreutz

2009-01-01

356

Calibration accuracy of a 625 GHz on-wafer probe  

Microsoft Academic Search

The accuracy of an on-wafer probe system operating at 625 GHz is analyzed. A weighted least squares analysis is applied to the calibration of a one-port measurement system to propagate the non-systematic errors introduced by probe contact and probe placement variation. The worst-case errors of the 625 GHz on-wafer probe system are found and the combined effects of the VNA

Theodore J. Reck; Lihan Chen; Chunhu Zhang; Alex Arsenovic; Arthur Lichtenberger; Robert M. Weikle; N. S. Barker

2010-01-01

357

GHz on-silicon-wafer probing calibration methods  

Microsoft Academic Search

Three calibration\\/correction techniques for on-silicon-wafer S-parameter measurements to 18 GHz were assessed by comparing calibration standards on sapphire and silicon. The effect of these techniques was evaluated by measuring large and small devices, connected to large and small pads. Equivalent circuit models for the calibration standards on silicon are presented. In addition, a new technique for on-wafer S-parameter measurements of

Arthur Fraser; Reed Gleason; E. W. Strid

1988-01-01

358

A low cost wafer-level MEMS packaging technology  

Microsoft Academic Search

This paper presents a low-cost low-temperature packaging technique for wafer-level encapsulation of MEMS devices fabricated on any arbitrary substrate. The packaging process presented here does not involve wafer bonding and can be applied to a wide variety of MEMS devices after their fabrication sequence is completed. Our technique utilizes thermal decomposition of a sacrificial polymeric material through a polymer overcoat

P. Monajemi; F. Ayazi; P. J. Joseph; P. A. Kohl

2005-01-01

359

Low temperature epoxy bonding for wafer level MEMS packaging  

Microsoft Academic Search

In this paper, we report on a technology for wafer-level MEMS packaging with vertical via holes and low temperature bonding using a patternable B stage epoxy. We fabricated via holes for vertical feed-throughs and then applied bottom-up copper electroplating to fill the via holes. For low temperature wafer level packaging, we used B-stage epoxy bonding in the sealing line. The

Yong-Kook Kim; Eun-Kyung Kim; Soo-Won Kim; Byeong-Kwon Ju

2008-01-01

360

Silicon-on-insulator (SOI) wafer fabrication for MEMS applications  

NASA Astrophysics Data System (ADS)

In this paper, it is shown that Silicon-On-Insulator (SOI) wafers with good surface finish and thickness control can be realized using Silicon Fusion Bonding along with an optimized ethylenediamine-pyrocatechol-water (EDP) etching approach. Single crystal diaphragms of 11 ?m thickness have been fabricated using these SOI wafers. These diaphragms were tested and found to withstand N2 gas pressures in excess of 260 psi without rupturing.

KotiReddy, Bhimanadhuni R.; Rao, Parimi R.; DasGupta, Amitava; Bhat, Kunchinadka N. H.

2003-10-01

361

Silicon Wafer Bonding Mechanism for Silicon-on-Insulator Structures  

Microsoft Academic Search

X-ray diffraction topography and tensile testing are used to study the perfection of bonded interfaces in the sandwich structure where one of the two silicon wafers used had an SiO2 layer applied to it first. The tensile strength and the formation of unbonded areas (voids) were compared to the cases where two bare silicon wafers were used and where both

Takao Abe; Tokio Takei; Atsuo Uchiyama; Katsuo Yoshizawa; Yasuaki Nakazato

1990-01-01

362

Transparent masks for aligned deep x-ray lithography\\/LIGA: low-cost high-performance alternative using glass membranes  

Microsoft Academic Search

Deep x-ray lithography\\/LIGA has proven to be a well established framework of x-ray based technologies for the fabrication of microstructures and pseudo three-dimensional objects. Inherently, x-ray lithography\\/LIGA is not fully three-dimensional because of the principle of simple shadow printing onto resists of constant thickness. Thus, it would be impossible to obtain 3D spheres, but series of stacked monolithic 2D cylinders.

Roland K. Kupka; Stephan Megtert; Marc Roulliay; Faycal Bouamrane

1998-01-01

363

High temperature materials for thin-film thermocouples on silicon wafers  

Microsoft Academic Search

We have developed an instrumented calibration wafer for radiometric temperature measurements in rapid thermal processing (RTP) tools for semiconductor processing. The instrumented wafers have sputter deposited thin-film thermocouples to minimize the thermal disturbance of the wafer by the sensors. The National Institute of Standards and Technology (NIST) calibration wafer also employs platinum–palladium wire thermocouples to achieve a combined standard uncertainty

Kenneth G Kreider; Greg Gillen

2000-01-01

364

High productivity multiple DUT CV test for MEMS microphone wafer with automatic correction  

Microsoft Academic Search

Productivity in MEMS wafer process is getting more and more important as mass production on 200 mm wafer is increasing. Multiple DUT parallel CV test is a high productive way for MEMS Microphone wafer test process, however, in case of the one of two electrodes is connected to the wafer substrate with some contact resistance, interference among DUTs has an

S. Inuzuka

2010-01-01

365

Production scheduling in a semiconductor wafer fabrication facility producing multiple product types with distinct due dates  

Microsoft Academic Search

Focuses on production scheduling in a semiconductor wafer fab producing multiple product types that have different due dates and different process flows. In the wafer fab, wafer lots are processed on serial and batch processing workstations, each of which consists of parallel identical machines. Machines in serial processing workstations process wafer lots one by one, while those in batch processing

Yeong-Dae Kim; Jae-Gon Kim; Bum Choi; Hyung-Un Kim

2001-01-01

366

Electrochemical method for defect delineation in silicon-on-insulator wafers  

DOEpatents

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, Terry R. (Albuquerque, NM); Jones, Howland D. T. (Albuquerque, NM); Kelly, Michael J. (Albuquerque, NM); Medernach, John W. (Albuquerque, NM); Stevenson, Joel O. (Albuquerque, NM); Tsao, Sylvia S. (Albuquerque, NM)

1991-01-01

367

Electrical through-wafer interconnects with sub-picofarad parasitic capacitance [MEMS packaging  

Microsoft Academic Search

This paper presents a technology for high density and low parasitic capacitance electrical through-wafer interconnects to an array of capacitive micromachined ultrasonic transducers (CMUTs) on a silicon wafer. Vertical wafer feedthroughs (interconnects) connect an array of sensors or actuators from the front side (transducer side) to the backside (packaging side) of the wafer. A 20 to 1 high aspect ratio

C. H. Cheng; A. S. Ergun; B. T. Khuri-Yakub

2001-01-01

368

Electrochemical method for defect delineation in silicon-on-insulator wafers  

DOEpatents

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, T.R.; Jones, D.T.H.; Kelly, M.J.; Medernach, J.W.; Stevenson, J.O.; Tsao, S.S.

1990-01-01

369

Fabrication Of SOI Wafers With Buried Cavities Using Silicon Fusion Bonding And Electrochemical Etchback  

Microsoft Academic Search

This paper describes a new technique for batch fabrication of Silicon On Insulator (SOI) wafers for MEMS applications by silicon wafer bonding techniques. The process permits the inclusion of buried cavities in the SO1 wafers, providing a useful tool for sensor and actuator fabrication using the resulting wafers. A low cost electrochemical etchback step is used to accurately define the

J. Mark Noworolski; Emo Klaassen; John Logan; Kurt Petersen; N. Maluf

1995-01-01

370

Scribe characterization vehicle test chip for ultra fast product wafer yield monitoring  

Microsoft Academic Search

Sub 100nm technology nodes face more wafer to wafer and lot to lot variability. 300mm wafer manufacturing also faces larger within wafer spatial trends. Monitoring those issues on a per layer basis as well as correlating them to the product yield is key for significant yield improvements. A novel characterization vehicle® (CV®) has been developed, which is being used in

Christopher Hess; Anand Inani; Yun Lin; Michele Squicciarini; Ron Lindley; Nobuchika Akiya

2006-01-01

371

Plasma enhanced chemical vapor processing of semiconductive wafers  

US Patent & Trademark Office Database

Semiconductive wafers are processed, i.e., etched or layers deposited thereon, by means of a plasma enhanced chemical vapor processing system. The processing system includes an evacuable horizontal tubular envelope disposed within a surrounding heater or furnace for maintaining, the case of deposition, a region of uniform temperature within the central region of the elongated tubular envelope. Two sets of interleaved generally planar electrodes are disposed within the evacuable envelope for establishing an electrical plasma discharge in the process gaps defined between the interleaved electrodes. Wafers are loaded into the processing gaps vertically with the major face of each wafer facing into the process gap. The mutually opposed surfaces of the interleaved electrodes are preferably lined with a material of the same conductivity as that of the bulk material of the wafer to enhance the uniformity of the processing. The chemical vapor is caused to flow axially through the evacuable tube, and through the electrical plasma discharge established in the processing gaps at subatmospheric pressure, to produce chemically active vapor products of the plasma discharge which interact with the faces of the wafers facing into the processing gaps for processing of the wafers.

1980-09-16

372

Further investigation of EUV process sensitivities for wafer track processing  

NASA Astrophysics Data System (ADS)

As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.

Bradon, Neil; Nafus, K.; Shite, H.; Kitano, J.; Kosugi, H.; Goethals, M.; Cheng, S.; Hermans, J.; Hendrickx, E.; Baudemprez, B.; van den Heuvel, D.

2010-03-01

373

LIGA fabrication of mm-wave accelerating cavity structures at the Advanced Photon Source (APS)  

SciTech Connect

Recent microfabrication technologies based on the LIGA (German acronym for Lithographe, Galvanoformung, und Abformung) process have been applied to build high-aspect-ratio, metallic or dielectric planar structures suitable for high-frequency rf cavity structures. The cavity structures would be used as parts of linear accelerators, microwave undulators, and mm-wave amplifiers. The microfabrication process includes manufacture of precision x-ray masks, exposure of positive resist x-rays through the mask, resist development, and electroforming of the final microstructure. Prototypes of a 32-cell, 108-GHz constant-impedance cavity and a 66-cell, 94-GHz constant-gradient cavity were fabricated with the synchrotron radiation sources at APS and NSLS. This paper will present an overview of the new technology and details of the mm-wave cavity fabrication.

Song, J.J.; Bajikar, S.; Kang, Y.W. [and others

1997-08-01

374

Fundamental limitations of LIGA x-ray lithography : sidewall offset, slope and minimum feature size.  

SciTech Connect

Analytical and numerical methods are used to examine photoelectron doses and their effect on the dimensions of features produced by deep x-ray lithography. New analytical models describing electron doses are presented and used to compute dose distributions for several feature geometries. The history of development and final feature dimensions are also computed, taking into account the dose field, dissolution kinetics based on measured development rates, and the transport of PMMA fragments away from the dissolution front. We find that sidewall offsets, sidewall slope and producible feature sizes all exhibit at least practical minima and that these minima represent fundamental limitations of the LIGA process. The minimum values under optimum conditions are insensitive to the synchrotron spectrum, but depend strongly on resist thickness. This dependence on thickness is well approximated by simple analytical expressions describing the minimum offset, minimum sidewall slope, minimum producible size of positive and negative features, maximum aspect ratio and minimum radius of inside and outside corners.

Griffiths, Stewart K.

2004-01-01

375

Temperature rise of the silicon mask-PMMA resist assembly during LIGA exposure.  

SciTech Connect

Deep X-ray lithography on PMMA resist is used in the LIGA process. The resist is exposed to synchrotron X-rays through a patterned mask and then is developed in a liquid developer to make high aspect ratio microstructures. This work addresses the thermal analysis and temperature rise of the mask-resist assembly during exposure at the Advanced Light Source (ALS) synchrotron. The concern is that the thermal expansion will lower the accuracy of the lithography. We have developed a three-dimensional finite-element model of the mask and resist assembly. We employed the LIGA exposure-development software LEX-D and the commercial software ABAQUS to calculate heat transfer of the assembly during exposure. The calculations of assembly maximum temperature have been compared with temperature measurements conducted at ALS. The temperature rise in the silicon mask and the mask holder comes directly from the X-ray absorption, but forced convection of nitrogen jets carry away a significant portion of heat energy from the mask surface, while natural convection plays a negligible role. The temperature rise in PMMA resist is mainly from heat conducted from the silicon substrate backward to the resist and from the mask plate through inner cavity air forward to the resist, while the X-ray absorption is only secondary. Therefore, reduction of heat flow conducted from both substrate and cavity air to the resist is essential. An improved water-cooling block is expected to carry away most heat energy along the main heat conductive path, leaving the resist at a favorable working temperature.

Ting, Aili

2004-10-01

376

Fabrication of Germanium-on-Insulator by low temperature direct wafer bonding  

Microsoft Academic Search

A Germanium-on-Insulator (GeOI) wafer was fabricated using low temperature direct wafer bonding method. A hydrogen implanted Ge donor wafer was bonded to a thermally oxided Si handle wafer with in-situ oxygen radical activation before bonding in a vacuum chamber. Ex-situ anneals were use to enhance the bond strength or exfoliate the implanted Ge wafer. The insight into the exfoliation mechanism

Ran Yu; Ki Yeol Byun; I. Ferain; D. Angot; R. Morrison; C. Colinge

2010-01-01

377

Incorporating BCNU wafers into malignant glioma treatment: European case studies.  

PubMed

Carmustine (BCNU: N,N'-bis[2-chloroethyl]-N-nitrosourea) wafers are a local chemotherapeutic agent for the treatment of malignant glioma. They avoid the problems of high toxicity and short half-life associated with systemic delivery, and can bridge the traditional 'treatment gap' between surgery and subsequent conventional chemo- or radiotherapy. Clinical trials have demonstrated significant improvements in survival and quality of life for patients after complete tumour resection and BCNU wafer implantation. In practice, clinicians may use BCNU wafers in conjunction with other radio- and chemotherapies, in order to maximize the chance of a beneficial patient outcome. The purpose of these case reports is to exemplify how four experienced European clinicians employ BCNU wafers for the management of malignant glioma, and to illustrate how BCNU wafers can be effectively incorporated into treatment regimens. Four patients are described in whom BCNU wafers were implanted during the course of treatment for glioblastoma multiforme, the most severe and common type of malignant glioma. These include three patients with recurrent disease, and a single patient with a newly diagnosed tumour. All four patients received additional radio- and chemotherapy as appropriate. Treatment was well tolerated and patient survival from diagnosis ranged from 56 to 132 weeks. This compared favourably with the survival of approximately 58 weeks seen in the recent EORTC-NCIC clinical trial of combined radiotherapy with concomitant and adjuvant temozolomide. BCNU wafers are an effective means of increasing survival and quality of life in patients diagnosed with malignant glioma, and are a valuable addition to the overall multimodal treatment strategy for these tumours. PMID:20155992

Balossier, Anne; Dörner, Lutz; Emery, Evelyne; Heese, Oliver; Mehdorn, H Maximilian; Menei, Philippe; Singh, Jagmohan

2010-01-01

378

100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices  

SciTech Connect

A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

OLIVER,ANDREW D.; MATZKE,CAROLYN M.

2000-04-06

379

Highly precise micro-retroreflector array fabricated by the LIGA process and its application as tapped delay line filter.  

PubMed

We report on the fabrication of a one-dimensional micro-retroreflector array with a pitch of 100 ?m. The array was fabricated by x-ray lithography and the lithographie, galvanik und abformung (LIGA) process in a 1 mm thick poly(methyl methacrylate) (PMMA) layer and subsequently covered with Au. The area of the array is 1 mm×10 mm. The high precision of the LIGA-based fabrication process allows one to use the element in spectrometers. Here, it is suggested to apply it to the implementation of a transversal filter for femtosecond pulses. We present a theoretical description of the performance of the retroreflector array as a filtering device and show experimental results. PMID:22945143

Bohling, Michael; Seiler, Thomas; Wdowiak, Boguslaw; Jahns, Jürgen; Mohr, Jürgen; Börner, Martin

2012-09-01

380

Thermal spray and cold spray analysis of density, porosity, and tensile Specimens for use with LIGA applications  

SciTech Connect

This analysis provides a preliminary investigation into using Twin-Wire Arc Thermal Spray and Cold Spray as material deposition processes for LIGA applications. These spray material processes were studied to make an initial determination of their potential as alternatives to producing mechanical parts via the electroplating process. Three materials, UltraMachinable{reg_sign} Stainless Steel, BondArc{reg_sign}, and aluminum, were sprayed using Thermal Spray. Only aluminum was sprayed using the Cold Spray process. Following the spray procedure, the test specimens were released from a copper mold and then tested. Three tests, density, tensile strength, and porosity, were performed on the specimens to determine the spray effect on material properties. Twin-Wire Arc Thermal Spray did not demonstrate adequate deposition properties and does not appear to be a good process candidate for LIGA. However, Cold Spray yielded better density results and warrants further investigation to analyze the minimum feature size produced by the process.

DECKER,MERLIN K.; SMITH,MARK F.

2000-02-01

381

Oxygen Precipitation Behavior in Czochralski Silicon Wafers  

NASA Astrophysics Data System (ADS)

The morphology change of oxygen precipitates and the formation of secondary defects were studied during single and two-step heat-treatments in Czochralski silicon (CZ-Si) wafers with transmission electron microscopy (TEM), high resolution transmission electron microscopy (HRTEM), and solute-oxygen concentration measurement by Fourier -transform infrared absorption spectroscopy (FT-IR). The oxygen precipitates were observed with various morphology after single annealing at different temperatures; thermal donors, platelets, dendritic large-plates, and octahedra are formed in the temperature ranges of 400 ~ 450^circ C, 650 ~ 800^ circC, 900 ~ 1000 ^circC, and 1100^ circC, respectively. The dendritic shape is found for the first time as a precipitate morphology formed at 900 ~ 1000^ circC. The growth kinetics of the precipitates is found to be explained by Ham's diffusion-limited-precipitation theory. The morphology change of the precipitates in two -step annealings was seen generally in a way that the dissolution of a lower-temperature precipitate-form and the formation of a high-temperature form occur simultaneously. Thermal donors lose their electrical activity and apparently dissolve into solute. However, they leave a local fluctuation of the solute-oxygen concentration and it enhances the new nucleation of higher-temperature precipitates. Platelets were dissolved partially and octahedra can grow from the partially dissolved platelets as well as newly nucleated ones in the second high-temperature annealing. These results indicate that the morphology change and dissolution effect should be taken into account to clarify the total precipitation kinetics. As secondary defects of the precipitation, dislocation loops were observed dominantly in the single annealings in association with the platelet formation; on the other hand, stacking faults were mainly seen after the octahedron formation in the two-step annealings. It is proposed that the precipitate morphology is determined by the relaxation of the lattice stress due to the volume difference between the oxide and the matrix silicon; the platelet is a favorable shape to reduce the strain at lower temperatures and the octahedron is easily formed with the stress release by self-interstitial emission at temperatures higher than 1000^circC.

Hasebe, Masami

382

X-ray transmission lenses by deep x-ray lithography and LIGA technique: first results and fundamental limits  

Microsoft Academic Search

Today's dimensionality of microtechnology enables the fabrication of precise objects, like diffraction limited x- ray transmission optics. Based on deep x-ray\\/LIGA technology, first results are presented concerning the fabrication and modelling of parabolic and massive-serial focalizing x-ray transmission lenses in PMMA, as opposed to standard grazing incidence reflection optics. The theoretical performance limitations of such optical systems are derived and

Roland K. Kupka; Faycal Bouamrane; Marc Roulliay; Stephan Megtert

1999-01-01

383

Fabrication of micro nickel\\/diamond abrasive pellet array lapping tools using a LIGA-like technology  

Microsoft Academic Search

A manufacturing process of micro nickel\\/diamond abrasive pellet array lapping tools using a LIGA-like technology is reported here. The thickness of JSR THB-151N resist coated on an aluminum alloy substrate for micro lithography can reach up to 110 µm. During the lithography, different geometrical photomasks were used to create specific design patterns of the resist mold on the substrate. Micro

Sheng-Yih Luo; Tsung-Han Yu; Yuh-Chung Hu

2007-01-01

384

Large-Area X-ray Lithography System for LIGA Process Operating in Wide Energy Range of Synchrotron Radiation  

Microsoft Academic Search

We developed a new X-ray lithography system for the lithographite, galvanoformung and abformung process (LIGA process) using synchrotron radiation at the NewSUBARU facility of the University of Hyogo. The X-ray lithography system can utilize two different energy regions: one is a high-energy region: from 2 keV to 12 keV, and the other is a low-energy region from 1 to 2

Yuichi Utsumi; Takefumi Kishimoto; Tadashi Hattori; Hirotsugu Hara

2005-01-01

385

Low-temperature titanium-based wafer bonding  

NASA Astrophysics Data System (ADS)

This thesis presents novel methods of metal-based wafer bonding at back-end-of-the-line (BEOL) compatible conditions (?450°C). For the first time to our knowledge, 200 mm diameter oxidized Si wafers are bonded with prime Si wafers using 10-300 nm thick Ti as bonding intermediate at 300-450°C. Nearly void-free bonding with strong mechanical integrity has been confirmed. Moreover, microcavity formation has been demonstrated by bonding of patterned wafers. Both Rutherford backscattering spectroscopy (RBS) and Auger electron spectroscopy (AES) show clear evidence of Si and Ti interdiffusion, whereas high-resolution transmission electron microscopy (HRTEM) reveals an approximately 8 nm thick amorphous layer at the bonding interface. Those results indicate that the strong adhesion at the Ti/Si bonding interface is attributed to a solid-state amorphization (SSA) assisted by interdiffusion. A key effort is devoted to fundamental investigation of low-temperature transition metal(TM)/Si-based wafer bonding. With the extensive work on Ti/Si system, additional experiments are performed with six other TM/Si systems, namely Ni/Si, Co/Si, Pd/Si, Hf/Si, Au/Si and Ta/Si. The results indicate there are two principal requirements for TM/Si-based wafer bonding: (1) intimate contact (able to break through kinetic barriers), and (2) adequate chemical bonding. Three kinetic barriers addressed in this thesis are: (1) enclosed microvoids due to surface roughness, (2) gas molecules at the bonding interface, and (3) interfacial oxides. Presence of these barriers can prevent formation of intimate contact, consequently retarding or even blocking interfacial interactions for chemical bonding. The unique properties of Group IVA metals (e.g., Ti and Hf) to reduce native SiO2 on Si surfaces and their exceptionally large solid solubility for O2 and N2, help overcome those issues. Once kinetic barriers are surmounted, the key for strong metal/Si-based wafer bonding is formation of chemical bonds, aided primarily by interdiffusion. According to their principal bonding mechanisms, the examined seven TM/Si-based wafer bonding can be divided into three groups: (1) silicidation bonding (Ni/Si, Co/Si and Pd/Si), (2) solid-state amorphization bonding (Ti/Si and Hf/Si), and (3) eutectic bonding (Au/Si). One of the major thesis contributions is the development and identification of a new type of metal-based wafer bonding, i.e. SSA bonding.

Yu, Jian

386

WaferOptics® mass volume production and reliability  

NASA Astrophysics Data System (ADS)

The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

Wolterink, E.; Demeyer, K.

2010-04-01

387

Fabrication of the 3 Dimension Resist Microstructure Using X-Ray Diffraction and Applying to LIGA Process  

NASA Astrophysics Data System (ADS)

The LIGA process consists of lithography, electroforming and molding has attracted attention in microstructure fabrication techniques. At the molding process of LIGA process, it is difficult to pull out from the mold that is assumed especially in the case of high aspect ratio structures. However, release from mold is improved by tapered structure. In this research, we have proposed a method for achieving tapered structure using the diffraction exposure technique which makes use of diffraction phenomenon. Diffraction is caused by providing a clearance between a resist structure and an X-ray mask. The fabricated structure was the lines and intermediate space whose processed depth was 200 µm and designated the taper angle of 5 degrees as set point. The variable parameters were the slit width, the X-ray dose and the gap between the X-ray mask and the resist structure. It is controlled that discovering the conditions for taper angle 5 degrees and inspecting the relationship between a taper angle and a mold releasability by electroforming and the molding of the LIGA process. We have fabricated the mold with taper angle of 2.5 degrees by electroforming. The Ni mold could partially copy the master pattern well.

Sawa, Yoshitaka; Tanabiki, Kyo; Noda, Daiji; Hattori, Tadashi

388

Chemical processing of materials on silicon: more functionality, smaller features, and larger wafers.  

PubMed

The invention of the transistor followed by more than 60 years of aggressive device scaling and process integration has enabled the global information web and subsequently transformed how people communicate and interact. The principles and practices built upon chemical processing of materials on silicon have been widely adapted and applied to other equally important areas, such as microfluidic systems for chemical and biological analysis and microscale energy storage solutions. The challenge of continuing these technological advances hinges on further improving the performance of individual devices and their interconnectivity while making the manufacturing processes economical, which is dictated by the materials' innate functionality and how they are chemically processed. In this review, we highlight challenges in scaling up the silicon wafers and scaling down the individual devices as well as focus on needs and challenges in the synthesis and integration of multifunctional materials. PMID:22691090

Marchack, Nathan; Chang, Jane P

2012-01-01

389

Non-contacting electrostatic voltmeter for wafer potential monitoring  

NASA Astrophysics Data System (ADS)

As part of the continuing reduction of half-pitch line widths, the International Technology Roadmap for Semiconductors (ITRS) forecasts an increasing number of issues with electrostatic discharge (ESD) related phenomena and the need for improved electrostatic charge control in semiconductor wafer processing. This means that wafer metrology should encompass charge measurements as a routine operation. Additionally, with the increasing complexity of wafer processing, in-line measurements including surface voltage and charge detection and analysis are becoming more important. One of the instruments utilized in such measurements is a non-contacting electrostatic voltmeter (ESVM). In this paper the authors would like to introduce a new design for the ESVM probe which allows for the measurement of surface voltages with DC stability and millivolt sensitivity. The construction of the probe utilizes a gold plated sensor that is mounted on a vibrating tuning fork which is electromechanically excited by a piezoelectric driver.

Noras, Maciej A.; Maryniak, William A.

2007-03-01

390

Vacuum chuck having vacuum-nipples wafer support  

US Patent & Trademark Office Database

A vacuum chuck is disclosed which has nipples as support structure and for vacuum delivery. In the preferred embodiment, two types of nipples are used: "plain" nipples which provide only support and vacuum nipples which provide support and deliver vacuum to retain the wafer on the chuck. The contact surface of the plain nipples is made smaller than that of the vacuum nipples. The chuck is secured to a stage using special supports which have limited flexibility in two axis with respect to the chuck, so as to prevent warping the chuck. Special vacuum nipples are disclosed which do not deliver vacuum unless the wafer exerts sufficient predetermined pressure on the nipple. The chuck is designed to hold both 200 mm and 300 mm wafers.

2001-07-10

391

Low cost wafer metrology using a NIR low coherence interferometry.  

PubMed

In this investigation, a low cost Si wafer metrology system based on low coherence interferometry using NIR light is proposed and verified. The whole system consists of two low coherence interferometric principles: low coherence scanning interferometry (LCSI) for measuring surface profiles and spectrally-resolved interferometry (SRI) to obtain the nominal optical thickness of the double-sided polished Si wafer. The combination of two techniques can reduce the measurement time and give adequate dimensional information of the Si wafer. The wavelength of the optical source is around 1 ?m, for which transmission is non-zero for undoped silicon and can be also detected by a typical CCD camera. Because of the typical CCD camera, the whole system can be constructed inexpensively. PMID:23736617

Kim, Young Gwang; Seo, Yong Bum; Joo, Ki-Nam

2013-06-01

392

Correlation of the structural properties of a Pt seed layer with the perpendicular magnetic anisotropy features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 junctions via a 12-inch scale Si wafer process  

NASA Astrophysics Data System (ADS)

We elucidated the interfacial-perpendicular magnetic anisotropy (i-PMA) features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 magnetic-tunnel-junctions as functions of the structural properties of the Pt seed layer including its thickness and ex situ annealing temperature. All of the samples were prepared in a 12-inch silicon wafer process for real industry applications. The observations of the M-H loops emphasize that a thinner Pt seed layer and a high ex situ annealing temperature enhance the surface roughness of the seed layer, providing better i-PMA characteristics. HR-TEM images of the samples were evaluated to understand the structural effects of thin and thick Pt seed layers.

Chae, Kyo-Suk; Lee, Du-Yeong; Shim, Tae-Hun; Hong, Jin-Pyo; Park, Jea-Gun

2013-10-01

393

Modeling emissivity of rough and textured silicon wafers  

SciTech Connect

A method for calculating the emissivity of Si wafers with planar and nonplanar (such as rough or textured) surface morphologies is described. The technique is similar to that used in modeling of light trapping in solar cells and is also applicable to those cases when the wafer may have thin dielectric or metal layers. A software package is developed that uses this method. This package includes an approach for calculating the refractive index and absorption coefficient as a function of wavelength, for various temperatures and dopant concentrations. The authors present results for a number of cases to demonstrate the applications of this model.

Sopori, B.L.; Chen, W. [National Renewable Energy Lab., Golden, CO (United States); Abedrabbo, S.; Ravindra, N.M. [New Jersey Inst. of Tech., Newark, NJ (United States)

1998-12-01

394

Full-wafer technology for laser fabrication and testing  

Microsoft Academic Search

Summary Full-wafer fal~rication of A1GaAs lasers, which have mirrors etched by chemically assisted ion-beam etching and passivated by ion-beam sputtered AlzO3, is described. Full-wafer testing techniques for both laser parameters (P-l, far-field, spectrum, T0), as well as other test sites for process development and control (critical dimensions, overlay, etch depths, sheet resistances) have been developed, q'he lasers have excellent beam

D. J. Webb; M. K. Benedict; G. L. Bona; P. Buchman; N. Cahoon; K. Dätwyler; H. P. Dietrich; A. Moser; G. Sasso; H. K. Seitz; P. Vettiger; O. Voegeli; P. Wolf

1991-01-01

395

Semiconductor wafer bonding and ion-cut layer transfer  

NASA Astrophysics Data System (ADS)

This dissertation describes a semiconductor layer transfer process using wafer bonding and hydrogen-induced semiconductor cleavage. In this process, hydrogen is implanted into a wafer that has the layer to be transferred. The implanted hydrogen ions form a highly damaged region around the hydrogen stopping range. The implanted wafer is then bonded to another wafer using low-temperature direct bonding. With appropriate heat or mechanical treatment, the bonded wafer pair separates along the highly damaged region, resulting in the transfer of the layer from one substrate to the other. With this technique, we have been able to fabricate silicon-on-insulator (SOI) structures by transferring single- and poly-crystalline silicon layers, especially using hydrogen plasma implantation, oxygen plasma-activated wafer bonding, and thermal cleavage and mechanical cleavage methods. We have also formed silicon, SOI, and oxide membranes on buried cavities and channels, which can be applied for use in pressure transducers, micro-fluidic systems, and radio frequency filters and resonators. In these demonstrations, we have observed good thickness uniformity (<1%) across a 100 mm wafer and surface microroughness (<10 nm) of the transferred layers. For the transfer of pre-fabricated electronic device layers, gate oxide damage was first evaluated after high-dose and high-energy hydrogen implantation through metal-oxide-silicon (MOS) transistors. The results showed that stress-induced leakage current (SILO) through the gate oxide increased as hydrogen dose increased for the 5 nm-thick oxide. For the 1.8 nm-thick gate oxide, no SILC was observed, showing that the implantation damage is not significant for the ultra-thin (<2 nm) oxides. To protect the thicker (>3 nm) oxides from damage during the hydrogen implantation, we have proposed layer transfer with patterned implantation of hydrogen. In this process, active device regions were masked during the implantation. This experiment showed that the hydrogen induced silicon layer cleavage is feasible even without a continuous hydrogen implantation of the entire wafer, and that the silicon cleavage can propagate across at least 16 microns of non-implanted area from a 4 micron-wide implanted region each side. Furthermore, it has shown that the mechanical cleaving can overcome some non-implantation area limitations imposed by the thermal cleavage process.

Yun, Changhan

396

Wafer CD variation for random units of track and polarization  

NASA Astrophysics Data System (ADS)

After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle MTT and wafer intra-field MTT is shown for ENG process without polarization. The influence of different exposure conditions - with and without polarization of scanner laser source - on the average CD value for isolated and dense structures is demonstrated.

Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

2012-03-01

397

An application of selective electrochemical wafer thinning for silicon characterization  

SciTech Connect

A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

1990-01-01

398

The influence of feature sidewall tolerance on minimum absorber thickness for LIGA x-ray masks  

SciTech Connect

Minimizing mask absorber thickness is an important practical concern in producing very small features by the LIGA process. To assist in this minimization, the authors have developed coupled numerical models describing both the exposure and development of a thick PMMA resist. The exposure model addresses multi-wavelength, one-dimensional x-ray transmission through multiple beam filters, through the mask substrate and absorber, and the subsequent attenuation and photon absorption in the PMMA resist. The development model describes one-dimensional dissolution of a feature and its sidewalls, taking into account the variation in absorbed dose through the PMMA thickness. These exposure and development models are coupled in a single interactive code, permitting the automated adjustment of mask absorber thickness to yield a prescribed sidewall taper or dissolution distance. They have used this tool to compute the minimum required absorber thickness yielding a prescribed sidewall tolerance for exposures performed at the ALS, SSRL and NSLS synchrotron sources. Results are presented as a function of the absorbed dose for a range of the prescribed sidewall tolerance, feature size, PMMA thickness, mask substrate thickness and the development temperature.

S. K. Griffiths; J. M. Hruby; A. Ting

1999-02-01

399

Wafer bonding using microwave heating of parylene intermediate layers  

Microsoft Academic Search

This paper describes a novel wafer bonding technique using microwave heating of parylene intermediate layers. The bonding is achieved by parylene deposition and thermal lamination using microwave heating. Variable frequency microwave heating provides uniform, selective and rapid heating for parylene intermediate layers. The advantages of this bonding technique include short bonding time, low bonding temperature, relatively high bonding strength, less

Hong-seok Noh; Kyoung-sik Moon; Andrew Cannon; Peter J. Hesketh; C. P. Wong

2004-01-01

400

90nm Games Processor Wafer to Module Power Yield Optimization  

Microsoft Academic Search

When fabricating a high volume games processor (CPU) for the consumer market, due to the cost of the module package, it is important to optimize the functional yield loss between the wafer die and the finished module package. For a performance CPU in a mature 90 nm technology the primary yield drivers can be power and performance. A functional power

Raymond Mallette; Brad Rawlins

2008-01-01

401

The uses of Man-Made diamond in wafering applications  

Microsoft Academic Search

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The

D. B. Fallon

1982-01-01

402

Surface activated bonding of silicon wafers at room temperature  

Microsoft Academic Search

A method to bond silicon wafers directly at room temperature was developed. In this method, surfaces of two silicon samples are activated by argon atom beam etching and brought into contact in a vacuum. By the infrared microscope and KOH etching method, no void at the bonded interface was detected in all the specimens tested. In the tensile test, fracture

H. Takagi; K. Kikuchi; R. Maeda; T. R. Chung; T. Suga

1996-01-01

403

A Parallel Discrete-Event Simulation of Wafer Fabrication Processes  

Microsoft Academic Search

Simulation modeling is an important tool for planning factory operations, to identify and eliminate possible bottlenecks and to maintain h igh machine utilization. The objective of our project i s to app ly parallel simulation techniques for virtual f actory modeling in the electronics manufacturing sector. We have implemented a parallel wafer fabrication simulation model based on the Sematech data

Chu-Cheow LIM; Yoke-Hean LOW; Boon-Ping GAN; Stephen J. Turner; Sanjay Jain; Wentong CAI; Wen Jing HSU; Shell Ying

1998-01-01

404

Failure analysis of wafer-level reliability testing failure  

Microsoft Academic Search

Wafer-level reliability (WLR) testing is an important tool that is used during the productization phase to investigate the reliability performance of devices and materials before full qualification cycle. The rapid nature of the WLR testing permits the process engineer to evaluate process variation and to obtain almost instantaneous feedback about its reliability impact. Fast reliability feedback is essential to help

Chong K. Oh; Soh P. Neo; Jian H. Bi; Zong M. Wu; Lian C. Goh; Shailesh Redkar

1999-01-01

405

Thermomechanical Design of Resilient Contact Systems for Wafer Level Packaging  

Microsoft Academic Search

Wafer level packaging (WLP) technologies are cost effective packaging solutions which are used increasingly. Second level reliability, i.e. mainly the thermo-mechanical reliability during thermal cycling, is a major concern of WLP. To avoid excessive solder straining, solder balls have been replaced by resilient interconnects, which can adopt the main part of the thermal mismatch deformation. One solution combining an increased

Rainer Dudek; Hans Walter; Ralf Doering; Bernd Michel; Thorsten Meyer; Joerg Zapf; Harry Hedler

2006-01-01

406

On-Wafer Testing of Circuits Through 220 GHz.  

National Technical Information Service (NTIS)

We have jointly developed the capability to perform on-wafer s-parameter and noise figure measurements through 220 GHz. S-parameter test sets have been developed covering full waveguide bands of 90-140 GHz (WR-08) and 140-220 GHz (WR-05). The test sets ha...

T. Gaier L. Samoska C. Oleson G. Boll

1999-01-01

407

Error Correction in On-Wafer Harmonic Power Measurements  

Microsoft Academic Search

This paper presents a simple method for correcting errors in on-wafer harmonic power measurements due to non-50 ¿ port impedances and network losses. To correct for losses and mismatches and to calculate the equivalent 50 ¿ power levels at the fundamental and harmonic frequencies, the formulation makes use of vector S-parameter characterization of the test system and the DUT. The

Peter Winson; Lawrence P. Dunleavy; Paul Abernathy

1994-01-01

408

Hermetic wafer bonding based on rapid thermal processing  

Microsoft Academic Search

Hermetic wafer bonding based on rapid thermal processing (RTP) has been demonstrated for the first time. Microcavities encapsulated between glass and silicon substrate have been sealed with aluminum solder by using RTP at 990°C for 2s. Reliability experiments of IPA leak and autoclave accelerated tests show that 100% of survival rate can be achieved. The best encapsulation results are accomplished

Mu Chiao; Liwei Lin

2001-01-01

409

Optical leak detection for wafer level hermeticity testing  

Microsoft Academic Search

Cost reduction in optoelectronic and MEMS packaging is a key issue already today and will become even more important in the future. We developed a novel hermetic packaging technology and an optical leak detector for wafer level assembly and testing, respectively. Silicon caps (HyCap®) for localized hermetic sealing are manufactured using standard MEMS technology. Sensitive optoelectronic or MEMS devices are

Gordon Elger; Lior Shiv; Nika Nikac; Frank Müller; Rainer Liebe; Marcus Grigat

2004-01-01

410

Development of Sample Planning for Wafer Defect Inspection  

Microsoft Academic Search

Sample planning for wafer defect inspection is a critical issue for reducing total cost. It is important to develop a cost-effective sampling plan. In the present study, using three parameters (gain, coefficient of gain variation, and payback period), an optimized sampling plan has been identified by principal component analysis. In particular, a robust sampling plan can be evaluated in terms

T. Nagai; A. Hamaguchi; Y. Yamazaki; M. Yamasaki; Y. Kaga

2005-01-01

411

The leading edge of production wafer probe test technology  

Microsoft Academic Search

Microelectronic wafer and die level testing have undergone significant changes in the past few years. This work's first section describes today's leading edge characteristics for numerous areas of this test technology including the minimum I\\/O pad pitch, advances in contactor technologies, maximum number of l\\/Os probed, maximum number of die tested in parallel, the largest prober and substrates, and the

W. R. Mann; Frederick L. Taber; Philip W. Seitzer; Jerry J. Broz

2004-01-01

412

The Leading Edge of Production Wafer Probe Test Technology  

Microsoft Academic Search

Microelectronic wafer and die level testing have undergone significant changes in the past few years. This paper's first section describes today's leading edge characteristics for numerous areas of this test technology including the minimum I\\/O pad pitch, advances in contactor technologies, maximum number of I\\/Os probed, maximum number of die tested in parallel, the largest prober and substrates, and the

William R. Mann; Frederick L. Taber; Philip W. Seitzer; Jerry J. Broz

2004-01-01

413

Ultra-Gradient Test Cavity for Testing SRF Wafer Samples  

SciTech Connect

A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

2010-11-01

414

Localized induction heating solder bonding for wafer level MEMS packaging  

Microsoft Academic Search

This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was heated using induction heating causing the solder to reflow. The experiment results show that it took less than 1 min to complete the bonding process. In addition, the MEMS devices experienced a temperature of only 110 °C during bonding, thus

Hsueh-An Yang; Mingching Wu; Weileun Fang

2005-01-01

415

Localized induction heating solder bonding for wafer level MEMS packaging  

Microsoft Academic Search

This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. The electroplated magnetic film was heated up using the induction heating, and leaded to solder reflow. It took only several seconds to complete the solder reflow and bonding process. The measurement results showed that the temperature of device region was only 110°C during heating.

Hsueh-An Yang; Mingching Wu; Weileun Fang

2004-01-01

416

Wafer bonding using microwave heating of parylene for MEMS packaging  

Microsoft Academic Search

This paper describes a novel wafer bonding technique using microwave beating of parylene intermediate layers. The bonding is achieved by parylene deposition and thermal lamination using microwave heating. Variable frequency microwave heating provides uniform, selective, and rapid heating for parylene intermediate layers. The advantages of this bonding technique include short bonding time, low bonding temperature, relatively high bonding strength, less

Hong-seok Noh; Kyoung-sik Moon; Andrew Cannon; Peter J. Hesketh; C. P. Wong

2004-01-01

417

Characterization of silicon wafer bonding for Power MEMS applications  

Microsoft Academic Search

This paper reports the investigation of low-temperature silicon wafer fusion bonding for MEMS applications. A bonding process utilizing annealing temperatures between 400 and 1100°C was characterized. The silicon–silicon bonded interface was analyzed by infrared transmission (IT) and transmission electron microscopy (TEM) and the bond toughness was quantified by a four-point bending–delamination technique.

Arturo A. Ayón; Xin Zhang; Kevin T. Turner; Dongwon Choi; Bruno Miller; Steven F. Nagle; S. Mark Spearing

2003-01-01

418

A merged MEMS-CMOS process using silicon wafer bonding  

Microsoft Academic Search

A process for fabricating integrated silicon micromachined sensors is demonstrated. The process uses silicon wafer bonding to create a substrate that can be inserted into an existing IC fabrication line without perturbation of the line. After circuits are completed, micromachining steps are performed to release the silicon membranes and form the sensors. A variety of test structures including MOSFETs, piezoresistive

Lalitha Parameswaran; Charles Hsu; Martin A. Schmidt

1995-01-01

419

Thin film sputtered silicon for silicon wafer bonding applications  

Microsoft Academic Search

Sputtered silicon has been investigated as a low temperature bonding layer for microelectronic applications such as silicide on silicon on insulator, thin film transistors, micromachining and temperature sensitive substrates; sputtered silicon acting as a replacement for polysilicon with a deposition temperature around 600°C. For wafer bonding, a deposited layer must have sub-nanometer roughness, be free from particles and have a

R. E Hurley; H. S Gamble

2003-01-01

420

Modeling and scheduling for semiconductor wafer fabrication systems  

Microsoft Academic Search

Two methods were presented to model the semiconductor wafer fabrication system and an AI based search was introduced for the scheduling. First, resource based Petri net was defined to model the structure of the system so that the net will not expanded rapidly with the process going on. Then, a modeling method which integrated IDEF0 with Petri net was given

Shao Zhifang; Chen Yu

2008-01-01

421

300mm wafer Atomic force probe characterization methodology  

Microsoft Academic Search

The laboratory practice of employing atomic force probing (AFP) using AFP current imaging and Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for identification of front end of line (FEOL) defects in MOSFET devices, especially for silicon on insulator applications has been extensively detailed. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) on bulk silicon wafers and silicon on insulator

Terence Kane

2010-01-01

422

On the scribing and subsequent fracturing of silicon semiconductor wafers  

Microsoft Academic Search

The integrated circuits deposited on silicon wafers are often separated by scribing with a diamond tool followed by bending to produce fracture. Using a commercial scribing tool we find permanent deformation and three types of crack. The median crack which propagates downwards is the objective of the scribing process. Lateral cracks which form, apparently following plastic deformation, may lead to

A. Misra; I. Fininie

1979-01-01

423

An innovative platform for high-throughput high-accuracy lithography using a single wafer stage  

NASA Astrophysics Data System (ADS)

For 32 nm half-pitch node, double patterning is recognized as the most promising technology since some significant obstacles still remain in EUV in terms of technology and cost. This means much higher productivity and overlay performance will be required for lithography tools. This paper shows the technical features of Nikon's new immersion tool, NSR-S620 based on newly developed platform "StreamlignTM" designed for 2nm overlay, 200wph throughput and 2week setup time. The S620 is built basically upon Nikon's Tandem Stage and Local Fill Nozzle technology, but has several additional features. For excellent overlay, laser encoders with short optical path are applied for wafer stage measurement in addition to interferometers. By using this hybrid metrology, the non-linearity of the encoder scale can be easily calibrated, while eliminating the air fluctuation error of interferometer. For high throughput, a method with a new alignment microscope system and a new auto focus mapping, called Stream Alignment is introduced. It makes it possible to reduce the overhead time between the exposures remarkably. The target productivity is 4,000 wafer outs per day. Accuracy is also improved because many more alignment points and a continuous wafer height map without stitching are available. Higher acceleration and faster scan velocity of the stages are also achieved by optimal vibration dynamics design and new control system. The main body, including the projection lens, is isolated by Sky Hook Technology used already on the NSR-SF150 and SF155 steppers, and also the reticle stage is mechanically isolated from the main body. With this new platform, the imaging performance can be maximized.

Shibazaki, Yuichi; Kohno, Hirotaka; Hamatani, Masato

2009-03-01

424

Prediction of back-end process-induced wafer warpage and experimental verification  

Microsoft Academic Search

During the back-end processes of wafer manufacturing, wafer warpage occurs due to the mismatch in thermal expansion coefficients of the various applied materials. Large wafer warpage is one of the root causes leading to process and product failures. Therefore, the ability to predict the back-end process induced wafer warpage is important to achieve an optimal IC design and back-end process.

R. B. R. van Silfhout; W. D. van Driel; Y. Li; G. Q. Zhang; L. J. Ernst

2002-01-01

425

Predicting Wafer-Lot Output Time With a Hybrid FCM-FBPN Approach  

Microsoft Academic Search

Output-time prediction is a critical task to a wafer fab. To further enhance the accuracy of wafer-lot output-time prediction, the concept of input classification is applied to Chen's fuzzy backpropagation network (FBPN) approach in this paper by preclassifying wafer lots with the fuzzy c-means (FCM) classifier before predicting the output times. In this way, similar wafer lots are clustered in

Toly Chen

2007-01-01

426

Fabrication of SOI wafers with buried cavities using silicon fusion bonding and electrochemical etchback  

Microsoft Academic Search

This paper describes a new technique for batch fabrication of silicon-on-insulator (SOI) wafers for microelectromechanical systems (MEMS) applications by silicon wafer bonding techniques. The process permits the inclusion of buried cavities in the SOI wafers, providing a useful tool for sensor and actuator fabrication using the resulting wafers. A low-cost electrochemical etchback step is used to define accurately the thickness

J. Mark Noworolski; Erno Klaassen; John Logan; Kurt Petersen; Nadim I. Maluf

1996-01-01

427

Toward perfect on-wafer pattern placement: stitched overlay exposure tool characterization  

NASA Astrophysics Data System (ADS)

Continued lithographic pattern density scaling depends on aggressive overlay error reduction.1,2 Double patterning processes planned for the 22nm node require overlay tolerances below 5 nm; at which point even sub-nanometer contributions must be considered. In this paper we highlight the need to characterize and control the single-layer matching among the three pattern placement mechanisms intrinsic to step&scan exposure - optical imaging, mask-to- wafer scanning, and field-to-field stepping. Without stable and near-perfect pattern placement on each layer, nanometer-scale layer-to-layer overlay tolerance is not likely to be achieved. Our approach to understanding onwafer pattern placement is based on the well-known technique of stitched field overlay. We analyze dense sampling around the field perimeter to partition the systematic contributors to pattern placement error on representative dry and immersion exposure tools.

Ausschnitt, Christopher P.; Brunner, Timothy A.; Felix, Nelson M.; Minghetti, Blandine

2010-03-01

428

Advanced FTIR technology for the chemical characterization of product wafers  

NASA Astrophysics Data System (ADS)

Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers. .

Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

2001-01-01

429

Impact of Wafer Geometry and Thermal History on Pressure and von Mises Stress Non-Uniformity During Chemical Mechanical Planarization  

NASA Astrophysics Data System (ADS)

This study employs pressure measurements and von Mises stress simulations across surfaces of wafers in order to examine the effect of wafer-ring gap size, extent and direction of wafer bow, and the effect of thermal history on within wafer pressure non-uniformity (WWPNU). WWPNU analysis for nominally flat, thermally untreated, wafers indicates that the wafer’s ‘central zone’ has average pressure profiles, which remain constant, while the ‘edge region’ exhibits a sharp pressure peak. Dependence of wafer-ring gap size for the ‘central zone’ of bowed and thermally untreated wafers on WWPNU indicates that pressure profiles at larger gap sizes remain constant regardless of wafer shape. The ‘edge zone’ shows that the extent and direction of wafer bow has no effect on average pressure and variability. The effect of wafer-ring gap size on WWPNU for thermally treated wafers indicates that heat treatment reduces, or masks, the effect of gap size on average pressure in the ‘central zone’ of the wafer. A major effect of thermal treatment is the increase in overall pressure variability at the ‘edge zone’ of wafers.

Sorooshian, J.; Philipossian, A.; Goldstein, M.; Beaudoin, S.; Huber, W.

2003-10-01

430

Al–Cu Pattern Wafer Study on Metal Corrosion Due to Chloride Ion Contaminants  

Microsoft Academic Search

Chloride ions in the cleanroom environment induce metal corrosion of integrated circuits, and cause wafer scrap events. In this paper, pattern wafers were designed to monitor critical concentration which leads to metal corrosion effects in a simulated airborne molecular contamination (AMC) environment. The simulated contamination environment was established by placing different numbers of preventive maintenance (PM) wipers in wafer pods

Bi-Jun Wu; Hsunling Bai; I-Kai Lin; S. S. Liu

2010-01-01

431

The effect of patterns on thermal stress during rapid thermal processing of silicon wafers  

Microsoft Academic Search

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport

Jeffrey P. Hebb; Klavs F. Jensen

1998-01-01

432

Photoconductivity characterization of silicon wafer mirror-polishing subsurface damage related to gate oxide integrity  

Microsoft Academic Search

The correlation between gate oxide integrity, photoconductivity amplitude and surface microroughness was systematically measured with 9 SC1 cleanings to remove residual subsurface damage induced by mirror polishing on the subsurface of silicon wafers. The same measurements were also carried out for as-epitaxial wafers as a comparison. Measured gate oxide integrity and photoconductivity amplitude in polished wafers increased with increase in

Y. Ogita; K Kobayashi; H Daio

2000-01-01

433

Transfer of metal MEMS packages using a wafer-level solder transfer technique  

Microsoft Academic Search

This paper presents a modular, low profile, wafer-level encapsulation technology for microelectromechanical systems (MEMS) packaging. Electroplated caps are formed on top of a solder transfer layer previously deposited on a carrier wafer, then simultaneously transferred and bonded to a device wafer by a novel solder transfer method and transient liquid phase (TLP) bonding technology. The solder transfer method is enabled

Warren C. Welch; Junseok Chae; Khalil Najafi

2005-01-01

434

Transfer of metal MEMS packages using a wafer-level solder sacrificial layer  

Microsoft Academic Search

This paper presents a modular, low profile, wafer-level encapsulation technology for 0-level MEMS packaging. Electroplated caps are formed on a carrier wafer then simultaneously transferred and bonded to a device wafer by a novel solder transfer method and transient liquid phase (TLP) bonding technology. The solder transfer method is enabled by the dewetting of the solder transfer layer from the

Warren C Welch; Khalil Najafi

2005-01-01

435

Wafer Direct Bonding: From Advanced Substrate Engineering to Future Applications in Micro\\/Nanoelectronics  

Microsoft Academic Search

Wafer direct bonding refers to the process of adhesion of two flat mirror-polished wafers without using any intermediate gluing layers in ambient air or vacuum at room temperature. The adhesion of the two wafers occurs due to attractive long range van der Waals or hydrogen bonding forces. At room temperature the bonding energy of the interface is low and higher

Silke H. Christiansen; Rajendra Singh; Ulrich Gosele

2006-01-01

436

Fabrication technology for wafer through-hole interconnections and three-dimensional stacks of chips and wafers  

Microsoft Academic Search

This paper presents an approach to build electronic systems with very high chip count. Instead of packing the chips laterally as it is done in multichip-modules (MCMs), individual dies, blocks of dies and ultimately entire wafers are stacked on top of each other. Electrical interconnection is accomplished using plated through-hole contacts through the silicon substrate. Proper thermal management is obtained

S. Linder; H. Baltes; F. Gnaedinger; E. Doering

1994-01-01

437

Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers for PV Cells  

SciTech Connect

As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay ({mu}PCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

Guthrey, H.; Gorman, B.; Al-Jassim, M.

2011-01-01

438

Updated meta-analysis of randomized controlled trials comparing conventional excisional haemorrhoidectomy with LigaSure for haemorrhoids  

Microsoft Academic Search

Background  To compare the surgical outcome of haemorrhoidectomy performed using LigaSure bipolar diathermy with conventional haemorrhoidectomy.\\u000a \\u000a \\u000a \\u000a Methods  Only randomized and alternate allocated studies were included from the major electronic databases using the search terms “ligasure”\\u000a and “haemorrhoids” Duration of operation, blood loss during operation, postoperative pain score, wound healing, in-hospital\\u000a stay, time to return to normal activities and complications were assessed.\\u000a \\u000a \\u000a \\u000a Results  The

M. Y. Mastakov; P. G. Buettner; Y.-H. Ho

2008-01-01

439

Height inspection of wafer bumps without explicit 3D reconstruction  

NASA Astrophysics Data System (ADS)

The shrunk dimension of electronic devices leads to more stringent requirement on process control and quality assurance of their fabrication. For instance, direct die-to-die bonding requires placement of solder bumps not on PCB but on the wafer itself. Such wafer solder bumps, which are much miniaturized from the counterparts on PCB, still need to have their heights meet the specification, or else the electrical connection could be compromised, or the dies be crushed, or even the manufacturing equipments be damaged. Yet the tiny size, typically tens of microns in diameter, and the textureless and mirror nature of the bumps pose great challenge to the 3D inspection process. This paper addresses how a large number of such wafer bumps could have their heights massively checked against the specification. We assume ball bumps in this work. We propose a novel inspection measure about the collection of bump heights that possesses these advantages: (1) it is sensitive to global and local disturbances to the bump heights, thus serving the bump height inspection purpose; (2) it is invariant to how individual bumps are locally displaced against one another on the substrate surface, thus enduring 2D displacement error in soldering the bumps onto the wafer substrate; and (3) it is largely invariant to how the wafer itself is globally positioned relative to the imaging system, thus having tolerance to repeatability error in wafer placement. This measure makes use of the mirror nature of the bumps, which used to cause difficulty in traditional inspection methods, to capture images of two planes. One contains the bump peaks and the other corresponds to the substrate. With the homography matrices of these two planes and fundamental matrix of the camera, we synthesize a matrix called Biplanar Disparity Matrix. This matrix can summarize the bumps' heights in a fast and direct way without going through explicit 3D reconstruction. We also present a design of the imaging and illumination setup that allows the measure to be revealed in two images, and how the inspection measure could be estimated from the image data so acquired. Both synthetic and real data experimental results are shown to illustrate the effectiveness of the proposed system.

Dong, Mei; Chung, Ronald; Zhao, Yang; Lam, Edmund Y.

2006-01-01

440

The Study of Deep Lithography and Moulding Process of LIGA Technique  

NASA Astrophysics Data System (ADS)

The knowledge of the development behavior, especially the development rate, is of primary importance for the study of deep x-ray lithography in LIGA technique. In the first part of this paper, we have measured the development rates of crosslinked PMMA foils irradiated in NSRL covering a wide dose range (bottom dose in the range:2.5-8.0 kJ/cm3). After the exposure, we use a so-called period-development method (to dip development in GG-developer for 20 minutes and clean in rinse solution for 40 minutes as a development period). For processing the experiment data, we get the KD? model to describe our PMMA/GG-developer system. The aim of this work is to find out a stable experiment condition for deep X-ray lithography and development. The result shows that in small amount of dose (bottom dose range: 2.5-4 kJ/cm3), this model is very stable. While in large amount of dose (bottom dose range: 5-8kJ/cm3), the model becomes very sensitive and even unavailable. To verify the conclusion validity, the fixed dose range (bottom dose range: 3.5-4 kJ/cm3) is applied on PMMA microstructures. And the result shows an effective development process. In the following procedure, mold inserts can be produced by micro-electroforming and plastic replicas can be mass produced by hot embossing. To emboss high-aspect-ratio microstructures, the deformation of microstructures usually occurs due to the demolding forces between the sidewall of mold inserts and the thermoplastic (PMMA). To minimize the friction force the optimized experiment has been performed using Ni-PTFE compound material mold inserts. Typical defects like pull-up and damaged edges can be greatly reduced.

Guo, Yuhua; Liu, Gang; Kan, Ya; Tian, Yangchao

2007-01-01

441

A photo-sensor on thin polysilicon membrane embedded in wafer level package LED  

NASA Astrophysics Data System (ADS)

A wafer level packaging LED with photo-sensor which is fabricated on thin poly-silicon membrane located on the corner of silicon cavity is presented in this paper. The wafer substrate was fabricated with (100) orientation silicon wafer and a cavity was etched on the top of the wafer with wet chemical anisotropic etching process for mounting a LED chip. A thin polysilicon membrane was fabricated on the corner of the cavity and a MSM (Metal Semiconductor Metal) type photo-sensor was fabricated on the thin polysilicon membrane. The photo-sensor fabrication and LED packaging were completed on wafer level. The embedded photo-sensor in a wafer level packaging LED is designed to measure light intensity of a LED. The membrane structure photo-sensor can sense the light of the mounted LED directly, so it can measure accurate light intensity of the wafer level packing LED.

Kim, Jin Kwan; Lee, Hee Chul

2012-05-01

442

Nanoindentation tests on diamond-machined silicon wafers  

NASA Astrophysics Data System (ADS)

Nanoindentation tests were performed on ultraprecision diamond-turned silicon wafers and the results were compared with those of pristine silicon wafers. Remarkable differences were found between the two kinds of test results in terms of load-displacement characteristics and indent topologies. The machining-induced amorphous layer was found to have significantly higher microplasticity and lower hardness than pristine silicon. When machining silicon in the ductile mode, we are in essence always machining amorphous silicon left behind by the preceding tool pass; thus, it is the amorphous phase that dominates the machining performance. This work indicated the feasibility of detecting the presence and the mechanical properties of the machining-induced amorphous layers by nanoindentation.

Yan, Jiwang; Takahashi, Hirokazu; Tamaki, Jun'ichi; Gai, Xiaohui; Harada, Hirofumi; Patten, John

2005-05-01

443

Investigation of carrier transport through silicon wafers by photocurrent measurements  

NASA Astrophysics Data System (ADS)

A model for the minority-carrier diffusion processes which are basic to the operation of light addressable potentiometric sensor (LAPS) devices is demonstrated. Photocurrent measurements as a function of frequency provide an alternative method of measuring bulk minority-carrier lifetime, whose main advantage is to less sensitive to surface recombination. The dependence of the ac photocurrent/frequency curves for the same wafer at different wafer thicknesses was evaluated to verify the consistency of the theoretical model used. The obtained values from the semiconductor bulk and recombination velocity with the photocurrent measurement were compared with those obtained with a noncontact photoconductive decay (PCD) technique. The fundamental dependency of the ac photocurrent amplitude in LAPS devices was characterized on various parameters, namely modulation frequency, semiconductor substrate thickness, and the choice of the side of the device which is illuminated.

Bousse, Luc; Mostarshed, Shahriar; Hafeman, Dean; Sartore, Marco; Adami, Manuela; Nicolini, Claudio

1994-04-01

444

Cartilage-retaining Wafer Resection Osteotomy of the Distal Ulna  

PubMed Central

Ulnar-sided wrist pain resulting from ulnar impaction is common. We describe a new cartilage-retaining wafer resection osteotomy designed to keep the cartilage intact and decompress the ulnocarpal articulation without requiring internal fixation. We retrospectively reviewed seven patients with ulnar impaction who had the procedure. The minimum followup was 14 months (mean, 30 months; range, 14–38 months). The mean change in ulnar variance was ?1.29 mm. Patients showed radiographic healing by a mean of 11 weeks. Our preliminary results suggest the cartilage-retaining wafer resection osteotomy may be an effective way to unload the ulnocarpal joint without requiring internal fixation or destruction of the distal ulna cartilage. Level of Evidence: Level IV, therapeutic study. See the Guidelines for Authors for a complete description of levels of evidence.

Macksoud, Wadih S.

2008-01-01

445

JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES  

SciTech Connect

There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

Montoya, Angela C.; Maji, Arup K. [University of New Mexico, Department of Civil Engineering, Albuquerque, New Mexico, 87131 (United States)

2010-02-22

446

Metal adsorbent for alkaline etching aqua solutions of Si wafer  

NASA Astrophysics Data System (ADS)

High performance adsorbent is expected to be synthesized for the removal of Ni and Cu ions from strong alkaline solution used in the surface etching process of Si wafer. Fibrous adsorbent was synthesized by radiation-induce emulsion graft polymerization onto polyethylene nonwoven fabric and subsequent amination. The reaction condition was optimized using 30 L reaction vessel and nonwoven fabric, 0.3 m width and 18 m long. The resulting fibrous adsorbent was evaluated by 48 wt% NaOH and KOH contaminated with Ni and Cu ions, respectively. The concentration levels of Ni and Cu ions was reduced to less than 1 ?g/kg (ppb) at the flow rate of 10 h-1 in space velocity. The life of adsorbent was 30 times higher than that of the commercialized resin. This novel adsorbent was commercialized as METOLATE® since the ability of adsorption is remarkably higher than that of commercial resin used practically in Si wafer processing.

Tamada, Masao; Ueki, Yuji; Seko, Noriaki; Takeda, Toshihide; Kawano, Shin-ichi

2012-08-01

447

Materials integration for high-performance photovoltaics by wafer bonding  

NASA Astrophysics Data System (ADS)

The fundamental efficiency limit for state of the art triple-junction photovoltaic devices is being approached. By allowing integration of non-lattice-matched materials in monolithic structures, wafer bonding enables novel photovoltaic devices that have a greater number of subcells to improve the discretization of the solar spectrum, thus extending the efficiency limit of the devices. Additionally, wafer bonding enables the integration of non-lattice-matched materials with foreign substrates to confer desirable properties associated with the handle substrate on the solar cell structure, such as reduced mass, increased thermal conductivity, and improved mechanical toughness. This thesis outlines process development and characterization of wafer bonding integration technologies essential for transferring conventional triple-junction solar cell designs to potentially lower cost Ge/Si epitaxial templates. These epitaxial templates consist of a thin film of single-crystal Ge on a Si handle substrate. Additionally, a novel four-junction solar cell design consisting of non-lattice matched subcells of GaInP, GaAs, InGaAsP, and InGaAs based on InP/Si wafer-bonded epitaxial templates is proposed and InP/Si template fabrication and characterization is pursued. In this thesis the detailed-balance theory of the thermodynamic limiting performance of solar cell efficiency is applied to several device designs enabled by wafer bonding and layer exfoliation. The application of the detailed-balance theory to the novel four-junction cell described above shows that operating under 100 suns at 300 K a maximum efficiency of 54.9% is achievable with subcell bandgaps of 1.90, 1.42, 1.02, and 0.60 eV, a material combination achievable by integrating two wide-bandgap subcells lattice matched to GaAs and two narrow-bandgap subcells lattice matched to InP. Wafer bonding and layer transfer processes with sufficient quality to enable subsequent material characterization are demonstrated for both Ge/Si and InP/Si structures. The H-induced exfoliation process in each of these materials is studied using TEM, AFM, and FTIR to elucidate the chemical states of hydrogen leading to exfoliation. Additionally, the electrical properties of wafer-bonded interfaces between bulk-Ge/Si and bulk-InP/Si structures are show Ohmic, low-resistance electrical contact. Further studies of p-p isotype heterojunctions in Ge/Si indicate that significant conduction paths exist through defects at the bonded interface. The first known instance of epitaxy of III-V compound semiconductors on wafer-bonded Ge/Si epitaxial templates is demonstrated. Additionally InGaAs is grown on InP/Si templates that have been improved by removal of damage induced by the ion implantation and exfoliation processes.

Zahler, James Michael

448

Self-assembly of Epitaxial Monolayers for Vacuum Wafer Bonding  

Microsoft Academic Search

Self-assembled epitaxial metal monolayers can be used for hetero-integration of mismatched semiconductors, leading to simultaneously low interfacial resistance and high optical transparency. Lattice-mismatched wafers of Si(100) and Si(111) were bonded at room temperature in situ after vacuum deposition of a single atomic layer of Ag on them. The interfacial resistance was measured to be 3.9x 10-4 ohm. cm^ 2 and

Igor Altfeder; Biqin Huang; Ian Appelbaum; Barry Walker

2007-01-01

449

On-wafer calibration using space-conservative (SOLT) standards  

Microsoft Academic Search

In this paper the accuracy of on-wafer calibration using space-conservative (SOLT) standards is evaluated. The calibration approach relies on measurement-based standard definitions. Results are presented using CPW standards with 50 and 300 micron offsets, over the range from .045-65 GHz. In comparing to a multi-line TRL, the magnitude of the difference between the S-parameters is less than 0.05 up to

M. Imparato; T. Weller; L. Dunleavy

1999-01-01

450

The measurement developing of wafer level MEMS microphone  

Microsoft Academic Search

This paper investigates about characteristic measurement methods and experimental results for micro-capacitance and electro-acoustics of wafer level MEMS microphone. And this paper also studies packaging and measurement for the microphone product to verify yield of semi-finished products from the measurement methods to save cost of the production. The repeatability of the micro-capacitance measurement system is high, and construction of direct

Hui-Chuan Lu; Wei-Liang Chan; Hsui-Li Lee; Yu-Jen Fang; Chieh-Ling Hsiao; Chih-Hung Wang; Peter Chang; Chin-Ching Huang; Ming-Te Tu

2007-01-01

451

The Measurement Developing of Wafer Level MEMS Microphone  

Microsoft Academic Search

This paper investigates about characteristic measurement methods and experimental results for micro-capacitance and electro-acoustics of wafer level MEMS microphone. And this paper also studies packaging and measurement for the microphone product to verify yield of semi-finished products from the measurement methods to save cost of the production. The repeatability of the micro-capacitance measurement system is high, and construction of direct

Hui-Chuan Lu; Wei-Liang Chan; Hsui-Li Lee; Yu-Jen Fang; Chieh-Ling Hsiao; Chih-Hung Wang; Peter Chang; Chin-Ching Huang; Ming-Te Tu

2009-01-01

452

Study of polishing of HgCdTe wafers  

Microsoft Academic Search

Wafer thinning is a key process in the fabrication of bulk HgCdTe photoconductive detectors. The currently used method in SITP is chemo-mechanical polishing combined with a following bromine-ethanol etching, which leaves a rough and non-stoichiometric composition surface. The thickness of damaged layer caused by chemo-mechanical polishing might be several hundred angstroms, so the process of bromine-ethanol etching after the chemo-mechanical

Li-Yao Zhang; Hui Qiao; Jin-Tong Xu; Xiang-Yang Li

2011-01-01

453

Performance limiting micropipe defects in silicon carbide wafers  

Microsoft Academic Search

Reports on the characteristics of a major defect in mass-produced silicon carbide wafers which severely limits the performance of silicon carbide power devices. Micropipe defects originating in 4H- and 6H-SiC substrates were found to cause pre-avalanche reverse-bias point failures in most epitaxially-grown pn junction devices of 1 mm2 or larger in area. Until such defects are significantly reduced from their

Philip G. Neudeck; Anthony J. Powell

1994-01-01

454

Cool Plasma Activated Surface in Silicon Wafer Direct Bonding Technology  

Microsoft Academic Search

A novel cool plasma surface activation method has been developed for high quality SOI\\/SDB (Silicon wafer Direct Bonding) preparation. The activation effectiveness of different plasma gases, espetially of O2 plsma gases were investigated. The measurements of H. V-PMOS and L.V.-NMOS devices made on the SOI\\/SDB and on a bulk Silicon indicate that ratios of electron and hole mobility of SOI

G.-L. Sun; J. Zhan; Q.-Y. Tong; S.-J. Xie; Y.-M. Cai; S.-J. Lu

1988-01-01

455

Silicon-to-silicon wafer bonding using evaporated glass  

Microsoft Academic Search

Anodic bonding of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 °C to 450 °C. The composition of the deposited glass is enriched in sodium as compared to the target material. The roughness of the as-deposited films was below 5 run and was found to be

Steen Weichel; Roger de Reus; Michael Lindahl

1998-01-01

456

Influence of scribe lanes on wafer potentials and charging damage  

Microsoft Academic Search

Experimental results show that scribe lane structures can exert a significant influence on surface-substrate potentials and J-V characteristics measured on a wafer in ion-implant processes. This suggests that scribe lane structures used for process control in IC manufacturing, as well as the internal layout of the product itself, may exert significant influence on the surface-to-substrate potentials observed within a die

Wes Lukaszek

2000-01-01

457

Three-dimensional shared memory fabricated using wafer stacking technology  

Microsoft Academic Search

We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the

K. W. Lee; T. Nakamura; T. Ono; Y. Yamada; T. Mizukusa; H. Hashimoto; K. T. Park; H. Kurino; M. Koyanagi

2000-01-01

458

Surface micromachined tunable resonant cavity LED using wafer bonding  

Microsoft Academic Search

Surface micromachining and wafer bonding techniques have been integrated to fabricate a dual-use resonant cavity tunable LED\\/photodetector operating at 1.5 micrometers . The device has a tuning range of 75 nm, and a spectral linewidth of 4 nm, with an extinction ratio of greater than 20 dB throughout the tuning range. The device has potential applications in WDM networks and

Gina L. Christenson; Alex T. Tran; Zuhua Zhu; Yu-Hwa Lo; Minghwei Hong; J. P. Mannaerts; Rajaram J. Bhat

1997-01-01

459

Reaching a CD uniformity of below 3 nm for 300 mm post-etch wafers by adjusting the CD distribution of ADI wafers  

NASA Astrophysics Data System (ADS)

Obtaining good post-etching CD uniformity is getting more and more important in advanced processes such as 90 nm, 65 nm, and even 45nm for 300 mm wafers. But process noise greatly impacts the CD uniformity, especially etching bias and metrology noise. To achieve a CD uniformity of below 3 nm for 300 mm post-etch wafers, the metrology noise and process noise must be reduced and compensated for. In this paper, we demonstrate spectroscopic ellipsometry CD with the advantages of high stability and high accuracy to get CD information precisely, and high sensitivity to monitor PEB temperature and exposure energy fine variation in order to compensate for the etching bias. This study focuses on the feasibility of minimizing the CD uniformity of post-etch wafers by ADI CD compensation for a 300 mm leading-edge fab. Because the CD uniformity of after-development inspection (ADI) wafers from a leading-edge lithographic tool could be in the range of only 3 nm, it is very challenging to reveal the true CD signature of an ADI wafer using a metrology tool. A spectroscopic ellipsometry based metrology tool, SpectraCD, was used in this study. In order to make sure the CD signatures reported by SpectraCD reveal the true behavior of a lithographic tool, the well-published Total Test Repeatability (TTR) test was adopted. In comparison with 3 nm CD uniformity, a 0.2 nm TTR is accurate enough for this study. In addition, from more than 100 wafers produced within a week, the CD signature of ADI wafers is very stable on wafer-to-wafer and lot-to-lot bases. Basically, all the ADI wafers produced from a single post-exposure-bake plate of an exposure tool within a week show very similar CD signatures. The feasibility of reaching a CD uniformity of 3 nm for post-etch wafers will be demonstrated in this study.

Sun, Jie-Wei; Huang, Yong-Fa; Lee, Sho-Shen; Yu, Chun-Chi; Lin, Benjamin S.; Fu, Steven; Slessor, Mike

2005-05-01

460

Method for making circular tubular channels with two silicon wafers  

DOEpatents

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

Yu, Conrad M. (Antioch, CA); Hui, Wing C. (Campbell, CA)

1996-01-01

461

Wafer-level membrane transfer bonding of polycrystalline silicon bolometers for use in infrared focal plane arrays  

Microsoft Academic Search

In this paper we present a new, innovative technology for fabrication and integration of free-hanging transducers. The transducer structures are processed on the original substrate wafer (sacrificial device wafer) and then transferred to a new substrate wafer (target wafer). The technology consists only of low-temperature processes, thus it is compatible with integrated circuits. We have applied the new membrane transfer

Frank Niklaus; Edvard Kälvesten; Göran Stemme

2001-01-01

462

Metrology study of high precision mm parts made by the deep x-ray lithography (LIGA) technique  

NASA Astrophysics Data System (ADS)

Microcomponents are increasingly applied in industrial products, e.g. smallest gears, springs or the watch industry. Apart from their small dimensions, such components are characterized by a high contour accuracy. Industry requires the tolerances to be in the µm range. Measurement of lateral dimensions in the mm range with submicrometer accuracy and precision, however, results in high requirements on measurement technology. The relevance of this problem is illustrated by the fact that the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) has launched the Collaborative Research Center 1159 on 'New Strategies of Measurement and Inspection for the Production of Microsystems and Nanostructures'. The Institut für Mikrostrukturtechnik, Karlsruhe (Institute of Microstructure Technology, Karlsruhe), produces microstructures by means of the LIG(A) technique (German acronym for lithography, electrodeposition, molding). Presently, a coordinate measurement machine equipped with an optical fiber probe to measure these microstructures is being tested. This paper will particularly focus on the precision and accuracy of the machine. The rules of measurement system analysis will be applied for this purpose. Following the elimination of the systematic error, reproducibility of deep-etch x-ray lithography will be highlighted using the LIGA production of gold gears as an example.

Mäder, Olaf; Meyer, Pascal; Saile, Volker; Schulz, Joachim

2009-02-01

463

Reactor scaling for large area plasma processing  

NASA Astrophysics Data System (ADS)

Migration to 300 mm wafer size is a topic of active research and development in semiconductor processing. Plasma process tool development for 300 mm wafers faces significant technical challanges, particularly from the point of view of process uniformity across the wafer. Process and reactor modeling can play a complementary role in tool design and development. Many of the models in the literature have focused thus far on discharge physics aspects of the modeling excercise. In this work, we also focus on gas flow and other reactor issues. The model involves two dimensional solution to compressible gas flow, energy and multispecies conservation equations. A simplified chemical scheme for the chlorine etching of silicon is considered. Simulation results are presented for various reactor geometrical parameters, pressures, and flow rates. Scaling to 300 mm wafer is discussed.

Meyyappan, M.

1996-10-01

464

Comparison of measurement methods for microsystem components: application to microstructures made by the deep x-ray lithography process (x-ray LIGA)  

Microsoft Academic Search

The LIGA (a German acronym for lithography, electroplating and molding) process using highly parallel x-rays permits the production of a microstructure with still unique characteristics: high aspect ratio, high accuracy, high perpendicularity and lower roughness of the side wall. From a marketing point of view, this qualitative description might suffice to attract users to the technology. Regarding widespread commercialization and

Pascal Meyer; Olaf Mäder; Volker Saile; Joachim Schulz

2009-01-01

465

A novel technique for the fabrication of herringbone grooves in a dynamic thrust bearing combining UV-LIGA with electro-discharge machining  

Microsoft Academic Search

This paper presents a novel technique for the fabrication of herringbone grooves in a dynamic thrust bearing by combining both UV-LIGA (the German words for lithography, electroplating, and molding) and electro-discharge machining (EDM) processes. A negative photoresist is used to fabricate an electroforming mold from which a microelectrode for the EDM process is electroformed. The last step is to employ

J. S. Kuo; K. T. Chiu; S. W. Hsu; P. H. Chen; Y. S. Liao

2006-01-01

466

Wafer bonding of 50 mm diameter mirror substrate to AlGaInP light-emitting diode wafer  

Microsoft Academic Search

The feasibility of 50-mm wafer bonding AlGaInP LED with mirror substrate has been demonstrated using a bonding process under a low temperature and short thermal treatment duration. Si substrate with good thermal conductivity is used as the mirror substrate to prevent LED device from joule heating. The performance of the mirror substrate AlGaInP LED is much better than that of

C. H. Seieh; R. H. Horng; M. F. Huang; D. S. Wuu; W. C. Peng; S. J. Tsai; J. S. Liu

2000-01-01

467

Gate-Oxide-Integrity Characteristics of Vacancy-rich Wafer Compared with Crystal-Originated-Pits-free Wafer as a Function of Oxide Thickness  

NASA Astrophysics Data System (ADS)

The dielectric breakdown of oxides with various thickness between 5-70 nm on Czochralski (CZ)-grown silicon wafer had been investigated. To observe the effects of crystal-originated-particle (COP), vacancy-rich wafers and COP-free wafers were compared. In breakdown voltage (BV) measurement, breakdown fractions of vacancy-rich wafers were increased with the increase of oxide thickness (tOX) and showed a maximum value at the tOX range of 10-20 nm. On the other hand, COP-free wafers showed few breakdowns over all the range of tOX. Furthermore, time dependent dielectric breakdown (TDDB) of the vacancy-rich wafers showed higher extrinsic breakdowns than that of the COP-free wafers in the tOX below 20 nm. For the intrinsic breakdown, two groups showed the same charge-to-breakdown (QBD) along the strength of injection current over all the range of tOX. Especially, only in case of vacancy-rich wafer, abnormal increase of current, i.e., hump phenomena, was observed in the range of electric field below the Fowler-Nordheim (F-N) tunneling.

Lee, Ki-Sang; Cho, Won-Ju; Lee, Bo-Young; Yoo, Hak-Do

2000-07-01

468

Thermomechanical Reliability Study of Benzocyclobutene Film in Wafer-Level Chip-Size Package  

NASA Astrophysics Data System (ADS)

A new wafer-level chip-scale package process for high-performance, low-cost packaging has been developed based on passivation with low dielectric constant. This process is simpler and shorter when using permanent photosensitive benzocyclobutene (BCB) compared with the conventional process. However, cracks nucleating on the BCB cause serious reliability problems. The major reasons for cracking of the BCB layer seem to be both thermal stress and a shortage of BCB cross-linking agent (cyclobutene). The stress was reduced by optimizing the thickness of the BCB layer and the underlying stress buffer layer. The BCB cracking resistance was improved by creating more cross-linking agent at the final curing process through modification of the photolithography processes.

Lee, K.-O.

2012-04-01

469

Optical pressure sensor head fabrication using ultrathin silicon wafer anodic bonding  

NASA Astrophysics Data System (ADS)

A technology for fabricating fiber optically interrogated pressure sensors is described. This technology is based on anodic bonding of ultra-thin silicon wafers to patterned, micro-machined glass wafers, providing low-cost fabrication of optical pressure sensor heads that operate with reproducible technical characteristics in various dynamic ranges. Pressure sensors using 10, 20 and 50 micron thick silicon wafers for membranes have been fabricated on 10 cm diameter, 500-micron thick, Pyrex glass wafers. The glass wafers have been micro-machined using ultrasonic drilling in order to form cavities, optical fiber feedthrough holes and vent holes. One of the main challenges of the manufacturing process is the handling of the ultra-thin silicon wafers. Being extremely flexible, the thin silicon wafers cannot be cleaned, oxidized, or dried in the same way as normal since wafers with a thickness of the order of 400 microns. Specific handling techniques have been developed in order to achieve reproducible cleaning and oxidation processes. The anodic bonding was performed using an Electronic Visions EV501S bonder. The wafers were heated at 420 degrees C and a voltage of 1200 volts was applied in vacuum of 10-5 Torr. The bonded wafer stack was then fixed in a wax and diced. The resulting chips have been used to fabricate operating pressure sensors.

Beggans, Michael H.; Ivanov, Dentcho I.; Fu, Steven G.; Digges, Thomas G.; Farmer, Kenneth R.

1999-03-01

470

Wafer-level sandwiched packaging for high-yield fabrication of high-performance mems inertial sensors  

Microsoft Academic Search

A wafer-level sandwiched packaging technology is developed for micromechanical sensors such as inertial sensors, which comprise movable parts, e.g. spring-mass structures. Via a thin polymer intermediate layer of benzocyclobuene (BCB), a pre-micromachined silicon cap wafer is aligned bonded with the sensor-chip wafer. Prior to the BCB bonding, the sensor-chip wafer was formed by anodic bonding a Pyrex-7740 glass wafer to

Kun Zhang; Wei Jiang; Xinxin Li

2008-01-01

471

Science and technology of plasma activated direct wafer bonding  

NASA Astrophysics Data System (ADS)

This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.