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Sample records for wafer scale liga

  1. The influence of wafer elasticity on acoustic waves during LIGA development.

    SciTech Connect

    Ting, Aili

    2003-12-01

    During acoustically stimulated LIGA development, a wafer receives sound waves from both sides at a wide variety of incidence angles that vary in time depending on the orientation of the wafer relative to the multiple transducers that are typically actuated in a periodic sequence. It is important to understand the influence of these variables on the transmission of energy through the wafer as well as the induced motion of the wafer itself because these processes impact the induced acoustic streaming of the fluid within features, the mechanism presently thought responsible for enhanced development of LIGA features. In the present work, the impact of wafer elasticity on LIGA development is investigated. Transmission waves, wafer bending waves, and the related concepts such as critical bending frequency, mechanical impedance, coincidence, and resonance, are discussed. Supercritical-frequency incident waves induce supersonic bending waves in the wafer. Incident wave energy is channeled into three components, transmitted, reflected and energy deposited to the wafer, depending on the wafer material, thickness and wave incidence angle. Results show at normal incidence for a 1-mm PMMA wafer, about 47% of the wave energy is deposited in the wafer. The wafer gains almost half of the incident energy, a result that agrees well with the Bankert et a1 measurements. In LIGA development, transmitted waves may sometimes produce strong acoustic motion of the developer on the wafer backside, especially for the so-called coincidence case in which almost all incident wave energy transfers to the backside. Wafer bending waves cause wafer oscillation at high frequency, promoting the development process, but features shaking may weaken their attachments to the substrate. Resonance is not likely for the entire wafer, but may occur in short and wide wafer feature columns, which are least likely to break away from the substrate, perhaps resulting in good agitation of the fluid in adjacent feature cavities.

  2. Wafer Post-Processing for a Reconfigurable Wafer-Scale Circuit Moufid Radji1

    E-print Network

    Hamoui, Anas

    Wafer Post-Processing for a Reconfigurable Wafer-Scale Circuit Board Moufid Radji1 , Ahmed Outaouais (3) Département d'Informatique, Université du Quebec à Montréal Abstract The WaferBoardTM rapid, performance and reliability constraints. At the core of WaferBoardTM is the WaferICTM , a wafer

  3. LIGA Scanner Control Software

    Energy Science and Technology Software Center (ESTSC)

    1999-02-01

    The LIGA Scanner Software is a graphical user interface package that facilitates controlling the scanning operation of x-rays from a synchrotron and sample manipulation for making LIGA parts. The process requires scanning of the LIGA mask and the PMMA resist through a stationary x-ray beam to provide an evenly distributed x-ray exposure over the wafer. This software package has been written specifically to interface with Aerotech motor controllers.

  4. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  5. Parallel Assembly of LIGA Components

    SciTech Connect

    Christenson, T.R.; Feddema, J.T.

    1999-03-04

    In this paper, a prototype robotic workcell for the parallel assembly of LIGA components is described. A Cartesian robot is used to press 386 and 485 micron diameter pins into a LIGA substrate and then place a 3-inch diameter wafer with LIGA gears onto the pins. Upward and downward looking microscopes are used to locate holes in the LIGA substrate, pins to be pressed in the holes, and gears to be placed on the pins. This vision system can locate parts within 3 microns, while the Cartesian manipulator can place the parts within 0.4 microns.

  6. Wafer-Scale Fabrication of Plasmonic Crystals from Patterned Silicon Templates Prepared by Nanosphere Lithography

    E-print Network

    Wafer-Scale Fabrication of Plasmonic Crystals from Patterned Silicon Templates Prepared Supporting Information ABSTRACT: By combining nanosphere lithography with template stripping, silicon wafers then replicated in gold by metal evaporation, resulting in wafer-scale hexagonal gratings for plasmonic

  7. Wafer scale packaging for a MEMS video scanner

    NASA Astrophysics Data System (ADS)

    Helsel, Mark P.; Barger, Jon; Wine, David W.; Osborn, Thor D.

    2001-04-01

    Miniaturized scanners have proven their usefulness in a host of applications including video display, bar code reading, image capture, laser printing and optical switching. In order for these applications to reach fruition, however, the MEMS scanner component must be packaged in a manner that is compatible with the volume manufacturing capabilities of the technology. This paper describes a process that was developed to package an SVGA resolution (800 X 600) biaxial video scanner. The scanner is designed for a head mounted display product, targeted to the medical and industrial markets. The scanner is driven magnetically on one axis and capacitively on the other axis. The first level wafer scale package described here incorporates the capacitive drive electrodes into the mounting substrate. The substrate wafer and the device wafer are then bonded using a glass frit sealing technique. Finally, the scanner and substrate are hermetically sealed into a metal can at reduced pressure.

  8. Zinc Oxide Nanowires Low-Temperature Wafer-Scale Production of

    E-print Network

    Cohen, Ronald C.

    Zinc Oxide Nanowires Low-Temperature Wafer-Scale Production of ZnO Nanowire Arrays** Lori E. Greene aqueous conditions. We present data for arrays on four-inch (ca. 10 cm) silicon wafers and two) wafer to form a 50­200-nm thick film of crystal seeds. Between coatings, the wafer was annealed at 1508C

  9. Liga developer apparatus system

    DOEpatents

    Boehme, Dale R. (Pleasanton, CA); Bankert, Michelle A. (San Francisco, CA); Christenson, Todd R. (Albuquerque, NM)

    2003-01-01

    A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

  10. Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors

    E-print Network

    Zhou, Chongwu

    Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display Applications compatibility. Here in this paper, we report our progress on wafer-scale processing of separated nanotube thin-film transistors (SN-TFTs) for display applications, including key technology components such as wafer

  11. Non-Wafer-Scale Sieving Hardware for the NFS: Another Attempt to Cope with 1024-bit

    E-print Network

    International Association for Cryptologic Research (IACR)

    Non-Wafer-Scale Sieving Hardware for the NFS: Another Attempt to Cope with 1024-bit Willi to be about 2 to 3.5 times slower than TWIRL (a wafer-scale design). Due to the more moderate technological. ­ TWIRL [ST03,LTS+ 03] seems to be the currently best-explored design. Unfortunately, it is a wafer

  12. Wafer-scale aluminum plasmonics for fluorescence based biodetection

    NASA Astrophysics Data System (ADS)

    Farhang, Arash; George, Matthew C.; Williamson, Brent; Black, Mike; Wangensteen, Ted; Fraser, James; Petrova, Rumyana; Prestgard, Kent

    2015-08-01

    Moxtek has leveraged existing capabilities in wafer-scale patterning of sub-wavelength wire grid polarizers into the fabrication of 1D and 2D periodic aluminum plasmonic structures. This work will discuss progress in 200 mm diameter wafer-scale fabrication, with detailed emphasis within the realm of microarray based fluorescence detection. Aluminum nanohole arrays in a hexagonal lattice are first numerically investigated. The nanohole array geometry and periodicity are specifically tuned to coincide both with the excitation of the fluorophore Cy3, and to provide a high field enhancement within the nanoholes where labeled biomolecules are captured. This is accomplished through numerical modelling, nanofabrication, SEM imaging, and optical characterization. A 200mm diameter wafer, patterned with the optically optimized nanohole array, is cut into standard 1x3 inch microscope slide pieces and then subsequently printed with various antigens at 9 different concentrations. A sandwich bioassay is then carried out, using the corresponding conjugate antibodies in order to demonstrate specificity. The nanohole array exhibit a 3-4 times total fluorescence enhancement of Cy3, when compared to a leading commercial microarray glass slide.

  13. Wafer-scale nanowell array patterning based electrochemical impedimetric immunosensor.

    PubMed

    Lee, JuKyung; Cho, SiHyeong; Lee, JungHwan; Ryu, HeonYul; Park, JinGoo; Lim, SunHee; Oh, ByungDo; Lee, ChangWoo; Huang, Wilber; Busnaina, Ahmed; Lee, HeaYeon

    2013-12-01

    We have reported that nanowell array (NWA) can enhance electrochemical detection of molecular binding events by controlling the binding sites of the captured molecules. Using NWA biosensor based amperometric analysis, we have detected biological macromolecules such as DNA, protein or aptamers at low concentrations. In this research, we developed an impedimetric immunosensor based on wafer-scale NWA for electrochemical detection of stress-induced-phosphoprotein-1 (STIP-1). In order to develop NWA sensor through the cost-effective combination of high-throughput nanopattern, the NWA electrode was fabricated on Si wafer by krypton-fluoride (KrF) stepper semiconductor process. Finally, 12,500,000 ea nanowell with a 500 nm diameter was fabricated on 4 mm × 2 mm substrate. Next, by using these electrodes, we measured impedance to quantify antigen binding to the immunoaffinity layer. The limit of detection (LOD) of the NWA was improved about 100-fold compared to milli-sized electrodes (4 mm × 2 mm) without an NWA. These results suggest that wafer-scale NWA immunosensor will be useful for biosensing applications because their interface response is appropriate for detecting molecular binding events. PMID:24013070

  14. Wafer-scale plasmonic and photonic crystal sensors

    NASA Astrophysics Data System (ADS)

    George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

    2015-08-01

    200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

  15. Towards Wafer-Scale Monocrystalline Graphene Growth and Characterization.

    PubMed

    Nguyen, Van Luan; Lee, Young Hee

    2015-08-01

    Since its discovery in 2004, graphene has boosted numerous fundamental sciences and technological applications due to its massless Dirac particle-like linear band dispersion, that causes unprecedented physical properties. Among the various methods for synthesizing graphene, chemical vapor deposition is the most suitable approach for scalable production on a wafer scale, which is a critical step for practical applications. Graphene grain boundaries (GGBs), consisting of nonhexagonal carbon rings and therefore modulating the properties of graphene films, are inevitably formed via the merging of adjacent graphene domains with different orientations. Large-area monocrystalline graphene synthesis without forming GGBs has been challenging, let alone observing such boundaries. Here, an up-to-date review is presented of how to grow wafer-scale monocrystalline graphene without GGBs. One approach is to make single domain sizes as large as possible by reducing or passivating the number of nucleation sites. Another approach is to align graphene domains in identical orientations, and then merge them atomically. The recently developed methods for observing graphene orientation and GGBs both at the atomic and macro-scales are also presented. Finally, perspectives for future research in graphene growth are discussed. PMID:25903119

  16. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

  17. 498 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 4, JULY 2009 Wafer-Scale Growth and Transfer of Aligned

    E-print Network

    Zhou, Chongwu

    498 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 4, JULY 2009 Wafer-Scale Growth and Transfer, and Subhasish Mitra, Senior Member, IEEE Abstract--Experimental demonstration of wafer-scale growth of well-aligned, dense, single-walled carbon nanotubes on 4 ST- cut quartz wafers is presented. We developed a new carbon

  18. Wafer-scale 3D integration of silicon-on-insulator RF amplifiers

    E-print Network

    Keast, Craig L.

    RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens ...

  19. ISOTROPIC ETCHING OF 111 SCS FOR WAFER-SCALE MANUFACTURING OF PERFECTLY HEMISPHERICAL SILICON MOLDS

    E-print Network

    Afshari, Ehsan

    ISOTROPIC ETCHING OF 111 SCS FOR WAFER-SCALE MANUFACTURING OF PERFECTLY HEMISPHERICAL SILICON MOLDS as sacrificial molds for micro-scale hemispherical resonator gyroscopes (HRGs) made using hemispherical shell resonators. Geometric uniformity of the mold is critical for HRG applications in order to achieve degenerate

  20. Wafer-scale growth of VO2 thin films using a combinatorial approach.

    PubMed

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C; Alem, Nasim; Engel-Herbert, Roman

    2015-01-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that 'electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

  1. Wafer-scale growth of VO2 thin films using a combinatorial approach

    NASA Astrophysics Data System (ADS)

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

    2015-10-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that `electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems.

  2. Wafer-scale growth of VO2 thin films using a combinatorial approach

    PubMed Central

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

    2015-01-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that ‘electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

  3. Bio/chemical microsystem designed for wafer scale testing

    NASA Astrophysics Data System (ADS)

    Jorgensen, Anders M.; Mogensen, Klaus B.; Rong, Weimin; Telleman, Pieter; Kutter, Joerg P.

    2001-04-01

    We have designed a bio/chemical microsystem for online monitoring of glucose concentrations during fermentation. The system contains several passive microfluidic components including an enzyme reactor, a flow lamination part and a detector. Detection is based on the reaction of hydrogen peroxide, that is produced from glucose in an enzyme reactor, with luminol. This chemiluminescent reaction generates light that is detected by an integrated back-side contacted photodiode array. Various tests during fabrication are outlined with the emphasis on microwave detected photo conductance decay. The presented microsystem has both fluidic and electrical connection points accessible from the backside. This allows simultaneous testing of both fluidic and electrical parts before dicing the wafer.

  4. Wafer-scale metamaterials for polarization-insensitive and dual-band perfect absorption.

    PubMed

    Liu, Jia; Zhu, Maoxia; Zhang, Nan; Zhang, Haitao; Zhou, Yu; Sun, Shang; Yi, Ningbo; Gao, Shang; Song, Qinghai; Xiao, Shumin

    2015-12-01

    Mid-infrared (IR) perfect absorbers have great potential in practical applications such as biomedical sensing and thermal energy and have been successfully demonstrated in a number of plasmonic metallic nanostructures. However, all the experimental realizations of perfect absorbers are strongly dependent on nanofabrication techniques, which usually require high costs and a long time to fabricate a wafer scale device. Here we propose and experimentally demonstrate a wafer scale, polarization independent, wide angle, and dual-band IR perfect absorber. By fabricating double "E"-shaped metallic structures on a ZnSe coated gold film, a dual-band metamaterial absorber has been uniformly realized on a 2'' silicon wafer. Two absorption peaks have been realized at 18 and 27 THz, which are well consistent with the designs. We believe that our research will boost the applications of metamaterial perfect absorbers. PMID:26525777

  5. Wafer-scale metamaterials for polarization-insensitive and dual-band perfect absorption

    NASA Astrophysics Data System (ADS)

    Liu, Jia; Zhu, Maoxia; Zhang, Nan; Zhang, Haitao; Zhou, Yu; Sun, Shang; Yi, Ningbo; Gao, Shang; Song, Qinghai; Xiao, Shumin

    2015-11-01

    Mid-infrared (IR) perfect absorbers have great potential in practical applications such as biomedical sensing and thermal energy and have been successfully demonstrated in a number of plasmonic metallic nanostructures. However, all the experimental realizations of perfect absorbers are strongly dependent on nanofabrication techniques, which usually require high costs and a long time to fabricate a wafer scale device. Here we propose and experimentally demonstrate a wafer scale, polarization independent, wide angle, and dual-band IR perfect absorber. By fabricating double ``E''-shaped metallic structures on a ZnSe coated gold film, a dual-band metamaterial absorber has been uniformly realized on a 2'' silicon wafer. Two absorption peaks have been realized at 18 and 27 THz, which are well consistent with the designs. We believe that our research will boost the applications of metamaterial perfect absorbers.

  6. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

  7. Wafer-Scale High-Throughput Ordered Growth of Vertically Aligned ZnO Nanowire

    E-print Network

    Wang, Zhong L.

    - synthesized morphology. The development of textured ZnO seed layers for replacing single crystalline GaN- chemically, or heteroepitaxially on GaN film. The substrates can be patterned with periodic ordered, variableWafer-Scale High-Throughput Ordered Growth of Vertically Aligned ZnO Nanowire Arrays Yaguang Wei

  8. Control of wafer-scale non-uniformity in chemical-mechanical planarization by face-up polishing

    E-print Network

    Mau, Catherine (Catherine K.)

    2008-01-01

    Chemical-mechanical planarization (CMP) is a key process in the manufacture of ultra-large-scale-integrated (ULSI) semiconductor devices. A major concern in CMP is non-uniform planarization, or polishing, at the wafer-scale ...

  9. Low-energy silicon-on-insulator ion implanted gratings for optical wafer scale testing

    NASA Astrophysics Data System (ADS)

    Loiacono, Renzo; Reed, Graham T.; Mashanovich, Goran Z.; Gwilliam, Russell M.; Lulli, Giorgio; Feldesh, Ran; Jones, Richard

    2011-01-01

    Silicon photonics shows tremendous potential for the development of the next generation of ultra fast telecommunication, tera-scale computing, and integrated sensing applications. One of the challenges that must be addressed when integrating a "photonic layer" onto a silicon microelectronic circuit is the development of a wafer scale optical testing technique, similar to that employed today in integrated electronics industrial manufacturing. This represents a critical step for the advancement of silicon photonics to large scale production technology with reduced costs. In this work we propose the fabrication and testing of ion implanted gratings in sub micrometer SOI waveguides, which could be applied to the implementation of optical wafer scale testing strategies. An extinction ratio of over 25dB has been demonstrated for ion implanted Bragg gratings fabricated by low energy implants in submicron SOI rib waveguides with lengths up to 1mm. Furthermore, the possibility of employing the proposed implanted gratings for an optical wafer scale testing scheme is discussed in this work.

  10. Hybrid wafer-scale processor. Final report, 15 July 1988-14 January 1989

    SciTech Connect

    Jacobi, W.J.

    1989-03-14

    The basic goal of this project is to develop and demonstrate techniques for the reduction of power consumption of space-based processors for infrared-surveillance systems. The primary technique is to minimize the capacitive loading encountered in off-chip communications for highly concurrent processing architectures. Both processing architecture and chip packaging are simultaneously considered to maximize MOPS per watt by increasing throughput while reducing system capacitance, signal delay, noise, voltage swing, and power consumption (the costs of system communications). With conventional packaging technology, highly concurrent processing architectures result in hardware implementations that are extremely large, very heavy, and that consume excessive power. Monolithic wafer-scale integration is theoretically ideal but requires an extensive amount of redundant circuitry and provisions for circuit reconstructurability because of manufacturing yield problems. In the hybrid wafer-scale integration (HWSI) approach, individual pre-tested chips are bonded to a fine-line interconnect structure fabricated on the surface of a wafer-scale substrate. With this technique, high yields can be achieved without redundancy.

  11. Terahertz wafer-scale mobility mapping of graphene on insulating substrates without a gate.

    PubMed

    Buron, Jonas D; Mackenzie, David M A; Petersen, Dirch H; Pesquera, Amaia; Centeno, Alba; Bøggild, Peter; Zurutuza, Amaia; Jepsen, Peter U

    2015-11-30

    We demonstrate wafer-scale, non-contact mapping of essential carrier transport parameters, carrier mobility (µdrift), carrier density (Ns), DC sheet conductance (?dc), and carrier scattering time (?sc) in CVD graphene, using spatially resolved terahertz time-domain conductance spectroscopy. ?dc and ?sc are directly extracted from Drude model fits to terahertz conductance spectra obtained in each pixel of 10 × 10 cm2 maps with a 400 µm step size. ?dc- and ?sc-maps are translated into µdrift and Ns maps through Boltzmann transport theory for graphene charge carriers and these parameters are directly compared to van der Pauw device measurements on the same wafer. The technique is compatible with all substrate materials that exhibit a reasonably low absorption coefficient for terahertz radiation. This includes many materials used for transferring CVD graphene in production facilities as well as in envisioned products, such as polymer films, glass substrates, cloth, or paper substrates. PMID:26698704

  12. Growth of wafer-scale MoS2 monolayer by magnetron sputtering

    NASA Astrophysics Data System (ADS)

    Tao, Junguang; Chai, Jianwei; Lu, Xin; Wong, Lai Mun; Wong, Ten It; Pan, Jisheng; Xiong, Qihua; Chi, Dongzhi; Wang, Shijie

    2015-01-01

    The two-dimensional layer of molybdenum disulfide (MoS2) exhibits promising prospects in the applications of optoelectronics and valleytronics. Herein, we report a successful new process for synthesizing wafer-scale MoS2 atomic layers on diverse substrates via magnetron sputtering. Spectroscopic and microscopic results reveal that these synthesized MoS2 layers are highly homogeneous and crystallized; moreover, uniform monolayers at wafer scale can be achieved. Raman and photoluminescence spectroscopy indicate comparable optical qualities of these as-grown MoS2 with other methods. The transistors composed of the MoS2 film exhibit p-type performance with an on/off current ratio of ~103 and hole mobility of up to ~12.2 cm2 V-1 s-1. The strategy reported herein paves new ways towards the large scale growth of various two-dimensional semiconductors with the feasibility of controllable doping to realize desired p- or n-type devices.The two-dimensional layer of molybdenum disulfide (MoS2) exhibits promising prospects in the applications of optoelectronics and valleytronics. Herein, we report a successful new process for synthesizing wafer-scale MoS2 atomic layers on diverse substrates via magnetron sputtering. Spectroscopic and microscopic results reveal that these synthesized MoS2 layers are highly homogeneous and crystallized; moreover, uniform monolayers at wafer scale can be achieved. Raman and photoluminescence spectroscopy indicate comparable optical qualities of these as-grown MoS2 with other methods. The transistors composed of the MoS2 film exhibit p-type performance with an on/off current ratio of ~103 and hole mobility of up to ~12.2 cm2 V-1 s-1. The strategy reported herein paves new ways towards the large scale growth of various two-dimensional semiconductors with the feasibility of controllable doping to realize desired p- or n-type devices. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr06411a

  13. LIGA Micromachining: Infrastructure Establishment

    SciTech Connect

    Alfredo M. Morales; Barry V. Hess; Dale R. Boehme; Jill M. Hruby; John S. Krafcik; Robert H. Nilson; Stewart K. Griffiths; William D. Bonivert

    1999-02-01

    LIGA is a micromachining technology that uses high energy x-rays from a synchrotron to create patterns with small lateral dimensions in a deep, non-conducting polymeric resist. Typical dimensions for LIGA parts are microns to tens of microns in lateral size, and hundreds of microns to millimeters in depth. Once the resist is patterned, metal is electrodeposited in the features to create metal microparts, or to create a metal mold for subsequent replication. The acronym LIGA comes from the German words for lithography, electroforming, and molding, and the technology has been under worldwide development for more than a decade. over the last five years, a full-service capability to produce metal microparts using the LIGA process has been established at Sandia national Laboratories, California. This report describes the accomplishments made during the past two years in infrastructure establishment funded by a Laboratory Directed Research and Development (LDRD) project entitled ''LIGA Micromachining.'' Specific topics include photoresist processing for LIGA mask making, x-ray scanning equipment, plating bath instrumentation, plating uniformity, and software architecture.

  14. Microfluidic design and fabrication of wafer-scale varifocal liquid lens

    NASA Astrophysics Data System (ADS)

    Lee, Jeong-Yub; Choi, Seung-Tae; Lee, Seung-Wan; Kim, Woonbae

    2009-08-01

    Microfluidic design and fabrication was developed for wafer-scale varifocal liquid lens which is slim less than 0.9mm. The liquid-filled varifocal lens has advanced functions such as auto macro and focusing to obtain a high quality of image. This varifocal lens is similar to human eye and it consists of main Si frame which has penetrated inner hole, upside-bonded PDMS (polydimethylsiloxane) elastomer membrane, downside-bonded glass plate and optical fluid confined by these structures. Si frame, which has a circular hole for tunable lens chamber, several holes for actuator chamber and micro-fluidic channels between chambers, is fabricated using thin Si wafer and microelectromechanical system (MEMS) processes. When optical fluid is filled the internal cavity by conventional injection, void trapping which degrades optical performance or filling impossibility happens because of high aspect ratio between lens diameter and thickness for slim liquid lens. To prevent these problems, we developed wafer-based microfabrications of seal line dispensing, accurate dropping of optical fluid, pressing & bonding process in vacuum and UV sealant curing. Afterward, electro-active polymer actuators, which push the optical fluid to change the lens shape, was attached on the PDMS membrane of liquid lens wafer and sawing process of 9.4mm*9.0mm chip size followed. Finally, the varifocal liquid lens which is slim less than 0.6mm thickness (0.9mm included actuators), tunable more than 20diopter changes of refractive power, guaranteed reliability of 300,000 repetitions and suitable for mass production, was realized.

  15. Growth of wafer-scale MoS2 monolayer by magnetron sputtering.

    PubMed

    Tao, Junguang; Chai, Jianwei; Lu, Xin; Wong, Lai Mun; Wong, Ten It; Pan, Jisheng; Xiong, Qihua; Chi, Dongzhi; Wang, Shijie

    2015-02-14

    The two-dimensional layer of molybdenum disulfide (MoS2) exhibits promising prospects in the applications of optoelectronics and valleytronics. Herein, we report a successful new process for synthesizing wafer-scale MoS2 atomic layers on diverse substrates via magnetron sputtering. Spectroscopic and microscopic results reveal that these synthesized MoS2 layers are highly homogeneous and crystallized; moreover, uniform monolayers at wafer scale can be achieved. Raman and photoluminescence spectroscopy indicate comparable optical qualities of these as-grown MoS2 with other methods. The transistors composed of the MoS2 film exhibit p-type performance with an on/off current ratio of ?10(3) and hole mobility of up to ?12.2 cm(2) V(-1) s(-1). The strategy reported herein paves new ways towards the large scale growth of various two-dimensional semiconductors with the feasibility of controllable doping to realize desired p- or n-type devices. PMID:25569291

  16. A Wafer-Scale Etching Technique for High Aspect Ratio Implantable MEMS Structures

    PubMed Central

    Bhandari, R; Negi, S; Rieth, L.; Solzbacher, F

    2010-01-01

    Microsystem technology is well suited to batch fabricate microelectrode arrays, such as the Utah electrode array (UEA), intended for recording and stimulating neural tissue. Fabrication of the UEA is primarily based on the use of dicing and wet etching to achieve high aspect ratio (15:1) penetrating electrodes. An important step in the array fabrication is the etching of electrodes to produce needle-shape electrodes with sharp tips. Traditional etching processes are performed on a single array, and the etching conditions are not optimized. As a result, the process leads to variable geometries of electrodes within an array. Furthermore, the process is not only time consuming but also labor-intensive. This report presents a wafer-scale etching method for the UEA. The method offers several advantages, such as substantial reduction in the processing time, higher throughput and lower cost. More importantly, the method increases the geometrical uniformity from electrode to electrode within an array (1.5 ± 0.5 % non-uniformity), and from array to array within a wafer (2 ± 0.3 % non-uniformity). Also, the etching rate of silicon columns, produced by dicing, are studied as a function of temperature, etching time and stirring rate in a nitric acid rich HF-HNO3 solution. These parameters were found to be related to the etching rates over the ranges studied and more-importantly affect the uniformity of the etched silicon columns. An optimum etching condition was established to achieve uniform shape electrode arrays on wafer-scale. PMID:20706618

  17. Assembly of LIGA using Electric Fields

    SciTech Connect

    FEDDEMA, JOHN T.; WARNE, LARRY K.; JOHNSON, WILLIAM A.; OGDEN, ALLISON J.; ARMOUR, DAVID L.

    2002-04-01

    The goal of this project was to develop a device that uses electric fields to grasp and possibly levitate LIGA parts. This non-contact form of grasping would solve many of the problems associated with grasping parts that are only a few microns in dimensions. Scaling laws show that for parts this size, electrostatic and electromagnetic forces are dominant over gravitational forces. This is why micro-parts often stick to mechanical tweezers. If these forces can be controlled under feedback control, the parts could be levitated, possibly even rotated in air. In this project, we designed, fabricated, and tested several grippers that use electrostatic and electromagnetic fields to grasp and release metal LIGA parts. The eventual use of this tool will be to assemble metal and non-metal LIGA parts into small electromechanical systems.

  18. Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

    PubMed Central

    Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

    2014-01-01

    In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32?A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50?kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

  19. Face-to-face transfer of wafer-scale graphene films

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene.

  20. Wafer-Scale Double-Layer Stacked Au/Al2O3@Au Nanosphere Structure with Tunable Nanospacing for Surface-Enhanced Raman Scattering

    E-print Network

    Wang, Wei Hua

    19/2014 Wafer-Scale Double-Layer Stacked Au/Al2O3@Au Nanosphere Structure with Tunable Nanospacing wafer-scale double-layer stacked Au/Al2O3@ Au(Ag) nanosphere structures with tunable nanospacing;3933© 2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim wileyonlinelibrary.com Wafer-Scale Double-Layer Stacked

  1. Fabrication of CVD graphene-based devices via laser ablation for wafer-scale characterization

    NASA Astrophysics Data System (ADS)

    Mackenzie, David M. A.; Buron, Jonas D.; Whelan, Patrick R.; Jessen, Bjarke S.; Silajd?i?, Adnan; Pesquera, Amaia; Centeno, Alba; Zurutuza, Amaia; Bøggild, Peter; Petersen, Dirch H.

    2015-12-01

    Selective laser ablation of a wafer-scale graphene film is shown to provide flexible, high speed (1 wafer/hour) device fabrication while avoiding the degradation of electrical properties associated with traditional lithographic methods. Picosecond laser pulses with single pulse peak fluences of 140 mJ cm?2 for 1064 nm, 40 mJ cm?2 for 532 nm, and 30 mJ cm?2 for 355 nm are sufficient to ablate the graphene film, while the ablation onset for Si/SiO2 (thicknesses 500 ?m/302 nm) did not occur until 240 mJ cm?2, 150 mJ cm?2, and 135 mJ cm?2, respectively, allowing all wavelengths to be used for graphene ablation without detectable substrate damage. Optical microscopy and Raman Spectroscopy were used to assess the ablation of graphene, while stylus profilometery indicated that the SiO2 substrate was undamaged. CVD graphene devices were electrically characterized and showed comparable field-effect mobility, doping level, on–off ratio, and conductance minimum before and after laser ablation fabrication.

  2. Wafer scale imprint uniformity evaluated by LSPR spectroscopy: a high volume characterization method for nanometer scale structures.

    PubMed

    Jeppesen, Claus; Lindstedt, Daniel Nilsson; Vig, Asger Laurberg; Kristensen, Anders; Mortensen, N Asger

    2012-09-28

    We exploit the localized surface-plasmon resonance (LSPR) of terahertz gold gammadion structures for wafer scale critical dimension metrology of nanostructures. The proposed characterization method, LSPR spectroscopy, is based on optical transmission measurements and is benchmarked against numerical simulations of imprinted structures characterized by atomic force microscopy. There is a fair agreement between the two methods and the simulations enable the translation of optical spectra to critical dimensions of the physical structures, a concept known from scatterometry. The results demonstrate the potential of LSPR spectroscopy as an alternative characterization method to scanning electron microscopy, atomic force microscopy and scatterometry. PMID:22948403

  3. High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity.

    PubMed

    Kang, Kibum; Xie, Saien; Huang, Lujie; Han, Yimo; Huang, Pinshane Y; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-04-30

    The large-scale growth of semiconducting thin films forms the basis of modern electronics and optoelectronics. A decrease in film thickness to the ultimate limit of the atomic, sub-nanometre length scale, a difficult limit for traditional semiconductors (such as Si and GaAs), would bring wide benefits for applications in ultrathin and flexible electronics, photovoltaics and display technology. For this, transition-metal dichalcogenides (TMDs), which can form stable three-atom-thick monolayers, provide ideal semiconducting materials with high electrical carrier mobility, and their large-scale growth on insulating substrates would enable the batch fabrication of atomically thin high-performance transistors and photodetectors on a technologically relevant scale without film transfer. In addition, their unique electronic band structures provide novel ways of enhancing the functionalities of such devices, including the large excitonic effect, bandgap modulation, indirect-to-direct bandgap transition, piezoelectricity and valleytronics. However, the large-scale growth of monolayer TMD films with spatial homogeneity and high electrical performance remains an unsolved challenge. Here we report the preparation of high-mobility 4-inch wafer-scale films of monolayer molybdenum disulphide (MoS2) and tungsten disulphide, grown directly on insulating SiO2 substrates, with excellent spatial homogeneity over the entire films. They are grown with a newly developed, metal-organic chemical vapour deposition technique, and show high electrical performance, including an electron mobility of 30 cm(2) V(-1) s(-1) at room temperature and 114 cm(2) V(-1) s(-1) at 90 K for MoS2, with little dependence on position or channel length. With the use of these films we successfully demonstrate the wafer-scale batch fabrication of high-performance monolayer MoS2 field-effect transistors with a 99% device yield and the multi-level fabrication of vertically stacked transistor devices for three-dimensional circuitry. Our work is a step towards the realization of atomically thin integrated circuitry. PMID:25925478

  4. Wafer-scale design of lightweight and transparent electronics that wraps around hairs

    NASA Astrophysics Data System (ADS)

    Salvatore, Giovanni A.; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

    2014-01-01

    Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-?m thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12?V and above 1?MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

  5. Wafer-scale, three-dimensional helical porous thin films deposited at a glancing angle

    NASA Astrophysics Data System (ADS)

    Huang, Zhifeng; Bai, Fan

    2014-07-01

    Minimization of helices opens a door to impose novel functions derived from the dimensional shrinkage of optical, mechanical and electronic devices. Glancing angle deposition (GLAD) enables one to deposit three-dimensional helical porous thin films (HPTFs) composed of separated spiral micro/nano-columns. GLAD integrates a series of advantageous features, including one-step deposition, wafer-scale production with mono-handedness of spirals, flexible engineering of spiral materials and dimensions, and the adaption to various kinds of substrates. Herein, we briefly review the fabrication of HPTFs by GLAD, specific growth mechanisms, physical properties in structures, mechanics and chiral optics, and the emerging applications in green energy. A prospective outlook is presented to illuminate some promising developments in enantioselection, bio-dynamic analyses, wirelessly-controlled drug delivery and mass production.

  6. C-and L-band erbium-doped waveguide lasers with wafer-scale silicon nitride cavities

    E-print Network

    Reif, Rafael

    C- and L-band erbium-doped waveguide lasers with wafer-scale silicon nitride cavities Purnawirman,1; posted April 22, 2013 (Doc. ID 187023); published May 20, 2013 We report on integrated erbium and a top erbium-doped aluminum oxide layer deposited as the final step in the fabrication process

  7. Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits

    E-print Network

    Shaver, David C.

    In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on ...

  8. High speed wafer scale bulge testing for the determination of thin film mechanical properties.

    PubMed

    Orthner, M P; Rieth, L W; Solzbacher, F

    2010-05-01

    A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50-150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 microm in width comprised of 720+/-10 nm thick low pressure chemical vapor deposited silicon nitride with approximately 20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to approximately 8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (approximately 350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young's modulus was estimated for the films assuming a Poisson's ratio of v=0.25. Calculations to determine Young's modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young's modulus for the smaller membranes. The deflection measurements of three 1200 x 1200 microm(2) Si(3)N(4-x) membranes were taken at increased pressures (>25 kPa) to increase nonlinearity and better determine Young's modulus. This pressure-deflection data were fit to an analytical solution and Young's modulus estimated to be 257+/-3 GPa, close to those previously reported in literature. PMID:20515176

  9. A wafer-scale graphene and ferroelectric multilayer for flexible and fast-switched modulation applications.

    PubMed

    Zhu, Minmin; Wu, Jing; Du, Zehui; Tay, Roland Yingjie; Li, Hongling; Özyilmaz, Barbarous; Teo, Edwin Hang Tong

    2015-09-21

    Here we report a wafer-scale graphene/P(VDF-TrFE)/graphene multilayer for light-weight, flexible and fast-switched broadband modulation applications. The P(VDF-TrFE) film not only significantly reduces the sheet resistance of graphene throughout heavy doping of ?0.8 × 10(13) cm(-2) by nonvolatile ferroelectric dipoles, but also acts as an efficient electro-optic (EO) layer. Such multilayered structural integration with remarkable ferroelectric polarization, high transparency (>90%), low sheet resistance (?302 ??(-1)), and excellent mechanic flexibility shows the potential of a flexible modulation application over a broad range of wavelengths. Moreover, the derived device also exhibits strong field-induced EO modulation even under bending and one large Pockels coefficient (?54.3 pm V(-1)) is obtained. Finally, the graphene and ferroelectric hybrid demonstrates a fast switching time (?2 ?s) and works well below low sheet resistance level over a long time. This work gives insights into the potential of graphene and ferroelectric hybrid structures, enabling future exploration on next-generation high-performance, flexible transparent electronics and photonics. PMID:26284783

  10. Wafer-scale highly-transparent and superhydrophilic sapphires for high-performance optics.

    PubMed

    Leem, Jung Woo; Yu, Jae Su

    2012-11-19

    We reported the wafer-scale highly-transparent and superhydrophilic sapphires with antireflective subwavelength structures (SWSs) which were fabricated by dry etching using thermally dewetted gold (Au) nanomasks. Their optical transmittance properties were experimentally and theoretically investigated. The density, size, and period of the thermally dewetted Au nanopatterns can be controlled by the Au film thickness. For the sapphire with both-side SWSs at 5 nm of Au film, the average total transmittance (T(avg)) of ~96.5% at 350-800 nm was obtained, indicating a higher value than those of the flat sapphire (T(avg)~85.6%) and the sapphire with one-side SWSs (T(avg)~91%), and the less angle-dependent transmittance property was observed. The calculated transmittance results also showed a similar tendency to the measured data. The SWSs enhanced significantly the surface hydrophilicity of sapphires, exhibiting a water contact angle (?(c)) of < 5° for Au film of 5 nm compared to ?(c)~37° of the flat sapphire. PMID:23187471

  11. Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy

    PubMed Central

    Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

    2013-01-01

    The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (“metasurfaces”) can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

  12. Wafer-scale self-organized InP nanopillars with controlled orientation for photovoltaic devices.

    PubMed

    Sanatinia, Reza; Berrier, Audrey; Dhaka, Veer; Perros, Alexander P; Huhtio, Teppo; Lipsanen, Harri; Anand, Srinivasan

    2015-10-16

    A unique wafer-scale self-organization process for generation of InP nanopillars is demonstrated, which is based on maskless ion-beam etching (IBE) of InP developed to obtain the nanopillars, where the height, shape, and orientation of the nanopillars can be varied by controlling the processing parameters. The fabricated InP nanopillars exhibit broadband suppression of the reflectance, 'black InP,' a property useful for solar cells. The realization of a conformal p-n junction for carrier collection, in the fabricated solar cells, is achieved by a metalorganic vapor phase epitaxy (MOVPE) overgrowth step on the fabricated pillars. The conformal overgrowth retains the broadband anti-reflection property of the InP nanopillars, indicating the feasibility of this technology for solar cells. Surface passivation of the formed InP nanopillars using sulfur-oleylamine solution resulted in improved solar-cell characteristics. An open-circuit voltage of 0.71 V and an increase of 0.13 V compared to the unpassivated device were achieved. PMID:26403979

  13. Wafer-scale self-organized InP nanopillars with controlled orientation for photovoltaic devices

    NASA Astrophysics Data System (ADS)

    Sanatinia, Reza; Berrier, Audrey; Dhaka, Veer; Perros, Alexander P.; Huhtio, Teppo; Lipsanen, Harri; Anand, Srinivasan

    2015-10-01

    A unique wafer-scale self-organization process for generation of InP nanopillars is demonstrated, which is based on maskless ion-beam etching (IBE) of InP developed to obtain the nanopillars, where the height, shape, and orientation of the nanopillars can be varied by controlling the processing parameters. The fabricated InP nanopillars exhibit broadband suppression of the reflectance, ‘black InP,’ a property useful for solar cells. The realization of a conformal p-n junction for carrier collection, in the fabricated solar cells, is achieved by a metalorganic vapor phase epitaxy (MOVPE) overgrowth step on the fabricated pillars. The conformal overgrowth retains the broadband anti-reflection property of the InP nanopillars, indicating the feasibility of this technology for solar cells. Surface passivation of the formed InP nanopillars using sulfur-oleylamine solution resulted in improved solar-cell characteristics. An open-circuit voltage of 0.71 V and an increase of 0.13 V compared to the unpassivated device were achieved.

  14. Wafer-scale synthesis of single-crystal zigzag silicon nanowire arrays with controlled turning angles.

    PubMed

    Chen, Huan; Wang, Hui; Zhang, Xiao-Hong; Lee, Chun-Sing; Lee, Shuit-Tong

    2010-03-10

    Silicon nanowires (SiNWs) having curved structures may have unique advantages in device fabrication. However, no methods are available to prepare curved SiNWs controllably. In this work, we report the preparation of three types of single-crystal SiNWs with various turning angles via metal-assisted chemical etching using (111)-oriented silicon wafers near room temperature. The zigzag SiNWs are single crystals and can be p- or n-doped using corresponding Si wafer as substrate. The controlled growth direction is attributed to the preferred movement of Ag nanoparticles along 001 and other directions in Si wafer. Our results demonstrate that metal-assisted chemical etching may be a viable approach to fabricate SiNWs with desired turning angles by utilizing the various crystalline directions in a Si wafer. PMID:20104856

  15. A wafer-scale backplane-assisted resonating nanoantenna array SERS device created by tunable thermal dewetting nanofabrication

    NASA Astrophysics Data System (ADS)

    Chang, Te-Wei; Ranjan Gartia, Manas; Seo, Sujin; Hsiao, Austin; Logan Liu, Gang

    2014-04-01

    A tunable lithography-less nanofabrication process using a metal thin-film thermal dewetting technique has been developed to fabricate wafer-scale and uniform plasmonic substrates at low cost for optimal performance in surface enhanced Raman scattering (SERS) applications. The relationship between the tunable parameters of this process and the corresponding optical and plasmonic characteristic is investigated both experimentally and theoretically to understand the deterministic design of an optimal SERS device with a three-dimensional plasmonic nanoantenna structure. The enhancement of SERS using various nanoplasmonic particle sizes, structure lengths, lateral hot spot spacings and resonating effects are examined and demonstrated. We achieve a uniform optimal enhancement factor of 1.38 × 108 on a 4 in wafer-scale SERS substrate with a backplane-assisted resonating nanoantenna array design. Sensitive environmental nitrate sensing, vitamin detection and oligonucleotide identification are demonstrated on the high-performance SERS device.

  16. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300?mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700?cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  17. Wafer-scale production of uniform InAs(y)P(1-y) nanowire array on silicon for heterogeneous integration.

    PubMed

    Shin, Jae Cheol; Lee, Ari; Mohseni, Parsian Katal; Kim, Do Yang; Yu, Lan; Kim, Jae Hun; Kim, Hyo Jin; Choi, Won Jun; Wasserman, Daniel; Choi, Kyoung Jin; Li, Xiuling

    2013-06-25

    One-dimensional crystal growth allows the epitaxial integration of compound semiconductors on silicon (Si), as the large lattice-mismatch strain arising from heterointerfaces can be laterally relieved. Here, we report the direct heteroepitaxial growth of a mixed anion ternary InAsyP1-y nanowire array across an entire 2 in. Si wafer with unprecedented spatial, structural, and special uniformity across the entire 2 in. wafer and dramatic improvements in aspect ratio (>100) and area density (>5 × 10(8)/cm(2)). Heterojunction solar cells consisting of n-type InAsyP1-y (y = 0.75) and p-type Si achieve a conversion efficiency of 3.6% under air mass 1.5 illumination. This work demonstrates the potential for large-scale production of these nanowires for heterogeneous integration of optoelectronic devices. PMID:23651314

  18. Study of wafer thickness scaling in n-type rear-emitter solar cells with different bulk lifetimes

    NASA Astrophysics Data System (ADS)

    Chen, Chen; Zhang, Wei; Xing, Zhao; Sun, Yun; Jia, Rui; Jin, Zhi; Liu, Xinyu; Redwing, Joan M.

    2014-08-01

    In case of the n-type rear-emitter solar cell (n-RESC), wafer thickness scaling down has been studied and simulated under different bulk lifetimes (?bulk). The effect of minority-carrier lifetime of bulk ?bulk on photovoltaic properties has been studied by using a symmetrical front-and-rear electrode structure, followed by a discussion of the physical mechanism. Simulation results show that by decreasing the wafer thickness, high energy-conversion efficiency can be achieved, even though a low bulk lifetime substrate is used, suggesting a cost-effective way to manufacture the high efficiency n-RESC. In addition, emitter saturation current density (Joe) of the n-RESC has also been extracted.

  19. Using wafer-scale epitaxial graphene for producing twisted bilayers with controlled twist angle for electronics applications (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Dimitrakopoulos, Christos D.

    2015-09-01

    Graphene's exceptional properties make it attractive for technological applications in many areas, including high-speed electronics. The establishment of processes for producing high quality, large-scale graphene is necessary for such applications. Large area growth of epitaxial graphene on the Si-face of hexagonal SiC (0001) wafers exhibits manageable growth kinetics, and most importantly, its azimuthal orientation is fixed, as it is determined by the structure of the single crystal substrate. Therefore, this is a viable method for producing graphene with uniform coverage and structural coherence at wafer-scale.[1],[2] Semi-insulating SiC is a good substrate for graphene RF transistors, however, its cost is so high that potentially only niche applications of graphene on SiC (e.g. defense or space related) can be viable. Furthermore, to enable hybrid electronics, where standard circuits built on Si perform digital logic functions while graphene that does not exhibit a band gap is used for ultrafast analog devices, we would need to transfer epitaxial graphene onto Si wafers. To address these issues, we have developed a method in which a graphene film grown on a 4" SiC wafer is exfoliated via the stress induced by an overgrown Ni film and transferred to other substrates, resulting in a wafer-scale monolayer of graphene that is continuous and has a single azimuthal orientation.[3] This growth and transfer process can be repeated on the same SiC wafer hundreds to thousands of times, dramatically reducing the cost per wafer-sized graphene layer. The characterization of the transferred films shows that they are of quality similar to the pristine films on SiC. Capitalizing on this new method for single crystal epitaxial graphene transfer, we have initiated a project to produce bilayers of graphene with deterministically controlled twist angles. The inspiration for this experimental work is recent theoretical work by Maroudas and coworkers4 that predicts the opening of substantial band gaps at specific twist angles in bilayer graphene. We will report our methods for producing twisted bilayers with controlled twist angle, their characterization and device results. [1] C. Dimitrakopoulos, Y.-M. Lin, A. Grill, D. B. Farmer, M. Freitag, Y. Sun, S.-J. Han, Z. Chen, K. A. Jenkins, Y. Zhu, Z. Liu, T. J. McArdle, J. A. Ott, R. Wisnieff, Ph. Avouris J. Vac. Sci. Technol. B 28, 985-992, (2010). [2] Y.-M. Lin, C. Dimitrakopoulos, K. A. Jenkins, D. B. Farmer, H.-Y. Chiu, Ph. Avouris Science 327, 662 (2010). [3] J. Kim, H. Park, J. B. Hannon, S. W. Bedell, K. Fogel, D. K. Sadana, C. Dimitrakopoulos Science 342, 833-836 (2013). [4] A. R. Muniz, D. Maroudas Phys. Rev. B 86, 075404 (2012)

  20. Fabrication of a wafer-scale uniform array of single-crystal organic nanowire complementary inverters by nanotransfer printing

    NASA Astrophysics Data System (ADS)

    Park, Kyung Sun; Baek, Jangmi; Koo Lee, Yong-Eun; Sung, Myung Mo

    2015-02-01

    We report the fabrication and electrical characterization of a wafer-scale array of organic complementary inverters using single-crystal 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-PEN) and fullerene (C60) nanowires as p- and n-channels, respectively. Two arrays of single-crystal organic nanowires were generated consecutively on desired locations of a common substrate with a desired mutual alignment by a direct printing method (liquid-bridge-mediated nanotransfer molding). Another direct printing of silver micron scale structures, as source and drain electrodes, on the substrate with the two printed nanowire arrays produced an array of complementary inverters with a bottom gate, top contact configuration. Field-effect mobilities of single-crystal TIPS-PEN and C60 nanowire field-effect transistors (FETs) in the arrays were uniform with 1.01 ± 0.14 and 0.10 ± 0.01 cm2V-1 s-1, respectively. A wafer-scale array of complementary inverters produced all by the direct printing method showed good performance with an average gain of 25 and with low variations among the inverters.

  1. Stationary Optical Concentrator Designs and Wafer Scale Monolithic Integration of Semiconductor Devices for Next Generation Photovoltaic Panels

    NASA Astrophysics Data System (ADS)

    Kim, Jung Min

    A major barrier in utilizing solar energy for large scale deployment is the cost of the photovoltaic (PV) systems. Several approaches have been used for the cost reduction such as by modifying PV system designs in addition to enhancing the efficiency of solar cells. Due to the high cost of materials, minimizing the use of solar cells such as in concentrator type systems is highly attractive for reducing the cost of the PV modules by focusing the incident light onto the PV cell. However concentrator PV systems (CPV) require constant tracking of the sun and hence are complex in design and expensive to operate, except in limited situations such as large scale PV power plants. It is desirable to design new concentrator type systems that do not require continuous tracking of the sun. These systems could ultimately reduce the PV system cost to a minimum while maximizing the power conversion efficiency. In this thesis we propose a simple design for a stationary concentrator photovoltaic (SCPV) system that could significantly reduce the cost of generating electricity using PV devices. Using optical ray tracing simulations, we have been able to design SCPV systems that could reduce the PV module cost by 2--10 times without compromising on the power conversion efficiency of the system. Another alternative approach for sustainable high efficiency PV system design is to develop low cost PV cells for terrestrial applications. To meet the demands of low cost and large scale production, larger and thinner (or flexible) substrates are required. We demonstrated the feasibility of fabricating monolithic interconnected PV devices at the wafer scale (2 inch wafers). In this study, GaSb PV cells grown on semi-insulating GaAs were used as the model material. Crucial device fabrication steps such as a selective etching process have been developed that is necessary for isolating individual devices on the wafer and interconnecting them with sub-micron scale accuracy. Selective etching of GaSb and GaAs has been developed for isolation of GaSb devices on semi-insulating GaAs substrates. Smooth side wall morphology and desirable depth profile of the etched structures have been accomplished using optimized etching conditions presented in this thesis. Device fabrication of series interconnected GaSb PV cells on a GaAs substrate with single-sided metal contacts has been successfully demonstrated.

  2. Fabrication method for chip-scale-vacuum-packages based on a chip-to-wafer-process

    NASA Astrophysics Data System (ADS)

    Bauer, J.; Weiler, D.; Ruß, M.; Heß, J.; Yang, P.; Voß, J.; Arnold, N.,; Vogt, H.

    2010-10-01

    This paper introduces a simple vacuum packaging method which is based on a Chip-to-Wafer process. The MEMS-device is provided with an electroplated solder frame. A Si-lid with the same solder frame is mounted on each die of the wafer using a flip chip process. The same materials for lid and substrate are used in order to reduce the mechanical stress due to the same thermal coefficients of expansion. The resulting cavity between die and lid can be evacuated and hermetically sealed with an eutectic soldering process. The feasibility of the method is demonstrated with an infrared focal plane array (IR-FPA). In this case, the Si-lid acts as an optical window and contains an anti reflective layer for the 8-14 ?m wavelength area on both sides. The long-term vacuum stability is supported by a getter film inside the package. This method simplifies the sawing process and has the additional cost benefit that it is possible to package only known good dies.

  3. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking

    PubMed Central

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-01-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

  4. Modeling electrodeposition for LIGA microdevice fabrication

    SciTech Connect

    Griffiths, S.K.; Nilson, R.H.; Bradshaw, R.W.

    1998-02-01

    To better understand and to help optimize the electroforming portion of the LIGA process, we have developed one and two-dimensional numerical models describing electrode-position of metal into high aspect-ratio molds. The one-dimensional model addresses dissociation, diffusion, electromigration, and deposition of multiple ion species. The two-dimensional model is limited to a single species, but includes transport induced by forced flow of electrolyte outside the mold and by buoyancy associated with metal ion depletion within the mold. To guide model development and to validate these models, we have also conducted a series of laboratory experiments using a sulfamate bath to deposit nickel in cylindrical molds having aspect ratios up to twenty-five. The experimental results indicate that current densities well in excess of the diffusion-limited currents may still yield metal deposits of acceptable morphology. However, the numerical models demonstrate that such large ion fluxes cannot be sustained by convection within the mold resulting from flow across the mold top. Instead, calculations suggest that the observed enhancement of transport probably results from natural convection within the molds, and that buoyancy-driven flows may be critical to metal ion transport even in micron-scale features having very large aspect ratios. Taking advantage of this enhanced ion transport may allow order-of-magnitude reductions in electroforming times for LIGA microdevice fabrication. 42 refs., 14 figs., 1 tab.

  5. Wafer-scale synthesis of thickness-controllable MoS2 films via solution-processing using a dimethylformamide/n-butylamine/2-aminoethanol solvent system.

    PubMed

    Yang, Jaehyun; Gu, Yeahyun; Lee, Eunha; Lee, Hyangsook; Park, Sang Han; Cho, Mann-Ho; Kim, Yong Ho; Kim, Yong-Hoon; Kim, Hyoungsub

    2015-05-28

    The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates. PMID:25946575

  6. Wafer-scale single-domain-like graphene by defect-selective atomic layer deposition of hexagonal ZnO

    NASA Astrophysics Data System (ADS)

    Park, Kyung Sun; Kim, Sejoon; Kim, Hongbum; Kwon, Deokhyeon; Koo Lee, Yong-Eun; Min, Sung-Wook; Im, Seongil; Choi, Hyoung Joon; Lim, Seulky; Shin, Hyunjung; Koo, Sang Man; Sung, Myung Mo

    2015-10-01

    Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity.Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr05392g

  7. Wafer-scale single-domain-like graphene by defect-selective atomic layer deposition of hexagonal ZnO.

    PubMed

    Park, Kyung Sun; Kim, Sejoon; Kim, Hongbum; Kwon, Deokhyeon; Koo Lee, Yong-Eun; Min, Sung-Wook; Im, Seongil; Choi, Hyoung Joon; Lim, Seulky; Shin, Hyunjung; Koo, Sang Man; Sung, Myung Mo

    2015-10-22

    Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity. PMID:26452020

  8. Wafer-scale fabrication of self-actuated piezoelectric nanoelectromechanical resonators based on lead zirconate titanate (PZT)

    NASA Astrophysics Data System (ADS)

    Dezest, D.; Thomas, O.; Mathieu, F.; Mazenq, L.; Soyer, C.; Costecalde, J.; Remiens, D.; Deü, J. F.; Nicu, L.

    2015-03-01

    In this paper we report an unprecedented level of integration of self-actuated nanoelectromechanical system (NEMS) resonators based on a 150?nm thick lead zirconate titanate (PZT) thin film at the wafer-scale. A top-down approach combining ultraviolet (UV) lithography with other standard planar processing technologies allows us to achieve high-throughput manufacturing. Multilayer stack cantilevers with different geometries have been implemented with measured fundamental resonant frequencies in the megahertz range and Q-factor values ranging from ~130 in air up to ~900 in a vacuum at room temperature. A refined finite element model taking into account the exact configuration of the piezoelectric stack is proposed and demonstrates the importance of considering the dependence of the beam’s cross-section upon the axial coordinate. We extensively investigate both experimentally and theoretically the transduction efficiency of the implemented piezoelectric layer and report for the first time at this integration level a piezoelectric constant of {{d}31}=15 ?fm?V-1. Finally, we discuss the current limitations to achieve piezoelectric detection.

  9. 50 ?m pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis

    NASA Astrophysics Data System (ADS)

    Zhao, C.; Konstantinidis, A. C.; Zheng, Y.; Anaxagoras, T.; Speller, R. D.; Kanicki, J.

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 ?m pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10?mm?1 and a DQE of around 0.5 at spatial frequencies??<1?mm?1. In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5?cm thickness, 50% glandular fraction), 165 ?m microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 ?m microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered.

  10. 50 ?m pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    PubMed

    Zhao, C; Konstantinidis, A C; Zheng, Y; Anaxagoras, T; Speller, R D; Kanicki, J

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 ?m pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10?mm(-1) and a DQE of around 0.5 at spatial frequencies??<1?mm(-1). In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5?cm thickness, 50% glandular fraction), 165 ?m microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 ?m microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered. PMID:26540090

  11. Facile fabrication of wafer-scale MoS2 neat films with enhanced third-order nonlinear optical performance.

    PubMed

    Zhang, Xiaoyan; Zhang, Saifeng; Chang, Chunxia; Feng, Yanyan; Li, Yuanxin; Dong, Ningning; Wang, Kangpeng; Zhang, Long; Blau, Werner J; Wang, Jun

    2015-02-21

    Wafer-scale MoS2 neat films with controllable thicknesses were successfully fabricated by vacuum filtering liquid-exfoliated MoS2 dispersions. The obtained MoS2 filtered thin films were systematically characterized by UV-Vis spectroscopy, Fourier transform infrared spectroscopy (FTIR), Raman spectroscopy, atomic force microscopy (AFM) and scanning electron microscopy (SEM). It was found that the fabricated scalable MoS2 films have a smooth surface and high optical homogeneity verified by AFM and a collimated 532 nm beam, respectively. We investigated the ultrafast nonlinear optical (NLO) properties of the filtered films by an open aperture Z-scan method using 515 and 1030 nm femtosecond laser pulses. Saturable absorption was observed at both 515 and 1030 nm with the figure of merit (FOM) values as ?3.3 × 10(-12) esu cm and ?3.4 × 10(-14) esu cm, respectively. The observation of ultrafast NLO performance of the MoS2 filtered films indicates that vacuum filtration is a feasible method for the fabrication of optical thin films, which can be expanded to fabricate other two-dimensional films from the corresponding dispersions. This easy film fabrication technology will greatly enlarge the application of graphene analogues including graphene in photonic devices, especially of MoS2 as a saturable absorber. PMID:25597818

  12. Wafer-scale synthesis of thickness-controllable MoS2 films via solution-processing using a dimethylformamide/n-butylamine/2-aminoethanol solvent system

    NASA Astrophysics Data System (ADS)

    Yang, Jaehyun; Gu, Yeahyun; Lee, Eunha; Lee, Hyangsook; Park, Sang Han; Cho, Mann-Ho; Kim, Yong Ho; Kim, Yong-Hoon; Kim, Hyoungsub

    2015-05-01

    The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates.The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates. Electronic supplementary information (ESI) available: Optical microscopy image of the spin-coated film, thermogravimetric data of the spin-coating solution, Raman spectra after first- and second-annealing, and AFM images of selected MoS2 films. See DOI: 10.1039/c5nr01486g

  13. Multi scale modeling and simulation for oxygen precipitate behavior in silicon wafer.

    PubMed

    Lee, Sang Hun; Kang, Jeong Won; Kim, Do Hyun

    2011-07-01

    Oxygen precipitates in semiconductor device are generally considered beneficial for its metallic contaminants gettering function, but the oxygen precipitates also affect to degrade the efficiency of solar cell. The formation of oxygen precipitates is closely related to the grown-in defects like oxygen in crystal growth process and heat treatment cycle in device process. Oxygen comes into the silicon melt by dissolving quartz (SiO2) crucible and incorporates into the silicon crystal in Czochralski process. The oxygen plays key role in the formation of oxygen precipitate nuclei in crystal growth process and then the nuclei grow up to be oxygen precipitates in device process. Therefore, the formation of oxygen precipitates is closely related to the crystal growing process and device manufacturing process. In this research, we interpreted the formation and behavior of oxygen precipitates depending on varying oxygen concentrations by using Multi_Scale method. The method is very useful to obtain more reliable interpretation result than other single methods. The validity of this research is verified by comparing with experimental data. PMID:22121643

  14. Slip, Crystal Orientation, and Damage Evolution During Thermal Cycling in High-Strain Wafer-Level Chip-Scale Packages

    NASA Astrophysics Data System (ADS)

    Zhou, Bite; Zhou, Quan; Bieler, Thomas R.; Lee, Tae-kyu

    2015-03-01

    Wafer-level chip-scale package samples with pre-cross-sectioned edge rows were thermally cycled to study microstructure evolution and damage development. Electron backscattered diffraction (EBSD) and high-energy x-ray diffraction were used to obtain Sn grain orientations and the average coefficient of thermal expansion normal to the board in every joint of the package for samples in the as-fabricated and thermally cycled conditions. The results indicated a near-random distribution of joint orientation. Optical, scanning electron microscopy, and EBSD methods were used to characterize microstructure changes in pre-cross-sectioned samples due to thermal cycling. Slip trace analysis and Orientation Imaging Microscopy™ (OIM) show that slip systems with high Schmid factors (estimated global shear stress based on the package neutral point) are responsible for the observed microstructure evolution during thermal cycling, which provides information about slip systems that are more easily activated. Two joints were analyzed in detail to evaluate slip activity at different stages of their thermal history. The first case showed that a solidification twin grain boundary misorientation deviated from the twin relationship due to slip activity during thermal cycling, which can influence damage development and the path of crack propagation. The second case showed a new grain orientation developing due to gradual lattice rotation about the Sn [110] axis by a continuous recrystallization mechanism. This rotation was correlated with the operation of slip system . Small tin whiskers emerged from the initially polished chip interface and grew with increasing thermal cycles until a crack developed in the solder that relieved the stress. As the local stresses are not known experimentally, this analysis provides observations that can be compared with a crystal plasticity model simulation.

  15. 1144 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 10, OCTOBER 2007 Wafer-Level Modular Testing of Core-Based SoCs

    E-print Network

    Chakrabarty, Krishnendu

    2007 Wafer-Level Modular Testing of Core-Based SoCs Sudarshan Bahukudumbi, Student Member, IEEECs. To reduce packaging cost and the test cost for pack- aged chips, wafer-level testing (wafer sort) is used constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can

  16. Laser wafering for silicon solar.

    SciTech Connect

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  17. Imaging ATUM ultrathin section libraries with WaferMapper: a multi-scale approach to EM reconstruction of neural circuits

    PubMed Central

    Hayworth, Kenneth J.; Morgan, Josh L.; Schalek, Richard; Berger, Daniel R.; Hildebrand, David G. C.; Lichtman, Jeff W.

    2014-01-01

    The automated tape-collecting ultramicrotome (ATUM) makes it possible to collect large numbers of ultrathin sections quickly—the equivalent of a petabyte of high resolution images each day. However, even high throughput image acquisition strategies generate images far more slowly (at present ~1 terabyte per day). We therefore developed WaferMapper, a software package that takes a multi-resolution approach to mapping and imaging select regions within a library of ultrathin sections. This automated method selects and directs imaging of corresponding regions within each section of an ultrathin section library (UTSL) that may contain many thousands of sections. Using WaferMapper, it is possible to map thousands of tissue sections at low resolution and target multiple points of interest for high resolution imaging based on anatomical landmarks. The program can also be used to expand previously imaged regions, acquire data under different imaging conditions, or re-image after additional tissue treatments. PMID:25018701

  18. Versatile Wafer-Scale Technique for the Formation of Ultrasmooth and Thickness-Controlled Graphene Oxide Films Based on Very Large Flakes.

    PubMed

    Azevedo, Joël; Campidelli, Stéphane; He, Delong; Cornut, Renaud; Bertucchi, Michael; Sorgues, Sébastien; Benattar, Jean-Jacques; Colbeau-Justin, Christophe; Derycke, Vincent

    2015-09-30

    We present a new strategy to form thickness-adjusted and ultrasmooth films of very large and unwrinkled graphene oxide (GO) flakes through the transfer of both hemispherical and vertical water films stabilized by surfactants. With its versatility in terms of substrate type (including flexible organic substrates) and in terms of flake density (from isolated flakes to continuous and multilayer films), this wafer-scale assembly technique is adapted to a broad range of experiments involving GO and rGO (reduced graphene oxide). We illustrate its use through the evaluation of transparent rGO electrodes. PMID:26348321

  19. Ultrathin silicon wafer bonding: Physics and applications

    NASA Astrophysics Data System (ADS)

    Beggans, Michael Howard

    Ultrathin silicon wafer bonding is an emerging process that simplifies device fabrication, reduces manufacturing costs, increases yield, and allows the realization of novel devices. Ultrathin silicon wafers are between 3 and 200 microns thick with all the same properties of the thicker silicon wafers (greater than 300 microns) normally used by the semiconductor electronics industry. Wafer bonding is one technique by which multiple layers are formed. In this thesis, the history and practice of wafer bonding is described and applied to the manufacture of microelectomechanical systems (MEMS) devices with layer thickness on the scale of microns. Handling and processing problems specific to ultrathin silicon wafers and their bonding are addressed and solved. A model that predicts the conformal nature of these flexible silicon wafers and its impact on bonding is developed in terms of a relatively new description of surface quality, the Power Spectral Density (PSD). A process for reducing surface roughness of silicon is elucidated and a model of this process is described. A method of detecting particle contamination in chemical baths and other processes using wafer bonding is detailed. A final section highlights some recent work that has used ultrathin silicon wafer bonding to fabricate MEMS devices that have reduced existing design complexity and made possible novel, and otherwise difficult to produce, sensors. A new fabrication process that can reduce the required time for "proof-of-principle" devices using ultrathin silicon wafers is also described.

  20. Large-area, wafer-scale epitaxial growth of germanium on silicon and integration of high-performance transistors

    NASA Astrophysics Data System (ADS)

    Ghosh, Swapnadip

    Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the ˜105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress simulation shows that the oval air gaps around the SiO2 template can reduce the thermal stress by 50% and help reduce the DD. We have then compared the structural and electrical characteristics of n-type Ge films with its p-type counter parts. In n-type Ge, the DD decreases from ˜109cm-2 near the Ge-Si interface to ˜105 cm-2 at the film surface. In contrast, we observe 5x107 cm-2 TDD at the film surface in p-type Ge. The full width at half-maximum for our n-type Ge(004) XRD peak is ~70% narrower than that of p-type Ge. As a stringent test of the dislocation reduction, we have also fabricated and characterized high-carrier-mobility MOSFETs on GoS substrates. We also report p- and n-MOSFETs with microeff of 401 and 940 cm2/V-s and a subthreshold slope of 100 and 200 mV/decade, respectively. These effective mobilities show an exceptional 82 and 30% improvement over that of conventional Si channel MOSFETs. We also investigate the optical quality of ultra-low DD GoS film by measuring photoluminescence (PL). The n-type Ge PL main peak shows pronounced tensile-strain (x0.8%) than that of p-type which is an indicator of direct BG shrinking at the \\Gcy band-edge. Going beyond epitaxial engineering and device fabrication, we have also recently demonstrated a scalable path to create a 2D array of Ge quantum dots (QDs) on responsive SiGe substrates based on elastic mechanical deformation and subsequent SiGe compositional redistribution, coupled with MBE growth. For large-scale manufacturing of single-electron transistors, we have also demonstrated that a spatially structured elastic compressive stress to the SiGe substrate with thermally annealing leads to a compositional redistribution of Si and Ge in the near-surface region of SiGe substrates, forming a 2D array of Ge-depleted nanoscale regions. Based on these latest findings, we have also begun to chart a future direction for my research group, where one can explore new advanced device architectures, such as Si-compatible, optically actuated, Ge-quantum dot-based field effect transistors.

  1. Wafer-scale double-layer stacked Au/Al2O3@Au nanosphere structure with tunable nanospacing for surface-enhanced Raman scattering.

    PubMed

    Hu, Zhaosheng; Liu, Zhe; Li, Lin; Quan, Baogang; Li, Yunlong; Li, Junjie; Gu, Changzhi

    2014-10-15

    Fabricating perfect plasmonic nanostructures has been a major challenge in surface enhanced Raman scattering (SERS) research. Here, a double-layer stacked Au/Al2O3@Au nanosphere structures is designed on the silicon wafer to bring high density, high intensity "hot spots" effect. A simply reproducible high-throughput approach is shown to fabricate feasibly this plasmonic nanostructures by rapid thermal annealing (RTA) and atomic layer deposition process (ALD). The double-layer stacked Au nanospheres construct a three-dimensional plasmonic nanostructure with tunable nanospacing and high-density nanojunctions between adjacent Au nanospheres by ultrathin Al2O3 isolation layer, producing highly strong plasmonic coupling so that the electromagnetic near-field is greatly enhanced to obtain a highly uniform increase of SERS with an enhancement factor (EF) of over 10(7). Both heterogeneous nanosphere group (Au/Al2O@Ag) and pyramid-shaped arrays structure substrate can help to increase the SERS signals further, with a EF of nearly 10(9). These wafer-scale, high density homo/hetero-metal-nanosphere arrays with tunable nanojunction between adjacent shell-isolated nanospheres have significant implications for ultrasensitive Raman detection, molecular electronics, and nanophotonics. PMID:24995658

  2. In-Situ Investigation of Wafer-Slurry-Pad Interactions during CMP , A. Mueller

    E-print Network

    White, Robert D.

    In-Situ Investigation of Wafer-Slurry-Pad Interactions during CMP N. Braun 1 , C. Gray 1 , A) including slurry film thickness and flow, wafer-pad contact, wafer- scale friction, and small-scale shear measurements were taken on a modified Struers RotoPol-31 table top polisher in which the wafer carrier has been

  3. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 ?m SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  4. Optical measurement of LIGA milliengine performance

    NASA Astrophysics Data System (ADS)

    Dickey, Fred M.; Holswade, Scott C.; Christenson, Todd R.; Garcia, Ernest J.; Polosky, Marc A.

    1998-03-01

    Understanding the parameters that affect the performance of milliscale and microscale actuators is essential to the development of optimized designs and fabrication processes, as well as the qualification of devices for commercial applications. This paper discusses the development of optical techniques for motion measurements of LIGA fabricated milliengines. LIGA processing permits the fabrication of precision millimeter-sized machine elements that cannot be fabricated by conventional miniature machining techniques because of their small feature sizes. In addition, tolerances of 1 part in 103 to 104 may be maintained in millimeter sized components with this processing technique. Optical techniques offer a convenient means for measuring long term statistical performance data and transient responses needed to optimize designs and manufacturing techniques. Optical techniques can also be used to provide feedback signals needed for control and sensing of the state of the machine. Optical probe concepts and experimental data obtained using a milliengine developed at Sandia National Laboratories are presented.

  5. High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth.

    PubMed

    Miao, Xin; Chabak, Kelson; Zhang, Chen; Mohseni, Parsian K; Walker, Dennis; Li, Xiuling

    2015-05-13

    Wafer-scale defect-free planar III-V nanowire (NW) arrays with ?100% yield and precisely defined positions are realized via a patterned vapor-liquid-solid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 10(4), 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 × 1.5 cm(2) chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics. PMID:25494481

  6. LigaSure Hemorrhoidectomy for Symptomatic Hemorrhoids: First Pediatric Experience.

    PubMed

    Grossmann, Ole; Soccorso, Giampiero; Murthi, Govind

    2015-08-01

    Hemorrhoids are uncommon in children. Third and fourth degree symptomatic hemorrhoids may be surgically excised. We describe the first experience of using LigaSure (Covidien, Mansfield, Massachusetts, United States) to perform hemorrhoidectomies in children. LigaSure hemorrhoidectomy has been well described in adults and is found to be superior in patient tolerance as compared with conventional hemorrhoidectomy. PMID:24918403

  7. Solution structure of leptospiral LigA4 Big domain.

    PubMed

    Mei, Song; Zhang, Jiahai; Zhang, Xuecheng; Tu, Xiaoming

    2015-11-13

    Pathogenic Leptospiraspecies express immunoglobulin-like proteins which serve as adhesins to bind to the extracellular matrices of host cells. Leptospiral immunoglobulin-like protein A (LigA), a surface exposed protein containing tandem repeats of bacterial immunoglobulin-like (Big) domains, has been proved to be involved in the interaction of pathogenic Leptospira with mammalian host. In this study, the solution structure of the fourth Big domain of LigA (LigA4 Big domain) from Leptospira interrogans was solved by nuclear magnetic resonance (NMR). The structure of LigA4 Big domain displays a similar bacterial immunoglobulin-like fold compared with other Big domains, implying some common structural aspects of Big domain family. On the other hand, it displays some structural characteristics significantly different from classic Ig-like domain. Furthermore, Stains-all assay and NMR chemical shift perturbation revealed the Ca(2+) binding property of LigA4 Big domain. PMID:26449456

  8. Final-part metrology for LIGA springs, Build Group 1.

    SciTech Connect

    Aigeldinger, Georg; Skala, Dawn M.; Ceremuga, Joseph T.; Mills, Bernice E.

    2004-03-01

    The LIGA spring is a recently designed part for defense program applications. The Sandia California LIGA team has produced an initial group build of these nickel alloy parts. These are distinctive in having a macroscopic lateral size of about 1 cm, while requiring microscopic dimensional precision on the order of a few micrometers. LIGA technology capabilities at Sandia are able to manufacture such precise structures. While certain aspects of the LIGA process and its production capabilities have been dimensionally characterized in the past, [1-6] the present work is exclusive in defining a set of methods and techniques to inspect and measure final LIGA nickel alloy parts in large prototype quantities. One hundred percent inspection, meaning that every single LIGA part produced needs to be measured, ensures quality control and customer satisfaction in this prototype production run. After a general visual inspection of the parts and an x-ray check for voids, high precision dimensional metrology tools are employed. The acquired data is analyzed using both in house and commercially available software. Examples of measurements illustrating these new metrology capabilities are presented throughout the report. These examples furthermore emphasize that thorough inspection of every final part is not only essential to characterize but also improve the LIGA manufacturing process.

  9. Wafer characteristics via reflectometry

    SciTech Connect

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  10. Wafer level reliability testing: An idea whose time has come

    NASA Technical Reports Server (NTRS)

    Trapp, O. D.

    1987-01-01

    Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

  11. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  12. Wafer scale micromachine assembly method

    DOEpatents

    Christenson, Todd R. (Albuquerque, NM)

    2001-01-01

    A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.

  13. Cantilevered multilevel LIGA devices and methods

    DOEpatents

    Morales, Alfredo Martin (Pleasanton, CA); Domeier, Linda A. (Danville, CA)

    2002-01-01

    In the formation of multilevel LIGA microstructures, a preformed sheet of photoresist material, such as polymethylmethacrylate (PMMA) is patterned by exposure through a mask to radiation, such as X-rays, and developed using a developer to remove the exposed photoresist material. A first microstructure is then formed by electroplating metal into the areas from which the photoresist has been removed. Additional levels of microstructure are added to the initial microstructure by covering the first microstructure with a conductive polymer, machining the conductive polymer layer to reveal the surface of the first microstructure, sealing the conductive polymer and surface of the first microstructure with a metal layer, and then forming the second level of structure on top of the first level structure. In such a manner, multiple layers of microstructure can be built up to allow complex cantilevered microstructures to be formed.

  14. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  15. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

  16. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  17. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  18. Etching Of Semiconductor Wafer Edges

    DOEpatents

    Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

    2003-12-09

    A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

  19. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  20. Laser-LIGA for Ni microcantilevers

    NASA Astrophysics Data System (ADS)

    Jin, Hengyi; Harvey, Erol C.; Hayes, Jason P.; Ghantasala, Muralidhar K.; Fu, Yao; Jolic, Karlo; Solomon, Matthew; Graves, Kynan

    2002-11-01

    This paper presents our design and experimental results of nickel microcantilevers, which were fabricated using a laser-LIGA process, based on KrF (248 nm) excimer laser micromachining. A chrome-on-quartz mask, containing the desired mask patterns was prepared for this work. The substrate of copper (30 ?m thick) clad printed circuit board (PCB) was laminated with Laminar 5038 photopolymer to be laser patterned. Following laser patterning and laser cleaning, all the samples were electroformed with nickel on top of the copper layer. To release the Ni microcantilevers, the excimer laser was employed again to remove the polymer in the localised area to facilitate Cu selective etching. Here, copper acted as the sacrificial layer as well. The Cu selective etching was carried out with ~ 20 % (wt) aqueous solution of ammonium persulfate. Because the Cu selective etching is isotropic, some undercuts happened next to the anchor area. The samples were characterised using optical microscope, confocal laser scanning microscope and SEM, and some of Ni cantilevers were tested electro-thermally. Their performance was analyzed with respect to the simulation results.

  1. Recent Developments in Microsystems Fabricated by the Liga-Technique

    NASA Technical Reports Server (NTRS)

    Schulz, J.; Bade, K.; El-Kholi, A.; Hein, H.; Mohr, J.

    1995-01-01

    As an example of microsystems fabricated by the LIGA-technique (x-ray lithography, electroplating and molding), three systems are described and characterized: a triaxial acceleration sensor system, a micro-optical switch, and a microsystem for the analysis of pollutants. The fabrication technologies are reviewed with respect to the key components of the three systems: an acceleration sensor, and electrostatic actuator, and a spectrometer made by the LIGA-technique. Aa micro-pump and micro-valve made by using micromachined tools for molding and optical fiber imaging are made possible by combining LIGA and anisotropic etching of silicon in a batch process. These examples show that the combination of technologies and components is the key to complex microsystems. The design of such microsystems will be facilitated is standardized interfaces are available.

  2. Torsion Testing of Diffusion Bonded LIGA Formed Nickel

    SciTech Connect

    Buchheit, T.E.; Christenson, T.R.; Schmale, D.T.

    1999-01-27

    A test technique has been devised which is suitable for the testing of the bond strength of batch diffusion bonded LIGA or DXRL defined structures. The method uses a torsion tester constructed with the aid of LIGA fabrication and distributed torsion specimens which also make use of the high aspect ratio nature of DXRL based processing. Measurements reveal achieved bond strengths of 130MPa between electroplated nickel with a bond temperature of 450 C at 7 ksi pressure which is a sufficiently low temperature to avoid mechanical strength degradation.

  3. Great enhancement in the excitonic recombination and light extraction of highly ordered InGaN/GaN elliptic nanorod arrays on a wafer scale

    NASA Astrophysics Data System (ADS)

    Zhuang, Zhe; Guo, Xu; Liu, Bin; Hu, Fengrui; Dai, Jiangping; Zhang, Yun; Li, Yi; Tao, Tao; Zhi, Ting; Xie, Zili; Ge, Haixiong; Wang, Xiaoyong; Xiao, Min; Wang, Tao; Shi, Yi; Zheng, Youdou; Zhang, Rong

    2016-01-01

    A series of highly ordered c-plane InGaN/GaN elliptic nanorod (NR) arrays were fabricated by our developed soft UV-curing nanoimprint lithography on a wafer. The photoluminescence (PL) integral intensities of NR samples show a remarkable enhancement by a factor of up to two orders of magnitude compared with their corresponding as-grown samples at room temperature. The radiative recombination in NR samples is found to be greatly enhanced due to not only the suppressed non-radiative recombination but also the strain relaxation and optical waveguide effects. It is demonstrated that elliptic NR arrays improve the light extraction greatly and have polarized emission, both of which possibly result from the broken structure symmetry. Green NR light-emitting diodes have been finally realized, with good current–voltage performance and uniform luminescence.

  4. Great enhancement in the excitonic recombination and light extraction of highly ordered InGaN/GaN elliptic nanorod arrays on a wafer scale.

    PubMed

    Zhuang, Zhe; Guo, Xu; Liu, Bin; Hu, Fengrui; Dai, Jiangping; Zhang, Yun; Li, Yi; Tao, Tao; Zhi, Ting; Xie, Zili; Ge, Haixiong; Wang, Xiaoyong; Xiao, Min; Wang, Tao; Shi, Yi; Zheng, Youdou; Zhang, Rong

    2016-01-01

    A series of highly ordered c-plane InGaN/GaN elliptic nanorod (NR) arrays were fabricated by our developed soft UV-curing nanoimprint lithography on a wafer. The photoluminescence (PL) integral intensities of NR samples show a remarkable enhancement by a factor of up to two orders of magnitude compared with their corresponding as-grown samples at room temperature. The radiative recombination in NR samples is found to be greatly enhanced due to not only the suppressed non-radiative recombination but also the strain relaxation and optical waveguide effects. It is demonstrated that elliptic NR arrays improve the light extraction greatly and have polarized emission, both of which possibly result from the broken structure symmetry. Green NR light-emitting diodes have been finally realized, with good current-voltage performance and uniform luminescence. PMID:26595508

  5. Multi-Wafer Virtual Probe: Minimum-Cost Variation Characterization by Exploring Wafer-to-Wafer Correlation

    E-print Network

    Li, Xin

    Multi-Wafer Virtual Probe: Minimum-Cost Variation Characterization by Exploring Wafer-to-Wafer In this paper, we propose a new technique, referred to as Multi- Wafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Towards this goal, a novel Bayesian

  6. Development of a LIGA-based elastodynamic flying mechanism

    NASA Astrophysics Data System (ADS)

    Cox, Adam G.; Garcia, Ephrahim

    1998-07-01

    With the emergence of MEMS and LIGA technology piezoceramics can be integrated to create tiny solid state devices. The precision motion that piezoelectric materials can provide is complimented by the tolerances that can be achieved through MEMS and LIGA micromachining. The integration of these two technologies is ideal for microactuation. A LIGA based devices has been developed that is capable of amplifying small motions from a piezoelectric element into an output stroke angle large enough to produce flight. Micro flight is a difficult aerodynamic problem. With small wing areas conventional lift requires velocities that are difficult to achieve. However it is possible to induce lift using drag in the same manner as some birds and insects. Flapping is a highly efficient way to produce flight. For sustained low energy flight both insects and birds use a complex elastodynamic system that only requires them to excite it at its natural frequency. The actuation device presented is based on the same flight principle of insects and birds, a resonating elastodynamic system excited at its natural frequency or at a lower harmonic. This allows for long distance flights that require little energy. Piezoceramics posses a high energy level and force output that can excite the device and induce a flapping motion. The dynamics of the system rely on the LIGA flexure mechanism, the piezoelectric element, as well as the aerodynamic interaction of the wing and the air which is a complex nonlinear problem.

  7. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  8. Wafer to wafer overlay control algorithm implementation based on statistics

    NASA Astrophysics Data System (ADS)

    Lee, Byeong Soo; Kang, Young Seog; Kong, Jeong Heung; Hwang, Hyun Woo; Song, Myeong Gyu

    2015-03-01

    For mass production of DRAM device, a stable and effective overlay control becomes more and more important as DRAM design rule shrinks. Existent technologies were already applied to overcome this situation. Nevertheless, we are still suffered from tight overlay margin and forced to move from lot-based to wafer-based overlay control. However, the wafer-based control method requires a huge amount of measurement resource. In this paper, we present the insight for the wafer-based overlay correction with optimal measurement resource which is suitable for mass production. The experiment which is the wafer-based overlay correction by several statistical analyses carried out for 2X nm node DRAM. Among them, linear regression is a strong candidate for wafer-based overlay control, which improved up to 0.8 nm of maximum overlay.

  9. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  10. Silicon cast wafer recrystallization for photovoltaic applications

    E-print Network

    Hantsoo, Eerik T. (Eerik Torm)

    2008-01-01

    Current industry-standard methods of manufacturing silicon wafers for photovoltaic (PV) cells define the electrical properties of the wafer in a first step, and then the geometry of the wafer in a subsequent step. The ...

  11. System for slicing wafers

    NASA Technical Reports Server (NTRS)

    1982-01-01

    A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

  12. System for slicing wafers

    NASA Astrophysics Data System (ADS)

    1982-02-01

    A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

  13. Wafer-Level Thermocompression Bonds

    E-print Network

    Tsau, Christine H.

    Thermocompression bonding of gold is a promising technique for achieving low temperature, wafer-level bonding without the application of an electric field or complicated pre-bond cleaning procedure. The presence of a ductile ...

  14. Spinner For Etching Of Semiconductor Wafers

    NASA Technical Reports Server (NTRS)

    Lombardi, Frank

    1989-01-01

    Simple, inexpensive apparatus coats semiconductor wafers uniformly with hydrofluoric acid for etching. Apparatus made in part from small commercial electric-fan motor. Features bowl that collects acid. Silicon wafer placed on platform and centered on axis; motor switched on. As wafer spins, drops of hydrofluoric acid applied from syringe. Centrifugal force spreads acid across wafer in fairly uniform sheet.

  15. Wafer handling and placement tool

    DOEpatents

    Witherspoon, Linda L. (22 Cottonwood La., Los Lunas, NM 87031)

    1988-01-05

    A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

  16. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    PubMed

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

  17. Development of Megasonic cleaning for silicon wafers. Final report

    SciTech Connect

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  18. Computational Modeling in Plasma Processing for 300 mm Wafers

    NASA Technical Reports Server (NTRS)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  19. Role of oxide thickening in fatigue crack initiation in LIGA nickel MEMS thin films

    E-print Network

    Shan, Wanliang

    Role of oxide thickening in fatigue crack initiation in LIGA nickel MEMS thin films W.L. Shan a 2012 Accepted 16 October 2012 Available online 24 October 2012 Keywords: LIGA Ni MEMS thin films Oxide micro-electro-mechanical-systems (MEMS) structures. & 2012 Elsevier B.V. All rights reserved. 1

  20. Wafer-Scale Precise Patterning of Organic Single-Crystal Nanowire Arrays via a Photolithography-Assisted Spin-Coating Method.

    PubMed

    Deng, Wei; Zhang, Xiujuan; Wang, Liang; Wang, Jincheng; Shang, Qixun; Zhang, Xiaohong; Huang, Liming; Jie, Jiansheng

    2015-12-01

    A photolithography-assisted spin-coating approach is developed to produce single-crystal organic nanowire (NW) arrays at designated locations with high precision and high efficiency. This strategy enables the large-scale fabrication of organic NW arrays with nearly the same accuracy, reliability, and flexibility as photolithography. The high mobilities of the organic NWs enable the control of the switch of multicolored light-emitting devices with good stability. PMID:26460612

  1. Wafer characteristics via reflectometry and wafer processing apparatus and method

    DOEpatents

    Sopori, Bhushan L. (Denver, CO)

    2007-07-03

    An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

  2. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    SciTech Connect

    Bajikar, Sateesh S.; DeCarlo, Francesco; Song, Joshua J.

    1998-05-22

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized from pyromellitic anhydride and oxydianiline (PMDA-ODA).

  3. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    DOEpatents

    Bajikar, Sateesh S.; De Carlo, Francesco; Song, Joshua J.

    2004-01-27

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  4. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    DOEpatents

    Bajikar, Sateesh S. (San Jose, CA); De Carlo, Francesco (Darien, IL); Song, Joshua J. (Naperville, IL)

    2001-01-01

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  5. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  6. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R. (Berkeley, CA)

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  7. Characterization of Sidewall and Planar Surfaces of Electroformed LIGA Parts

    SciTech Connect

    PRASAD,SOMURI V.; HALL,AARON C.; DUGGER,MICHAEL T.

    2000-10-01

    The nature of surfaces and the way they interact with each other during sliding contact can have a direct bearing on the performance of a microelectromechanical (MEMS) device. Therefore, a study was undertaken to characterize the surfaces of LIGA fabricated Ni and Cu components. Sidewall and planar surfaces were examined by scanning electron microscopy (SEM) and atomic force microscopy (AFM). Surface roughness was quantified using the AFM. Post-processing (e.g. lapping, removal of polymer film) can profoundly influence the morphology of LIGA components. Edge rounding and smearing of ductile materials during lapping can result in undesirable sidewall morphologies. By judicious selection of AFM scan sizes, the native roughness ({approximately}10 nm RMS) can be distinguished from that arising due to post processing, e.g. scratches, debris, polymer films. While certain processing effects on morphology such as those due to lapping or release etch can be controlled, the true side wall morphology appears to be governed by the morphology of the polymer mold or by the electroforming process itself, and may be much less amenable to modification.

  8. GEM-type detectors using LIGA and etchable glass technologies

    SciTech Connect

    Ahn, S.K.; Kim, J.G.; Perez-Mendez, V.; Chang, S.; Jackson, K.H.; Kadyk, J.A.; Wenzel, W.A.; Cho, G.

    2001-11-02

    Gas electron multipliers (GEMS) have been made by a deep X-ray lithography technique (LIGA process) using synchrotron radiation on polymethylmethacrylate (PMMA) and by UV processes using a UV etchable glass. Gain, stability and rate capability for these detectors are described.The LIGA detectors described consist of PMMA sheets of various thicknesses, 125mm to 350mm, and have 150mm x 150mm square holes spaced with a pitch of 300mm. Thin copper electrodes are plated on the top and bottom surfaces using a Damascene method, followed by electroless plating of the copper onto a palladium-tin base layer. For various thicknesses of PMMA measurements have been made of absolute gain vs. voltage, time stability of gain, and rate capability. The operating gas mixture was usually Ar/CO2 (70/30) gas, but some tests were also done using P10 gas. We also made GEM-like detectors using the UV etchable glass called Foturan, patterned by exposure to UV light and subsequent etching. A few measurements using these detectors will be reported, including avalanche gain and time stability.

  9. Smoother Scribing of Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Danyluk, S.

    1986-01-01

    Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

  10. Wafer bonding for optoelectronic devices

    NASA Astrophysics Data System (ADS)

    Wu, Yew-Chung Sermon

    A periodic GaAs wafer-bonded structure has been proposed for quasi-phase-matched (QPM) second harmonic generation (SHG). The basic bonding technology involves elevated temperatures and pressures, which can lead to unacceptable optical losses and poor device performance. Three sources of optical losses were first found in this study: (1) decomposition at the exposed surface, (2) interfacial defects between the bonded wafers, and (3) bulk defects within the wafers. Bulk and surface defects were studied by measuring the optical transmission through single GaAs. It was found that an increase in bonding temperature and/or time led to an increase in the bulk and surface defects. An increase in the free hole concentration (thermal conversion) is though to be the major cause of the optical losses by a free carrier absorption mechanism. Since it was difficult to eliminate free-carrier and interfacial defect losses once they have formed because of diffusion kinetic limitations, processing conditions that minimized their formation were sought. In contrast, defects on the external surfaces caused by arsenic depletion resulting from incongruent evaporation were easily eliminated by repolishing. Interfacial defects were studied by introducing artificial voids into the interface region by bonding topographically-patterned GaAs wafers to unpatterned wafers. We found that the filling of these artificial voids depended strongly on the magnitude of the height of the surface irregularities on the wafer interfaces, as well as on temperature and time. Typically, when bonding temperature and time were increased, the interfacial defect density decreased. After bonding, two kinds of features corresponding to the newly bonded areas were observed by IR microscopy. These two features, having diamond and dendrite geometries, were shown to depend on both surface energy anisotropy and growth rate anisotropy. An investigation of the relationship between bonding conditions (temperature, time and pressure) and optical losses (resulting from bulk, interfacial and surface defects), has led to the development of an optimized process for preparing periodic GaAs structures useful in quasi-phase-matched second harmonic generation applications. With this bonding process, low optical loss (~0.1-0.3%/interface) wafer-bonded (110) structures (containing up to 40 layers) for practical device applications were first fabricated in this study.

  11. LIGA-based microsystem manufacturing:the electrochemistry of through-mold depostion and material properties.

    SciTech Connect

    Kelly, James J.; Goods, Steven Howard

    2005-06-01

    The report presented below is to appear in ''Electrochemistry at the Nanoscale'', Patrik Schmuki, Ed. Springer-Verlag, (ca. 2005). The history of the LIGA process, used for fabricating dimensional precise structures for microsystem applications, is briefly reviewed, as are the basic elements of the technology. The principal focus however, is on the unique aspects of the electrochemistry of LIGA through-mask metal deposition and the generation of the fine and uniform microstructures necessary to ensure proper functionality of LIGA components. We draw from both previously published work by external researchers in the field as well as from published and unpublished studies from within Sandia.

  12. NREL Core Program; Session: Wafer Silicon (Presentation)

    SciTech Connect

    Wang, Q.

    2008-04-01

    This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

  13. APPLIED PHYSICS REVIEWSFOCUSED REVIEW Adhesive wafer bonding

    E-print Network

    Lü, James Jian-Qiang

    APPLIED PHYSICS REVIEWS­FOCUSED REVIEW Adhesive wafer bonding F. Niklausa Microsystem Technology 9 February 2006 Wafer bonding with intermediate polymer adhesives is an important fabrication-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive

  14. Silicon Wafer Processing Dr. Seth P. Bates

    E-print Network

    Colton, Jonathan S.

    Silicon Wafer Processing Dr. Seth P. Bates Applied Materials Summer, 2000 Objective To provide from blank silicon wafers. Goals The Transfer Plan provides a curriculum covering the process of manufacturing integrated circuits from the silicon wafer blanks, using the equipment manufactured by Applied

  15. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  16. Accurate surface profilometry of ultrathin wafers

    NASA Astrophysics Data System (ADS)

    Weeks, A. E.; Litwin, D.; Galas, J.; Surma, B.; Piatkowski, B.; MacLaren, D. A.; Allison, W.

    2007-09-01

    Geometric characterization of 50 mm diameter, 50 µm thick single-crystal Si(1 1 1) wafers has been performed using complementary methods: industry-standard capacitance measurements of warp and total thickness variation (TTV), and a technique we term scanned chromatic confocal profilometry (SCCP). We compare the measurements made by the two techniques and demonstrate the limitations of capacitance measurements when applied to ultrathin wafers. The two-dimensional SCCP measurements are shown to enhance the description of wafer thickness variations beyond that generated by the standard test method. We discuss a Fourier transform-based analysis and show it to be useful in wafer quality assessment. Adding a summary of spatial frequencies in a wafer's thickness map to the conventional measures of warp and TTV provides a more complete summary of the salient features of a wafer's geometry.

  17. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    DOEpatents

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  18. Wafer Resection of the Distal Ulna.

    PubMed

    Griska, Adam; Feldon, Paul

    2015-11-01

    The wafer procedure is an effective treatment for ulnar impaction syndrome, which decompresses the ulnocarpal junction through a limited open or arthroscopic approach. In comparison with other common decompressive procedures, the wafer procedure does not require bone healing or internal fixation and also provides excellent exposure of the proximal surface of the triangular fibrocartilage complex. Results of the wafer procedure have been good and few complications have been reported. PMID:26518323

  19. Effect of Wafer Bow and Etch Patterns in Direct Wafer Bonding

    E-print Network

    Spearing, S. Mark

    Direct wafer bonding has been identified as an en-abling technology for microelectromechanical systems (MEMS). As the complexity of devices increase and the bonding of multiple patterned wafers is required, there is a need ...

  20. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  1. Wafer level reliability for high-performance VLSI design

    NASA Technical Reports Server (NTRS)

    Root, Bryan J.; Seefeldt, James D.

    1987-01-01

    As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

  2. Process 2.1 Handle Wafer Bonding For Etch Processing

    E-print Network

    Healy, Kevin Edward

    Process 2.1 Handle Wafer Bonding For Etch Processing 1.0 Process Summary 1.1 Certain processes in the Nanolab require handle or breakthrough wafers to handle exotic substrates or through wafer processing. Reversible bonding attaches chips and wafers to these handle wafers with a secure bond that can handle robust

  3. On Optimizing Test Cost for Wafer-to-Wafer 3D-Stacked ICs Mottaqiallah Taouil Said Hamdioui

    E-print Network

    On Optimizing Test Cost for Wafer-to-Wafer 3D-Stacked ICs Mottaqiallah Taouil Said Hamdioui to manufacture such 3D-SICs. Wafer-to-Wafer (W2W) stacking seems the most favorable approach when high manufacturing throughput, thinned wafers and small die handling is required. However, efficient and optimal test

  4. On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs Mottaqiallah Taouil1

    E-print Network

    On Maximizing the Compound Yield for 3D Wafer-to-Wafer Stacked ICs Mottaqiallah Taouil1 Said, and lower power consumption compared to planar ICs. Fabricating these 3D-SICs using Wafer-to- Wafer (W2W) stacking has several advantages including: high throughput, thin wafer and small die handling, and high TSV

  5. An aluminum resist substrate for microfabrication by LIGA.

    SciTech Connect

    Kelly, James J.; Boehme, Dale R.; Hauck, Cheryl A.; Yang, Chu-Yeu Peter; Hunter, Luke L.; Griffiths, Stewart K.; McLean, Dorrance E.; Aigeldinger, Georg; Hekmaty, Michelle A.; Hachman, John T.; Losey, Matthew W.; Skala, Dawn M.; Korellis, John S.; Friedmann, Thomas Aquinas; Yang, Nancy Y. C.; Lu, Wei-Yang

    2005-04-01

    Resist substrates used in the LIGA process must provide high initial bond strength between the substrate and resist, little degradation of the bond strength during x-ray exposure, acceptable undercut rates during development, and a surface enabling good electrodeposition of metals. Additionally, they should produce little fluorescence radiation and give small secondary doses in bright regions of the resist at the substrate interface. To develop a new substrate satisfying all these requirements, we have investigated secondary resist doses due to electrons and fluorescence, resist adhesion before exposure, loss of fine features during extended development, and the nucleation and adhesion of electrodeposits for various substrate materials. The result of these studies is a new anodized aluminum substrate and accompanying methods for resist bonding and electrodeposition. We demonstrate successful use of this substrate through all process steps and establish its capabilities via the fabrication of isolated resist features down to 6 {micro}m, feature aspect ratios up to 280 and electroformed nickel structures at heights of 190 to 1400 {micro}m. The minimum mask absorber thickness required for this new substrate ranges from 7 to 15 {micro}m depending on the resist thickness.

  6. Methane production using resin-wafer electrodeionization

    SciTech Connect

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  7. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Rhee, S. S.

    1979-01-01

    Several aspects of silicon wafer surface texturizing were studied. A low cost cleaning method that utilizes recycled Freon in an ultrasonic vapor degreaser to remove organic and inorganic contaminants from the surface of silicon wafers as received from silicon suppliers was investigated. The use of clean dry air and high throughout wafer batch drying techniques was shown to lower the cost of wafer drying. A two stage texturizing process was examined for suitability in large scale production. Also, an in-depth gettering study with the two stage texturizing process was performed for the enhancement of solar cell efficiency, minimization of current versus voltage curve dispersion, and improvement in process reproducibility. The 10% efficiency improvement goal was exceeded for the near term implementation of flat plate photovoltaic cost reduction.

  8. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  9. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  10. The Imaging Properties of a Silicon Wafer X-Ray Telescope

    NASA Technical Reports Server (NTRS)

    Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

    1994-01-01

    Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

  11. Silicon wafers for scanning helium microscopy

    NASA Astrophysics Data System (ADS)

    Litwin, D.; Galas, J.; Sitarek, S.

    2008-01-01

    The Scanning Helium Microscopy is a new technique currently under development. The paper is an overview of measurements of the geometrical characteristics of Silicon wafer concentrating on accuracy and closely related matters. In the microscope the helium atom beam is used as a probe. The overall microscope resolution depends on a deflecting element, which shapes the beam and focuses it onto a sample's surface. The most promising focusing component appears to be an ultra thin silicon wafer that is deformed under a precise electric field. Flatness and thickness uniformity of the wafer must be measured in order to select the best plate to be used in the microscope. A scanning measurement system consists of two coaxially positioned confocal heads. The paper discusses measures taken to overcome the system sensitivity to temperature variation and concludes with utilizing symmetry descriptors for final selection of wafers.

  12. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  13. Modelling deformation and fracture in confectionery wafers

    SciTech Connect

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  14. Use of scanning capacitance microscopy for controlling wafer processing

    E-print Network

    Brune, Harald

    Use of scanning capacitance microscopy for controlling wafer processing O. Jeandupeux a , V tip is used for imaging the wafer topography in conven- tional contact mode. The tip also serves elec- trode is the backside of the wafer. SCM has been used to determine the 2D dopant profile of wafer

  15. PHASE NOISE PERFORMANCE COMPARISON BETWEEN LIGA-MEMS AND ON-CHIP CMOS CAPACITORS

    E-print Network

    Saskatchewan, University of

    PHASE NOISE PERFORMANCE COMPARISON BETWEEN LIGA-MEMS AND ON-CHIP CMOS CAPACITORS FOR A VCO between the VCO using a new type of MEMS vari- able capacitor and that using conventional CMOS varactor, which is built on-chip together with the CMOS VCO. A representative MEMS variable capacitor, fabricated

  16. Total x-ray power measurements in the Sandia LIGA program.

    SciTech Connect

    Malinowski, Michael E. (Sandia National Laboratories, Livermore, CA); Ting, Aili (Sandia National Laboratories, Livermore, CA)

    2005-08-01

    Total X-ray power measurements using aluminum block calorimetry and other techniques were made at LIGA X-ray scanner synchrotron beamlines located at both the Advanced Light Source (ALS) and the Advanced Photon Source (APS). This block calorimetry work was initially performed on the LIGA beamline 3.3.1 of the ALS to provide experimental checks of predictions of the LEX-D (LIGA Exposure- Development) code for LIGA X-ray exposures, version 7.56, the version of the code in use at the time calorimetry was done. These experiments showed that it was necessary to use bend magnet field strengths and electron storage ring energies different from the default values originally in the code in order to obtain good agreement between experiment and theory. The results indicated that agreement between LEX-D predictions and experiment could be as good as 5% only if (1) more accurate values of the ring energies, (2) local values of the magnet field at the beamline source point, and (3) the NIST database for X-ray/materials interactions were used as code inputs. These local magnetic field value and accurate ring energies, together with NIST database, are now defaults in the newest release of LEX-D, version 7.61. Three dimensional simulations of the temperature distributions in the aluminum calorimeter block for a typical ALS power measurement were made with the ABAQUS code and found to be in good agreement with the experimental temperature data. As an application of the block calorimetry technique, the X-ray power exiting the mirror in place at a LIGA scanner located at the APS beamline 10 BM was measured with a calorimeter similar to the one used at the ALS. The overall results at the APS demonstrated the utility of calorimetry in helping to characterize the total X-ray power in LIGA beamlines. In addition to the block calorimetry work at the ALS and APS, a preliminary comparison of the use of heat flux sensors, photodiodes and modified beam calorimeters as total X-ray power monitors was made at the ALS, beamline 3.3.1. This work showed that a modification of a commercially available, heat flux sensor could result in a simple, direct reading beam power meter that could be a useful for monitoring total X-ray power in Sandia's LIGA exposure stations at the ALS, APS and Stanford Synchrotron Radiation Laboratory (SSRL).

  17. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  18. Effects of wafer thermostability and wafer-holding materials on optical loss in GaAs annealing

    E-print Network

    Fejer, Martin M.

    Effects of wafer thermostability and wafer-holding materials on optical loss in GaAs annealing Y. S for publication 13 February 1998 A periodic structure of bonded GaAs wafers has been proposed for quasi lead to unacceptably high optical losses. When commercial semi-insulating GaAs wafers were bonded

  19. Porous solid ion exchange wafer for immobilizing biomolecules

    SciTech Connect

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  20. Analyzes Data from Semiconductor Wafers

    Energy Science and Technology Software Center (ESTSC)

    2002-07-23

    This program analyzes reflectance data from semiconductor wafers taken during the deposition or evolution of a thin film, typically via chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). It is used to determine the growth rate and optical constants of the deposited thin films using a virtual interface concept. Growth rates and optical constants of multiple-layer structures is possible by selecting appropriate sections in the reflectance vs time waveform. No prior information or estimatesmore »of growth rates and materials properties is required if an absolute reflectance waveform is used. If the optical constants of a thin film are known, then the growth rate may be extracted from a relative reflectance data set. The analysis is valid for either s or p polarized light at any incidence angle and wavelength. The analysis package is contained within an easy-to-use graphical user interface. The program is based on the algorighm described in the following two publications: W.G. Breiland and K.P. Killen, J. Appl. Phys. 78 (1995) 6726, and W. G. Breiland, H.Q. Hou, B.E. Hammons, and J.F. Klem, Proc. XXVIII SOTAPOCS Symp. Electrochem. Soc. San Diego, May 3-8, 1998. It relies on the fact that any multiple-layer system has a reflectance spectrum that is mathematically equivalent to a single-layer thin film on a virtual substrate. The program fits the thin film reflectance with five adjustable parameters: 1) growth rate, 2) real part of complex refractive index, 3) imaginary part of refractive index, 4) amplitude of virtual interface reflectance, 5) phase of virtual interface reflectance.« less

  1. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

  2. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  3. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  4. Laser furnace and method for zone refining of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

    1988-01-01

    A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

  5. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ?50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (? 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu-precipitates (upto 50 nm) compresses Si-lattice to facilitate Si-XII/III

  6. Seasoning of Plasma Reactors: Feedback Control Strategies to Counter Wafer-to-Wafer Drifts

    NASA Astrophysics Data System (ADS)

    Agarwal, Ankur; Kushner, Mark J.

    2007-10-01

    Seasoning of plasma etching reactors is the deposition of materials on wafers and surfaces of the chamber resulting in process or wafer-to-wafer drift in etch rates or uniformity. Feedback control with in situ diagnostics is being investigated to combat this drift. The Virtual Plasma Equipment Model, an implementation of sensors, actuators and control algorithms in the HPEM, was used to investigate real-time and wafer-to-wafer control strategies. The model system is Ar/Cl2 etching of Si in an inductively coupled plasma reactor. The passivation of surfaces in contact with the plasma, including the deposition of etch products, change reactive sticking coefficients and produce etch blocks which in turn affect etch rate. Sputtering of dielectrics may introduce additional etch-block capable species. A PID controller was used to vary the bias voltage in response to an etch rate monitor to enable control of etch rate. We found that control is problematic at high bias voltages where the flux of etch products from the wafer is sufficiently large that plasma properties are affected and redeposition increases etch blocks on the wafer. Multiple sensors-and-actuators may be necessary when sputtering of dielectrics produce additional etch-block species.

  7. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  8. Diamond-like nanocomposite coatings for LIGA-fabricated nickel alloy parts.

    SciTech Connect

    Prasad, Somuri V.; Scharf, Thomas W.

    2005-03-01

    A commercial plasma enhanced chemical vapor deposition (PECVD) technique with planetary substrate rotation was used to apply a thin (200-400 nm thick) conformal diamond-like carbon (DLC) coating (known as a diamond-like nanocomposite (DLN)) on LIGA fabricated Ni-Mn alloy parts. The PECVD technique is known to overcome the drawbacks associated with the line-of-sight nature of physical vapor deposition (PVD) and substrate heating inherent with traditional chemical vapor deposition (CVD). The purpose of the present study is to characterize the coverage, adhesion, and tribological (friction and wear) behavior of DLN coatings applied to planar and sidewall surfaces of small featured LIGA Ni-Mn fabricated parts, e.g. 280 {micro}m thick sidewalls. Friction and wear tests were performed in dry nitrogen, dry air, and air with 50% RH at Hertzian contact pressures ranging from 0.3 to 0.6 GPa. The friction coefficient of bare Ni-Mn alloy was determined to be 0.9. In contrast, low friction coefficients ({approx}0.02 in dry nitrogen and {approx}0.2 in 50% RH air) and minimal amount of wear were exhibited for the DLN coated LIGA Ni-Mn alloy parts and test coupons. This behavior was due to the ability of the coating to transfer to the rubbing counterface providing low interfacial shear at the sliding contact; resultantly, coating one surface was adequate for low friction and wear. In addition, a 30 nm thick titanium bond layer was determined to be necessary for good adhesion of DLN coating to Ni-Mn alloy substrates. Raman spectroscopy and cross-sectional SEM with energy dispersive x-ray analysis revealed that the DLN coatings deposited by the PECVD with planetary substrate rotation covered both the planar and sidewall surfaces of LIGA fabricated parts, as well as narrow holes of 300 {micro}m (0.012 inch) diameter.

  9. Wafer capping of MEMS with fab-friendly metals

    NASA Astrophysics Data System (ADS)

    Martin, Jack

    2007-01-01

    Inertial MEMS (Micro Electro Mechanical System) sensors are normally sealed in hermetic enclosures. Some are assembled in hermetic packages but wafer level packaging has become much more important in recent years. Anodic bonding can be used to achieve wafer level seals between silicon and glass but most suppliers of inertial sensors screen print glass frit onto silicon cap wafers. After removing the organic vehicle, these patterned cap wafers are sealed to device wafer prior to wafer singulation and plastic packaging. Anodic and glass frit bonding are both cost-effective. However, they impose size, quality and performance limitations. Wafer level sealing with a metal removes some of these limitations but introduces other concerns. This paper will review the current wafer level hermetic processes followed by a description of a thermocompression metal seal technology that is compatible with IC fabrication.

  10. Geometry control of recrystallized silicon wafers for solar applications

    E-print Network

    Ruggiero, Christopher W

    2009-01-01

    The cost of manufacturing crystalline silicon wafers for use in solar cells can be reduced by eliminating the waste streams caused by sawing ingots into individual wafers. Professor Emanuel Sachs has developed a new method ...

  11. Apparatus for edge etching of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Casajus, A.

    1986-01-01

    A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

  12. Hermetic wafer bonding based on rapid thermal processing , Liwei Lin

    E-print Network

    Lin, Liwei

    Hermetic wafer bonding based on rapid thermal processing Mu Chiao* , Liwei Lin Berkeley Sensor 94720-1740, USA Abstract Hermetic wafer bonding based on rapid thermal processing (RTP) has been for wafer-level MEMS fabrication and packaging. # 2001 Elsevier Science B.V. All rights reserved. Keywords

  13. Spatial Estimation of Wafer Measurement Parameters Using Gaussian Process Models

    E-print Network

    Makris, Yiorgos

    Spatial Estimation of Wafer Measurement Parameters Using Gaussian Process Models Nathan Kupp, Ke) are collected to monitor the health-of-line and to make wafer scrap decisions preceding final test. These measurements are typically sampled spatially across the surface of the wafer from between-die scribe line sites

  14. Enhanced Design Flow and Optimizations for Multi-Project Wafers

    E-print Network

    Zelikovsky, Alexander

    1 Enhanced Design Flow and Optimizations for Multi-Project Wafers Andrew B. Kahng Ion I. Mandoiu Xu and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW of mask tooling among up to tens of designs. However, MPW reticle floorplanning and wafer dicing introduce

  15. Wafer Slicing and Wire Saw Manufacturing Technology I. Kao (PI)

    E-print Network

    Kao, Imin

    Wafer Slicing and Wire Saw Manufacturing Technology I. Kao (PI) and V. Prasad, J. Li, M. Bhagavat to cut very thin wafers from large diameter crystalline ingots of semiconductor materials, has emerged as a leading technology for wafer production in semiconductor and photovoltaic industry. Nevertheless, the wire

  16. Automatic Clustering of Wafer Spatial Signatures Wangyang Zhang

    E-print Network

    Li, Xin

    1 Automatic Clustering of Wafer Spatial Signatures Wangyang Zhang 1 , Xin Li 1 , Sharad Saxena 2 of wafer spatial signatures to aid yield improvement. Our proposed methodology is based on three steps. First, we apply sparse regression to automatically capture wafer spatial signatures by a small number

  17. Defect detection in patterned wafers using multichannel Scanning Electron Microscope

    E-print Network

    Cohen, Israel

    Defect detection in patterned wafers using multichannel Scanning Electron Microscope Maria Zontak using Scanning Electron Microscope (SEM) images. A wafer is irradiated with a focused beam of electrons s t r a c t Recent computational methods of wafer defect detection often inspect Scanning Electron

  18. Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Shi, Fang Frank

    Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances. Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported. Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure mechanism. The kinetic and thermodynamic analysis of the annealing-induced interfacial transformation process has been performed based upon the temporal measurements of interface electrical conductivity and micromorphologies. Finally, the feasibility of using the combination of low-temperature grown amorphous alpha-(Ga, As) materials and wafer-bonding technology to fabricate GaSb semiconductor on GaAs substrates to potentially create GaSb-on-insulator structure has been demonstrated.

  19. Analysis of the interdigitated back contact solar cells: The n-type substrate lifetime and wafer thickness

    NASA Astrophysics Data System (ADS)

    Zhang, Wei; Chen, Chen; Jia, Rui; Sun, Yun; Xing, Zhao; Jin, Zhi; Liu, Xin-Yu; Liu, Xiao-Wen

    2015-10-01

    The n-type silicon integrated-back contact (IBC) solar cell has attracted much attention due to its high efficiency, whereas its performance is very sensitive to the wafer of low quality or the contamination during high temperature fabrication processing, which leads to low bulk lifetime ?bulk. In order to clarify the influence of bulk lifetime on cell characteristics, two-dimensional (2D) TCAD simulation, combined with our experimental data, is used to simulate the cell performances, with the wafer thickness scaled down under various ?bulk conditions. The modeling results show that for the IBC solar cell with high ?bulk, (such as 1 ms-2 ms), its open-circuit voltage Voc almost remains unchanged, and the short-circuit current density Jsc monotonically decreases as the wafer thickness scales down. In comparison, for the solar cell with low ?bulk (for instance, < 500 ?s) wafer or the wafer contaminated during device processing, the Voc increases monotonically but the Jsc first increases to a maximum value and then drops off as the wafer’s thickness decreases. A model combing the light absorption and the minority carrier diffusion is used to explain this phenomenon. The research results show that for the wafer with thinner thickness and high bulk lifetime, the good light trapping technology must be developed to offset the decrease in Jsc. Project supported by the Chinese Ministry of Science and Technology Projects (Grant Nos. 2012AA050304 and Y0GZ124S01), the National Natural Science Foundation of China (Grant Nos. 11104319, 11274346, 51202285, 51402347, and 51172268), and the Fund of the Solar Energy Action Plan from the Chinese Academy of Sciences (Grant Nos. Y3ZR044001 and Y2YF014001).

  20. Sensors and Achcators A, 43 (1994) 22X29 223 Low-temperature silicon wafer-to-wafer bonding using gold at

    E-print Network

    Grigoriev, Alexei

    1994-01-01

    Sensors and Achcators A, 43 (1994) 22X29 223 Low-temperature silicon wafer-to-wafer bonding using and actuator systems of high complexity bemme commercially viable when realized as a multi-wafer device in which the mechanical functions are distributed over different wafers and one of the wafers is dedicated

  1. Elimination of wafer edge die yield loss for accelerometers

    NASA Astrophysics Data System (ADS)

    Zhang, Zhenjun; Eskes, Kim A.

    2000-08-01

    Residual stresses from deposition of several micron thick polysilicon film on accelerometer wafers caused wafer to warp towards edge of wafer. The average peak to valley difference for wafer flat across wafer is 16 +/- 1 micrometers . The photo layer following the thick polysilicon deposition process is a CD critical layer with 1 micrometers spacing to be resolved. With standard stepper configuration, wafer non- flatness from residual stresses reduced overall depth of focus and made the 1 (mu) spacing in edge dies not resolved, resulting in stiction and yield loss for edge dies. To minimize the effect of wafer non-flatness on across wafer CD control and edge die CD definition at photo, three different focus algorithms as well as two different wafer chuck styles were evaluated on 1X steppers. Results showed that both oblong wafer chuck and two step focus option significantly improved CD definition and resolution of the 1 micrometers spacing in edge dies. Two step focus combined with oblong chuck offered the best CD control edge dies. Edge die yield loss was eliminated for accelerometer wafers ran with oblong chuck and two step focus. Oblong chuck, and two step focus combination have been released to full production at Poly2 layer of accelerometers.

  2. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL); St. Martin, Edward (Libertyville, IL); Arora, Michelle (Woodridge, IL); de la Garza, Linda (Woodridge, IL)

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  3. Economic impact of single-wafer multiprocessors

    NASA Astrophysics Data System (ADS)

    Wood, Samuel C.; Saraswat, Krishna C.; Harrison, J. M.

    1991-04-01

    Single wafer multiprocessors generally in the form of cluster tools are gaining increasing importance in commercial semiconductor product manufacture. This paper describes potential cost-related and timerelated advantages that could come from the multipmcessors. Next hypothetical conventional and clusterbased fabs are simulated. The simulations results are discussed in terms of their evidence for the cost and time advantages of the fabs. One general conclusion is that cluster tools can be used to achieve very short throughput times at a premium cost per wafer. Finally based on the potential advantages and the simulation results three areas of non-process issues are discussed which will determine the extent of the multiprocessors'' economic utility. These areas are cost time and fab management related. 1

  4. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  5. Warpage Measurement of Thin Wafers by Reflectometry

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

  6. Precipitating Chromium Impurities in Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Salama, A. M.

    1982-01-01

    Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

  7. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  8. Equipment for On-Wafer Testing From 220 to 325 GHz

    NASA Technical Reports Server (NTRS)

    Samoska, Lorene; Peralta, Alejandro; Dawson, Douglas; Lee, Karen; Boll, Greg; Oleson, Chuck

    2006-01-01

    A system of electronic instrumentation, constituting the equivalent of a two-port vector network analyzer, has been developed for use in on-wafer measurement of key electrical characteristics of semiconductor devices at frequencies from 220 to 325 GHz. A prior system designed according to similar principles was reported in Equipment for On-Wafer Testing at Frequencies Up to 220 GHz (NPO-20760), NASA Tech Briefs, Vol. 25, No. 11 (November 2001), page 42. As one would expect, a major source of difficulty in progressing to the present higher-frequency-range system was the need for greater mechanical precision as wavelengths shorten into the millimeter range, approaching the scale of mechanical tolerances of prior systems. The system (see figure) includes both commercial off-the-shelf and custom equipment. As in the system of the cited prior article, the equipment includes test sets that are extended versions of commercial network analyzers that function in a lower frequency range. The extension to the higher frequency range is accomplished by use of custom frequency-extension modules that contain frequency multipliers and harmonic mixers. On-wafer measurement is made possible by waveguide wafer probes that were custom designed and built for this wavelength range, plus an on-wafer calibration substrate designed for use with these probes. In this case, the calibration substrate was specially fabricated by laser milling. The system was used to make the first on-wafer measurements of a semiconductor device in the frequency range from 220 to 320 GHz. Some of the measurement results showed that the device had gain.

  9. Mask-to-wafer alignment system

    DOEpatents

    Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

    2003-11-04

    A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

  10. Modeling and fabrication of micro 3K-2-type planetary gear reducer utilizing SU-8 photoresist as alternative LIGA technology

    NASA Astrophysics Data System (ADS)

    Zhang, Weiping; Chen, Wenyuan; Chen, Di; Chen, Xiaomei; Wu, Xiaosheng; Xu, Zhengfu

    2001-10-01

    The LIGA type process, utilizing SU-8 photoresist as alternative LIGA technology, can fabricate high aspect ratio microstructures without employing synchrotron light and suitable X-ray mask. Based on LIGA type process in this paper, detailed investigations of the modeling and fabrication of micro 3K-2 type planetary gear reducer, such as the modeling and design of micro reducer, CAD of micro gear mask, SU-8 UV photolithography, micro electroforming, micro molding, have been performed. And 400 um thickness sun gear, 400 um thickness planet gear, 200 um thickness fixed inner gear, and 200 um thickness rotary inner gear, whose teeth are 15,11,36,39 respectively, have been obtained. Utilizing these gears, the micro reducer whose modulus, outer diameter and velocity ratio are 0.03, 2mm, 44.2:1, has been assembled and applied in (phi) 2mm micro electro magnetic motor successfully.

  11. LIGA-fabricated two-dimensional quadrupole array and scroll pump for miniature gas chromatograph/mass spectrometer

    NASA Astrophysics Data System (ADS)

    Wiberg, Dean V.; Myung, Nosang V.; Eyre, Beverley; Shcheglov, Kirill; Orient, Otto J.; Moore, Eric; Munz, Philip

    2003-07-01

    A 3X3 array of hyperboloid quadrupole mass filters with a 3 mm pole length was fabricated using the LIGA (LIthographic Galvanoformung and Abformung) process. Electrical connectivity and spatial orientation are established by bonding the pole array to a low temperature co-fired ceramic (LTCC) substrate. A miniature scroll pump for vacuum pumping with a scroll height of 3 mm was also fabricated using the LIGA process. New LIGA fabrication steps (e.g. expose and developed freestanding PMMA, compression bonding of electroplating base and PMMA, low-stress electroplated films) have been developed to fabricate ultra thick PMMA molds with high aspect ratios (70:1) and high precision. Computational analysis was performed to estimate the miniature scroll pump performance characteristics.

  12. Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size

    NASA Astrophysics Data System (ADS)

    Kim, Hee Yeoun; Yang, Chungmo; Park, Jae Hong; Jung, Ho; Kim, Taehyun; Kim, Kyung Tae; Lim, Sung Kyu; Lee, Sang Woo; Mitchell, Jay; Hwang, Wook Joong; Lee, Kwyro

    2013-06-01

    For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.

  13. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  14. Wafer warpage characterization measurement with modified fringe reflection method

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2015-05-01

    We have demonstrated a modified fringe reflection method to compensate the warpage measurement errors caused by the height difference between optical reference mirror and wafer sample surface. We have used a linearity analysis approach to obtain the parabolic height errors for a 4-inch sapphire wafer warpage measurement, which is around 1.48 ?m of 100 ?m height difference. The experimental results shows the warp discrepancy of 6-inch sapphire wafer is less than 1 ?m compared with the reference Tropel instrument.

  15. "Performance Of A Wafer Stepper With Automatic Intra-Die Registration Correction."

    NASA Astrophysics Data System (ADS)

    van den Brink, M. A.; Wittekoek, S.; Linders, H. F. D.; van Hout, F. J.; George, R. A.

    1987-01-01

    An evaluation of a wafer stepper with the new improved Philips/ASM-L phase grating alignment system is reported. It is shown that an accurate alignment system needs an accurate X-Y-0 wafer stage and an accurate reticle Z stage to realize optimum overlay accuracy. This follows from a discussion of the overlay budget and an alignment procedure model. The accurate wafer stage permits high overlay accuracy using global alignment only, thus eliminating the throughput penalty of align-by-field schemes. The accurate reticle Z stage enables an intra-die magnification control with respect to the wafer scale. Various overlay data are reported, which have been measured with the automatic metrology program of the stepper. It is demonstrated that the new dual alignment system (with the external spatial filter) has improved the ability to align to weakly reflecting layers. The results are supported by a Fourier analysis of the alignment signal. Resolution data are given for the PAS 2500 projection lenses, which show that the high overlay accuracy of the system is properly matched with submicron linewidth control. The results of a recently introduced 20mm i-line lens with a numerical aperture of 0.4 (Zeiss 10-78-58) are included.

  16. Fabrication of PMMA Microchip of Capillary Electrophoresis by Optimized UV-LIGA Process

    NASA Astrophysics Data System (ADS)

    Zhu, Xuelin; Liu, Gang; Xiong, Ying; Guo, Yuhua; Tian, Yangchao

    2006-04-01

    Design and fabrication of microfluidic devices on polymethylmethacrylate (PMMA) substrates for electrochemical analysis applications using improved UV-LIGA process are described. The micro-channel structures are transferred from Nickel mould into the plastic plates by hot embossing method. During the mould fabrication, the exposure process is optimized for the large ratio of exposed area to unexposed area of negative photo-resist (SU-8), then non-planar electroforming technique is used for the large line space of the SU8 photoresist mold. Microelectrodes for electrochemical detection are fabricated on other blank PMMA plates through lift-off process. Then these substrates with microchannels are bonded to PMMA plates with microelectrodes by thermal bonding method based on surface modification. In this study, the PMMA microchips of capillary electrophoresis for electrochemical detection (CE-ECD Chips) have been demonstrated by electrophoretic separation of L-ascorbic and uric acid. The results indicate that the fabrication of CE chips by this improved UV-LIGA process has potential of mass production with low cost.

  17. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  18. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M. (Antioch, CA)

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  19. Wafer Signature Analysis of IDDQ Test Data Sagar S. Sabade D. M. H. Walker

    E-print Network

    Walker, Duncan M. "Hank"

    Wafer Signature Analysis of IDDQ Test Data Sagar S. Sabade D. M. H. Walker Department of Computer. The concept of wafer signature is proposed. A wafer signature is obtained by sorting all IDDQ readings on a wafer for a vector. A break or jump in the wafer signature is considered to indicate defective chips

  20. Comparison of lateral thermal damage of the human peritoneum using monopolar diathermy, Harmonic scalpel and LigaSure

    PubMed Central

    Družijani?, Nikica; Pogoreli?, Zenon; Perko, Zdravko; Mrkli?, Ivana; Tomi?, Snježana

    2012-01-01

    Background New hemostatic technologies are often employed in open and laparoscopic surgery to reduce duration of surgery and complications. Monopolar diathermy, Harmonic scalpel and LigaSure are routinely used in open and laparoscopic surgery for tissue cutting and hemostasis. We compared lateral thermal damage following in vivo application of 3 commonly used instruments. Methods We used monopolar diathermy, Harmonic scalpel and LigaSure to coagulate and divide the peritoneum of patients who underwent median laparotomy. After anesthesia, median supraumbilical laparotomy was performed, and the peritoneum of each patient was coagulated using different devices. Using light microscopy and morphometric imaging analysis, the width of tissue lateral thermal damage was measured from the point of the peritoneal incision. Results We included 100 patients in our study. After a peritoneal incision, the mean lateral thermal damage of monopolar diathermy, Harmonic scalpel (output power 3), Harmonic scalpel (output power 5) and LigaSure were 215.79 ?m, 90.42 ?m, 127.48 ?m and 144.18 ?m, respectively. Conclusion The degree of lateral thermal spread varied by instrument type, power setting and application time. LigaSure and Harmonic scalpel were the safest and most efficient methods of tissue coagulation. Monopolar diathermy resulted in the greatest degree of thermal damage in tissues. PMID:22854112

  1. Fabrication of a micro-retroreflector by LIGA J. Jahns, Th. Seiler, J. Mohr1, M. Borner1

    E-print Network

    Jahns, Jürgen

    Fabrication of a micro-retroreflector by LIGA J. Jahns, Th. Seiler, J. Mohr1, M. B¨orner1 (1Karlsruhe Institute of Technology) The fabrication of microoptical elements with prismatic shape is and a sharp edge. The difficulty lies in achieving both simultaneously: the fabrication of a smooth surface

  2. Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers

    E-print Network

    Lü, James Jian-Qiang

    Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal. Monolithic wafer-level 3D integration offers the potential for a high density of micron-sized through-die vias necessary for highest performance of integrated systems. In addition, such wafer

  3. Particulate contamination removal from wafers using plasmas and mechanical agitation

    SciTech Connect

    Selwyn, Gary S.

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  4. Reduction of Thermal Conductivity in Wafer-Bonded Silicon

    SciTech Connect

    ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

    2006-11-27

    Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

  5. Thermal Warpage of Large Diameter Czochralski-Grown Silicon Wafers

    NASA Astrophysics Data System (ADS)

    Shimizu, Hirofumi; Aoshima, Takaaki

    1988-12-01

    Thermal warping of large diameter Czochralski-grown silicon wafers as affected by oxygen precipitation is investigated both experimentally and theoretically. The difference of wafer warpage and its shape between the heating and cooling processes is clarified by thermal stresses calculated from temperature gradients in wafers for each process. The critical temperatures for the slip occurrence are determined for the heating and cooling processes as a function of the microdefect density. Then, the optimized process conditions to avoid slip dislocations are obtained experimentally. The critical stress curve for the processed wafers in MOS devices is determined by comparison with the thermal stress curves calculated under various process conditions, and thereby predicting the slip-free conditions for wafers in a row with various diameters from 100 to 200 mm.

  6. Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

    2014-01-01

    This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

  7. Piezoresistive stress sensors on (110) silicon wafers

    NASA Technical Reports Server (NTRS)

    Kang, Y. L.; Suhling, J. C.; Jaeger, R. C.

    1992-01-01

    Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

  8. Wafer Mapping Using Deuterium Enhanced Defect Characterization

    NASA Astrophysics Data System (ADS)

    Hossain, K.; Holland, O. W.; Hellmer, R.; Vanmil, B.; Bubulac, L. O.; Golding, T. D.

    2010-07-01

    Deuterium (as well as other hydrogen isotopes) binds with a wide range of morphological defects in semiconductors and, as such, becomes distributed similarly to those defects. Thus, the deuterium profile within the sample serves as the basis of a technique for defect mapping known as amethyst wafer mapping (AWM). The efficiency of this technique has been demonstrated by evaluation of ion-induced damage in implanted Si, as well as as-grown defects in HgCdTe (MCT) epilayers. The defect tagging or decoration capability of deuterium is largely material independent and applicable to a wide range of defect morphologies. A number of analytical techniques including ion channeling and etch pit density measurements were used to evaluate the AWM results.

  9. Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon wafers

    E-print Network

    Akin, Tayfun

    Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon September 2010 Keywords: Diamond-on-insulator Plasma activation Ultrananocrystalline diamond Direct bonding Diamond-on-insulator (DOI) wafers featuring ultrananocrystalline diamond are studied via atomic force

  10. Overlay Tolerances For VLSI Using Wafer Steppers

    NASA Astrophysics Data System (ADS)

    Levinson, Harry J.; Rice, Rory

    1988-01-01

    In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his merchandise appear as attractive as possible, the lithographer is frequently placed in the position of having to explain subtle issues in order to justify his decisions. It is the purpose of this paper to provide that explanation.

  11. Temperature rise of the silicon mask-PMMA resist assembly during LIGA exposure

    NASA Astrophysics Data System (ADS)

    Ting, Aili

    2005-01-01

    Deep X-ray lithography on PMMA resist is used in the LIGA process. The resist is exposed to synchrotron X-rays through a patterned mask and then is developed in a liquid developer to make high aspect ratio microstructures. This work addresses the thermal analysis and temperature rise of the mask-resist assembly during exposure at the Advanced Light Source (ALS) synchrotron. The concern is that the thermal expansion will lower the accuracy of the lithography. We have developed a three-dimensional finite-element model of the mask and resist assembly. We employed the LIGA exposure-development software LEX-D and the commercial software ABAQUS to calculate heat transfer of the assembly during exposure. The calculations of assembly maximum temperature have been compared with temperature measurements conducted at ALS. The temperature rise in the silicon mask and the mask holder comes directly from the X-ray absorption, but forced convection of nitrogen jets carry away a significant portion of heat energy from the mask surface, while natural convection plays a negligible role. The temperature rise in PMMA resist is mainly from heat conducted from the silicon substrate backward to the resist and from the mask plate through inner cavity air forward to the resist, while the X-ray absorption is only secondary. Therefore, reduction of heat flow conducted from both substrate and cavity air to the resist is essential. An improved water-cooling block is expected to carry away most heat energy along the main heat conductive path, leaving the resist at a favorable working temperature.

  12. Optima XE Single Wafer High Energy Ion Implanter

    SciTech Connect

    Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny

    2008-11-03

    The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

  13. Techniques for the evaluation of outgassing from polymeric wafer pods

    SciTech Connect

    McIntyre, D.C.; Liang, A.; Thornberg, S.M.; Bender, S.F.; Lujan, R.D.; Blewer, R.S.; Bowers, W.D.

    1994-03-01

    In recent years there has been increasing interest in using wafer-level isolation environments or pods (microenvironments) to provide a more controllable, cleaner wafer environment during wafer processing. It has been shown that pods can be effective in reducing the amount of particulate contamination on wafers during manufacturing. However, there have also been studies that indicate that pods and wafer boxes can be the source of condensible, molecular organic contamination. This paper summarizes the work that has been performed during the past year at Sandia National Laboratories` Contamination Free Manufacturing Research Center (CFMRC) on (1) devising standard, low-temperature, high sensitivity techniques to detect outgassing of volatile organic compounds (VOCs) from polymers used to construct wafer pods and (2) development of a technique that can be used to continuously measure the condensible contamination within pods so that the pod environment can be monitored during manufacturing. Although these techniques have been developed specifically for assessing contamination threats from wafer pods, they can be used to evaluate other potential contamination sources. The high sensitivity outgassing techniques can be used to evaluate outgassing of volatiles from other clean-room materials and the real-time outgassing sensor can be used to monitor contamination condensation in non-pod environments such as ballroom-type cleanrooms and minienvironments.

  14. On-Wafer Testing of Circuits Through 220 GHz

    NASA Technical Reports Server (NTRS)

    Gaier, Todd; Samoska, Lorene; Oleson, Charles; Boll, Greg

    1999-01-01

    We have jointly developed the capability to perform on-wafer s-parameter and noise figure measurements through 220 GHz. S-parameter test sets have been developed covering full waveguide bands of 90-140 GHz (WR-08) and 140-220 GHz (WR-05). The test sets have been integrated with coplanar probes to allow accurate measurements on-wafer. We present the design and performance of the test sets and wafer probes. We also present calibration data as well as measurements of active circuits at frequencies as high as 215 GHz.

  15. The uses of Man-Made diamond in wafering applications

    NASA Technical Reports Server (NTRS)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  16. Potentials of LiGa(S 1-xSe x) 2 mixed crystals for optical frequency conversion

    NASA Astrophysics Data System (ADS)

    Huang, J.-J.; Atuchin, V. V.; Andreev, Yu. M.; Lanskii, G. V.; Pervukhina, N. V.

    2006-07-01

    Phase-matching conditions are considered for second harmonic generation (SHG) and optical parametric generation in LiGa(S 1-xSe x) 2 mixed crystals as a function of chemical composition under the supposition of linear dependence of refractive indices on x. It has been shown that by tuning x over the range 0-1 the SHG can be realized in XY plane for ?=2.1-7.8 ?m pumping at ?=43-90°, in YZ plane for ?=2.1-2.2 and 4.8-7.8 ?m pumping at ?=0-90°, and in XZ plane for ?=1.6-11.7 ?m pumping at ?=0-57°. The LiGa(S 1-xSe x) 2 solid solutions are also attractive for design of tunable femtosecond pulse frequency converters with saving of pump pulse duration.

  17. Low-temperature full wafer adhesive bonding

    NASA Astrophysics Data System (ADS)

    Niklaus, Frank; Enoksson, Peter; Kälvesten, Edvard; Stemme, Göran

    2001-03-01

    We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 µm and 18 µm. The tested polymer materials were benzocyclobutene (BCB) from Dow Chemical, a negative photoresist (ULTRA-i 300) and a positive photoresist (S1818) from Shipley, a polyimide (HTR3) from Arch Chemical and two different polyimides (PI2555 and PI2610) from DuPont. The polymer material, the bonding pressure and the pre-curing time and temperature for the polymer significantly influence void formation at the bond interface. High bonding pressure and optimum pre-curing times/temperatures counteract void formation. We present the process parameters to achieve void-free bonding with the BCB coating and with the ULTRA-i 300 photoresist coating as adhesive materials. Excellent void-free and strong bonds have been achieved by using BCB as the bonding material which requires a minimum bonding temperature of 180 °C.

  18. Wafer bonding : mechanics-based models and experiments

    E-print Network

    Turner, Kevin Thomas, 1977-

    2004-01-01

    Direct wafer bonding has emerged as an important technology in the manufacture of silicon-on-insulator substrates (SOI), microelectromechanical systems (MEMS), and three-dimensional integrated circuits (3D IC's). While the ...

  19. Infrared backwards laser melting of a silicon wafer

    NASA Astrophysics Data System (ADS)

    Lill, Patrick C.; Köhler, Jürgen R.

    2015-11-01

    We investigate a method for melting a silicon wafer's rear side with a pulsed infrared laser (1064 nm) impinging onto the front side. The targeted application for this method is deep laser doping. Our numerical model simulates the evolution of the two-dimensional temperature distribution in the wafer caused by pulsed infrared laser irradiation. The model incorporates the temperature dependent material properties of silicon and the enthalpy-based phase change by means of finite volumes. The simulation yields spacial temperature distributions of the wafer's cross section at defined time steps. We obtain the laser parameters for a continuous melt depth of 40 µm in a 200 µm thick wafer from the analysis of the simulation results.

  20. Surface defects in GaAs wafer processes

    NASA Astrophysics Data System (ADS)

    Matsushita, H.; Ishida, M.; Kikawa, J.

    1990-06-01

    The causes of micro- and macro-irregularities observed on GaAs(100) polished wafers were investigated. From the results, the wafer processes were improved so that a high-quality surface was obtained without orange peel, haze, or pits. For 3-inch wafers the flatness was improved to less than 2 ?m in TTV and the warp to less than 5 ?m. Improvements in the wafer processes were: development of a better polishing solution, filtering of this solution with maintenance of the pad conditions, thereby eliminating scratches, annealing at high temperature to eliminate pits, advances in slicing and lapping to reduce warp, and three-stage double-sided polishing to eliminate dimples and to improve TTV.

  1. Estimation of wafer warpage profile during thermal processing in microlithography

    NASA Astrophysics Data System (ADS)

    Tay, Arthur; Ho, Weng Khuen; Hu, Ni; Chen, Xiaoqi

    2005-07-01

    Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability, and linewidth control in various processing steps. Early detection will minimize cost and processing time. We propose in this article an in situ approach for estimating wafer warpage profile during the thermal processing steps in the microlithography process. The average air gap between wafer and bake-plate at multiple locations of a multizone bake-plate can be estimated and a profile can be obtained by joining these points. Experimental results demonstrate the feasibility and repeatability of the approach. This is a major improvement over our previously developed approach, in which only the average warpage could be obtained. The proposed approach requires no extra processing steps and time, as compared to conventional off-line methods.

  2. Efficient data transmission from silicon wafer strip detectors

    SciTech Connect

    Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

    1991-12-31

    An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

  3. Proceedings of the Low-Cost Solar Array Wafering Workshop

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1982-01-01

    The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

  4. National solar technology roadmap: Wafer-silicon PV

    SciTech Connect

    Sopori, Bhushan

    2007-06-01

    This report applies to all bulk-silicon-based PV technologies, including those based on Czochralski, multicrystalline, float-zone wafers, and melt-grown crystals that are 100 ?m or thicker, such as ribbons, sheet, or spheral silicon.

  5. Tool procurement planning for wafer fabrication facilities: a scenario-based approach

    E-print Network

    Swaminathan, Jayashankar M.

    Tool procurement planning for wafer fabrication facilities: a scenario-based approach JAYASHANKAR M addresses the issue of tool procurement planning at a semiconductor wafer fabrication facility which makes be divided into four basic steps: (i) wafer fabrication; (ii) wafer probe; (iii) assembly; and (iv) ®nal

  6. MultiProject Reticle Floorplanning and Wafer Dicing # Andrew B. Kahng, Ion M

    E-print Network

    Kahng, Andrew B.

    Multi­Project Reticle Floorplanning and Wafer Dicing # Andrew B. Kahng, Ion M â?? andoiu + , Qinke@engr.uconn.edu, alexz@cs.gsu.edu ABSTRACT Multi­project Wafers (MPW) are an efficient way to share the rising costs­project reticle floorplanning and wafer dicing problems under the prevalent side­ to­side wafer dicing technology

  7. An accurate method for calibrating photoluminescence-based lifetime images on multi-crystalline silicon wafers

    E-print Network

    -crystalline silicon wafers H.C. Sio a,n , S.P. Phang a , T. Trupke b , D. Macdonald a a Research School of Engineering for silicon wafers with inhomogeneous lifetime distributions, such as multi-crystalline silicon wafers, based on a calibration factor extracted from a separate, homogeneous, mono-crystalline calibration wafer and simple

  8. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R. (Albuquerque, NM); Jones, Howland D. T. (Albuquerque, NM); Kelly, Michael J. (Albuquerque, NM); Medernach, John W. (Albuquerque, NM); Stevenson, Joel O. (Albuquerque, NM); Tsao, Sylvia S. (Albuquerque, NM)

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  9. Penetration of plasma into the wafer-focus ring gap in capacitively coupled plasmas

    E-print Network

    Kushner, Mark

    Penetration of plasma into the wafer-focus ring gap in capacitively coupled plasmas Natalia Y the edge of the wafer and wafer terminating structures, such as focus rings. The intended purpose of these structures is to make the reactant fluxes uniform to the edge of the wafer and so prevent a larger than

  10. APPLICATION OF REDUCED-RANK MULTIVARIATE METHODS TO THE MONITORING OF SPATIAL UNIFORMITY OF WAFER ETCHING

    E-print Network

    Nikolaou, Michael

    1 APPLICATION OF REDUCED-RANK MULTIVARIATE METHODS TO THE MONITORING OF SPATIAL UNIFORMITY OF WAFER wafers. An industrial case study is discussed. 1 INTRODUCTION Spatially uniformity is necessary for high on 300-mm wafer surface, interpolated over 49 measurement points (black dots). Both wafers correspond

  11. Silicon Wafer Transport in a High Vacuum, Microgravity Environment Nick Pfeiffer(1)

    E-print Network

    Chapman, Glenn H.

    are studying a system based upon magnetic levitation for the transport and fixturing of wafers in the orbital of freedom through magnetic levitation. In this system, the wafer is produced with a series of circular eddy of wafers in the orbital environment. While magnetic levitation has been utilized for the transport of wafer

  12. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  13. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-03-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  14. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  15. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2008-10-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  16. Strategy optimization for mask rule check in wafer fab

    NASA Astrophysics Data System (ADS)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  17. High Throughput, Noncontact System for Screening Silicon Wafers Predisposed to Breakage During Solar Cell Production

    SciTech Connect

    Sopori, B.; Rupnowski, P.; Basnyat, P.; Mehta, V.

    2011-01-01

    We describe a non-contact, on-line system for screening wafers that are likely to break during solar cell/module fabrication. The wafers are transported on a conveyor belt under a light source, which illuminates the wafers with a specific light distribution. Each wafer undergoes a dynamic thermal stress whose magnitude mimics the highest stress the wafer will experience during cell/module fabrication. As a result of the stress, the weak wafers break, leaving only the wafers that are strong enough to survive the production processes. We will describe the mechanism of wafer breakage, introduce the wafer system, and discuss the results of the time-temperature (t-T) profile of wafers with and without microcracks.

  18. Assessment of patients’ quality of life after haemorrhoidectomy using the LigaSure device

    PubMed Central

    Leksowski, Krzysztof

    2015-01-01

    Introduction Haemorrhoids are small anatomical structures within the anal canal that are involved in the proper functioning of the lower gastrointestinal tract. Factors favouring the development of haemorrhoidal disease are insufficient physical activity, prolonged sitting and hence a shortage of physical activity, as well as poor diet which lacks adequate amounts of fibre. The main symptom of this disease is bleeding with bright red blood just after defecation. Haemorrhoidal disease occurs when the ligamentous apparatus comes loose and the internal haemorrhoidal plexus translocates down, whereas haemorrhoids enlarge and move out of the anal canal. Haemorrhoidal disease treatment includes conservative, instrumental and surgical therapy. Aim To assess treatment and satisfaction in particular life domains after haemorrhoidectomy. Material and methods The research was undertaken in the General, Thoracic and Vascular Surgery Clinic of the 10th Military Clinical Hospital with Polyclinic in Bydgoszcz among 50 patients treated due to haemorrhoids and operated on in the period 2007–2008. The study evaluated quality of patients’ life after haemorrhoidectomy by Ferguson's method using a LigaSure appliance. Results The study investigated whether patients perceived a difference before and after surgery. The research proved that patients can describe disease symptoms and know the risk factors for haemorrhoids. In the studied group patients are able to describe characteristic signs of haemorrhoidal disease and also indicate differences in everyday life before and after the surgery. They can also describe and classify the pain before and 1 year after the haemorrhoidectomy, which was statistically significantly lower already 3 months after the operation. Conclusions Conducted examinations showed that sick people in the precise way were able to determine manifestations and know risk factors of the prevalence of disease hemorrhoidal. Operated sick people indicated the difference in quality of the life both before, as well as after the undergone treatment. After the operation of the haemorrhoids with method of Ferguson using LigaSure apparatus operated sick persons could distinguish and classify pain before the treatment as well as in a year after which was statistically characteristically lower already after three months from treatment. PMID:25960796

  19. Auto Defect Classification (ADC) Value for Patterned Wafer Inspection Systems in PLY Within a High Volume Wafer Manufacturing Fabrication Facility

    E-print Network

    Durniak, John

    2010-05-14

    The purpose of this investigation is to demonstrate value for Auto Defect Classification (ADC) for patterned wafer inspection systems within a high volume manufacturing fabrication in the Process Limited Yield (PLY) defect area. Process excursions...

  20. Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis

    SciTech Connect

    Tobin, K.W.

    2003-05-22

    This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

  1. Wafer current measurement for process monitoring

    NASA Astrophysics Data System (ADS)

    Shur, Dmitry; Kadyshevitch, Alexander; Zelenko, Jeremy; Mata, Carlos; Verdugo, Victor; Guittet, Pierre-Yves; Starr, Brian; Duncan, Craig; Ventola, Stefano; Klinger, Jan

    2005-05-01

    Wafer Current Measurement (WCM) is an emerging technique for in-line process monitoring. A joint development project (JDP) has been conducted by Infineon Technologies and Applied Ma-terials (Process Diagnostics and Control Group). The main goal of this project was development of applications for the WCM technique in production environment and specifically for state of the art DRAM Infineon process. A new generation of SEM review tool with integrated FIB (Ap-plied SEMVision G2 FIB Defect Analysis system) was used for this work. A challenging layer approached in this work was the DTMO (Deep Trench Mask Open) which serves as a hard mask for subsequent deep trench (DT) capacitor formation in a silicon substrate. The aspect ratio of the openings in the DTMO layer can be as high as 20:1. As a result of the aggressive aspect ra-tio and sub-100 nm CDs the only available techniques for evaluating DTMO etch integrity (pos-sible under-etch and/or bottom CD variation) are destructive analysis methods. As a result of the extensive JDP, crucial yield limiting problems such as dielectric or/and stop layer under-etch as well as bottom CD violation have been revealed by the WCM in-line rather than by cross-sectioning in failure analysis laboratory or other destructive means. Besides, on the basis of bottom CD sensitivity of the WCM technique, etch chamber qualification (including matching and adjustment) feasibility was conducted. The motivation behind this is that chamber qualification is essential to shorten cycle time. In production environment the WCM technique is targeted for two basic applications: process monitoring including excursion control and early etch process drift warning and in-line etch chamber qualification. WCM "pilot" has been performed in production after DTMO for four novel DRAM products with CD down to 70 nm.

  2. Post exposure bake unit equipped with wafer-shape compensation technology

    NASA Astrophysics Data System (ADS)

    Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

    2007-03-01

    In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

  3. Fine Mapping of the Interaction between C4b-Binding Protein and Outer Membrane Proteins LigA and LigB of Pathogenic Leptospira interrogans.

    PubMed

    Breda, Leandro C D; Hsieh, Ching-Lin; Castiblanco Valencia, Mónica M; da Silva, Ludmila B; Barbosa, Angela S; Blom, Anna M; Yung-Fu, Chang; Isaac, Lourdes

    2015-10-01

    The complement system consists of more than 40 proteins that participate in the inflammatory response and in pathogen killing. Complement inhibitors are necessary to avoid the excessive consumption and activation of this system on host cells. Leptospirosis is a worldwide zoonosis caused by spirochetes from the genus Leptospira. Pathogenic leptospires are able to escape from complement activation by binding to host complement inhibitors Factor H [FH] and C4b-binding protein (C4BP) while non-pathogenic leptospires are rapidly killed in the presence of fresh serum. In this study, we demonstrate that complement control protein domains (CCP) 7 and 8 of C4BP ?-chain interact with the outer membrane proteins LcpA, LigA and LigB from the pathogenic leptospire L. interrogans. The interaction between C4BP and LcpA, LigA and LigB is sensitive to ionic strength and inhibited by heparin. We fine mapped the LigA and LigB domains involved in its binding to C4BP and heparin and found that both interactions are mediated through the bacterial immunoglobulin-like (Big) domains 7 and 8 (LigA7-8 and LigB7-8) of both LigA and LigB and also through LigB9-10. Therefore, C4BP and heparin may share the same binding sites on Lig proteins. PMID:26517116

  4. Fine Mapping of the Interaction between C4b-Binding Protein and Outer Membrane Proteins LigA and LigB of Pathogenic Leptospira interrogans

    PubMed Central

    Breda, Leandro C. D.; Hsieh, Ching-Lin; Castiblanco Valencia, Mónica M.; da Silva, Ludmila B.; Barbosa, Angela S.; Blom, Anna M.; Yung-Fu, Chang; Isaac, Lourdes

    2015-01-01

    The complement system consists of more than 40 proteins that participate in the inflammatory response and in pathogen killing. Complement inhibitors are necessary to avoid the excessive consumption and activation of this system on host cells. Leptospirosis is a worldwide zoonosis caused by spirochetes from the genus Leptospira. Pathogenic leptospires are able to escape from complement activation by binding to host complement inhibitors Factor H [FH] and C4b-binding protein (C4BP) while non-pathogenic leptospires are rapidly killed in the presence of fresh serum. In this study, we demonstrate that complement control protein domains (CCP) 7 and 8 of C4BP ?-chain interact with the outer membrane proteins LcpA, LigA and LigB from the pathogenic leptospire L. interrogans. The interaction between C4BP and LcpA, LigA and LigB is sensitive to ionic strength and inhibited by heparin. We fine mapped the LigA and LigB domains involved in its binding to C4BP and heparin and found that both interactions are mediated through the bacterial immunoglobulin-like (Big) domains 7 and 8 (LigA7-8 and LigB7-8) of both LigA and LigB and also through LigB9-10. Therefore, C4BP and heparin may share the same binding sites on Lig proteins. PMID:26517116

  5. Comparison and Efficacy of LigaSure and Rubber Band Ligature in Closing the Inflamed Cecal Stump in a Rat Model of Acute Appendicitis

    PubMed Central

    Yeh, Chun-Chieh; Jan, Chia-Ing; Yang, Horng-Ren; Jeng, Long-Bin; Su, Wen-Pang

    2015-01-01

    Safety of either LigaSure or rubber band in closing inflamed appendiceal stump in acute appendicitis has been less investigated. In this study, cecal ligation followed by resecting inflamed cecum was performed to mimic appendectomy in a rat model of acute appendicitis. Rats were sacrificed immediately (Group A) and 7 days (Group B) after cecal resection, respectively. The cecal stumps were closed by silk ligature (S), 5?mm LigaSure (L), or rubber band (R). Seven days after cecal resection, the LigaSure (BL) and silk subgroups (BS) had significantly less intra-abdominal adhesion and better laparotomy wound healing than rubber band subgroup (BR). The initial bursting pressure at cecal stump was comparable among the three methods; along with tissue healing process, both BL and BS provided a higher bursting pressure than BR 7 days after appendectomy. BL subgroup had more abundant hydroxyproline deposition than BS and BR subgroup. Furthermore, serum TNF-? in BR group kept persistently increasing along with time after cecal resection. Thus, the finding that LigaSure but not rubber band is safe in sealing off the inflamed cecal stump in rat model of acute appendicitis suggests the possibility of applying LigaSure for appendectomy via single port procedure or natural orifice transluminal endoscopic surgery (NOTES). PMID:25699264

  6. Comparison and efficacy of LigaSure and rubber band ligature in closing the inflamed cecal stump in a rat model of acute appendicitis.

    PubMed

    Yeh, Chun-Chieh; Jan, Chia-Ing; Yang, Horng-Ren; Huang, Po-Han; Jeng, Long-Bin; Su, Wen-Pang; Chen, Hui-Chen

    2015-01-01

    Safety of either LigaSure or rubber band in closing inflamed appendiceal stump in acute appendicitis has been less investigated. In this study, cecal ligation followed by resecting inflamed cecum was performed to mimic appendectomy in a rat model of acute appendicitis. Rats were sacrificed immediately (Group A) and 7 days (Group B) after cecal resection, respectively. The cecal stumps were closed by silk ligature (S), 5 mm LigaSure (L), or rubber band (R). Seven days after cecal resection, the LigaSure (BL) and silk subgroups (BS) had significantly less intra-abdominal adhesion and better laparotomy wound healing than rubber band subgroup (BR). The initial bursting pressure at cecal stump was comparable among the three methods; along with tissue healing process, both BL and BS provided a higher bursting pressure than BR 7 days after appendectomy. BL subgroup had more abundant hydroxyproline deposition than BS and BR subgroup. Furthermore, serum TNF-? in BR group kept persistently increasing along with time after cecal resection. Thus, the finding that LigaSure but not rubber band is safe in sealing off the inflamed cecal stump in rat model of acute appendicitis suggests the possibility of applying LigaSure for appendectomy via single port procedure or natural orifice transluminal endoscopic surgery (NOTES). PMID:25699264

  7. The influence of feature sidewall tolerance on minimum absorber thickness for LIGA x-ray masks

    SciTech Connect

    S. K. Griffiths; J. M. Hruby; A. Ting

    1999-02-01

    Minimizing mask absorber thickness is an important practical concern in producing very small features by the LIGA process. To assist in this minimization, the authors have developed coupled numerical models describing both the exposure and development of a thick PMMA resist. The exposure model addresses multi-wavelength, one-dimensional x-ray transmission through multiple beam filters, through the mask substrate and absorber, and the subsequent attenuation and photon absorption in the PMMA resist. The development model describes one-dimensional dissolution of a feature and its sidewalls, taking into account the variation in absorbed dose through the PMMA thickness. These exposure and development models are coupled in a single interactive code, permitting the automated adjustment of mask absorber thickness to yield a prescribed sidewall taper or dissolution distance. They have used this tool to compute the minimum required absorber thickness yielding a prescribed sidewall tolerance for exposures performed at the ALS, SSRL and NSLS synchrotron sources. Results are presented as a function of the absorbed dose for a range of the prescribed sidewall tolerance, feature size, PMMA thickness, mask substrate thickness and the development temperature.

  8. 100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices

    SciTech Connect

    OLIVER,ANDREW D.; MATZKE,CAROLYN M.

    2000-04-06

    A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

  9. Quantitative phase measurement for wafer-level optics

    NASA Astrophysics Data System (ADS)

    Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

    2015-07-01

    Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

  10. Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.

    2004-01-01

    An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

  11. A novel post exposure bake technique to improve CD uniformity over product wafers

    NASA Astrophysics Data System (ADS)

    Takeishi, Tomoyuki; Hayasaki, K.; Shibata, Tsuyoshi

    2005-05-01

    The impact of wafer warpage on critical dimension (CD) control is getting larger in ArF lithography. The product wafers with stacked films are warped due to the stress caused by the difference in the film stack structure between the top side and the back side of the wafers. A typical warpage of the product wafers is of convex shape, and the amount of the warpage is larger than 50 ?m for 200mm wafer. On the other hand, proximity bake method is widely used in the Post Exposure Bake (PEB). When the warped wafer is placed on the hot plate, the gap between the wafer and the hot plate varies across the wafer. That is, the temperature of the wafer center is lower than that of wafer edge. Such a temperature variation affects CD uniformity within wafer. In particular the fact is obvious in ArF chemical amplified resist because PEB sensitivity of ArF resist is larger than 5nm/degree. In this study we optimize PEB zone temperature within wafer to suit the wafer warpage. This method is based on controlling zone temperature of the PEB hot plate with concentrically divided heaters. We carry out that the CD uniformity for the warped wafer is improved by 70% compared with the conventional process.

  12. Surface quality of silicon wafer improved by hydrodynamic effect polishing

    NASA Astrophysics Data System (ADS)

    Peng, Wenqiang; Guan, Chaoliang; Li, Shengyi

    2014-08-01

    Differing from the traditional pad polishing, hydrodynamic effect polishing (HEP) is non-contact polishing with the wheel floated on the workpiece. A hydrodynamic lubricated film is established between the wheel and the workpiece when the wheel rotates at a certain speed in HEP. Nanoparticles mixed with deionized water are employed as the polishing slurry, and with action of the dynamic pressure, nanoparticles with high chemisorption due to the high specific surface area can easily reacted with the surface atoms forming a linkage with workpiece surface. The surface atoms are dragged away when nanoparticles are transported to separate by the flow shear stress. The development of grand scale integration put extremely high requirements on the surface quality on the silicon wafer with surface roughness at subnanometer and extremely low surface damage. In our experiment a silicon sample was processed by HEP, and the surface topography before and after polishing was observed by the atomic force microscopy. Experiment results show that plastic pits and bumpy structures on the initial surface have been removed away clearly with the removal depth of 140nm by HEP process. The processed surface roughness has been improved from 0.737nm RMS to 0.175nm RMS(10?m×10?m) and the section profile shows peaks of the process surface are almost at the same height. However, the machining ripples on the wheel surface will duplicate on the silicon surface under the action of the hydrodynamic effect. Fluid dynamic simulation demonstrated that the coarse surface on the wheel has greatly influence on the distribution of shear stress and dynamic pressure on the workpiece surface.

  13. RELAXED SIGE ON INSULATOR FABRICATED VIA WAFER BONDING AND LAYER TRANSFER: ETCH-BACK AND SMART-CUT ALTERNATIVES

    E-print Network

    RELAXED SIGE ON INSULATOR FABRICATED VIA WAFER BONDING AND LAYER TRANSFER: ETCH-BACK AND SMART.25. The substrate is bonded to an oxidized Si handle wafer, and the Si backside of the SiGe wafer is ground. Various, for the Smart-cut approach, the CMPed SiGe wafer is transferred onto an oxidized Si handle wafer. In particular

  14. 232 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 16, NO. 2, APRIL 2007 Glass Blowing on a Wafer Level

    E-print Network

    Chen, Zhongping

    232 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 16, NO. 2, APRIL 2007 Glass Blowing on a Wafer--A fabrication process for the simultaneous shaping of arrays of glass shells on a wafer level is introduced wafer to the etched silicon wafer. The bonded wafers are then heated inside a furnace at a temperature

  15. Negative Photolithography Process Procedure with SU -8 Lithography consists of the following basic steps: Wafer preparation, photoresist

    E-print Network

    Kassegne, Samuel Kinde

    steps: Wafer preparation, photoresist coating, softbaking, exposing to UV light, post-exposure baking, and developing. 1. Prepare Wafer I. Simple Cleaning To remove contaminants from the wafer surface. a. Clean all equipment (wafer holders, tweezers, etc.) with acetone to avoid wafer contamination. b. Cover the surface

  16. Positive Photolithography Process Procedure with Shipley's 1813 Lithography consists of the following basic steps: Wafer preparation, photo resist

    E-print Network

    Kassegne, Samuel Kinde

    of the following basic steps: Wafer preparation, photo resist Coating, soft baking, exposing to UV light, post-exposure baking, and developing. 1. Prepare Wafer I. Simple Cleaning To remove contaminants from the wafer surface. a. Clean all equipment (wafer holders, tweezers, etc.) with acetone to avoid wafer contamination. b

  17. Wafer heating mechanisms in a molecular gas, inductively coupled plasma: in situ, real time wafer surface measurements and three-dimensional thermal modeling

    SciTech Connect

    Titus, M. J.; Graves, D. B.

    2008-09-15

    The authors report measurements and modeling of wafer heating mechanisms in an Ar/O{sub 2} inductively coupled plasma (ICP). The authors employed a commercially available on-wafer sensor system (PlasmaTemp developed by KLA-Tencor) consisting of an on-board electronics module housing battery power and data storage with 30 temperature sensors embedded onto the wafer at different radial positions. This system allows for real time, in situ wafer temperature measurements. Wafer heating mechanisms were investigated by combining temperature measurements from the PlasmaTemp sensor wafer with a three-dimensional heat transfer model of the wafer and a model of the ICP. Comparisons between pure Ar and Ar/O{sub 2} discharges demonstrated that two additional wafer heating mechanisms can be important in molecular gas plasmas compared to atomic gas discharges. The two mechanisms are heating from the gas phase and O-atom surface recombination. These mechanisms were shown to contribute as much as 60% to wafer heating under conditions of low bias power. This study demonstrated how the 'on-wafer' temperature sensor not only yields a temperature profile distribution across the wafer, but can be used to help determine plasma characteristics, such as ion flux profiles or plasma processing temperatures.

  18. Characterizing SOI Wafers By Use Of AOTF-PHI

    NASA Technical Reports Server (NTRS)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  19. Optical evaluation of ingot fixity in semiconductor wafer slicing

    NASA Astrophysics Data System (ADS)

    Ng, T. W.; Nallathamby, R.

    2004-11-01

    The fixity of an ingot may greatly affect the quality of wafers produced during a wire saw process and improved mechanical clamping is a means for improving ingot fixity. Here, an optical technique that is based on laser beam deflection is described. The technique was demonstrated on ingot assemblies subjected to impulse loads within a prescribed range using an original and improved clamping system. The technique revealed that the ingot assembly had lower degrees of mean displacement and standard displacement deviation under the improved clamping system. The data on warp obtained from the actual production of wafers corroborates this finding. The technique described is an effective method of quantitatively evaluating the fixity of ingots in a wafer wire saw process.

  20. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  1. Temperature influence in confocal techniques for a silicon wafer testing

    NASA Astrophysics Data System (ADS)

    Litwin, D.; Galas, J.; Sitarek, S.; Surma, B.; Piatkowski, B.; Miros, A.

    2007-05-01

    The paper discusses problems of Silicon wafer measurements accuracy in context of the scanning helium atom microscope, which is a new technique currently under development. In the microscope the helium atom beam is used as a probe. The overall microscope resolution depends on a deflecting element, which shapes the beam and focuses it onto a sample's surface. The most promising focusing component appears to be an ultra thin silicon wafer that is deformed under a precise electric field. Thus its quality is decisive for the project success. Flatness and thickness uniformity of the wafer must be measured in order to select the best plate to be used in the microscope. A scanning measurement system consists of two coaxially positioned confocal heads. Recent studies have revealed that the system is very sensitive to temperature variation. The compensation algorithms and further measures designed to suppress the temperature effect are presented and discussed.

  2. Interferometric and confocal techniques for testing of silicon wafers

    NASA Astrophysics Data System (ADS)

    Galas, J.; Litwin, D.; Sitarek, S.; Surma, B.; Piatkowski, B.; Miros, A.

    2006-04-01

    The paper provides new insights into Silicon wafer measurements in context of technological problems of developing a sophisticated measurement technique, which harnesses helium atom beam as a probe. Nano-resolution imaging techniques such as scanning tunnelling microscopy (STM) and atomic force microscopy (AFM) are well-know in surface science. A scanning helium atom microscope, where a focused beam of low energy, neutral helium atoms is used as an imaging probe is a new concept creating non-destructive and non-invasive surface investigation tool in science and industry. This paper is focused on measurements of flatness and thickness of the wafer, which is used as a deflecting mirror of the helium beam. Two -optics based- measurement techniques are presented: scanning confocal system and the Fizeau interferometer. The latter is applied as a quick reference device placed close to the production line whereas the former offers high accuracy flatness and thickness maps of the wafers.

  3. Wafer Fusion for Integration of Semiconductor Materials and Devices

    SciTech Connect

    Choquette, K.D.; Geib, K.M.; Hou, H.Q.; Allerman, A.A.; Kravitz, S.; Follstaedt, D.M.; Hindi, J.J.

    1999-05-01

    We have developed a wafer fusion technology to achieve integration of semiconductor materials and heterostructures with widely disparate lattice parameters, electronic properties, and/or optical properties for novel devices not now possible on any one substrate. Using our simple fusion process which uses low temperature (400-600 C) anneals in inert N{sub 2} gas, we have extended the scope of this technology to examine hybrid integration of dissimilar device technologies. As a specific example, we demonstrate wafer bonding vertical cavity surface emitting lasers (VCSELs) to transparent AlGaAs and GaP substrates to fabricate bottom-emitting short wavelength VCSELs. As a baseline fabrication technology applicable to many semiconductor systems, wafer fusion will revolutionize the way we think about possible semiconductor devices, and enable novel device configurations not possible by epitaxial growth.

  4. Minority lifetime degradation of silicon wafers after electric zone melting

    NASA Astrophysics Data System (ADS)

    Wu, M. C.; Yang, C. F.; Lan, C. W.

    2015-06-01

    The degradation of minority lifetime of mono- and multi-crystalline silicon wafers after electric zone melting, a simple and contamination-free process, was investigated. The thermal-stress induced dislocations were responsible to the degradation; however, the grain size also played a crucial role. It was believed that the grain boundaries helped the relaxation of thermal stress, so that the degradation was reduced as the grain size decreased. In addition to lifetime mapping and etch pit density, photoluminescence mapping was also used to examine the electrically active defects after zone melting. Factors affecting lifetime degradation of silicon wafers after electric zone melting were examined. Small-grain multi-crystalline wafers showed better lifetime after zone melting. Twining area showed better lifetime. The formation of new grains relaxed the thermal stress mitigating lifetime degradation.

  5. On-wafer magnetic resonance of magnetite nanoparticles

    NASA Astrophysics Data System (ADS)

    Little, Charles A. E.; Russek, Stephen E.; Booth, James C.; Kabos, Pavel; Usselman, Robert J.

    2015-11-01

    Magnetic resonance measurements of ferumoxytol and TEMPO were made using an on-wafer transmission line technique with a vector network analyzer, allowing for broadband measurements of small sample volumes (4 nL) and small numbers of spins (1 nmol). On-wafer resonance measurements were compared with standard single-frequency cavity-based electron paramagnetic resonance (EPR) measurements using a new power conservation approach and the results show similar line shape. On-wafer magnetic resonance measurements using integrated microfluidics and microwave technology can significantly reduce the cost and sample volumes required for EPR spectral analysis and allow for integration of EPR with existing lab-on-a-chip processing and characterization techniques for point-of-care medical diagnostic applications.

  6. The Relationship between the Bending Stress in Silicon Wafers and the Mechanical Strength of Silicon Crystals

    NASA Astrophysics Data System (ADS)

    Fukuda, Tetsuo

    1995-06-01

    Silicon wafers horizontally stacked in a vertical furnace bend downward due to their weight. Using a linear elastic theory, we calculated the shear stress caused by the wafer bending and investigated the mechanical strength by comparing the shear stress with the upper yield stress of silicon crystals. We concluded that the maximum shear stress increased with the increase in the wafer diameter, 0.20, 0.30, and 0.55 MPa for 6, 8, and 12 inch wafers. In bending the 12 inch wafers, oxygen precipitates, lowering the upper yield stress, caused serious wafer warping because the shear stress exceeded the lowered yield stress.

  7. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  8. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, Theodoer F. (31843 Miwok Trail, P.O. Box 1453, Evergreen, CO 80439)

    1995-01-01

    Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

  9. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    SciTech Connect

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  10. SUEX process optimization for ultra-thick high-aspect ratio LIGA imaging

    NASA Astrophysics Data System (ADS)

    Johnson, Donald W.; Goettert, Jost; Singh, Varshni; Yemane, Dawit

    2011-04-01

    The focus of this paper is on the use of SUEX Thick Dry Film Sheet (TDFS) laminates which DJ DevCorp is developing as a thick resist material in optical and X-ray lithography. Preliminary thick dry film sheets up to 1mm thickness were successfully prepared and patterned at the CAMD X-ray beamlines and presented at HARMST 2007. Recently, new results have been published using SUEX resist sheets in UV lithography showing great market potential including plating molds for metal microparts, polymer MEMS, multilayer microfluidics structures, BioMEMS, medical devices, wafer level packaging processes, and displays. The SUEX TDFS are available in a range of thicknesses from 100?m to 1mm or more and are pre-cut into a number of standard wafer sizes. This new material is a modified epoxy formulation containing an antimony-free photo acid generator (PAG) prepared under a highly controlled solvent-less process which provides uniform coatings between two throw-away layers of protective polyester film. As part of our initial studies resist layers of 250, 500 and 1000?m were laminated onto regular silicon wafers using a hot roll laminator at a speed of 1ft/min at 75°C. The entire substrate preparation takes about 1 hour and with practice users can prepare up to 10 substrates in this time which are typically ready to use within 2 hours. In our efforts to develop a commercially viable product we have conducted experiments using standard equipment available at CAMD (Quintel UV aligner and CAMD XRLM 1 and 4 beamline). Initial X-ray exposure tests were done with a bottom dose ranging between 100 and 400 J/cm3 and a top/bottom dose ratio of less than 3 for sheets up to 2mm in thickness. Exposure time for typical conditions of the CAMD storage ring (ring current ranging between 100 and 160mA, beam lifetime of about 10hrs at 100mA ring current) is about 10-15min for a 4' wafer. After exposure the samples were immediately post exposure baked between 70°C and 110°C using a convection oven, taken out and cooled to RT then relaxed up to 3 days before development to reduce stress. Development was done in PGMEA for up to 3 hours for the 1000?m thick samples followed by a short IPA rinse and drying in air. Very high aspect ratios of 100 or more have been routinely patterned with nearly perfectly straight sidewalls (~1-1.5?m deviation for a 1mm tall structure) and excellent image fidelity.

  11. 450mm wafer patterning with jet and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  12. On the viscoplastic response of a composite wafer

    NASA Technical Reports Server (NTRS)

    Valanis, K. C.; Landel, R. F.; Peng, S. T. J.

    1988-01-01

    In the present treatment of a viscoplastic composite wafer formed from a viscoplastic matrix that is reinforced by elastic or viscoplastic fibers attached to its plane surfaces, one constitutive equation is established by considering the viscoplastic behavior of the matrix as determined by an integral-type constitutive law whose intrinsic time-measure is pertinent to endochronic viscoplasticity. Attention is given to asymptotic cases where fiber stiffnesses and the hydrostatic modulus of the wafer are much larger than the latter's shear modulus. An explicit calculation is used when the stress field is uniaxial.

  13. An application of selective electrochemical wafer thinning for silicon characterization

    SciTech Connect

    Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

    1990-01-01

    A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

  14. Rayleigh surface wave in a piezoelectric wafer with subsurface damage

    NASA Astrophysics Data System (ADS)

    Cao, Xiaoshan; Jin, Feng; Jeon, Insu

    2009-12-01

    An analytical study is carried out on the propagation of Rayleigh surface waves in a piezoelectric wafer with subsurface damage. The region of subsurface damage is considered to be a functionally graded piezoelectric thin film. The findings show the influence of the gradient parameter, thickness of the region of subsurface damage, and three different types of damage on the properties of surface-wave propagation, including the phase velocity and electromechanical coupling factor. They can provide theoretical guidance in nondestructive evaluation for the analysis of the reliability and durability of electronic devices made of piezoelectric wafers.

  15. Chip-Scale Quadrupole Mass Filters for Portable Mass Spectrometry

    E-print Network

    Cheung, Kerry

    We report the design, fabrication, and characterization of a new class of chip-scale quadrupole mass filter (QMF). The devices are completely batch fabricated using a wafer-scale process that integrates the quadrupole ...

  16. Patterned growth of single-walled carbon nanotubes on full 4-inch wafers Nathan R. Franklin, Yiming Li, Robert J. Chen, Ali Javey, and Hongjie Daia)

    E-print Network

    Javey, Ali

    - pension of Al2O3 supported Fe/Mo catalyst in methanol11 was spun onto the wafer at a low speed of 250 These molecular-scale wires, derived by bottom-up chemical synthesis approaches, are also promising as core

  17. Multi-wafer slicing with a fixed abrasive

    NASA Technical Reports Server (NTRS)

    Schmid, Frederick (Inventor); Khattak, Chandra P. (Inventor); Smith, Maynard B. (Inventor)

    1988-01-01

    A wafering machine having a multiplicity of wire cutting blades supported by a bladehead reciprocally moving past a workpiece supported by a holder that rocks about an axis perpendicular to the wires at a frequency less than the reciprocation of the bladehead.

  18. Curvature measurement system of Si-wafer using circular gratings

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    2010-03-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. However, due to the prevalence of surface flatness measurement systems that flooded the market, the cycle time for curvature measurement system has become one of the critical factors for the user to consider. A simple and rapid whole-field curvature measurement system using a novel a computer aided phase shift reflection grating method has been developed and discussed in the previous publications. Laterals gratings in horizontal has vertical directions are needed in order to realize the curvature information on the wafer in both directions. In this paper, with same system setup, circular grating is being projected on to the specimen to measure the curvature distribution of the wafer. With the aid of coordinate-transform method and the digital phase-shifting technique, the digital images of reflected gratings are processed automatically and analyzed in the polar coordinate system. Unlike vertical or horizontal line gratings, the utilization of the circular gratings in radial shearing method provides curvature information in all directions, not only in one. Further, only four phase shifted images are captured and the measurement cycle time is thus reduced by half.

  19. Curvature measurement system of Si-wafer using circular gratings

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    2009-12-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. However, due to the prevalence of surface flatness measurement systems that flooded the market, the cycle time for curvature measurement system has become one of the critical factors for the user to consider. A simple and rapid whole-field curvature measurement system using a novel a computer aided phase shift reflection grating method has been developed and discussed in the previous publications. Laterals gratings in horizontal has vertical directions are needed in order to realize the curvature information on the wafer in both directions. In this paper, with same system setup, circular grating is being projected on to the specimen to measure the curvature distribution of the wafer. With the aid of coordinate-transform method and the digital phase-shifting technique, the digital images of reflected gratings are processed automatically and analyzed in the polar coordinate system. Unlike vertical or horizontal line gratings, the utilization of the circular gratings in radial shearing method provides curvature information in all directions, not only in one. Further, only four phase shifted images are captured and the measurement cycle time is thus reduced by half.

  20. Fabricating a Microcomputer on a Single Silicon Wafer

    NASA Technical Reports Server (NTRS)

    Evanchuk, V. L.

    1983-01-01

    Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

  1. Vibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements

    E-print Network

    Kao, Imin

    Vibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements I. Kao (PI), S the yield per crystal and to reduce the cost. In this paper, the vibration model of wiresaw system of vibration indicate the interference of excitation and natural frequencies in the vibration patterns

  2. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    SciTech Connect

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

  3. Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence

    E-print Network

    Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence H. C. Sio, Z-mediated nonclassical crystal growth of sodium fluorosilicate nanowires and nanoplates AIP Advances 1, 042165 (2011) Crystal phase and growth orientation dependence of GaAs nanowires on NixGay seeds via vapor

  4. Full wafer metrology for chemically graded thin films

    NASA Astrophysics Data System (ADS)

    Jobin, Marc; Jotterand, Stéphane; Pellodi, Cédric; dos Santos, Sergio; Sandu, Cosmin Silviu; Wagner, Estelle; Benvenuti, Giacomo

    2012-04-01

    Combinatorial CBVD (Chemical Beam Vapor Deposition) is a thin film deposition technology which has the ability to produce multi-element thin films with large controlled composition spread gradients. If functional characterizations can be carried out systematically and rapidly on such graded films over full wafers, they enable to identify precisely the best film composition for a given application, and CBVD then easily allows for the deposition of the optimized film homogeneously on large wafers. In this article, we demonstrate the efficiency of such a process development based on the optimization of new Transparent Conductive Oxide thin films (TCO) of few % Nb doped TiO2. We have developed a full wafer metrology instrument which maps the optical thickness and the sheet resistance with a lateral resolution below 400um. We discuss the performance of various algorithms to extract the optical thickness from the white light reflectance measurement in the case of very small thickness. The sheet resistance is measured with an array of four AFM-like conductive cantilevers, allowing accurate sheet resistance (R) measurement where the standard tungsten four probes destroy porous thin oxide films. Application of these measurements to several Nb doped TiO2 films deposited on 4" wafer by CBVD is presented.

  5. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  6. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    SciTech Connect

    Qiusheng, Y. Senkai, C. Jisheng, P.

    2015-03-30

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8?µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5?µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  7. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    NASA Astrophysics Data System (ADS)

    Qiusheng, Y.; Senkai, C.; Jisheng, P.

    2015-03-01

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  8. Production scale MOVPE reactors for electronic and optoelectronic applications

    NASA Astrophysics Data System (ADS)

    Protzmann, Harry; Gerstenbrandt, Georg; Alam, Assadullah; Schoen, Oliver; Luenenbuerger, Markus; Dikme, Yilmaz; Kalisch, Holger; Jansen, Rolf H.; Heuken, Michael

    2002-06-01

    In this letter a number of latest results from the process development on AIXTRON production scale MOVPE reactors will be reported. Growth of GaN on alternative substrates has been examined. Up to 900 nm crack free GaN layer were deposited on Si using a double nucleation interfacing technique. Low yellow band vs. band-edge related photoluminescence emission ratios have been observed and sheet resistances of up to 3500 ? have been achieved on 2" Si substrates. Also, first results are reported of the up-scaling of the Planetary Reactor to 24 x 2". First results from fully loaded runs show an average 2" on wafer peak wavelength standard deviation of 3.8 nm, average wafer to wafer standard deviation across all wafers of 2.0 nm and average 3 x 2" disk to disk standard deviation of 1.6 nm at an average wavelength of 477.9 nm across all wafers (evaluated with peak integration and 2 mm edge exclusion for the 2" wafers). Photoluminescence peak intensity (area) varied with 13.6% standard deviation wafer to wafer and 12.8% disk to disk. On wafer intensity deviation was 11.3%.

  9. Production scale MOVPE reactors for electronic and optoelectronic applications

    NASA Astrophysics Data System (ADS)

    Protzmann, Harry; Gerstenbrandt, Georg; Alam, Assadullah; Schoen, Oliver; Luenenbuerger, Markus; Dikme, Yilmaz; Kalisch, Holger; Jansen, Rolf H.; Heuken, Michael

    2003-06-01

    In this letter a number of latest results from the process development on AIXTRON production scale MOVPE reactors will be reported. Growth of GaN on alternative substrates has been examined. Up to 900 nm crack free GaN layer were deposited on Si using a double nucleation interfacing technique. Low yellow band vs. band-edge related photoluminescence emission ratios have been observed and sheet resistances of up to 3500 ?/? have been achieved on 2" Si substrates. Also, first results are reported of the up-scaling of the Planetary Reactor to 24 x 2". First results from fully loaded runs show an average 2" on wafer peak wavelength standard deviation of 3.8 nm, average wafer to wafer standard deviation across all wafers of 2.0 nm and average 3 x 2" disk to disk standard deviation of 1.6 nm at an average wavelength of 477.9 nm across all wafers (evaluated with peak integration and 2 mm edge exclusion for the 2" wafers). Photoluminescence peak intensity (area) varied with 13.6% standard deviation wafer to wafer and 12.8% disk to disk. On wafer intensity deviation was 11.3%.

  10. Test-Pattern Ordering for Wafer-Level Test-During-Burn-In

    E-print Network

    Chakrabarty, Krishnendu

    Test-Pattern Ordering for Wafer-Level Test-During-Burn-In Sudarshan Bahukudumbi and Krishnendu Chakrabarty Department of Electrical and Computer Engineering Duke University, Durham, NC 27708 Abstract--Wafer [1]. Wafer level burn-in (WLBI) has recently emerged as an enabling technology to lower the cost

  11. Comparison of Wafer-level Spatial IDDQ Estimation Methods: NNR versus NCR Sagar S. Sabade*

    E-print Network

    Walker, Duncan M. "Hank"

    Comparison of Wafer-level Spatial IDDQ Estimation Methods: NNR versus NCR Sagar S. Sabade* D. M. H in IDDQ at the wafer level for estimating fault-free IDDQ of a chip are proposed. This paper compares two its sensitivity is a topic of research in recent years [1][2]. Several methods that use wafer

  12. Modeling of hydrophilic wafer bonding by molecular dynamics simulations David A. Litton and Stephen H. Garofalinia)

    E-print Network

    Garofalini, Stephen H.

    Modeling of hydrophilic wafer bonding by molecular dynamics simulations David A. Litton and Stephen for publication 31 December 2000 The role of moisture in hydrophilic wafer bonding was modeled using molecular Institute of Physics. DOI: 10.1063/1.1351538 I. INTRODUCTION Wafer bonding technology takes advantage

  13. Integration of Self-Assembled Three-Dimensional Photonic Crystals onto Structured Silicon Wafers

    E-print Network

    Jonsson, Fredrik

    Integration of Self-Assembled Three-Dimensional Photonic Crystals onto Structured Silicon Wafers silica spheres (diameter of 890 nm), self-assembled in hydrophilic trenches of silicon wafers by using a spatial selectivity of opal crystallization without special treatment of the wafer surface, a filling

  14. Improved Wafer-level Spatial Analysis for IDDQ Limit Setting Sagar Sabade D. M. H. Walker

    E-print Network

    Walker, Duncan M. "Hank"

    Improved Wafer-level Spatial Analysis for IDDQ Limit Setting Sagar Sabade D. M. H. Walker methodology for estimating the upper bound on the IDDQ of defect free chips by using wafer level spatial data. Such a methodology accounts for the change in IDDQ due to process variations across wafers

  15. Integrated Modeling of Wiresaw in Wafer Slicing I. Kao (PI), M. Bhagavat, V. Prasad

    E-print Network

    Kao, Imin

    Integrated Modeling of Wiresaw in Wafer Slicing I. Kao (PI), M. Bhagavat, V. Prasad Department of an integrated model of the wiresaw manufacturing processes in wafer slicing. The wiresaw, utilizing the "Free) and large diameter ( 200 mm) wafers required in photovoltaic and semiconductor industries, respectively. FAM

  16. MultiProject Reticle Design and Wafer Dicing under Uncertain Demand #

    E-print Network

    Kahng, Andrew B.

    Multi­Project Reticle Design and Wafer Dicing under Uncertain Demand # Andrew B. Kahng, Ion M wafers (MPW) have been proposed as an effective technique for sharing the cost of mask tooling among up optimizations that arise in this context: reticle design under demand uncertainty and on­ demand wafer dicing

  17. wafer bonding approach allows point de-fects and potentially also waveguides to be

    E-print Network

    Zhuang, Xiaowei

    188 wafer bonding approach allows point de- fects and potentially also waveguides to be introduced parallel to the layers by proper lithography. In addition, wafer bonding can incorporate a layer that acts implica- tions? In principle, the combination of li- thography, etching, and wafer bonding could

  18. Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels

    E-print Network

    Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels Wei. wafers using NIL at all lithography levels. The nanotransistors exhibit excellent operational characteristics across the wafer. The statistics from consecutive multiwafer processing show an average overlay

  19. Mechanically flexible thin-film transistors that use ultrathin ribbons of silicon derived from bulk wafers

    E-print Network

    Rogers, John A.

    wafers S. Mack, M. A. Meitl, A. J. Baca, Z.-T. Zhu, and J. A. Rogersa Department of Materials Science created by lithographic patterning and anisotropic etching of bulk silicon 111 wafers. Devices described top-down methods5­11 generate semicon- ductor wires, ribbons, and sheets from wafer based sources

  20. Wafer Topography-Aware Optical Proximity Correction for Better DOF Margin and CD Control

    E-print Network

    Kahng, Andrew B.

    Wafer Topography-Aware Optical Proximity Correction for Better DOF Margin and CD Control Puneet are oblivious to the predictable nature of focus variation arising from wafer topography. As a result, designers that is generated by CMP simulation. The wafer topography variations result in local defocus, which we explicitly

  1. Megasonic cleaning of wafers in electrolyte solutions: Possible role of electro-acoustic and cavitation effects

    E-print Network

    Deymier, Pierre

    Megasonic cleaning of wafers in electrolyte solutions: Possible role of electro Keywords: Wafer Cleaning Electrolyte Megasonic Electro-acoustic Cavitation Pressure amplitude a b s t r a c t Investigations have been conducted on the feasibility of removal of particles from silicon wafers in elec

  2. Noncontact semiconductor wafer characterization with the terahertz Hall D. M. Mittleman,a)

    E-print Network

    Natelson, Douglas

    Noncontact semiconductor wafer characterization with the terahertz Hall effect D. M. Mittleman,a) J wafers with roughly 250 m spatial resolution, using polarization rotation of focused beams of terahertz carrier density and mobility of a doped semiconductor wafer have been obtained. © 1997 American Institute

  3. Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand*

    E-print Network

    Kahng, Andrew B.

    Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand* Andrew B. Kahng, Ion leads to dramatic increases in mask costs. In response to this trend, mUltiple project wafers (MPW) have in this context: reticle design under demand uncertainty and on demand wafer dicing. Preliminary experiments

  4. Behaviour of Natural and Implanted Iron during Annealing of Multicrystalline Silicon Wafers

    E-print Network

    Behaviour of Natural and Implanted Iron during Annealing of Multicrystalline Silicon Wafers Daniel, recombination Abstract. Changes in the concentration of interstitial iron in multicrystalline silicon wafers-grown multicrystalline silicon wafers. Introduction Iron is a common impurity in multicrystalline silicon (mc

  5. Supplemental Information for "Variations in properties of atomic force microscope cantilevers fashioned from the same wafer"

    E-print Network

    Chan, Derek Y C

    fashioned from the same wafer" Grant B. Webber1,2 , Geoffrey W. Stevens1 , Franz Grieser2 , Raymond R microscopy of 101 V-shaped cantilevers derived from the same wafer as received from the manufacturer by the thermal method and optical microscopy of 101 V-shaped cantilevers derived from the same wafer as received

  6. Theoretical calculation of the acoustic force on a patterned silicon wafer during megasonic cleaning

    E-print Network

    Deymier, Pierre

    Theoretical calculation of the acoustic force on a patterned silicon wafer during megasonic wafer immersed in water subjected to a megasonic beam. The method of calculation is based on a Green as a function of frequency and the angle the incident megasonic beam makes with the wafer surface

  7. Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand

    E-print Network

    Zelikovsky, Alexander

    Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand Andrew B. Kahng, Ion Mandoiu leads to dramatic increases in mask costs. In response to this trend, multiple project wafers (MPW) have in this context: reticle design under demand uncertainty and on- demand wafer dicing. Preliminary experiments

  8. Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs

    E-print Network

    Lü, James Jian-Qiang

    Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs J Montopolis Drive, Austin TX 78741 Abstract -- Electrical and mechanical impacts of wafer bonding and thinning interconnect structures. This procedure permits evaluation of bonding and thinning integrity without inter-wafer

  9. A LOW COST WAFER-LEVEL MEMS PACKAGING TECHNOLOGY Pejman Monajemi, Paul J. Joseph*

    E-print Network

    Ayazi, Farrokh

    A LOW COST WAFER-LEVEL MEMS PACKAGING TECHNOLOGY Pejman Monajemi, Paul J. Joseph* , Paul A. Kohl-cost low-temperature packaging technique for wafer-level encapsulation of MEMS devices fabricated on any arbitrary substrate. The packaging process presented here does not involve wafer bonding and can be applied

  10. A Material Removal Model for CMP Based on the Contact Mechanics of Pad, Abrasives, and Wafer

    E-print Network

    Müftü, Sinan

    A Material Removal Model for CMP Based on the Contact Mechanics of Pad, Abrasives, and Wafer Dinçer, Massachusetts 02115, USA Applied pressure in chemical mechanical polishing CMP is shared by the two-body pad­wafer and the three-body pad­abrasive­ wafer contacts. The fraction of applied pressure transferred through

  11. Spatio-Temporal Wafer-Level Correlation Modeling with Progressive Sampling: A Pathway to HVM

    E-print Network

    Makris, Yiorgos

    Spatio-Temporal Wafer-Level Correlation Modeling with Progressive Sampling: A Pathway to HVM Yield Abstract--Wafer-level spatial correlation modeling of probe- test measurements has been explored of a popular Gaussian process-based wafer-level spatial correlation method through two key enhancements: (i

  12. Multilevel nanoimprint lithography with submicron alignment over 4 in. Si wafers

    E-print Network

    Multilevel nanoimprint lithography with submicron alignment over 4 in. Si wafers Wei Zhanga that multilevel nanoimprint lithography NIL with submicron alignment over an entire 4 in. Si wafer can be achieved in ten consecutive tests of multilevel NIL. The multilevel alignment was achieved by aligning the wafer

  13. Test Cost Analysis for 3D Die-to-Wafer Stacking Mottaqiallah Taouil1

    E-print Network

    Test Cost Analysis for 3D Die-to-Wafer Stacking Mottaqiallah Taouil1 Said Hamdioui1 Kees Beenakker2 footprint. Several 3D stacking approaches are under development. From a yield point of view, Die-to-Wafer (D the stack yield is the best approach to use. Keywords: 3D test flow, 3D test cost, Die-to-Wafer stack- ing

  14. Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques

    E-print Network

    Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques Gianni-insulator include SIMOX, Ge condensation and wafer bonding. In this paper, a brief introduction of each method is presented, with a detailed discussion of wafer bonding approaches for strained Si, SiGe, and Ge on

  15. Numerical Simulation of a Single-Wafer Isothermal Plasma Etching Reactor

    E-print Network

    Economou, Demetre J.

    Numerical Simulation of a Single-Wafer Isothermal Plasma Etching Reactor Sang-Kyu Parkand Demetre J-plate single- wafer isothermal reactor was conducted. The oxygen plasma etching of polymer under high pressure as the flow rate increased. Etching rate increased but etching uniformity degraded as the wafer reactivity

  16. Electrical characterization of annular Through Silicon Vias for a Reconfigurable Wafer-sized Circuit Board

    E-print Network

    Hamoui, Anas

    Electrical characterization of annular Through Silicon Vias for a Reconfigurable Wafer characterization of annular TSV technology for full wafer applications. A possible utilization of this technology is the WaferBoardTM , a reconfigurable circuit board for rapid system prototyping. Electrical resistance

  17. Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests

    E-print Network

    Makris, Yiorgos

    Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests Ke of wafer-level measurements has recently attracted increased attention. Exist- ing approaches for capturing spatial correlation modeling of wafer- level analog/RF tests to handle such effects and, thereby

  18. Determining Pad-Wafer Contact using Dual Emission Laser Induced Fluorescence Caprice Gray1

    E-print Network

    White, Robert D.

    Determining Pad-Wafer Contact using Dual Emission Laser Induced Fluorescence Caprice Gray1 , Chris operating during CMP requires knowledge of the nature of the pad-wafer contact. Dual Emission Laser Induced Fluorescence (DELIF) can be used to study the fluid layer profile between the polishing pad and the wafer

  19. Mask blank defect printability comparison using optical and SEM mask and wafer inspection and bright field actinic mask imaging

    NASA Astrophysics Data System (ADS)

    Mangat, Pawitter; Verduijn, Erik; Wood, Obert R.; Benk, Markus P.; Wojdyla, Antoine; Goldberg, Kenneth A.

    2015-07-01

    Despite significant enhancements in defect detection using optical and e-beam methodology, the smaller length scales and increasing challenges of future technology nodes motivate ongoing research into the need and associated cost of actinic inspection for EUV masks. This paper reports an extensive study of two EUV patterned masks, wherein the mask blank defectivity was characterized using optical (mask and wafer) methods and bright-field mask imaging (using the SHARP actinic microscope) of previously identified blank defects. We find that the bright field actinic imaging tool microscope captures and images many defects that are not seen by the automated optical inspection of patterned masks and printed wafers. In addition, actinic review reveals the impact of multilayer damage and depicts the printability profile which can be used as an added metric to define the patterned mask repair and defect compensation strategies.

  20. Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

    PubMed

    Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

    2008-07-30

    Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ?2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer. PMID:21828759

  1. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Luo, Xianshu; Cao, Yulian; Song, Junfeng; Hu, Xiaonan; Cheng, Yungbing; Li, Chengming; Liu, Chongyang; Liow, Tsung-Yang; Yu, Mingbin; Wang, Hong; Wang, Qijie; Lo, Patrick Guo-Qiang

    2015-04-01

    Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS) fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W) bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP) laser, lateral-coupled distributed feedback (LC-DFB) laser with side wall grating, and mode-locked laser (MLL). From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC).

  2. Enhanced capture rate for haze defects in production wafer inspection

    NASA Astrophysics Data System (ADS)

    Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

    2010-03-01

    Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure involved scanning with three different recipe types: Standard Inspection: Nominal recipe with a low false alarm rate was used to scan the wafer and repeaters were extracted from the final defect map. Haze Monitoring Application: Recipe sensitivity was enhanced and run on a single field column from which on repeating defects were extracted. Enhanced Repeater Extractor: Defect processing included the two parallel routes: a nominal recipe for the random defects and the new high sensitive repeater extractor algorithm. The results showed that the new application (recipe #3) had the highest capture rate on haze defects and detected new repeater defects not found in the first two recipes. In addition, the recipe was much simpler to setup since repeaters are filtered separately from random defects. We expect that in the future, with the advent of mask-less lithography and EUV lithography, the monitoring of field and die repeating defects on the wafer will become a necessity for process control in the semiconductor fab.

  3. Scale

    ERIC Educational Resources Information Center

    Schaffhauser, Dian

    2009-01-01

    The common approach to scaling, according to Christopher Dede, a professor of learning technologies at the Harvard Graduate School of Education, is to jump in and say, "Let's go out and find more money, recruit more participants, hire more people. Let's just keep doing the same thing, bigger and bigger." That, he observes, "tends to fail, and fail…

  4. Wafer-level packaging with compression-controlled seal ring bonding

    DOEpatents

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  5. Measurement and modeling of time- and spatial-resolved wafer surface temperature in inductively coupled plasmas

    SciTech Connect

    Hsu, C. C.; Titus, M. J.; Graves, D. B.

    2007-05-15

    The transient temperature profile across a commercial wafer temperature sensor device in an inductively coupled Ar plasma is reported. The measured temperatures are compared to model predictions, based on a coupled plasma-wafer model. The radial temperature profile is the result of the radial profile in the ion energy flux. The ion energy flux profile is obtained by combining the Langmuir probe measurement, the ion wall flux probe measurement, and a plasma model. A methodology to estimate the ion flux profile using the sensor measurements has been validated by combining the plasma measurements, the wafer temperature measurements, and the plasma-wafer model. It is shown that with minimal heat transfer between the wafer and the chuck, the initial transient wafer temperature profile after plasma ignition can be used to estimate the ion energy flux profile across the wafer.

  6. Influence of the bonding front propagation on the wafer stack curvature

    SciTech Connect

    Navarro, E.; Bréchet, Y.; Barthelemy, A.; Radu, I.; Pardoen, T.; Raskin, J.-P.

    2014-08-11

    The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

  7. Single incision cholecystectomy using a clipless technique with LigaSure in a resource limited environment: The Bahamas experience

    PubMed Central

    Downes, Ross O.; McFarlane, Michael; Diggiss, Charles; Iferenta, James

    2015-01-01

    Background Scarless/single-incision laparoscopic cholecystectomy (SILC) is a new procedure. It affords a superior cosmetic outcome when compared to conventional laparoscopic cholecystectomy. We examine the application of this technique using LigaSure via a clipless method. The present study looks at the experience of a single surgeon using this method with initial evaluation of the safety, feasibility, affordability, and benefits of this procedure. Methods Twenty-eight patients underwent transumbilical SILC at Doctors Hospital from January to December, 2014. The cohort included both emergency and elective patients. There was no difference in the preoperative work-up as indicated. To perform the operation, a 2–2.5-cm linear incision was made through the umbilicus and the single port platform utilized. A 10 mm 30-degree laparoscope, a 5 mm LigaSure and straight instruments were used to perform the laparoscopic cholecystectomy procedure. Results All patients except two were operated on successfully. Conversion was considered the placement of an additional epigastric/Right upper quadrant (RUQ) port. The conversion rate to standard LC was 7%. No patient was converted to open cholecystectomy. In the 28 successfully completed patients, the median duration of the operation was 38.5 min and estimated operative blood loss was 24 ml. Patients were commenced on liquid diet immediately on being fully conscious and after return to the ward with an estimated time of 6 h. The mean postoperative hospital stay was 1.4 days. Follow-up visits were conducted for all patients at 2-weeks intervals and continued for 6 weeks after surgery where possible. Two patients developed wound infections. All patients were satisfied with the good cosmetic effect of the surgery. The total satisfaction rate was 100%. Conclusions SILC is a safe and feasible technique for operating with scarless outcomes and reducing perioperative discomfort at the same time. The GelPOINTTM is a safe and feasible platform to be used. The procedure can be accomplished using regular instruments and laparoscope. Curved instruments and a bariatric length laparoscope may make the procedure easier and result in greater time saving. The addition of LigaSure™ decreases the complexity of the operation, decreases operative time and blood loss. The technique is economical in a resource-limited environment. PMID:25958050

  8. Wafer Alignment marks Wx, Wy, W . Also called Search marks or WGA marks. These are used to establish wafer position on the stage and orients the X and Y alignment

    E-print Network

    Reif, Rafael

    Wafer Alignment marks Wx, Wy, W . Also called Search marks or WGA marks. These are used to establish wafer position on the stage and orients the X and Y alignment marks on wafer, making them parallel to the Y stage mirror. This is called Wafer Global Alignment (WGA). Wy and W were once separate marks. Now

  9. Designing DWDM multiplexers on SiON wafers

    NASA Astrophysics Data System (ADS)

    Dragnea, Laurentiu

    2010-11-01

    I propose an integrated multiplexer/demultiplexer that use a concave blazed diffraction grating on SiON wafer. The paper presents a technology that overcome existing issues regarding implementation of such a microoptic device. Two types of similar integrated systems were developed but both of them have not minimized chromatic, astigmatism and spherical aberrations. Both systems use gold coating for vertical walls of diffraction grating that has reflection index lower than aluminum for wavelength used. Technology proposed in this paper minimizes the chromatic, astigmatism and spherical aberrations. Also is used aluminum for coating of vertical walls of diffraction grating. SiON wafer is etched with Argon plasma through photoresist mask with thickness of 0,8 ?m for grating configuration allowing reusing of the photoresist in next stage of coating. This makes possible that coating through liftoff to be aligned to vertical walls of concave diffraction grating, eliminating positioning errors due to coating mask.

  10. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    SciTech Connect

    Montoya, Angela C.; Maji, Arup K.

    2010-02-22

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  11. Chemical method for producing smooth surfaces on silicon wafers

    DOEpatents

    Yu, Conrad (Antioch, CA)

    2003-01-01

    An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

  12. Sputter deposition of SiC coating on silicon wafers

    NASA Technical Reports Server (NTRS)

    Robson, M. T.; Blue, C. A.; Warrier, S. G.; Lin, R. Y.

    1992-01-01

    A study is conducted of the effect of substrate temperature during coating on the properties of coated SiC films on Si wafers, using a scratch test technique. While specimen temperature during coating has little effect on deposition rate, it significantly affects the durability of the coating. Scratch test damage to both film coating and substrate decreased with increasing deposition temperature, perhaps due to the rapid diffusion of the deposited atoms.

  13. Cost of Czochralski wafers as a function of diameter

    NASA Technical Reports Server (NTRS)

    Leipold, M. H.; Radics, C.; Kachare, A.

    1980-01-01

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

  14. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    NASA Astrophysics Data System (ADS)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 ?m AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 ?m pixel size and 160x120, 52 ?m pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  15. Influence of gas composition on wafer temperature in a tungsten chemical vapor deposition reactor: Experimental measurements, model

    E-print Network

    Rubloff, Gary W.

    Influence of gas composition on wafer temperature in a tungsten chemical vapor deposition reactor 13 April 2000; accepted 23 October 2000 Experimental measurements of wafer temperature in a single-wafer, lamp-heated chemical vapor deposition system were used to study the wafer temperature response to gas

  16. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    SciTech Connect

    Daix, N. Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup ?2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  17. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates

    NASA Astrophysics Data System (ADS)

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-10-01

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the “melt-back” effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200?°C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20??m was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude.

  18. Stress measurement of thin wafer using reflection grating method

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand K.

    2010-08-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this research, the system is calibrated with reference to stress measurement equipment from KLA-Tencor. Some initial results based on a joint project with Infineon Technologies are re-examined. The stress distribution of the wafers are derived with the aid of Stoney's equation. Finally, the results from our proposed system are compared and contrasted with data obtained from KLA-Tencor equipment.

  19. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, C.M.; Hui, W.C.

    1996-11-19

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

  20. Physical mechanisms of copper-copper wafer bonding

    NASA Astrophysics Data System (ADS)

    Rebhan, B.; Hingerl, K.

    2015-10-01

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing.

  1. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, Conrad M. (Antioch, CA); Hui, Wing C. (Campbell, CA)

    1996-01-01

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

  2. Scales

    SciTech Connect

    Murray Gibson

    2007-04-27

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain — a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  3. Scales

    ScienceCinema

    Murray Gibson

    2010-01-08

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain ? a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  4. Magnetic Phase Diagram of the Breathing Pyrochlore Antiferromagnet LiGa1-xInxCr4O8

    NASA Astrophysics Data System (ADS)

    Okamoto, Yoshihiko; Nilsen, Gøran J.; Nakazono, Taishi; Hiroi, Zenji

    2015-04-01

    The spinel oxides LiGaCr4O8 and LiInCr4O8 contain size-alternating pyrochlore lattices of spin-3/2 Cr3+ tetrahedra with different magnitudes of alternation. We show here that the solid solutions LiGa1-xInxCr4O8 between these two "breathing" pyrochlore compounds display (i) rapid suppression of magnetic and structural transitions upon doping the end members, (ii) spin-glass-like freezing above 2 K in the range 0.1 ? x ? 0.6, and (iii) apparent spin-gap behavior for x ? 0.7. Furthermore, no transitions are observed above 2 K at x ˜ 0.9, where magnetic susceptibility remains finite at 2 K and magnetic heat capacity shows a quadratic temperature dependence at 1-5 K. Our work shows that breathing pyrochlore compounds provide a unique opportunity for studying both geometrical frustration and bond alternation.

  5. B-Cell-Specific Peptides of Leptospira interrogans LigA for Diagnosis of Patients with Acute Leptospirosis

    PubMed Central

    Kanagavel, Murugesan; Shanmughapriya, Santhanam; Anbarasu, Kumarasamy

    2014-01-01

    Leptospirosis is a reemerging infectious disease that is underdiagnosed and under-recognized due to low-sensitivity and cumbersome serological tests. Rapid reliable alternative tests are needed for early diagnosis of the disease. Considering the importance of the pathogenesis-associated leptospiral LigA protein expressed in vivo, we have evaluated its application in the diagnosis of the acute form of leptospirosis. The C-terminal coding sequence of ligA (ligA-C) was cloned into pET15b and expressed in Escherichia coli. Furthermore, the B-cell-specific epitopes were predicted and were synthesized as peptides for evaluation along with recombinant LigA-C. Epitope 1 (VVIENTPGK), with a VaxiJen score of 1.3782, and epitope 2 (TALSVGSSK), with a score of 1.2767, were utilized. A total of 140 serum samples collected from leptospirosis cases during the acute stage of the disease and 138 serum samples collected from normal healthy controls were utilized for evaluation. The sensitivity, specificity, positive predictive value, and negative predictive value were calculated for the recombinant LigA-C-specific IgM enzyme-linked immunosorbent assay (ELISA) and were found to be 92.1%, 97.7%, 92.8%, and 97.5%, respectively. Epitopes 1 and 2 used in the study showed 5.1 to 5.8% increased sensitivity over recombinant LigA-C in single and combination assays for IgM antibody detection. These findings suggest that these peptides may be potential candidates for the early diagnosis of leptospirosis. PMID:24403522

  6. Design, fabrication and measurement of a novel 140?GHz folded waveguide based on SU-8 UV-LIGA technology

    NASA Astrophysics Data System (ADS)

    Xie, Fuqiang; Ding, Guifu; Zhao, Xiaolin; Cheng, Ping

    2015-08-01

    In an RF MEMS field, a folded waveguide is the core structure of a traveling wave tube as a slow-wave structure. 140?GHz is an important atmospheric working window. In this paper, the dispersion property and interaction impedance of a novel 140?GHz folded waveguide were analyzed and simulated using CST Microwave Studio. The beam-wave interaction in the folded waveguide was also simulated, using CST Particle Studio. The output power gain of the folded waveguide reached 24.5?dB at 140?GHz when the emission voltage was 12.7?kV and the emission current was 0.15?A. The simulation process provided structure parameters for further micromachining. Furthermore, to analyze the effect of structure fabrication errors, CST was used to simulate the dispersion and interaction impedance by adding tolerance to some important structure parameters. Finally, multi-step SU-8 UV-LIGA technology was adopted for micromachining the folded waveguide. To ensure adhesion between the SU-8 photoresist and substrate, a thin TiO2 film was formed on the surface of the Ti substrate. In the end, test results showed that the reflection coefficient S 11 and transmission coefficient S 21 were near -28.1?dB and -1.2?dB respectively. Moreover, the output power gain was close to 23?dB at 140?GHz. Good accordance between the simulation and experimental results indicated a reasonable design and high precision of microfabrication by SU-8 UV-LIGA technology.

  7. Penetration of plasma into the wafer-focus ring gap in capacitively coupled plasmas

    SciTech Connect

    Babaeva, Natalia Y.; Kushner, Mark J.

    2007-06-01

    In plasma etching equipment for microelectronics fabrication, there is an engineered gap between the edge of the wafer and wafer terminating structures, such as focus rings. The intended purpose of these structures is to make the reactant fluxes uniform to the edge of the wafer and so prevent a larger than desired edge exclusion where useful products cannot be obtained. The wafer-focus ring gap (typically<1 mm) is a mechanical requirement to allow for the motion of the wafer onto and off of the substrate. Plasma generated species can penetrate into this gap and under the beveled edge of the wafer, depositing films and possibly creating particles which produce defects. In this paper, we report on a computational investigation of capacitively coupled plasma reactors with a wafer-focus ring gap. The penetration of plasma generated species (i.e., ions and radicals) into the wafer-focus ring gap is discussed. We found that the penetration of plasma into the gap and under the wafer bevel increases as the size of the gap approaches and exceeds the Debye length in the vicinity of the gap. Deposition of, for example, polymer by neutral species inside the gap and under the wafer is less sensitive to the size of the gap due the inability of ions, which might otherwise sputter the film, to penetrate into the gap.

  8. Warpage Analysis of Silicon Wafer in Ingot Slicing by Wire-Saw Machine

    NASA Astrophysics Data System (ADS)

    Yamada, Toshiro; Kinai, Fumiaki; Ichikawa, Takesh; Yokoyama, Atsushi; Fukunaga, Moritaka; Ohshita, Takashi

    2004-06-01

    It is possible thermal expansion from heat generation by slicing deforms a single-crystal silicon ingot but the authors can find no report on the point. In addition, numerical analysis is useful to clarify the mechanism of wafer warping but no paper has been reported the numerical analysis from the start to end of the wafer slicing process. The authors carried out experiments for the wafer slicing. In addition, a finite element analysis was carried out in order to solve the warping mechanism from the start to end of the wafer slicing process. The warp of wafer in the vertical direction was 6.05 ? m in the experiment whereas the warp in the finite element analysis was 5.30 ? m. The result by the finite element analysis gave good agreement with experimental one. This paper suggests that thermal expansion of the ingot has great influence on the warp of wafer.

  9. On the residual stress and fracture strength of crystalline silicon wafers

    NASA Astrophysics Data System (ADS)

    Yang, Chris; Mess, Frank; Skenes, Kevin; Melkote, Shreyes; Danyluk, Steven

    2013-01-01

    This letter reports on residual stress measurement in thin crystalline silicon wafers with a full-field near-infrared polariscope. Residual stress is analyzed in combination with observed surface defects, and the results are related to measured fracture strength variation in the wafers. Measurements indicate that there is a sawing process-related residual stress in the as-cut wafers, and that etch-removal of ˜5 ?m from the wafer surface eliminates a damage layer that can significantly reduce the residual stress in the wafer, and therefore increases the observed fracture strength. There is a corresponding 2 to 3 ?m reduction in the observed characteristic defect size after etching. Fracture strength anisotropy observed in the wafers is related to defect orientation (scratching grooves and microcracks) caused by the sawing process.

  10. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

    1979-01-01

    A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

  11. Multiproject wafers: not just for million-dollar mask sets

    NASA Astrophysics Data System (ADS)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task dictates careful consideration of the alternative methods.

  12. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  13. Alternative fabrication process for edgeless detectors on 6 in. wafers

    NASA Astrophysics Data System (ADS)

    Kalliopuska, Juha; Eränen, Simo; Virolainen, Tuula

    2011-05-01

    VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150 ?m thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 5×5 and 1×1 cm2 edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.4×1.4 cm2 Medipix2 edgeless pixel detectors were also fabricated.This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100 ?m from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50-70 nA/cm2 and 580-660 pF/cm2 at, respectively, 40 V reverse bias for the p-on-n. For the n-on-n design these parameters were 116-118 nA/cm2 and 930-960 pF/cm2. The breakdown voltages were above 150 V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13-28 V.

  14. High transmittance silicon terahertz polarizer using wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Yu, Ting-Yang; Tsai, Hsin-Cheng; Wang, Shiang-Yu; Luo, Chih-Wei; Chen, Kuan-Neng

    2015-08-01

    Due to the difficulties faced in fabricating robust Terahertz (THz) optical components with low Fresnel reflection loss, the need to increase the efficiency of THz system with reduced cost is still considered as one of the most essential tasks. In this report, a new low cost THz polarizer with robust structure is proposed and demonstrated. This new THz wire grid polarizer was based on an anti-reflection (AR) layer fabricated with low temperature metal bonding and deep reactive ion etching (DRIE). After patterning Cu wire gratings and the corresponding In/Sn solder ring on the individual silicon wafers, the inner gratings were sealed by wafer-level Cu to In/Sn guard ring bonding, providing the protection against humidity oxidation and corrosion. With the low eutectic melting point of In/Sn solder, wafers could be bonded face to face below 150°C. Two anti-reflection layers on both outward surfaces were fabricated by DRIE. With the mixing of empty holes and silicon, the effective refractive index was designed to be the square root of the silicon refractive index. The central frequency of the anti-reflection layers was designed between 0.5THz to 2THz with an approximate bandwidth of 0.5THz. The samples were measured with a commercial free-standing wire grid polarizer by a THz time domain spectroscopy (THz-TDS) from 0.2THz to 2.2THz. The power transmittance is close to 100% at central frequency. Extinction ratio of the polarizer is between 20dB to 40dB depending on the frequency. The advantages of this new polarizer include high transmittance, robust structure and low cost with no precision optical alignment required.

  15. Advanced Ceramic Wafer Seals Demonstrated at 2000 deg. F

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Durable, high-temperature sliding seals are required in advanced hypersonic engines and around movable control surfaces on future vehicles. These seals must operate at temperatures of 2000 to 2500 F, limit hot gas flow, remain resilient for multiple cycles, and resist scrubbing damage against rough surfaces. Current seal designs do not meet these demanding requirements, so the NASA Glenn Research Center is developing advanced seals and preload devices to overcome these shortfalls. An advanced ceramic wafer seal design and two silicon nitride compression spring designs were evaluated in a series of compression, scrub, and flow tests.

  16. Propagation of Nd-laser pulses through crystalline silicon wafers

    SciTech Connect

    Kirichenko, N A; Kuzmin, P G; Shcherbina, M E

    2011-07-31

    Propagation of pulses from an Nd:YAG laser (wavelength, 1.064 {mu}m; pulse duration, 270 ns; pulse energy, 225 {mu}J) through crystalline silicon wafers is studied experimentally. Mathematical modelling of the process is performed: the heat conduction equation is solved numerically, the temperature dependences of the absorption and refraction of a substance, as well as generation of nonequilibrium carriers by radiation are taken into account. The constructed model satisfactorily explains the experimentally observed intensity oscillations of transmitted radiation. (interaction of laser radiation with matter)

  17. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  18. Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes

    NASA Astrophysics Data System (ADS)

    Peterson, Joel; Rusk, Gary; Veeraraghavan, Sathish; Huang, Kevin; Koffas, Telly; Kimani, Peter; Sinha, Jaydeep

    2015-03-01

    The semiconductor industry continues to push the limits of immersion lithography through multiple patterning techniques for printing features with critical dimension 20 nm and below. As a result overlay has become one of the critical lithography control parameters impacting device performance and has a stringent budget for yielding at smaller half pitch nodes. Overlay has several sources of errors related to scanner, lens, mask, and wafer. Lithographers have developed both linear and higher order field and wafer models to successfully compensate for the static fingerprints from different sources of error. After the static modeled portion of the fingerprint is removed, the remaining overlay error can be characterized as unstable modeled error or un-modeled error, commonly called uncorrectable residual error. This paper explores the fundamental relationship of overlay to wafer geometry through mechanisms of process-induced contributions to the wafer overlay, categorized as plastic and elastic wafer deformation. Correlation of overlay to local features such as slip lines is proven experimentally. The paper describes methodologies and geometry-induced overlay metrics for the application of wafer geometry to perform overlay feedback and feed forward applications. Feedback applications allow for process development and controlling semiconductor processes through in-line monitoring of wafers. Feed forward applications could include geometrybased corrections to the scanner for compensating non-static wafer geometry related overlay errors, and grouping wafers based on higher-order geometry.

  19. A practical approach to LWIR wafer-level optics for thermal imaging systems

    NASA Astrophysics Data System (ADS)

    Symmons, Alan; Pini, Ray

    2013-06-01

    The development and implementation of wafer level packaging for commercial microbolometers has opened the pathway towards full wafer-based thermal imaging systems. The next challenge in development is moving from discrete element LWIR imaging systems to a wafer based optical system, similar to lens assemblies found in cell phone cameras. This paper will compare a typical high volume thermal imaging design manufactured from discrete lens elements to a similar design optimized for manufacture through a wafer based approach. We will explore both performance and cost tradeoffs as well as review the manufacturability of all designs.

  20. Improved quality control of silicon wafers using novel off-line air pocket image analysis

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Sanna, M. Cristina

    2014-08-01

    Air pockets (APK) occur randomly in Czochralski (Cz) grown silicon (Si) crystals and may become included in wafers after slicing and polishing. Previously the only APK of interest were those that intersected the front surface of the wafer and therefore directly impacted device yield. However mobile and other electronics have placed new demands on wafers to be internally APK-free for reasons of thermal management and packaging yield. We present a novel, recently patented, APK image processing technique and demonstrate the use of that technique, off-line, to improve quality control during wafer manufacturing.

  1. FDTD simulation of an 1x2 beam splitter using photonic bandgap on SOI wafer

    NASA Astrophysics Data System (ADS)

    Tsao, Shyh-Lin; Yang, Lan-Chih; Huang, Hsin-Chun; Hu, Shu-Fen

    2003-12-01

    In recent years, SOI optical waveguide is an attractive component of optical waveguide elements. Because fabrication of complementary metal oxide semiconductor (CMOS) electronic devices on SOI wafers shows promising results in the future low-power, high speed electronic device, and SOI opto-electronic integrated devices becomes an important issue[1]. Owing to the presence of periodically positioned scatters, the PBG theory is based on the principle of localization. If periodicity is equal or near a wavelength, the frequency of lightwave within the bandgap is stuck inside the material and not allowed to propagation. Recently, PBG have been suggested for a variety of optoelectronic applications, such as ultra low threshold lasers, high transmission waveguides with a bending radius comparable to the light wavelength[2]. In this paper, we design and analyze the 3 db 1x2 PBG splitter on SOI wafer, we simulated the 1x2 PBG splitter by finite difference time domain ( FDTD ) technology. In this work, our designed SOI wafer waveguide includes a 0.4 ?m oxide layer and a 1.5 ?m crystal silicon surface layer. The buried oxide structure is a planar slab working as the lower cladding ( nsio2 = 1.5 ) layer, the surface silicon layer (nsi = 3.5 ) is the waveguide core and the top cladding is air ( nair = 1 ). The width of rib waveguide is 4?m. The device is less than 30?m2, the input lightwave is separated into two opposite directions. In the future, we expect such a novel device can be applied in many very large scale opto-electronic integrated circuits. Reference [1] A. Layadi, A. Vonsovical, R. Orobtchouk, D. Pascal, and A. Koster, 'Low loss optical waveguide on standard SOI/SIMOX substrate', Optical Communication, vol. 146, pp. 31-33, 1998. [2] Park Young-Jin, A. Herschlein and W. Wiesbeck, 'A photonic bandgap (PBG) structure for guiding and suppressing surface waves in millimeter-wave antennas', IEEE Transactions on Microwave Theory and Techniques, vol. 49, pp. 1854-1859, 2001.

  2. Creating a single twin boundary between two CdTe (111) wafers with controlled rotation angle by wafer bonding

    SciTech Connect

    Sun, Ce; Lu, Ning; Wang, Jinguo; Lee, Jihyung; Peng, Xin; Kim, Moon J.; Klie, Robert F.

    2013-12-16

    The single twin boundary with crystallographic orientation relationship (1{sup ¯}1{sup ¯}1{sup ¯})//(111) [01{sup ¯}1]//[011{sup ¯}] was created by wafer bonding. Electron diffraction patterns and high-resolution transmission electron microscopy images demonstrated the well control of the rotation angle between the bonded pair. At the twin boundary, one unit of wurtzite structure was found between two zinc-blende matrices. High-angle annular dark-field scanning transmission electron microscopy images showed Cd- and Te-terminated for the two bonded portions, respectively. The I-V curve across the twin boundary showed increasingly nonlinear behavior, indicating a potential barrier at the bonded twin boundary.

  3. Photonic crystal preparation by a wafer bonding approach

    NASA Astrophysics Data System (ADS)

    Yamamoto, Noritsugu; Ogawa, Shinpei; Imada, Masahiro; Noda, Susumu

    2001-10-01

    Various important scientific and engineering applications, such as control of spontaneous emission, zero-threshold lasing, sharp bending of light, and trapping of photons, are expected by using photonic bandgap (PBG) crystals with artificially introduced defect states and/ or light-emitters. Realizing the maximum potential of photonic crystals requires the following steps: (i) construct a three-dimensional (3D) crystal with a complete photonic bandgap in the optical wavelength region; (ii) introduce an arbitrary defect into the crystal at an arbitrary position; (iii) introduce an efficient light-emitter; and, (iv) use an electronically conductive crystal, as this is desirable for actual device application. Although various approaches to constructing 3D crystals have been proposed and investigated, none of these reports satisfies the above requirements simultaneously. To develop complete 3D crystals at infrared (5-10um) to near-infrared wavelengths (1-2um), we stacked III-V semiconductor gratings into a diamond structure by means of wafer bonding and a laser-beam-assisted very precise alignment technique. Since the crystal is constructed with III-V semiconductors, which are widely used for optoelectronic devices, requirement (iii) is satisfied. Moreover, as the wafer bonding enables us to construct an arbitrary structure and to form an electronically conductive interface, all the above requirements (i)-(iv) will be satisfied. In this paper, we review our approach for creating full 3D photonic bandgap crystals at near-infrared wavelengths.

  4. Progress on 300-mm wafer lithography equipment and processes

    NASA Astrophysics Data System (ADS)

    Mautz, Karl E.; Maltabes, John G.

    2001-09-01

    SEMICONDUCTOR300 was the first pilot-production facility for 300mm wafers in the world. The company, a joint venture between Motorola, Inc. and Infineon Technologies started in early 1998 to test and compare process, metrology and probe equipment, develop robust processes, and manufacture products using a 300mm wafer tool set. The lithography tools included I-line steppers, an I-line scanner, a DUV stepper, and DUV scanners. All of these exposure tools were running in-line with various photoresist coat and develop tracks. The lithography tools were used to build both 64M and 256M DRAM devices and aggressive test vehicles. The process capability of the initial 0.25 micrometers reference process was done and compared to the 200mm data set of the sister factory. Automation issues for lithography tools were addressed and the cost metrics were calculated. SC300 demonstrated that a manufacturable 300mm lithography tool set and process for various ground rule devices was possible with the required performance in image transfer, CD control, and overlay. Further testing on 0.18micrometers and 0.15micrometers ground rule features indicated a sufficient process window for potential manufacturing. Additionally, it was demonstrated that non-concentric subfield stepping was feasible.

  5. Patterning of photocleavable zwitterionic polymer brush fabricated on silicon wafer.

    PubMed

    Kamada, Tomohiro; Yamazawa, Yuka; Nakaji-Hirabayashi, Tadashi; Kitano, Hiromi; Usui, Yuki; Hiroi, Yoshiomi; Kishioka, Takahiro

    2014-11-01

    Brushes of a polymer, namely poly(carboxymethylbetaine) (PCMB), were fabricated on silicon wafers by reversible addition-fragmentation chain-transfer (RAFT) polymerization using a surface-confined RAFT agent having an aromatic group at its bottom. The polymer brush showed effective suppression of the non-specific adsorption of bovine serum albumin (BSA) and adhesion of fibroblasts (3T3 cells). In contrast, BSA and 3T3 cells significantly adsorbed on and adhered to positively or negatively charged polymer brushes fabricated by the same procedure. Upon UV irradiation at 193 nm, the thickness of the PCMB brush with an aromatic group at its bottom decreased significantly whereas PCMB prepared using a surface-confined RAFT agent without an aromatic group needed a much higher irradiation dose to afford a comparable decrease in thickness. These results indicate a preferential cleavage of the PCMB brush due to photodecomposition of the phenyl group at the bottom. BSA and 3T3 cells non-specifically adsorbed on and adhered to the UV irradiation-induced hollow spaces, respectively. Furthermore, a designed pattern with a resolution of 5 ?m was successfully made on the PCMB brush above the silicon wafer by simple UV irradiation. These results suggest that the surface-confined aromatic RAFT agent will be quite useful for simple photolithography in biomedical fields. PMID:25466462

  6. Formation of silver nanoparticles and nanocraters on silicon wafers.

    PubMed

    He, Junhui; Kunitake, Toyoki

    2006-08-29

    Silver nanocraters and monodisperse nanoparticles were formed on silicon wafers by spin-coating of an aqueous AgNO3/PVA solution and calcination of the resulting Ag+/PVA composite film. The monodisperse Ag nanoparicles were formed from small Ag+/PVA aggregates and were uniformly and stably distributed on the substrate surface. They were located as close as 2.8 nm apart (edge to edge) without coalescence. This nanoparticle stability was apparently derived from their interaction with the oxidized wafer surface. On the other hand, Ag metallic nanocraters with and without nanodots at their centers were produced from large Ag+/PVA aggregates. The explosive decomposition of AgNO3 and PVA by calcination could explain their formation. When Ag+ ions were reduced to Ag nanoparticles prior to calcination, larger Ag nanoparticles were produced probably due to aggregation of closely situated nanoparticles. Those nanoparticles that were located far enough stayed intact. Perspectives are discussed in terms of potential applications. PMID:16922578

  7. High-accuracy inspection of defects and profile of wafers by phase measuring deflectometry

    NASA Astrophysics Data System (ADS)

    Yue, Huimin; Wu, Yuxiang; Zhao, Biyu; Ou, Zhonghua; Liu, Yong

    2014-09-01

    The demands of the less-defective and high-flatness wafers are urgent in many wafer based technologies ranging from micro-electronics to the current photovoltaic industry. As the wafer becomes thinner and larger to cope with the advances in those industries, there is an increasing possibility of the emerging of crack and warp on the wafer surface. High-accuracy inspection of defects and profile are thus necessary to ensure the reliability of device. Phase measuring deflectometry(PMD) is a fast, cost-effective and high accuracy measurement technology which has been developed in recent years. As a slope measurement technology, PMD possesses a high sensitivity. Very small slope variation will lead to a large variation of the phase. PMD is very possible to have a good performance in the wafer inspection. In this paper, the requirements of the wafer inspection in the industries are discussed, and compatibility of PMD and those requirements is analyzed. In the experimental work, PMD gets the slope information of the wafer surface directly. The curvature or height information can be acquired simply by the derivation or integral of the slope. PMD is proved to make a superior result in high-precision defect detecting and shape measurement of wafer by the analysis of experiment results.

  8. Deep subsurface electronic defect image contrast and resolution amplification in Si wafers using infrared photocarrier radiometry

    E-print Network

    Mandelis, Andreas

    Deep subsurface electronic defect image contrast and resolution amplification in Si wafers using with the applications to deep subsurface electronic defect analysis in Si wafers. It is shown that the use of a dc light.1063/1.1785289] Bulk lifetime and surface recombination velocity are the most commonly used parameters for detection

  9. Wafer-Level Packaging Technology for RF Applications Based on a Rigid Low-Loss Spacer

    E-print Network

    Technische Universiteit Delft

    Wafer-Level Packaging Technology for RF Applications Based on a Rigid Low-Loss Spacer Substrate Alexander Polyakov #12;#12;Wafer-Level Packaging Technology for RF Applications Based on a Rigid Low Dr. N.J.A. van Veen, Koninklijke Philips Electronics N.V. Prof. Dr.-Ing. H. Sandmaier, Universität

  10. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbrecher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-01-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  11. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbracher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-07-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  12. Effects of wafer bow and warpage on the integrity of thin gate oxides

    NASA Astrophysics Data System (ADS)

    Thakur, R. P. S.; Chhabra, N.; Ditali, A.

    1994-06-01

    We have studied the effects of initial wafer bow and warpage on the integrity of thinner gate oxides grown by both furnace and rapid thermal processing (RTP) methods. There is evidence of a correlation between wafer warpage and bow to the charge-to-breakdown characteristics of the gate oxide. An almost linear increase in defect density was observed when plotted as a function of increasing wafer warpage. The lifetime (t50%) of the samples with initial warpage of 10 ?m or less is reported higher than those with initial warpage of more than 60 ?m for both furnace and RTP-grown oxides. The value of bow for the warped samples was taken for cases with the highest positive and negative values so both kinds of shape trends could be investigated. With initial wafer warpage ranging from 4 to 70 ?m, we present the results of wafer dimensional analysis and correlate these to defect density and lifetime studies for thin gate oxides.

  13. Multiple-surface interferometry of highly reflective wafer by wavelength tuning.

    PubMed

    Kim, Yangjin; Hibino, Kenichi; Hanayama, Ryohei; Sugita, Naohiko; Mitsuishi, Mamoru

    2014-09-01

    The surface shape and optical thickness variation of a lithium niobate (LNB) wafer were measured simultaneously using a wavelength-tuning interferometer with a new phase-shifting algorithm. It is necessary to suppress the harmonic signals for testing a highly reflective sample such as a crystal wafer. The LNB wafer subjected to polishing, which is in optical contact with a fused-silica (FS) supporting plate, generates six different overlapping interference fringes. The reflectivity of the wafer is typically 15%, yielding significant harmonic signals. The new algorithm can flexibly select the phase-shift interval and effectively suppress the harmonic signals and crosstalk. Experimental results indicated that the optical thickness variation of the LNB wafer was measured with an accuracy of 2 nm. PMID:25321495

  14. Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

    SciTech Connect

    Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

    2006-03-13

    An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection.

  15. High performance LWIR microbolometer with Si/SiGe quantum well thermistor and wafer level packaging

    NASA Astrophysics Data System (ADS)

    Roer, Audun; Lapadatu, Adriana; Bring, Martin; Wolla, Erik; Hohler, Erling; Kittilsland, Gjermund

    2011-11-01

    An uncooled microbolometer with peak responsivity in the long wave infrared region of the electromagnetic radiation is developed at Sensonor Technologies. It is a 384 x 288 focal plane array with a pixel pitch of 25?m, based on monocrystalline Si/SiGe quantum wells as IR sensitive material. The high sensitivity (TCR) and low 1/f noise are the main performance characteristics of the product. The frame rate is maximum 60Hz and the output interface is digital (LVDS). The quantum well thermistor material is transferred to the read-out integrated circuit (ROIC) by direct wafer bonding. The ROIC wafer containing the released pixels is bonded in vacuum with a silicon cap wafer, providing hermetic encapsulation at low cost. The resulting wafer stack is mounted in a standard ceramic package. In this paper the architecture of the pixels and the ROIC, the wafer packaging and the electro-optical measurement results are presented.

  16. Effects of wafer impedance on the monitoring and control of ion energy in plasma reactors

    SciTech Connect

    Sobolewski, Mark A.

    2006-09-15

    Ion kinetic energy in plasma reactors is controlled by applying radio-frequency (rf) substrate bias, but the efficiency and reproducibility of such control will be affected if the wafer being processed has a significant electrical impedance. Here, the effects of wafer impedance were studied by modeling and electrical measurements. Models of wafer impedance were proposed and tested by comparing model predictions to measured electrical wave forms. The tests were performed in an inductively coupled plasma reactor in 50% Ar, 50% CF{sub 4} gas at a pressure of 1.33 Pa (10 mTorr), rf bias frequencies of 0.1-10 MHz, rf bias amplitudes of 20-300 V, and inductive source powers of 100-500 W. At high bias frequencies, the dominant contribution to the wafer impedance was the capacitance of the gap between the wafer and its chuck. At low bias frequencies, however, a resistance associated with the contact between the wafer and the chuck became significant. Electrical wave forms and ion energy distributions were most sensitive to wafer impedance at low bias frequencies and low bias amplitudes. At low bias frequencies, model predictions indicate that the wafer impedance produces an undesirable variation in surface potential, sheath voltage, and ion energy across the wafer surface. Because it neglects wafer impedance effects, a technique that analyzes electrical wave forms to determine ion currents, sheath voltages, and ion energy distributions was found to suffer significant errors at low bias frequencies and amplitudes. Nevertheless, the technique provided accurate results at moderate to high bias frequency and amplitude.

  17. Effects of Lightpipe Proximity on Si Wafer Temperature in Rapid Thermal Processing Tools

    NASA Astrophysics Data System (ADS)

    Kreider, K. G.; Chen, D. H.; DeWitt, D. P.; Kimes, W. A.; Tsai, B. K.

    2003-09-01

    Lightpipe radiation thermometers (LPRTs) are used as temperature monitoring sensors in most rapid thermal processing (RTP) tools for semiconductor fabrication. These tools are used for dopant anneal, gate oxide formation, and other high temperature processing. In order to assure uniform wafer temperatures during processing these RTP tools generally have highly reflecting chamber walls to promote a uniform heat flux on the wafer. Therefore, only minimal disturbances in the chamber reflectivity are permitted for the sensors, and the small 2 mm diameter sapphire lightpipe is generally the temperature sensor of choice. This study was undertaken to measure and model the effect of LPRT proximity on the wafer temperature. Our experiments were performed in the NIST RTP test bed using a NIST thin-film thermocouple (TFTC) calibration wafer. We measured the spectral radiance temperature with the center lightpipe and compared these with the TFTC junctions and with the three LPRTs at the mid-radius of the wafer. We measured LPRT outputs from a position flush with the reflecting plate to within 2 mm of the stationary wafer under steady-state conditions with wafer-to-cold plate separation distances of 6 mm, 10 mm and 12.5 mm. Depressions in the wafer temperature up to 25 °C were observed. A finite-element radiation model of the wafer-chamber-lightpipe was developed to predict the temperature depression as a function of proximity distance and separation distance. The experimental results were compared with those from a model that accounts for lightpipe geometry and radiative properties, wafer emissivity and chamber cold plate reflectivity.

  18. Visible luminescence from silicon wafers subjected to stain etches

    NASA Technical Reports Server (NTRS)

    Fathauer, R. W.; George, T.; Ksendzov, A.; Vasquez, R. P.

    1992-01-01

    Etching of Si in a variety of solutions is known to cause staining. These stain layers consist of porous material similar to that produced by anodic etching of Si in HF solutions. In this work, photoluminescence peaked in the red from stain-etched Si wafers of different dopant types, concentrations, and orientations produced in solutions of HF:HNO3:H2O was observed. Luminescence is also observed in stain films produced in solutions of NaNO2 in HF, but not in stain films produced in solutions of CrO3 in HF. The luminescence spectra are similar to those reported recently for porous Si films produced by anodic etching in HF solutions. However, stain films are much easier to produce, requiring no special equipment.

  19. A Wafer Transfer Technology for MEMS Adaptive Optics

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean V.

    2001-01-01

    Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

  20. Effect of lubricant environment on saw damage in silicon wafers

    NASA Technical Reports Server (NTRS)

    Kuan, T. S.; Shih, K. K.; Vanvechten, J. A.; Westdorp, W. A.

    1982-01-01

    The chemomechanical effect of lubricant environments on the inner diameter (ID) sawing induced surface damage in Si wafers was tested for four different lubricants: water, dielectric oil, and two commercial cutting solutions. The effects of applying different potential on Si crystals during the sawing were also tested. It is indicated that the number and depth of surface damage are sensitive to the chemical nature of the saw lubricant. It is determined that the lubricants that are good catalysts for breaking Si bonds can dampen the out of plane blade vibration more effectively and produce less surface damage. Correlations between the applied potential and the depth of damage in the dielectric oil and one of the commercial cutting solutions and possible mechanisms involved are discussed.

  1. Chemical strategies for die/wafer submicron alignment and bonding.

    SciTech Connect

    Martin, James Ellis; Baca, Alicia I.; Chu, Dahwey; Rohwer, Lauren Elizabeth Shea

    2010-09-01

    This late-start LDRD explores chemical strategies that will enable sub-micron alignment accuracy of dies and wafers by exploiting the interfacial energies of chemical ligands. We have micropatterned commensurate features, such as 2-d arrays of micron-sized gold lines on the die to be bonded. Each gold line is functionalized with alkanethiol ligands before the die are brought into contact. The ligand interfacial energy is minimized when the lines on the die are brought into registration, due to favorable interactions between the complementary ligand tails. After registration is achieved, standard bonding techniques are used to create precision permanent bonds. We have computed the alignment forces and torque between two surfaces patterned with arrays of lines or square pads to illustrate how best to maximize the tendency to align. We also discuss complex, aperiodic patterns such as rectilinear pad assemblies, concentric circles, and spirals that point the way towards extremely precise alignment.

  2. Nanotribology of nanooxide materials in ionic liquids on silicon wafers

    NASA Astrophysics Data System (ADS)

    Hamidunsani, Ahmad Termizi; Radiman, Shahidan; Hassan, Masjuki Haji; Rahman, Irman Abdul

    2015-09-01

    Nanotribological properties have a significant impact on daily life. Ionic liquids (ILs) are becoming new favourable lubricants currently in researches. Addition of nanooxide materials in lubricants provide improvements to new technology. In this study, we determine nanotribological properties of BMIM+BF4- IL addition of different amount of ZnO nanomaterial on single crystals silicon wafer (Si110). The viscosity changes of IL samples against temperature increase were determined by rheological method. Nanotribological properties were determined by changes in friction coefficient and wear rate on silicon substrate surfaces using a reciprocating friction and wear monitor in 1 hour duration time. Aluminium cylinders acted as pins used to rub Si (110) substrate sample surfaces. Thus, on range between 0 mg to 3.5 mg of ZnO nanooxide material dispersed in 10ml BMIM+BF4- showed a good friction coefficient, wear and surface roughness reduction.

  3. Precise Fabrication of Silicon Wafers Using Gas Cluster Ion Beams

    SciTech Connect

    Isogai, Hiromichi; Toyoda, Eiji; Izunome, Koji; Kashima, Kazuhiko; Mashita, Takafumi; Toyoda, Noriaki; Yamada, Isao

    2009-03-10

    Precise surface processing of a silicon wafer was studied by using a gas cluster ion beam (GCIB). The damage caused to the silicon surface was strongly dependent on irradiation parameters. The extent of damage varied with the species of source gas and the acceleration voltage (Va) of cluster ions. It also varied with the cluster size and residual gas pressure. The influence of electron acceleration voltage (Ve) used for ionization of a neutral cluster was also investigated. The irradiation damage, such as an amorphous silicon (a-Si) layer, a mixed layer of a-Si and c-Si (transition layer), and surface roughness, was increased with Ve. It is suggested that the increase in the amount of energy per atom was induced by high Ve, because of variation of the cluster size and/or cluster charge. An undamaged smooth surface can be produced by Ar-GCIB irradiation at low Ve and Va.

  4. Magnetometory of AlGaN/GaN heterostructure wafers

    NASA Astrophysics Data System (ADS)

    Tsubaki, K.; Maeda, N.; Saitoh, T.; Kobayashi, N.

    2005-06-01

    AlGaN/GaN heterostructure wafers are becoming a key technology for next generation cellar-phone telecommunication system because of their potential for high-performance microwave applications. Therefore, the electronic properties of a 2DEG in AlGaN/GaN heterostructures have recently been discussed. In this paper, we performed the extraordinary Hall effect measurement and the SQUID magnetometory of AlGaN/GaN heterostructure wafer at low temperature. The AlGaN/GaN heterostructures were grown by low-pressure metal-organic chemical vapour phase epitaxy on (0001) SiC substrate using AlN buffers. The electron mobility and electron concentration at 4.2 K are 9,540cm2/V s and 6.6 × 1012cm-2, respectively. In the extraordinary Hall effect measurement of AlGaN/GaN heterostructures, the hysteresis of Hall resistance appeared below 4.5 K and disappeared above 4.5 K. On the other hand, the hysteresis of magnetometric data obtained by SQUID magnetometory appears near zero magnetic field when the temperature is lower than 4.5 K. At the temperature larger than 4.5 K, the hysteresis of magnetometric data disappears. And the slopes of magnetometric data with respect to magnetic field become lower as obeying Currie-Weiss law and the Curie temperature TC is 4.5 K. Agreement of TC measured by the extraordinary Hall effect and the SQUID magnetometory implies the ferromagnetism at the AlGaN/GaN heterojunction. However, the conformation of the ferromagnetism of AlGaN/GaN heterostructure is still difficult and the detailed physical mechanism is still unclear.

  5. Relaxed SiGe-on-insulator fabricated via wafer bonding and etch back Gianni Taraschi,a)

    E-print Network

    Relaxed SiGe-on-insulator fabricated via wafer bonding and etch back Gianni Taraschi,a) Thomas A was performed to deposit a strained Si etch stop layer followed by a Si0.75Ge0.25 layer. The wafers were bonded to oxidized Si handle wafers, and the wafer pairs were annealed. The backsides of the SiGe virtual substrates

  6. Enhanced Wafer Matching Heuristics for 3-D ICs Vasilis F. Pavlidis, Hu Xu, and Giovanni De Micheli

    E-print Network

    De Micheli, Giovanni

    Enhanced Wafer Matching Heuristics for 3-D ICs Vasilis F. Pavlidis, Hu Xu, and Giovanni De Micheli.demicheli}@epfl.ch Pre-bond test has been identified as a vital step for the wafer level integration of 3-D ICs [1], [2 the profit obtained by wafer- to-wafer (W2W) matching, where the speed of the resulting 3-D cir- cuits

  7. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates.

    PubMed

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-01-01

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the "melt-back" effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200?°C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20??m was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude. PMID:26487465

  8. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates

    PubMed Central

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-01-01

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the “melt-back” effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200?°C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20??m was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude. PMID:26487465

  9. Generation of SWNTs on Si Wafer by Alcohol Catalytic CVD Shigeo Maruyama, Shohei Chiashi and Yuhei Miyauchi

    E-print Network

    Maruyama, Shigeo

    Generation of SWNTs on Si Wafer by Alcohol Catalytic CVD Shigeo Maruyama, Shohei Chiashi and Yuhei possible. We tried to generate SWNTs on Si wafer by ACCVD technique. Zeolite particles supporting Fe/Co catalysts were dispersed in ethanol, and this dispersion liquid (about 1 ) was dropped onto a Si wafer (10

  10. 2-dimensional ion velocity distributions measured by laser-induced fluorescence above a radio-frequency biased silicon wafer

    E-print Network

    Carter, Troy

    -frequency biased silicon wafer Nathaniel B. Moore,1,a) Walter Gekelman,1,b) Patrick Pribyl,1,c) Yiting Zhang,2,d cm diameter, 2.2 MHz-biased silicon wafer in a commercial inductively coupled plasma processing along the surface of the wafer by utilizing a planar laser sheet from a pulsed, tunable dye laser

  11. SiGe-free strained Si on insulator by wafer bonding and layer transfer T. A. Langdo,a)

    E-print Network

    SiGe-free strained Si on insulator by wafer bonding and layer transfer T. A. Langdo,a) M. T. Currie; accepted 4 April 2003 SiGe-free strained Si on insulator substrates were fabricated by wafer bonding substrates have been fabricated by separation by implantation of oxygen,5 wafer bonding, and layer transfer,6

  12. Contact Model for a Pad Asperity and a Wafer Surface in the Presence of Abrasive Particles for Chemical Mechanical Polishing

    E-print Network

    Müftü, Sinan

    Contact Model for a Pad Asperity and a Wafer Surface in the Presence of Abrasive Particles April 9-13, 2007. In CMP the interface of the polishing-pad and the wafer is filled with liquid slurry the pad asperites and the wafer. Therefore, it is necessary to understand the relative contributions

  13. Preparation and characterization of Al/Al2O3/Cu SIN tunnel junctions microfabricated with a full wafer process

    E-print Network

    Neuhauser, Barbara

    wafer process J. P. Castlea,b, M. F. Cunninghama,b, B. Neuhausera,b, S. Golwalab, F. P. Lipschultza at Storrs We have developed a "full wafer" process for producing Al/Al2O3/Cu superconductor and stable, and junctions produced on the same wafer had very similar tunneling characteristics. However

  14. 2006 IEEE SENSORS JOURNAL, VOL. 14, NO. 6, JUNE 2014 Microwave Characterization of a Wafer-Level

    E-print Network

    Akin, Tayfun

    2006 IEEE SENSORS JOURNAL, VOL. 14, NO. 6, JUNE 2014 Microwave Characterization of a Wafer the microwave characterization of a wafer level packaging approach for RF MEMS devices, using glass frit characterization of the package structure. Prior to bonding of the cap on the transmission lines, cap wafers

  15. 432 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 17, NO. 3, AUGUST 2004 Image-Based Wafer Navigation

    E-print Network

    Rivlin, Ehud

    432 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 17, NO. 3, AUGUST 2004 Image-Based Wafer- portant information. We present a new method for navigation on wafers that is based on localization of microscopic eye-point im- ages using a previously acquired wafer map. It is fast enough for in-line microscopy

  16. An Algorithm to Convert Wafer to Calendar-Based Preventive Maintenance Schedules for Semiconductor Manufacturing Systems1

    E-print Network

    Fernandez, Emmanuel

    An Algorithm to Convert Wafer to Calendar-Based Preventive Maintenance Schedules for Semiconductor schedules based on the count of wafers processed into equivalent calendar PM schedules. These equivalent a discrete mathematical model and an algorithm to convert from wafer-count targets into equivalent calendar

  17. Deterministic assembly of releasable single crystal silicon-metal oxide field-effect devices formed from bulk wafers

    E-print Network

    Rogers, John A.

    formed from bulk wafers Tae-il Kim, Yei Hwan Jung, Hyun-Joong Chung, Ki Jun Yu, Numair Ahmed et al silicon-metal oxide field-effect devices formed from bulk wafers Tae-il Kim,1,2,a) Yei Hwan Jung,1,a released from the surfaces of bulk wafers with (111) orientation provides a route to high quality

  18. Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs

    E-print Network

    Chakrabarty, Krishnendu

    Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs Sudarshan Bahukudumbi.kacprowicz@intel.com Abstract--Wafer-level test during burn-in (WLTBI) has re- cently emerged as a promising technique to reduce result in high cost [1], [5]. Wafer level burn-in (WLBI) has recently emerged as an enabling technology

  19. Wafer-level Spatial and Flush Delay Analysis for IDDQ Estimation Sagar S. Sabade Duncan M. Walker

    E-print Network

    Walker, Duncan M. "Hank"

    Wafer-level Spatial and Flush Delay Analysis for IDDQ Estimation Sagar S. Sabade Duncan M. Walker between IDDQ and a second parameter like speed [16], temperature [17], and die position on a wafer [18 median IDDQ for all chips that passed all tests or failed only IDDQ test at the wafer level and had

  20. Evaluation of the Technical Feasibility and Effective Cost of Various Wafer Thicknesses for the Manufacture of Solar Cells

    NASA Technical Reports Server (NTRS)

    1979-01-01

    Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.

  1. Mapping of Defects in Large-Area Silicon Carbide Wafers via Photoluminescence and its Correlation with Synchrotron White Beam X-Ray Topography

    SciTech Connect

    Chen, Yi; Balaji, R.; Dudley, Michael; Murthy, Madhu; Maximenko, Serguei I.; Freitas, Jamie A.

    2008-12-12

    Comparative studies of defect microstructure in 4H-SiC wafers have been carried out using photoluminescence (PL) imaging and grazing-incidence Synchrotron White Beam X-ray Topography. Images of low angle grain boundaries on the PL images correlate well with SWBXT observations, and similar correlation can be established for some micropipe images although the latter is complicated by the overall level of distortion and misorientation associated with the low angle grain boundaries and the fact that many of the micropipes are located in or close to the boundaries. This validation indicates that PL imaging may provide a rapid way of imaging such defect structures in large-scale SiC wafers.

  2. Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers Used for PV Cells: Preprint

    SciTech Connect

    Guthrey, H.; Gorman, B.; Al-Jassim, M.

    2011-07-01

    As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay (uPCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

  3. Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010

    SciTech Connect

    Lorenz, A.

    2011-06-01

    1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

  4. A fast in situ approach to estimating wafer warpage profile during thermal processing in microlithography

    NASA Astrophysics Data System (ADS)

    Hu, Ni; Tay, Arthur; Tsai, Kuen-Yu

    2006-08-01

    Wafer warpage can affect device performance, reliability and linewidth control in various processing steps in microelectronics manufacturing. Early detection will minimize cost and processing time. We have previously demonstrated an on-line approach for detecting wafer warpage and the profile of the warped wafer. The proposed approach demonstrates that the profile of the wafer can be computed during thermal processing steps in the lithography sequence. However, the approach is computationally intensive and information is made available at the end of the thermal processing step. Any attempts at real-time correction of the wafer temperature are thus not possible. In this paper, we proposed an in situ approach to detect wafer warpage and its profile midway through the thermal process. Based on first principles thermal modelling, we are able to detect and estimate the profile of a warped wafer from available temperature measurements. The proposed approach can be implemented on conventional thermal processing systems. Experimental results demonstrate the feasibility and repeatability of the approach. A 75% improvement in computational time is achieved with the proposed approach.

  5. Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

    NASA Technical Reports Server (NTRS)

    Okojie, Robert S. (Inventor)

    2002-01-01

    A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

  6. Validation of thermodesorption method for analysis of semi-volatile organic compounds adsorbed on wafer surface.

    PubMed

    Hayeck, Nathalie; Gligorovski, Sasho; Poulet, Irène; Wortham, Henri

    2014-05-01

    To prevent the degradation of the device characteristics it is important to detect the organic contaminants adsorbed on the wafers. In this respect, a reliable qualitative and quantitative analytical method for analysis of semi-volatile organic compounds which can adsorb on wafer surfaces is of paramount importance. Here, we present a new analytical method based on Wafer Outgassing System (WOS) coupled to Automated Thermal Desorber-Gas chromatography-Mass spectrometry (ATD-GC-MS) to identify and quantify volatile and semi-volatile organic compounds from 6", 8" and 12" wafers. WOS technique allows the desorption of organic compounds from one side of the wafers. This method was tested on three important airborne contaminants in cleanroom i.e. tris-(2-chloroethyl) phosphate (TCEP), tris-(2-chloroisopropyl) phosphate (TCPP) and diethyl phthalate (DEP). In addition, we validated this method for the analysis and quantification of DEP, TCEP and TCPP and we estimated the backside organic contamination which may contribute to the front side of the contaminated wafers. We are demonstrating that WOS/ATD-GC-MS is a suitable and highly efficient technique for desorption and quantitative analysis of organophosphorous compounds and phthalate ester which could be found on the wafer surface. PMID:24720963

  7. Therml & Gravitational Stress in Si Wafers; Lim. on Process Htg & Cool. Rates

    Energy Science and Technology Software Center (ESTSC)

    1997-01-14

    The MacWafer code determines maximum allowable processing temperatures and maximum heating and cooling rates for thermal processing of silicon semiconductor wafers in single and multiple wafer furnaces. The program runs interactively on Macintosh, PC, and workstation computers. Execution time is typically 20 seconds on a Macintosh 68040 processor operating at 33 MHz. Gravitational stresses and displacements are first calculated based on the user''s input of a support system consisting of a ring beneath the wafermore »and/or arbitrarily placed point supports. The maximum operating temperature is then deduced by comparing the calculated gravitational stresses with the temperature-dependent wafer strength. At lower temperatures, the difference between wafer strength and gravitational stress is used to determine the allowable thermal stress, and hence the allowable radial temperature difference across the wafer. Finally, an analytical model of radial heat transfer in a batch furnace yields the maximum heating or cooling rate as a function of the allowable temperature difference based on the user''s inputs of wafer spacing and furnace power. Outputs to the screen include plots of stress components and vertical displacement, as well as tables of maximum stresses and maximum heating and cooling rates as a function of temperature. All inputs and outputs may be directed to user-named files for further processing or graphical display.« less

  8. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss

    PubMed Central

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-01-01

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180??m) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping. PMID:24820403

  9. CDU improvement with wafer warpage control oven for high-volume manufacturing

    NASA Astrophysics Data System (ADS)

    Tomita, T.; Weichert, H.; Hornig, S.; Trepte, S.; Shite, H.; Uemura, R.; Kitano, J.

    2009-03-01

    Immersion lithography has been developed for 45nm technology node generation during the last several years. Currently, IC manufacturers are moving to high volume production using immersion lithography. Due to the demand of IC manufactures, as the critical dimension (CD) target size is shrinking, there are more stringent requirements for CD control. Post Exposure Bake (PEB) process, which is the polymer de-protection process after exposure, is one of the important processes to control the CD in the 193nm immersion lithography cluster. Because of the importance of the PEB process for CD uniformity, accurate temperature control is a high priority. Tokyo Electron LTD (TEL) has been studying the temperature control of PEB plates. From our investigation, total thermal history during the PEB process is a key point for controlling intra wafer and inter wafer CD [1]. Further, production wafers are usually warped, which leads to a nonuniform thermal energy distribution during the PEB process. So, it is necessary to correct wafer warpage during the baking process in order to achieve accurate CD control on production wafers. TEL has developed a new PEB plate for 45nm technology node mass production, which is able to correct wafer warpage. The new PEB plate succeeded in controlling the wafer temperature on production wafers using its warpage control function. In this work, we evaluated CD process capability using the wafer warpage control PEB plate, which is mounted on a CLEAN TRACKTM LITHIUS ProTM-i (TEL) linked with the latest immersion exposure tool. The evaluation was performed together with an IC manufacturer on their 45nm production substrates in order to determine the true performance in production.

  10. Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

    NASA Astrophysics Data System (ADS)

    Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

    2015-02-01

    The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

  11. W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

    NASA Technical Reports Server (NTRS)

    Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

    1997-01-01

    Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

  12. Low temperature solder process to join a copper tube to a silicon wafer

    NASA Astrophysics Data System (ADS)

    Versteeg, Christo; Scarpim de Souza, Marcio

    2014-06-01

    With the application for wafer level packages, which could be Complementary Metal-Oxide-Semiconductor (CMOS) based, and which requires a reduced atmosphere, a copper tube connection to a vacuum pump and the package is proposed. The method evaluated uses laser assisted brazing of a solder, to join the copper tube to a silicon wafer. The method was applied to a silicon wafer coated with a metallic interface to bond to the solder. The hermeticity of the joint was tested with a helium leak rate tester and the bonding energy thermal extent was verified with a thin layer of indium that melted wherever the substrate temperature rose above its melting temperature.

  13. Wafer chamber having a gas curtain for extreme-UV lithography

    DOEpatents

    Kanouff, Michael P. (Livermore, CA); Ray-Chaudhuri, Avijit K. (Livermore, CA)

    2001-01-01

    An EUVL device includes a wafer chamber that is separated from the upstream optics by a barrier having an aperture that is permeable to the inert gas. Maintaining an inert gas curtain in the proximity of a wafer positioned in a chamber of an extreme ultraviolet lithography device can effectively prevent contaminants from reaching the optics in an extreme ultraviolet photolithography device even though solid window filters are not employed between the source of reflected radiation, e.g., the camera, and the wafer. The inert gas removes the contaminants by entrainment.

  14. Correlation of 150-mm silicon wafer site flatness with stepper performance for deep submicron applications

    NASA Astrophysics Data System (ADS)

    Huff, Howard R.; Vigil, Joseph C.; Kuyel, Birol; Chan, David Y.; Nguyen, Long P.

    1992-06-01

    An experimental study was conducted to correlate wafer site flatness SFQD with stepper performance for half-micron lines and spaces. CD measurements were taken on wafers patterned on both GCA pre-production XLS i-line and SVGL Micrascan-90 DUV steppers as well as focus measurements on the Micrascan-90. Wafer site flatness SFQD less than 0.3 micrometers was observed to be a sufficiently small variable in CD non-uniformities for these initial half-micron stepper applications.

  15. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sang Min; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Vukkadala, Pradeep; Awasthi, Amartya; Kim, J. H.; Veeraraghavan, Sathish; Choi, DongSub; Huang, Kevin; Dighe, Prasanna; Lee, Cheouljung; Byeon, Jungho; Dey, Soham; Sinha, Jaydeep

    2015-03-01

    Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes - which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.

  16. Adhesive disbond detection using piezoelectric wafer active sensors

    NASA Astrophysics Data System (ADS)

    Roth, William; Giurgiutiu, Victor

    2015-04-01

    The aerospace industry continues to increase the use of adhesives for structural bonding due to the increased joint efficiency (reduced weight), even distribution of the load path and decreases in stress concentrations. However, the limited techniques for verifying the strength of adhesive bonds has reduced its use on primary structures and requires an intensive inspection schedule. This paper discusses a potential structural health monitoring (SHM) technique for the detection of disbonds through the in situ inspection of adhesive joints. This is achieved through the use of piezoelectric wafer active sensors (PWAS), thin unobtrusive sensors which are permanently bonded to the aircraft structure. The detection method discussed in this study is electromechanical impedance spectroscopy (EMIS), a local vibration method. This method detects disbonds from the change in the mechanical impedance of the structure surrounding the disbond. This paper will discuss how predictive modeling can provide valuable insight into the inspection method, and provide better results than empirical methods alone. The inspection scheme was evaluated using the finite element method, and the results were verified experimentally using a large aluminum test article, and included both pristine and disbond coupons.

  17. Heavily doped silicon crystals: neckless growth and robust wafers

    NASA Astrophysics Data System (ADS)

    Hoshikawa, Keigo; Huang, Xinming; Taishi, Toshinori

    2005-02-01

    Some interesting phenomena relating to dislocation behavior occurring near the seed/grown-crystal interface during the growth of heavily B-doped Si crystals have been observed, which have not been reported in the literature. The generation and/or propagation of dislocations have been shown to be suppressed remarkably due to an impurity hardening effect in heavily B-doped or heavily B- and Ge-codoped Si crystals. As a result, in the heavily B-doped or B- and Ge-codoped Si crystals, dislocations did not multiply in spite of the fact that some dislocations could not always be fully eliminated even after use of a severe thin neck process. Consequently, neckless growth of a dislocation-free Si crystal has been successfully achieved, based on this discovery. Furthermore, a new kind of so-called "robust Si wafer" has been proposed, which exhibits a high resistance to thermal stress and is suitable for any kind of epitaxial growth without the generation of misfit dislocations.

  18. Three-step approach for wafer sawing lane inspection

    NASA Astrophysics Data System (ADS)

    Wang, Jing-Wein; Wang, Chia-Nan; Chen, Wen-Yuan

    2009-11-01

    Wafer sawing performance must be closely monitored to ensure a satisfactory integrated circuits manufacturing yield. The inspection must allow the GO/NG decision to be fast and reliable, while also assuring that the training of the inspector is simple and not time consuming. The traditional neural-network approach to inspect images, while simple to implement, presents some disadvantages, including training efficiency and model effectiveness. Based on contour detection of the sawing lane, this work proposes a novel method combined with cross-center localization of sawing lanes, detection of sawing track, and four signatures to detect the abnormality of sawing effectively and timely. Our method does not need pretraining but runs faster and provides a better method with more effectiveness, higher flexibility, and immediate feedback to the sawing operation. An experiment using real data collected from an international semiconductor package factory is conducted to validate the performance of the proposed framework. The accurate acceptance rate and the accurate rejection rate are both 100%, while the false acceptance rate and false rejection rate are both zero as well. The results demonstrate that the proposed method is sound and useful for sawing inspection in industries.

  19. Development of a novel wafer-probe for in situ measurements of thin film properties

    NASA Astrophysics Data System (ADS)

    el Otell, Z.; Marinov, D.; Šamara, V.; Bowden, M. D.; de Marneffe, J.-F.; Verdonck, P.; Braithwaite, N. St. J.

    2015-06-01

    We report a new development of a diagnostic technique, referred to as the wafer probe, which enables us to qualitatively monitor the plasma-induced changes in thin film dielectrics, in-situ and in real time. The wafer probe is an adaptation of the well-established ion flux probe technique, also known as RF biased or pulse biased planar Langmuir probe. This technique utilises the top surface of a tile cut from a multi-layer wafer as the probing area. This technique was successfully used to characterise different plasma conditions and monitor the plasma-induced changes in the thin layers of the tile, e.g. a porous organosilicate-glass low-? dielectrics. The wafer probe was used to monitor the different effects of an argon and a hydrogen plasma on low-? dielectrics, as well as to monitor the etch rate and endpoint of an Ar/SF6 plasma.

  20. On-wafer vector network analyzer measurements in the 220-325 Ghz frequency band

    NASA Technical Reports Server (NTRS)

    Fung, King Man Andy; Dawson, D.; Samoska, L.; Lee, K.; Oleson, C.; Boll, G.

    2006-01-01

    We report on a full two-port on-wafer vector network analyzer test set for the 220-325 GHz (WR3) frequency band. The test set utilizes Oleson Microwave Labs frequency extenders with the Agilent 8510C network analyzer. Two port on-wafer measurements are made with GGB Industries coplanar waveguide (CPW) probes. With this test set we have measured the WR3 band S-parameters of amplifiers on-wafer, and the characteristics of the CPW wafer probes. Results for a three stage InP HEMT amplifier show 10 dB gain at 235 GHz [1], and that of a single stage amplifier, 2.9 dB gain at 231 GHz. The approximate upper limit of loss per CPW probe range from 3.0 to 4.8 dB across the WR3 frequency band.

  1. A study of defects on EUV mask using blank inspection, patterned mask inspection, and wafer inspection

    SciTech Connect

    Huh, S.; Ren, L.; Chan, D.; Wurm, S.; Goldberg, K. A.; Mochi, I.; Nakajima, T.; Kishimoto, M.; Ahn, B.; Kang, I.; Park, J.-O.; Cho, K.; Han, S.-I.; Laursen, T.

    2010-03-12

    The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing. yet link data is available for understanding native defects on real masks. In this paper, a full-field EUV mask is fabricated to investigate the printability of various defects on the mask. The printability of defects and identification of their source from mask fabrication to handling were studied using wafer inspection. The printable blank defect density excluding particles and patterns is 0.63 cm{sup 2}. Mask inspection is shown to have better sensitivity than wafer inspection. The sensitivity of wafer inspection must be improved using through-focus analysis and a different wafer stack.

  2. Fab cycle time improvement through inventory control : a wafer starts approach

    E-print Network

    Ward, Matthew John

    2007-01-01

    Intel's Colorado Springs wafer fabrication facility, known internally as F23, has undertaken several initiatives to reduce cycle time including High Precision Maintenance (HPM), content reduction through the application ...

  3. Low Loss, Finite Width Ground Plane, Thin Film Microstrip Lines on Si Wafers

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Margomenos, Alexandros; Katehi, Linda P. B.

    1999-01-01

    Si RFICs on standard, 2 Omega-cm. Si wafers require novel transmission lines to reduce the loss caused by the resistive substrate. One such transmission line is commonly called Thin Film Microstrip (TFMS), which is created by depositing a metallic ground plane, thin insulating layers, and the microstrip lines on the Si wafer. Thus, the electric fields are isolated from the Si wafer. In this paper, it is shown through experimental results that the ground plane of TFMS may be finite width and comparable to the strip width in size while still achieving low loss on 2 Omega-cm Si. Measured effective permittivity shows that the field interaction with the Si wafer is small.

  4. Standardizing and improving test wafer processes : inventory optimization and a days of inventory pull system

    E-print Network

    Johnson, David W. (David William), S.M. Massachusetts Institute of Technology

    2009-01-01

    Over the past few years, the Intel Fab-17 facility has aggressively pursued lean methodology to reduce the manufacturing costs associated with its aging 200mm diameter wafer process. One area ripe with improvement opportunities ...

  5. Fabrication of capacitive absolute pressure sensor using Si-Au eutectic bonding in SOI wafer

    NASA Astrophysics Data System (ADS)

    Ryeol Lee, Kang; Kim, Kunnyun; Park, Hyo-Derk; Kim, Yong Kook; Choi, Seung-Woo; Choi, Woo-Beom

    2006-04-01

    A capacitive absolute pressure sensor was fabricated using a large deflected diaphragm with a sealed vacuum cavity formed by removing handling silicon wafer and oxide layers from a SOI wafer after eutectic bonding of a silicon wafer to the SOI wafer. The deflected displacements of the diaphragm formed by the vacuum cavity in the fabricated sensor were similar to simulation results. Initial capacitance values were about 2.18pF and 3.65pF under normal atmosphere, where the thicknesses of the diaphragm used to fabricate the vacuum cavity were 20 µm and 30 µm, respectively. Also, it was confirmed that the differences of capacitance value from 1000hPa to 5hPa were about 2.57pF and 5.35pF, respectively.

  6. High-temperature healing of interfacial voids in GaAs wafer bonding

    NASA Astrophysics Data System (ADS)

    Wu, YewChung Sermon; Liu, Po Chun; Feigelson, R. S.; Route, R. K.

    2002-02-01

    Artificial voids were introduced at bonding interfaces to study how processing parameters affected the healing mechanism of interfacial voids in GaAs wafer bonding. These voids were created by placing unpatterned wafers in contact with topographically patterned wafers. During the bonding process, crystallites formed within these voids and corresponded to bonded regions within the voids. Their formation depended strongly on the height of the surface irregularities at the wafer interfaces. When the void depth (h) was ?200 nm, most of the crystallites were diamond shaped. The edges of the diamond features were elongated in the <100> direction. On the other hand, when the void depth was small (h?70 nm), dendrites grew quickly in the <110> direction.

  7. Trans-wafer removal of metallization using a nanosecond Tm:fiber laser

    NASA Astrophysics Data System (ADS)

    Mingareev, Ilya; Berger, Sascha; Tetz, Thomas; Abdulfattah, Ali; Sincore, Alex M.; Shah, Lawrence; Richardson, Martin C.

    2015-03-01

    By utilizing photon energies considerably smaller than the semiconductors' energy band gap, space-selective modifications can be induced in semiconductors beyond the laser-incident surface. Previously, we demonstrated that back surface modifications could be produced in 500-600 ?m thin Si and GaAs wafers independently without affecting the front surface. In this paper, we present our latest studies on trans-wafer processing of semiconductors using a self-developed nanosecond-pulsed thulium fiber laser operating at the wavelength 2 ?m. A qualitative study of underlying physical mechanisms responsible for material modification was performed. We explored experimental conditions that will enable many potential applications such as trans-wafer metallization removal for PV cell edge isolation, selective surface annealing and wafer scribing. These processes were investigated by studying the influence of process parameters on the resulting surface morphology, microstructure and electric properties.

  8. Photocatalytic water disinfection by simple and low-cost monolithic and heterojunction ceramic wafers.

    PubMed

    Makwana, Neel M; Hazael, Rachael; McMillan, Paul F; Darr, Jawwad A

    2015-06-01

    In this work, the photocatalytic disinfection of Escherichia coli (E. coli) using dual layer ceramic wafers, prepared by a simple and low-cost technique, was investigated. Heterojunction wafers were prepared by pressing TiO2 and WO3 powders together into 2 layers within a single, self-supported monolith. Data modelling showed that the heterojunction wafers were able to sustain the formation of charged species (after an initial "charging" period). In comparison, a wafer made from pure TiO2 showed a less desirable bacterial inactivation profile in that the rate decreased with time (after being faster initially). The more favourable kinetics of the dual layer system was due to superior electron-hole vectorial charge separation and an accumulation of charges beyond the initial illumination period. The results demonstrate the potential for developing simplified photocatalytic devices for rapid water disinfection. PMID:25976167

  9. In Situ Examinations of Mechanical Dicing-Induced Damage in Semiconductor Wafers

    NASA Astrophysics Data System (ADS)

    Lee, Seong-Min

    This work illustrates how the separation of a semiconductor wafer into individual devices occurs during conventional mechanical dicing. In situ examinations indicate that the final separation of the wafer takes place before the dicing blade has fully penetrated its active surface. Thus, it was predicted that mechanical dicing-induced damage in the separated device patterns would be due to other mechanical actions rather than the grinding action between the diamond particles embedded in the blade and the wafer. Based on the in situ examinations, it was experimentally tested how manipulating the revolving speed of the dicing blade affected the prevention of dicing-induced damage to device patterns. The experimental results show that among various mechanical actions, the impact stress due to the revolving action of the blade could be the most possible candidate for damage in the device pattern on the final uncut semiconductor wafer.

  10. Multi-wire slurry wafering demonstrations. [slicing silicon ingots for solar arrays

    NASA Technical Reports Server (NTRS)

    Chen, C. P.

    1978-01-01

    Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

  11. Reflectance reduction of InP wafers after high-temperature annealing

    E-print Network

    Luryi, Serge

    is beneficial for many devices, such as solar cells, LEDs, and sen- sors. Various methods of reflection unprocessed as the reference sample. Three quarters of one wafer were annealed in an oven at 350, 500, and 600

  12. Nanoetching process on silicon solar cell wafers during mass production for surface texture improvement.

    PubMed

    Ahn, Chisung; Kulkarni, Atul; Ha, Soohyun; Cho, Yujin; Kim, Jeongin; Park, Heejin; Kim, Taesung

    2014-12-01

    Major challenge in nanotechnology is to improve the solar cells efficiency. This can be achieved by controlling the silicon solar cell wafer surface structure. Herein, we report a KOH wet etching process along with an ultrasonic cleaning process to improve the surface texture of silicon solar cell wafers. We evaluated the KOH temperature, concentration, and ultra-sonication time. It was observed that the surface texture of the silicon solar wafer changed from a pyramid shape to a rectangular shape under edge cutting as the concentration of the KOH solution was increased. We controlled the etching time to avoid pattern damage and any further increase of the reflectance. The present study will be helpful for the mass processing of silicon solar cell wafers with improved reflectance. PMID:25971104

  13. IEEE TRANSACTIONS ON CONTROL SYSTEMS TECHNOLOGY, VOL. 9, NO. 2, MARCH 2001 381 Multivariable Feedback Relevant System Identification of a Wafer Stepper

    E-print Network

    Van den Hof, Paul

    Feedback Relevant System Identification of a Wafer Stepper System Raymond A. de Callafon and Paul M. J. Van of a positioning mechanism present in a wafer stepper. The positioning mechanism in a wafer stepper is used in chip manufacturing processes for accurate posi- tioning of the silicon wafer on which the chips are to be produced

  14. Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng, Ion Mandoiu, Qinke Wang, Xu Xu, and Alex Z. Zelikovsky

    E-print Network

    Zelikovsky, Alexander

    Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng, Ion Mandoiu, Qinke Wang, Xu@cs.gsu.edu ABSTRACT Multi-project Wafers (MPW) are an efficient way to share the rising costs of mask tooling between and wafer dicing problems under the prevalent side- to-side wafer dicing technology. Our contributions

  15. Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs

    E-print Network

    Chakrabarty, Krishnendu

    Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital So for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort practical constraint for wafer sort, even more so than for package test, not all the scan-based digital

  16. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    SciTech Connect

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.

    2011-07-12

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  17. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    DOEpatents

    Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL)

    2008-11-18

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  18. Improved algorithm for automated alignment of wafers via optimized features location

    NASA Astrophysics Data System (ADS)

    Parshin, Michael; Zalevsky, Zeev

    2009-10-01

    We present a new fuzzy logic-based approach for automatic optimized features location. The technique is used for improved automatic alignment and classification of silicon wafers and chips that are used in the electronics industry. The proposed automatic image processing approach was realized and experimentally demonstrated in real industrial application with typical wafers. The automatic features location and grading supported the industrial requirements and could replace human expert-based inspection that currently is performed manually.

  19. Long persistent near infrared luminescence nanoprobes LiGa5O8:Cr3+-PEG-OCH3 for in vivo imaging

    NASA Astrophysics Data System (ADS)

    Fu, Xiaoyan; Liu, Chunlin; Shi, Junpeng; Man, Huizi; Xu, Jia; Zhang, Hongwu

    2014-09-01

    The Cr3+-doped LiGa5O8 nanoparticles (LGNPs) with long-persistent near-infrared phosphorescence were obtained through a sol-gel approach followed by heat treatment at 800 °C in air. The obtained results reveal that the nanoparticles with an average diameter of 100 nm are well defined and have pure structure of LiGa5O8. After illumination for 3 min using a 254 nm UV lamp, the LGNPs exhibit strong near-infrared peak at ca. 720 nm belonging to tissue transparency window which can last for more than 1 h. Via surface modified with PEG-5000-OCH3, the LGNPs-PEG-OCH3 exhibit excellent biocompatibility and low toxicity. Under in vitro pre-excitation using a 254 nm UV lamp for 3 min, the in vivo distribution of the LGNPs-PEG-OCH3 in the abdomen can be detected in real time for more than 1 h. All the results indicate that the LGNPs-PEG-OCH3 can be used as potential nanoprobes to realize in vivo, real time and long time imaging with high sensitivity.

  20. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    PubMed Central

    Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

    2013-01-01

    Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

  1. Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

    SciTech Connect

    Johnston, S.; Yan, F.; Dorn, D.; Zaunbrecher, K.; Al-Jassim, M.; Sidelkheir, O.; Ounadjela, K.

    2012-06-01

    Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect band images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.

  2. Time-varying wetting behavior on copper wafer treated by wet-etching

    NASA Astrophysics Data System (ADS)

    Tu, Sheng-Hung; Wu, Chuan-Chang; Wu, Hsing-Chen; Cheng, Shao-Liang; Sheng, Yu-Jane; Tsao, Heng-Kwong

    2015-06-01

    The wet cleaning process in semiconductor fabrication often involves the immersion of the copper wafer into etching solutions and thereby its surface properties are significantly altered. The wetting behavior of a copper film deposited on silicon wafer is investigated after a short dip in various etching solutions. The etchants include glacial acetic acid and dilute solutions of nitric acid, hydrofluoric acid, and tetramethylammonium hydroxide. It was found that in most cases a thin oxide layer still remains on the surface of as-received Cu wafers when they are subject to etching treatments. However, a pure Cu wafer can be obtained by the glacial acetic acid treatment and its water contact angle (CA) is about 45°. As the pure Cu wafer is placed in the ambient condition, the oxide thickness grows rapidly to the range of 10-20 Å within 3 h and the CA on the hydrophilic surface also rises. In the vacuum, it is surprising to find that the CA and surface roughness of the pure Cu wafer can grow significantly. These interesting results may be attributed to the rearrangement of surface Cu atoms to reduce the surface free energy.

  3. A comparative analysis of Si wafer surface structure based on AFM and scattered light measurement techniques

    NASA Astrophysics Data System (ADS)

    Litwin, D.; Surma, B.; Piatkowski, B.; Miros, A.; Galas, J.

    2005-09-01

    A scanning helium atom microscope, is a very promising tool in surface science. In this technique a focused beam of low energy, neutral helium atoms is used as an imaging probe. The method is suitable to be applied to surface investigation in science and industry. The He-beam is created by supersonic expansion from a high pressure reservoir through a nozzle. It is focused onto the sample by a mirror created from an electrostatically deformed single silicon wafer. The shape of the mirror is obtained by an electrode system controlled by a computer. The focusing mirror consists of a chemically-prepared silicon wafer placed between two aluminium discs and suspended above an electrode structure. The surface quality of the mirror is the most crucial because it limits resolution of the helium microscope. Therefore it is planned to make various improvements to the mirror at both the macroscopic and atomic levels. The centre of gravity of the paper is in measurements of the surface quality of the wafer using scattered light based technique and AFM, so that the technological process of the wafers could be modified to obtain improved surface. The roughness was studied for the (111) oriented mechanically-chemically polished surfaces of silicon wafers with different miscut. The wafers with miscut of 0°, +/- 0.25o and +/- 0.5o toward (11bar2) direction were used for experiments. The miscut was determined with the accuracy of +/-1'.

  4. Measurements of the geometrical characteristics of the silicon wafer for helium microscope focusing mirror

    NASA Astrophysics Data System (ADS)

    Litwin, D.; Galas, J.; Kozlowski, T.; Sitarek, S.

    2005-09-01

    Nano-resolution imaging techniques such as scanning tunnelling microscopy (STM) and atomic force microscopy(AFM) are well-know in surface science. However, a scanning helium atom microscope, where a focused beam of low energy, neutral helium atoms is used as an imaging probe is a very new concept creating non-destructive and noninvasive surface investigation tool in science and industry. The He-beam is created by supersonic expansion from a high pressure reservoir through a nozzle. It is focused onto the sample by a mirror created from an electrostatically deformed single silicon wafer. The shape of the mirror is enforced by an electrode system controlled by a computer. The focusing mirror consists of a chemically-prepared silicon wafer placed between two aluminium discs and suspended above an electrode structure. The deflection of the mirror is controlled by an electric field between the wafer and the electrodes. The accuracy of the shape of the mirror is the most critical since it determines the resolution of the helium microscope. The required modeling of the mirror shape depends on initial quality of the wafer. Therefore it is planned to make various improvements to the mirror at both the macroscopic and atomic levels. This paper is focused on measurements of flatness and thickness of the wafer with high accuracy using specialized optics based techniques, so that the technological process of the wafers could be modified to obtain high quality material.

  5. Quantitative analysis of trace bulk oxygen in silicon wafers using an inert gas fusion method.

    PubMed

    Uchihara, Hiroshi; Ikeda, Masahiko; Nakahara, Taketoshi

    2003-11-01

    This paper describes a method for removing oxide film from the surface of silicon wafers using an inert gas fusion impulse furnace and precise determination of bulk oxygen within the wafer. A silicon wafer was cut to about 0.35 g (6 x 13 x 2 mm) and dropped into a graphite crucible. The sample was then heated for 40 s at 1300 degrees C. The wafer's oxide film was reduced by carbon and removed as carbon monoxide. The treated silicon sample was taken out of the graphite crucible and maintained again with the holder of the oxygen analyzer. The graphite crucible was then heated to 2100 degrees C. The treated silicon sample was dropped into the heated graphite crucible and the trace bulk oxygen in the wafer was measured using the inert gas fusion infrared absorption method. The relative standard deviations of the oxygen in silicon wafer samples with the removed surface oxide film were determined to be 0.8% for 9.8 x 10(17) atoms/cm3, and 2.7% for 13.0 x 10(17) atoms/cm3. PMID:14640456

  6. Wafer Bonding and Layer Transfer Processes for High Efficiency Solar Cells

    SciTech Connect

    Zahler, J. M.; Fontcuberta i Morral, A.; Ahn, C. G.; Atwater, H. A.; Wanlass, M. W.; Chu, C.; Iles, P. A.

    2003-05-01

    A wafer-bonded four-junction cell design consisting of InGaAs, InGaAsP, GaAs, and Ga0.5In0.5P subcells that could reach one-sun AM0 efficiencies of 35.4% is described. The design relies on wafer-bonding and layer transfer for integration of non-lattice-matched subcells. Wafer bonding and layer transfer processes have shown promise in the fabrication of InP/Si epitaxial templates for growth of the bottom InGaAs and InGaAsP subcells on a Si support substrate. Subsequent wafer bonding and layer transfer of a thin Ge layer onto the lower subcell stack can serve as an epitaxial template for GaAs and Ga0.5In0.5P subcells. Additionally, wafer bonded Ge/Si substrates offer the possibility to improve the mechanical performance of existing triple-junction solar cell designs, while simultaneously reducing their cost. Present results indicate that optically active III/V compound semiconductors can be grown on both Ge/Si and InP/Si heterostructures. Current-voltage electrical characterization of the interfaces of these structures indicates that both InP/Si and Ge/Si interfaces have specific resistances lower than 0.1 W?cm2 for heavily doped wafer bonded interfaces, enabling back surface power extraction from the finished cell structure.

  7. Determining lifetime in silicon blocks and wafers with accurate expressions for carrier density

    NASA Astrophysics Data System (ADS)

    Bowden, Stuart; Sinton, Ronald A.

    2007-12-01

    In recent years, many studies of silicon minority-carrier lifetime have been performed with quasi-steady-state photoconductance measurements. The method has been used to characterize the defect levels, surface passivation, and trapping effects in wafers by using absolutely calibrated data for minority-carrier lifetime versus minority-carrier injection level. This paper generalizes the quasi-steady-state photoconductance technique for use in thick wafers or blocks of silicon where the diffusion length or light absorption depth is much less than the sample thickness. The photogeneration and carrier diffusion profiles are calculated for special cases of interest. The measured effective lifetimes can then be used to estimate the bulk lifetime in the material, and report this lifetime at an appropriate average minority-carrier density for the measurement conditions. In this way, the results and measurement methodologies previously developed for use on wafers can be applied to single- or multi-crystalline silicon ingots or thick wafers. In thick silicon samples, long-wavelength weakly absorbed light can be used to reduce the effects of surface recombination on the measurement giving important advantages compared to the case of measuring unpassivated wafers. The generalization presented here offers advantages for accurately determining the bulk lifetime of silicon material prior to sawing into wafers and without requiring surface passivation.

  8. Wire-sawing defects on multicrystalline silicon wafers grown by a directional solidification method

    NASA Astrophysics Data System (ADS)

    Du, Guoping; Chen, Nan; Rossetto, Pietro

    2008-05-01

    In the industrial production of multicrystalline silicon (mc-Si) wafers used for solar cells, linear wire-sawing defects are sometimes generated on the surfaces of mc-Si wafers. The presence of such wire-sawing defects makes the mc-Si wafers unsuitable for the fabrication of solar cells. In this work, we first studied the nature of the linear wire-sawing defects on the mc-Si wafers, and then investigated how these wire-sawing defects were generated during the wire-sawing process. It has been found that the linear wire-sawing defects are sawing ridges and ditches on the wafer surfaces, and direct evidence has suggested that they are generated due to the presence of SiC particles embedded within mc-Si. The SiC particles form an obstacle to the movement of the sawing wire during the wire-sawing process, and the sawing wire tends to climb over the SiC obstacle, resulting in the generation of the wire-sawing defects. A model for the generation of the wire-sawing defects has been proposed. This work will be of much practical interest to the commercial mc-Si wafer production communities for solar cells.

  9. Inspection of processes during silicon wafer sawing using low coherence interferometry in the near infrared wavelength region

    NASA Astrophysics Data System (ADS)

    Gastinger, Kay; Johnsen, Lars; Simonsen, Ove; Aksnes, Astrid

    2011-05-01

    Multi-wire sawing of silicon wafers is a tribological process. Slurry consisting of small silicon carbide particles embedded in polyethyleneglycol carries out the abrasive material removal process. During this process small silicon chips are removed from the bulk material. Low coherence interferometry (LCI) is widely used for high accuracy surface topography measurements of materials. This paper presents an application of LCI where the surface of a material (silicon) is inspected from the inside. Light in the near infrared (NIR) wavelength region is used. High spatial resolution is necessary to be able to observe the processes on the micro scale. Therefore a modified solid immersion approach is suggested. That makes it possible to reach a spatial resolution in the range of the illumination wavelength. The topography changes produced by the chippings are in the range of some micrometers. To be able to estimate the volumes of the Si chippings interferometric phase measurements are applied.

  10. P/N InP solar cells on Ge wafers

    NASA Technical Reports Server (NTRS)

    Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

    1994-01-01

    Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented indicating InP/Ge has more power output than GaAs/Ge cells at fluences in excess of this value.

  11. Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule

    SciTech Connect

    Emanuel Sachs Tonio Buonassisi

    2013-01-16

    The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the wafer. In addition, it was found to be suitable for growing very large crystals. The equipment used was simple and inexpensive to operate. Reasonable solar cells were fabricated on re-crystallized material.

  12. Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers

    NASA Astrophysics Data System (ADS)

    Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

    2009-03-01

    As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

  13. Control of Gene Expression in Leptospira spp. by Transcription Activator-Like Effectors Demonstrates a Potential Role for LigA and LigB in Leptospira interrogans Virulence.

    PubMed

    Pappas, Christopher J; Picardeau, Mathieu

    2015-11-15

    Leptospirosis is a zoonotic disease that affects ?1 million people annually, with a mortality rate of >10%. Currently, there is an absence of effective genetic manipulation tools for targeted mutagenesis in pathogenic leptospires. Transcription activator-like effectors (TALEs) are a recently described group of repressors that modify transcriptional activity in prokaryotic and eukaryotic cells by directly binding to a targeted sequence within the host genome. To determine the applicability of TALEs within Leptospira spp., two TALE constructs were designed. First, a constitutively expressed TALE gene specific for the lacO-like region upstream of bgaL was trans inserted in the saprophyte Leptospira biflexa (the TALE?gal strain). Reverse transcriptase PCR (RT-PCR) analysis and enzymatic assays demonstrated that BgaL was not expressed in the TALE?gal strain. Second, to study the role of LigA and LigB in pathogenesis, a constitutively expressed TALE gene with specificity for the homologous promoter regions of ligA and ligB was cis inserted into the pathogen Leptospira interrogans (TALElig). LigA and LigB expression was studied by using three independent clones: TALElig1, TALElig2, and TALElig3. Immunoblot analysis of osmotically induced TALElig clones demonstrated 2- to 9-fold reductions in the expression levels of LigA and LigB, with the highest reductions being noted for TALElig1 and TALElig2, which were avirulent in vivo and nonrecoverable from animal tissues. This study reconfirms galactosidase activity in the saprophyte and suggests a role for LigA and LigB in pathogenesis. Collectively, this study demonstrates that TALEs are effective at reducing the expression of targeted genes within saprophytic and pathogenic strains of Leptospira spp., providing an additional genetic manipulation tool for this genus. PMID:26341206

  14. Stress diagnostics and crack detection in full-size silicon wafers using resonance ultrasonic vibrations

    NASA Astrophysics Data System (ADS)

    Byelyayev, Anton

    Non-destructive monitoring of residual elastic stress in silicon wafers is a matter of strong concern for modern photovoltaic industry. The excess stress can generate cracks within the crystalline structure, which further may lead to wafer breakage. Cracks diagnostics and reduction in multicrystalline silicon, for example, are ones of the most important issues in photovoltaics now. The industry is intent to improve the yield of solar cells fabrication. There is a number of techniques to measure residual stress in semiconductor materials today. They include Raman spectroscopy, X-ray diffraction and infrared polariscopy. None of these methods are applicable for in-line diagnostics of residual elastic stress in silicon wafers for solar cells. Moreover, the method has to be fast enough to fit in solar cell sequential production line. In photovoltaics, fast in-line quality control has to be performed within two seconds per wafer to match the throughput of the production lines. During this Ph.D. research we developed the resonance ultrasonic vibration (RUV) approach to diagnose residual stress non-destructively in full-size multicrystalline silicon wafers used in solar cell manufacturing. This method is based on excitation of longitudinal resonance ultrasonic vibrations in the material using an external piezoelectric transducer combined with high sensitive ultrasonic probe and data acquisition of the frequency response to make the method suitable for in-line diagnostics during wafer and cell manufacturing. Theoretical and experimental analyses of the vibration mode in single crystal and multicrystalline silicon wafers were used to provide a benchmark reference analysis and validation of the approach. Importantly, we observed a clear trend of increasing resonance frequency of the longitudinal vibration mode with higher average in-plane stress obtained with scanning infrared polariscopy. Using the same experimental approach we assessed a fast crack detection and length determination in full-size solar-grade crystalline silicon wafers. We demonstrated on a set of identical non-processed crystalline Si wafers with introduced periphery cracks that the crack shifts a selected RUV peak to a lower frequency and increases the resonance peak's half-width. Both characteristics are gradually increased with the length of the crack. This was confirmed also theoretically by performing finite element analysis of longitudinal vibrations of wafers with cracks. The frequency shift and peak half-width were found to be reliable indicators of the crack appearance in silicon wafers suitable for mechanical quality control and fast wafer's inspection. Resonance ultrasonic vibrations metrology is a promising technique to provide quality control in full-size silicon wafers. This approach has the potential to be further developed into a diagnostic tool to address the needs of silicon wafer manufacturers, both in the microelectronic and the solar cell industries.

  15. Inspection of mechanical and electrical properties of silicon wafers using terahertz tomography and spectroscopy

    NASA Astrophysics Data System (ADS)

    Arnold, Thomas; Muehleisen, Wolfgang; Schicker, Johannes; Hirschl, Christina

    2015-05-01

    Two different THz applications in the semiconductor industry were explored and validated against established reference measurement techniques and simulations. The first application investigated the possibility of measuring mechanical deformation behaviour of silicon wafers. Time-domain THz tomography mapping scans were carried out to measure wafer thickness and flatness, both in the native state and under different external mechanical loads. These measurements were carried out for a variety of wafers, and the ensuing deformation maps used to validate newly developed numerical simulation models for wafer deformation, and vice versa. In the second part of this paper, carrier dynamics of optically injected charges were investigated by THz spectroscopy. THz pump/probe measurements were carried out in transmission and reflection arrangements on silicon wafers illuminated by a metal halide light source. The light source generates free charge carriers in the semiconductor material that affect the transmission and reflection properties of the semiconductor material. The results of the THz measurements are compared to established standard techniques, like microwave-detected photo-conductance decay (MWPCD) or quasi-steady-state photo conductance (QSSPC) measurements. The defective areas identified with the THz measurements are in good agreement with the defective areas identified by the reference methods. A common benefit of time-domain THz measurements is that the wafer thickness, which is an important measure for the interaction volume of the THz radiation with the semiconductor material, can be calculated from the time- domain signals. The results indicate that THz spectroscopy and imaging can be valuable tools for defect analysis and quality control of silicon wafers, especially since the measurement is fully contact-free and can determine mechanical and electrical properties within a single modality.

  16. Meso-scale machining capabilities and issues

    SciTech Connect

    BENAVIDES,GILBERT L.; ADAMS,DAVID P.; YANG,PIN

    2000-05-15

    Meso-scale manufacturing processes are bridging the gap between silicon-based MEMS processes and conventional miniature machining. These processes can fabricate two and three-dimensional parts having micron size features in traditional materials such as stainless steels, rare earth magnets, ceramics, and glass. Meso-scale processes that are currently available include, focused ion beam sputtering, micro-milling, micro-turning, excimer laser ablation, femto-second laser ablation, and micro electro discharge machining. These meso-scale processes employ subtractive machining technologies (i.e., material removal), unlike LIGA, which is an additive meso-scale process. Meso-scale processes have different material capabilities and machining performance specifications. Machining performance specifications of interest include minimum feature size, feature tolerance, feature location accuracy, surface finish, and material removal rate. Sandia National Laboratories is developing meso-scale electro-mechanical components, which require meso-scale parts that move relative to one another. The meso-scale parts fabricated by subtractive meso-scale manufacturing processes have unique tribology issues because of the variety of materials and the surface conditions produced by the different meso-scale manufacturing processes.

  17. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Larkin, David J. (inventor); Powell, J. Anthony (inventor)

    1992-01-01

    A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  18. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Powell, J. Anthony (inventor)

    1991-01-01

    This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  19. Behavior of piezoelectric wafer active sensor in various media

    NASA Astrophysics Data System (ADS)

    Kamas, Tuncay

    The dissertation addresses structural health monitoring (SHM) techniques using ultrasonic waves generated by piezoelectric wafer active sensors (PWAS) with an emphasis on the development of theoretical models of standing harmonic waves and guided waves. The focal objective of the research is to extend the theoretical study of electro-mechanical coupled PWAS as a resonator/transducer that interacts with standing and traveling waves in various media through electro-mechanical impedance spectroscopy (EMIS) method and guided wave propagation. The analytical models are developed and the coupled field finite element analysis (CF-FEA) models are simulated and verified with experiments. The dissertation is divided into two parts with respect to the developments in EMIS methods and GWP methods. In the first part, analytical and finite element models have been developed for the simulation of PWAS-EMIS in in-plane (longitudinal) and out-of-plane (thickness) mode. Temperature effects on free PWAS-EMIS are also discussed with respect to the in-plane mode. Piezoelectric material degradation on certain electrical and mechanical properties as the temperature increases is simulated by our analytical model for in-plane circular PWAS-EMIS that agrees well with the sets of experiments. Then the thickness mode PWAS-EMIS model was further developed for a PWAS resonator bonded on a plate-like structure. The latter analytical model was to determine the resonance frequencies for the normal mode expansion method through the global matrix method by considering PWAS-substrate and proof mass-PWAS-substrate models. The proof mass concept was adapted to shift the systems resonance frequencies in thickness mode. PWAS in contact with liquid medium on one of its surface has been analytically modeled and simulated the electro-mechanical response of PWAS with various liquids with different material properties such as the density and the viscosity. The second part discusses the guided wave propagation in elastic structures. The feature guided waves in thick structures and in high frequency range are discussed considering weld guided quasi-Rayleigh waves. Furthermore, the weld guided quasi Rayleigh waves and their interaction with damages in thick plates and thick walled pipes are examined by the finite element models and experiments. The dissertation finishes with a summary of contributions followed by conclusions, and suggestions for future work.

  20. Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

    PubMed

    Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

    2015-11-01

    Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. PMID:26452942

  1. Process for uniformly electroplating a patterned wafer with electrically isolated devices

    NASA Astrophysics Data System (ADS)

    Zhang, S.; Meng, X.; Zheng, X.; Das, S. R.; Shepherd, F.

    2004-05-01

    This article reports a technique to electroplate a patterned wafer with electrically isolated devices. A seed layer of Ti/Au was deposited on a SiO2/InP substrate. After lithography, 1.2-?m-thick Au was electroplated on the patterned wafer. Then Ti (10 nm) was deposited on the wafer by vacuum evaporation. Ti on the photoresist was lifted off in PRS 2000, while Ti on the plated Au was retained and was used as an etch-protection layer. The wafer was etched in saturated KI solution to remove the unprotected Au of the seed layer. Finally, exposed Ti in the seed layer, as well as on the plated gold surface, was etched with a HF:HNO3:H2O solution. Auger electron spectroscopy analysis of the wafer did not detect any residual Ti on the gold surface or on the SiO2. Electrical probing between two isolated devices exhibited infinite resistance, which indicated that the unwanted seed layer was completely removed. Scanning electron microscopy confirmed that the metal (seed layer plus electroplated Au) on the devices had the desired cross section. This technique has been used to successfully fabricate T electrodes on traveling wave polarization converter devices and bond pads for p-side down bonding of uncooled directly modulated lasers. .

  2. Characterization of Charging Control of a Single Wafer High Current Spot Beam Implanter

    SciTech Connect

    Schmeide, Matthias; Bukethal, Christoph

    2008-11-03

    This paper focuses on the characterization of charging control of an Axcelis Optima HD single wafer high current spot beam implanter using MOS capacitors with attached antennas of different size and shape. Resist patterns are implemented on Infineon Technologies own charging control wafers to investigate the influence of photo resist on charging damage. Compared to batch high current implanters the design of the beamline and the beam shape are comparable to single wafer high current spot beam implanters, however due to the different scanning architecture the dose rate of the single wafer high current spot beam implanters is significantly higher compared to the batch tools. Therefore, the risk of charging damage will be higher. The charging damage was studied as a function of the energy, the beam current and the most important plasma flood gun parameters. The results have shown that for very high antenna ratios the charging damage for single wafer implanters, even spot or ribbon beam implanters, is higher than for high current batch implanters.

  3. Wafer bonding technology for new generation vacuum MEMS: challenges and promises

    NASA Astrophysics Data System (ADS)

    Dragoi, V.; Pabo, E.

    2015-05-01

    Various MEMS devices are incorporated into consumer electronic devices. A particular category of MEMS require vacuum packaging by wafer bonding with the need to encapsulate vacuum levels of 10-2 mbar or higher with long time stability. The vacuum requirement is limiting the choice of the wafer bonding process and raises significant challenges to the existing investigation methods (metrology) used for results qualification. From the broad range of wafer bonding processes only few are compatible with vacuum applications: fusion bonding, anodic bonding, glass frit bonding and metal-based bonding. The outgassing from the enclosed surfaces after bonding will affect the vacuum level in the cavity: in some cases, a getter material is used inside the device cavity to compensate for this outgassing. Additionally the selected bonding process must be compatible with the devices on the wafers being bonded. This work reviews the principles of vacuum encapsulation using wafer bonding. Examples showing the suitability of each process for specific applications types will be presented. A significant challenge in vacuum MEMS fabrication is the lack of analytical methods needed for process characterization or reliability testing. A short overview of the most used methods and their limitations will be presented. Specific needs to be addressed will be introduced with examples.

  4. Gated Silicon Drift Detector Fabricated from a Low-Cost Silicon Wafer

    PubMed Central

    Matsuura, Hideharu; Sakurai, Shungo; Oda, Yuya; Fukushima, Shinya; Ishikawa, Shohei; Takeshita, Akinobu; Hidaka, Atsuki

    2015-01-01

    Inexpensive high-resolution silicon (Si) X-ray detectors are required for on-site surveys of traces of hazardous elements in food and soil by measuring the energies and counts of X-ray fluorescence photons radially emitted from these elements. Gated silicon drift detectors (GSDDs) are much cheaper to fabricate than commercial silicon drift detectors (SDDs). However, previous GSDDs were fabricated from 10-k?·cm Si wafers, which are more expensive than 2-k?·cm Si wafers used in commercial SDDs. To fabricate cheaper portable X-ray fluorescence instruments, we investigate GSDDs formed from 2-k?·cm Si wafers. The thicknesses of commercial SDDs are up to 0.5 mm, which can detect photons with energies up to 27 keV, whereas we describe GSDDs that can detect photons with energies of up to 35 keV. We simulate the electric potential distributions in GSDDs with Si thicknesses of 0.5 and 1 mm at a single high reverse bias. GSDDs with one gate pattern using any resistivity Si wafer can work well for changing the reverse bias that is inversely proportional to the resistivity of the Si wafer. PMID:26007742

  5. Microwave ECR plasma electron flood for low pressure wafer charge neutralization

    SciTech Connect

    Vanderberg, Bo; Nakatsugawa, Tomoya; Divergilio, William

    2012-11-06

    Modern ion implanters typically use dc arc discharge Plasma Electron Floods (PEFs) to neutralize wafer charge. The arc discharge requires using at least some refractory metal hardware, e.g. a thermionically emitting filament, which can be undesirable in applications where no metallic contamination is critical. rf discharge PEFs have been proposed to mitigate contamination risks but the gas flows required can result in high process chamber pressures. Axcelis has developed a microwave electron cyclotron resonance (ECR) PEF to provide refractory metals contamination-free wafer neutralization with low gas flow requirement. Our PEF uses a custom, reentrant cusp magnet field providing ECR and superior electron confinement. Stable PEF operation with extraction slits sized for 300 mm wafers can be attained at Xe gas flows lower than 0.2 sccm. Electron extraction currents can be as high as 20 mA at absorbed microwave powers < 70 W. On Axcelis' new medium current implanter, plasma generation has proven robust against pressure transients caused by, for example, photoresist outgassing by high power ion beams. Charge monitor and floating potential measurements along the wafer surface corroborate adequate wafer charge neutralization for low energy, high current ion beams.

  6. X-ray studies of ultra-thin Si wafers for mirror application

    NASA Astrophysics Data System (ADS)

    Sass, J.; Mazur, K.; Surma, B.; Eichhorn, F.; Litwin, D.; Galas, J.; Sitarek, S.

    2006-12-01

    The ultra-thin 2 in. diameter silicon (1 1 1)-H(1 × 1) wafer appeared to be a promising material for a mirror focusing He-atom beam in a scanning atom microscope. To increase achievable at present resolution from 1.5 ?m to a sub-micron range the 50 ?m thick (1 1 1) silicon wafer with thickness distribution better than ±1 ?m and 0.05° precision of miscut value is necessary. The purpose of this paper was to adapt X-ray measurements to control the miscut value with high precision for the 50 ?m thick silicon wafers as well as to control the deviation of the wafer surface from ideal flat plane by measurements of low-angle reflection using X-ray high resolution diffractometer (HRXRD). The crucial point was the construction of a stress-free ultra-thin wafer holder. The precision of 0.01° miscut value was obtained. The deviation of the surface from the ideal flat surface obtained by X-ray measurements were compared with the one estimated from optical (confocal) method. A satisfactory good conformity between both methods has been observed.

  7. Minimizing wafer defectivity during high-temperature baking of organic films in 193nm lithography

    NASA Astrophysics Data System (ADS)

    Randall, Mai; Longstaff, Christopher; Ueda, Kenichi; Nicholson, Jim; Winter, Thomas

    2006-03-01

    Demands for continued defect reduction in 300mm IC manufacturing is driving process engineers to examine all aspects of the apply process for improvement. Process engineers, and their respective tool sets, are required to process films at temperatures above the boiling point of the casting solvents. This can potentially lead to the sublimation of the film chemical components. The current methods used to minimize wafer defectivity due to bake residues include frequent cleaning of bake plate modules and surrounding equipment, process optimization, and hardware improvements until more robust chemistries are available. IBM has evaluated the Tokyo Electron CLEAN TRACK TM ACT TM 12 high exhaust high temperature hotplate (HHP) lid to minimize wafer level contamination due to the outgasing of a bottom anti-reflective coating (BARC) films during the high temperature bake process. Goal was to minimize airborne contamination (particles in free space), reduce hotplate contamination build up, and ultimately reduce defects on the wafer. This evaluation was performed on a 193nm BARC material. Evaluation data included visual hardware inspections, airborne particle counting, relative thickness build up measurements on hotplate lids, wafer level defect measurements, and electrical open fail rate. Film coat thickness mean and uniformity were also checked to compare the high exhaust HHP with the standard HHP lid. Chemical analysis of the HHP module residue was performed to identify the source material. The work will quantify potential cost savings achieved by reducing added wafer defects during processing and extending PM frequency for equipment cleaning.

  8. A method for temperature profile measurement of silicon wafers in high-temperature environments

    NASA Astrophysics Data System (ADS)

    Appapillai, Anjuli T.; Sachs, Emanuel M.

    2011-02-01

    This paper describes the development of a method to characterize the temperature profile of silicon wafers in high-temperature environments. Monocrystalline wafers are implanted on one surface with B and P ions, which diffuse into the wafer at different rates based on the temperature-dependent diffusivity of the ions during a 30 min soak in the high-temperature environment between 1000 and 1400 °C. The use of two different dopant species, instead of one, yields higher sensitivity of the measured resistance to changes in temperature in this high-temperature range. The ?-T relation is simulated using TSUPREM-4 and calibrated using a furnace of known temperature. The final sheet resistance varies spatially between 50 and 250 ? /sq, and can be related to the temperature of each part of the wafer during the soak step, with a sensitivity of ˜0.5 ?/°C, and a two-dimensional temperature map can be extracted. The method is demonstrated on wafers by characterizing the hot zone of a high-temperature furnace.

  9. New sensing wafer technique for artifact-free transient temperature measurements in PEB processes

    NASA Astrophysics Data System (ADS)

    Sun, Mei H.; Cohen, Barney M.; Quli, Farhat; Renken, Wayne G.

    2003-05-01

    A system for monitoring the transient and steady state temperature profiles during the deep UV (DUV) post exposure bake (PEB) is described. The system, called Accura°C, consists of a sensor wafer, a wireless electronics unit and software on a laptop computer. To monitor temperature platinum resistance temperature detectors (RTDs) are embedded into silicon wafers. A flexible high temperature printed circuit (PC) ribbon cable connects the wireless electronics unit to the wafer. The system robot moves both the sensor wafer and electronics unit through the system. Communication between the electronics unit and a laptop computer is accomplished by a Bluetooth RF link. The RF link enables the laptop computer to analyze the temperature measurements in real time. The rechargeable batteries in the electronics unit allow detailed examination of all process chambers. Further the long operating time and real time data stream provide for bake chamber optimization such as tuning. The sensor integration into the wafer provides accurate, artifact free measurements of the rapid temperature changes during PEB ramps.

  10. Wafer-scale growth of large arrays of perovskite microplate crystals for functional electronics and optoelectronics.

    PubMed

    Wang, Gongming; Li, Dehui; Cheng, Hung-Chieh; Li, Yongjia; Chen, Chih-Yen; Yin, Anxiang; Zhao, Zipeng; Lin, Zhaoyang; Wu, Hao; He, Qiyuan; Ding, Mengning; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

    2015-10-01

    Methylammonium lead iodide perovskite has attracted intensive interest for its diverse optoelectronic applications. However, most studies to date have been limited to bulk thin films that are difficult to implement for integrated device arrays because of their incompatibility with typical lithography processes. We report the first patterned growth of regular arrays of perovskite microplate crystals for functional electronics and optoelectronics. We show that large arrays of lead iodide microplates can be grown from an aqueous solution through a seeded growth process and can be further intercalated with methylammonium iodide to produce perovskite crystals. Structural and optical characterizations demonstrate that the resulting materials display excellent crystalline quality and optical properties. We further show that perovskite crystals can be selectively grown on prepatterned electrode arrays to create independently addressable photodetector arrays and functional field effect transistors. The ability to grow perovskite microplates and to precisely place them at specific locations offers a new material platform for the fundamental investigation of the electronic and optical properties of perovskite materials and opens a pathway for integrated electronic and optoelectronic systems. PMID:26601297

  11. A 24 GHz Wafer Scale Electronically Scanned Antenna Using BST Phase Shifters for Collision Avoidance Systems

    E-print Network

    York, Robert A.

    advances in recent years. The automotive application of ultrasonic sensors, infrared devices, video cameras and can provide detection ranges from within a few centimeters of the vehicle to several hundred meters [1

  12. Wafer-Scale Fabrication of Nanofluidic Arrays and Networks Using Nanoimprint Lithography and Lithographically Patterned Nanowire

    E-print Network

    and Lithographically Patterned Nanowire Electrodeposition Gold Nanowire Masters Aaron R. Halpern, Keith C. Donavan in polydimethylsiloxane (PDMS) from a surface pattern of electrodeposited gold nanowires in a master-replica process measurements. Patterns of gold nanowires with cross-sectional dimensions as small as 50 nm in height and 100 nm

  13. An optical fiber-taper probe for wafer-scale microphotonic device

    E-print Network

    ://www.opticsinfobase.org/abstract.cfm?URI=oe-11-26-3555. 6. M. L. Gorodetsky and V. S. Ilchenko, "High-Q optical whispering-gallery for optical whispering-gallery modes," Opt. Lett. 24, 723­725 (1999). URL http`evre, "Eroded monomode optical fiber for whispering-gallery mode excitation in fused-silica microspheres," Opt

  14. Low-dose performance of wafer-scale CMOS-based X-ray detectors

    NASA Astrophysics Data System (ADS)

    Maes, Willem H.; Peters, Inge M.; Smit, Chiel; Kessener, Yves; Bosiers, Jan

    2015-03-01

    Compared to published amorphous-silicon (TFT) based X-ray detectors, crystalline silicon CMOS-based active-pixel detectors exploit the benefits of low noise, high speed, on-chip integration and featuring offered by CMOS technology. This presentation focuses on the specific advantage of high image quality at very low dose levels. The measurement of very low dose performance parameters like Detective Quantum Efficiency (DQE) and Noise Equivalent Dose (NED) is a challenge by itself. Second-order effects like defect pixel behavior, temporal and quantization noise effects, dose measurement accuracy and limitation of the x-ray source settings will influence the measurements at very low dose conditions. Using an analytical model to predict the low dose behavior of a detector from parameters extracted from shot-noise limited dose levels is presented. These models can also provide input for a simulation environment for optimizing the performance of future detectors. In this paper, models for predicting NED and the DQE at very low dose are compared to measurements on different CMOS detectors. Their validity for different sensor and optical stack combinations as well as for different x-ray beam conditions was validated.

  15. Wafer-scale growth of large arrays of perovskite microplate crystals for functional electronics and optoelectronics

    PubMed Central

    Wang, Gongming; Li, Dehui; Cheng, Hung-Chieh; Li, Yongjia; Chen, Chih-Yen; Yin, Anxiang; Zhao, Zipeng; Lin, Zhaoyang; Wu, Hao; He, Qiyuan; Ding, Mengning; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

    2015-01-01

    Methylammonium lead iodide perovskite has attracted intensive interest for its diverse optoelectronic applications. However, most studies to date have been limited to bulk thin films that are difficult to implement for integrated device arrays because of their incompatibility with typical lithography processes. We report the first patterned growth of regular arrays of perovskite microplate crystals for functional electronics and optoelectronics. We show that large arrays of lead iodide microplates can be grown from an aqueous solution through a seeded growth process and can be further intercalated with methylammonium iodide to produce perovskite crystals. Structural and optical characterizations demonstrate that the resulting materials display excellent crystalline quality and optical properties. We further show that perovskite crystals can be selectively grown on prepatterned electrode arrays to create independently addressable photodetector arrays and functional field effect transistors. The ability to grow perovskite microplates and to precisely place them at specific locations offers a new material platform for the fundamental investigation of the electronic and optical properties of perovskite materials and opens a pathway for integrated electronic and optoelectronic systems. PMID:26601297

  16. Numerical simulation of a single wafer atomic layer deposition process

    E-print Network

    Jones, A. Andrew D., III (Akhenaton-Andrew Dhafir)

    2010-01-01

    Atomic Layer Deposition (ALD) is a process used to deposit nanometer scale films for use in nano electronics. A typical experimental reactor consist of a warm wall horizontal flow tube, a single disc mounted halfway down ...

  17. LIGA FOR LOBSTER?

    SciTech Connect

    Peele, A.G.; Irving, T.H.

    2000-09-01

    The prospect of making a lobster-eye telescope is drawing closer with recent developments in the manufacture of microchannel-plate optics. This would lead to an x-ray all-sky monitor with vastly improved sensitivity and resolution over existing and other planned instruments. We consider a new approach, using deep etch x-ray lithography, to making a lobster-eye lens that offers certain advantages even over microchannel-plate technology.

  18. Initiation time of near-infrared laser-induced slip on the surface of silicon wafers

    SciTech Connect

    Choi, Sungho; Jhang, Kyung-Young

    2014-06-23

    We have determined the initiation time of laser-induced slip on a silicon wafer surface subjected to a near-infrared continuous-wave laser by numerical simulations and experiments. First, numerical analysis was performed based on the heat transfer and thermoelasticity model to calculate the resolved shear stress and the temperature-dependent yield stress. Slip initiation time was predicted by finding the time at which the resolved shear stress reached the yield stress. Experimentally, the slip initiation time was measured by using a laser scattering technique that collects scattered light from the silicon wafer surface and detects strong scattering when the surface slip is initiated. The surface morphology of the silicon wafer surface after laser irradiation was also observed using an optical microscope to confirm the occurrence of slip. The measured slip initiation times agreed well with the numerical predictions.

  19. Fabrication of microoptical freeform arrays on wafer level for imaging applications.

    PubMed

    Dunkel, Jens; Wippermann, Frank; Reimann, Andreas; Brückner, Andreas; Bräuer, Andreas

    2015-12-14

    Miniaturized imaging systems combining an ultra-compact form factor in combination with the ability of refocusing and depth imaging have gained much interest in the field of mobile imaging. Therefore, artificial compound eye cameras are an extremely promising approach for the realization of compact monolithic camera modules on wafer level. Up to now, their imaging performance was limited to low resolution in the range of VGA format according to fabrication constrains given by the established microoptical fabrication methods, namely the reflow of photoresist. In order to overcome these classical limitations, the use of refractive freeform arrays (RFFA) instead of conventional microlens arrays is inevitable. To enable high volume and cost efficient mass production of artificial compound eye cameras for mass markets like the consumer electronics industry, their fabrication on wafer level is essential, but has not been published up to now. We present a wafer level based process chain enabling the fabrication of these elements for the first time. PMID:26698983

  20. Vertically Conductive Single-Crystal SiC-Based Bragg Reflector Grown on Si Wafer.

    PubMed

    Massoubre, David; Wang, Li; Hold, Leonie; Fernandes, Alanna; Chai, Jessica; Dimitrijev, Sima; Iacopi, Alan

    2015-01-01

    Single-crystal silicon carbide (SiC) thin-films on silicon (Si) were used for the fabrication and characterization of electrically conductive distributed Bragg reflectors (DBRs) on 100?mm Si wafers. The DBRs, each composed of 3 alternating layers of SiC and Al(Ga)N grown on Si substrates, show high wafer uniformity with a typical maximum reflectance of 54% in the blue spectrum and a stopband (at 80% maximum reflectance) as large as 100?nm. Furthermore, high vertical electrical conduction is also demonstrated resulting to a density of current exceeding 70?A/cm(2) above 1.5?V. Such SiC/III-N DBRs with high thermal and electrical conductivities could be used as pseudo-substrate to enhance the efficiency of SiC-based and GaN-based optoelectronic devices on large Si wafers. PMID:26601894

  1. Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer

    SciTech Connect

    Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

    1999-09-07

    We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

  2. Strong, high-yield and low-temperature thermocompression silicon wafer-level bonding with gold

    NASA Astrophysics Data System (ADS)

    Taklo, M. M. V.; Storås, P.; Schjølberg-Henriksen, K.; Hasting, H. K.; Jakobsen, H.

    2004-07-01

    A systematic variation of process parameters for wafer-level thermocompression bonding with gold is presented for the first time. The process was optimized for high bond strength and high bond yield. In addition, the impact of the process temperature was investigated. A bond strength of 10.7 ± 4.5 MPa and a bond yield of 89% was achieved when bonding a wafer pair at 298 °C applying 4 MPa pressure for 45 min. A total of ten wafer pairs were bonded in a custom-built bonding tool and tested to establish the optimal process parameters. The bonded interface was found to be strong and dense enough for MEMS applications. The bonds were characterized using pull tests, transmission electron microscopy (TEM) and energy dispersive x-ray spectroscopy (EDS). The TEM inspections indicated that it is possible to form hermetic seals by using the presented bonding method.

  3. Study of Ag-In solder as low temperature wafer bonding intermediate layer

    NASA Astrophysics Data System (ADS)

    Made, Riko I.; Gan, Chee Lip; Lee, Chengkuo; Yan, Li Ling; Yu, Aibin; Yoon, Seung Wook; Lau, John H.

    2008-02-01

    Indium-silver as solder materials for low temperature bonding had been introduced earlier. In theory the final bonding interface composition is determined by the overall materials composition. Wafer bonding based multiple intermediate layers facilitates precise control of the formed alloy composition and the joint thickness. Thus the bonding temperature and post-bonding re-melting temperature could be easily designed by controlling the multilayer materials. In this paper, a more fundamental study of In-Ag solder materials is carried out in chip-to-chip level by using flip-chip based thermocompression bonding. Bonding at 180°C for various time duration under various bonding pressure is studied. Approaches of forming Ag IIIn with re-melting temperature higher than 400°C at the bonding interface are proposed and discussed. Knowledge learned in this process technology can support us to develop sophisticated wafer level packaging process based wafer bonding for applications of MEMS and IC packages.

  4. Self-cooling on power MOSFET using n-type Si wafer

    NASA Astrophysics Data System (ADS)

    Nakatsugawa, H.; Sato, T.; Okamoto, Y.; Kawahara, T.; Yamaguchi, S.

    2012-06-01

    The self-cooling device was developed by combining the commercial n-channel power MOSFET and the copper plating single-crystalline Sb doped n-type silicon wafer in order to improve heat removal or cooling for power devices. The time dependence of the temperature distribution of the self-cooling device was measured to estimate the heat flux both by the thermal conduction and by the Peltier effect. We found that the average temperature of the upper side of the power MOSFET was cooled down about 0.7°C by the addition of the copper plating n-type Si wafer after 40 minutes despite enlargement of the temperature distribution range. This fact strongly indicates that the copper plating ntype Si wafer is one of the candidate materials for use in self-cooling devices.

  5. 3D micro-optical lens scanner made by multi-wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Bargiel, S.; Gorecki, C.; Bara?ski, M.; Passilly, N.; Wiemer, M.; Jia, C.; Frömel, J.

    2013-03-01

    We present the preliminary design, construction and technology of a microoptical, millimeter-size 3-D microlens scanner, which is a key-component for a number of optical on-chip microscopes with emphasis on the architecture of confocal microscope. The construction of the device relies on the vertical integration of micromachined building blocks: top glass lid, silicon electrostatic comb-drive X-Y and Z microactuators with integrated scanning microlenses, ceramic LTCC spacer, and bottom lid with focusing microlens. All components are connected on the wafer level only by sequential anodic bonding. The technology of through wafer vias is applied to create electrical connections through a stack of wafers. More generally, the presented bonding/connection technologies are also of a great importance for the development of various silicon-based devices based on vertical integration scheme. This approach offers a space-effective integration of complex MOEMS devices and an effective integration of various heterogeneous technologies.

  6. First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

    NASA Technical Reports Server (NTRS)

    Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Lai, R.

    2008-01-01

    Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.

  7. Gettering of metal impurities by using phosphorus diffusion in UMG silicon wafers

    NASA Astrophysics Data System (ADS)

    Yoon, Sung Yean; Kim, Jeong; Choi, Kyoon

    2012-06-01

    Upgraded metallurgical grade (UMG) silicon is a cost-effective and energy-efficient silicon material for the production of solar cells. UMG silicon wafers with 5N purity include various kinds of metal impurities like Fe, Ni, Cu, and Co, which may limit the electrical performance of UMG silicon wafers and solar cells. Phosphorus diffusion gettering, which can effectively reduce the transition-metal impurities in the bulk of UMG silicon wafers and enhance the minority carrier lifetime (MCLT), is a well-known process to improve the performance of solar cells in the photovoltaic (PV) industry. In this study, phosphorus diffusion gettering was used at a constant temperature of 700 for 5 hours, and the effects of the gettering process were confirmed by measuring the MCLTs and the efficiencies of the solar cells. Depth profiles of the Fe concentration before and after the gettering process were compared using secondary ion mass spectroscopy (SIMS) measurements.

  8. Vertically Conductive Single-Crystal SiC-Based Bragg Reflector Grown on Si Wafer

    PubMed Central

    Massoubre, David; Wang, Li; Hold, Leonie; Fernandes, Alanna; Chai, Jessica; Dimitrijev, Sima; Iacopi, Alan

    2015-01-01

    Single-crystal silicon carbide (SiC) thin-films on silicon (Si) were used for the fabrication and characterization of electrically conductive distributed Bragg reflectors (DBRs) on 100?mm Si wafers. The DBRs, each composed of 3 alternating layers of SiC and Al(Ga)N grown on Si substrates, show high wafer uniformity with a typical maximum reflectance of 54% in the blue spectrum and a stopband (at 80% maximum reflectance) as large as 100?nm. Furthermore, high vertical electrical conduction is also demonstrated resulting to a density of current exceeding 70?A/cm2 above 1.5?V. Such SiC/III-N DBRs with high thermal and electrical conductivities could be used as pseudo-substrate to enhance the efficiency of SiC-based and GaN-based optoelectronic devices on large Si wafers. PMID:26601894

  9. Impact of EUV photomask line-edge roughness on wafer prints

    NASA Astrophysics Data System (ADS)

    Qi, Zhengqing John; Gallagher, Emily; Negishi, Yoshiyuki; McIntyre, Gregory; Zweber, Amy; Senna, Tasuku; Akutagawa, Satoshi; Konishi, Toshio

    2012-11-01

    The line-edge roughness (LER) of a photomask image has a measurable impact on the corresponding printed wafer LER. This impact increases as wafer exposures move from 193nm DUV to 13.5nm EUV wavelengths since the imaging tool is a low-pass filter with EUV passing more spatial frequencies. Even the high frequency mask LER may impact the wafer image by lowering its image log-slope (ILS). Studying the magnitude and frequency content of mask LER is a first step to reducing the wafer LER. The next step is to determine which components of mask line roughness actually contribute to the wafer line roughness. Order is imposed on this study by fabricating programmed LER patterns on an EUV mask to introduce controlled variations in LER spatial frequency and magnitude. More specifically, line-width roughness (LWR), LER and power spectral density (PSD) are extracted from 64nm and 90nm (1X) pitch lines on a programmed LER EUV photomask. The same mask is then exposed on the ASML EUV Alpha Demo Tool (ADT) at best focus and dose. Three chemically amplified EUV photoresists are evaluated using the programmed LER photomask through PSD and LWR comparisons and the highest performance resist is used for a comprehensive LER transfer analysis. Wafer LWR is extracted from 64nm and 90nm pitch lines and correlated back to the base mask patterns revealing an empirical LWR transfer function (LTF). Finally, the study is extended to 45nm (1X) pitch lines by deploying a pupil filter on the ADT to explore the effect on LWR as the feature sizes shrink.

  10. Improving wafer level CD uniformity for logic applications utilizing mask level metrology and process

    NASA Astrophysics Data System (ADS)

    Cohen, Avi; Trautzsch, Thomas; Buttgereit, Ute; Graitzer, Erez; Hanuka, Ori

    2013-09-01

    Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit (IC). The extension of 193nm based lithography usage combined with design rule shrinkage makes process control, in particular the wafer level CDU control, an extremely important and challenging task in IC manufacturing. In this study the WLCD-CDC closed loop solution offered by Carl Zeiss SMS was examined. This solution aims to improve the wafer level intra-field CDU without the need to run wafer prints and extensive wafer CD metrology. It combines two stand-alone tools: The WLCD tool which measures CD based on aerial imaging technology while applying the exact scanner-used illumination conditions to the photomask and the CDC tool which utilizes an ultra-short femto-second laser to write intra-volume shading elements (Shade-In Elements™) inside the photomask bulk material. The CDC process changes the dose going through the photomask down to the wafer, hence the wafer level intra-field CDU improves. The objective of this study was to evaluate how CDC process is affecting the CD for different type of features and pattern density which are typical for logic and system on chip (SOC) devices. The main findings show that the linearity and proximity behavior is maintained by the CDC process and CDU and CDC Ratio (CDCR) show a linear behavior for the different feature types. Finally, it was demonstrated that the CDU errors of the targeted (critical) feature have been effectively eliminated. In addition, the CDU of all other features have been significantly improved as well.

  11. Apparatus for use in examining the lattice of a semiconductor wafer by X-ray diffraction

    NASA Technical Reports Server (NTRS)

    Parker, D. L.; Porter, W. A. (inventor)

    1978-01-01

    An improved apparatus for examining the crystal lattice of a semiconductor wafer utilizing X-ray diffraction techniques was presented. The apparatus is employed in a method which includes the step of recording the image of a wafer supported in a bent configuration conforming to a compound curve, produced through the use of a vacuum chuck provided for an X-ray camera. The entire surface thereof is illuminated simultaneously by a beam of incident X-rays which are projected from a distant point-source and satisfy conditions of the Bragg Law for all points on the surface of the water.

  12. Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Calaway, Michael J.; Rodriquez, M. C.; Allton, J. H.; Stansbery, E. K.

    2009-01-01

    The Genesis sample return capsule, though broken during the landing impact, contained most of the shattered ultra-pure solar wind collectors comprised of silicon and other semiconductor wafers materials. Post-flight analysis revealed that all wafer fragments were littered with surface particle contamination from spacecraft debris as well as soil from the impact site. This particulate contamination interferes with some analyses of solar wind. In early 2005, the Genesis science team decided to investigate methods for removing the surface particle contamination prior to solar wind analysis.

  13. Thermal and structural assessments of a ceramic wafer seal in hypersonic engine

    NASA Technical Reports Server (NTRS)

    Tong, Mike; Steinetz, Bruce

    1991-01-01

    The thermal and structural performances of a ceramic wafer seal in a simulated hypersonic engine environment are numerically assessed. The effects of aerodynamic heating, surface contact conductance between the seal and its adjacent surfaces, flow of purge coolant gases, and leakage of hot engine flow path gases on the seal temperature were investigated from the engine inlet back to the entrance region of the combustion chamber. Finite element structural analyses, coupled with Weibull failure analyses, were performed to determine the structural reliability of the wafer seal.

  14. Thermal and structural assessments of a ceramic wafer seal in hypersonic engines

    NASA Technical Reports Server (NTRS)

    Tong, Mike T.; Steinetz, Bruce M.

    1991-01-01

    The thermal and structural performances of a ceramic wafer seal in a simulated hypersonic engine environment are numerically assessed. The effects of aerodynamic heating, surface contact conductance between the seal and its adjacent surfaces, flow of purge coolant gases, and leakage of hot engine flow path gases on the seal temperature were investigated from the engine inlet back to the entrance region of the combustion chamber. Finite element structural analyses, coupled with Weibull failure analyses, were performed to determine the structural reliability of the wafer seal.

  15. Process for the homoepitaxial growth of single-crystal silicon carbide films on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Powell, J. Anthony (inventor)

    1993-01-01

    The invention is a method for growing homoepitaxial films of SiC on low tilt angle vicinal (0001) SiC wafers. The invention proposes and teaches a new theoretical model for the homoepitaxial growth of SiC films on (0001) SiC substrates. The inventive method consists of preparing the growth surface of SiC wafers slightly off-axis (from less the 0.1 to 6 deg) from the (0001) plane, subjecting the growth surface to a suitable etch, and then growing the homoepitaxial film using conventional SiC growth techniques.

  16. Measurement of principal refractive indices of birefringent wafer by analysis of Fabry-Perot interference fringes.

    PubMed

    Choi, Hee Joo; Cha, Myoungsik

    2014-08-20

    We developed an efficient method for measuring the principal refractive indices and thickness of an optically anisotropic wafer that involves the analysis of Fabry-Perot interference fringes. Utilizing the birefringence of the medium, the 2? phase ambiguity was readily resolved in single-wavelength measurements of the birefringent medium index. Although the accuracy of the index measurements is limited due to the innate ambiguity, our analysis method overcame this limit and could determine the principal refractive indices and thickness with an uncertainty of 10(-5). Our method was validated against measurements of a lithium niobate wafer for which the values of the indices are precisely known. PMID:25321129

  17. Application of contact theory to metal-metal bonding of silicon wafers

    NASA Astrophysics Data System (ADS)

    Leong, H. L.; Gan, C. L.; Thompson, C. V.; Pey, K. L.; Li, H. Y.

    2007-11-01

    A model is presented which relates the applied load and surface roughness to the integrity of metal-metal wafer-level thermocompression bonds. Using contact theory, the true contact area is calculated as a function of the applied load and surface roughness as characterized using atomic force microscopy. The relationship between the nominal and true contact areas quantifies the effects of applied load and surface roughness on the bond integrity of the bonded wafers as indicated by the dicing yield. Experiments on Cu-Cu bonds show that the true contact area provides a better indicator of bond integrity than either the nominal contact area or applied force, taken together or separately.

  18. Second harmonic generation for contactless non-destructive characterization of silicon on insulator wafers

    NASA Astrophysics Data System (ADS)

    Damianos, D.; Pirro, L.; Soylu, G.; Ionica, I.; Nguyen, V.; Vitrant, G.; Kaminski, A.; Blanc-Pelissier, D.; Onestas, L.; Changala, J.; Kryger, M.; Cristoloveanu, S.

    2016-01-01

    In this work we investigate a non-invasive, non-destructive characterization technique for monitoring the quality of film, oxide and interfaces in silicon-on-insulator (SOI) wafers. This technique is based on optical Second Harmonic Generation (SHG). The principles of SHG and the experimental setup will be thoroughly described. The experimental parameters best suited for testing SOI wafers with SHG are identified. SOI geometry, as well as the passivation of the top surface, both have an impact on the observed SHG signal. The back-gate bias applied on the substrate is shown to modulate the SHG signal.

  19. Study on higher harmonic suppression using edge filter and polished Si wafer

    SciTech Connect

    Gupta, R. K. Singh, Amol Modi, Mohammed H. Lodha, G. S.

    2014-04-24

    Higher harmonics contamination is a severe problem in synchrotron beamlines where grating monochromators are used. In these beamlines, absorption edge filters and critical angle mirrors are used to suppress the harmonic contaminations. In the present study, carried out using Indus-1 reflectivity beamline, a harmonic suppression characteristic of Al edge filter and polished silicon wafer are determined. It is found that the Al filter suppresses higher harmonics in 2–7% range whereas the polished silicon wafer can suppress the higher harmonics below 1%. The results of comparative study are discussed.

  20. A chemical/microwave technique for the measurement of bulk minority carrier lifetime in silicon wafers

    NASA Technical Reports Server (NTRS)

    Luke, Keung L.; Cheng, Li-Jen

    1988-01-01

    A chemical/microwave technique for the measurement of bulk minority carrier lifetime in silicon wafers is described. This method consists of a wet chemical treatment (surface cleaning, oxidation in solution, and measurement in HF solution) to passivate the silicon surfaces, a laser diode array for carrier excitation, and a microwave bridge measuring system which is more sensitive than the microwave systems used previously for lifetime measurement. Representative experimental data are presented to demonstrate this technique. The result reveals that this method is useful for the determination of bulk lifetime of commercial silicon wafers.