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Sample records for wafer scale liga

  1. A Batch Wafer Scale LIGA Assembly and Packaging Technique vai Diffusion Bonding

    SciTech Connect

    Christenson, T.R.; Schmale, D.T.

    1999-01-27

    A technique using diffusion bonding (or solid-state welding) has been used to achieve batch fabrication of two- level nickel LIGA structures. Interlayer alignment accuracy of less than 1 micron is achieved using press-fit gauge pins. A mini-scale torsion tester was built to measure the diffusion bond strength of LIGA formed specimens that has shown successful bonding at temperatures of 450"C at 7 ksi pressure with bond strength greater than 100 Mpa. Extensions to this basic process to allow for additional layers and thereby more complex assemblies as well as commensurate packaging are discussed.

  2. LIGA Scanner Control Software

    Energy Science and Technology Software Center (ESTSC)

    1999-02-01

    The LIGA Scanner Software is a graphical user interface package that facilitates controlling the scanning operation of x-rays from a synchrotron and sample manipulation for making LIGA parts. The process requires scanning of the LIGA mask and the PMMA resist through a stationary x-ray beam to provide an evenly distributed x-ray exposure over the wafer. This software package has been written specifically to interface with Aerotech motor controllers.

  3. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  4. Parallel Assembly of LIGA Components

    SciTech Connect

    Christenson, T.R.; Feddema, J.T.

    1999-03-04

    In this paper, a prototype robotic workcell for the parallel assembly of LIGA components is described. A Cartesian robot is used to press 386 and 485 micron diameter pins into a LIGA substrate and then place a 3-inch diameter wafer with LIGA gears onto the pins. Upward and downward looking microscopes are used to locate holes in the LIGA substrate, pins to be pressed in the holes, and gears to be placed on the pins. This vision system can locate parts within 3 microns, while the Cartesian manipulator can place the parts within 0.4 microns.

  5. Low cost camera modules using integration of wafer-scale optics and wafer-level packaging of image sensors

    NASA Astrophysics Data System (ADS)

    Han, Hongtao; Main, Keith

    2009-11-01

    Using wafer scale optics, wafer scale integration, and wafer level packaging of image sensor, we developed small form factor (3.3mmx3.3mmx2.5mm), low manufacturing cost, Pb-free solder reflow compatible digital camera modules which are suitable for many applications including mobile electronic devices, automotives, security, and medical applications.

  6. Wafer-scale aluminum nano-plasmonics

    NASA Astrophysics Data System (ADS)

    George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

    2014-09-01

    The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

  7. IGBT scaling principle toward CMOS compatible wafer processes

    NASA Astrophysics Data System (ADS)

    Tanaka, Masahiro; Omura, Ichiro

    2013-02-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

  8. Wafer-scale synthesis and transfer of graphene films.

    PubMed

    Lee, Youngbin; Bae, Sukang; Jang, Houk; Jang, Sukjae; Zhu, Shou-En; Sim, Sung Hyun; Song, Young Il; Hong, Byung Hee; Ahn, Jong-Hyun

    2010-02-10

    We developed means to produce wafer scale, high-quality graphene films as large as 3 in. wafer size on Ni and Cu films under ambient pressure and transfer them onto arbitrary substrates through instantaneous etching of metal layers. We also demonstrated the applications of the large-area graphene films for the batch fabrication of field-effect transistor (FET) arrays and stretchable strain gauges showing extraordinary performances. Transistors showed the hole and electron mobilities of the device of 1100 +/- 70 and 550 +/- 50 cm(2)/(V s) at drain bias of -0.75 V, respectively. The piezo-resistance gauge factor of strain sensor was approximately 6.1. These methods represent a significant step toward the realization of graphene devices in wafer scale as well as application in optoelectronics, flexible and stretchable electronics. PMID:20044841

  9. Liga developer apparatus system

    DOEpatents

    Boehme, Dale R.; Bankert, Michelle A.; Christenson, Todd R.

    2003-01-01

    A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

  10. Wafer-scale fabrication of penetrating neural microelectrode arrays.

    PubMed

    Bhandari, Rajmohan; Negi, Sandeep; Solzbacher, Florian

    2010-10-01

    The success achieved with implantable neural interfaces has motivated the development of novel architectures of electrode arrays and the improvement of device performance. The Utah electrode array (UEA) is one example of such a device. The unique architecture of the UEA enables single-unit recording with high spatial and temporal resolution. Although the UEA has been commercialized and been used extensively in neuroscience and clinical research, the current processes used to fabricate UEA's impose limitations in the tolerances of the electrode array geometry. Further, existing fabrication costs have led to the need to develop less costly but higher precision batch fabrication processes. This paper presents a wafer-scale fabrication method for the UEA that enables both lower costs and faster production. More importantly, the wafer-scale fabrication significantly improves the quality and tolerances of the electrode array and allow better controllability in the electrode geometry. A comparison between the geometrical and electrical characteristics of the wafer-scale and conventional array-scale processed UEA's is presented. PMID:20480240

  11. Wafer-scale aluminum plasmonics for fluorescence based biodetection

    NASA Astrophysics Data System (ADS)

    Farhang, Arash; George, Matthew C.; Williamson, Brent; Black, Mike; Wangensteen, Ted; Fraser, James; Petrova, Rumyana; Prestgard, Kent

    2015-08-01

    Moxtek has leveraged existing capabilities in wafer-scale patterning of sub-wavelength wire grid polarizers into the fabrication of 1D and 2D periodic aluminum plasmonic structures. This work will discuss progress in 200 mm diameter wafer-scale fabrication, with detailed emphasis within the realm of microarray based fluorescence detection. Aluminum nanohole arrays in a hexagonal lattice are first numerically investigated. The nanohole array geometry and periodicity are specifically tuned to coincide both with the excitation of the fluorophore Cy3, and to provide a high field enhancement within the nanoholes where labeled biomolecules are captured. This is accomplished through numerical modelling, nanofabrication, SEM imaging, and optical characterization. A 200mm diameter wafer, patterned with the optically optimized nanohole array, is cut into standard 1x3 inch microscope slide pieces and then subsequently printed with various antigens at 9 different concentrations. A sandwich bioassay is then carried out, using the corresponding conjugate antibodies in order to demonstrate specificity. The nanohole array exhibit a 3-4 times total fluorescence enhancement of Cy3, when compared to a leading commercial microarray glass slide.

  12. Wafer-scale nanowell array patterning based electrochemical impedimetric immunosensor.

    PubMed

    Lee, JuKyung; Cho, SiHyeong; Lee, JungHwan; Ryu, HeonYul; Park, JinGoo; Lim, SunHee; Oh, ByungDo; Lee, ChangWoo; Huang, Wilber; Busnaina, Ahmed; Lee, HeaYeon

    2013-12-01

    We have reported that nanowell array (NWA) can enhance electrochemical detection of molecular binding events by controlling the binding sites of the captured molecules. Using NWA biosensor based amperometric analysis, we have detected biological macromolecules such as DNA, protein or aptamers at low concentrations. In this research, we developed an impedimetric immunosensor based on wafer-scale NWA for electrochemical detection of stress-induced-phosphoprotein-1 (STIP-1). In order to develop NWA sensor through the cost-effective combination of high-throughput nanopattern, the NWA electrode was fabricated on Si wafer by krypton-fluoride (KrF) stepper semiconductor process. Finally, 12,500,000 ea nanowell with a 500 nm diameter was fabricated on 4 mm × 2 mm substrate. Next, by using these electrodes, we measured impedance to quantify antigen binding to the immunoaffinity layer. The limit of detection (LOD) of the NWA was improved about 100-fold compared to milli-sized electrodes (4 mm × 2 mm) without an NWA. These results suggest that wafer-scale NWA immunosensor will be useful for biosensing applications because their interface response is appropriate for detecting molecular binding events. PMID:24013070

  13. Wafer-scale plasmonic and photonic crystal sensors

    NASA Astrophysics Data System (ADS)

    George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

    2015-08-01

    200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

  14. Wrinkled bilayer graphene with wafer scale mechanical strain

    NASA Astrophysics Data System (ADS)

    Mikael, Solomon; Seo, Jung-Hun; Javadi, Alireza; Gong, Shaoqin; Ma, Zhenqiang

    2016-05-01

    Wafer-scale strained bilayer graphene is demonstrated by employing a silicon nitride (Si3N4) stressor layer. Different magnitudes of compressive stress up to 840 MPa were engineered by adjusting the Si3N4 deposition recipes, and different strain conditions were analyzed using Raman spectroscopy. The strained graphene displayed significant G peak shifts and G peak splitting with 16.2 cm-1 and 23.0 cm-1 of the G band and two-dimensional band shift, which corresponds to 0.26% of strain. Raman mapping of large regions of the graphene films found that the largest shifts/splitting occurred near the bilayer regions of the graphene films. The significance of our approach lies in the fact that it can be performed in a conventional microfabrication process, i.e., the plasma enhanced chemical vapor deposition system, and thus easily implemented for large scale production.

  15. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

  16. Designing defect spins for wafer-scale quantum technologies

    SciTech Connect

    Koehl, William F.; Seo, Hosung; Galli, Giulia; Awschalom, David D.

    2015-11-27

    The past decade has seen remarkable progress in the development of the nitrogen-vacancy (NV) defect center in diamond, which is one of the leading candidates for quantum information technologies. The success of the NV center as a solid-state qubit has stimulated an active search for similar defect spins in other technologically important and mature semiconductors, such as silicon carbide. If successfully combined with the advanced microfabrication techniques available to such materials, coherent quantum control of defect spins could potentially lead to semiconductor-based, wafer-scale quantum technologies that make use of exotic quantum mechanical phenomena like entanglement. In this article, we describe the robust spin property of the NV center and the current status of NV center research for quantum information technologies. We then outline first-principles computational modeling techniques based on density functional theory to efficiently search for potential spin defects in nondiamond hosts suitable for quantum information applications. The combination of computational modeling and experimentation has proven invaluable in this area, and we describe the successful interplay between theory and experiment achieved with the divacancy spin qubit in silicon carbide.

  17. Wafer-scale arrays of epitaxial ferroelectric nanodiscs and nanorings

    NASA Astrophysics Data System (ADS)

    Han, Hee; Ji, Ran; Park, Yong Jun; Lee, Sung Kyun; LeRhun, Gwenael; Alexe, Marin; Nielsch, Kornelius; Hesse, Dietrich; Gösele, Ulrich; Baik, Sunggi

    2009-01-01

    Wafer-scale arrays of well-ordered Pb(Zr0.2Ti0.8)O3 nanodiscs and nanorings were fabricated on the entire area (10 mm × 10 mm) of the SrRuO3 bottom electrode on an SrTiO3 single-crystal substrate using the laser interference lithography (LIL) process combined with pulsed laser deposition. The shape and size of the nanostructures were controlled by the amount of PZT deposited through the patterned holes and the temperature of the post-crystallization steps. X-ray diffraction and transmission electron microscopy confirmed that (001)-oriented PZT nanostructures were grown epitaxially on the SrRuO3(001) bottom electrode layer covering the (001)-oriented single-crystal substrate. The domain structures of PZT nano-islands were characterized by reciprocal space mapping using synchrotron x-ray radiation. Ferroelectric properties of each PZT nanostructure were characterized by scanning force microscopy in the piezoresponse mode.

  18. Wafer-scale arrays of epitaxial ferroelectric nanodiscs and nanorings.

    PubMed

    Han, Hee; Ji, Ran; Park, Yong Jun; Lee, Sung Kyun; Le Rhun, Gwenael; Alexe, Marin; Nielsch, Kornelius; Hesse, Dietrich; Gösele, Ulrich; Baik, Sunggi

    2009-01-01

    Wafer-scale arrays of well-ordered Pb(Zr(0.2)Ti(0.8))O3 nanodiscs and nanorings were fabricated on the entire area (10 mm x 10 mm) of the SrRuO3 bottom electrode on an SrTiO3 single-crystal substrate using the laser interference lithography (LIL) process combined with pulsed laser deposition. The shape and size of the nanostructures were controlled by the amount of PZT deposited through the patterned holes and the temperature of the post-crystallization steps. X-ray diffraction and transmission electron microscopy confirmed that (001)-oriented PZT nanostructures were grown epitaxially on the SrRuO3(001) bottom electrode layer covering the (001)-oriented single-crystal substrate. The domain structures of PZT nano-islands were characterized by reciprocal space mapping using synchrotron x-ray radiation. Ferroelectric properties of each PZT nanostructure were characterized by scanning force microscopy in the piezoresponse mode. PMID:19417246

  19. 100-GHz transistors from wafer-scale epitaxial graphene.

    PubMed

    Lin, Y-M; Dimitrakopoulos, C; Jenkins, K A; Farmer, D B; Chiu, H-Y; Grill, A; Avouris, Ph

    2010-02-01

    The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon transistors of the same gate length. PMID:20133565

  20. Wafer-scale fabrication of plasmonic crystals from patterned silicon templates prepared by nanosphere lithography.

    PubMed

    Hall, Anthony Shoji; Friesen, Stuart A; Mallouk, Thomas E

    2013-06-12

    By combining nanosphere lithography with template stripping, silicon wafers were patterned with hexagonal arrays of nanowells or pillars. These silicon masters were then replicated in gold by metal evaporation, resulting in wafer-scale hexagonal gratings for plasmonic applications. In the nanosphere lithography step, two-dimensional colloidal crystals of 510 nm diameter polystyrene spheres were assembled at the air-water interface and transferred to silicon wafers. The spheres were etched in oxygen plasma in order to define their size for masking of the silicon wafer. For fabrication of metallic nanopillar arrays, an alumina film was grown over the nanosphere layer and the spheres were then removed by bath sonication. The well pattern was defined in the silicon wafer by reactive ion etching in a chlorine plasma. For fabrication of metal nanowell arrays, the nanosphere monolayer was used directly as a mask and exposed areas of the silicon wafer were plasma-etched anisotropically in SF6/Ar. Both techniques could be used to produce subwavelength metal replica structures with controlled pillar or well diameter, depth, and profile, on the wafer scale, without the use of direct writing techniques to fabricate masks or masters. PMID:23614608

  1. Wafer-scale growth of VO2 thin films using a combinatorial approach

    NASA Astrophysics Data System (ADS)

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

    2015-10-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that `electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems.

  2. Wafer-scale metamaterials for polarization-insensitive and dual-band perfect absorption

    NASA Astrophysics Data System (ADS)

    Liu, Jia; Zhu, Maoxia; Zhang, Nan; Zhang, Haitao; Zhou, Yu; Sun, Shang; Yi, Ningbo; Gao, Shang; Song, Qinghai; Xiao, Shumin

    2015-11-01

    Mid-infrared (IR) perfect absorbers have great potential in practical applications such as biomedical sensing and thermal energy and have been successfully demonstrated in a number of plasmonic metallic nanostructures. However, all the experimental realizations of perfect absorbers are strongly dependent on nanofabrication techniques, which usually require high costs and a long time to fabricate a wafer scale device. Here we propose and experimentally demonstrate a wafer scale, polarization independent, wide angle, and dual-band IR perfect absorber. By fabricating double ``E''-shaped metallic structures on a ZnSe coated gold film, a dual-band metamaterial absorber has been uniformly realized on a 2'' silicon wafer. Two absorption peaks have been realized at 18 and 27 THz, which are well consistent with the designs. We believe that our research will boost the applications of metamaterial perfect absorbers.

  3. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

  4. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates.

    PubMed

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-19

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes. PMID:26789103

  5. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates

    NASA Astrophysics Data System (ADS)

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-01

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes.

  6. Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments.

    PubMed

    Bomer, Johan G; Prokofyev, Alexander V; van den Berg, Albert; Le Gac, Séverine

    2014-12-01

    We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the microchannels, and alignment precision. Experiments on lipid bilayers with electrophysiological recordings using a model pore-forming polypeptide are demonstrated. PMID:25284632

  7. Wafer-scale growth of VO2 thin films using a combinatorial approach

    PubMed Central

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

    2015-01-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that ‘electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

  8. Fabrication of wafer-scale nanopatterned sapphire substrate through phase separation lithography

    NASA Astrophysics Data System (ADS)

    Guo, Xu; Ni, Mengyang; Zhuang, Zhe; Dai, Jiangping; Wu, Feixiang; Cui, Yushuang; Yuan, Changsheng; Ge, Haixiong; Chen, Yanfeng

    2016-04-01

    A phase separation lithography (PSL) based on polymer blend provides an extremely simple, low-cost, and high-throughput way to fabricate wafer-scale disordered nanopatterns. This method was introduced to fabricate nanopatterned sapphire substrates (NPSSs) for GaN-based light-emitting diodes (LEDs). The PSL process only involved in spin-coating of polystyrene (PS)/polyethylene glycol (PEG) polymer blend on sapphire substrate and followed by a development with deionized water to remove PEG moiety. The PS nanoporous network was facilely obtained, and the structural parameters could be effectively tuned by controlling the PS/PEG weight ratio of the spin-coating solution. 2-in. wafer-scale NPSSs were conveniently achieved through the PS nanoporous network in combination with traditional nanofabrication methods, such as O2 reactive ion etching (RIE), e-beam evaporation deposition, liftoff, and chlorine-based RIE. In order to investigate the performance of such NPSSs, typical blue LEDs with emission wavelengths of ~450 nm were grown on the NPSS and a flat sapphire substrate (FSS) by metal-organic chemical vapor deposition, respectively. The integral photoluminescence (PL) intensity of the NPSS LED was enhanced by 32.3 % compared to that of the FSS-LED. The low relative standard deviation of 4.7 % for PL mappings of NPSS LED indicated the high uniformity of PL data across the whole 2-in. wafer. Extremely simple, low cost, and high throughput of the process and the ability to fabricate at the wafer scale make PSL a potential method for production of nanopatterned sapphire substrates.

  9. LIGA Micromachining: Infrastructure Establishment

    SciTech Connect

    Alfredo M. Morales; Barry V. Hess; Dale R. Boehme; Jill M. Hruby; John S. Krafcik; Robert H. Nilson; Stewart K. Griffiths; William D. Bonivert

    1999-02-01

    LIGA is a micromachining technology that uses high energy x-rays from a synchrotron to create patterns with small lateral dimensions in a deep, non-conducting polymeric resist. Typical dimensions for LIGA parts are microns to tens of microns in lateral size, and hundreds of microns to millimeters in depth. Once the resist is patterned, metal is electrodeposited in the features to create metal microparts, or to create a metal mold for subsequent replication. The acronym LIGA comes from the German words for lithography, electroforming, and molding, and the technology has been under worldwide development for more than a decade. over the last five years, a full-service capability to produce metal microparts using the LIGA process has been established at Sandia national Laboratories, California. This report describes the accomplishments made during the past two years in infrastructure establishment funded by a Laboratory Directed Research and Development (LDRD) project entitled ''LIGA Micromachining.'' Specific topics include photoresist processing for LIGA mask making, x-ray scanning equipment, plating bath instrumentation, plating uniformity, and software architecture.

  10. Self-adaptive phosphor coating technology for wafer-level scale chip packaging

    NASA Astrophysics Data System (ADS)

    Linsong, Zhou; Haibo, Rao; Wei, Wang; Xianlong, Wan; Junyuan, Liao; Xuemei, Wang; Da, Zhou; Qiaolin, Lei

    2013-05-01

    A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.

  11. Terahertz wafer-scale mobility mapping of graphene on insulating substrates without a gate.

    PubMed

    Buron, Jonas D; Mackenzie, David M A; Petersen, Dirch H; Pesquera, Amaia; Centeno, Alba; Bggild, Peter; Zurutuza, Amaia; Jepsen, Peter U

    2015-11-30

    We demonstrate wafer-scale, non-contact mapping of essential carrier transport parameters, carrier mobility (drift), carrier density (Ns), DC sheet conductance (?dc), and carrier scattering time (?sc) in CVD graphene, using spatially resolved terahertz time-domain conductance spectroscopy. ?dc and ?sc are directly extracted from Drude model fits to terahertz conductance spectra obtained in each pixel of 10 10 cm2 maps with a 400 m step size. ?dc- and ?sc-maps are translated into drift and Ns maps through Boltzmann transport theory for graphene charge carriers and these parameters are directly compared to van der Pauw device measurements on the same wafer. The technique is compatible with all substrate materials that exhibit a reasonably low absorption coefficient for terahertz radiation. This includes many materials used for transferring CVD graphene in production facilities as well as in envisioned products, such as polymer films, glass substrates, cloth, or paper substrates. PMID:26698704

  12. 200 mm wafer-scale epitaxial transfer of single crystal Si on glass by anodic bonding of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Teh, W. H.; Trigg, Alastair; Tung, C. H.; Kumar, R.; Balasubramanian, N.; Kwong, D. L.

    2005-08-01

    We report a low-temperature (350 °C) anodic bonding followed by grind/etch-back method for a 200 mm wafer-scale epitaxial transfer of ultrathin (1.9 kÅ) single crystalline Si on Pyrex glass. Standard back-end-of-line 3 kÅ SiN/3 kÅ undoped silicon glass passivating films were used as the buffer layers between the silicon-on-insulator wafer and the glass wafer. The quality and strain-free state of the transferred transparent Si film to glass was characterized by cross-sectional transmission electron microscopy, x-ray diffraction (XRD), and high-resolution XRD. Complete removal of the bulk Si after bonding was ascertained by Auger electron spectroscopy spectra and depth profiling. Strong adhesion between the transferred film and the glass wafer was verified by standard tape adhesion tests. This process will pave the way for future generations of Si-based microelectronics including bioelectronics.

  13. Inexpensive and fast wafer-scale fabrication of nanohole arrays in thin gold films for plasmonics.

    PubMed

    Klein, Mona J K; Guillaumée, Mickaël; Wenger, Bernard; Andrea Dunbar, L; Brugger, Jürgen; Heinzelmann, Harry; Pugin, Raphaël

    2010-05-21

    In this paper, a fast and inexpensive wafer-scale process for the fabrication of arrays of nanoscale holes in thin gold films for plasmonics is shown. The process combines nanosphere lithography using spin-coated polystyrene beads with a sputter-etching process. This allows the batch fabrication of several 1000 microm(2) large hole arrays in 200 nm thick gold films without the use of an adhesion layer for the gold film. The hole size and lattice period can be tuned independently with this method. This allows tuning of the optical properties of the hole arrays for the desired application. An example application, refractive index sensing, is demonstrated. PMID:20413837

  14. Assembly of LIGA using Electric Fields

    SciTech Connect

    FEDDEMA, JOHN T.; WARNE, LARRY K.; JOHNSON, WILLIAM A.; OGDEN, ALLISON J.; ARMOUR, DAVID L.

    2002-04-01

    The goal of this project was to develop a device that uses electric fields to grasp and possibly levitate LIGA parts. This non-contact form of grasping would solve many of the problems associated with grasping parts that are only a few microns in dimensions. Scaling laws show that for parts this size, electrostatic and electromagnetic forces are dominant over gravitational forces. This is why micro-parts often stick to mechanical tweezers. If these forces can be controlled under feedback control, the parts could be levitated, possibly even rotated in air. In this project, we designed, fabricated, and tested several grippers that use electrostatic and electromagnetic fields to grasp and release metal LIGA parts. The eventual use of this tool will be to assemble metal and non-metal LIGA parts into small electromechanical systems.

  15. A Method to Pattern Silver Nanowires Directly on Wafer-Scale PDMS Substrate and Its Applications.

    PubMed

    Chou, Namsun; Kim, Youngseok; Kim, Sohee

    2016-03-01

    This study describes a fabrication method of microsized AgNW patterns based on poly dimethylsiloxane (PDMS) substrate using a poly(p-xylylene) (parylene) stencil technique. Various patterns of AgNW conductive sheets were created on the wafer scale area in the forms of straight and serpentine lines, texts, and symbols, which dimensions ranged from a few tens of micrometers to hundreds of micrometers. We demonstrated the electrical performance of straight line and serpentine line patterned AgNW electrodes when subjected to mechanical strains. The gauge factor and stretchability ranged from 0.5 to 55.2 at 2% uniaxial strain and from 4.7 to 55.7%, respectively, depending on the shapes and structures of the AgNW electrodes. Using the developed AgNW patterning technique, we fabricated strain sensors to detect small body signals epidermally such as hand motion, eye blink and heart rate. Also, tactile sensors were fabricated and exhibited the sensitivity of 3.91 MPa(-1) in the pressure range lower than 50 kPa, and 0.28 MPa(-1) in the pressure range greater than 50 kPa up to 1.3 MPa. From these results, we concluded that the proposed technique enables the fabrication of reliable AgNW patterns on wafer-scale PDMS substrate and the potential applications for various flexible electronic devices. PMID:26882099

  16. Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

    PubMed Central

    Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

    2014-01-01

    In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

  17. Face-to-face transfer of wafer-scale graphene films

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene.

  18. Fabrication of CVD graphene-based devices via laser ablation for wafer-scale characterization

    NASA Astrophysics Data System (ADS)

    Mackenzie, David M. A.; Buron, Jonas D.; Whelan, Patrick R.; Jessen, Bjarke S.; Silajdźić, Adnan; Pesquera, Amaia; Centeno, Alba; Zurutuza, Amaia; Bøggild, Peter; Petersen, Dirch H.

    2015-12-01

    Selective laser ablation of a wafer-scale graphene film is shown to provide flexible, high speed (1 wafer/hour) device fabrication while avoiding the degradation of electrical properties associated with traditional lithographic methods. Picosecond laser pulses with single pulse peak fluences of 140 mJ cm-2 for 1064 nm, 40 mJ cm-2 for 532 nm, and 30 mJ cm-2 for 355 nm are sufficient to ablate the graphene film, while the ablation onset for Si/SiO2 (thicknesses 500 μm/302 nm) did not occur until 240 mJ cm-2, 150 mJ cm-2, and 135 mJ cm-2, respectively, allowing all wavelengths to be used for graphene ablation without detectable substrate damage. Optical microscopy and Raman Spectroscopy were used to assess the ablation of graphene, while stylus profilometery indicated that the SiO2 substrate was undamaged. CVD graphene devices were electrically characterized and showed comparable field-effect mobility, doping level, on-off ratio, and conductance minimum before and after laser ablation fabrication.

  19. Wafer-scale growth of MoS2 thin films by atomic layer deposition.

    PubMed

    Pyeon, Jung Joon; Kim, Soo Hyun; Jeong, Doo Seok; Baek, Seung-Hyub; Kang, Chong-Yun; Kim, Jin-Sang; Kim, Seong Keun

    2016-05-19

    The wafer-scale synthesis of MoS2 layers with precise thickness controllability and excellent uniformity is essential for their application in the nanoelectronics industry. Here, we demonstrate the atomic layer deposition (ALD) of MoS2 films with Mo(CO)6 and H2S as the Mo and S precursors, respectively. A self-limiting growth behavior is observed in the narrow ALD window of 155-175 °C. Long H2S feeding times are necessary to reduce the impurity contents in the films. The as-grown MoS2 films are amorphous due to the low growth temperature. Post-annealing at high temperatures under a H2S atmosphere efficiently improves the film properties including the crystallinity and chemical composition. An extremely uniform film growth is achieved even on a 4 inch SiO2/Si wafer. These results demonstrate that the current ALD process is well suited for the synthesis of MoS2 layers for application in industry. PMID:27166838

  20. High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity.

    PubMed

    Kang, Kibum; Xie, Saien; Huang, Lujie; Han, Yimo; Huang, Pinshane Y; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-04-30

    The large-scale growth of semiconducting thin films forms the basis of modern electronics and optoelectronics. A decrease in film thickness to the ultimate limit of the atomic, sub-nanometre length scale, a difficult limit for traditional semiconductors (such as Si and GaAs), would bring wide benefits for applications in ultrathin and flexible electronics, photovoltaics and display technology. For this, transition-metal dichalcogenides (TMDs), which can form stable three-atom-thick monolayers, provide ideal semiconducting materials with high electrical carrier mobility, and their large-scale growth on insulating substrates would enable the batch fabrication of atomically thin high-performance transistors and photodetectors on a technologically relevant scale without film transfer. In addition, their unique electronic band structures provide novel ways of enhancing the functionalities of such devices, including the large excitonic effect, bandgap modulation, indirect-to-direct bandgap transition, piezoelectricity and valleytronics. However, the large-scale growth of monolayer TMD films with spatial homogeneity and high electrical performance remains an unsolved challenge. Here we report the preparation of high-mobility 4-inch wafer-scale films of monolayer molybdenum disulphide (MoS2) and tungsten disulphide, grown directly on insulating SiO2 substrates, with excellent spatial homogeneity over the entire films. They are grown with a newly developed, metal-organic chemical vapour deposition technique, and show high electrical performance, including an electron mobility of 30 cm(2) V(-1) s(-1) at room temperature and 114 cm(2) V(-1) s(-1) at 90 K for MoS2, with little dependence on position or channel length. With the use of these films we successfully demonstrate the wafer-scale batch fabrication of high-performance monolayer MoS2 field-effect transistors with a 99% device yield and the multi-level fabrication of vertically stacked transistor devices for three-dimensional circuitry. Our work is a step towards the realization of atomically thin integrated circuitry. PMID:25925478

  1. Near-infrared tailored thermal emission from wafer-scale continuous-film resonators.

    PubMed

    Roberts, Alexander S; Chirumamilla, Manohar; Thilsing-Hansen, Kasper; Pedersen, Kjeld; Bozhevolnyi, Sergey I

    2015-09-21

    We experimentally investigate the near-infrared emission from simple-to-fabricate, continuous-film Fabry-Perot-type resonators, consisting only of unstructured dielectric and metallic films. We show that the proposed configuration is suitable for realization of narrowband emitters, tunable in ranges from mid- to near-infrared, and demonstrate emission centered at the wavelength of 1.7 μm, which corresponds to the band gap energy of GaSb-based photodetectors. The emission is measured at 748 K and follows well the emissivity as predicted from reflection measurements and Kirchhoff's reciprocity. The considered emitter configuration is spectrally highly tunable and, consisting of only few unstructured layers, is amenable to wafer-scale fabrication at low cost by use of standard deposition procedures. PMID:26406741

  2. Wafer-scale, three-dimensional helical porous thin films deposited at a glancing angle

    NASA Astrophysics Data System (ADS)

    Huang, Zhifeng; Bai, Fan

    2014-07-01

    Minimization of helices opens a door to impose novel functions derived from the dimensional shrinkage of optical, mechanical and electronic devices. Glancing angle deposition (GLAD) enables one to deposit three-dimensional helical porous thin films (HPTFs) composed of separated spiral micro/nano-columns. GLAD integrates a series of advantageous features, including one-step deposition, wafer-scale production with mono-handedness of spirals, flexible engineering of spiral materials and dimensions, and the adaption to various kinds of substrates. Herein, we briefly review the fabrication of HPTFs by GLAD, specific growth mechanisms, physical properties in structures, mechanics and chiral optics, and the emerging applications in green energy. A prospective outlook is presented to illuminate some promising developments in enantioselection, bio-dynamic analyses, wirelessly-controlled drug delivery and mass production.

  3. Wafer-scale, three-dimensional helical porous thin films deposited at a glancing angle.

    PubMed

    Huang, Zhifeng; Bai, Fan

    2014-08-21

    Minimization of helices opens a door to impose novel functions derived from the dimensional shrinkage of optical, mechanical and electronic devices. Glancing angle deposition (GLAD) enables one to deposit three-dimensional helical porous thin films (HPTFs) composed of separated spiral micro/nano-columns. GLAD integrates a series of advantageous features, including one-step deposition, wafer-scale production with mono-handedness of spirals, flexible engineering of spiral materials and dimensions, and the adaption to various kinds of substrates. Herein, we briefly review the fabrication of HPTFs by GLAD, specific growth mechanisms, physical properties in structures, mechanics and chiral optics, and the emerging applications in green energy. A prospective outlook is presented to illuminate some promising developments in enantioselection, bio-dynamic analyses, wirelessly-controlled drug delivery and mass production. PMID:24838479

  4. Wafer-scale nanopatterning and translation into high-performance piezoelectric nanowires.

    PubMed

    Nguyen, Thanh D; Nagarah, John M; Qi, Yi; Nonnenmann, Stephen S; Morozov, Anatoli V; Li, Simonne; Arnold, Craig B; McAlpine, Michael C

    2010-11-10

    The development of a facile method for fabricating one-dimensional, precisely positioned nanostructures over large areas offers exciting opportunities in fundamental research and innovative applications. Large-scale nanofabrication methods have been restricted in accessibility due to their complexity and cost. Likewise, bottom-up synthesis of nanowires has been limited in methods to assemble these structures at precisely defined locations. Nanomaterials such as PbZr(x)Ti(1-x)O(3) (PZT) nanowires (NWs)--which may be useful for nonvolatile memory storage (FeRAM), nanoactuation, and nanoscale power generation--are difficult to synthesize without suffering from polycrystallinity or poor stoichiometric control. Here, we report a novel fabrication method which requires only low-resolution photolithography and electrochemical etching to generate ultrasmooth NWs over wafer scales. These nanostructures are subsequently used as patterning templates to generate PZT nanowires with the highest reported piezoelectric performance (d(eff) ∼ 145 pm/V). The combined large-scale nanopatterning with hierarchical assembly of functional nanomaterials could yield breakthroughs in areas ranging from nanodevice arrays to nanodevice powering. PMID:20939584

  5. High speed wafer scale bulge testing for the determination of thin film mechanical properties

    PubMed Central

    Orthner, M. P.; Rieth, L. W.; Solzbacher, F.

    2010-01-01

    A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50–150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 μm in width comprised of 720±10 nm thick low pressure chemical vapor deposited silicon nitride with ∼20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to ∼8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (∼350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young’s modulus was estimated for the films assuming a Poisson’s ratio of v=0.25. Calculations to determine Young’s modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young’s modulus for the smaller membranes. The deflection measurements of three 1200×1200 μm2 Si3N4−x membranes were taken at increased pressures (>25 kPa) to increase nonlinearity and better determine Young’s modulus. This pressure-deflection data were fit to an analytical solution and Young’s modulus estimated to be 257±3 GPa, close to those previously reported in literature. PMID:20515176

  6. Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale

    PubMed Central

    2013-01-01

    We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production. PMID:24289275

  7. Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale

    NASA Astrophysics Data System (ADS)

    Ho, Jian-Wei; Wee, Qixun; Dumond, Jarrett; Tay, Andrew; Chua, Soo-Jin

    2013-12-01

    We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production.

  8. Wafer-Scale Monolayer Films of Semiconducting Metal Dichalcogenides for High-Performance Electronics

    NASA Astrophysics Data System (ADS)

    Xie, Saien; Kang, Kibum; Huang, Lujie; Han, Yimo; Huang, Pinshane; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-03-01

    Two-dimensional semiconducting transition metal dichalcogenides (TMDs) have shown their potential in electronics, optoelectronic and valleytronis. However, large-scale growth methods reported to date have only produced materials with limited structural and electrical uniformity, hindering further technological applications. Here we present a 4-inch scale growth of continuous monolayer molybdenum disulfide (MoS2) and tungsten disulfide (WS2) films that show excellent structural and electrical uniformity over the entire wafer using metal-organic chemical vapor deposition. The resulting monolayer films show high mobility of 30 cm2/Vs at room temperature, as well as the phonon-limited transport for MoS2, regardless of the channel length and device location. They allow for the batch fabrication of monolayer MoS2 field effect transistors with a 99% yield, which display spatially-uniform n-type transistor operation with a high on/off ratio. We further demonstrate the multi-level growth and fabrication of vertically-stacked monolayer MoS2 films and devices, which could enable the development of novel three-dimensional circuitry and device integration.

  9. A wafer-scale graphene and ferroelectric multilayer for flexible and fast-switched modulation applications

    NASA Astrophysics Data System (ADS)

    Zhu, Minmin; Wu, Jing; Du, Zehui; Tay, Roland Yingjie; Li, Hongling; Özyilmaz, Barbarous; Teo, Edwin Hang Tong

    2015-08-01

    Here we report a wafer-scale graphene/P(VDF-TrFE)/graphene multilayer for light-weight, flexible and fast-switched broadband modulation applications. The P(VDF-TrFE) film not only significantly reduces the sheet resistance of graphene throughout heavy doping of ~0.8 × 1013 cm-2 by nonvolatile ferroelectric dipoles, but also acts as an efficient electro-optic (EO) layer. Such multilayered structural integration with remarkable ferroelectric polarization, high transparency (>90%), low sheet resistance (~302 Ω □-1), and excellent mechanic flexibility shows the potential of a flexible modulation application over a broad range of wavelengths. Moreover, the derived device also exhibits strong field-induced EO modulation even under bending and one large Pockels coefficient (~54.3 pm V-1) is obtained. Finally, the graphene and ferroelectric hybrid demonstrates a fast switching time (~2 μs) and works well below low sheet resistance level over a long time. This work gives insights into the potential of graphene and ferroelectric hybrid structures, enabling future exploration on next-generation high-performance, flexible transparent electronics and photonics.Here we report a wafer-scale graphene/P(VDF-TrFE)/graphene multilayer for light-weight, flexible and fast-switched broadband modulation applications. The P(VDF-TrFE) film not only significantly reduces the sheet resistance of graphene throughout heavy doping of ~0.8 × 1013 cm-2 by nonvolatile ferroelectric dipoles, but also acts as an efficient electro-optic (EO) layer. Such multilayered structural integration with remarkable ferroelectric polarization, high transparency (>90%), low sheet resistance (~302 Ω □-1), and excellent mechanic flexibility shows the potential of a flexible modulation application over a broad range of wavelengths. Moreover, the derived device also exhibits strong field-induced EO modulation even under bending and one large Pockels coefficient (~54.3 pm V-1) is obtained. Finally, the graphene and ferroelectric hybrid demonstrates a fast switching time (~2 μs) and works well below low sheet resistance level over a long time. This work gives insights into the potential of graphene and ferroelectric hybrid structures, enabling future exploration on next-generation high-performance, flexible transparent electronics and photonics. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr03020j

  10. Efficient fabrication of wafer scale thin film of individualized single-walled carbon nanotubes by dual-nozzle spin casting

    NASA Astrophysics Data System (ADS)

    Kim, Yong Shin; Kwon, Soongeun; Shin, Dong Hun; Shim, Hyung Cheoul; Woo, Ju Yeon; Lim, Donghyun; Kwak, Yoon Keun; Kim, Soohyun; Han, Chang-Soo

    2010-06-01

    In this paper, a dual-nozzle spin casting method was proposed to form a thin film of individualized single-walled carbon nanotubes (SWNTs) at the wafer scale. Each nozzle simultaneously ejected the SWNT solution and methanol, respectively. During the ejection process, two solutions were mixed at the contacting end of the nozzles and then dropped onto the substrate. Functionalization of the wafer substrate with the amine group improved the uniformity of the SWNT thin film as well as the adhesion between the individualized SWNTs and the substrate. The best condition of the spin casting involved the substrate functionalization using 3-aminopropyltriethosilane aqueous solution with a concentration of ˜10 mM and a deposition velocity of ˜5000 rpm. The root-mean-square roughness of the fabricated SWNT layer over the wafer substrate was found to be 1.4-1.8 nm, which indicated that the resultant thin film was one or two layers of SWNTs. The wafer scale SWNT thin film formed by dual-nozzle spin casting can be further used for the mass production and high integration of the SWNT nanoelectronic devices.

  11. Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

    PubMed

    Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

    2012-01-01

    Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects. PMID:22805564

  12. Performance of 4-in. wafer-scale thermoset working stamps in hot-embossing lithography

    NASA Astrophysics Data System (ADS)

    Roos, Nils; Schulz, Hubert; Fink, Marion; Pfeiffer, Karl; Osenberg, Frank; Scheer, Hella-Christin

    2002-07-01

    In order to reduce the cost for stamps featuring nanometer structures in a hot embossing lithography (HEL) process the production and performance of working stamps made of thermoset polymer are of interest. Fabrication of stamps made of thermosetting material no silicon substrates by hot embossing with 2 X 2 cm2 templates and their replication by HEL has already been demonstrate. In this paper the enlargement of this principle to 4 inch wafer- scale is presented. Two procedures to obtain working stamps by hot embossing are compared, one solely based on hot embossing, the other enhanced by additional UV-exposure. The produced working stamps are tested for performance under standard embossing conditions are the topic of anti-sticking layers, a key issue in all large area imprint applications is addressed. Two methods of tailoring adhesion properties of thermosets are proposed, plasma-depositing a fluorinated film and coating with a self-assembled monolayer of fluoroalkyltrichlorosilane, only the former of which was employed successfully. The achieved fidelity of pattern replication with working stamps and imprints thereof is assessed by cross-sectional SEM investigation, showing only the UV-enhanced method to be well suited for the task of obtaining low-cost replications of silicon stamps.

  13. Wafer-scale pattern transfer of metal nanostructures on polydimethylsiloxane (PDMS) substrates via holographic nanopatterns.

    PubMed

    Du, Ke; Wathuthanthri, Ishan; Liu, Yuyang; Xu, Wei; Choi, Chang-Hwan

    2012-10-24

    In this paper, we report on a cost-effective and simple, nondestructive pattern transfer method that allows the fabrication of metallic nanostructures on a polydimethylsiloxane (PDMS) substrate on a wafer scale. The key idea is to use holographic nanopatterns of a photoresist (PR) layer as template structures, where a metal film is directly deposited in order to replicate the nanopatterns of the PR template layer. Then, the PDMS elastomer is molded onto the metal film and the metal/PDMS composite layer is directly peeled off from the PR surface. Many metallic materials including Ti, Al, and Ag were successfully nanopatterned on PDMS substrates by the pattern transfer process with no use of any adhesion promoter layer or coating. In case of Au that has poor adhesion to PDMS material, a salinization of the metal surface with 3-(aminopropyl)-triethoxysilane (APTES) monolayer promoted the adhesion and led to successful pattern transfer. A series of adhesion tests confirmed the good adhesion of the transferred metal films onto the molded PDMS substrates, including scotch-tape and wet immersion tests. The inexpensive and robust pattern transfer approach of metallic nanostructures onto transparent and flexible PDMS substrates will open the new door for many scientific and engineering applications such as micro-/nanofluidics, optofluidics, nanophotonics, and nanoelectronics. PMID:23020206

  14. High throughput ultralong (20 cm) nanowire fabrication using a wafer-scale nanograting template.

    PubMed

    Yeon, Jeongho; Lee, Young Jae; Yoo, Dong Eun; Yoo, Kyoung Jong; Kim, Jin Su; Lee, Jun; Lee, Jeong Oen; Choi, Seon-Jin; Yoon, Gun-Wook; Lee, Dong Wook; Lee, Gi Seong; Hwang, Hae Chul; Yoon, Jun-Bo

    2013-09-11

    Nanowires are being actively explored as promising nanostructured materials for high performance flexible electronics, biochemical sensors, photonic applications, solar cells, and secondary batteries. In particular, ultralong (centimeter-long) nanowires are highly attractive from the perspective of electronic performance, device throughput (or productivity), and the possibility of novel applications. However, most previous works on ultralong nanowires have issues related to limited length, productivity, difficult alignment, and deploying onto the planar substrate complying with well-matured device fabrication technologies. Here, we demonstrate a highly ordered ultralong (up to 20 cm) nanowire array, with a diameter of 50 nm (aspect ratio of up to 4,000,000:1), in an unprecedented large (8 in.) scale (2,000,000 strands on a wafer). We first devised a perfectly connected ultralong nanograting master template on the whole area of an 8 in. substrate using a top-down approach, with a density equivalent to that achieved with e-beam lithography (100 nm). Using this large-area, ultralong, high-density nanograting template, we developed a fast and effective method for fabricating up to 20 cm long nanowire arrays on a plastic substrate, composed of metal, dielectric, oxide, and ferroelectric materials. As a suggestion of practical application, a prototype of a large-area aluminum wire grid polarizer was demonstrated. PMID:23899099

  15. Wafer-scale design of lightweight and transparent electronics that wraps around hairs

    NASA Astrophysics Data System (ADS)

    Salvatore, Giovanni A.; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

    2014-01-01

    Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

  16. Electronic and optoelectronic devices based on chirality-enriched wafer-scale single-wall carbon nanotube thin films

    NASA Astrophysics Data System (ADS)

    Gao, Weilu; He, Xiaowei; Xie, Lijuan; Zhang, Qi; Haroz, Erik; Doorn, Stephen K.; Kono, Junichiro

    2015-03-01

    The unique and rich material properties of single-wall carbon nanotubes (SWCNTs) make them attractive for nano-electronic and optoelectronic applications. Slight changes in tube diameter and wrapping angle, defined by the chirality indices (n, m), can dramatically modify the bandstructure, which can be utilized for designing devices with tailored properties. However, it remains to be a challenge to fabricate macroscopic, single-chirality devices. Here, we introduce a simple way of producing chirality-enriched wafer-scale SWCNT films by combining recently developed solution-based polymer-modified sorting method and vacuum filtration. The produced thin films can be easily transferred onto any substrate to have a CMOS compatible wafer. We fabricated a transistor of (6,5)-enriched SWCNTs with an on/off ratio >103. Large-scale photothermoelectric-effect-based and photovoltaic-effect-based photodetectors made of (6,6)- and (6,5)-enriched films, respectively, will also be discussed.

  17. A wafer-scale backplane-assisted resonating nanoantenna array SERS device created by tunable thermal dewetting nanofabrication

    NASA Astrophysics Data System (ADS)

    Chang, Te-Wei; Ranjan Gartia, Manas; Seo, Sujin; Hsiao, Austin; Logan Liu, Gang

    2014-04-01

    A tunable lithography-less nanofabrication process using a metal thin-film thermal dewetting technique has been developed to fabricate wafer-scale and uniform plasmonic substrates at low cost for optimal performance in surface enhanced Raman scattering (SERS) applications. The relationship between the tunable parameters of this process and the corresponding optical and plasmonic characteristic is investigated both experimentally and theoretically to understand the deterministic design of an optimal SERS device with a three-dimensional plasmonic nanoantenna structure. The enhancement of SERS using various nanoplasmonic particle sizes, structure lengths, lateral hot spot spacings and resonating effects are examined and demonstrated. We achieve a uniform optimal enhancement factor of 1.38 × 108 on a 4 in wafer-scale SERS substrate with a backplane-assisted resonating nanoantenna array design. Sensitive environmental nitrate sensing, vitamin detection and oligonucleotide identification are demonstrated on the high-performance SERS device.

  18. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  19. Field-effect transistors based on wafer-scale, highly uniform few-layer p-type WSe2

    NASA Astrophysics Data System (ADS)

    Campbell, Philip M.; Tarasov, Alexey; Joiner, Corey A.; Tsai, Meng-Yen; Pavlidis, Georges; Graham, Samuel; Ready, W. Jud; Vogel, Eric M.

    2016-01-01

    The synthesis of few-layer tungsten diselenide (WSe2) via chemical vapor deposition typically results in highly non-uniform thickness due to nucleation initiated growth of triangular domains. In this work, few-layer p-type WSe2 with wafer-scale thickness and electrical uniformity is synthesized through direct selenization of thin films of e-beam evaporated W on SiO2 substrates. Raman maps over a large area of the substrate show small variations in the main peak position, indicating excellent thickness uniformity across several square centimeters. Additionally, field-effect transistors fabricated from the wafer-scale WSe2 films demonstrate uniform electrical performance across the substrate. The intrinsic field-effect mobility of the films at a carrier concentration of 3 × 1012 cm-2 is 10 cm2 V-1 s-1. The unprecedented uniformity of the WSe2 on wafer-scale substrates provides a substantial step towards producing manufacturable materials that are compatible with conventional semiconductor fabrication processes.

  20. Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress

    NASA Astrophysics Data System (ADS)

    Chen, Po-Ying; Kung, Heng-Yu; Lai, Yi-Shao; Hsiung Tsai, Ming; Yeh, Wen-Kuan

    2008-02-01

    In this work, we present a novel approach and method for elucidating the characteristics of wafer-level chip-scale packages (WLCSPs) for electromigration (EM) tests. The die in WLCSP was directly attached to the substrate via a soldered interconnect. The shrinking of the area of the die that is available for power, and the solder bump also shrinks the volume and increases the density of electrons for interconnect efficiency. The bump current density now approaches to 106 A/cm2, at which point the EM becomes a significant reliability issue. As known, the EM failure depends on numerous factors, including the working temperature and the under bump metallization (UBM) thickness. A new interconnection geometry is adopted extensively with moderate success in overcoming larger mismatches between the displacements of components during current and temperature changes. Both environments and testing parameters for WLCSP are increasingly demanded. Although failure mechanisms are considered to have been eliminated or at least made manageable, new package technologies are again challenging its process, integrity and reliability. WLCSP technology was developed to eliminate the need for encapsulation to ensure compatibility with smart-mount technology (SMT). The package has good handing properties but is now facing serious reliability problems. In this work, we investigated the reliability of a WLCSP subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 °C. A very strong correlation exists between the mean time to failure (MTTF) of the WLCSP test vehicle and the mean current density that is carried by a solder joint. A series of current densities were applied to the WLCSP architecture; Black's power law was employed in a failure mode simulation. Additionally, scanning electron microscopy (SEM) was adopted to determine the differences existing between high- and low-current-density failure modes.

  1. Wafer-scale arrayed p-n junctions based on few-layer epitaxial GaTe

    NASA Astrophysics Data System (ADS)

    Yuan, Xiang; Tang, Lei; Hu, Weida; Xiu, Faxian

    2015-03-01

    Two dimensional (2D) materials have showed appealing applications in electronics and optoelectronics. Gapless graphene presents ultra-broadband and fast photoresponse while the 2D semiconducting MoS2 and GaTe exhibit highly sensitive and tunable responsivity to the visible light. However, the device yield and its repeatability call for a further improvement of 2D materials to render large-scale uniformity. Here we report a layer-by-layer growth of the wafer-scale GaTe by molecular beam epitaxy. To develop the arrayed p-n junctions, the few-layer GaTe was grew on three-inch Si wafers. The resultant diodes reveal good rectifying characteristics and photoresponse with maximum photodetection responsivity of 2.74 A/W and photovoltaic external quantum efficiency up to 62%. The photocurrent reaches saturation very fast within 22 ?s and shows no sign of device degradation after 1.37 million cycles of operation. Most strikingly, such high performance has been achieved across the entire wafer, making the volume production of devices accessible. Finally, several photo-images was acquired by using these photodiodes with a reasonable contrast and resolution, demonstrating for the first time the potential for these 2D technology coming into the real life.

  2. Study of wafer thickness scaling in n-type rear-emitter solar cells with different bulk lifetimes

    NASA Astrophysics Data System (ADS)

    Chen, Chen; Zhang, Wei; Xing, Zhao; Sun, Yun; Jia, Rui; Jin, Zhi; Liu, Xinyu; Redwing, Joan M.

    2014-08-01

    In case of the n-type rear-emitter solar cell (n-RESC), wafer thickness scaling down has been studied and simulated under different bulk lifetimes (τbulk). The effect of minority-carrier lifetime of bulk τbulk on photovoltaic properties has been studied by using a symmetrical front-and-rear electrode structure, followed by a discussion of the physical mechanism. Simulation results show that by decreasing the wafer thickness, high energy-conversion efficiency can be achieved, even though a low bulk lifetime substrate is used, suggesting a cost-effective way to manufacture the high efficiency n-RESC. In addition, emitter saturation current density (Joe) of the n-RESC has also been extracted.

  3. Wafer-scale fabrication of transistors using CVD-grown graphene and its application to inverter circuit

    NASA Astrophysics Data System (ADS)

    Nakaharai, Shu; Iijima, Tomohiko; Ogawa, Shinichi; Yagi, Katsunori; Harada, Naoki; Hayashi, Kenjiro; Kondo, Daiyu; Takahashi, Makoto; Li, Songlin; Tsukagoshi, Kazuhito; Sato, Shintaro; Yokoyama, Naoki

    2015-04-01

    Graphene transistors were fabricated by a wafer-scale “top-down” process using a graphene sheet formed by the chemical vapor deposition (CVD) method. The devices have a dual-gated structure with an ion-irradiated channel, in which transistor polarity can be electrostatically controlled. We demonstrated, at room temperature, an on/off operation of current and electrostatic control of transistor polarity. By combining two dual-gated transistors, a six-terminal device was fabricated with three top gates and two ion-irradiated channels. In this device, we demonstrated an inverter operation.

  4. Wafer scale fabrication of porous three-dimensional plasmonic metamaterials for the visible region: chiral and beyond

    NASA Astrophysics Data System (ADS)

    Singh, Johnson Haobijam; Nair, Greshma; Ghosh, Arijit; Ghosh, Ambarish

    2013-07-01

    We report on a wafer scale fabrication method of a three-dimensional plasmonic metamaterial with strong chiroptical response in the visible region of the electromagnetic spectrum. The system was comprised of metallic nanoparticles arranged in a helical fashion, with high degree of flexibility over the choice of the underlying material, as well as their geometrical parameters. This resulted in exquisite control over the chiroptical properties, most importantly the spectral signature of the circular dichroism. In spite of the large variability in the arrangement, as well as the size and shape of the constituent nanoparticles, the average chiro-optical response of the material remained uniform across the wafer, thus confirming the suitability of this system as a large area chiral metamaterial. By simply heating the substrate for a few minutes, the geometrical properties of the nanoparticles could be altered, thus providing an additional handle towards tailoring the spectral response of this novel material.We report on a wafer scale fabrication method of a three-dimensional plasmonic metamaterial with strong chiroptical response in the visible region of the electromagnetic spectrum. The system was comprised of metallic nanoparticles arranged in a helical fashion, with high degree of flexibility over the choice of the underlying material, as well as their geometrical parameters. This resulted in exquisite control over the chiroptical properties, most importantly the spectral signature of the circular dichroism. In spite of the large variability in the arrangement, as well as the size and shape of the constituent nanoparticles, the average chiro-optical response of the material remained uniform across the wafer, thus confirming the suitability of this system as a large area chiral metamaterial. By simply heating the substrate for a few minutes, the geometrical properties of the nanoparticles could be altered, thus providing an additional handle towards tailoring the spectral response of this novel material. Electronic supplementary information (ESI) available: Experimental procedure (fabrication and characterization); effect of linear dichroism; chiroptical response for isotropic collection of helices; details of the computational model; thickness dependent red shift. See DOI: 10.1039/c3nr02666c

  5. Stationary Optical Concentrator Designs and Wafer Scale Monolithic Integration of Semiconductor Devices for Next Generation Photovoltaic Panels

    NASA Astrophysics Data System (ADS)

    Kim, Jung Min

    A major barrier in utilizing solar energy for large scale deployment is the cost of the photovoltaic (PV) systems. Several approaches have been used for the cost reduction such as by modifying PV system designs in addition to enhancing the efficiency of solar cells. Due to the high cost of materials, minimizing the use of solar cells such as in concentrator type systems is highly attractive for reducing the cost of the PV modules by focusing the incident light onto the PV cell. However concentrator PV systems (CPV) require constant tracking of the sun and hence are complex in design and expensive to operate, except in limited situations such as large scale PV power plants. It is desirable to design new concentrator type systems that do not require continuous tracking of the sun. These systems could ultimately reduce the PV system cost to a minimum while maximizing the power conversion efficiency. In this thesis we propose a simple design for a stationary concentrator photovoltaic (SCPV) system that could significantly reduce the cost of generating electricity using PV devices. Using optical ray tracing simulations, we have been able to design SCPV systems that could reduce the PV module cost by 2--10 times without compromising on the power conversion efficiency of the system. Another alternative approach for sustainable high efficiency PV system design is to develop low cost PV cells for terrestrial applications. To meet the demands of low cost and large scale production, larger and thinner (or flexible) substrates are required. We demonstrated the feasibility of fabricating monolithic interconnected PV devices at the wafer scale (2 inch wafers). In this study, GaSb PV cells grown on semi-insulating GaAs were used as the model material. Crucial device fabrication steps such as a selective etching process have been developed that is necessary for isolating individual devices on the wafer and interconnecting them with sub-micron scale accuracy. Selective etching of GaSb and GaAs has been developed for isolation of GaSb devices on semi-insulating GaAs substrates. Smooth side wall morphology and desirable depth profile of the etched structures have been accomplished using optimized etching conditions presented in this thesis. Device fabrication of series interconnected GaSb PV cells on a GaAs substrate with single-sided metal contacts has been successfully demonstrated.

  6. Wafer-Scale and Wrinkle-Free Epitaxial Growth of Single-Orientated Multilayer Hexagonal Boron Nitride on Sapphire.

    PubMed

    Jang, A-Rang; Hong, Seokmo; Hyun, Chohee; Yoon, Seong In; Kim, Gwangwoo; Jeong, Hu Young; Shin, Tae Joo; Park, Sung O; Wong, Kester; Kwak, Sang Kyu; Park, Noejung; Yu, Kwangnam; Choi, Eunjip; Mishchenko, Artem; Withers, Freddie; Novoselov, Kostya S; Lim, Hyunseob; Shin, Hyeon Suk

    2016-05-11

    Large-scale growth of high-quality hexagonal boron nitride has been a challenge in two-dimensional-material-based electronics. Herein, we present wafer-scale and wrinkle-free epitaxial growth of multilayer hexagonal boron nitride on a sapphire substrate by using high-temperature and low-pressure chemical vapor deposition. Microscopic and spectroscopic investigations and theoretical calculations reveal that synthesized hexagonal boron nitride has a single rotational orientation with AA' stacking order. A facile method for transferring hexagonal boron nitride onto other target substrates was developed, which provides the opportunity for using hexagonal boron nitride as a substrate in practical electronic circuits. A graphene field effect transistor fabricated on our hexagonal boron nitride sheets shows clear quantum oscillation and highly improved carrier mobility because the ultraflatness of the hexagonal boron nitride surface can reduce the substrate-induced degradation of the carrier mobility of two-dimensional materials. PMID:27120101

  7. Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

    NASA Astrophysics Data System (ADS)

    Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

    2014-02-01

    Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

  8. Wafer-scale, conformal and direct growth of MoS2 thin films by atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Jang, Yujin; Yeo, Seungmin; Lee, Han-Bo-Ram; Kim, Hyungjun; Kim, Soo-Hyun

    2016-03-01

    Molybdenum disulfide (MoS2) thin films were grown directly on SiO2 covered wafers by atomic layer deposition (ALD) at the deposition temperatures ranging from 175 to 225 °C using molybdenum hexacarbonyl [Mo(CO)6] and H2S plasma as the precursor and reactant, respectively. Self-limited film growth on the thermally-grown SiO2 substrate was observed with both the precursor and reactant pulsing time. The growth rate was ∼0.05 nm/cycle and a short incubation cycle of around 13 was observed at a deposition temperature of 175 °C. The MoS2 films formed nanocrystalline microstructure with a hexagonal crystal system (2H-MoS2), which was confirmed by X-ray diffraction and transmission electron microscopy. Single crystal MoS2 nanosheets, ∼20 nm in size, were fabricated by controlling the number of ALD cycles. The ALD-MoS2 thin films exhibited good stoichiometry with negligible C impurities, approximately 0.1 at.% from Rutherford backscattering spectrometry (RBS). X-ray photoelectron spectroscopy confirmed the formation of chemical bonding from MoS2. The step coverage of ALD-MoS2 was approximately 75% at a 100 nm sized trench. Overall, the ALD-MoS2 process made uniform deposition possible on the wafer-scale (4 in. in diameter).

  9. Room-temperature epitaxial electrodeposition of single-crystalline germanium nanowires at the wafer scale from an aqueous solution.

    PubMed

    Fahrenkrug, Eli; Gu, Junsi; Jeon, Sunyeol; Veneman, P Alexander; Goldman, Rachel S; Maldonado, Stephen

    2014-02-12

    Direct epitaxial growth of single-crystalline germanium (Ge) nanowires at room temperature has been performed through an electrodeposition process on conductive wafers immersed in an aqueous bath. The crystal growth is based on an electrochemical liquid-liquid-solid (ec-LLS) process involving the electroreduction of dissolved GeO2(aq) in water at isolated liquid gallium (Ga) nanodroplet electrodes resting on single-crystalline Ge or Si supports. Ge nanowires were electrodeposited on the wafer scale (>10 cm(2)) using only common glassware and a digital potentiostat. High-resolution electron micrographs and electron diffraction patterns collected from cross sections of individual substrate-nanowire contacts in addition to scanning electron micrographs of the orientation of nanowires across entire films on substrates with different crystalline orientations, supported the notion of epitaxial nanowire growth. Energy dispersive spectroscopic elemental mapping of single nanowires indicated the Ga(l) nanodroplet remains affixed to the tip of the growing nanowire throughout the nanowire electrodeposition process. Current-voltage responses measured across many individual nanowires yielded reproducible resistance values. The presented data cumulatively show epitaxial growth of covalent group IV nanowires is possible from the reduction of a dissolved oxide under purely benchtop conditions. PMID:24417670

  10. Highly Transparent Wafer-Scale Synthesis of Crystalline WS2 Nanoparticle Thin Film for Photodetector and Humidity-Sensing Applications.

    PubMed

    Pawbake, Amit S; Waykar, Ravindra G; Late, Dattatray J; Jadkar, Sandesh R

    2016-02-10

    In the present investigation, we report a one-step synthesis method of wafer-scale highly crystalline tungsten disulfide (WS2) nanoparticle thin film by using a modified hot wire chemical vapor deposition (HW-CVD) technique. The average size of WS2 nanoparticle is found to be 25-40 nm over an entire 4 in. wafer of quartz substrate. The low-angle XRD data of WS2 nanoparticle shows the highly crystalline nature of sample along with orientation (002) direction. Furthermore, Raman spectroscopy shows two prominent phonon vibration modes of E(1)2g and A1g at ∼356 and ∼420 cm(-1), respectively, indicating high purity of material. The TEM analysis shows good crystalline quality of sample. The synthesized WS2 nanoparticle thin film based device shows good response to humidity and good photosensitivity along with good long-term stability of the device. It was found that the resistance of the films decreases with increasing relative humidity (RH). The maximum humidity sensitivity of 469% along with response time of ∼12 s and recovery time of ∼13 s were observed for the WS2 thin film humidity sensor device. In the case of photodetection, the response time of ∼51 s and recovery time of ∼88 s were observed with sensitivity ∼137% under white light illumination. Our results open up several avenues to grow other transition metal dichalcogenide nanoparticle thin film for large-area nanoelectronics as well as industrial applications. PMID:26771049

  11. Modeling electrodeposition for LIGA microdevice fabrication

    SciTech Connect

    Griffiths, S.K.; Nilson, R.H.; Bradshaw, R.W.

    1998-02-01

    To better understand and to help optimize the electroforming portion of the LIGA process, we have developed one and two-dimensional numerical models describing electrode-position of metal into high aspect-ratio molds. The one-dimensional model addresses dissociation, diffusion, electromigration, and deposition of multiple ion species. The two-dimensional model is limited to a single species, but includes transport induced by forced flow of electrolyte outside the mold and by buoyancy associated with metal ion depletion within the mold. To guide model development and to validate these models, we have also conducted a series of laboratory experiments using a sulfamate bath to deposit nickel in cylindrical molds having aspect ratios up to twenty-five. The experimental results indicate that current densities well in excess of the diffusion-limited currents may still yield metal deposits of acceptable morphology. However, the numerical models demonstrate that such large ion fluxes cannot be sustained by convection within the mold resulting from flow across the mold top. Instead, calculations suggest that the observed enhancement of transport probably results from natural convection within the molds, and that buoyancy-driven flows may be critical to metal ion transport even in micron-scale features having very large aspect ratios. Taking advantage of this enhanced ion transport may allow order-of-magnitude reductions in electroforming times for LIGA microdevice fabrication. 42 refs., 14 figs., 1 tab.

  12. C- and L-band erbium-doped waveguide lasers with wafer-scale silicon nitride cavities.

    PubMed

    Purnawirman; Sun, J; Adam, T N; Leake, G; Coolbaugh, D; Bradley, J D B; Shah Hosseini, E; Watts, M R

    2013-06-01

    We report on integrated erbium-doped waveguide lasers designed for silicon photonic systems. The distributed Bragg reflector laser cavities consist of silicon nitride waveguide and grating features defined by wafer-scale immersion lithography and a top erbium-doped aluminum oxide layer deposited as the final step in the fabrication process. The resulting inverted ridge waveguide yields high optical intensity overlap with the active medium for both the 0.98 μm pump (89%) and 1.5 μm laser (87%) wavelengths with a pump-laser intensity overlap of >93%. We obtain output powers of up to 5 mW and show lasing at widely spaced wavelengths within both the C and L bands of the erbium gain spectrum (1536, 1561, and 1596 nm). PMID:23862218

  13. 12-inch-wafer-scale CMOS active-pixel sensor for digital mammography

    NASA Astrophysics Data System (ADS)

    Heo, Sung Kyn; Kosonen, Jari; Hwang, Sung Ha; Kim, Tae Woo; Yun, Seungman; Kim, Ho Kyung

    2011-03-01

    This paper describes the development of an active-pixel sensor (APS) panel, which has a field-of-view of 23.1×17.1 cm and features 70-μm-sized pixels arranged in a 3300×2442 array format, for digital mammographic applications. The APS panel was realized on 12-inch wafers based on the standard complementary metal-oxide-semiconductor (CMOS) technology without physical tiling processes of several small-area sensor arrays. Electrical performance of the developed panel is described in terms of dark current, full-well capacity and leakage current map. For mammographic imaging, the optimized CsI:Tl scintillator is experimentally determined by being combined with the developed panel and analyzing im aging characteristics, such as modulation-transfer function, noise-power spectrum, detective quantum efficiency, image l ag, and contrast-detail analysis by using the CDMAM 3.4 phantom. With these results, we suggest that the developed CMOS-based detector can be used for conventional and advanced digital mammographic applications.

  14. Wafer-scale single-domain-like graphene by defect-selective atomic layer deposition of hexagonal ZnO

    NASA Astrophysics Data System (ADS)

    Park, Kyung Sun; Kim, Sejoon; Kim, Hongbum; Kwon, Deokhyeon; Koo Lee, Yong-Eun; Min, Sung-Wook; Im, Seongil; Choi, Hyoung Joon; Lim, Seulky; Shin, Hyunjung; Koo, Sang Man; Sung, Myung Mo

    2015-10-01

    Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity.Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr05392g

  15. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

    PubMed Central

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-01-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

  16. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

    NASA Astrophysics Data System (ADS)

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-02-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

  17. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors.

    PubMed

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-01-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

  18. Wafer-scale single-domain-like graphene by defect-selective atomic layer deposition of hexagonal ZnO.

    PubMed

    Park, Kyung Sun; Kim, Sejoon; Kim, Hongbum; Kwon, Deokhyeon; Lee, Yong-Eun Koo; Min, Sung-Wook; Im, Seongil; Choi, Hyoung Joon; Lim, Seulky; Shin, Hyunjung; Koo, Sang Man; Sung, Myung Mo

    2015-11-14

    Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity. PMID:26452020

  19. Wafer-scale fabrication of self-actuated piezoelectric nanoelectromechanical resonators based on lead zirconate titanate (PZT)

    NASA Astrophysics Data System (ADS)

    Dezest, D.; Thomas, O.; Mathieu, F.; Mazenq, L.; Soyer, C.; Costecalde, J.; Remiens, D.; Deü, J. F.; Nicu, L.

    2015-03-01

    In this paper we report an unprecedented level of integration of self-actuated nanoelectromechanical system (NEMS) resonators based on a 150 nm thick lead zirconate titanate (PZT) thin film at the wafer-scale. A top-down approach combining ultraviolet (UV) lithography with other standard planar processing technologies allows us to achieve high-throughput manufacturing. Multilayer stack cantilevers with different geometries have been implemented with measured fundamental resonant frequencies in the megahertz range and Q-factor values ranging from ~130 in air up to ~900 in a vacuum at room temperature. A refined finite element model taking into account the exact configuration of the piezoelectric stack is proposed and demonstrates the importance of considering the dependence of the beam’s cross-section upon the axial coordinate. We extensively investigate both experimentally and theoretically the transduction efficiency of the implemented piezoelectric layer and report for the first time at this integration level a piezoelectric constant of {{d}31}=15  fm V-1. Finally, we discuss the current limitations to achieve piezoelectric detection.

  20. Wafer-scale graphene/ferroelectric hybrid devices for low-voltage electronics

    NASA Astrophysics Data System (ADS)

    Zheng, Yi; Ni, Guang-Xin; Bae, Sukang; Cong, Chun-Xiao; Kahya, Orhan; Toh, Chee-Tat; Kim, Hye Ri; Im, Danho; Yu, Ting; Ahn, Jong Hyun; Hong, Byung Hee; Özyilmaz, Barbaros

    2011-01-01

    Preparing graphene and its derivatives on functional substrates may open enormous opportunities for exploring the intrinsic electronic properties and new functionalities of graphene. However, efforts in replacing SiO2 have been greatly hampered by a very low sample yield of the exfoliation and related transferring methods. Here, we report a new route in exploring new graphene physics and functionalities by transferring large-scale chemical-vapor deposition single-layer and bilayer graphene to functional substrates. Using ferroelectric Pb(Zr0.3Ti0.7)O3 (PZT), we demonstrate ultra-low-voltage operation of graphene field effect transistors within ±1 V with maximum doping exceeding 1013 cm- 2 and on-off ratios larger than 10 times. After polarizing PZT, switching of graphene field effect transistors are characterized by pronounced resistance hysteresis, suitable for ultra-fast non-volatile electronics.

  1. Wafer-scale synthesis of thickness-controllable MoS2 films via solution-processing using a dimethylformamide/n-butylamine/2-aminoethanol solvent system

    NASA Astrophysics Data System (ADS)

    Yang, Jaehyun; Gu, Yeahyun; Lee, Eunha; Lee, Hyangsook; Park, Sang Han; Cho, Mann-Ho; Kim, Yong Ho; Kim, Yong-Hoon; Kim, Hyoungsub

    2015-05-01

    The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates.The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates. Electronic supplementary information (ESI) available: Optical microscopy image of the spin-coated film, thermogravimetric data of the spin-coating solution, Raman spectra after first- and second-annealing, and AFM images of selected MoS2 films. See DOI: 10.1039/c5nr01486g

  2. Miniature Inchworm Actuators Fabricated by Use of LIGA

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok

    2003-01-01

    Miniature inchworm actuators that would have relatively simple designs have been proposed for applications in which there are requirements for displacements of the order of microns or tens of microns and for the ability to hold their positions when electric power is not applied. The proposed actuators would be members of the class of microelectromechanical systems (MEMS), but would be designed and fabricated following an approach that is somewhat unusual for MEMS. Like other MEMS actuators, the proposed inchworm actuators could utilize thermoplastic, bimetallic, shape-memory-alloy, or piezoelectric actuation principles. The figure depicts a piezoelectric inchworm actuator according to the proposal. As in other inchworm actuators, linear motion of an extensible member would be achieved by lengthening and shortening the extensible member in synchronism with alternately clamping and releasing one and then the other end of the member. In this case, the moving member would be the middle one; the member would be piezoelectric and would be shortened by applying a voltage to it. The two outer members would also be piezoelectric; the release of the clamps on the upper or lower end would be achieved by applying a voltage to the electrodes on the upper or lower ends, respectively, of these members. Usually, MEMS actuators cannot be fabricated directly on the side walls of silicon wafers, yet the geometry of this actuator necessitates such fabrication. The solution, according to the proposal, would be to use the microfabrication technique known by the German acronym LIGA - "lithographie, galvanoformung, abformung," which means lithography, electroforming, molding. LIGA involves x-ray lithography of a polymer film followed by selective removal of material to form a three-dimensional pattern from which a mold is made. Among the advantages of LIGA for this purpose are that it is applicable to a broad range of materials, can be used to implement a variety of designs, including those of structures >1 mm high, affords submicron precision, and is amenable to mass production at relatively low unit cost. Fabrication of the proposed actuators would involve some technological risks - in particular, in the integration of electrode connection lines and placement of actuator elements. It will also be necessary to perform an intensive study of the feasibility of growing piezoelectric crystals onto LIGA molds.

  3. Slip, Crystal Orientation, and Damage Evolution During Thermal Cycling in High-Strain Wafer-Level Chip-Scale Packages

    NASA Astrophysics Data System (ADS)

    Zhou, Bite; Zhou, Quan; Bieler, Thomas R.; Lee, Tae-kyu

    2015-03-01

    Wafer-level chip-scale package samples with pre-cross-sectioned edge rows were thermally cycled to study microstructure evolution and damage development. Electron backscattered diffraction (EBSD) and high-energy x-ray diffraction were used to obtain Sn grain orientations and the average coefficient of thermal expansion normal to the board in every joint of the package for samples in the as-fabricated and thermally cycled conditions. The results indicated a near-random distribution of joint orientation. Optical, scanning electron microscopy, and EBSD methods were used to characterize microstructure changes in pre-cross-sectioned samples due to thermal cycling. Slip trace analysis and Orientation Imaging Microscopy™ (OIM) show that slip systems with high Schmid factors (estimated global shear stress based on the package neutral point) are responsible for the observed microstructure evolution during thermal cycling, which provides information about slip systems that are more easily activated. Two joints were analyzed in detail to evaluate slip activity at different stages of their thermal history. The first case showed that a solidification twin grain boundary misorientation deviated from the twin relationship due to slip activity during thermal cycling, which can influence damage development and the path of crack propagation. The second case showed a new grain orientation developing due to gradual lattice rotation about the Sn [110] axis by a continuous recrystallization mechanism. This rotation was correlated with the operation of slip system . Small tin whiskers emerged from the initially polished chip interface and grew with increasing thermal cycles until a crack developed in the solder that relieved the stress. As the local stresses are not known experimentally, this analysis provides observations that can be compared with a crystal plasticity model simulation.

  4. MUSE - a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer-scale integration. Technical report

    SciTech Connect

    Rader, C.M.; Allen, D.L.; gLASCO , D.B.; Woodward, C.E.

    1990-05-18

    This report describes an architecture for a highly parallel system of computational processors specialized for real-time adaptive antenna nulling computations with many degrees of freedom, which we call MUSE (Matrix Update Systolic Experiment), and a specific realization of MUSE for 64 degrees of freedom. Each processor uses the CORDIC algorithm and has been designed as a single integrated circuit. Ninety-six such processors working together can update the 64-element nulling weights based on 300 new observations in only 6.7 milliseconds. This is equivalent to 2.88 Giga-ops for a conventional processor. The computations are accurate enough to support 50 decibel of signal-to-noise improvement in a sidelobe canceller. The connectivity between processors is quite simple and permits MUSE to be realized on a single large wafer, using restructurable VLSI (Very Large Scale Integration). The complete design of such a wafer is described.

  5. Laparoscopic Splenectomy Using LigaSure

    PubMed Central

    Kindy, Nayil Al; Chopra, Pradeep J.

    2010-01-01

    Background: Laparoscopic splenectomy (LS) has become the standard approach for most splenectomy cases. Bleeding is the main complication and cause for conversion. We present our experience with the LigaSure and discuss its advantage as a vessel sealing system in achieving safe vascular control. Method: Over a 3-year period, we performed 12 consecutive LS using LigaSure at a single center. A literature review of all the patients who had undergone laparoscopic splenectomy with of the LigaSure to achieve vascular control at the hilum was carried out, assessing its advantages and outcome. Results: Twelve LS were performed. Eleven of these patients had ITP, and one patient had sickle cell disease. The mean blood loss was 70mL (range, 50 to 460), and operating time was 126 minutes (range, 110 to 240). Two postoperative complications occurred: portal vein thrombosis in one case and subphrenic collection in the other. The literature review revealed 8 studies with 231 cases in which the LigaSure was used to perform laparoscopic splenectomy. A significant reduction in operating time (average 102 minutes) and intraabdominal blood loss (66mL) was observed with the LigaSure compared with endostaplers. Conclusion: The use of LigaSure and the semilateral position results in a gain of time and safety in addition to low intraoperative bleeding, need for transfusion, minimal complications and a low conversion rate. PMID:21605520

  6. Imaging ATUM ultrathin section libraries with WaferMapper: a multi-scale approach to EM reconstruction of neural circuits.

    PubMed

    Hayworth, Kenneth J; Morgan, Josh L; Schalek, Richard; Berger, Daniel R; Hildebrand, David G C; Lichtman, Jeff W

    2014-01-01

    The automated tape-collecting ultramicrotome (ATUM) makes it possible to collect large numbers of ultrathin sections quickly-the equivalent of a petabyte of high resolution images each day. However, even high throughput image acquisition strategies generate images far more slowly (at present ~1 terabyte per day). We therefore developed WaferMapper, a software package that takes a multi-resolution approach to mapping and imaging select regions within a library of ultrathin sections. This automated method selects and directs imaging of corresponding regions within each section of an ultrathin section library (UTSL) that may contain many thousands of sections. Using WaferMapper, it is possible to map thousands of tissue sections at low resolution and target multiple points of interest for high resolution imaging based on anatomical landmarks. The program can also be used to expand previously imaged regions, acquire data under different imaging conditions, or re-image after additional tissue treatments. PMID:25018701

  7. Imaging ATUM ultrathin section libraries with WaferMapper: a multi-scale approach to EM reconstruction of neural circuits

    PubMed Central

    Hayworth, Kenneth J.; Morgan, Josh L.; Schalek, Richard; Berger, Daniel R.; Hildebrand, David G. C.; Lichtman, Jeff W.

    2014-01-01

    The automated tape-collecting ultramicrotome (ATUM) makes it possible to collect large numbers of ultrathin sections quickly—the equivalent of a petabyte of high resolution images each day. However, even high throughput image acquisition strategies generate images far more slowly (at present ~1 terabyte per day). We therefore developed WaferMapper, a software package that takes a multi-resolution approach to mapping and imaging select regions within a library of ultrathin sections. This automated method selects and directs imaging of corresponding regions within each section of an ultrathin section library (UTSL) that may contain many thousands of sections. Using WaferMapper, it is possible to map thousands of tissue sections at low resolution and target multiple points of interest for high resolution imaging based on anatomical landmarks. The program can also be used to expand previously imaged regions, acquire data under different imaging conditions, or re-image after additional tissue treatments. PMID:25018701

  8. Optimization and scale-down of wafer-based resist strip and rinse processes for photomask production

    NASA Astrophysics Data System (ADS)

    Aggus, Brant L.; Weaver, Gene

    2002-03-01

    Retrofitting of wafer processing equipment is a common scenario in the photomask industry, as most available tools are built to accommodate the high throughput and substrate size of wafers. The acid process tanks in use at most mask shops are built to suit a single rack of 25 8 inch wafers, each coated with roughly two microns of photoresist. Conversely, a typical photomask shop sends one to two masks at a time through the resist strip line, each coated with 4500 angstroms of resist. The amount of unused volume of active chemical within an 8 inch X 8.5 inch X 10 inch acid tank when it is dumped is enough to warrant a hardware change. Experimentation has shown that it is possible to decrease Piranha usage by 43 percent by optimizing tank size for photomasks. The same logic applies to quick dump rinsers (QDRs). Additionally, water is wasted with 'spray down' processes, whereby masks are sprayed via perforated bars or nozzles. Because a < 0.5 μm viscous sublayer can not be practically achieved through spraying the mask, better cleaning performance is obtained with a bottom-filled weiring process. This is demonstrated through experimental results and theoretical mass transfer models.

  9. Laser wafering for silicon solar.

    SciTech Connect

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  10. Wafer-scale pixelated scintillator and specially designed data acquisition system for fiber optic taper array-coupled digital x-ray detector

    NASA Astrophysics Data System (ADS)

    Zhao, Zhigang; Li, Ji; Lei, Yaohu; Wang, Ru; Ren, Jianping; Qiao, Jian; Niu, Hanben

    2015-09-01

    A digital x-ray detector scheme based on a pixelated scintillator coupled with a fiber optic (FOT) array is suitable for many high-resolution x-ray imaging applications. However, certain challenges need to be addressed for fabrication of wafer-scale uniform pixelated x-ray scintillators. In addition, difficulties associated with implementation of the data acquisition system for acquiring output image data from the multiple image sensors used in the detector also need to be addressed. In this paper, a 2×2 FOT array-coupled digital x-ray detector scheme using a 5-in. pixelated scintillator is proposed. A novel fabrication setup along with the corresponding processes for fabricating the wafer-scale pixelated scintillator and implementation of a specially designed embedded data acquisition system based on a single embedded micro-processer (ARM) and four field-programmable gate array (FPGA) chips are discussed in detail. Preliminary experiments demonstrate that this pixelated scintillator-based digital x-ray detector scheme with an active imaging area of about 100 mm×100 mm shows considerable potential for use in high-resolution x-ray imaging.

  11. Large-area, wafer-scale epitaxial growth of germanium on silicon and integration of high-performance transistors

    NASA Astrophysics Data System (ADS)

    Ghosh, Swapnadip

    Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the ˜105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress simulation shows that the oval air gaps around the SiO2 template can reduce the thermal stress by 50% and help reduce the DD. We have then compared the structural and electrical characteristics of n-type Ge films with its p-type counter parts. In n-type Ge, the DD decreases from ˜109cm-2 near the Ge-Si interface to ˜105 cm-2 at the film surface. In contrast, we observe 5x107 cm-2 TDD at the film surface in p-type Ge. The full width at half-maximum for our n-type Ge(004) XRD peak is ~70% narrower than that of p-type Ge. As a stringent test of the dislocation reduction, we have also fabricated and characterized high-carrier-mobility MOSFETs on GoS substrates. We also report p- and n-MOSFETs with microeff of 401 and 940 cm2/V-s and a subthreshold slope of 100 and 200 mV/decade, respectively. These effective mobilities show an exceptional 82 and 30% improvement over that of conventional Si channel MOSFETs. We also investigate the optical quality of ultra-low DD GoS film by measuring photoluminescence (PL). The n-type Ge PL main peak shows pronounced tensile-strain (x0.8%) than that of p-type which is an indicator of direct BG shrinking at the \\Gcy band-edge. Going beyond epitaxial engineering and device fabrication, we have also recently demonstrated a scalable path to create a 2D array of Ge quantum dots (QDs) on responsive SiGe substrates based on elastic mechanical deformation and subsequent SiGe compositional redistribution, coupled with MBE growth. For large-scale manufacturing of single-electron transistors, we have also demonstrated that a spatially structured elastic compressive stress to the SiGe substrate with thermally annealing leads to a compositional redistribution of Si and Ge in the near-surface region of SiGe substrates, forming a 2D array of Ge-depleted nanoscale regions. Based on these latest findings, we have also begun to chart a future direction for my research group, where one can explore new advanced device architectures, such as Si-compatible, optically actuated, Ge-quantum dot-based field effect transistors.

  12. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  13. Optical measurement of LIGA milliengine performance

    SciTech Connect

    Dickey, F.M.; Holswade, S.C.; Christenson, T.R.; Garcia, E.J.; Polosky, M.A.

    1997-12-31

    Understanding the parameters that affect the performance of milliscale and microscale actuators is essential to the development of optimized designs and fabrication processes, as well as the qualification of devices for commercial applications. This paper discusses the development of optical techniques for motion measurements of LIGA fabricated milliengines. LIGA processing permits the fabrication of precision millimeter-sized machine elements that cannot be fabricated by conventional miniature machining techniques because of their small feature sizes. In addition, tolerances of 1 part in 10{sup 3} to 10{sup 4} may be maintained in millimeter sized components with this processing technique. Optical techniques offer a convenient means for measuring long term statistical performance data and transient responses needed to optimize designs and manufacturing techniques. Optical techniques can also be used to provide feedback signals needed for control and sensing of the state of the machine. Optical probe concepts and experimental data obtained using a milliengine developed at Sandia National Laboratories are presented.

  14. High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth.

    PubMed

    Miao, Xin; Chabak, Kelson; Zhang, Chen; Mohseni, Parsian K; Walker, Dennis; Li, Xiuling

    2015-05-13

    Wafer-scale defect-free planar III-V nanowire (NW) arrays with ∼100% yield and precisely defined positions are realized via a patterned vapor-liquid-solid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 10(4), 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 × 1.5 cm(2) chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics. PMID:25494481

  15. Injection molding of LIGA and LIGA-similar microstructures using filled and unfilled thermoplastics

    NASA Astrophysics Data System (ADS)

    Ruprecht, Robert; Bacher, Walter; Hausselt, Juergen H.; Piotter, Volker

    1995-09-01

    Micromolding is a key technology for the economic production of micro-components for microsystems. It is applied in several microstructuring techniques including the LIGA process which was invented and developed at Forschungszentrum Karlsruhe. Injection molding of multiple-use LIGA tool inserts produced by deep-etch x-ray lithography and electroforming allows the economic production of components for most applications using microsystems technology. Such microstructures are produced in small and large series and commercialized by Forschungszentrum Karlsruhe and the microParts Company, Dormund, Germany, cooperating within the framework of a license agreement. Special molding machines are applied for the production of single- or multi-stepped microstructures of a few micrometers in lateral dimension and structural details in the submicrometer range. Maximum aspect ratios of several ten up to 600 are achieved. In contrast to compact disc production, the machines are equipped with a special control unit, by means of which tool temperature is often kept above the melting temperatures of the plastics processed during injection. Evacuation of the tool cavity is required for the complete filling of the microstructurized nest area of the mold. Cycle time is mainly determined by the heating and cooling of the whole molding tool. Recently, novel techniques were developed for the production of ceramic LIGA or LIGA-similar microstructures at Forschungszentrum Karlsruhe, where further development of the LIGA technique has been performed for more than a decade. Using lost plastic microstructures and sometimes even metal tools, microstructures are made of structural (e.g., aluminum oxide, zirconium oxide) and functional ceramics (e.g., PZT). Current development activities are aimed at producing lost plastic molds for metal microstructures by injection molding. Molding tests with conductively filled thermoplastics have been carried out to manufacture lost molds for e.g. spin nozzles.

  16. Wafer-scale monolayer MoS2 grown by chemical vapor deposition using a reaction of MoO3 and H2S

    NASA Astrophysics Data System (ADS)

    Kim, Youngchan; Bark, Hunyoung; Ryu, Gyeong Hee; Lee, Zonghoon; Lee, Changgu

    2016-05-01

    Monolayer MoS2 nanosheets are potentially useful in optoelectronics, photoelectronics, and nanoelectronics due to their flexibility, mechanical strength, and direct band gap of 1.89 eV. Experimentalists have studied the synthesis of MoS2 using chemical vapor deposition (CVD) methods in an effort to fabricate wafer-scale nanofilms with a high uniformity and continuity for practical electronic applications. In this work, we applied the CVD method to a reaction of MoO3 powder and H2S gas to grow high-quality polycrystalline monolayer MoS2 sheets with unprecedented uniformity over an area of several centimeters. The monolayer MoS2 was characterized using Raman spectroscopy, photoluminescence (PL) spectroscopy, atomic force microscopy (AFM), x-ray photoemission spectroscopy (XPS), and transmission electron microscopy (TEM). The top-gate field-effect transistor prepared with a 30 nm HfO2 capping layer displayed an electrical mobility of 1 cm2 v‑1 s‑1 and an I on/off of ~105. This method paves the way for the development of practical devices with MoS2 monolayers and advances fundamental research.

  17. Wafer-scale monolayer MoS2 grown by chemical vapor deposition using a reaction of MoO3 and H2S.

    PubMed

    Kim, Youngchan; Bark, Hunyoung; Ryu, Gyeong Hee; Lee, Zonghoon; Lee, Changgu

    2016-05-11

    Monolayer MoS2 nanosheets are potentially useful in optoelectronics, photoelectronics, and nanoelectronics due to their flexibility, mechanical strength, and direct band gap of 1.89 eV. Experimentalists have studied the synthesis of MoS2 using chemical vapor deposition (CVD) methods in an effort to fabricate wafer-scale nanofilms with a high uniformity and continuity for practical electronic applications. In this work, we applied the CVD method to a reaction of MoO3 powder and H2S gas to grow high-quality polycrystalline monolayer MoS2 sheets with unprecedented uniformity over an area of several centimeters. The monolayer MoS2 was characterized using Raman spectroscopy, photoluminescence (PL) spectroscopy, atomic force microscopy (AFM), x-ray photoemission spectroscopy (XPS), and transmission electron microscopy (TEM). The top-gate field-effect transistor prepared with a 30 nm HfO2 capping layer displayed an electrical mobility of 1 cm(2) v(-1) s(-1) and an I on/off of ~10(5). This method paves the way for the development of practical devices with MoS2 monolayers and advances fundamental research. PMID:27058779

  18. Final-part metrology for LIGA springs, Build Group 1.

    SciTech Connect

    Aigeldinger, Georg; Skala, Dawn M.; Ceremuga, Joseph T.; Mills, Bernice E.

    2004-03-01

    The LIGA spring is a recently designed part for defense program applications. The Sandia California LIGA team has produced an initial group build of these nickel alloy parts. These are distinctive in having a macroscopic lateral size of about 1 cm, while requiring microscopic dimensional precision on the order of a few micrometers. LIGA technology capabilities at Sandia are able to manufacture such precise structures. While certain aspects of the LIGA process and its production capabilities have been dimensionally characterized in the past, [1-6] the present work is exclusive in defining a set of methods and techniques to inspect and measure final LIGA nickel alloy parts in large prototype quantities. One hundred percent inspection, meaning that every single LIGA part produced needs to be measured, ensures quality control and customer satisfaction in this prototype production run. After a general visual inspection of the parts and an x-ray check for voids, high precision dimensional metrology tools are employed. The acquired data is analyzed using both in house and commercially available software. Examples of measurements illustrating these new metrology capabilities are presented throughout the report. These examples furthermore emphasize that thorough inspection of every final part is not only essential to characterize but also improve the LIGA manufacturing process.

  19. Micro-grippers for assembly of LIGA parts

    SciTech Connect

    Feddema, J.; Polosky, M.; Christenson, T.; Spletzer, B.; Simon, R.

    1997-12-31

    This paper describes ongoing testing of two microgrippers for assembly of LIGA (Lithographie Galvanoformung Abformung) parts. The goal is to place 100 micron outside diameter (OD) LIGA gears with a 50 micron inner diameter hole onto pins ranging from 35 to 49 microns. The first micro gripper is a vacuum gripper made of a 100 micron OD stainless steel tube. The second micro gripper is a set of tweezers fabricated using the LIGA process. Nickel, Permalloy, and copper materials are tested. The tweezers are actuated by a collet mechanism which is closed by a DC linear motor.

  20. Contrastive study on the mechanical performance of MEMS microsprings fabricated by LIGA and UV-LIGA technology

    NASA Astrophysics Data System (ADS)

    Li, Hua; Shi, Gengchen

    2008-03-01

    With good mechanical performance and mature fabrication technology of LIGA and UV-LIGA, Ni is chosen as the material of S style MEMS microspring. At 24°C and 25% relative humidity, five different points in LIGA Ni sample were tested with the MICRO HARDNESS TESTER, and the Young's modulus was 219GPa. From the tensile tests of UV-LIGA Ni sample the Young's modulus of UV-LIGA Ni is 180GPa. The S style microspring was fabricated by LIGA and UV-LIGA technology separately. Applying the Castigliano second theorem of energy method in macro theory, the spring constant formulas of S style microspring in three application modes were deduced, and the correctness was verified by the FEA (Finite Element Analysis) simulation. The experiments of S style microspring's deformation properties were carried out by the Tytron250 micro force test machine and a tensile measurement system separately. The experimental results agree with the theoretical analysis. Based on the above analysis, the change laws of microspring's spring coefficient in different application patters are summarized.

  1. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    PubMed

    Zhao, C; Konstantinidis, A C; Zheng, Y; Anaxagoras, T; Speller, R D; Kanicki, J

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm(-1) and a DQE of around 0.5 at spatial frequencies  <1 mm(-1). In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered. PMID:26540090

  2. Microstructural Evolution of SAC305 Solder Joints in Wafer Level Chip-Scale Packaging (WLCSP) with Continuous and Interrupted Accelerated Thermal Cycling

    NASA Astrophysics Data System (ADS)

    Zhou, Quan; Zhou, Bite; Lee, Tae-Kyu; Bieler, Thomas

    2016-06-01

    Four high-strain design wafer level chip scale packages were given accelerated thermal cycling with a 10°C/min ramp rate and 10 min hold times between 0°C and 100°C to examine the effects of continuous and interrupted thermal cycling on the number of cycles to failure. The interruptions given two of the samples were the result of periodic examinations using electron backscattered pattern mapping, leading to room temperature aging of 30 days-2.5 years after increments of about 100 cycles at several stages of the cycling history. The continuous thermal cycling resulted in solder joints with a much larger degree of recrystallization, whereas the interrupted thermal cycling tests led to much less recrystallization, which was more localized near the package side, and the crack was more localized near the interface and had less branching. The failure mode for both conditions was still the same, with cracks nucleating along the high angle grain boundaries formed during recrystallization. In conditions where there were few recrystallized grains, recovery led to formation of subgrains that strengthened the solder, and the higher strength led to a larger driving force for crack growth through the solder, leading to failure after less than half of the cycles in the continuous accelerated thermal cycling condition. This work shows that there is a critical point where sufficient strain energy accumulation will trigger recrystallization, but this point depends on the rate of strain accumulation in each cycle and various recovery processes, which further depends on local crystal orientations, stress state evolution, and specific activated slip and twinning systems.

  3. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis

    NASA Astrophysics Data System (ADS)

    Zhao, C.; Konstantinidis, A. C.; Zheng, Y.; Anaxagoras, T.; Speller, R. D.; Kanicki, J.

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm-1 and a DQE of around 0.5 at spatial frequencies  <1 mm-1. In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered.

  4. Microstructural Evolution of SAC305 Solder Joints in Wafer Level Chip-Scale Packaging (WLCSP) with Continuous and Interrupted Accelerated Thermal Cycling

    NASA Astrophysics Data System (ADS)

    Zhou, Quan; Zhou, Bite; Lee, Tae-Kyu; Bieler, Thomas

    2016-02-01

    Four high-strain design wafer level chip scale packages were given accelerated thermal cycling with a 10°C/min ramp rate and 10 min hold times between 0°C and 100°C to examine the effects of continuous and interrupted thermal cycling on the number of cycles to failure. The interruptions given two of the samples were the result of periodic examinations using electron backscattered pattern mapping, leading to room temperature aging of 30 days-2.5 years after increments of about 100 cycles at several stages of the cycling history. The continuous thermal cycling resulted in solder joints with a much larger degree of recrystallization, whereas the interrupted thermal cycling tests led to much less recrystallization, which was more localized near the package side, and the crack was more localized near the interface and had less branching. The failure mode for both conditions was still the same, with cracks nucleating along the high angle grain boundaries formed during recrystallization. In conditions where there were few recrystallized grains, recovery led to formation of subgrains that strengthened the solder, and the higher strength led to a larger driving force for crack growth through the solder, leading to failure after less than half of the cycles in the continuous accelerated thermal cycling condition. This work shows that there is a critical point where sufficient strain energy accumulation will trigger recrystallization, but this point depends on the rate of strain accumulation in each cycle and various recovery processes, which further depends on local crystal orientations, stress state evolution, and specific activated slip and twinning systems.

  5. Cantilevered multilevel LIGA devices and methods

    DOEpatents

    Morales, Alfredo Martin; Domeier, Linda A.

    2002-01-01

    In the formation of multilevel LIGA microstructures, a preformed sheet of photoresist material, such as polymethylmethacrylate (PMMA) is patterned by exposure through a mask to radiation, such as X-rays, and developed using a developer to remove the exposed photoresist material. A first microstructure is then formed by electroplating metal into the areas from which the photoresist has been removed. Additional levels of microstructure are added to the initial microstructure by covering the first microstructure with a conductive polymer, machining the conductive polymer layer to reveal the surface of the first microstructure, sealing the conductive polymer and surface of the first microstructure with a metal layer, and then forming the second level of structure on top of the first level structure. In such a manner, multiple layers of microstructure can be built up to allow complex cantilevered microstructures to be formed.

  6. Wafer scale micromachine assembly method

    DOEpatents

    Christenson, Todd R.

    2001-01-01

    A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.

  7. Miniature Scroll Pumps Fabricated by LIGA

    NASA Technical Reports Server (NTRS)

    Wiberg, Dean; Shcheglov, Kirill; White, Victor; Bae, Sam

    2009-01-01

    Miniature scroll pumps have been proposed as roughing pumps (low - vacuum pumps) for miniature scientific instruments (e.g., portable mass spectrometers and gas analyzers) that depend on vacuum. The larger scroll pumps used as roughing pumps in some older vacuum systems are fabricated by conventional machining. Typically, such an older scroll pump includes (1) an electric motor with an eccentric shaft to generate orbital motion of a scroll and (2) conventional bearings to restrict the orbital motion to a circle. The proposed miniature scroll pumps would differ from the prior, larger ones in both design and fabrication. A miniature scroll pump would include two scrolls: one mounted on a stationary baseplate and one on a flexure stage (see figure). An electromagnetic actuator in the form of two pairs of voice coils in a push-pull configuration would make the flexure stage move in the desired circular orbit. The capacitance between the scrolls would be monitored to provide position (gap) feedback to a control system that would adjust the drive signals applied to the voice coils to maintain the circular orbit as needed for precise sealing of the scrolls. To minimize power consumption and maximize precision of control, the flexure stage would be driven at the frequency of its mechanical resonance. The miniaturization of these pumps would entail both operational and manufacturing tolerances of <1 m. Such tight tolerances cannot be achieved easily by conventional machining of high-aspect-ratio structures like those of scroll-pump components. In addition, the vibrations of conventional motors and ball bearings exceed these tight tolerances by an order of magnitude. Therefore, the proposed pumps would be fabricated by the microfabrication method known by the German acronym LIGA ( lithographie, galvanoformung, abformung, which means lithography, electroforming, molding) because LIGA has been shown to be capable of providing the required tolerances at large aspect ratios.

  8. Scriber for silicon wafers

    NASA Technical Reports Server (NTRS)

    Yamakawa, K. A.; Fortier, E. P. (Inventor)

    1981-01-01

    A device for dividing silicon wafers into rectangular chips is characterized by a base including a horizontally oriented bed with a planar support surface, a vacuum chuck adapted to capture a silicon wafer seated on the support for translation in mutually perpendicular directions. A stylus support mounted on the bed includes a shaft disposed above and extended across the bed and a truck mounted on the shaft and supported thereby for linear translation along a path extended across the bed a vertically oriented scribe has a diamond tip supported by the truck also adapted as to engage a silicon wafer captured by the chuck and positioned beneath it in order to form score lines in the surface of the wafer as linear translation is imparted to the truck. A chuck positioning means is mounted on the base and is connected to the chuck for positioning the chuck relative to the stylus.

  9. Wafer characteristics via reflectometry

    DOEpatents

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  10. Reciprocating Saw for Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.; Collins, E. R., Jr.

    1985-01-01

    Concept increases productivity and wafer quality. Cutting wafers from silicon ingots produces smooth wafers at high rates with reduced blade wear. Involves straight reciprocating saw blade and slight rotation of ingot between cutting strokes. Many parallel blades combined to cut many wafers simultaneously from ingot.

  11. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  12. Wafer level reliability testing: An idea whose time has come

    NASA Technical Reports Server (NTRS)

    Trapp, O. D.

    1987-01-01

    Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

  13. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  14. Modeling electrodeposition in LIGA microfabrication using an arbitrary-Lagrangian-Eulerian formulation for moving-boundary tracking with repeated re-meshing.

    SciTech Connect

    Chen, Ken Shuang

    2003-06-01

    Electrodeposition is a key process in LIGA (Lithographie, Galvanoformung, Abformung - German words for lithography, electroplating and molding) - microfabrication, which is increasingly demonstrated to be a viable technology for fabricating micro-devices or parts. LIGA Electrodeposition involves complex multi-physics phenomena: (1) diffusion, migration, and convection of charged species in a centimeter-scale electrolyte-bath region and in micron-scale featurecavity or trench regions; (2) homogeneous and heterogeneous electrochemical reactions; and (3) moving deposition surface or surfaces on which metal ions (e.g., {approx} i) are electrochemically reduced to form a pure metal or an alloy.

  15. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  16. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  17. Recent Developments in Microsystems Fabricated by the Liga-Technique

    NASA Technical Reports Server (NTRS)

    Schulz, J.; Bade, K.; El-Kholi, A.; Hein, H.; Mohr, J.

    1995-01-01

    As an example of microsystems fabricated by the LIGA-technique (x-ray lithography, electroplating and molding), three systems are described and characterized: a triaxial acceleration sensor system, a micro-optical switch, and a microsystem for the analysis of pollutants. The fabrication technologies are reviewed with respect to the key components of the three systems: an acceleration sensor, and electrostatic actuator, and a spectrometer made by the LIGA-technique. Aa micro-pump and micro-valve made by using micromachined tools for molding and optical fiber imaging are made possible by combining LIGA and anisotropic etching of silicon in a batch process. These examples show that the combination of technologies and components is the key to complex microsystems. The design of such microsystems will be facilitated is standardized interfaces are available.

  18. Etching Of Semiconductor Wafer Edges

    DOEpatents

    Kardauskas, Michael J.; Piwczyk, Bernhard P.

    2003-12-09

    A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

  19. Metallic nanowires by full wafer stencil lithography.

    PubMed

    Vazquez-Mena, O; Villanueva, G; Savu, V; Sidler, K; van den Boogaart, M A F; Brugger, J

    2008-11-01

    Aluminum and gold nanowires were fabricated using 100 mm stencil wafers containing nanoslits fabricated with a focused ion beam. The stencils were aligned and the nanowires deposited on a substrate with predefined electrical pads. The morphology and resistivity of the wires were studied. Nanowires down to 70 nm wide and 5 mum long have been achieved showing a resistivity of 10 microOmegacm for Al and 5 microOmegacm for Au and maximum current density of approximately 10(8) A/cm(2). This proves the capability of stencil lithography for the fabrication of metallic nanowires on a full wafer scale. PMID:18817451

  20. Torsion Testing of Diffusion Bonded LIGA Formed Nickel

    SciTech Connect

    Buchheit, T.E.; Christenson, T.R.; Schmale, D.T.

    1999-01-27

    A test technique has been devised which is suitable for the testing of the bond strength of batch diffusion bonded LIGA or DXRL defined structures. The method uses a torsion tester constructed with the aid of LIGA fabrication and distributed torsion specimens which also make use of the high aspect ratio nature of DXRL based processing. Measurements reveal achieved bond strengths of 130MPa between electroplated nickel with a bond temperature of 450 C at 7 ksi pressure which is a sufficiently low temperature to avoid mechanical strength degradation.

  1. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  2. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

  3. A LIGA Fabricated Quadrupole Array for Mass Spectroscopy

    NASA Technical Reports Server (NTRS)

    Jackson, K.; Wiberg, D. V.; Hecht, M. H.; Orient, O. J.; Chutjian, A.; Yee, K.; Fuerstenau, S.; Brennen, R. A.; Hruby, J.; Bonivert, W.

    1997-01-01

    A linear array of nine quadrupoles was fabricated using the LIGA process. Pole heights ranging from 1 to 3 mm were fabricated using synchrotron X-ray exposures to form free standing polymethylmethacrylate (PMMA) molds into which copper, gold or nickel were electroplated.

  4. Fracture of silicon wafers

    NASA Astrophysics Data System (ADS)

    McLaughlin, J. C.; Willoughby, A. F. W.

    1987-11-01

    In spite of the increasing use of silicon in applications where mechanical stresses are deliberately applied to the material, such as in transducers, and the fatal nature of cracking in silicon devices, there is very limited characterisation and understanding of the fracture behaviour of silicon wafers at room temperature. This understanding is of increasing importance with the use of larger diameter wafers in modern technology. This paper examines the fracture strength of a wide range of silicon material both as-grown and after processing. The wafers tested were from crystals grwon by float-zone and Czochralski techniques and the effects of oxidation, ion-implantation and annealing in various environments have been studied. The technique used to measure the fracture stress involved simply supporting the wafer on an aluminium ring concentric to the load axis. The load was gradually increased until the wafer fractured. This method was chosen to avoid edge effects, and has proved to have adequate reproducibility. Typical values of the fracture stress obtained by this method, for different crystals, vary between 2 and 3.5 GPa. In the first part of the study, the role of the surface on the fracture behaviour has been investigated in detail. While the surface perfection of the tensile surface has a major effect on the fracture stress (as shown in previous studies), some of the results were found to be sensitive to the compressive surface as well. In the case where the results are sensitive to the compressive surface finish the fracture stress rose from 3.7 to 8.8 GPa as the surface finish was improved while in the cases where they were not sensitive the fracture stress remained at about 3.5-4.6 GPa. Only in the float-zone material were fracture stresses approaching 8.8 GPa observed. At this level of fracture stress, the behaviour is believed to be sensitive to surface defects less than 0.01 ?m in size. These results can be analyzed in terms of surface controlled defects under conditions where surface defects are dominant and bulk controlled defects where these defects are dominant. In this manner bulk effects can be isolated from surface ones. This gives the opportunity to study the effects of specific defects on the fracture stress and the results in this paper are discussed in terms of the role of surface and internal defects on the fracture stress.

  5. Great enhancement in the excitonic recombination and light extraction of highly ordered InGaN/GaN elliptic nanorod arrays on a wafer scale.

    PubMed

    Zhuang, Zhe; Guo, Xu; Liu, Bin; Hu, Fengrui; Dai, Jiangping; Zhang, Yun; Li, Yi; Tao, Tao; Zhi, Ting; Xie, Zili; Ge, Haixiong; Wang, Xiaoyong; Xiao, Min; Wang, Tao; Shi, Yi; Zheng, Youdou; Zhang, Rong

    2016-01-01

    A series of highly ordered c-plane InGaN/GaN elliptic nanorod (NR) arrays were fabricated by our developed soft UV-curing nanoimprint lithography on a wafer. The photoluminescence (PL) integral intensities of NR samples show a remarkable enhancement by a factor of up to two orders of magnitude compared with their corresponding as-grown samples at room temperature. The radiative recombination in NR samples is found to be greatly enhanced due to not only the suppressed non-radiative recombination but also the strain relaxation and optical waveguide effects. It is demonstrated that elliptic NR arrays improve the light extraction greatly and have polarized emission, both of which possibly result from the broken structure symmetry. Green NR light-emitting diodes have been finally realized, with good current-voltage performance and uniform luminescence. PMID:26595508

  6. Great enhancement in the excitonic recombination and light extraction of highly ordered InGaN/GaN elliptic nanorod arrays on a wafer scale

    NASA Astrophysics Data System (ADS)

    Zhuang, Zhe; Guo, Xu; Liu, Bin; Hu, Fengrui; Dai, Jiangping; Zhang, Yun; Li, Yi; Tao, Tao; Zhi, Ting; Xie, Zili; Ge, Haixiong; Wang, Xiaoyong; Xiao, Min; Wang, Tao; Shi, Yi; Zheng, Youdou; Zhang, Rong

    2016-01-01

    A series of highly ordered c-plane InGaN/GaN elliptic nanorod (NR) arrays were fabricated by our developed soft UV-curing nanoimprint lithography on a wafer. The photoluminescence (PL) integral intensities of NR samples show a remarkable enhancement by a factor of up to two orders of magnitude compared with their corresponding as-grown samples at room temperature. The radiative recombination in NR samples is found to be greatly enhanced due to not only the suppressed non-radiative recombination but also the strain relaxation and optical waveguide effects. It is demonstrated that elliptic NR arrays improve the light extraction greatly and have polarized emission, both of which possibly result from the broken structure symmetry. Green NR light-emitting diodes have been finally realized, with good current-voltage performance and uniform luminescence.

  7. Wafer level warpage characterization of 3D interconnect processing wafers

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2012-03-01

    We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 μm after thinning down to the nominal thickness of 75 μm and 50 μm. The measurement precision is better than 2 um.

  8. Interferometry for wafer dimensional metrology

    NASA Astrophysics Data System (ADS)

    Freischlad, Klaus; Tang, Shouhong; Grenfell, Jim

    2007-09-01

    Wafer shape and thickness variation are important parameters in the IC manufacturing process. The thickness variation, also called flatness, enters the depth-of-focus budget of microlithography, and also affects film thickness uniformity in the CMP processing. The shape mainly affects wafer handling, and may also require some depth-of-focus if the wafer shape is not perfectly flattened by chucking. In the progression of technology nodes to smaller feature sizes, and hence smaller depth-of-focus of the lithography tool, the requirement for the PV-flatness over stepper exposure sites is becoming progressively tighter, and has reached 45nm for the next technology node of 45nm half pitch. Consequently, in order to be gauge-capable the flatness metrology tool needs to provide a measurement precision of the order of 1nm. Future technology nodes will require wafers with even better flatness and metrology tools with better measurement precision. For the last several years the common capacitive tools for wafer dimensional metrology have been replaced by interferometric tools with higher sensitivity and resolution. In the interferometric tools the front and back surface figure of the wafer is measured simultaneously while the wafer is held vertically in its intrinsic shape. The thickness variation and shape are then calculated from these single-sided maps. The wafer shape, and hence each wafer surface figure, can be tens of microns, necessitating a huge dynamic range of the interferometer when considering the 1nm measurement precision. Furthermore, wafers are very flexible, and hence very prone to vibrations as well as bending. This presentation addresses these special requirements of interferometric wafer measurements, and discusses the system configuration and measurement performance of WaferSight TM, KLA-Tencor's interferometric dimensional metrology tool for 300mm wafers for current and future technology nodes.

  9. Wafer-scale controlled exfoliation of metal organic vapor phase epitaxy grown InGaN/GaN multi quantum well structures using low-tack two-dimensional layered h-BN

    NASA Astrophysics Data System (ADS)

    Ayari, Taha; Sundaram, Suresh; Li, Xin; El Gmili, Youssef; Voss, Paul L.; Salvestrini, Jean Paul; Ougazzaden, Abdallah

    2016-04-01

    Recent advances in epitaxial growth have led to the growth of III-nitride devices on 2D layered h-BN. This advance has the potential for wafer-scale transfer to arbitrary substrates, which could improve the thermal management and would allow III-N devices to be used more flexibly in a broader range of applications. We report wafer scale exfoliation of a metal organic vapor phase epitaxy grown InGaN/GaN Multi Quantum Well (MQW) structure from a 5 nm thick h-BN layer that was grown on a 2-inch sapphire substrate. The weak van der Waals bonds between h-BN atomic layers break easily, allowing the MQW structure to be mechanically lifted off from the sapphire substrate using a commercial adhesive tape. This results in the surface roughness of only 1.14 nm on the separated surface. Structural characterizations performed before and after the lift-off confirm the conservation of structural properties after lift-off. Cathodoluminescence at 454 nm was present before lift-off and 458 nm was present after. Electroluminescence near 450 nm from the lifted-off structure has also been observed. These results show that the high crystalline quality ultrathin h-BN serves as an effective sacrificial layer—it maintains performance, while also reducing the GaN buffer thickness and temperature ramps as compared to a conventional two-step growth method. These results support the use of h-BN as a low-tack sacrificial underlying layer for GaN-based device structures and demonstrate the feasibility of large area lift-off and transfer to any template, which is important for industrial scale production.

  10. Augmented reality for wafer prober

    NASA Astrophysics Data System (ADS)

    Gilgenkrantz, Pascal

    2011-03-01

    The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

  11. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  12. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  13. W-band LiGA fabricated klystron

    NASA Astrophysics Data System (ADS)

    Song, Liqun

    2002-01-01

    Klystrino-W-band klystron was proposed by scientists at SLAC to satisfy recent applications in advanced accelerators, medical treatment, radars and communications. LiGA (a German acronym for lithographe, galvanoformung, and abformung) is introduced in the fabrication of klystrino for the first time in the history of microwave tube fabrication. The cold test experiments show that LiGA fabrication yields best surface smoothness compared with an alternative way EDM (Electrical Discharge Machining). Resultantly LiGA fabricated klystrino has the smallest wall loss which maximizes the circuit efficiency of the output structure. A multiple-gap coupled cavity is motivated to be employed as the klystrino output cavity for maximizing the efficiency. Klytrino is simulated by 1-D, 2-D and 3-D simulation codes. Particularly a complete klystrino is simulated intensively using 2-D MAGIC Particle-in-Cell (PIC) code either for beam absence or beam presence. Many simulation techniques are developed such as model transformation from 3-D to 2-D, circuit parameter simulation, dispersion characteristic analysis, pre bunched electron beam mode and so on. Klystrino, as a 3-D structure, is modeled by 3-D MAFIA for analyzing the cold circuit properties. 3-D MAGIC is explored to simulate klystrino for the actual structure analysis and actual beam interaction process observation.

  14. In-situ detection method for wafer movement and micro-arc discharge around a wafer in plasma etching process using electrostatic chuck wafer stage with built-in acoustic emission sensor

    NASA Astrophysics Data System (ADS)

    Kasashima, Yuji; Tabaru, Tatsuo; Yasaka, Mitsuo; Kobayashi, Yoshikazu; Akiyama, Morito; Nabeoka, Natsuko; Motomura, Taisei; Sakamoto, Shingo; Uesugi, Fumihiko

    2014-01-01

    We report an electrostatic chuck (ESC) wafer stage with a built-in acoustic emission (AE) sensor for detecting anomalies occurring around a wafer during plasma etching. The built-in AE sensor detects acoustic waves caused by wafer movement and micro-arc discharge with high sensitivity, and identifies these anomalies based on the frequency characteristics of the waves. The results demonstrate the effectiveness of using an ESC wafer stage with a built-in AE sensor for in-situ anomaly detection, which can improve the production yield and overall equipment efficiency in large scale integrated circuit (LSI) manufacturing.

  15. System for slicing wafers

    NASA Astrophysics Data System (ADS)

    1982-02-01

    A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

  16. System for slicing wafers

    NASA Technical Reports Server (NTRS)

    1982-01-01

    A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

  17. MEMS Wafer-level Packaging Technology Using LTCC Wafer

    NASA Astrophysics Data System (ADS)

    Mohri, Mamoru; Esashi, Masayoshi; Tanaka, Shuji

    This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature co-fired ceramic (LTCC) wafer, in which multi-layer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of micro electro mechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (-40°C×30min/+125°C×30min) by diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection methods; The electrical connection is established by porous Au bumps, which are a part of Au vias exposed in wet-etched cavities on the LTCC wafer. 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

  18. Wafer Replacement Cluster Tool (Presentation);

    SciTech Connect

    Branz, H. M.

    2008-04-01

    This presentation on wafer replacement cluster tool discusses: (1) Platform for advanced R and D toward SAI 2015 cost goal--crystal silicon PV at area costs closer to amorphous Si PV, it's 15% efficiency, inexpensive substrate, and moderate temperature processing (<800 C); (2) Why silicon?--industrial and knowledge base, abundant and environmentally benign, market acceptance, and good efficiency; and (3) Why replace wafers?--expensive, high embedded energy content, and uses 50-100 times more silicon than needed.

  19. Wafer-Scale Precise Patterning of Organic Single-Crystal Nanowire Arrays via a Photolithography-Assisted Spin-Coating Method.

    PubMed

    Deng, Wei; Zhang, Xiujuan; Wang, Liang; Wang, Jincheng; Shang, Qixun; Zhang, Xiaohong; Huang, Liming; Jie, Jiansheng

    2015-12-01

    A photolithography-assisted spin-coating approach is developed to produce single-crystal organic nanowire (NW) arrays at designated locations with high precision and high efficiency. This strategy enables the large-scale fabrication of organic NW arrays with nearly the same accuracy, reliability, and flexibility as photolithography. The high mobilities of the organic NWs enable the control of the switch of multicolored light-emitting devices with good stability. PMID:26460612

  20. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    SciTech Connect

    Bajikar, Sateesh S.; DeCarlo, Francesco; Song, Joshua J.

    1998-05-22

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized from pyromellitic anhydride and oxydianiline (PMDA-ODA).

  1. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    DOEpatents

    Bajikar, Sateesh S.; De Carlo, Francesco; Song, Joshua J.

    2004-01-27

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  2. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    DOEpatents

    Bajikar, Sateesh S.; De Carlo, Francesco; Song, Joshua J.

    2001-01-01

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  3. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    PubMed

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

  4. Development of Megasonic cleaning for silicon wafers. Final report

    SciTech Connect

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  5. GEM-type detectors using LIGA and etchable glass technologies

    SciTech Connect

    Ahn, S.K.; Kim, J.G.; Perez-Mendez, V.; Chang, S.; Jackson, K.H.; Kadyk, J.A.; Wenzel, W.A.; Cho, G.

    2001-11-02

    Gas electron multipliers (GEMS) have been made by a deep X-ray lithography technique (LIGA process) using synchrotron radiation on polymethylmethacrylate (PMMA) and by UV processes using a UV etchable glass. Gain, stability and rate capability for these detectors are described.The LIGA detectors described consist of PMMA sheets of various thicknesses, 125mm to 350mm, and have 150mm x 150mm square holes spaced with a pitch of 300mm. Thin copper electrodes are plated on the top and bottom surfaces using a Damascene method, followed by electroless plating of the copper onto a palladium-tin base layer. For various thicknesses of PMMA measurements have been made of absolute gain vs. voltage, time stability of gain, and rate capability. The operating gas mixture was usually Ar/CO2 (70/30) gas, but some tests were also done using P10 gas. We also made GEM-like detectors using the UV etchable glass called Foturan, patterned by exposure to UV light and subsequent etching. A few measurements using these detectors will be reported, including avalanche gain and time stability.

  6. Investigation of sidewall cracking in PMMA LIGA structures

    NASA Astrophysics Data System (ADS)

    Hunter, L. L.; Skala, D. M.; Levey, B. S.

    2006-07-01

    During x-ray exposure in the LIGA process, the polymethylmethacrylate (PMMA) photoresist undergoes chain scission, which reduces the molecular weight of the exposed materials. Under some exposure and development conditions, sidewall cracking is observed on the PMMA sidewall, creating surface texture that is undesirable. In this research, exposed and developed PMMA sidewalls were examined for evidence of crack formation using optical profilometry. PMMA thickness, exposure dose and delay time between the end of exposure and beginning of development were varied. Our analysis of samples, with three different radiation doses and four different delay times from the end of exposure to the beginning of development, indicate that the first occurrence of cracking and the extent of cracking are affected by both the dose and the development delay time. This work includes the examination of the depth of cracks into the PMMA, distance between cracks, the width of cracks and the relationship between crack occurrence and dose profile. An empirical predictive model to correlate the delay time to the observance of sidewall cracking based on the deposited dose is presented. This information has direct implication for predicting processing conditions and logistics for LIGA fabricated parts.

  7. Manufacturing microcomponents for optical information technology using the LIGA technique

    NASA Astrophysics Data System (ADS)

    Bauer, Hans-Dieter; Ehrfeld, Wolfgang; Hossfeld, Jens; Paatzsch, Thomas

    1999-09-01

    Recently, splices and connectors for fibers ribbons, optical cross connects and especially planar waveguide devices have been fabricated via LIGA in combination with precision engineering techniques. LIGA combines high precision and mass production capability, necessary for products designed for applications in the telecom and datacom market. In this presentation the fabrication of three-level molding and embossing tools is presented, which have been used for the manufacturing of waveguide prestructures consisting of waveguide channels and bier-to-waveguide coupling grooves. The precision of the tools is better than 1 micrometers in all directions, which allows for simple passive pigtailing. A first product, a precision of the tool is better than 1 micrometers in all directions, which allows for simple passive pigtailing. A first product, sixfold array of 4 X 4 multimode star couplers has been realized. The molding behavior of PMMA and COC material has been tested and compared. Production and assembly was tested by fabricating a series of 300 star couplers. The average insertion los has been found better than 9dB, the uniformity better than 3dB, both measured at 830nm. THe device is designed for application in optical backplanes for high-speed computers.

  8. Characterization of Sidewall and Planar Surfaces of Electroformed LIGA Parts

    SciTech Connect

    PRASAD,SOMURI V.; HALL,AARON C.; DUGGER,MICHAEL T.

    2000-10-01

    The nature of surfaces and the way they interact with each other during sliding contact can have a direct bearing on the performance of a microelectromechanical (MEMS) device. Therefore, a study was undertaken to characterize the surfaces of LIGA fabricated Ni and Cu components. Sidewall and planar surfaces were examined by scanning electron microscopy (SEM) and atomic force microscopy (AFM). Surface roughness was quantified using the AFM. Post-processing (e.g. lapping, removal of polymer film) can profoundly influence the morphology of LIGA components. Edge rounding and smearing of ductile materials during lapping can result in undesirable sidewall morphologies. By judicious selection of AFM scan sizes, the native roughness ({approximately}10 nm RMS) can be distinguished from that arising due to post processing, e.g. scratches, debris, polymer films. While certain processing effects on morphology such as those due to lapping or release etch can be controlled, the true side wall morphology appears to be governed by the morphology of the polymer mold or by the electroforming process itself, and may be much less amenable to modification.

  9. X-ray Lenses Fabricated by LIGA Technology

    SciTech Connect

    Nazmov, Vladimir; Last, Arndt; Saile, Volker; Reznikova, Elena; Mohr, Jurgen; Simon, Rolf; DiMichiel, Marco

    2007-01-19

    X-ray refractive optical lens systems have been successfully elaborated, designed, fabricated at the Institute for Microstructure Technology at the Forschungszentrum Karlsruhe (Germany) using LIGA technology in recent years. The lenses are structured in a SU-8 polymer. The capability of the LIGA technique to create an arbitrary profile of the focusing microstructures allow the fabrication of lenses with different curvature radius of parabolic geometry, minimized absorption and a large depth of focus. Also a set of planar lens systems on one substrate can be realized with 17 lenses providing identical focal distances for different X-ray energies from 2 to over 100 keV. Nickel lenses fabricated by electroforming using polymer templates can be applied for energies larger than 80 keV. The parabolic crossed lenses are used for 2D nano focusing of monochromatic beams. The quasi-parabolic crossed lenses with a submicron focus and a focus depth of the centimetre range can be used as an achromatic system. Mosaic truncated parabolic lenses with a focusing aperture up to 1 mm are made to increase the X-ray intensity in the focused spot.

  10. Selective area growth of InP in shallow trench isolation on large scale Si(001) wafer using defect confinement technique

    NASA Astrophysics Data System (ADS)

    Merckling, C.; Waldron, N.; Jiang, S.; Guo, W.; Richard, O.; Douhard, B.; Moussa, A.; Vanhaeren, D.; Bender, H.; Collaert, N.; Heyns, M.; Thean, A.; Caymax, M.; Vandervorst, W.

    2013-07-01

    Heterogeneous integration of III-V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III-V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III-V virtual substrates on large-scale Si substrates.

  11. Computational Modeling in Plasma Processing for 300 mm Wafers

    NASA Technical Reports Server (NTRS)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  12. Wafer characteristics via reflectometry and wafer processing apparatus and method

    DOEpatents

    Sopori, Bhushan L.

    2007-07-03

    An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

  13. BCB wafer bonding for microfluidics

    NASA Astrophysics Data System (ADS)

    Hwang, Taejoo; Popa, Dan; Sin, Jeongsik; Stephanou, Harry E.; Leonard, Eric M.

    2004-01-01

    In this paper we show that BCB wafer bonding, combined with deep-reactive-ion-etching (DRIE) for silicon, and HF etching for FOTURAN glass are viable methods to fabricate three-dimensional microfluidics. The BCB film is patterned by dry-etching technique with a photoresist mask and the target wafer is then bulk-micromachined together with the BCB mask. The two micromachined wafers are then bonded together under vacuum or nitrogen gas environment, at low temperature. Silicon-glass, silicon-silicon and glass-glass are all possible bonding pairs using thermocompressive bonding with BCB. It was found that hard-cured BCB bonding is more suitable for microfluidic channel fabrications than soft-cured BCB bonding, due to adhesive overflows in microfluidic channels and delamination during wet etching.

  14. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  15. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R. (Berkeley, CA)

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  16. Nano-particle laser removal from silicon wafers

    NASA Astrophysics Data System (ADS)

    Lee, J. M.; Cho, S. H.; Kim, T. H.; Park, Jin-Goo; Busnaina, Ahmed A.

    2003-11-01

    A laser shock cleaning (LSC) technique as a new dry cleaning methodology has been applied to remove micro and nano-scale inorganic particulate contaminants. Shock wave is generated in the air just above the wafer surface by focusing intensive laser beam. The velocity of shock wave can be controlled to 10,000 m/sec. The sub-micron sized silica and alumina particles are attempted to remove from bare silicon wafer surfaces. More than 95% of removal efficiency of the both particles are carried out by the laser-induced airborne shock waves. In the final, a removal of nano-scale slurry particles from real patterned wafers are successfully demonstrated by LSC after chemical-mechanical polishing (CMP) process.

  17. LIGA-based microsystem manufacturing:the electrochemistry of through-mold depostion and material properties.

    SciTech Connect

    Kelly, James J.; Goods, Steven Howard

    2005-06-01

    The report presented below is to appear in ''Electrochemistry at the Nanoscale'', Patrik Schmuki, Ed. Springer-Verlag, (ca. 2005). The history of the LIGA process, used for fabricating dimensional precise structures for microsystem applications, is briefly reviewed, as are the basic elements of the technology. The principal focus however, is on the unique aspects of the electrochemistry of LIGA through-mask metal deposition and the generation of the fine and uniform microstructures necessary to ensure proper functionality of LIGA components. We draw from both previously published work by external researchers in the field as well as from published and unpublished studies from within Sandia.

  18. Genesis of nanostructured, magnetically tunable ceramics from the pyrolysis of cross-linked polyferrocenylsilane networks and formation of shaped macroscopic objects and micron scale patterns by micromolding inside silicon wafers.

    PubMed

    Ginzburg, Madlen; MacLachlan, Mark J; Yang, San Ming; Coombs, Neil; Coyle, Thomas W; Raju, Nandyala P; Greedan, John E; Herber, Rolfe H; Ozin, Geoffrey A; Manners, Ian

    2002-03-20

    The ability to form molded or patterned metal-containing ceramics with tunable properties is desirable for many applications. In this paper we describe the evolution of a ceramic from a metal-containing polymer in which the variation of pyrolysis conditions facilitates control of ceramic structure and composition, influencing magnetic and mechanical properties. We have found that pyrolysis under nitrogen of a well-characterized cross-linked polyferrocenylsilane network derived from the ring-opening polymerization (ROP) of a spirocyclic [1]ferrocenophane precursor gives shaped macroscopic magnetic ceramics consisting of alpha-Fe nanoparticles embedded in a SiC/C/Si(3)N(4) matrix in greater than 90% yield up to 1000 degrees C. Variation of the pyrolysis temperature and time permitted control over the nucleation and growth of alpha-Fe particles, which ranged in size from around 15 to 700 A, and the crystallization of the surrounding matrix. The ceramics contained smaller alpha-Fe particles when prepared at temperatures lower than 900 degrees C and displayed superparamagnetic behavior, whereas the materials prepared at 1000 degrees C contained larger alpha-Fe particles and were ferromagnetic. This flexibility may be useful for particular materials applications. In addition, the composition of the ceramic was altered by changing the pyrolysis atmosphere to argon, which yielded ceramics that contain Fe(3)Si(5). The ceramics have been characterized by a combination of physical techniques, including powder X-ray diffraction, TEM, reflectance UV-vis/near-IR spectroscopy, elemental analysis, XPS, SQUID magnetometry, Mössbauer spectroscopy, nanoindentation, and SEM. Micromolding of the spirocyclic [1]ferrocenophane precursor within soft lithographically patterned channels housed inside silicon wafers followed by thermal ROP and pyrolysis enabled the formation of predetermined micron scale designs of the magnetic ceramic. PMID:11890813

  19. Characterization of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  20. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  1. Temperature Dependent Electrical Properties of PZT Wafer

    NASA Astrophysics Data System (ADS)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  2. Temperature Dependent Electrical Properties of PZT Wafer

    NASA Astrophysics Data System (ADS)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-01-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  3. Deposition uniformity inspection in IC wafer surface

    NASA Astrophysics Data System (ADS)

    Li, W. C.; Lin, Y. T.; Jeng, J. J.; Chang, C. L.

    2014-03-01

    This paper focuses on the task of automatic visual inspection of color uniformity on the surface of integrated circuits (IC) wafers arising from the layering process. The oxide thickness uniformity within a given wafer with a desired target thickness is of great importance for modern semiconductor circuits with small oxide thickness. The non-uniform chemical vapor deposition (CVD) on a wafer surface will proceed to fail testing in Wafer Acceptance Test (WAT). Early detection of non-uniform deposition in a wafer surface can reduce material waste and improve production yields. The fastest and most low-priced inspection method is a machine vision-based inspection system. In this paper, the proposed visual inspection system is based on the color representations which were reflected from wafer surface. The regions of non-uniform deposition present different colors from the uniform background in a wafer surface. The proposed inspection technique first learns the color data via color space transformation from uniform deposition of normal wafer surfaces. The individual small region statistical comparison scheme then proceeds to the testing wafers. Experimental results show that the proposed method can effectively detect the non-uniform deposition regions on the wafer surface. The inspection time of the deposited wafers is quite compatible with the atmospheric pressure CVD time.

  4. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  5. Wafer Manufacturing and Slicing Using Wiresaw

    NASA Astrophysics Data System (ADS)

    Kao, Imin; Chung, Chunhui; Moreno Rodriguez, Roosevelt

    Wafer manufacturing (or wafer production) refers to a series of modern manufacturing processes of producing single-crystalline or poly-crystalline wafers from crystal ingot (or boule) of different sizes and materials. The majority of wafers are single-crystalline silicon wafers used in microelectronics fabrication although there is increasing importance in slicing poly-crystalline photovoltaic (PV) silicon wafers as well as wafers of different materials such as aluminum oxide, lithium niobate, quartz, sapphire, III-V and II-VI compounds, and others. Slicing is the first major post crystal growth manufacturing process toward wafer production. The modern wiresaw has emerged as the technology for slicing various types of wafers, especially for large silicon wafers, gradually replacing the ID saw which has been the technology for wafer slicing in the last 30 years of the 20th century. Modern slurry wiresaw has been deployed to slice wafers from small to large diameters with varying wafer thickness characterized by minimum kerf loss and high surface quality. The needs for slicing large crystal ingots (300 mm in diameter or larger) effectively with minimum kerf losses and high surface quality have made it indispensable to employ the modern slurry wiresaw as the preferred tool for slicing. In this chapter, advances in technology and research on the modern slurry wiresaw manufacturing machines and technology are reviewed. Fundamental research in modeling and control of modern wiresaw manufacturing process are required in order to understand the cutting mechanism and to make it relevant for improving industrial processes. To this end, investigation and research have been conducted for the modeling, characterization, metrology, and control of the modern wiresaw manufacturing processes to meet the stringent precision requirements of the semiconductor industry. Research results in mathematical modeling, numerical simulation, experiments, and composition of slurry versus wafer quality are presented. Summary and further reading are also provided.

  6. An aluminum resist substrate for microfabrication by LIGA.

    SciTech Connect

    Kelly, James J.; Boehme, Dale R.; Hauck, Cheryl A.; Yang, Chu-Yeu Peter; Hunter, Luke L.; Griffiths, Stewart K.; McLean, Dorrance E.; Aigeldinger, Georg; Hekmaty, Michelle A.; Hachman, John T.; Losey, Matthew W.; Skala, Dawn M.; Korellis, John S.; Friedmann, Thomas Aquinas; Yang, Nancy Y. C.; Lu, Wei-Yang

    2005-04-01

    Resist substrates used in the LIGA process must provide high initial bond strength between the substrate and resist, little degradation of the bond strength during x-ray exposure, acceptable undercut rates during development, and a surface enabling good electrodeposition of metals. Additionally, they should produce little fluorescence radiation and give small secondary doses in bright regions of the resist at the substrate interface. To develop a new substrate satisfying all these requirements, we have investigated secondary resist doses due to electrons and fluorescence, resist adhesion before exposure, loss of fine features during extended development, and the nucleation and adhesion of electrodeposits for various substrate materials. The result of these studies is a new anodized aluminum substrate and accompanying methods for resist bonding and electrodeposition. We demonstrate successful use of this substrate through all process steps and establish its capabilities via the fabrication of isolated resist features down to 6 {micro}m, feature aspect ratios up to 280 and electroformed nickel structures at heights of 190 to 1400 {micro}m. The minimum mask absorber thickness required for this new substrate ranges from 7 to 15 {micro}m depending on the resist thickness.

  7. LIGA-fabricated compact mm-wave linear accelerator cavities.

    SciTech Connect

    Song, J.J.; Bajikar, S.S.; DeCarlo, F.; Kang, Y.W.; Kustom, R.L.; Mancini, D.C.; Nassiri, A.; Lai, B.; Feinerman, A.D.; White, V.

    1998-03-23

    Millimeter-wave rf cavities for use in linear accelerators, free-electron lasers, and mm-wave undulatory are under development at Argonne National Laboratory. Typical cavity dimensions are in the 1000 mm range, and the overall length of the accelerator structure, which consists of 30-100 cavities, is about 50-100 mm. An accuracy of 0.2% in the cavity dimensions is necessary in order to achieve a high Q-factor of the cavity. To achieve this these structures are being fabricated using deep X-ray lithography, electroforming, and assembly (LIGA). The first prototype cavity structures are designed for 108 GHz and 2p/3-mode operation. Input and output couplers are integrated with the cavity structures. The cavities are fabricated on copper substrates by electroforming copper into 1-mm-thick PMMA resists patterned by deep x-ray lithography and polishing the copper down to the desired thickness. These are fabricated separately and subsequently assembled with precision spacing and alignment using microspheres, optical fibers, or microfabricated spacers/alignment pieces. Details of the fabrication process, alignment, and assembly work are presented in here.

  8. Technology for integrated circuit micropackages for neural interfaces, based on gold-silicon wafer bonding

    NASA Astrophysics Data System (ADS)

    Saeidi, N.; Schuettler, M.; Demosthenous, A.; Donaldson, N.

    2013-07-01

    Progress in the development of active neural interface devices requires a very compact method for protecting integrated circuits (ICs). In this paper, a method of forming micropackages is described in detail. The active areas of the chips are sealed in gas-filled cavities of the cap wafer in a wafer-bonding process using Au-Si eutectic. We describe the simple additions to the design of the IC, the post-processing of the active wafer and the required features of the cap wafer. The bonds, which were made at pressure and temperature levels within the range of the tolerance of complementary metal-oxide-semiconductor ICs, are strong enough to meet MIL STD 883G, Method 2019.8 (shear force test). We show results that suggest a method for wafer-scale gross leak testing using FTIR. This micropackaging method requires no special fabrication process and is based on using IC compatible or conventional fabrication steps.

  9. Wafer-bonded surface plasmon waveguides

    NASA Astrophysics Data System (ADS)

    Berini, Pierre; Mattiussi, Greg; Lahoud, Nancy; Charbonneau, Robert

    2007-02-01

    Direct wafer bonding and thinning were explored as an approach for constructing long-range surface plasmon waveguides. The structures consist of a thin metal stripe deposited into a shallow trench etched into one of the claddings, to which another cladding of the same material is directly bonded. The approach was developed first using Pyrex wafers in order to assess feasibility and then using lithium niobate wafers. Optical and electro-optical measurements validate the approach.

  10. Particle detector with three microchannel wafers

    SciTech Connect

    Gribov, I.V.; Gubin, S.V.; Lazutin, E.V.; Persiantseva, N.M.; Shumakov, A.V.

    1985-11-01

    A particle detector consisting of three series-connected microchannel wafers is described. The detector provides a singleelectron gain of 2x10/sup 7/ without using extreme wafer operating conditions and the width of the pulse amplitude distribution is approximately 100%. The particle sources used were a tritium beta source, a Pierce electron gun with spherical electrodes, and a /sup 233/ Pu alpha source. The load characteristics of one microchannel wafer for various supply voltages were measured.

  11. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  12. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    SciTech Connect

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  13. Wafer level reliability for high-performance VLSI design

    NASA Technical Reports Server (NTRS)

    Root, Bryan J.; Seefeldt, James D.

    1987-01-01

    As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

  14. Structural and compositional characterization of MOVPE GaN thin films transferred from sapphire to glass substrates using chemical lift-off and room temperature direct wafer bonding and GaN wafer scale MOVPE growth on ZnO-buffered sapphire

    NASA Astrophysics Data System (ADS)

    Gautier, S.; Moudakir, T.; Patriarche, G.; Rogers, D. J.; Sandana, V. E.; Hosseini Téherani, F.; Bove, P.; El Gmili, Y.; Pantzas, K.; Sundaram, Suresh; Troadec, D.; Voss, P. L.; Razeghi, M.; Ougazzaden, A.

    2013-05-01

    GaN thin films were grown on ZnO/c-Al2O3 with excellent uniformity over 2 in. diameter wafers using a low temperature/pressure MOVPE process with N2 as a carrier and dimethylhydrazine as an N source. 5 mm×5 mm sections of similar GaN layers were direct-fusion-bonded onto soda lime glass substrates after chemical lift-off from the sapphire substrates. X-Ray Diffraction, Scanning Electron Microscopy and Transmission Electron Microscopy confirmed the bonding of crack-free wurtzite GaN films onto a glass substrate with a very good quality of interface, i.e. continuous/uniform adherence and absence of voids or particle inclusions. Using this approach, (In) GaN based devices can be lifted-off expensive single crystal substrates and bonded onto supports with a better cost-performance profile. Moreover, the approach offers the possibility of reclaiming the expensive sapphire substrate so it can be utilized again for growth.

  15. Preparation and Characterization of PZT Wafers

    NASA Astrophysics Data System (ADS)

    Seal, A.; Rao, B. S. S. Chandra; Kamath, S. V.; Sen, A.; Maiti, H. S.

    2008-07-01

    Piezoelectric materials have recently attracted a lot of attention for ultrasonic structural health monitoring (shm) in aerospace, defence and civilian sectors, where they can act as both actuators and sensors. Incidentally, piezoelectric materials in the form of wafers (pwas-piezoelectric wafer active sensor, approx. 5-10 mm square and 0.2-0.3 mm thickness) are inexpensive, non intrusive and non-resonant wide band devices that can be surface-mounted on existing structures, inserted between the layers of lap joints or embedded inside composite materials. The material of choice for piezoelectric wafers is lead zirconate titanate (PZT) of composition close to morphotropic phase boundary [pb(zr0.52 ti0.48)o3]. However, an excess pbo is normally added to pzt as a densification aid and also to make up for the lead loss during high temperature sintering. Hence, it is of paramount importance to know how the shift of the lead content from the morphotropic composition affects the piezoelectric and mechanical properties of the sintered wafers, keeping in view the importance of mechanical properties of wafers in shm. In the present study, we observed that with the increase in the lead content of the sintered wafers, the dielectric and piezoelectric constants decreased. However, the elastic modulus, hardness and fracture toughness of the wafers increased with increasing lead content in the composition. Hence, the lead content in the sintered wafers should be optimized to get acceptable piezoelectric and mechanical

  16. Formation and combustion characteristics of elephantgrass and energycane wafers

    NASA Astrophysics Data System (ADS)

    Mofleh, Mohamad I.

    Elephantgrass (Pennisetum purpureum Schum.) and energycane (Saccharum Spp.) are two cane type grasses. These are tall-growing perennial bunchgrasses that produce long hardened stems and grow in the tropics and subtropics. Traditionally, they have been used for forage and, in some regions, have been randomly burned on fields or disposed of uselessly. However, these plants have high dry matter yield and, thus, are excellent candidates as energy crops. Elephantgrass and energycane have been used for direct combustion in their loose form in large-scale applications. Several problems, many of which were attributed to their low bulk density, were encountered with using the materials. Consequently, this project was initiated to investigate the formation and combustion characteristics of the two materials in the form of small compact units called wafers. A hydraulic press that applied axial stresses on the material in four different dies was used. A load cell and a displacement transducer were utilized to measure the stresses and material detection. Wafer quality was evaluated using a tumbler built according to the American Society of Agricultural Engineers standards. In addition, a small stove was built to test wafer combustion. Thermocouples were used to measure temperatures during combustion. All the data gathered was transferred to a computer using a data acquisition system. It was found that the stress-deformation and stress-density relationships of elephantgrass and energycane were of exponential nature. Compaction energy required, which was calculated from the area under the force-deformation curves, ranged from 0.1 to 0.3% of their energy content. It was also found that wafer quality (durability) was mainly a function of wafer size and its final (relaxed) density in addition to material stem-to-leaf ratio and its crude protein content. Wafers possessed poor ignition quality but once ignited, they burned satisfactorily. The results indicated that sufficient and uniform combustion air distribution and a stove lining were critical factors in burning these materials. Further, the findings revealed that it may not be recommended to use elephantgrass or energycane in large-scale applications due to their high slagging index. Nonetheless, using them in small-scale applications may be possible. Elephantgrass was generally a better candidate for such an application.

  17. Methane production using resin-wafer electrodeionization

    SciTech Connect

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  18. Total x-ray power measurements in the Sandia LIGA program.

    SciTech Connect

    Malinowski, Michael E. (Sandia National Laboratories, Livermore, CA); Ting, Aili (Sandia National Laboratories, Livermore, CA)

    2005-08-01

    Total X-ray power measurements using aluminum block calorimetry and other techniques were made at LIGA X-ray scanner synchrotron beamlines located at both the Advanced Light Source (ALS) and the Advanced Photon Source (APS). This block calorimetry work was initially performed on the LIGA beamline 3.3.1 of the ALS to provide experimental checks of predictions of the LEX-D (LIGA Exposure- Development) code for LIGA X-ray exposures, version 7.56, the version of the code in use at the time calorimetry was done. These experiments showed that it was necessary to use bend magnet field strengths and electron storage ring energies different from the default values originally in the code in order to obtain good agreement between experiment and theory. The results indicated that agreement between LEX-D predictions and experiment could be as good as 5% only if (1) more accurate values of the ring energies, (2) local values of the magnet field at the beamline source point, and (3) the NIST database for X-ray/materials interactions were used as code inputs. These local magnetic field value and accurate ring energies, together with NIST database, are now defaults in the newest release of LEX-D, version 7.61. Three dimensional simulations of the temperature distributions in the aluminum calorimeter block for a typical ALS power measurement were made with the ABAQUS code and found to be in good agreement with the experimental temperature data. As an application of the block calorimetry technique, the X-ray power exiting the mirror in place at a LIGA scanner located at the APS beamline 10 BM was measured with a calorimeter similar to the one used at the ALS. The overall results at the APS demonstrated the utility of calorimetry in helping to characterize the total X-ray power in LIGA beamlines. In addition to the block calorimetry work at the ALS and APS, a preliminary comparison of the use of heat flux sensors, photodiodes and modified beam calorimeters as total X-ray power monitors was made at the ALS, beamline 3.3.1. This work showed that a modification of a commercially available, heat flux sensor could result in a simple, direct reading beam power meter that could be a useful for monitoring total X-ray power in Sandia's LIGA exposure stations at the ALS, APS and Stanford Synchrotron Radiation Laboratory (SSRL).

  19. Temperature Sensitivity Conferred by ligA Alleles from Psychrophilic Bacteria upon Substitution in Mesophilic Bacteria and a Yeast Species.

    PubMed

    Pankowski, Jarosław A; Puckett, Stephanie M; Nano, Francis E

    2016-01-01

    We have assembled a collection of 13 psychrophilic ligA alleles that can serve as genetic elements for engineering mesophiles to a temperature-sensitive (TS) phenotype. When these ligA alleles were substituted into Francisella novicida, they conferred a TS phenotype with restrictive temperatures between 33 and 39°C. When the F. novicida ligA hybrid strains were plated above their restrictive temperatures, eight of them generated temperature-resistant variants. For two alleles, the mutations that led to temperature resistance clustered near the 5' end of the gene, and the mutations increased the predicted strength of the ribosome binding site at least 3-fold. Four F. novicida ligA hybrid strains generated no temperature-resistant variants at a detectable level. These results suggest that multiple mutations are needed to create temperature-resistant variants of these ligA gene products. One ligA allele was isolated from a Colwellia species that has a maximal growth temperature of 12°C, and this allele supported growth of F. novicida only as a hybrid between the psychrophilic and the F. novicida ligA genes. However, the full psychrophilic gene alone supported the growth of Salmonella enterica, imparting a restrictive temperature of 27°C. We also tested two ligA alleles from two Pseudoalteromonas strains for their ability to support the viability of a Saccharomyces cerevisiae strain that lacked its essential gene, CDC9, encoding an ATP-dependent DNA ligase. In both cases, the psychrophilic bacterial alleles supported yeast viability and their expression generated TS phenotypes. This collection of ligA alleles should be useful in engineering bacteria, and possibly eukaryotic microbes, to predictable TS phenotypes. PMID:26773080

  20. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  1. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  2. Yield-driven multi-project reticle design and wafer dicing

    NASA Astrophysics Data System (ADS)

    Kahng, Andrew B.; Mandoiu, Ion; Xu, Xu; Zelikovsky, Alex

    2005-11-01

    The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies has lead to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such low volume designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle design and wafer dicing introduce complexities not encountered in typical, single-project wafers. Recent works on wafer dicing adopt some assumptions to reduce the problem complexity. Although using one or more assumptions makes the problem solvable, the feasibility or performance of the solutions may be degraded. Also, the delay cost associated with schedule alignment was ignored in all previous works. In this paper we propose a general MPW flow including four main steps: (1) schedule-aware project partitioning (2) multi-project reticle floorplanning, (3) wafer shot-map definition, and (4) wafer dicing plan definition. Our project partitioner provides the best trade-off between the mask cost and delay cost. Our reticle floorplaner can automatically clone a design to better fit given production volumes. The round wafer shot-map definition step allows extracting functional dies from partially printed reticle images. Finally, our dicing planner allows multiple side-to-side dicing plans for different wafers and image rows/columns within a wafer. Experiments on industry testcases show that our methods outperform significantly not only previous methods in the literature, but also reticle floorplans manually designed by experienced engineers.

  3. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Rhee, S. S.

    1979-01-01

    Several aspects of silicon wafer surface texturizing were studied. A low cost cleaning method that utilizes recycled Freon in an ultrasonic vapor degreaser to remove organic and inorganic contaminants from the surface of silicon wafers as received from silicon suppliers was investigated. The use of clean dry air and high throughout wafer batch drying techniques was shown to lower the cost of wafer drying. A two stage texturizing process was examined for suitability in large scale production. Also, an in-depth gettering study with the two stage texturizing process was performed for the enhancement of solar cell efficiency, minimization of current versus voltage curve dispersion, and improvement in process reproducibility. The 10% efficiency improvement goal was exceeded for the near term implementation of flat plate photovoltaic cost reduction.

  4. Modelling deformation and fracture in confectionery wafers

    SciTech Connect

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  5. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  6. Forming electrical interconnections through semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Anthony, T. R.

    1981-01-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  7. Forming electrical interconnections through semiconductor wafers

    NASA Astrophysics Data System (ADS)

    Anthony, T. R.

    1981-08-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  8. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  9. Analyzes Data from Semiconductor Wafers

    Energy Science and Technology Software Center (ESTSC)

    2002-07-23

    This program analyzes reflectance data from semiconductor wafers taken during the deposition or evolution of a thin film, typically via chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). It is used to determine the growth rate and optical constants of the deposited thin films using a virtual interface concept. Growth rates and optical constants of multiple-layer structures is possible by selecting appropriate sections in the reflectance vs time waveform. No prior information or estimatesmore » of growth rates and materials properties is required if an absolute reflectance waveform is used. If the optical constants of a thin film are known, then the growth rate may be extracted from a relative reflectance data set. The analysis is valid for either s or p polarized light at any incidence angle and wavelength. The analysis package is contained within an easy-to-use graphical user interface. The program is based on the algorighm described in the following two publications: W.G. Breiland and K.P. Killen, J. Appl. Phys. 78 (1995) 6726, and W. G. Breiland, H.Q. Hou, B.E. Hammons, and J.F. Klem, Proc. XXVIII SOTAPOCS Symp. Electrochem. Soc. San Diego, May 3-8, 1998. It relies on the fact that any multiple-layer system has a reflectance spectrum that is mathematically equivalent to a single-layer thin film on a virtual substrate. The program fits the thin film reflectance with five adjustable parameters: 1) growth rate, 2) real part of complex refractive index, 3) imaginary part of refractive index, 4) amplitude of virtual interface reflectance, 5) phase of virtual interface reflectance.« less

  10. The Imaging Properties of a Silicon Wafer X-Ray Telescope

    NASA Technical Reports Server (NTRS)

    Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

    1994-01-01

    Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

  11. Porous solid ion exchange wafer for immobilizing biomolecules

    DOEpatents

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  12. Metal-assisted homogeneous etching of single crystal silicon: A novel approach to obtain an ultra-thin silicon wafer

    NASA Astrophysics Data System (ADS)

    Bai, Fan; Li, Meicheng; Song, Dandan; Yu, Hang; Jiang, Bing; Li, Yingfeng

    2013-05-01

    Homogeneous etching of silicon is achieved through one-step metal-assisted chemical etching (MACE), which offers a simple route to obtain the ultra-thin silicon wafer with thickness below 50 ?m. The surface of the ultra-thin silicon wafer obtained by this method is smooth at the nanometer scale, and its surface roughness is around 10 nm. The homogenous etching mechanism is discussed in terms of the hole injection principle. It's found that the introduction of a high concentration of H2O2 facilitates the uniform distribution of the holes injected on the silicon surface, causing the homogeneous etching of the silicon. Meanwhile, the thinning is uniform across a large wafer area, and ultra thin silicon wafers up to 4 in. in diameter were obtained. Furthermore, any thickness of silicon wafer within 30-180 ?m can be obtained by modulating the etching process accurately.

  13. Improvement of focus accuracy on processed wafer

    NASA Astrophysics Data System (ADS)

    Higashibata, Satomi; Komine, Nobuhiro; Fukuhara, Kazuya; Koike, Takashi; Kato, Yoshimitsu; Hashimoto, Kohji

    2013-04-01

    As feature size shrinkage in semiconductor device progress, process fluctuation, especially focus strongly affects device performance. Because focus control is an ongoing challenge in optical lithography, various studies have sought for improving focus monitoring and control. Focus errors are due to wafers, exposure tools, reticles, QCs, and so on. Few studies are performed to minimize the measurement errors of auto focus (AF) sensors of exposure tool, especially when processed wafers are exposed. With current focus measurement techniques, the phase shift grating (PSG) focus monitor 1) has been already proposed and its basic principle is that the intensity of the diffraction light of the mask pattern is made asymmetric by arranging a π/2 phase shift area on a reticle. The resist pattern exposed at the defocus position is shifted on the wafer and shifted pattern can be easily measured using an overlay inspection tool. However, it is difficult to measure shifted pattern for the pattern on the processed wafer because of interruptions caused by other patterns in the underlayer. In this paper, we therefore propose "SEM-PSG" technique, where the shift of the PSG resist mark is measured by employing critical dimension-scanning electron microscope (CD-SEM) to measure the focus error on the processed wafer. First, we evaluate the accuracy of SEM-PSG technique. Second, by applying the SEM-PSG technique and feeding the results back to the exposure, we evaluate the focus accuracy on processed wafers. By applying SEM-PSG feedback, the focus accuracy on the processed wafer was improved from 40 to 29 nm in 3σ.

  14. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

  15. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y.; James, Ralph B.

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  16. Integrating III-V compound semiconductors with silicon using wafer bonding

    NASA Astrophysics Data System (ADS)

    Zhou, Yucai

    2000-12-01

    From Main Street to Wall Street, everyone has felt the effects caused by the Internet revolution. The Internet has created a new economy in the New Information Age and has brought significant changes in both business and personal life. This revolution has placed strong demands for higher bandwidth and higher computing speed due to high data traffic on today's information highway. In order to alleviate this problem, growing interconnection bottlenecks in digital designs have to be solved. The most feasible and practical way is to replace the conventional electrical interconnect with an optical interconnect. Since silicon does not have the optical properties necessary to accommodate these optical interconnect requirements, III-V based devices, most of which are GaAs-based or InP-based, must be intimately interconnected with the Si circuit at chip level. This monolithic integration technology enables the development of both intrachip and interchip optical connectors to take advantage of the enormous bandwidth provided by both high-performance very-large-scale integrated (VLSI) circuits and allied fiber and free-space optical technologies. However, lattice mismatch and thermal expansion mismatches between III-V materials and Si create enormous challenges for developing a feasible technology to tackle this problem. Among all the available approaches today, wafer bonding distinguishes itself as the most promising technology for integration due to its ability to overcome the constraints of both lattice constant mismatch and thermal expansion coefficient differences and even strain due to the crystal orientation. We present our development of wafer bonding technology for integrating III-V with Si in my dissertation. First, the pick-and-place multiple-wafer bonding technology was introduced. Then we systematically studied the wafer bonding of GaAs and InP with Si. Both high temperature wafer fusion and low/room temperature (LT/RT) wafer bonding have been investigated for different applications. We also systematically studied the electrical properties of bonding interfaces for high temperature wafer fusion of GaAs/Si and InP/Si. Room temperature and low temperature wafer bonding technology has been invented primarily for bonding GaAs with Si due to larger thermal expansion coefficient mismatches. Finally, we showed the feasibility and practicality of our wafer bonding technologies by fabricating high performance devices. A high performance InP-based avalanche photodetector on Si was fabricated utilizing the high temperature wafer fusion of InP and Si. And a 0.85 μm GaAs-based vertical cavity surface emitting lasers (VCSELs) were fabricated by utilizing the low temperature wafer bonding of GaAs and Si.

  17. A Transdermal Drug Delivery System Based on LIGA Technology and Soft Lithography

    NASA Astrophysics Data System (ADS)

    Matteucci, Marco; Perennes, Frederic; Marmiroli, Benedetta; Di Fabrizio, Enzo

    2007-01-01

    This report presents a transdermal drug delivery system based on LIGA fabricated microparts. It is a portable device combining a magnetically actuated micro gear pump with a microneedle array. The fluidic behaviour of the system is analyzed in order to predict its performance according to the dimension of the microparts and then compared to experimental data. The manufacturing process of both micropump and microneedle array are described.

  18. Diamond-like nanocomposite coatings for LIGA-fabricated nickel alloy parts.

    SciTech Connect

    Prasad, Somuri V.; Scharf, Thomas W.

    2005-03-01

    A commercial plasma enhanced chemical vapor deposition (PECVD) technique with planetary substrate rotation was used to apply a thin (200-400 nm thick) conformal diamond-like carbon (DLC) coating (known as a diamond-like nanocomposite (DLN)) on LIGA fabricated Ni-Mn alloy parts. The PECVD technique is known to overcome the drawbacks associated with the line-of-sight nature of physical vapor deposition (PVD) and substrate heating inherent with traditional chemical vapor deposition (CVD). The purpose of the present study is to characterize the coverage, adhesion, and tribological (friction and wear) behavior of DLN coatings applied to planar and sidewall surfaces of small featured LIGA Ni-Mn fabricated parts, e.g. 280 {micro}m thick sidewalls. Friction and wear tests were performed in dry nitrogen, dry air, and air with 50% RH at Hertzian contact pressures ranging from 0.3 to 0.6 GPa. The friction coefficient of bare Ni-Mn alloy was determined to be 0.9. In contrast, low friction coefficients ({approx}0.02 in dry nitrogen and {approx}0.2 in 50% RH air) and minimal amount of wear were exhibited for the DLN coated LIGA Ni-Mn alloy parts and test coupons. This behavior was due to the ability of the coating to transfer to the rubbing counterface providing low interfacial shear at the sliding contact; resultantly, coating one surface was adequate for low friction and wear. In addition, a 30 nm thick titanium bond layer was determined to be necessary for good adhesion of DLN coating to Ni-Mn alloy substrates. Raman spectroscopy and cross-sectional SEM with energy dispersive x-ray analysis revealed that the DLN coatings deposited by the PECVD with planetary substrate rotation covered both the planar and sidewall surfaces of LIGA fabricated parts, as well as narrow holes of 300 {micro}m (0.012 inch) diameter.

  19. LigaSure meets endobronchial valve in a case of lung cancer with pneumoconiosis

    PubMed Central

    Fiorelli, Alfonso; Accardo, Marina; Vicidomini, Giovanni

    2013-01-01

    Resection of lung cancer associated with pneumoconiosis may be difficult since fibrosis limits the exposure of hilum, and the use of stapler; yet, surgery may be complicated by persistent air leaks due to the underlying disease. In this setting, LigaSure was used to perform the tumor resection, and the postoperative treatment of air leaks in the same patient was treated with placement of endobronchial valves. PMID:25806247

  20. LigaSure meets endobronchial valve in a case of lung cancer with pneumoconiosis.

    PubMed

    Fiorelli, Alfonso; Accardo, Marina; Vicidomini, Giovanni; Santini, Mario

    2013-08-01

    Resection of lung cancer associated with pneumoconiosis may be difficult since fibrosis limits the exposure of hilum, and the use of stapler; yet, surgery may be complicated by persistent air leaks due to the underlying disease. In this setting, LigaSure was used to perform the tumor resection, and the postoperative treatment of air leaks in the same patient was treated with placement of endobronchial valves. PMID:25806247

  1. Effectiveness of the LigaSure Small Jaw Vessel-Sealing System in Hepatic Resection

    PubMed Central

    Yoshimoto, Miwa; Endo, Kanenori; Hanaki, Takehiko; Watanabe, Joji; Tokuyasu, Naruo; Sakamoto, Teruhisa; Honjo, Soichiro; Hirooka, Yasuaki; Ikeguchi, Masahide

    2014-01-01

    Background In hepatic resection for liver tumors, reducing operation time and blood loss are important for postsurgical complication prevention. This study aimed to compare the safety and efficacy of the LigaSure Small Jaw (Covidien, Boulder, CO) with those of the Cavitation Ultrasonic Surgical Aspirator (CUSA) system (Integra Life Sciences, Plainsboro, NJ) in hepatic surgery. Methods We enrolled 102 patients with liver tumors, of whom 51 underwent liver resection with the CUSA (CUSA group) between March 2004 and April 2011. Another 51 underwent resection with the LigaSure Small Jaw (LS group) between June 2011 and July 2012. We stratified patients by time period depending on the instrument used, and compared operative duration; intraoperative bleeding; and postoperative liver function and complication rate. Results Total operation time (mean ± SD) was significantly shorter in the LS group than in the CUSA group (358.8 ± 91.7 versus 460.6 ± 146.1 min, P < 0.001). Blood loss was not significantly different between the 2 groups. Frequency of postoperative complications was lower, but not significantly, in the LS group. Conclusion The LigaSure Small Jaw may allow a shorter total operative duration than the CUSA device. PMID:25324590

  2. A LigA Three-Domain Region Protects Hamsters from Lethal Infection by Leptospira interrogans

    PubMed Central

    Coutinho, Mariana L.; Choy, Henry A.; Kelley, Melissa M.; Matsunaga, James; Babbitt, Jane T.; Lewis, Michael S.; Aleixo, Jose Antonio G.; Haake, David A.

    2011-01-01

    The leptospiral LigA protein consists of 13 bacterial immunoglobulin-like (Big) domains and is the only purified recombinant subunit vaccine that has been demonstrated to protect against lethal challenge by a clinical isolate of Leptospira interrogans in the hamster model of leptospirosis. We determined the minimum number and location of LigA domains required for immunoprotection. Immunization with domains 11 and 12 was found to be required but insufficient for protection. Inclusion of a third domain, either 10 or 13, was required for 100% survival after intraperitoneal challenge with Leptospira interrogans serovar Copenhageni strain Fiocruz L1-130. As in previous studies, survivors had renal colonization; here, we quantitated the leptospiral burden by qPCR to be 1.2103 to 8105 copies of leptospiral DNA per microgram of kidney DNA. Although renal histopathology in survivors revealed tubulointerstitial changes indicating an inflammatory response to the infection, blood chemistry analysis indicated that renal function was normal. These studies define the Big domains of LigA that account for its vaccine efficacy and highlight the need for additional strategies to achieve sterilizing immunity to protect the mammalian host from leptospiral infection and its consequences. PMID:22180800

  3. Using wafer stacks as neutron monochromators

    NASA Astrophysics Data System (ADS)

    Vogt, T.; Passell, L.; Cheung, S.; Axe, J. D.

    1994-01-01

    A process to introduce a spatially homogeneous but anisotropic mosaic structure into thin, single-crystal wafers, which are then stacked and used as neutron monochromators, is described. The advantages compared to conventional techniques are good reproduceability, low cost and reduced risk of process failure. A focusing Ge(115) monochromator made from 24 wafer stacks was built for the high-resolution neutron powder diffractometer at the High Flux Beam Reactor at Brookhaven National Laboratory. Besides building "classical" monochromators for elastic neutron scattering experiments, individual wafers with a given peak reflectivity can be tilted with respect to each other to increase the reflected wavelength band Δλ/λ. Such "fanned" arrays present a competitive alternative to monochromators using highly-oriented pyrolitic graphite (HOPG).

  4. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  5. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  6. Thermal Behavior of Large-Diameter Silicon Wafers during High-Temperature Rapid Thermal Processing in Single Wafer Furnace

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Yokoyama, Ichiro; Kang, Kitaek; Takahashi, Nobuaki

    2002-07-01

    Thermal behavior of 200-mm- and 300-mm-diameter Si (100) wafers during high-temperature rapid thermal processing (RTP) in a single wafer furnace (SWF) is investigated as a function of temperature, pressure, process time, wafer handling method and speed. Significant elastic wafer shape deformation was observed during wafer temperature ramp-up. Slip generation was frequently observed in wafers processed above 1050°C. Size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in reducing defect generation during RTP at the given process conditions. Highly reproducible, slip-free RTP results were achieved in 200-mm- and 300-mm-diameter Si (100) wafers processed at 1100°C by optimizing the wafer handling method and speed.

  7. Methanol Steam Reformer on a Silicon Wafer

    SciTech Connect

    Park, H; Malen, J; Piggott, T; Morse, J; Sopchak, D; Greif, R; Grigoropoulos, C; Havstad, M; Upadhye, R

    2004-04-15

    A study of the reforming rates, heat transfer and flow through a methanol reforming catalytic microreactor fabricated on a silicon wafer are presented. Comparison of computed and measured conversion efficiencies are shown to be favorable. Concepts for insulating the reactor while maintaining small overall size and starting operation from ambient temperature are analyzed.

  8. Effects of cleaning procedures of silica wafers on their friction characteristics.

    PubMed

    Donose, Bogdan C; Taran, Elena; Vakarelski, Ivan U; Shinto, Hiroyuki; Higashitani, Ko

    2006-07-01

    Silicon wafers with thermal silicon oxide layers were cleaned and hydrophilized by three different methods: (1) the remote chemical analysis (RCA) wet cleaning by use of ammonia and hydrogen peroxide mixture solutions, (2) water-vapor plasma cleaning, and (3) UV/ozone combined cleaning. All procedures were found to remove effectively organic contaminations on wafers and gave identical characteristics of the contact angle, the surface roughness and the normal force interactions, measured by atomic force microscopy (AFM). However, it is found that wafers cleaned by the RCA method have several times larger friction coefficients than those cleaned by the plasma and UV/ozone methods. The difference was explained by the atomic-scale topological difference induced during the RCA cleaning. This study reveals the lateral force microscopy as a very sensitive method to detect the microstructure of surfaces. PMID:16473364

  9. Modeling and fabrication of micro 3K-2-type planetary gear reducer utilizing SU-8 photoresist as alternative LIGA technology

    NASA Astrophysics Data System (ADS)

    Zhang, Weiping; Chen, Wenyuan; Chen, Di; Chen, Xiaomei; Wu, Xiaosheng; Xu, Zhengfu

    2001-10-01

    The LIGA type process, utilizing SU-8 photoresist as alternative LIGA technology, can fabricate high aspect ratio microstructures without employing synchrotron light and suitable X-ray mask. Based on LIGA type process in this paper, detailed investigations of the modeling and fabrication of micro 3K-2 type planetary gear reducer, such as the modeling and design of micro reducer, CAD of micro gear mask, SU-8 UV photolithography, micro electroforming, micro molding, have been performed. And 400 um thickness sun gear, 400 um thickness planet gear, 200 um thickness fixed inner gear, and 200 um thickness rotary inner gear, whose teeth are 15,11,36,39 respectively, have been obtained. Utilizing these gears, the micro reducer whose modulus, outer diameter and velocity ratio are 0.03, 2mm, 44.2:1, has been assembled and applied in (phi) 2mm micro electro magnetic motor successfully.

  10. Effect of Substrate Configuration on the Grain Structure and Morphology of Electrodeposited Ni for Prototyping LIGA

    SciTech Connect

    Nacy Y. C. Yang

    2002-07-01

    Synchrotron X-ray lithographic molding of PMMA-Ti/Cu/Ti substrates has been developed and used in the electrodeposition of Ni microparts for prototype LIGA development at SNL, CA. Alternative molding processes that minimize x-ray beam line use and reduce processing time are of interest for the rapid fabrication of large quantities of microparts. The objective of this investigation is to examine, archive, and compare the grain structure and morphology of deposits produced from four different molding technologies currently under development. We conclude that deposit microstructure and uniformity are greatly influenced by substrate material and design configuration. The findings are summarized.

  11. A Wafer based W-band Phased Antenna Array

    NASA Astrophysics Data System (ADS)

    Kuo, Jerry Weiming

    A phased antenna array is a set of antennas that focuses radiating electromagnetic field with electronic steering of its main beam. Phased array has traditionally come with high development costs and hence is not widely used for more applications. The operation of phased array at W-band (94GHz) is also challenging since high frequency signal generation and reception is highly inefficient. The research goal of this work is to provide an integrated on-wafer solution to tackle these challenges. Novel techniques are integrated into a systematic solution in the following manner: First, a sub-harmonic mixing concept is introduced to ease W-band signal generation. Second, the phased array design is divided into different functional layers, and hence individual work could be collaboratively integrated. Finally, the direct implementation of phased array MMIC circuits through the wafer design limits the phase errors of the MMIC circuits and their connection circuits in a sub-micron scale, which is unprecedented in the traditional manufacturing style.

  12. Optical Cluster Eye fabricated on wafer-level

    NASA Astrophysics Data System (ADS)

    Meyer, Julia; Brückner, Andreas; Leitel, Robert; Dannberg, Peter; Bräuer, Andreas; Tünnermann, Andreas

    2011-08-01

    Wafer-level optics is considered as a cost-effective approach to miniaturized cameras, because fabrication and assembly are carried out for thousands of lenses in parallel. However, in most cases the micro-optical fabrication process is not mature enough to reach the required accuracy of the optical elements, which may have complex profiles and sags in the mm-scale. Contrary, the creation of microlens arrays is well controllable so that we propose a multi aperture system called ''Optical Cluster Eye'' which is based on conventional micro-optical fabrication techniques. The proposed multi aperture camera consists of many optical channels each transmitting a segment of the whole field of view. The design of the system provides the stitching of the partial images, so that a seamless image is formed and a commercially available image sensor can be used. The system can be fabricated on wafer-level with high yield due to small aperture diameters and low sags. The realized optics has a lateral size of 2.2 × 2.9 mm2, a total track length of 1.86 mm, and captures images at VGA video resolution.

  13. Optical Cluster Eye fabricated on wafer-level.

    PubMed

    Meyer, Julia; Brückner, Andreas; Leitel, Robert; Dannberg, Peter; Bräuer, Andreas; Tünnermann, Andreas

    2011-08-29

    Wafer-level optics is considered as a cost-effective approach to miniaturized cameras, because fabrication and assembly are carried out for thousands of lenses in parallel. However, in most cases the micro-optical fabrication process is not mature enough to reach the required accuracy of the optical elements, which may have complex profiles and sags in the mm-scale. Contrary, the creation of microlens arrays is well controllable so that we propose a multi aperture system called "Optical Cluster Eye" which is based on conventional micro-optical fabrication techniques. The proposed multi aperture camera consists of many optical channels each transmitting a segment of the whole field of view. The design of the system provides the stitching of the partial images, so that a seamless image is formed and a commercially available image sensor can be used. The system can be fabricated on wafer-level with high yield due to small aperture diameters and low sags. The realized optics has a lateral size of 2.2 × 2.9 mm2, a total track length of 1.86 mm, and captures images at VGA video resolution. PMID:21935117

  14. Whole wafer imprint patterning using step and flash imprint lithography: a manufacturing solution for sub-100-nm patterning

    NASA Astrophysics Data System (ADS)

    Lentz, David; Doyle, Gary; Miller, Mike; Schmidt, Gerald; Ganapathisuramanian, Maha; Lu, Xiaoming; Resnick, Doug; LaBrake, Dwayne L.

    2007-03-01

    Imprint lithography has been shown to be an effective technique for the replication of nano-scale features1. When the imprint material is a UV cross linkable liquid, it is possible to perform the patterning process at room temperature and ambient pressure, which enables good pattern fidelity, short processing times, and reduced process defectivity2. Imprinting whole wafers using drop on demand dispense techniques offers improved throughput and nanopatterning over wafer topography which can exceed 10 ?m. Template fabrication of arbitrary whole wafer patterns offers unique challenges for 1x feature fabrication. The resolution and pattern area of the imprint approach is strictly dependent on the ability to create a 1X master template. This paper provides a detailed description of whole wafer templates, imprint patterning processes, and etch processes that have been employed to create a whole wafer archetype process through hard mask patterning. Particular attention is given to high volume manufacturing focused on whole wafer template fabrication, throughput and pattern fidelity. Step and Flash Imprint Lithography (S-FIL TM) makes use of templates that can be fabricated with the same patterning and etch transfer processes that are used for manufacturing phase-shifting photo masks. In the case of whole wafer templates the master die pattern is fabricated using conventional techniques. The replicate template carries the full wafer die pattern imprinted by step and repeat using the master. The S-FIL/R process can be used for patterning the replicate template 3. The structure, pattern fidelity and critical dimension uniformity of the master and replicate templates and patterned wafer is shown to be within measurement errors.

  15. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.; St. Martin, Edward; Arora, Michelle; de la Garza, Linda

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  16. Innovative optical alignment technique for CMP wafers

    NASA Astrophysics Data System (ADS)

    Sugaya, Ayako; Kanaya, Yuho; Nakajima, Shinichi; Nagayama, Tadashi; Shiraishi, Naomasa

    2002-07-01

    Detecting position of the wafers such as after CMP process is critical theme of current and forthcoming IC manufacturing. The alignment system must be with high accuracy for any process. To satisfy such requirements, we have studied and analyzed factors that have made alignment difficult. From the result of the studies, we have developed new optical alignment techniques which improve the accuracy of FIA (alignment sensor of Nikon's NSR series) and examined them. The approaches are optimizing the focus position, developing an advanced algorithm for position detection, and selecting a suitable mark design. For experiment, we have developed the special wafers that make it possible to evaluate the influence of CMP processes. The experimental results show that the overlay errors decrease dramatically with the new alignment techniques. FIA with these new techniques will be much accurate and suitable alignment sensor for CMP and other processes of future generation ULSI production.

  17. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  18. Precipitating Chromium Impurities in Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Salama, A. M.

    1982-01-01

    Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

  19. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  20. Mask-to-wafer alignment system

    DOEpatents

    Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

    2003-11-04

    A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

  1. Wafer level test solutions for IR sensors

    NASA Astrophysics Data System (ADS)

    Giessmann, Sebastian; Werner, Frank-Michael

    2014-05-01

    Wafer probers provide an established platform for performing electrical measurements at wafer level for CMOS and similar process technologies. For testing IR sensors, the requirements are beyond the standard prober capabilities. This presentation will give an overview about state of the art IR sensor probing systems reaching from flexible engineering solutions to automated production needs. Cooled sensors typically need to be tested at a target temperature below 80 K. Not only is the device temperature important but also the surrounding environment is required to prevent background radiation from reaching the device under test. To achieve that, a cryogenic shield is protecting the movable chuck. By operating that shield to attract residual gases inside the chamber, a completely contamination-free test environment can be guaranteed. The use of special black coatings are furthermore supporting the removal of stray light. Typically, probe card needles are operating at ambient (room) temperature when connecting to the wafer. To avoid the entrance of heat, which can result in distorted measurements, the probe card is fully embedded into the cryogenic shield. A shutter system, located above the probe field, is designed to switch between the microscope view to align the sensor under the needles and the test relevant setup. This includes a completely closed position to take dark current measurements. Another position holds a possible filter glass with the required aperture opening. The necessary infrared sources to stimulate the device are located above.

  2. Wafer weak point detection based on aerial images or WLCD

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Philipp, Peter; Litt, Lloyd C.; Ackmann, Paul; Crell, Christian; Chen, Norman

    2015-10-01

    Aerial image measurement is a key technique for model based optical proximity correction (OPC) verification. Actual aerial images obtained by AIMS (aerial image measurement system) or WLCD (wafer level critical dimension) can detect printed wafer weak point structures in advance of wafer exposure and defect inspection. Normally, the potential wafer weak points are determined based on optical rule check (ORC) simulation in advance. However, the correlation to real wafer weak points is often not perfect due to the contribution of mask three dimension (M3D) effects, actual mask errors, and scanner lens effects. If the design weak points can accurately be detected in advance, it will reduce the wafer fab cost and improve cycle time. WLCD or AIMS tools are able to measure the aerial images CD and bossung curve through focus window. However, it is difficult to detect the wafer weak point in advance without defining selection criteria. In this study, wafer weak points sensitive to mask mean-to-nominal values are characterized for a process with very high MEEF (normally more than 4). Aerial image CD uses fixed threshold to detect the wafer weak points. By using WLCD through threshold and focus window, the efficiency of wafer weak point detection is also demonstrated. A novel method using contrast range evaluation is shown in the paper. Use of the slope of aerial images for more accurate detection of the wafer weak points using WLCD is also discussed. The contrast range can also be used to detect the wafer weak points in advance. Further, since the mean to nominal of the reticle contributes to the effective contrast range in a high MEEF area this work shows that control of the mask error is critical for high MEEF layers such as poly, active and metal layers. Wafer process based weak points that cannot be detected by wafer lithography CD or WLCD will be discussed.

  3. Dry Cleaning Technology of Silicon Wafer with a Line Beam for Semiconductor Fabrication by KrF Excimer Laser

    NASA Astrophysics Data System (ADS)

    Kim, Dae-Jin; Kim, Yong-Kee; Ryu, Je-Kil; Kim, Hyun-Jung

    2002-07-01

    The contaminants on a bare wafer or a patterned wafer can seriously impact the yield of manufacturing devices in semiconductor fabrication. In very large scale integrated circuit (VLSI) technology, as the device density increases, particularly for flat panel displays, the importance of cleaning also increases. The removal of particles and the Photoresist (PR) layer on a silicon wafer was investigated by a line beam of a KrF excimer laser in a cleanroom condition. This paper reports the effects of a high-energy laser beam onto the electrical, structural and morphological properties of the wafer and introduces a practical line beam laser cleaning method for particle removal and PR stripping. The removal of particles and the PR layer on a silicon wafer was performed using a KrF excimer laser in the cleanroom condition. The results of surface morphology were observed using a scanning electron microscope (SEM) and atomic force microscopy (AFM). The crystallization of the silicon wafer was observed by X-ray diffraction (XRD) studies. The electrical properties of the silicon wafer before and after laser irradiation were characterized by Hall measurements. The compositions of the PR covered wafers were determined by energy dispersive X-ray diffraction (EDX). The carrier concentration and resistivity of the bare silicon wafer were 1.4× 1015 cm-3 and 17.7 Ω{\\cdot}cm, respectively, before laser irradiation. The carrier concentration of the silicon wafers after laser irradiation was in the range of 1.1× 1015-1.6× 1015 cm-3, and the resistivity was in the range of 17.0-18.2 Ω{\\cdot}cm. The carrier concentration and resistivity of the bare silicon wafers were not changed even after high-energy laser irradiation of up to 600 mJ/cm2. After 6-pulse laser irradiation, the PR layer of 0.82 μm thickness was stripped perfectly with an energy density of 300 mJ/cm2 without the aid of any chemical or solvent. The ablation rates were 0.06 μm/pulse for 100 mJ/cm2, 0.10 μm/pulse for 200 mJ/cm2 and 0.13 μm/pulse for 300 mJ/cm2. Dry laser cleaning technology shows that particles and organic compounds, like PR, on the bare silicon wafer can be effectively removed without any damage to the silicon substrate.

  4. Equipment for On-Wafer Testing From 220 to 325 GHz

    NASA Technical Reports Server (NTRS)

    Samoska, Lorene; Peralta, Alejandro; Dawson, Douglas; Lee, Karen; Boll, Greg; Oleson, Chuck

    2006-01-01

    A system of electronic instrumentation, constituting the equivalent of a two-port vector network analyzer, has been developed for use in on-wafer measurement of key electrical characteristics of semiconductor devices at frequencies from 220 to 325 GHz. A prior system designed according to similar principles was reported in Equipment for On-Wafer Testing at Frequencies Up to 220 GHz (NPO-20760), NASA Tech Briefs, Vol. 25, No. 11 (November 2001), page 42. As one would expect, a major source of difficulty in progressing to the present higher-frequency-range system was the need for greater mechanical precision as wavelengths shorten into the millimeter range, approaching the scale of mechanical tolerances of prior systems. The system (see figure) includes both commercial off-the-shelf and custom equipment. As in the system of the cited prior article, the equipment includes test sets that are extended versions of commercial network analyzers that function in a lower frequency range. The extension to the higher frequency range is accomplished by use of custom frequency-extension modules that contain frequency multipliers and harmonic mixers. On-wafer measurement is made possible by waveguide wafer probes that were custom designed and built for this wavelength range, plus an on-wafer calibration substrate designed for use with these probes. In this case, the calibration substrate was specially fabricated by laser milling. The system was used to make the first on-wafer measurements of a semiconductor device in the frequency range from 220 to 320 GHz. Some of the measurement results showed that the device had gain.

  5. Acoustic emission monitoring during laser shock cleaning of silicon wafers

    NASA Astrophysics Data System (ADS)

    Kim, T.; Lee, J. M.; Cho, S. H.; Kim, T. H.

    2005-09-01

    A laser shock cleaning is a new dry cleaning methodology for the effective removal of submicron sized particles from solid surfaces. This technique uses a plasma shock wave produced by laser-induced air breakdown, which has applied to remove nano-scale silica particles from silicon wafer surfaces in this work. In order to characterize the laser shock cleaning process, acoustic waves generated during the shock process are measured in real time by a wide-band microphone and analyzed in the change of process parameters such as laser power density and gas species. It was found that the acoustic intensity is closely correlated with the shock wave intensity. From acoustic analysis, it is seen that acoustic intensity became stronger as incident laser power density increased. In addition, Ar gas has been found to be more effective to enhance the acoustic intensity, which allows higher cleaning performance compared with air or N 2 gas.

  6. Innovative metrology for wafer edge defectivity in immersion lithography

    NASA Astrophysics Data System (ADS)

    Pollentier, I.; Iwamoto, F.; Kocsis, M.; Somanchi, A.; Burkeen, F.; Vedula, S.

    2007-03-01

    In semiconductor manufacturing, the control of defects at the edge of the wafer is a key factor to keep the number of yielding die on a wafer as high as possible. Using dry lithography, this control is typically done by an edge bead removal (EBR) process, which is understood well. Immersion lithography however changes this situation significantly. During this exposure, the wafer edge is locally in contact with water from the immersion hood, and particles can then be transported back and forth from the wafer edge area to the scanner wafer stage. Materiel in the EBR region can also potentially be damaged by the dynamic force of the immersion hood movement. In this paper, we have investigated the impact of immersion lithography on wafer edge defectivity. In the past, such work has been limited to the inspection of the flat top part of the wafer edge, due to the inspection challenges at the curved wafer edge and lack of a comprehensive defect inspection solution. This study utilized KLA-Tencor's VisEdge, a new automated edge inspection system, that provides full wafer edge imaging (top, side, bottom) using laser-based optics and multi-sensor detection, and where defects of interest can be classified with Automated Defect Classification (ADC) software. Using the VisEdge technology, the impact from the immersion lithography towards wafer edge defectivity is investigated. The work revealed several key challenges to keep the wafer edge related defectivity under control : choice of resist, optimization of EBR recipes, scanner pollution and related memory effects, wafer handling, device processing, etc... Contributing to the understanding of the mechanisms of wafer edge related immersion defects and to the optimization the die yield level, this technology is believed to be important when the immersion processes are introduced in semiconductor manufacturing.

  7. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu-precipitates (upto 50 nm) compresses Si-lattice to facilitate Si-XII/III formations, i.e. high pressure ductile phases. Sweeping voltage measurements at a given load determine that Si lattice has to be stressed beyond 1 mN to complete the Si-I (semiconducting) to Si-II (ohmic) phase changes. Above 1 mN load DSB sample has a varistor-like behavior due to higher grain-boundary resistance from interfacial states. The precipitate defect structure stimulated stresses at the bulk Si lattice or grain boundary modify the rate of elastic energy release at the crack-tip and associated phase change and hardness values in response to external loading. The systematic approach in this thesis elucidates that the interfacial surface area between Si-lattice and precipitate plays pivotal role in defining extent of stresses in the silicon, i.e. smaller precipitates in higher densities are severe than few larger volume precipitates. The finding of high-pressure ductile phase formation during loading of compressed silicon structure has been suggested to PV industry as a prospective candidate for reducing the wafer breakage and allowing larger handling stresses.

  8. Electrooptic shutter devices utilizing PLZT ceramic wafers

    SciTech Connect

    Thornton, A.L.

    1981-01-01

    Optical transparency was achieved in lead zirconate-titanate ferroelectric ceramics by substituting moderate amounts of the element lanthanum (8 to 12%) for lead. These compositions exhibit the quadratic (Kerr) electrooptic effect. The excellent optical qualities of these materials (designated PLZT) has permitted the practical utilization of their electrooptic properties in a number of devices. All of these devices utilize the classic Kerr cell arrangement. A PLZT wafer with optical axis oriented at 45/sup 0/ with respect to the axes of polarization is sandwiched between crossed polarizers. Application of an electric field via an interdigital array of electrodes on opposing wafer surfaces forces the PLZT material into a tetragonal state with the resulting induced birefringence proportional to the square of the applied electric field. Hence, the electrooptic wafer provides a retardation of light so that a component is passed by the second crossed polarizer to achieve an ON or open state. Maximum transmission is achieved when the retardation is half-wave. Shutter devices developed by Sandia and those in continuing development are described with respect to operational characteristics and physical configuration. The devices range in size from very small apertures of 50 ..mu..m x 2 mm with center-to-center repeat dimensions of 125 ..mu..m - to very large - apertures of 15.2 cm in single pieces and mosaics with apertures of 15.2 cm x 20.3 cm. Major efforts have centered on shutter development for the protection of aircrew from eye-damaging weapon effects. Other devices are also described which: provide eye protection for welders, protect vidicon tubes, function as page composers for holographic memories serve as large aperture photographic shutters, provide stereoscopic three-dimensional TV displays, and serve as data links in a fiber-optic transmission path.

  9. Photoluminescence method of testing double heterostructure wafers

    SciTech Connect

    Besomi, P.R.; Wilt, D.P.

    1984-04-10

    Under photoluminescence (PL) excitation, the lateral spreading of photo-excited carriers can suppress the photoluminescence signal from double heterostructure (DH) wafers containing a p-n junction. In any DH with a p-n junction in the active layer, PL is suppressed if the power of the excitation source does not exceed a threshold value. This effect can be advantageously used for a nondestructive optical determination of the top cladding layer sheet conductance as well as p-n junction misplacement, important parameters for injection lasers and LEDs.

  10. Slip-Free Rapid Thermal Processing in Single Wafer Furnace

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-06-01

    Defect generation phenomena in Si wafers during atmospheric pressure rapid thermal processing (RTP) in a single wafer furnace (SWF) are investigated as a function of temperature, process time, wafer handling method and speed. The size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in controlling defect generation during RTP under given process conditions. Highly reproducible slip-free RTP results were achieved in 200-mm-diameter Si wafers processed at 1100°C for 60 s (up to 5 times) by optimizing the wafer handling method and speed.

  11. Resonance ultrasonic vibrations for crack detection in photovoltaic silicon wafers

    NASA Astrophysics Data System (ADS)

    Dallas, W.; Polupan, O.; Ostapenko, S.

    2007-03-01

    The resonance ultrasonic vibrations (RUV) technique is adapted for non-destructive crack detection in full-size silicon wafers for solar cells. The RUV methodology relies on deviation of the frequency response curve of a wafer, ultrasonically stimulated via vacuum coupled piezoelectric transducer, with a periphery crack versus regular non-cracked wafers as detected by a periphery mounted acoustic probe. Crack detection is illustrated on a set of cast wafers. We performed vibration mode identification on square-shaped production-grade Si wafers and confirmed by finite element analyses. The modelling was accomplished for the different modes of the resonance vibrations of a wafer with a periphery crack to assess the sensitivity of the RUV method relative to crack length and crack location.

  12. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  13. Desirable wafer edge flatness for CD control in photolithography

    NASA Astrophysics Data System (ADS)

    Fujisawa, Tadahito; Inoue, Soichi; Hagiwara, Tsuneyuki; Kennichi, Kodama; Kobayashi, Makoto; Okumura, Katsuya

    2003-06-01

    Desirable wafer edge flatness was investigated to obtain optimum free-standing wafer edge shape for photolithography. In order to obtain the criteria of free-standing edge shape, we clarified the desirable post-chuck flatness at edge sites in advance. We investigated a desirable free-standing wafer edge, taking into consideration both the wafer and wafer holder shape. Firstly, to obtain a desirable post-chuck wafer edge shape, the vicinity of wafer edge after chucking was modeled, and SFQR was simulated. Secondly, a shape in the vicinity of free-standing edge shape was modeled, and the edge flatness after chucking was simulated. And finally, the simulated flatness was compared with the desirable post-chucked wafer edge shape, and we could obtain desirable free-standing wafer edge shape. Individual measurement of the free-standing back-side and front-side surfaces as well as the thickness of the edge position was found to be necessary for accurate estimation of the post-chuck edge shape.

  14. Dominant factors of the laser gettering of silicon wafers

    SciTech Connect

    Bokhan, Yu. I. E-mail: yuibokhan@gmail.com; Kamenkov, V. S.; Tolochko, N. K.

    2015-02-15

    The laser gettering of silicon wafers is experimentally investigated. The typical gettering parameters are considered. The surfaces of laser-treated silicon wafers are investigated by microscopy. When studying the effect of laser radiation on silicon wafers during gettering, a group of factors determining the conditions of interaction between the laser beam and silicon-wafer surface and affecting the final result of treatment are selected. The main factors determining the gettering efficiency are revealed. Limitations on the desired value of the getter-layer capacity on surfaces with insufficiently high cleanness (for example, ground or matte) are established.

  15. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M.

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  16. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  17. Laser soft marking on silicon wafer

    NASA Astrophysics Data System (ADS)

    Khoong, L. E.; Lam, Y. C.; Zheng, H. Y.; Chen, X.

    2010-03-01

    A laser soft marking technique is developed for laser markings on a silicon wafer. Due to negligible surface modification, the laser soft wafer markings are invisible by naked eyes under room condition and are undetectable using sophisticated instruments. However, these laser markings are found to be visible to naked eyes through a differential condensation of water droplets on the laser-marked and unmarked silicon surfaces. To understand this phenomenon, a model is established to study the condensation of water droplets on laser-marked and unmarked silicon surfaces. Experimental observations and simulation results indicate that the laser soft marking could have modified the silicon surface with a thin polycrystalline silicon layer which has a much lower conductivity than the crystalline silicon. In addition, this thin layer exhibits a thermal conductivity which is approximately two orders of magnitude lower than that of its equivalent bulk material. As a result, heat transfer on the laser-marked silicon surface is much lower than the crystalline silicon and thus makes these laser soft markings easily visible visually under condensation.

  18. Diamond MEMS: wafer scale processing, devices, and technology insertion

    NASA Astrophysics Data System (ADS)

    Carlisle, J. A.

    2009-05-01

    Diamond has long held the promise of revolutionary new devices: impervious chemical barriers, smooth and reliable microscopic machines, and tough mechanical tools. Yet it's been an outsider. Laboratories have been effectively growing diamond crystals for at least 25 years, but the jump to market viability has always been blocked by the expense of diamond production and inability to integrate with other materials. Advances in chemical vapor deposition (CVD) processes have given rise to a hierarchy of carbon films ranging from diamond-like carbon (DLC) to vapor-deposited diamond coatings, however. All have pros and cons based on structure and cost, but they all share some of diamond's heralded attributes. The best performer, in theory, is the purest form of diamond film possible, one absent of graphitic phases. Such a material would capture the extreme hardness, high Young's modulus and chemical inertness of natural diamond. Advanced Diamond Technologies Inc., Romeoville, Ill., is the first company to develop a distinct chemical process to create a marketable phase-pure diamond film. The material, called UNCD® (for ultrananocrystalline diamond), features grain sizes from 3 to 300 nm in size, and layers just 1 to 2 microns thick. With significant advantages over other thin films, UNCD is designed to be inexpensive enough for use in atomic force microscopy (AFM) probes, microelectromechanical machines (MEMS), cell phone circuitry, radio frequency devices, and even biosensors.

  19. Fully-vectorial simulation and tolerancing of optical systems for wafer inspection by field tracing

    NASA Astrophysics Data System (ADS)

    Asoubar, Daniel; Schweitzer, Hagen; Hellmann, Christian; Kuhn, Michael; Wyrowski, Frank

    2015-06-01

    The simulation, design and tolerancing of optical systems for wafer inspection is a challenging task due to the different feature sizes, which are involved in these systems. On the one hand light is propagated through macroscopic lens systems and on the other hand light is diffracted at microscopic structures with features in the range of the wavelength of light. Due to this variety of scale plenty of different physical effects like refraction, diffraction, interference and polarization have to be taken into account for a realistic analysis of such inspection systems. We show that all of these effects can be included in a system simulation by field tracing, which combines physical and geometrical optics. The main idea is the decomposition of the complex optical setup in a sequence of subdomains. Per subdomain a different approximative or rigorous solution of Maxwell's equations is applied to propagate the light. In this work the different modeling techniques for the analysis of an exemplary wafer inspection system are discussed in detail. These techniques are mainly geometrical optics for the light propagation through macroscopic lenses, a rigorous Fourier Modal Method (FMM) for the modeling of light diffraction at the wafer microstructure and different free-space diffraction integrals. In combination with a numerically efficient algorithm for the coordinate transformation of electromagnetic fields, field tracing enables position and fabrication tolerancing. As an example different tilt tolerance effects on the polarization state and image contrast of a simple wafer inspection system are shown.

  20. "Performance Of A Wafer Stepper With Automatic Intra-Die Registration Correction."

    NASA Astrophysics Data System (ADS)

    van den Brink, M. A.; Wittekoek, S.; Linders, H. F. D.; van Hout, F. J.; George, R. A.

    1987-01-01

    An evaluation of a wafer stepper with the new improved Philips/ASM-L phase grating alignment system is reported. It is shown that an accurate alignment system needs an accurate X-Y-0 wafer stage and an accurate reticle Z stage to realize optimum overlay accuracy. This follows from a discussion of the overlay budget and an alignment procedure model. The accurate wafer stage permits high overlay accuracy using global alignment only, thus eliminating the throughput penalty of align-by-field schemes. The accurate reticle Z stage enables an intra-die magnification control with respect to the wafer scale. Various overlay data are reported, which have been measured with the automatic metrology program of the stepper. It is demonstrated that the new dual alignment system (with the external spatial filter) has improved the ability to align to weakly reflecting layers. The results are supported by a Fourier analysis of the alignment signal. Resolution data are given for the PAS 2500 projection lenses, which show that the high overlay accuracy of the system is properly matched with submicron linewidth control. The results of a recently introduced 20mm i-line lens with a numerical aperture of 0.4 (Zeiss 10-78-58) are included.

  1. LIGA fabrication of mm-wave accelerating cavity structures at the Advanced Photon Source (APS)

    SciTech Connect

    Song, J.J.; Bajikar, S.; Kang, Y.W.

    1997-08-01

    Recent microfabrication technologies based on the LIGA (German acronym for Lithographe, Galvanoformung, und Abformung) process have been applied to build high-aspect-ratio, metallic or dielectric planar structures suitable for high-frequency rf cavity structures. The cavity structures would be used as parts of linear accelerators, microwave undulators, and mm-wave amplifiers. The microfabrication process includes manufacture of precision x-ray masks, exposure of positive resist x-rays through the mask, resist development, and electroforming of the final microstructure. Prototypes of a 32-cell, 108-GHz constant-impedance cavity and a 66-cell, 94-GHz constant-gradient cavity were fabricated with the synchrotron radiation sources at APS and NSLS. This paper will present an overview of the new technology and details of the mm-wave cavity fabrication.

  2. Temperature rise of the silicon mask-PMMA resist assembly during LIGA exposure.

    SciTech Connect

    Ting, Aili

    2004-10-01

    Deep X-ray lithography on PMMA resist is used in the LIGA process. The resist is exposed to synchrotron X-rays through a patterned mask and then is developed in a liquid developer to make high aspect ratio microstructures. This work addresses the thermal analysis and temperature rise of the mask-resist assembly during exposure at the Advanced Light Source (ALS) synchrotron. The concern is that the thermal expansion will lower the accuracy of the lithography. We have developed a three-dimensional finite-element model of the mask and resist assembly. We employed the LIGA exposure-development software LEX-D and the commercial software ABAQUS to calculate heat transfer of the assembly during exposure. The calculations of assembly maximum temperature have been compared with temperature measurements conducted at ALS. The temperature rise in the silicon mask and the mask holder comes directly from the X-ray absorption, but forced convection of nitrogen jets carry away a significant portion of heat energy from the mask surface, while natural convection plays a negligible role. The temperature rise in PMMA resist is mainly from heat conducted from the silicon substrate backward to the resist and from the mask plate through inner cavity air forward to the resist, while the X-ray absorption is only secondary. Therefore, reduction of heat flow conducted from both substrate and cavity air to the resist is essential. An improved water-cooling block is expected to carry away most heat energy along the main heat conductive path, leaving the resist at a favorable working temperature.

  3. High-throughput automatic defect review for 300mm blank wafers with atomic force microscope

    NASA Astrophysics Data System (ADS)

    Zandiatashbar, Ardavan; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

    2015-03-01

    While feature size in lithography process continuously becomes smaller, defect sizes on blank wafers become more comparable to device sizes. Defects with nm-scale characteristic size could be misclassified by automated optical inspection (AOI) and require post-processing for proper classification. Atomic force microscope (AFM) is known to provide high lateral and the highest vertical resolution by mechanical probing among all techniques. However, its low throughput and tip life in addition to the laborious efforts for finding the defects have been the major limitations of this technique. In this paper we introduce automatic defect review (ADR) AFM as a post-inspection metrology tool for defect study and classification for 300 mm blank wafers and to overcome the limitations stated above. The ADR AFM provides high throughput, high resolution, and non-destructive means for obtaining 3D information for nm-scale defect review and classification.

  4. Surface activation enhanced low temperature silicon wafer bonding

    NASA Astrophysics Data System (ADS)

    Gan, Qing

    Direct wafer bonding technology has received great attention since 1985. It enables to realize the novel combinations of different materials for expanded functionality and provides a versatile device technology for transferring device layers to another wafer for further processing or device integration onto one wafer. Silicon direct wafer bonding has found a wide range of applications including Silicon-on-Insulator (SOI) wafers, micromechanical devices, and sensors and actuators. One of the challenges facing this technology is to achieve strong bonding at low temperatures that can survive post-wafer bonding processing. This dissertation presents the results of developing new wafer bonding processes for achieving high bonding energy at low temperatures. For thermal oxide covered silicon wafer bonding, dilute HF solution has been used to etch the wafers prior to room temperature bonding. The bonding energy has been significantly enhanced which reached silicon fracture energy after annealed at 100°C for 45 hours. For native oxide covered silicon wafers, the pre-treatment in dilute HNO3 and dilute HF mixtures has been found to be able to enhance the bonding energy at low temperatures. This is attributed to the incorporation of fluorine in native oxide during the pre-treatment. Various approaches have also been explored for hydrophobic silicon wafer bonding. Both boron doped surface layers and the amorphous surface layers have demonstrated an ability to significantly enhance the bonding energy at low temperatures, with silicon fracture energy achieved at 300--400°C for hydrophobically bonded pairs. The thermal management of heterojunction bipolar transistor (HBT) circuits fabricated by Symmetric Intrinsic HBT (SIHBT) processing was also studied in this research project using simulation method. Design criteria of selecting the surrogate substrates, interconnection dimension, and dielectric materials for the optimization of thermal management have been obtained.

  5. Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint

    SciTech Connect

    Rupnowski, P.; Sopori, B.

    2008-05-01

    This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

  6. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, Gary S.

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  7. Overlay Tolerances For VLSI Using Wafer Steppers

    NASA Astrophysics Data System (ADS)

    Levinson, Harry J.; Rice, Rory

    1988-01-01

    In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his merchandise appear as attractive as possible, the lithographer is frequently placed in the position of having to explain subtle issues in order to justify his decisions. It is the purpose of this paper to provide that explanation.

  8. Oral Immunization with Escherichia coli Expressing a Lipidated Form of LigA Protects Hamsters against Challenge with Leptospira interrogans Serovar Copenhageni

    PubMed Central

    Lourdault, Kristel; Wang, Long-Chieh; Vieira, Ana; Matsunaga, James; Melo, Rita; Lewis, Michael S.; Gomes-Solecki, Maria

    2014-01-01

    Leptospirosis is a potentially fatal zoonosis transmitted by reservoir host animals that harbor leptospires in their renal tubules and shed the bacteria in their urine. Leptospira interrogans serovar Copenhageni transmitted from Rattus norvegicus to humans is the most prevalent cause of urban leptospirosis. We examined L. interrogans LigA, domains 7 to 13 (LigA7-13), as an oral vaccine delivered by Escherichia coli as a lipidated, membrane-associated protein. The efficacy of the vaccine was evaluated in a susceptible hamster model in terms of the humoral immune response and survival from leptospiral challenge. Four weeks of oral administration of live E. coli expressing LigA7-13 improved survival from intraperitoneal (i.p.) and intradermal (i.d.) challenge by L. interrogans serovar Copenhageni strain Fiocruz L1-130 in Golden Syrian hamsters. Immunization with E. coli expressing LigA7-13 resulted in a systemic antibody response, and a significant LigA7-13 IgG level after the first 2 weeks of immunization was completely predictive of survival 28 days after challenge. As in previous LigA vaccine studies, all immunized hamsters that survived infection had renal leptospiral colonization and histopathological changes. In summary, an oral LigA-based vaccine improved survival from leptospiral challenge by either the i.p. or i.d. route. PMID:24478102

  9. Backside EBR process performance with various wafer properties

    NASA Astrophysics Data System (ADS)

    Goto, Tomohiro; Shigemori, Kazuhito; Vangheluwe, Rik; Erich, Daub; Sanada, Masakazu

    2009-03-01

    In immersion lithography process, film stacking architecture will be necessary to avoid top coat film peeling. To achieve suitable stacking architecture for immersion lithography process, an EBR process that delivers tightly controlled film edge position and good uniformity around the wafer circumference is needed. We demonstrated a new bevel rinse system on a SOKUDO RF3 coat-and-develop track for immersion lithography. The performance of the new bevel rinse system for various wafer properties was evaluated. It was found that the bevel rinse system has a good controllability of film edge position and good uniformity around the wafer circumference. The results indicate that the bevel rinse system has a large margin for wafer centering accuracy, back side particles, wafer shape and substrates with good film edge position controllability, uniformity and clean apex. The system has been demonstrated to provide a suitable film stacking architecture for immersion lithography mass production process.

  10. Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage.

    PubMed

    Rack, Alexander; Scheel, Mario; Danilewsky, Andreas N

    2016-03-01

    Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1-2 ms followed by jumps faster than 2-6 m s(-1), leading to a macroscopically observed average velocity of 0.028-0.055 m s(-1). The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound. PMID:27006774

  11. Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage

    PubMed Central

    Rack, Alexander; Scheel, Mario; Danilewsky, Andreas N.

    2016-01-01

    Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1–2 ms followed by jumps faster than 2–6 m s−1, leading to a macroscopically observed average velocity of 0.028–0.055 m s−1. The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound. PMID:27006774

  12. Thermal spray and cold spray analysis of density, porosity, and tensile Specimens for use with LIGA applications

    SciTech Connect

    DECKER,MERLIN K.; SMITH,MARK F.

    2000-02-01

    This analysis provides a preliminary investigation into using Twin-Wire Arc Thermal Spray and Cold Spray as material deposition processes for LIGA applications. These spray material processes were studied to make an initial determination of their potential as alternatives to producing mechanical parts via the electroplating process. Three materials, UltraMachinable{reg_sign} Stainless Steel, BondArc{reg_sign}, and aluminum, were sprayed using Thermal Spray. Only aluminum was sprayed using the Cold Spray process. Following the spray procedure, the test specimens were released from a copper mold and then tested. Three tests, density, tensile strength, and porosity, were performed on the specimens to determine the spray effect on material properties. Twin-Wire Arc Thermal Spray did not demonstrate adequate deposition properties and does not appear to be a good process candidate for LIGA. However, Cold Spray yielded better density results and warrants further investigation to analyze the minimum feature size produced by the process.

  13. Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

    2014-01-01

    This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

  14. Phoradendron liga (Gill. ex H. et A.) Eichl. (Viscaceae) used in folk medicine: anatomical, phytochemical, and immunochemical studies.

    PubMed

    Varela, Beatriz G; Fernández, Teresa; Ricco, Rafael A; Zolezzi, Paula Cerdá; Hajos, Silvia E; Gurni, Alberto A; Alvarez, Elida; Wagner, Marcelo L

    2004-09-01

    Phoradendron liga (Gill. ex H. et A.) Eichl. is a Viscaceae widely distributed in Argentina. It has been commonly used in folk medicine as a substitute of the European mistletoe (Viscum album L.) to decrease high blood pressure due to their external similarity. In this study, the anatomical features as well as micromolecular and macromolecular analysis of this species are reported. Anatomical study has shown that Phoradendron liga presents as anatomic features: papillous cuticle, clusters in leaves and stems, and isodiametric stone cells only in stems. The analysis of flavonoids showed that this species produces C-glycosylflavones and 3-desoxyproanthocyanidins. Protein study showed a protein pattern with components ranging from 14 to 90 kDa and the presence of related epitopes between the species was demonstrated by cross recognition using anti-Phoradendron and anti-Viscum antisera of both species by Western blot assay. In addition, a galactose specific lectin (L-Phl) was isolated form Phoradendron liga extracts. These results are part of a comprehensive project on Argentine hemiparasite species destinated to be applied to quality control of commercial samples and disclosed their potential use as a potential source for immunomodulatory compounds. PMID:15261970

  15. Direct Simulation Monte Carlo (DSMC) of rarefied gas flow during etching of large diameter (300-mm) wafers

    SciTech Connect

    Economou, D.J.; Bartel, T.J.

    1996-02-01

    As microelectronic devices are scaled down to enhance functionality and speed, wafer size increases to accommodate the larger dice and improve throughput. For example, the wafer diameter is projected to increase from the current 200 to 300 mm by the year 2001. Uniform deposition and etching of thin films over these large diameter wafers is of major concern to the microelectronics industry. Also, flat panel display and solar conversion technologies require uniform processing over large area substrates. Computer simulation can provide valuable insight concerning the physicochemical processes occurring in the reactor and can be used as a guide to new reactor designs that deliver uniform etching or deposition. Strong density gradients of a gas species can be sustained even at very low pressures when the reaction probability of that species is high. Under these conditions, inlet gas arrangements are very important to reaction uniformity.

  16. Study of temperature distributions in wafer exposure process

    NASA Astrophysics Data System (ADS)

    Lin, Zone-Ching; Wu, Wen-Jang

    During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

  17. Optima XE Single Wafer High Energy Ion Implanter

    SciTech Connect

    Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny

    2008-11-03

    The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

  18. Development of optical automatic positioning and wafer defect detection system

    NASA Astrophysics Data System (ADS)

    Tien, Chuen-Lin; Lai, Qun-Huang; Lin, Chern-Sheng

    2016-02-01

    The data of a wafer with defects can provide engineers with very important information and clues to improve the yield rate and quality in manufacturing. This paper presents a microscope automatic positioning and wafer detection system with human-machine interface based on image processing and fuzzy inference algorithms. In the proposed system, a XY table is used to move the position of each die on 6 inch or 8 inch wafers. Then, a high-resolution CCD and one set of two-axis optical linear encoder are used to accurately measure the position on the wafer. Finally, the developed human-machine interface is used to display the current position of an actual wafer in order to complete automatic positioning, and a wafer map database can be created. In the process of defect detection, CCD is used for image processing, and during preprocessing, it is required to filter noise, acquire the defect characteristics, define the defective template, and then take the characteristic points of the defective template as the reference input for fuzzy inference. A high-accuracy optical automatic positioning and wafer defect detection system is thus constructed. This study focused on automatic detection of spots, scratches, and bruises, and attempted to reduce the time to detect defective die and improve the accuracy of determining the defects of semiconductor devices.

  19. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    NASA Astrophysics Data System (ADS)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

    2016-03-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

  20. Applications of atomic force microscopy for silicon wafer characterization

    SciTech Connect

    Suhren, M.; Graef, D.; Schmolke, R.; Piontek, H.; Wagner, P.

    1996-12-01

    AFM (Atomic Force Microscopy) is a highly sensitive tool for the analysis of the microroughness of Si wafers and for the investigation of crystal defects. AFM images of atomic steps were used for verification of the vertical AFM calibration on slightly misoriented Si(111) wafers after chemical etching and epitaxial deposition. The roughness analysis of etched, polished and epitaxial Si(100) wafers shows a reduction of the surface roughness by chemomechanical polishing by more than two orders of magnitude compared to an etched surface. The morphology of crystal originated particles on Si(100) appears as smooth surface depression after polishing and sharply defined pit after SCI treatment.

  1. Analysis of the interdigitated back contact solar cells: The n-type substrate lifetime and wafer thickness

    NASA Astrophysics Data System (ADS)

    Zhang, Wei; Chen, Chen; Jia, Rui; Sun, Yun; Xing, Zhao; Jin, Zhi; Liu, Xin-Yu; Liu, Xiao-Wen

    2015-10-01

    The n-type silicon integrated-back contact (IBC) solar cell has attracted much attention due to its high efficiency, whereas its performance is very sensitive to the wafer of low quality or the contamination during high temperature fabrication processing, which leads to low bulk lifetime τbulk. In order to clarify the influence of bulk lifetime on cell characteristics, two-dimensional (2D) TCAD simulation, combined with our experimental data, is used to simulate the cell performances, with the wafer thickness scaled down under various τbulk conditions. The modeling results show that for the IBC solar cell with high τbulk, (such as 1 ms-2 ms), its open-circuit voltage Voc almost remains unchanged, and the short-circuit current density Jsc monotonically decreases as the wafer thickness scales down. In comparison, for the solar cell with low τbulk (for instance, < 500 μs) wafer or the wafer contaminated during device processing, the Voc increases monotonically but the Jsc first increases to a maximum value and then drops off as the wafer’s thickness decreases. A model combing the light absorption and the minority carrier diffusion is used to explain this phenomenon. The research results show that for the wafer with thinner thickness and high bulk lifetime, the good light trapping technology must be developed to offset the decrease in Jsc. Project supported by the Chinese Ministry of Science and Technology Projects (Grant Nos. 2012AA050304 and Y0GZ124S01), the National Natural Science Foundation of China (Grant Nos. 11104319, 11274346, 51202285, 51402347, and 51172268), and the Fund of the Solar Energy Action Plan from the Chinese Academy of Sciences (Grant Nos. Y3ZR044001 and Y2YF014001).

  2. Extraction and Analysis of Noise Parameters of On Wafer HEMTs up to 26.5 GHz

    SciTech Connect

    Caddemi, Alina; Crupi, Giovanni; Macchiarella, Alessio

    2009-04-23

    This paper presents a procedure for extracting the four noise parameters of on wafer scaled HEMTs based on AlGaAs/GaAs heterostructure. This procedure relies on 50-{omega} noise figure measurements up to 26.5 GHz by determining the equivalent temperatures associated to the intrinsic resistances of the small signal equivalent circuit. The non-quasi-static effect associated to the gate-drain resistance R{sub gd} is accounted for by the noise model. A good agreement between measured and simulated noise figure is obtained and scaling of the noise parameters is reported.

  3. Optoelectronic interconnects for 3D wafer stacks

    NASA Astrophysics Data System (ADS)

    Ludwig, David E.; Carson, John C.; Lome, Louis S.

    1996-01-01

    Wafer and chip stacking are envisioned as a means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper provides definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies are discussed.

  4. ELID supported grinding of thin sapphire wafers

    NASA Astrophysics Data System (ADS)

    Makarenko, Igor; Vogt, Christian; Rascher, Rolf; Sperber, Peter; Stirner, Thomas

    2010-10-01

    Sapphire material is, due to its crystal structure, difficult to machine in an economic way. There is a request for thin, i.e. below 0.2 mm thickness, sub surface damage free wafers to produce sensor elements. ELID -- electrolytic in process dressing -- is an innovative high end grinding technology, using small grain sizes, which enable to manufacture surfaces in a quality that is close to polished. ELID grinding requires exactly aligned machining parameters of the grinding process. To grind sapphire the material's behavior is additionally to be considered. Studies on the necessary oxide layer on the grinding wheel and influences on its build-up process will be presented. The presentation shows the results of comparing grinding experiments on different -- c-plane and r-plane -- sapphire materials. Different tool specifications are used. Infeed and grinding velocity are varied and the results on wear, removal rate and surface quality are shown. The process parameters the stiffness of the machine, the grinding forces and pressure are evaluated. The ELID grinding is compared in its results to conventional grinding steps. The material removal rate on sapphire is relatively small due to the extreme hardness of sapphire. The achieved excellent surface roughness will be discussed.

  5. The influence of feature sidewall tolerance on minimum absorber thickness for LIGA x-ray masks

    SciTech Connect

    S. K. Griffiths; J. M. Hruby; A. Ting

    1999-02-01

    Minimizing mask absorber thickness is an important practical concern in producing very small features by the LIGA process. To assist in this minimization, the authors have developed coupled numerical models describing both the exposure and development of a thick PMMA resist. The exposure model addresses multi-wavelength, one-dimensional x-ray transmission through multiple beam filters, through the mask substrate and absorber, and the subsequent attenuation and photon absorption in the PMMA resist. The development model describes one-dimensional dissolution of a feature and its sidewalls, taking into account the variation in absorbed dose through the PMMA thickness. These exposure and development models are coupled in a single interactive code, permitting the automated adjustment of mask absorber thickness to yield a prescribed sidewall taper or dissolution distance. They have used this tool to compute the minimum required absorber thickness yielding a prescribed sidewall tolerance for exposures performed at the ALS, SSRL and NSLS synchrotron sources. Results are presented as a function of the absorbed dose for a range of the prescribed sidewall tolerance, feature size, PMMA thickness, mask substrate thickness and the development temperature.

  6. Dimensional errors in LIGA-produced metal structures due to thermal expansion and swelling of PMMA.

    SciTech Connect

    Kistler, Bruce L.; Dryden, Andrew S.; Crowell, Jeffrey A.W.; Griffiths, Stewart K.

    2004-04-01

    Numerical methods are used to examine dimensional errors in metal structures microfabricated by the LIGA process. These errors result from elastic displacements of the PMMA mold during electrodeposition and arise from thermal expansion of the PMMA when electroforming is performed at elevated temperatures and from PMMA swelling due to absorption of water from aqueous electrolytes. Both numerical solutions and simple analytical approximations describing PMMA displacements for idealized linear and axisymmetric geometries are presented and discussed. We find that such displacements result in tapered metal structures having sidewall slopes up to 14 {micro}m per millimeter of height for linear structures bounded by large areas of PMMA. Tapers for curved structures are of similar magnitude, but these structures are additionally skewed from the vertical. Potential remedies for reducing dimensional errors are also discussed. Here we find that auxiliary moat-like features patterned into the PMMA surrounding mold cavities can reduce taper by an order of magnitude or more. Such moats dramatically reduce tapers for all structures, but increase skew for curved structures when the radius of curvature is comparable to the structure height.

  7. Efficient data transmission from silicon wafer strip detectors

    SciTech Connect

    Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

    1991-12-31

    An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

  8. 9nm node wafer defect inspection using visible light

    NASA Astrophysics Data System (ADS)

    Zhou, Renjie; Edwards, Chris; Popescu, Gabriel; Goddard, Lynford L.

    2014-04-01

    Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

  9. Proceedings of the Low-Cost Solar Array Wafering Workshop

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1982-01-01

    The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

  10. Stress rate and proof-testing of silicon wafers

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1985-01-01

    Fracture mechanics test methods were applied to evaluate the proof-test characteristics of single-crystal silicon wafers. The results indicate that the strength distribution of silicon wafers is truncated by proof-testing. No subcritical crack growth occurred during proof-loading, as inferred from the lack of a stress-rate effect on strength. Mechanical proof-testing appears to be an effective method for eliminating weak samples before cell processing.

  11. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2008-10-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  12. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  13. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-03-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  14. Epitaxial silicon carbide on a 6″ silicon wafer

    NASA Astrophysics Data System (ADS)

    Kukushkin, S. A.; Lukyanov, A. V.; Osipov, A. V.; Feoktistov, N. A.

    2014-01-01

    The results of the growth of silicon-carbide films on silicon wafers with a large diameter of 150 mm (6″) by using a new method of solid-phase epitaxy are presented. A SiC film growing on Si wafers was studied by means of spectral ellipsometry, SEM, X-ray diffraction, and Raman scattering. As follows from the studies, SiC layers are epitaxial over the entire surface of a 150-mm wafer. The wafers have no mechanical stresses, are smooth, and do not have bends. The half-width of the X-ray rocking curve (FWHMω- θ) of the wafers varies in the range from 0.7° to 0.8° across the thickness layer of 80-100 nm. The wafers are suitable as templates for the growth of SiC, AlN, GaN, ZnO, and other wide-gap semiconductors on its surface using standard CVD, HVPE, and MBE methods.

  15. Strategy optimization for mask rule check in wafer fab

    NASA Astrophysics Data System (ADS)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  16. Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis

    SciTech Connect

    Tobin, K.W.

    2003-05-22

    This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

  17. Fine Mapping of the Interaction between C4b-Binding Protein and Outer Membrane Proteins LigA and LigB of Pathogenic Leptospira interrogans.

    PubMed

    Breda, Leandro C D; Hsieh, Ching-Lin; Castiblanco Valencia, Mónica M; da Silva, Ludmila B; Barbosa, Angela S; Blom, Anna M; Chang, Yung-Fu; Yung-Fu, Chang; Isaac, Lourdes

    2015-01-01

    The complement system consists of more than 40 proteins that participate in the inflammatory response and in pathogen killing. Complement inhibitors are necessary to avoid the excessive consumption and activation of this system on host cells. Leptospirosis is a worldwide zoonosis caused by spirochetes from the genus Leptospira. Pathogenic leptospires are able to escape from complement activation by binding to host complement inhibitors Factor H [FH] and C4b-binding protein (C4BP) while non-pathogenic leptospires are rapidly killed in the presence of fresh serum. In this study, we demonstrate that complement control protein domains (CCP) 7 and 8 of C4BP α-chain interact with the outer membrane proteins LcpA, LigA and LigB from the pathogenic leptospire L. interrogans. The interaction between C4BP and LcpA, LigA and LigB is sensitive to ionic strength and inhibited by heparin. We fine mapped the LigA and LigB domains involved in its binding to C4BP and heparin and found that both interactions are mediated through the bacterial immunoglobulin-like (Big) domains 7 and 8 (LigA7-8 and LigB7-8) of both LigA and LigB and also through LigB9-10. Therefore, C4BP and heparin may share the same binding sites on Lig proteins. PMID:26517116

  18. Comparison and Efficacy of LigaSure and Rubber Band Ligature in Closing the Inflamed Cecal Stump in a Rat Model of Acute Appendicitis

    PubMed Central

    Yeh, Chun-Chieh; Jan, Chia-Ing; Yang, Horng-Ren; Jeng, Long-Bin; Su, Wen-Pang

    2015-01-01

    Safety of either LigaSure or rubber band in closing inflamed appendiceal stump in acute appendicitis has been less investigated. In this study, cecal ligation followed by resecting inflamed cecum was performed to mimic appendectomy in a rat model of acute appendicitis. Rats were sacrificed immediately (Group A) and 7 days (Group B) after cecal resection, respectively. The cecal stumps were closed by silk ligature (S), 5 mm LigaSure (L), or rubber band (R). Seven days after cecal resection, the LigaSure (BL) and silk subgroups (BS) had significantly less intra-abdominal adhesion and better laparotomy wound healing than rubber band subgroup (BR). The initial bursting pressure at cecal stump was comparable among the three methods; along with tissue healing process, both BL and BS provided a higher bursting pressure than BR 7 days after appendectomy. BL subgroup had more abundant hydroxyproline deposition than BS and BR subgroup. Furthermore, serum TNF-α in BR group kept persistently increasing along with time after cecal resection. Thus, the finding that LigaSure but not rubber band is safe in sealing off the inflamed cecal stump in rat model of acute appendicitis suggests the possibility of applying LigaSure for appendectomy via single port procedure or natural orifice transluminal endoscopic surgery (NOTES). PMID:25699264

  19. Fine Mapping of the Interaction between C4b-Binding Protein and Outer Membrane Proteins LigA and LigB of Pathogenic Leptospira interrogans

    PubMed Central

    Breda, Leandro C. D.; Hsieh, Ching-Lin; Castiblanco Valencia, Mónica M.; da Silva, Ludmila B.; Barbosa, Angela S.; Blom, Anna M.; Yung-Fu, Chang; Isaac, Lourdes

    2015-01-01

    The complement system consists of more than 40 proteins that participate in the inflammatory response and in pathogen killing. Complement inhibitors are necessary to avoid the excessive consumption and activation of this system on host cells. Leptospirosis is a worldwide zoonosis caused by spirochetes from the genus Leptospira. Pathogenic leptospires are able to escape from complement activation by binding to host complement inhibitors Factor H [FH] and C4b-binding protein (C4BP) while non-pathogenic leptospires are rapidly killed in the presence of fresh serum. In this study, we demonstrate that complement control protein domains (CCP) 7 and 8 of C4BP α-chain interact with the outer membrane proteins LcpA, LigA and LigB from the pathogenic leptospire L. interrogans. The interaction between C4BP and LcpA, LigA and LigB is sensitive to ionic strength and inhibited by heparin. We fine mapped the LigA and LigB domains involved in its binding to C4BP and heparin and found that both interactions are mediated through the bacterial immunoglobulin-like (Big) domains 7 and 8 (LigA7-8 and LigB7-8) of both LigA and LigB and also through LigB9-10. Therefore, C4BP and heparin may share the same binding sites on Lig proteins. PMID:26517116

  20. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  1. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  2. A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

    PubMed

    Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

    2012-07-01

    We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging. PMID:22966554

  3. Critical dimension control for prevention of wafer-to-wafer and module-to-module difference

    NASA Astrophysics Data System (ADS)

    Deguchi, Masatoshi; Tanaka, Kouichirou; Nagatani, Naohiko; Miyata, Yuichiro; Yamashita, Mitsuo; Minami, Yoshiaki; Matsuyama, Yuji

    2004-05-01

    In recent years, the worldwide semiconductor market has changed drastically, and it is expected that the digital device market will continue to expand towards general consumer electronics and away from the personal computers that have been the core of the market. To accommodate this shift, the new devices will be diversified with improved productivity, higher process yield, and higher precision. Clean Track (LITHIUS) design also has been changed drastically to maintain equal productivity with new high throughput exposure equipment. Design changes include increasing the number of processing chambers by stacking reduced size modules in order to meet high throughput and small footprint requirements. However, this design change concept raises concerns about increased wafer-to-wafer difference (WtW) and module-to-module different (MtM). These variations can result in lower process yield and have a negative effect on design rule shrinkage. The primary causes of WtW difference and MtM difference stem from minute module hardware variations, module height differences, and module parameter adjustment differences during the installation of the tool. Previous Clean Track development focused mainly on reduction of module hardware difference as an approach to reduce WtW variation. However, to further improve lot level uniformity, it is necessary to reduce module height difference factors within the system and module adjustment disparities such as plate temperature calibrations. Highly temperature sensitive ArF processes have necessitated precise manual PEB temperature adjustments. These calibrations are labor intensive and require many field hours to ensure optimal CD uniformity. Therefore, an auto temperature measurement and adjustment tool is developed to eliminate the human error due to manual adjustment and minimize adjustment time. In order to meet demands for design rules shrinkage and increased process uniformity we minimized the WtW and MtM difference by using thermal history adjustment and transfer time control. This method is also used to improve within wafer CD control technology resulting in a more stable process. In this report, we introduce improved features to reduce WtW and MtM variation and their effect on CD uniformity with 193nm (ArF) resist and 248nm (KrF) resist.

  4. The Study of Deep Lithography and Moulding Process of LIGA Technique

    NASA Astrophysics Data System (ADS)

    Guo, Yuhua; Liu, Gang; Kan, Ya; Tian, Yangchao

    2007-01-01

    The knowledge of the development behavior, especially the development rate, is of primary importance for the study of deep x-ray lithography in LIGA technique. In the first part of this paper, we have measured the development rates of crosslinked PMMA foils irradiated in NSRL covering a wide dose range (bottom dose in the range:2.5-8.0 kJ/cm3). After the exposure, we use a so-called period-development method (to dip development in GG-developer for 20 minutes and clean in rinse solution for 40 minutes as a development period). For processing the experiment data, we get the KDβ model to describe our PMMA/GG-developer system. The aim of this work is to find out a stable experiment condition for deep X-ray lithography and development. The result shows that in small amount of dose (bottom dose range: 2.5-4 kJ/cm3), this model is very stable. While in large amount of dose (bottom dose range: 5-8kJ/cm3), the model becomes very sensitive and even unavailable. To verify the conclusion validity, the fixed dose range (bottom dose range: 3.5-4 kJ/cm3) is applied on PMMA microstructures. And the result shows an effective development process. In the following procedure, mold inserts can be produced by micro-electroforming and plastic replicas can be mass produced by hot embossing. To emboss high-aspect-ratio microstructures, the deformation of microstructures usually occurs due to the demolding forces between the sidewall of mold inserts and the thermoplastic (PMMA). To minimize the friction force the optimized experiment has been performed using Ni-PTFE compound material mold inserts. Typical defects like pull-up and damaged edges can be greatly reduced.

  5. Performance of Ultra Hard Carbon Wear Coatings on Microgears Fabricated by Liga

    SciTech Connect

    Ager III, J.W.; Brown, I.G.; Christenson, T.R.; Dugger, M.T.; Follstaedt, D.M.; Knapp, J.A.; Monteiro, O.R.

    1998-12-18

    Stiction and friction are of concern for the reliable, long-term application of Ni-alloy micromachines. We have found that the application of a 30-70 nm hard carbon coating produces a significant reduction in the friction coefficient and wear rate of electroformed Ni substrates in reciprocating sliding contact under simulated MEMS operating conditions. To evaluate the performance of coated components, a series of 70-pm-thick microgears ranging in diameter from 0.2 to 2.2 mm were fabricated from electroformed Ni via standard LIGA processes and fixtured on posts in preparation for the coating procedure. A pulsed vacuum- arc deposition process was used to deposit a carbon coating on the gears with the plasma incident at a shallow angle to the gears' top surface. A sample bias of -2 keV was used in order to produce a coating with relatively low stress and good adhesion while maintaining high hardness. This coating process is known to be somewhat comformal to the component surfaces. The coating uniformity, particularly in the high-aspect-ratio areas between the gear teeth, was evaluated with micro-Raman spectroscopy. It is shown that the coating can be applied uniformly on the top gear surface. Between the gear teeth the coating was the same thickness as on top of the gear down to a point 50 ~m below the top surface. Below that point (i.e. between 50 and 70 Lm), the coating thickness is somewhat thinner, but is still present. These results demonstrate that it is possible to a deposit hard carbon coating on microgears to reduce friction and wear in micromachines.

  6. Application of EEM fluorescence spectroscopy in understanding of the "LIGA" phenomenon in the Bay of Biscay (France)

    NASA Astrophysics Data System (ADS)

    Parot, Jérémie; Susperregui, Nicolas; Rouaud, Vanessa; Dubois, Laurent; Anglade, Nathalie; Parlanti, Edith

    2014-05-01

    Marine mucilage is present in all oceans over the world, and in particular in the Mediterranean Sea and in the Pacific Ocean. Surface water warming and hydrodynamic processes can favor the coalescence of marine mucilage, large marine aggregates representing an ephemeral and extreme habitat for biota. DOM is a heterogeneous, complex mixture of compounds, including extracellular polymeric substances (EPS), with wide ranging chemical properties and it is well known to interact with pollutants and to affect their transport and their fate in aquatic environment. The LIGA French research program focuses on tracing colloidal dissolved organic matter (DOM) sources and cycling in the Bay of Biscay (South Western French coast). This ephemeral phenomenon (called "LIGA" in the South West of France) has been observed more than 750 times since 2010. It presents a great ecological impact on marine ecosystems and has been shown to be concomitant with the development of pathogen organisms. A one-year intensive survey of fluorescent DOM was undertaken. From April 2013 until May 2014, water samples were monthly collected from the Adour River (main fresh water inputs) and from 2 sites in the Bay of Biscay at 3 depths of the water column (surface water, at the maximum of chlorophyll-a, and deep water). Moreover, intensified samplings took place from the appearance of the phenomenon twice a week during 4 weeks. UV/visible absorbance and excitation emission matrix (EEM) fluorescence spectroscopy combined with PARAFAC and PCA analyses have been used to characterize colloidal DOM in the Bay of Biscay in order to estimate DOM sources as well as spatial and temporal variability of DOM properties. The preliminary results, obtained for about 70 samples of this survey, have already highlighted spatial and temporal variations of DOM optical properties and a peculiar fluorescent component (exc300nm/em338nm) was detected while the LIGA phenomenon arises. The appearance of this specific fluorescence signal seems to be correlated with high freshwater and terrestrial DOM inputs combined with physical forcing (flows, swell) as well as a rise in temperature and sunshine. This work already allowed us to identify different sources of colloidal DOM in the Bay of Biscay and highlighted a specific fingerprint of the LIGA phenomenon. The combination of EEM fluorescence spectroscopy with PARAFAC and PCA analyses appears thus to be a very powerful tool for the long term monitoring of such a phenomenon and would be very useful for a better understanding of the biogeochemical processes in marine environments and of the marine colloidal DOM ecodynamics.

  7. 100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices

    SciTech Connect

    OLIVER,ANDREW D.; MATZKE,CAROLYN M.

    2000-04-06

    A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

  8. Wafer level glass optics: precision glass molding as an alternative manufacturing approach

    NASA Astrophysics Data System (ADS)

    Huenten, Martin; Hollstegge, Daniel; Wang, Fei; Dambon, Olaf; Klocke, Fritz

    2011-02-01

    In this paper the manufacturing approach of wafer scale molded glass optics is described including a detailed view on each process step that needs to be accomplished. At first, an appropriate mold design based on FE-simulation results is applied. As in every replication process the mold is the key factor of success which is precision ground to its required shape. At this point different grinding kinematics with their characteristics are presented. In the final molding process one of the major challenges is the alignment of the upper and lower mold die to guarantee the centricity of the optical surfaces.

  9. Quantitative phase measurement for wafer-level optics

    NASA Astrophysics Data System (ADS)

    Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

    2015-07-01

    Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

  10. WaferOptics® mass volume production and reliability

    NASA Astrophysics Data System (ADS)

    Wolterink, E.; Demeyer, K.

    2010-05-01

    The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

  11. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    NASA Astrophysics Data System (ADS)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  12. Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.

    2004-01-01

    An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

  13. Scale

    ERIC Educational Resources Information Center

    Schaffhauser, Dian

    2009-01-01

    The common approach to scaling, according to Christopher Dede, a professor of learning technologies at the Harvard Graduate School of Education, is to jump in and say, "Let's go out and find more money, recruit more participants, hire more people. Let's just keep doing the same thing, bigger and bigger." That, he observes, "tends to fail, and fail…

  14. Scale

    ERIC Educational Resources Information Center

    Schaffhauser, Dian

    2009-01-01

    The common approach to scaling, according to Christopher Dede, a professor of learning technologies at the Harvard Graduate School of Education, is to jump in and say, "Let's go out and find more money, recruit more participants, hire more people. Let's just keep doing the same thing, bigger and bigger." That, he observes, "tends to fail, and fail

  15. Optical wafer metrology sensors for process-robust CD and overlay control in semiconductor device manufacturing

    NASA Astrophysics Data System (ADS)

    den Boef, Arie J.

    2016-06-01

    This paper presents three optical wafer metrology sensors that are used in lithography for robustly measuring the shape and position of wafers and device patterns on these wafers. The first two sensors are a level sensor and an alignment sensor that measure, respectively, a wafer height map and a wafer position before a new pattern is printed on the wafer. The third sensor is an optical scatterometer that measures critical dimension-variations and overlay after the resist has been exposed and developed. These sensors have different optical concepts but they share the same challenge that sub-nm precision is required at high throughput on a large variety of processed wafers and in the presence of unknown wafer processing variations. It is the purpose of this paper to explain these challenges in more detail and give an overview of the various solutions that have been introduced over the years to come to process-robust optical wafer metrology.

  16. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  17. Wafer Fusion for Integration of Semiconductor Materials and Devices

    SciTech Connect

    Choquette, K.D.; Geib, K.M.; Hou, H.Q.; Allerman, A.A.; Kravitz, S.; Follstaedt, D.M.; Hindi, J.J.

    1999-05-01

    We have developed a wafer fusion technology to achieve integration of semiconductor materials and heterostructures with widely disparate lattice parameters, electronic properties, and/or optical properties for novel devices not now possible on any one substrate. Using our simple fusion process which uses low temperature (400-600 C) anneals in inert N{sub 2} gas, we have extended the scope of this technology to examine hybrid integration of dissimilar device technologies. As a specific example, we demonstrate wafer bonding vertical cavity surface emitting lasers (VCSELs) to transparent AlGaAs and GaP substrates to fabricate bottom-emitting short wavelength VCSELs. As a baseline fabrication technology applicable to many semiconductor systems, wafer fusion will revolutionize the way we think about possible semiconductor devices, and enable novel device configurations not possible by epitaxial growth.

  18. White-light interferometric microscopy for wafer defect inspection

    NASA Astrophysics Data System (ADS)

    Zhou, Renjie; Edwards, Christopher; Bryniarski, Casey; Dallmann, Marjorie F.; Popescu, Gabriel; Goddard, Lynford L.

    2015-03-01

    White-light imaging systems are free of laser-speckle. Thus, they offer high sensitivity for optical defect metrology, especially when used with interferometry based quantitative phase imaging. This can be a potential solution for wafer inspection beyond the 9 nm node. Recently, we built a white-light epi-illumination diffraction phase microscopy (epi-wDPM) for wafer defect inspection. The system is also equipped with an XYZ scanning stage and real-time processing. Preliminary results have demonstrated detection of 15 nm by 90 nm in a 9 nm node densely patterned wafer with bright-field imaging. Currently, we are implementing phase imaging with epi-wDPM for additional sensitivity.

  19. On-wafer magnetic resonance of magnetite nanoparticles

    NASA Astrophysics Data System (ADS)

    Little, Charles A. E.; Russek, Stephen E.; Booth, James C.; Kabos, Pavel; Usselman, Robert J.

    2015-11-01

    Magnetic resonance measurements of ferumoxytol and TEMPO were made using an on-wafer transmission line technique with a vector network analyzer, allowing for broadband measurements of small sample volumes (4 nL) and small numbers of spins (1 nmol). On-wafer resonance measurements were compared with standard single-frequency cavity-based electron paramagnetic resonance (EPR) measurements using a new power conservation approach and the results show similar line shape. On-wafer magnetic resonance measurements using integrated microfluidics and microwave technology can significantly reduce the cost and sample volumes required for EPR spectral analysis and allow for integration of EPR with existing lab-on-a-chip processing and characterization techniques for point-of-care medical diagnostic applications.

  20. 450mm wafer patterning with jet and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  1. Digital model planning and computerized fabrication of orthognathic surgery wafers.

    PubMed

    Cousley, Richard R J; Turner, Mark J A

    2014-03-01

    Conventional orthognathic wafers are made by a process involving manual movement of stone dental models and acrylic laboratory fabrication. In addition, a facebow record and semi-adjustable articulator system are required for maxillary osteotomy cases. This paper introduces a novel process of producing both intermediate and final orthognathic surgical wafers using a combination of computerized digital model simulation and three-dimensional print fabrication, without the need for either a facebow record or the additional ionizing radiation exposure associated with cone beam computerized tomography. PMID:24235100

  2. Wafer CD variation for random units of track and polarization

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

    2012-03-01

    After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle MTT and wafer intra-field MTT is shown for ENG process without polarization. The influence of different exposure conditions - with and without polarization of scanner laser source - on the average CD value for isolated and dense structures is demonstrated.

  3. An application of selective electrochemical wafer thinning for silicon characterization

    SciTech Connect

    Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

    1990-01-01

    A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

  4. Piezoelectric photoacoustic evaluation of Si wafers with buried structures.

    PubMed

    Shen, Y C; Zhang, S Y

    1992-01-01

    The piezoelectric photoacoustic evaluation of Si wafers with buried structures is studied experimentally and theoretically. In the experiment, the authors have detected and imaged the Sb-doped regions in a Si wafer covered by an epitaxial Si layer with about 10-mum thickness. In order to explain the experimental results, the one-dimensional multilayered model with discontinuous thermal impedance between the neighboring layers is used, and the expressions for the thermal and acoustic fields in the sample and PZT transducer are also presented. Moreover, numerical calculations in accordance with the practical experimental conditions have been carried out. PMID:18263140

  5. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    SciTech Connect

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  6. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, Theodoer F.

    1995-01-01

    Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

  7. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  8. μ-Device fabrication and packaging below 300°C utilizing plasma-assisted wafer-to-wafer bonding

    NASA Astrophysics Data System (ADS)

    Kirchberger, Herwig; Pelzer, Rainer; Farrens, Sharon

    2006-01-01

    Wafer-to-wafer bonding techniques, such as anodic bonding or high temperature silicon direct fusion bonding, have been in development since the late 1960's and became key technologies for MEMS manufacturing. Plasma assisted wafer bonding is an emerging method offering several advantages over traditional bonding techniques. This technology was first discovered and patented in the early 1990's and has been used in SOI production for the past five years. Now plasma activation benefits are being used to enable 3D integration and advanced MEMS device fabrication and packaging. The main advantage of plasma assisted bonding is that high strength direct bonds between substrates, like Si, glass or polymers, can be achieved already below 300°C.

  9. Scales

    SciTech Connect

    Murray Gibson

    2007-04-27

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain — a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  10. Scales

    ScienceCinema

    Murray Gibson

    2010-01-08

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain ? a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  11. Transparent masks for aligned deep x-ray lithography/LIGA: low-cost high-performance alternative using glass membranes

    NASA Astrophysics Data System (ADS)

    Kupka, Roland K.; Megtert, Stephan; Roulliay, Marc; Bouamrane, Faycal

    1998-09-01

    Deep x-ray lithography/LIGA has proven to be a well established framework of x-ray based technologies for the fabrication of microstructures and pseudo three-dimensional objects. Inherently, x-ray lithography/LIGA is not fully three-dimensional because of the principle of simple shadow printing onto resists of constant thickness. Thus, it would be impossible to obtain 3D spheres, but series of stacked monolithic 2D cylinders. Hence, until recently, LIGA was mainly concerned with simple uni-level (1D) monolithic structures, using optically opaque mask-membranes like Be, Si or Ti with grown-on Au absorbers. In the course for mastering pseudo three-dimensional microstructures like micro-coils or electromagnetic applications, an alignment in between the lithographic steps becomes necessary which requires optically transparent membrane materials, if optical alignment is chosen. Diamond or SiC membranes are the actual suitable materials for such purposes, but their pricing and/or process robustness inhibit their frequent use in simple projects. We would like to report on a new promising material: a glued-on thin glass membrane. The advantages are incomparably lower costs compared to Diamond or SiC technologies, a considerable ease of fabrication, handling, quite favorable mechanical/optical properties, sufficient for lithographic purposes and multi-level deep x-ray lithography/LIGA activities.

  12. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  13. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    PubMed Central

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  14. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    NASA Astrophysics Data System (ADS)

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, Sanghyeon; Choi, Won Jun

    2016-02-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

  15. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications.

    PubMed

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called "Si photonics"). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  16. Scatterometry on pelliclized masks: an option for wafer fabs

    NASA Astrophysics Data System (ADS)

    Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

    2007-03-01

    Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

  17. National solar technology roadmap: Wafer-silicon PV

    SciTech Connect

    Sopori, Bhushan

    2007-06-01

    This report applies to all bulk-silicon-based PV technologies, including those based on Czochralski, multicrystalline, float-zone wafers, and melt-grown crystals that are 100 μm or thicker, such as ribbons, sheet, or spheral silicon.

  18. Interaction of an argon plasma jet with a silicon wafer

    NASA Astrophysics Data System (ADS)

    Engelhardt, Max; Pothiraja, Ramasamy; Kartaschew, Konstantin; Bibinov, Nikita; Havenith, Martina; Awakowicz, Peter

    2016-04-01

    A filamentary discharge is ignited in an argon plasma jet under atmospheric pressure conditions. The gas discharge is characterized with voltage-current measurements, optical emission spectroscopy and an ICCD-camera with a high temporal resolution down to 10 ns. In the effluent of the plasma jet, filaments come into contact with the surface of a silicon wafer and modify it, namely etching traces are produced and microcrystals are deposited. These traces are studied with optical and electron microscopes. The material of the deposited microcrystals and the surface modifications of the silicon wafer are analyzed with Raman microspectroscopy. Amorphous silicon is found within the etching traces. The largest part of the deposited microcrystals are composed of nitratine (NaNO3) and some of them are calcite (CaCO3). Analyzing the possible reasons for the silicon wafer modifications we come to the conclusion that plasmoids, which are produced near the substrate surface by interaction with ionization waves, are a plausible explanation for the observed surface modifications of the silicon wafer.

  19. Fabricating a Microcomputer on a Single Silicon Wafer

    NASA Technical Reports Server (NTRS)

    Evanchuk, V. L.

    1983-01-01

    Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

  20. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    SciTech Connect

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

  1. A reclaiming process for solar cell silicon wafer surfaces.

    PubMed

    Pa, P S

    2011-01-01

    The low yield of epoxy film and Si3N4 thin-film deposition is an important factor in semiconductor production. A new design system using a set of three lamination-shaped electrodes as a machining tool and micro electro-removal as a precision reclaiming process of the Si3N4 layer and epoxy film removal from silicon wafers of solar cells surface is presented. In the current experiment, the combination of the small thickness of the anode and cathodes corresponds to a higher removal rate for the thin films. The combination of the short length of the anode and cathodes combined with enough electric power produces fast electroremoval. A combination of the small edge radius of the anode and cathodes corresponds to a higher removal rate. A higher feed rate of silicon wafers of solar cells combined with enough electric power produces fast removal. A precise engineering technology constructed a clean production approach for the removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers from solar cells that can reduce pollution and lower cost. PMID:21446525

  2. Multi-wafer slicing with a fixed abrasive

    NASA Technical Reports Server (NTRS)

    Schmid, Frederick (Inventor); Khattak, Chandra P. (Inventor); Smith, Maynard B. (Inventor)

    1988-01-01

    A wafering machine having a multiplicity of wire cutting blades supported by a bladehead reciprocally moving past a workpiece supported by a holder that rocks about an axis perpendicular to the wires at a frequency less than the reciprocation of the bladehead.

  3. Virtual fab flow for wafer topography aware OPC

    NASA Astrophysics Data System (ADS)

    Stock, Hans-Jürgen; Bomholt, Lars; Krüger, Dietmar; Shiely, James; Song, Hua; Voznesenskiy, Nikolay

    2010-04-01

    Small feature sizes down to the current 45 nm node and precision requirements of patterning in 193 nm lithography as well as layers where the wafer stack does not allow any BARC require - not only correction of optical proximity (OPC) effects originating from mask topography and imaging system, but also correction of wafer topography proximity (WTPC) effects as well. In spite of wafer planarization process steps, wafer topography (proximity) effects induced by different optical properties of the patterned materials start playing a significant role, and correction techniques need to be applied in order to minimize the impact. In this paper, we study a methodology to create fast models intended for effective use in OPC and WTPC procedures. In order to be short we use the terms "OPCWTPC modeling" and "OPCWTPC models" through the paper although it would be more correctly to take the terms "mask synthesis modeling" and "mask synthesis models". A comprehensive data set is required to build a reliable OPC model. We present a "virtual fab" concept using extensive test pattern sets with both 1D and 2D structures to capture optical proximity effects as well as wafer topography effects. A rigorous lithography simulator taking into account exposure tool source maps, topographic mask effects as well as wafer topography is used to generate virtual measurement data, which are used for model calibration as well as for model validation. For model building, we use a two step approach: in a first step, an OPC model is built using test patterns on a planar, homogenous substrate; in a second step a WTPC model is calibrated, using results from simulated test patterns on shallow trench isolation (STI) layer. This approach allows building models from experimental data, including hybrid approaches where only experimental data from planar substrates is available and a corresponding OPC model for the planar case can be retrofitted with capabilities for correcting wafer topography effects. We analyze the relevant effects and requirements for model building and validation as well as the performance of fast WTPC models.

  4. Bonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits

    NASA Astrophysics Data System (ADS)

    Kim, Hyun S.; Blick, Robert H.; Kim, D. M.; Eom, C. B.

    2004-09-01

    We report a method for bonding silicon-on-insulator wafers onto glass wafers. After pre-cleaning the wafers by an ozone and ultraviolet exposure, followed by mega-sonic water rinse, the SOI wafers are bonded to glass wafers in a vacuum chamber. This is performed at a temperature of 400 °C under an applied voltage of 700 V. The interface between the glass and SOI wafer is tested mechanically and inspected by electron beam microscopy. Furthermore, we demonstrate removal of the silicon bulk layer after wafer bonding. The quality of the single crystalline Si thin film on the glass wafers has been verified by four-circle x-ray diffraction and scanning electron microscopy. This process will allow us the integration of thin-film electronics in biological sensor applications.

  5. Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

    NASA Astrophysics Data System (ADS)

    Calaway, M. J.; Rodriguez, M. C.; Allton, J. H.; Stansbery, E. K.

    2009-03-01

    The cleaning efficiency of the Genesis Ultra-pure Water Megasonic Wafer Spin Cleaner will be presented. Results show the effectiveness of the new cleaner removing particle contamination from Genesis silicon wafers implanted with solar wind.

  6. Electrical characterization of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Kang, Sunggun

    Silicon-on-Insulator (SOI) metal oxide semiconductor field effect transistors (MOSFET) have become a common subject in the semiconductor community due to enhanced performance such as simple processing, excellent scalability, sharp subthreshold characteristics, minimum short-channel effects, and reduced hot electron degradation. Since these films are used for devices, it is necessary to know the SOI film quality with simple and nondestructive methods. In this study, surface photovoltage (SPV) measurements, pseudo-MOSFET characterization, and capacitance-voltage (C-V) are used. Literature review and simulations show that material properties of SOI wafers can have significant effects on the device and circuit performance such as floating body effects, switching speed, leakage current, and noise characteristics. SPV results show the surface charges of SOI wafers to increase with frequency in the low frequency region, with several interface components acting in opposing directions. Iron contaminated wafers show increased surface charges due to a high density of interface states. The efficacy of surface passivation is clearly shown by measuring the effective generation lifetime as a function of time after applying the liquid to the pseudo-MOSFET surface. A more controlled method is the additional top gate controlling either the upper or lower silicon film surface, separately. C-V measurements for some SOI wafers show a leaky buried oxide (BOX) and high density of interface states. SOI wafers can exhibit quite different breakdown voltage before and after removing the Si layer, indicating that the gate current flows through weaker current paths in the BOX beyond the gate area. Transmission electron microscopy (TEM) images display smooth interfaces and a clean BOX, regardless of the breakdown voltage.

  7. Advanced FTIR technology for the chemical characterization of product wafers

    NASA Astrophysics Data System (ADS)

    Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

    2001-01-01

    Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers.

  8. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    SciTech Connect

    Qiusheng, Y. Senkai, C. Jisheng, P.

    2015-03-30

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  9. High throughput wafer defect monitor for integrated metrology applications in photolithography

    NASA Astrophysics Data System (ADS)

    Rao, Nagaraja; Kinney, Patrick; Gupta, Anand

    2008-03-01

    The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

  10. Enhanced capture rate for haze defects in production wafer inspection

    NASA Astrophysics Data System (ADS)

    Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

    2010-03-01

    Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure involved scanning with three different recipe types: Standard Inspection: Nominal recipe with a low false alarm rate was used to scan the wafer and repeaters were extracted from the final defect map. Haze Monitoring Application: Recipe sensitivity was enhanced and run on a single field column from which on repeating defects were extracted. Enhanced Repeater Extractor: Defect processing included the two parallel routes: a nominal recipe for the random defects and the new high sensitive repeater extractor algorithm. The results showed that the new application (recipe #3) had the highest capture rate on haze defects and detected new repeater defects not found in the first two recipes. In addition, the recipe was much simpler to setup since repeaters are filtered separately from random defects. We expect that in the future, with the advent of mask-less lithography and EUV lithography, the monitoring of field and die repeating defects on the wafer will become a necessity for process control in the semiconductor fab.

  11. Height inspection of wafer bumps without explicit 3D reconstruction

    NASA Astrophysics Data System (ADS)

    Dong, Mei; Chung, Ronald; Zhao, Yang; Lam, Edmund Y.

    2006-02-01

    The shrunk dimension of electronic devices leads to more stringent requirement on process control and quality assurance of their fabrication. For instance, direct die-to-die bonding requires placement of solder bumps not on PCB but on the wafer itself. Such wafer solder bumps, which are much miniaturized from the counterparts on PCB, still need to have their heights meet the specification, or else the electrical connection could be compromised, or the dies be crushed, or even the manufacturing equipments be damaged. Yet the tiny size, typically tens of microns in diameter, and the textureless and mirror nature of the bumps pose great challenge to the 3D inspection process. This paper addresses how a large number of such wafer bumps could have their heights massively checked against the specification. We assume ball bumps in this work. We propose a novel inspection measure about the collection of bump heights that possesses these advantages: (1) it is sensitive to global and local disturbances to the bump heights, thus serving the bump height inspection purpose; (2) it is invariant to how individual bumps are locally displaced against one another on the substrate surface, thus enduring 2D displacement error in soldering the bumps onto the wafer substrate; and (3) it is largely invariant to how the wafer itself is globally positioned relative to the imaging system, thus having tolerance to repeatability error in wafer placement. This measure makes use of the mirror nature of the bumps, which used to cause difficulty in traditional inspection methods, to capture images of two planes. One contains the bump peaks and the other corresponds to the substrate. With the homography matrices of these two planes and fundamental matrix of the camera, we synthesize a matrix called Biplanar Disparity Matrix. This matrix can summarize the bumps' heights in a fast and direct way without going through explicit 3D reconstruction. We also present a design of the imaging and illumination setup that allows the measure to be revealed in two images, and how the inspection measure could be estimated from the image data so acquired. Both synthetic and real data experimental results are shown to illustrate the effectiveness of the proposed system.

  12. Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

    NASA Astrophysics Data System (ADS)

    Altan, Hakan

    All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on transmission and mobility are quantitatively discussed.

  13. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Luo, Xianshu; Cao, Yulian; Song, Junfeng; Hu, Xiaonan; Cheng, Yungbing; Li, Chengming; Liu, Chongyang; Liow, Tsung-Yang; Yu, Mingbin; Wang, Hong; Wang, Qijie; Lo, Patrick Guo-Qiang

    2015-04-01

    Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS) fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W) bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP) laser, lateral-coupled distributed feedback (LC-DFB) laser with side wall grating, and mode-locked laser (MLL). From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC).

  14. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    NASA Astrophysics Data System (ADS)

    Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

    2016-02-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

  15. Simulations of a SCALPEL wafer-heating correction using an adaptive Kalman filter

    NASA Astrophysics Data System (ADS)

    Stanton, Stuart T.

    2001-08-01

    The high-energy (100KeV) electron imaging process used by SCALPEL causes a dynamic heat load and wafer expansion response. Despite good thermal contact between the wafer and chuck, the dynamic distortion on a die length scale is too large to allow in the overlay error budget, and is fundamentally difficult to prevent or dissipate. However, the sub-field scanning strategy of SCALPEL allows us to implement a dynamic distortion-correction algorithm, by making a real-time position adjustment of the imaging sub-field. Analytical tools developed for understanding these phenomena could be applied in a purely predictive correction algorithm, in principle. However, these predictions are limited by the variability of chuck thermal contact, as well as by difficulty in handling the frictional chuck-attachment boundary condition. Hence, a means of improving upon a basic prediction is necessary to support a robust correction strategy. In this paper, I will explore the practical real-time implementation of a correction algorithm based on Adaptive Kalman Filter techniques, using dynamic alignment updates. Simulations demonstrate the feasibility of this approach to make a very close estimate of the ideal correction.

  16. Wafer-level packaging with compression-controlled seal ring bonding

    DOEpatents

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  17. A silicon wafer packaging solution for HB-LEDs

    NASA Astrophysics Data System (ADS)

    Murphy, Tom; Weichel, Steen; Isaacs, Steven; Kuhmann, Jochen

    2007-09-01

    In this paper we present HyLED, a silicon wafer packaging solution for high-brightness LEDs. The associated technology is batch micro-machining/metallisation processing of silicon wafers allowing significant reduction of the final device size. The presented package is multi-functional where the micro-machined cavity acts as reflector, thermal conductor and reservoir for the silicone/colour conversion substance. The base material, silicon, has excellent mechanical and thermal properties and enables direct integration of intelligence. We present customer specific solutions, open tool samples and performance data for optical and thermal parameters and reliability testing. Thermal resistance values of R<5 K/W, junction-to-board are demonstrated.

  18. Chemical method for producing smooth surfaces on silicon wafers

    DOEpatents

    Yu, Conrad

    2003-01-01

    An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

  19. Metal adsorbent for alkaline etching aqua solutions of Si wafer

    NASA Astrophysics Data System (ADS)

    Tamada, Masao; Ueki, Yuji; Seko, Noriaki; Takeda, Toshihide; Kawano, Shin-ichi

    2012-08-01

    High performance adsorbent is expected to be synthesized for the removal of Ni and Cu ions from strong alkaline solution used in the surface etching process of Si wafer. Fibrous adsorbent was synthesized by radiation-induce emulsion graft polymerization onto polyethylene nonwoven fabric and subsequent amination. The reaction condition was optimized using 30 L reaction vessel and nonwoven fabric, 0.3 m width and 18 m long. The resulting fibrous adsorbent was evaluated by 48 wt% NaOH and KOH contaminated with Ni and Cu ions, respectively. The concentration levels of Ni and Cu ions was reduced to less than 1 μg/kg (ppb) at the flow rate of 10 h-1 in space velocity. The life of adsorbent was 30 times higher than that of the commercialized resin. This novel adsorbent was commercialized as METOLATE® since the ability of adsorption is remarkably higher than that of commercial resin used practically in Si wafer processing.

  20. Nanoindentation tests on diamond-machined silicon wafers

    NASA Astrophysics Data System (ADS)

    Yan, Jiwang; Takahashi, Hirokazu; Tamaki, Jun'ichi; Gai, Xiaohui; Harada, Hirofumi; Patten, John

    2005-05-01

    Nanoindentation tests were performed on ultraprecision diamond-turned silicon wafers and the results were compared with those of pristine silicon wafers. Remarkable differences were found between the two kinds of test results in terms of load-displacement characteristics and indent topologies. The machining-induced amorphous layer was found to have significantly higher microplasticity and lower hardness than pristine silicon. When machining silicon in the ductile mode, we are in essence always machining amorphous silicon left behind by the preceding tool pass; thus, it is the amorphous phase that dominates the machining performance. This work indicated the feasibility of detecting the presence and the mechanical properties of the machining-induced amorphous layers by nanoindentation.

  1. Single Wafer Furnace and Its Thermal Processing Applications

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kuribayashi, Hiromitsu; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-07-01

    A resistively heated, vacuum and atmospheric pressure compatible, single wafer furnace (SWF) system is proposed to improve operational flexibility of conventional furnaces and productivity of single wafer rapid thermal processing (RTP) systems. The design concept and hardware configuration of the SWF system are described. The temperature measurement/control techniques and thermal characteristics of the SWF system are described. Typical process results in TiSi formation, implant anneal and thin oxide formation using the SWF system are reported. Due to the vertically stacked, dual chamber configuration and steady state temperature control, very flexible operation with a high throughput at a minimal power consumption (<3.5 kW per process chamber at 1150°C) was realized. Many thermal processes used in furnaces and RTP systems can easily be converted to SWF processes without decreasing cost performance and/or deteriorating process results by using the SWF system.

  2. A gas chromatographic air analyzer fabricated on a silicon wafer

    NASA Technical Reports Server (NTRS)

    Terry, S. C.; Jerman, J. H.; Angell, J. B.

    1979-01-01

    A miniature gas analysis system has been built based on the principles of gas chromatography (GC). The major components are fabricated in silicon using photolithography and chemical etching techniques, which allows size reductions of nearly three orders of magnitude compared to conventional laboratory instruments. The chromatography system consists of a sample injection valve and a 1.5-m-long separating capillary column, which are fabricated on a substrate silicon wafer. The output thermal conductivity detector is separately batch fabricated and integrably mounted on the substrate wafer. The theory of gas chromatography has been used to optimize the performance of the sensor so that separations of gaseous hydrocarbon mixtures are performed in less than 10 s. The system is expected to find application in the areas of portable ambient air quality monitors, implanted biological experiments, and planetary probes.

  3. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    SciTech Connect

    Montoya, Angela C.; Maji, Arup K.

    2010-02-22

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  4. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    NASA Astrophysics Data System (ADS)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  5. Towards reduced impact of EUV mask defectivity on wafer

    NASA Astrophysics Data System (ADS)

    Jonckheere, R.; Van den Heuvel, D.; Pacco, A.; Pollentier, I.; Baudemprez, B.; Jehoul, C.; Hermans, J.; Hendrickx, E.

    2014-07-01

    The defectivity challenges of extreme ultraviolet (EUV) masks, that need to be addressed before production readiness of EUV lithography is assured from the mask perspective, are twofold. First, the EUV-specific defect type relating to the multi-layer (ML) mirror, the so-called ML-defects, require to become more detectable than they are printable. This not only requires proven capability of blank inspection, but also the existence of satisfactory printability mitigation strategies (comprising avoidance, pattern shift methodology, compensation repair). Both these assets need to become available within the mask supply chain, as there is little that can still be done about such residual defects at the wafer fab. In a production phase, finding unexpected printing ML-defects is unacceptable. It is shown how the specific way-of-working in use at imec, starting from the printed wafer, contributes to related learning and identification of remaining gaps, in getting this issue fully dealt with. The second challenge relates to particle contamination during use of the reticle at the wafer fab. Avoiding overlaycritical particles on the backside of NXE3100 reticles is facilitated by the established way-of-working. Minimizing the occurrence of particles "hopping" between reticles via the electrostatic clamp of the scanner (so-called clamp-traveling particles) is a major driver for appropriate mask cleaning. The latter may not have negative impact by frequent use, in view of the highly vulnerable EUV mask stack, and especially for the present "black-border" solution in which the ML is etched away at the image border on the reticle. A lot of effort is spent into monitoring of NXE3100 reticles for particle adders on the pattern side. This is realized by comparing past and present mask defect maps obtained by inspection of printed wafers with subsequent repeater analysis.

  6. Ultrahigh-vacuum field emitter array wafer tester

    SciTech Connect

    Gray, H.F.; Ardis, L.; Campisi, G.J.

    1987-02-01

    The device reported here allows the researcher the opportunity of gaining primitive yield information, threshold voltages, emission stability, and other information, e.g., gas effects, on field emitter arrays (FEA) which are microminiature ''vacuum tubes'' fabricated by microelectronic processing methods on silicon wafers, without scribing, dicing, and mounting each device on individual vacuum-compatible headers. This device also speeds up the entire data-acquisition process by requiring only one ultrahigh-vacuum pumpdown and one set of vacuum feedthroughs.

  7. Ultrahigh-vacuum field emitter array wafer tester

    NASA Astrophysics Data System (ADS)

    Gray, H. F.; Ardis, L.; Campisi, G. J.

    1987-02-01

    The device reported here allows the researcher the opportunity of gaining primitive yield information, threshold voltages, emission stability, and other information, e.g., gas effects, on field emitter arrays (FEA) which are microminiature ``vacuum tubes'' fabricated by microelectronic processing methods on silicon wafers, without scribing, dicing, and mounting each device on individual vacuum-compatible headers. This device also speeds up the entire data-acquisition process by requiring only one ultrahigh-vacuum pumpdown and one set of vacuum feedthroughs.

  8. A photo-sensor on thin polysilicon membrane embedded in wafer level package LED

    NASA Astrophysics Data System (ADS)

    Kim, Jin Kwan; Lee, Hee Chul

    2012-06-01

    A wafer level packaging LED with photo-sensor which is fabricated on thin poly-silicon membrane located on the corner of silicon cavity is presented in this paper. The wafer substrate was fabricated with (100) orientation silicon wafer and a cavity was etched on the top of the wafer with wet chemical anisotropic etching process for mounting a LED chip. A thin polysilicon membrane was fabricated on the corner of the cavity and a MSM (Metal Semiconductor Metal) type photo-sensor was fabricated on the thin polysilicon membrane. The photo-sensor fabrication and LED packaging were completed on wafer level. The embedded photo-sensor in a wafer level packaging LED is designed to measure light intensity of a LED. The membrane structure photo-sensor can sense the light of the mounted LED directly, so it can measure accurate light intensity of the wafer level packing LED.

  9. Influence of the bonding front propagation on the wafer stack curvature

    SciTech Connect

    Navarro, E.; Bréchet, Y.; Barthelemy, A.; Radu, I.; Pardoen, T.; Raskin, J.-P.

    2014-08-11

    The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

  10. Nanoimprint template fabrication using wafer pattern for sub-30nm

    NASA Astrophysics Data System (ADS)

    Park, C. M.; Kim, K. J.; Lee, Y. J.; Cho, K. Y.; Lee, Y. M.; Park, J. O.; Kim, In S.; Yeo, J. H.; Choi, S. W.; Park, C. H.; Lee, D. H.; Lee, B. K.; Hwang, S. W.

    2010-03-01

    Patterning of sub-30 nm features using high resolution nano-imprint lithography (NIL) requires use of quartz templates. To this end, various fabrication methods such as e-beam lithography, edge lithography, and focused ion beam lithography were employed for the template formation. Despite significant advances using these methods, NIL template formation process suffers from low throughput and high cost of fabrication when compared with the fabrication of masks used in optical lithography. This is largely owing to a 4X difference in feature sizes involved for the fabrication of NIL template and optical lithography mask. In this paper, we report on a simple, cost-effective method for the fabrication of sub-30 nm NIL templates. Typical fabrication-time required for the formation of sub-30 nm HP templates using conventional Gaussian beam electron beam lithography, runs into several days. Additionally, complicated etch procedures must be employed for pattern transfer onto quartz substrates. Here we propose a low cost, simplified fabrication process for the formation of high resolution NIL templates using wafer pattern replication. We fabricated sub- 30nmHP poly-silicon lines and spaces on silicon wafer using multiple patterning technique. These patterns were subsequently transferred onto quartz substrates using NIL technique. Several types of features were studied to realize a template using the triple patterning technique described above. Results of wafer printing using the said template will be discussed.

  11. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, C.M.; Hui, W.C.

    1996-11-19

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

  12. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, Conrad M.; Hui, Wing C.

    1996-01-01

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

  13. Physical mechanisms of copper-copper wafer bonding

    NASA Astrophysics Data System (ADS)

    Rebhan, B.; Hingerl, K.

    2015-10-01

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing.

  14. Wettability investigating on the wet etching textured multicrystalline silicon wafer

    NASA Astrophysics Data System (ADS)

    Liu, Xiangju; Niu, Yuchao; Zhai, Tongguang; Ma, Yuying; Zhen, Yongtai; Ma, Xiaoyu; Gao, Ying

    2016-02-01

    In order to investigate the wettability properties of multicrystalline silicon (mc-Si), the different surface structures were fabricated on the as-cut p-type multi-wire slurry sawn mc-Si wafers, such as as-cut, polished and etched in various acid solutions. The contact angles and the XRD spectra of these samples were measured. It was noted that both the surface structures and the use of surfactant, such as Tween 80, made a stronger effect on wettability of the Si wafer. Due to the lipophilic groups of Tween 80 combined with the Si atoms while the hydrophilic groups of it were outward, a lipophilic surface of Si changed into a hydrophilic one and the rougher the surface, the stronger the hydrophily. Thus, it is feasible to add an appropriate surfactant into the etching solution during black-Si wafer fabrication for solar cells. In addition, different crystal plains of Si had different dangling bond density, so that their surface energies were different. A surface with higher surface energy could attract more water atoms and its wettability was better. However, the effect of crystal plain on the surface wettability was much weaker than surface morphology.

  15. Bulk Laser Material Modification: Towards a Kerfless Laser Wafering Process

    NASA Astrophysics Data System (ADS)

    LeBeau, James

    Due to the ever increasing relevance of finer machining control as well as necessary reduction in material waste by large area semiconductor device manufacturers, a novel bulk laser machining method was investigated. Because the cost of silicon and sapphire substrates are limiting to the reduction in cost of devices in both the light emitting diode (LED) and solar industries, and the present substrate wafering process results in >50% waste, the need for an improved ingot wafering technique exists. The focus of this work is the design and understanding of a novel semiconductor wafering technique that utilizes the nonlinear absorption properties of band-gapped materials to achieve bulk (subsurface) morphological changes in matter using highly focused laser light. A method and tool was designed and developed to form controlled damage regions in the bulk of a crystalline sapphire wafer leaving the surfaces unaltered. The controllability of the subsurface damage geometry was investigated, and the effect of numerical aperture of the focusing optic, energy per pulse, wavelength, and number of pulses was characterized for a nanosecond pulse length variable wavelength Nd:YAG OPO laser. A novel model was developed to describe the geometry of laser induced morphological changes in the bulk of semiconducting materials for nanosecond pulse lengths. The beam propagation aspect of the model was based on ray-optics, and the full Keldysh multiphoton photoionization theory in conjuncture with Thornber's and Drude's models for impact ionization were used to describe high fluence laser light absorption and carrier generation ultimately resulting in permanent material modification though strong electron-plasma absorption and plasma melting. Although the electron-plasma description of laser damage formation is usually reserved for extremely short laser pulses (<20 ps), this work shows that it can be adapted for longer pulses of up to tens of nanoseconds. In addition to a model describing damage formation of sub-band gap energy laser light in semiconducting and transparent crystalline dielectrics, a novel nanosecond laser process was successfully realized to generate a thin plane of damage in the bulk of sapphire wafers. This was accomplished using high numerical aperture optics, a variable wavelength nanosecond laser source, and three-dimensional motorized precision stage control.

  16. The optimization of FA/O barrier slurry with respect to removal rate selectivity on patterned Cu wafers

    NASA Astrophysics Data System (ADS)

    Yi, Hu; Yan, Li; Yuling, Liu; Yangang, He

    2016-02-01

    Because the polishing of different materials is required in barrier chemical mechanical planarization (CMP) processes, the development of a kind of barrier slurry with improved removal rate selectivity for Cu/barrier/TEOS would reduce erosion and dishing defects on patterned Cu wafers. In this study, we developed a new benzotriazole-free barrier slurry named FA/O barrier slurry, containing 20 mL/L of the chelating agent FA/O, 5 mL/L surfactant, and a 1:5 concentration of abrasive particles. By controlling the polishing slurry ingredients, the removal rate of different materials could be controlled. For process integration considerations, the effect of the FA/O barrier slurry on the dielectric layer of the patterned Cu wafer was investigated. After CMP processing by the FA/O barrier slurry, the characteristics of the dielectric material were tested. The results showed that the dielectric characteristics met demands for industrial production. The current leakage was of pA scale. The resistance and capacitance were 2.4 kω and 2.3 pF, respectively. The dishing and erosion defects were both below 30 nm in size. CMP-processed wafers using this barrier slurry could meet industrial production demands. Project supported by the Special Project Items No. 2 in National Long-Term Technology Development Plan (No. 2009ZX02308), the Natural Science Foundation of Hebei Province (No. F2012202094), and the Doctoral Program Foundation of Xinjiang Normal University Plan (No. XJNUBS1226).

  17. Gas cluster ion beam processing of gallium antimonide wafers for surface and sub-surface damage reduction

    NASA Astrophysics Data System (ADS)

    Li, X.; Goodhue, W. D.; Santeufeimio, C.; Tetreault, T. G.; MacCrimmon, R.; Allen, L. P.; Bliss, D.; Krishnaswami, K.; Sung, C.

    2003-09-01

    In order to bring low-power epitaxy-based gallium antimonide (GaSb) electronics and electro-optics to market, high-quality GaSb substrates with smooth surfaces and no surface damage are required. Here, a novel final polishing technique, gas cluster ion beam (GCIB) processing, is shown to improve the surface finish of chemical-mechanical polished (CMP) 50 mm (1 0 0) GaSb wafers by etching and smoothing CMP surface atoms through the sub-surface damage. For the first time, a fluorine-based gas cluster ion beam is reported for GCIB surface etching and smoothing of GaSb material. For the selected processing sequence, the surface roughness of a high-quality, 0.70 nm RMS GaSb wafer was reduced to 0.18 nm RMS without any observed changes in the full-widths at half-maximum (FWHM) of the (4 0 0) and (1 1 1) X-ray peaks of 14 and 20 arcsec, respectively. Results indicate that the GCIB process did not contribute to wafer surface or sub-surface polish damage. In a second case, a GCIB etch removed 200 nm of material from a non-optimal CMP (1 0 0) GaSb surface and reduced the full-width at half-maximum (1 1 1) X-ray peak from 76 to 52 arcsec in conjunction with a surface roughness decrease from 0.70 to 0.35 nm RMS. The data suggests that GCIB processing appears to be promising as a final GaSb wafer polish with an etch rate compatible for large scale manufacturing.

  18. Photostimulated near-infrared persistent luminescence as a new optical read-out from Cr3+-doped LiGa5O8

    PubMed Central

    Liu, Feng; Yan, Wuzhao; Chuang, Yen-Jun; Zhen, Zipeng; Xie, Jin; Pan, Zhengwei

    2013-01-01

    In conventional photostimulable storage phosphors, the optical information written by x-ray or ultraviolet irradiation is usually read out as a visible photostimulated luminescence (PSL) signal under the stimulation of a low-energy light with appropriate wavelength. Unlike the transient PSL, here we report a new optical read-out form, photostimulated persistent luminescence (PSPL) in the near-infrared (NIR), from a Cr3+-doped LiGa5O8 NIR persistent phosphor exhibiting a super-long NIR persistent luminescence of more than 1,000 h. An intense PSPL signal peaking at 716 nm can be repeatedly obtained in a period of more than 1,000 h when an ultraviolet-light (250–360 nm) pre-irradiated LiGa5O8:Cr3+ phosphor is repeatedly stimulated with a visible light or a NIR light. The LiGa5O8:Cr3+ phosphor has promising applications in optical information storage, night-vision surveillance, and in vivo bio-imaging. PMID:23532003

  19. The terminal portion of leptospiral immunoglobulin-like protein LigA confers protective immunity against lethal infection in the hamster model of leptospirosis

    PubMed Central

    Silva, verton F.; Medeiros, Marco A.; McBride, Alan J. A.; Matsunaga, Jim; Esteves, Gabriela S.; Ramos, Joo G. R.; Santos, Cleiton S.; Croda, Jlio; Homma, Akira; Dellagostin, Odir A.; Haake, David A.; Reis, Mitermayer G.; Ko, Albert I.

    2007-01-01

    Subunit vaccines are a potential intervention strategy against leptospirosis, which is a major public health problem in developing countries and a veterinary disease in livestock and companion animals worldwide. Leptospiral immunoglobulin-like (Lig) proteins are a family of surface-exposed determinants that have Ig-like repeat domains found in virulence factors such as intimin and invasin. We expressed fragments of the repeat domain regions of LigA and LigB from Leptospira interrogans serovar Copenhageni. Immunization of Golden Syrian hamsters with Lig fragments in Freunds adjuvant induced robust antibody responses against recombinant protein and native protein, as detected by ELISA and immunoblot, respectively. A single fragment, LigANI, which corresponds to the six carboxy-terminal Ig-like repeat domains of the LigA molecule, conferred immunoprotection against mortality (67-100%, P <0.05) in hamsters which received a lethal inoculum of L. interrogans serovar Copenhageni. However, immunization with this fragment did not confer sterilizing immunity. These findings indicate that the carboxy-terminal portion of LigA is an immunoprotective domain and may serve as a vaccine candidate for human and veterinary leptospirosis. PMID:17629368

  20. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  1. High transmittance silicon terahertz polarizer using wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Yu, Ting-Yang; Tsai, Hsin-Cheng; Wang, Shiang-Yu; Luo, Chih-Wei; Chen, Kuan-Neng

    2015-08-01

    Due to the difficulties faced in fabricating robust Terahertz (THz) optical components with low Fresnel reflection loss, the need to increase the efficiency of THz system with reduced cost is still considered as one of the most essential tasks. In this report, a new low cost THz polarizer with robust structure is proposed and demonstrated. This new THz wire grid polarizer was based on an anti-reflection (AR) layer fabricated with low temperature metal bonding and deep reactive ion etching (DRIE). After patterning Cu wire gratings and the corresponding In/Sn solder ring on the individual silicon wafers, the inner gratings were sealed by wafer-level Cu to In/Sn guard ring bonding, providing the protection against humidity oxidation and corrosion. With the low eutectic melting point of In/Sn solder, wafers could be bonded face to face below 150°C. Two anti-reflection layers on both outward surfaces were fabricated by DRIE. With the mixing of empty holes and silicon, the effective refractive index was designed to be the square root of the silicon refractive index. The central frequency of the anti-reflection layers was designed between 0.5THz to 2THz with an approximate bandwidth of 0.5THz. The samples were measured with a commercial free-standing wire grid polarizer by a THz time domain spectroscopy (THz-TDS) from 0.2THz to 2.2THz. The power transmittance is close to 100% at central frequency. Extinction ratio of the polarizer is between 20dB to 40dB depending on the frequency. The advantages of this new polarizer include high transmittance, robust structure and low cost with no precision optical alignment required.

  2. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  3. Generation and detection of guided waves using PZT wafer transducers.

    PubMed

    Nieuwenhuis, Jeroen H; Neumann, John J; Greve, David W; Oppenheim, Irving J

    2005-11-01

    We report here the use of finite element simulation and experiments to further explore the operation of the wafer transducer. We have separately modeled the emission and detection processes. In particular, we have calculated the wave velocities and the received voltage signals due to A0 and S0 modes at an output transducer as a function of pulse center frequency. These calculations include the effects of finite pulse width, pulse dispersion, and the detailed interaction between the piezoelectric element and the transmitting medium. We show that the received signals for A0 and S0 modes have maxima near the frequencies predicted from the previously published point-force model. PMID:16422424

  4. A sliding wafer-OMVPE scheme for fabricating subnanometer superlattices

    NASA Astrophysics Data System (ADS)

    Minagawa, S.; Satoh, S.; Nakatsuka, S.; Kakibayashi, H.

    1988-03-01

    A sliding wafer-OMVPE (Organometallic Vapor Phase Epitaxy) reactor suitable for growing superlattices is developed. The reactor is a two-channel horizontal reactor with a susceptor placed across the two channels. A slider is used to transport the substrate by sliding it along the susceptor surface from one channel to the other. This scheme makes it possible to set the temperature of the susceptor in each channel independently by utilizing the skin effect of radio wave in graphite. The performance of this scheme is demonstrated by growing a superlattice of ten periods of GaAs(3.5 Å)/AlAs(7 Å).

  5. Propagation of Nd-laser pulses through crystalline silicon wafers

    SciTech Connect

    Kirichenko, N A; Kuzmin, P G; Shcherbina, M E

    2011-07-31

    Propagation of pulses from an Nd:YAG laser (wavelength, 1.064 {mu}m; pulse duration, 270 ns; pulse energy, 225 {mu}J) through crystalline silicon wafers is studied experimentally. Mathematical modelling of the process is performed: the heat conduction equation is solved numerically, the temperature dependences of the absorption and refraction of a substance, as well as generation of nonequilibrium carriers by radiation are taken into account. The constructed model satisfactorily explains the experimentally observed intensity oscillations of transmitted radiation. (interaction of laser radiation with matter)

  6. Advanced Ceramic Wafer Seals Demonstrated at 2000 deg. F

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Durable, high-temperature sliding seals are required in advanced hypersonic engines and around movable control surfaces on future vehicles. These seals must operate at temperatures of 2000 to 2500 F, limit hot gas flow, remain resilient for multiple cycles, and resist scrubbing damage against rough surfaces. Current seal designs do not meet these demanding requirements, so the NASA Glenn Research Center is developing advanced seals and preload devices to overcome these shortfalls. An advanced ceramic wafer seal design and two silicon nitride compression spring designs were evaluated in a series of compression, scrub, and flow tests.

  7. On the residual stress and fracture strength of crystalline silicon wafers

    NASA Astrophysics Data System (ADS)

    Yang, Chris; Mess, Frank; Skenes, Kevin; Melkote, Shreyes; Danyluk, Steven

    2013-01-01

    This letter reports on residual stress measurement in thin crystalline silicon wafers with a full-field near-infrared polariscope. Residual stress is analyzed in combination with observed surface defects, and the results are related to measured fracture strength variation in the wafers. Measurements indicate that there is a sawing process-related residual stress in the as-cut wafers, and that etch-removal of ˜5 μm from the wafer surface eliminates a damage layer that can significantly reduce the residual stress in the wafer, and therefore increases the observed fracture strength. There is a corresponding 2 to 3 μm reduction in the observed characteristic defect size after etching. Fracture strength anisotropy observed in the wafers is related to defect orientation (scratching grooves and microcracks) caused by the sawing process.

  8. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

    1979-01-01

    A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

  9. Magnetic Phase Diagram of the Breathing Pyrochlore Antiferromagnet LiGa1-xInxCr4O8

    NASA Astrophysics Data System (ADS)

    Okamoto, Yoshihiko; Nilsen, Gøran J.; Nakazono, Taishi; Hiroi, Zenji

    2015-04-01

    The spinel oxides LiGaCr4O8 and LiInCr4O8 contain size-alternating pyrochlore lattices of spin-3/2 Cr3+ tetrahedra with different magnitudes of alternation. We show here that the solid solutions LiGa1-xInxCr4O8 between these two "breathing" pyrochlore compounds display (i) rapid suppression of magnetic and structural transitions upon doping the end members, (ii) spin-glass-like freezing above 2 K in the range 0.1 ≲ x ≲ 0.6, and (iii) apparent spin-gap behavior for x ≳ 0.7. Furthermore, no transitions are observed above 2 K at x ˜ 0.9, where magnetic susceptibility remains finite at 2 K and magnetic heat capacity shows a quadratic temperature dependence at 1-5 K. Our work shows that breathing pyrochlore compounds provide a unique opportunity for studying both geometrical frustration and bond alternation.

  10. Fabrication of micro nickel/diamond abrasive pellet array lapping tools using a LIGA-like technology

    NASA Astrophysics Data System (ADS)

    Luo, Sheng-Yih; Yu, Tsung-Han; Hu, Yuh-Chung

    2007-06-01

    A manufacturing process of micro nickel/diamond abrasive pellet array lapping tools using a LIGA-like technology is reported here. The thickness of JSR THB-151N resist coated on an aluminum alloy substrate for micro lithography can reach up to 110 µm. During the lithography, different geometrical photomasks were used to create specific design patterns of the resist mold on the substrate. Micro roots, made by electrolytic machining on the substrate with guidance of the resist mold, can improve the adhesion of micro nickel abrasive pellets electroplated on the substrate. During the composite electroforming, the desired hardness of the nickel matrix inside the micro diamond abrasive pellets can be obtained by the addition of leveling and stress reducing agents. At moderate blade agitation and ultrasonic oscillation, higher concentration and more uniform dispersion of diamond powders deposited in the nickel matrix can be achieved. With these optimal experiment conditions of this fabrication process, the production of micro nickel/diamond abrasive pellet array lapping tools is demonstrated.

  11. Determination of wafer center position during the transfer process by using the beam-breaking method

    NASA Astrophysics Data System (ADS)

    Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

    2014-09-01

    A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human-machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions.

  12. Improved quality control of silicon wafers using novel off-line air pocket image analysis

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Sanna, M. Cristina

    2014-08-01

    Air pockets (APK) occur randomly in Czochralski (Cz) grown silicon (Si) crystals and may become included in wafers after slicing and polishing. Previously the only APK of interest were those that intersected the front surface of the wafer and therefore directly impacted device yield. However mobile and other electronics have placed new demands on wafers to be internally APK-free for reasons of thermal management and packaging yield. We present a novel, recently patented, APK image processing technique and demonstrate the use of that technique, off-line, to improve quality control during wafer manufacturing.

  13. Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes

    NASA Astrophysics Data System (ADS)

    Peterson, Joel; Rusk, Gary; Veeraraghavan, Sathish; Huang, Kevin; Koffas, Telly; Kimani, Peter; Sinha, Jaydeep

    2015-03-01

    The semiconductor industry continues to push the limits of immersion lithography through multiple patterning techniques for printing features with critical dimension 20 nm and below. As a result overlay has become one of the critical lithography control parameters impacting device performance and has a stringent budget for yielding at smaller half pitch nodes. Overlay has several sources of errors related to scanner, lens, mask, and wafer. Lithographers have developed both linear and higher order field and wafer models to successfully compensate for the static fingerprints from different sources of error. After the static modeled portion of the fingerprint is removed, the remaining overlay error can be characterized as unstable modeled error or un-modeled error, commonly called uncorrectable residual error. This paper explores the fundamental relationship of overlay to wafer geometry through mechanisms of process-induced contributions to the wafer overlay, categorized as plastic and elastic wafer deformation. Correlation of overlay to local features such as slip lines is proven experimentally. The paper describes methodologies and geometry-induced overlay metrics for the application of wafer geometry to perform overlay feedback and feed forward applications. Feedback applications allow for process development and controlling semiconductor processes through in-line monitoring of wafers. Feed forward applications could include geometrybased corrections to the scanner for compensating non-static wafer geometry related overlay errors, and grouping wafers based on higher-order geometry.

  14. A practical approach to LWIR wafer-level optics for thermal imaging systems

    NASA Astrophysics Data System (ADS)

    Symmons, Alan; Pini, Ray

    2013-06-01

    The development and implementation of wafer level packaging for commercial microbolometers has opened the pathway towards full wafer-based thermal imaging systems. The next challenge in development is moving from discrete element LWIR imaging systems to a wafer based optical system, similar to lens assemblies found in cell phone cameras. This paper will compare a typical high volume thermal imaging design manufactured from discrete lens elements to a similar design optimized for manufacture through a wafer based approach. We will explore both performance and cost tradeoffs as well as review the manufacturability of all designs.

  15. Effect of internal stresses on the mechanical parameters of silicon wafers

    SciTech Connect

    Oksanich, A.P.; Cherner, V.M.; Tuzovskii, K.A.

    1988-12-01

    The authors examined how the mechanical parameters of silicon wafers vary with the stress area. The polished (100) wafers were cut from a billet grown by Czochralski's method. The internal stresses were produced by moving the wafers in and out of an oven having a working zone at 1420 K. Then the oxide film was removed. The area of the stressed parts was determined by photoelasticity. The mechanical parameters were measured with contactless pneumatic loading and continuous central deflection measurement. The internal stresses affect the properties; at a given load the central deflection in an unstressed wafer is larger than in a stressed one.

  16. Measuring the thickness profiles of wafers to subnanometer resolution using Fabry-Perot interferometry

    SciTech Connect

    Farrant, David I.; Arkwright, John W.; Fairman, Philip S.; Netterfield, Roger P

    2007-05-20

    The resolution of an angle-scanning technique for measuring transparent optical wafers is analyzed, and it is shown both theoretically and experimentally that subnanometer resolution can be readily achieved. Data are acquired simultaneously over the whole area of the wafer, producing two-dimensional thickness variation maps in as little as 10 s.Repeatabilities of 0.07 nm have been demonstrated, and wafers of up to100 mm diameter have been measured, with1 mm or better spatial resolution. A technique for compensating wafer and system aberrations is incorporated and analyzed.

  17. Bare wafer metrology challenges in microlithography at 45 nm node and beyond

    NASA Astrophysics Data System (ADS)

    Huang, Chunsheng

    2008-03-01

    The shrinking depth of focus (100-150 nm) of high numerical aperture immersion microlithography optics dictates a tight wafer flatness budget. Wafer flatness nanotopography (NT), and edge roll off (ERO) are critical parts of the equation in immersion microlithographic technology at the 45 nm node and beyond. Wafer features at the nanometer level could result not only in focus variation of the litho process, or thin film thickness variation in CMP process, but also in structural defects of the devices. Therefore, the metrology to measure nanometer level features and to control the quality of wafer geometry is a key to the success of IC production at the 45 nm node and beyond.

  18. Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

    NASA Astrophysics Data System (ADS)

    Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

    2015-07-01

    Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

  19. How accurate are rapid prototyped (RP) final orthognathic surgical wafers? A pilot study.

    PubMed

    Shqaidef, Abedalrahman; Ayoub, Ashraf F; Khambay, Balvinder S

    2014-09-01

    Computer packages have been introduced to simulate the movements of the jaw in three dimensions to facilitate planning of treatment. After final 3-dimensional virtual planning, a rapid prototype wafer can be manufactured and used in theatre. Our aim was to assess the accuracy of rapid prototyping of virtual wafers derived from laser scanned dental models using CAD/CAM software. Upper and lower plaster models from 10 orthognathic patients, the articulated models, and the conventional wafers were scanned. The virtual wafers were made from CAD/CAM software, and printed on a stereolithographic printer. We also scanned the articulated models with rapid prototype wafers in place. The validity of the final rapid prototype wafer was measured by the accuracy with which upper and lower models related to one another. The absolute mean error of the rapid prototype wafer when aligned with the dental models was 0.94 (0.09) mm. The absolute distance of the 2 models articulated by conventional and rapid prototype wafers ranged from 0.04 - 1.73mm. The rapid prototype wafers were able to orientate the upper and lower dental models with an absolute mean error of 0.94 (0.09) mm, but it ranged from 0.04-1.73mm. PMID:24933576

  20. The optimization of CD uniformity and measurement on mask and wafer

    NASA Astrophysics Data System (ADS)

    Choi, Yongkyoo; Kim, Munsik; Han, Oscar

    2007-05-01

    As pattern size is shrinking, required mask CD specification is tighter and its effect on wafer patterning is more severe. To enhance the device performance, wafer CD uniformity should be enhanced and controlled by mask global CD uniformity. Mask global CD uniformity usually can be enhanced by mask process and optimal fogging effect correction. To enhance the mask global CD uniformity on mask, resist process and FEC (Fogging Effect Correction), reliable CD measurement tool and methods are necessary. Recently, group CD using OCD(Spectroscopic Ellipsometer) or AIMS(Aerial Image Measurement and Simulation) is used to represent global CD variation on mask. These methods are removing local CD variation on mask. Because local CD variation on wafer is large compared with the effect of local CD variation of mask, global CD uniformity can be measured with suppressed local CD variation [1]. In this paper, local CD variation of mask and wafer is evaluated, and area CD and smoothing methods are used to measure CD on mask and wafer, and the correlation of global CD of mask and field CD of wafer are evaluated. By these methods, CD measurement repeatability can be enhanced to get closer correlation of mask and wafer. Close correlation makes fine CD correction on mask to get better field CD uniformity on wafer. And the repeatability of field to field CD uniformity of wafer is evaluated according to measurement tool of CD-SEM and scatterometry.

  1. Progress on 300-mm wafer lithography equipment and processes

    NASA Astrophysics Data System (ADS)

    Mautz, Karl E.; Maltabes, John G.

    2001-09-01

    SEMICONDUCTOR300 was the first pilot-production facility for 300mm wafers in the world. The company, a joint venture between Motorola, Inc. and Infineon Technologies started in early 1998 to test and compare process, metrology and probe equipment, develop robust processes, and manufacture products using a 300mm wafer tool set. The lithography tools included I-line steppers, an I-line scanner, a DUV stepper, and DUV scanners. All of these exposure tools were running in-line with various photoresist coat and develop tracks. The lithography tools were used to build both 64M and 256M DRAM devices and aggressive test vehicles. The process capability of the initial 0.25 micrometers reference process was done and compared to the 200mm data set of the sister factory. Automation issues for lithography tools were addressed and the cost metrics were calculated. SC300 demonstrated that a manufacturable 300mm lithography tool set and process for various ground rule devices was possible with the required performance in image transfer, CD control, and overlay. Further testing on 0.18micrometers and 0.15micrometers ground rule features indicated a sufficient process window for potential manufacturing. Additionally, it was demonstrated that non-concentric subfield stepping was feasible.

  2. Deposition and removal of sodium contamination on silicon wafers

    NASA Astrophysics Data System (ADS)

    Constant, I.; Tardif, F.; Derrien, J.

    2000-01-01

    In this paper investigations are performed in order to understand the source of sodium contamination in clean-room environments and to find different cleaning processes able to limit or suppress sodium deposition. In a clean-room environment, the human being has been identified as one of the major sources of sodium. The airborne sodium contamination is essentially transmitted in particle form. In order to limit sodium deposition from the air, the wafers awaiting subsequent processing need to be stored in a protective box or placed far from the human environment and should not be left for much more than 1 week in a class 1 clean room. Also, wet chemistries could cause sodium contamination on wafers particularly during the deionized water rinse. In order to limit the possible contamination, the sodium deposition mechanisms have been studied: they show the typical characteristics of Langmuir adsorption. Temperature and ionic concentration are both parameters which influence the deposition. In water, sodium deposition can be avoided by introducing acid or alkaline solutions or increasing the temperature: it can be drastically reduced by adding traces of HCl (0.01%). Finally, other cleaning chemistries such as SC1 (NH4 OH-H2 O2 -H2 O) in 0.25:1:5 proportion, SC2 (HCl-H2 O2 -H2 O) in 1:1:5 proportion, 0.1% HF and SPM (H2 SO4 -H2 O2 ) in 3:1 proportion reduce the contamination as well.

  3. Process Performance of Optima XEx Single Wafer High Energy Implanter

    SciTech Connect

    Kim, J. H.; Yoon, Jongyoon; Kondratenko, S.; David, J.; Rubin, L. M.; Jang, I. S.; Cha, J. C.; Joo, Y. H.; Lee, A. B.; Jin, S. W.

    2011-01-07

    To meet the process requirements for well formation in future CMOS memory production, high energy implanters require more robust angle, dose, and energy control while maintaining high productivity. The Optima XEx high energy implanter meets these requirements by integrating a traditional LINAC beamline with a robust single wafer handling system. To achieve beam angle control, Optima XEx can control both the horizontal and vertical beam angles to within 0.1 degrees using advanced beam angle measurement and correction. Accurate energy calibration and energy trim functions accelerate process matching by eliminating energy calibration errors. The large volume process chamber and UDC (upstream dose control) using faraday cups outside of the process chamber precisely control implant dose regardless of any chamber pressure increase due to PR (photoresist) outgassing. An optimized RF LINAC accelerator improves reliability and enables singly charged phosphorus and boron energies up to 1200 keV and 1500 keV respectively with higher beam currents. A new single wafer endstation combined with increased beam performance leads to overall increased productivity. We report on the advanced performance of Optima XEx observed during tool installation and volume production at an advanced memory fab.

  4. Cryogenic wafer-level MWIR camera: laboratory demonstration

    NASA Astrophysics Data System (ADS)

    Druart, G.; De La Barrière, F.; Chambon, M.; Guérineau, N.; Lasfargues, G.; Fendler, M.

    2013-06-01

    We present a compact infrared cryogenic multichannel camera with a wide field of view equal to 120°. By merging the optics with the detector, the concept has to be compatible with both cryogenic constraints and wafer-level fabrication. For this, we take advantage of the progress in micro-optics to design a multichannel optical architecture directly integrated on the detector. This wafer-level camera uses state of art microlenses with a high sag height. The additional mass of the optics is sufficiently small to be compatible with the cryogenic environment of the Dewar. The performance of this camera will be discussed. Its characterization has been carried out in terms of modulation transfer function and noise equivalent temperature difference (NETD). The optical system is limited by the diffraction. By cooling the optics, we achieve a very low NETD equal to 15 mK compared with traditional infrared cameras. A postprocessing algorithm that aims at reconstructing a well-sampled image from the set of undersampled raw subimages produced by the camera is proposed and validated on experimental images.

  5. Laser-Assisted Chemical Polishing of Silicon (112) Wafers

    NASA Astrophysics Data System (ADS)

    Dandekar, Niru; Chivas, Robert; Silverman, Scott; Kou, Xiaolu; Goorsky, Mark

    2012-10-01

    Pulsed laser-assisted chemical etching (PLACE) offers an advanced, novel substrate preparation method for molecular beam epitaxy (MBE) growth of mercury cadmium telluride on silicon (112) wafers. By controlling the laser fluence, the chemical etch process is refined into a final polish step. PLACE offers surface roughness on the order of chemical mechanical polishing standards and has been verified by 488-nm Raman and high-resolution x-ray diffraction as causing no surface or subsurface damage. To the contrary, experiments show that using PLACE not only alters the surface chemically but also removes subsurface damage through recrystallization reaching micron depths. The process occurs in a modular vacuum chamber that could conceivably be transferred between tools so that vacuum is not broken between polishing and MBE deposition. PLACE can achieve ultra-high-purity and fine dimensional control since it is a dry process relying on pyrolytic vapor-phase reactions initiated, and constrained, by a pulsed laser. Since the process is a function of laser fluence and optics, it is imminently scalable to 6-inch wafer sizes and beyond.

  6. New fabrication method of glass packages with inclined optical windows for micromirrors on wafer level

    NASA Astrophysics Data System (ADS)

    Stenchly, Vanessa; Quenzer, Hans-Joachim; Hofmann, Ulrich; Janes, Joachim; Jensen, Björn; Benecke, Wolfgang

    2013-03-01

    For many applications it is inevitable to protect MEMS devices against environmental impacts like humidity which can affect their performance. Moreover recent publications demonstrates that micro mirrors can achieve very large optical scan angles at moderate driving voltages even exceeding 100 degrees when hermetically sealed under vacuum. While discrete chips may be evacuated and sealed on single die level using small can packages like TO housings, it is obvious that for high volume production a much more economical solution for the realisation of transparent optical packages already on wafer level must be developed. However, since any laser beam crossing a transparent glass surface is partly reflected even when anti-reflective coatings are applied, the construction of a wafer level optical housing suitable for laser projection purpose requires more than the integration of simple plane glass cap. The use of inclined optical windows avoids the occurrence of intense reflections of the incident laser beam in the projected images. This paper describes a unique technology to fabricate glass packages with inclined optical windows for micro mirrors on 8 inch wafers. The new process uses a high temperature glass forming process based on subsequent wafer bonding. A borosilicate glass wafer is bonded together with two structured silicon wafers. By grinding both sides of the wafer stack, a pattern of isolated silicon structures is defined. This preprocessed glass wafer is bonded thereon on a third structured silicon wafer, wherein the silicon islands are inserted into the cavities. By setting a defined pressure level inside the cavities during the final wafer bonding, the silicon glass stack extruded and it is out of plane during a subsequent annealing process at temperatures above the softening point of the glass. Finally the silicon is selectively removed in a wet etching process. This technique allows the fabrication of 8 inch glass wafers with oblique optical surfaces with surface roughness <1 nm and an evenness of < 300 nm.

  7. Alternative fabrication process for edgeless detectors on 6 in. wafers

    NASA Astrophysics Data System (ADS)

    Kalliopuska, Juha; Eränen, Simo; Virolainen, Tuula

    2011-05-01

    VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150 μm thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 5×5 and 1×1 cm2 edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.4×1.4 cm2 Medipix2 edgeless pixel detectors were also fabricated.This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100 μm from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50-70 nA/cm2 and 580-660 pF/cm2 at, respectively, 40 V reverse bias for the p-on-n. For the n-on-n design these parameters were 116-118 nA/cm2 and 930-960 pF/cm2. The breakdown voltages were above 150 V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13-28 V.

  8. Experimental investigation of piezoelectric wafers in monitoring the resin transfer moulding process

    NASA Astrophysics Data System (ADS)

    Wang, Xiaoming; Ehlers, Claus; Kissinger, Christian; Neitzel, Manfred; Ye, Lin; Mai, Yiu-Wing

    1998-02-01

    The objective of monitoring the composite manufacturing process resin transfer moulding (RTM) is pursued by means of applying piezoelectric wafers. First, the sensitivity of the piezoelectric wafers to their area wetted by a viscous liquid was evaluated to shed light on the possibility of utilizing the wafers for the inspection of the resin flow front during RTM. Further, the wafers were immersed in various liquids of different viscosity, to confirm their ability to distinguish such difference. The ability would then be employed to monitor the curing process before gelling of resins. Thirdly, the experimental set-up proved the validity of the wafers for sensing the change of temperature associated with the curing process around the gel point. The overall capability of the piezoelectric wafers to monitor the injection and curing process of thermosets in RTM was investigated, incorporating the wafers in random glass fibre mats of a preform injected with a thermoset resin. Experimental verification has shown promising results and demonstrated potential for using piezoelectric wafers as a novel method for complete process monitoring of composite manufacturing.

  9. Automatic on-line wafer stepper calibration system

    NASA Astrophysics Data System (ADS)

    van den Brink, Martin A.; Franken, Hans; Wittekoek, Stefan; Fahner, Theo

    1990-06-01

    This paper introduces a new wafer stepper on-line calibration sensor, the Image Sensor, which refers directly to the aerial reticle image at the exposure wavelength. This sensor system is integrated with other stepper metrology systems by a so-called Image Sensor fiducial plate, which interacts simultaneously with the aerial reticle image, the Image Sensor, the TTL alignment system and the focus sensor of the stepper. An integrated software package ensures on-line regular stepper calibration, eliminating dependance on environmental, process and time parameters. Unique in this concept is the direct measurement of the consequence of wavelength drift in excimer laser steppers by measuring the aerial image deformation at the exposure wavelength. This information is used as a direct feedback to the wavelength control of the laser. Initial results of this system are presented for both UV (365 nm) and DUV (248 nm) steppers.

  10. Thin-Film Devices Fabricated With Benzocyclobutene Adhesive Wafer Bonding

    NASA Astrophysics Data System (ADS)

    Christiaens, Ilse; Roelkens, Günther; de Mesel, Kurt; van Thourhout, Dries; Baets, Roel

    2005-02-01

    In this paper, we present and elaborate on die to wafer bonding technology with benzocyclobutene (BCB). This technology allows to fabricate a variety of reliable waferbonded components in a fairly simple way using only standard cleanroom equipment. We demonstrate the fabrication of passive devices such as microring resonators, as well as active components such as lasers and LEDs. We show good performance of these devices by presenting measurements of their characteristics. Furthermore, these devices were subjected to damp-heat testing, demonstrating the good quality of the BCB-bonding procedure. Finally,due to the low thermal conductivity of BCB, thermal management needs some attention. We present an analysis of the thermal problem and suggest a possible solution.

  11. Chemical strategies for die/wafer submicron alignment and bonding.

    SciTech Connect

    Martin, James Ellis; Baca, Alicia I.; Chu, Dahwey; Rohwer, Lauren Elizabeth Shea

    2010-09-01

    This late-start LDRD explores chemical strategies that will enable sub-micron alignment accuracy of dies and wafers by exploiting the interfacial energies of chemical ligands. We have micropatterned commensurate features, such as 2-d arrays of micron-sized gold lines on the die to be bonded. Each gold line is functionalized with alkanethiol ligands before the die are brought into contact. The ligand interfacial energy is minimized when the lines on the die are brought into registration, due to favorable interactions between the complementary ligand tails. After registration is achieved, standard bonding techniques are used to create precision permanent bonds. We have computed the alignment forces and torque between two surfaces patterned with arrays of lines or square pads to illustrate how best to maximize the tendency to align. We also discuss complex, aperiodic patterns such as rectilinear pad assemblies, concentric circles, and spirals that point the way towards extremely precise alignment.

  12. A Wafer Transfer Technology for MEMS Adaptive Optics

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean V.

    2001-01-01

    Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

  13. Effect of lubricant environment on saw damage in silicon wafers

    NASA Technical Reports Server (NTRS)

    Kuan, T. S.; Shih, K. K.; Vanvechten, J. A.; Westdorp, W. A.

    1982-01-01

    The chemomechanical effect of lubricant environments on the inner diameter (ID) sawing induced surface damage in Si wafers was tested for four different lubricants: water, dielectric oil, and two commercial cutting solutions. The effects of applying different potential on Si crystals during the sawing were also tested. It is indicated that the number and depth of surface damage are sensitive to the chemical nature of the saw lubricant. It is determined that the lubricants that are good catalysts for breaking Si bonds can dampen the out of plane blade vibration more effectively and produce less surface damage. Correlations between the applied potential and the depth of damage in the dielectric oil and one of the commercial cutting solutions and possible mechanisms involved are discussed.

  14. Homogenization of CZ Si wafers by Tabula Rasa annealing

    NASA Astrophysics Data System (ADS)

    Meduňa, M.; Caha, O.; Kuběna, J.; Kuběna, A.; Buršík, J.

    2009-12-01

    The precipitation of interstitial oxygen in Czochralski grown silicon has been investigated by infrared absorption spectroscopy, chemical etching, transmission electron microscopy and X-ray diffraction after application of homogenization annealing process called Tabula Rasa. The influence of this homogenization step consisting in short time annealing at high temperature has been observed for various temperatures and times. The experimental results involving the interstitial oxygen decay in Si wafers and absorption spectra of SiOx precipitates during precipitation annealing at 1000C were compared with other techniques for various Tabula Rasa temperatures. The differences in oxygen precipitation, precipitate morphology and evolution of point defects in samples with and without Tabula Rasa applied is evident from all used experimental techniques. The results qualitatively correlate with prediction of homogenization annealing process based on classical nucleation theory.

  15. Transient photoluminescence from silicon wafers: Finite element analysis

    NASA Astrophysics Data System (ADS)

    Wang, Kai; McLean, William; Kampwerth, Henner

    2013-10-01

    This paper presents an accurate and practical mathematical model of time-resolved photoluminescence (PL) response from silicon wafers generated by fast repetitive excitation pulses. The model is valid under low level injection condition and takes into account the depth dependence of carrier generation, diffusion, and surface recombination. Finite element analysis is employed for the carrier density and PL computations. By comparing computational results with results obtained from PC1D (a computer program solving fully coupled nonlinear equations for quasi-one-dimensional carrier transportation in crystalline semiconductor devices, especially focusing on photovoltaic devices), the validity of this method is confirmed. Early stage application and the limitations of this method have been studied, and future work has been proposed.

  16. Nanotribology of nanooxide materials in ionic liquids on silicon wafers

    NASA Astrophysics Data System (ADS)

    Hamidunsani, Ahmad Termizi; Radiman, Shahidan; Hassan, Masjuki Haji; Rahman, Irman Abdul

    2015-09-01

    Nanotribological properties have a significant impact on daily life. Ionic liquids (ILs) are becoming new favourable lubricants currently in researches. Addition of nanooxide materials in lubricants provide improvements to new technology. In this study, we determine nanotribological properties of BMIM+BF4- IL addition of different amount of ZnO nanomaterial on single crystals silicon wafer (Si110). The viscosity changes of IL samples against temperature increase were determined by rheological method. Nanotribological properties were determined by changes in friction coefficient and wear rate on silicon substrate surfaces using a reciprocating friction and wear monitor in 1 hour duration time. Aluminium cylinders acted as pins used to rub Si (110) substrate sample surfaces. Thus, on range between 0 mg to 3.5 mg of ZnO nanooxide material dispersed in 10ml BMIM+BF4- showed a good friction coefficient, wear and surface roughness reduction.

  17. Visible luminescence from silicon wafers subjected to stain etches

    NASA Technical Reports Server (NTRS)

    Fathauer, R. W.; George, T.; Ksendzov, A.; Vasquez, R. P.

    1992-01-01

    Etching of Si in a variety of solutions is known to cause staining. These stain layers consist of porous material similar to that produced by anodic etching of Si in HF solutions. In this work, photoluminescence peaked in the red from stain-etched Si wafers of different dopant types, concentrations, and orientations produced in solutions of HF:HNO3:H2O was observed. Luminescence is also observed in stain films produced in solutions of NaNO2 in HF, but not in stain films produced in solutions of CrO3 in HF. The luminescence spectra are similar to those reported recently for porous Si films produced by anodic etching in HF solutions. However, stain films are much easier to produce, requiring no special equipment.

  18. Kinetic mechanism and fidelity of nick sealing by Escherichia coli NAD+-dependent DNA ligase (LigA)

    PubMed Central

    Chauleau, Mathieu; Shuman, Stewart

    2016-01-01

    Escherichia coli DNA ligase (EcoLigA) repairs 3′-OH/5′-PO4 nicks in duplex DNA via reaction of LigA with NAD+ to form a covalent LigA-(lysyl-Nζ)–AMP intermediate (step 1); transfer of AMP to the nick 5′-PO4 to form an AppDNA intermediate (step 2); and attack of the nick 3′-OH on AppDNA to form a 3′-5′ phosphodiester (step 3). A distinctive feature of EcoLigA is its stimulation by ammonium ion. Here we used rapid mix-quench methods to analyze the kinetic mechanism of single-turnover nick sealing by EcoLigA–AMP. For substrates with correctly base-paired 3′-OH/5′-PO4 nicks, kstep2 was fast (6.8–27 s−1) and similar to kstep3 (8.3–42 s−1). Absent ammonium, kstep2 and kstep3 were 48-fold and 16-fold slower, respectively. EcoLigA was exquisitely sensitive to 3′-OH base mispairs and 3′ N:abasic lesions, which elicited 1000- to >20000-fold decrements in kstep2. The exception was the non-canonical 3′ A:oxoG configuration, which EcoLigA accepted as correctly paired for rapid sealing. These results underscore: (i) how EcoLigA requires proper positioning of the nick 3′ nucleoside for catalysis of 5′ adenylylation; and (ii) EcoLigA's potential to embed mutations during the repair of oxidative damage. EcoLigA was relatively tolerant of 5′-phosphate base mispairs and 5′ N:abasic lesions. PMID:26857547

  19. Microlenticular lens replication by the combination of gas-assisted imprint technology and LIGA-like process

    NASA Astrophysics Data System (ADS)

    Yeh, Chia-Hung; Shih, Ching-Jui; Wang, Hsuan-Cheng; Chang, Fuh-Yu; Young, Hong-Tsu; Chang, Wen-Chuan

    2012-09-01

    A mold used in creating diffractive optical elements significantly affects the quality of these devices. In this study, we improved traditional microlens fabrication processes, which have shortcomings, mainly by combining gas-assisted imprint technology and the lithographie galvanoformung abformung (LIGA)-like process. This combination resulted in the production of high-quality optical components with high replication rates, high uniformity, large areas and high flexibility. Given the pixel size of the panel used, the optimal viewing distance, the film thickness and the glass thickness in the formula, we could determine the radius of curvature and the thickness of the lens. By the use of U-groove machining, precise electroforming and embossing to produce polydimethylsiloxane (PDMS) molds, lens film elements can be produced via an ultraviolet (UV)-cured molding process that converts microlenses into flexible polyethylene terephthalate films. In this study, the microlenticular lens mold is fabricated by U-groove machining, Ni electroforming and PDMS casting. Then, the PDMS mold with microlenticular lens structure is used in the gas-assisted UV imprint process and the PET film with microlenticular lens array is obtained. The lenticular lens had a radius of curvature and height of 228 and 18 µm, respectively. A 3D confocal laser microscope was used to measure the radius of curvature and the spacing of the metal molds, nickel (Ni) molds, PDMS molds and the finished thin-film products. The geometry of the final microlenticular lens was very close to the design values. All geometric errors were below 5%, the surface roughness reached the optical level (with all Ra values less than 10 nm) and the replication rate was 95%. The results demonstrate that this process can be used to fabricate gapless, lenticular-shaped, high-precision microlens arrays with a unitary curvature.

  20. Kinetic mechanism and fidelity of nick sealing by Escherichia coli NAD+-dependent DNA ligase (LigA).

    PubMed

    Chauleau, Mathieu; Shuman, Stewart

    2016-03-18

    Escherichia coli DNA ligase (EcoLigA) repairs 3'-OH/5'-PO4 nicks in duplex DNA via reaction of LigA with NAD(+) to form a covalent LigA-(lysyl-Nζ)-AMP intermediate (step 1); transfer of AMP to the nick 5'-PO4 to form an AppDNA intermediate (step 2); and attack of the nick 3'-OH on AppDNA to form a 3'-5' phosphodiester (step 3). A distinctive feature of EcoLigA is its stimulation by ammonium ion. Here we used rapid mix-quench methods to analyze the kinetic mechanism of single-turnover nick sealing by EcoLigA-AMP. For substrates with correctly base-paired 3'-OH/5'-PO4 nicks, kstep2 was fast (6.8-27 s(-1)) and similar to kstep3 (8.3-42 s(-1)). Absent ammonium, kstep2 and kstep3 were 48-fold and 16-fold slower, respectively. EcoLigA was exquisitely sensitive to 3'-OH base mispairs and 3' N:abasic lesions, which elicited 1000- to >20000-fold decrements in kstep2. The exception was the non-canonical 3' A:oxoG configuration, which EcoLigA accepted as correctly paired for rapid sealing. These results underscore: (i) how EcoLigA requires proper positioning of the nick 3' nucleoside for catalysis of 5' adenylylation; and (ii) EcoLigA's potential to embed mutations during the repair of oxidative damage. EcoLigA was relatively tolerant of 5'-phosphate base mispairs and 5' N:abasic lesions. PMID:26857547

  1. Magnetometory of AlGaN/GaN heterostructure wafers

    NASA Astrophysics Data System (ADS)

    Tsubaki, K.; Maeda, N.; Saitoh, T.; Kobayashi, N.

    2005-06-01

    AlGaN/GaN heterostructure wafers are becoming a key technology for next generation cellar-phone telecommunication system because of their potential for high-performance microwave applications. Therefore, the electronic properties of a 2DEG in AlGaN/GaN heterostructures have recently been discussed. In this paper, we performed the extraordinary Hall effect measurement and the SQUID magnetometory of AlGaN/GaN heterostructure wafer at low temperature. The AlGaN/GaN heterostructures were grown by low-pressure metal-organic chemical vapour phase epitaxy on (0001) SiC substrate using AlN buffers. The electron mobility and electron concentration at 4.2 K are 9,540cm2/V s and 6.6 × 1012cm-2, respectively. In the extraordinary Hall effect measurement of AlGaN/GaN heterostructures, the hysteresis of Hall resistance appeared below 4.5 K and disappeared above 4.5 K. On the other hand, the hysteresis of magnetometric data obtained by SQUID magnetometory appears near zero magnetic field when the temperature is lower than 4.5 K. At the temperature larger than 4.5 K, the hysteresis of magnetometric data disappears. And the slopes of magnetometric data with respect to magnetic field become lower as obeying Currie-Weiss law and the Curie temperature TC is 4.5 K. Agreement of TC measured by the extraordinary Hall effect and the SQUID magnetometory implies the ferromagnetism at the AlGaN/GaN heterojunction. However, the conformation of the ferromagnetism of AlGaN/GaN heterostructure is still difficult and the detailed physical mechanism is still unclear.

  2. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbracher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-07-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  3. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbrecher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-01-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  4. A universal process development methodology for complete removal of residues from 300mm wafer edge bevel

    NASA Astrophysics Data System (ADS)

    Randall, Mai; Linnane, Michael; Longstaff, Chris; Ueda, Kenichi; Winter, Tom

    2006-03-01

    Many yield limiting, etch blocking defects are attributed to "flake" type contamination from the lithography process. The wafer edge bevel is a prime location for generation of this type of defect. Wafer bevel quality is not readily observed with top down or even most off axis inspection equipment. Not all chemistries are removed with one "universal" cleaning process. IC manufacturers must maximize usable silicon area as well. These requirements have made traditional chemical treatments to clean the wafer edge inadequate for many chemistry types used in 193nm processing. IBM has evaluated a method to create a robust wafer bevel and backside cleaning process. An August Technology AXi TM Series advanced macro inspection tool with E20 TM edge inspection module has been used to check wafer bevel cleanliness. Process impact on the removal of post apply residues has been investigated. The new process used backside solvent rinse nozzles only and cleaned the wafer bevel completely. The use of the topside edge solvent clean nozzles was eliminated. Thickness, wet film defect measurements (wet FM), and pattern wafer defect monitors showed no difference between the new backside rinse edge bead removal process and the process of record. Solvent topside edge bead removal of both bottom anti-reflective coatings and resist materials showed better cut width control and uniformity. We conclude that the topside solvent edge bead removal nozzle can be removed from the process. Backside solvent rinse nozzles can clean the backside of the wafer, the wafer bevel, and can wrap to the front edge of the wafer to provide a uniform edge bead removal cut width that is not sensitive to coater module tolerances. Recommendations are made for changes to the typical preventive maintenance procedures.

  5. Creating a single twin boundary between two CdTe (111) wafers with controlled rotation angle by wafer bonding

    SciTech Connect

    Sun, Ce; Lu, Ning; Wang, Jinguo; Lee, Jihyung; Peng, Xin; Kim, Moon J.; Klie, Robert F.

    2013-12-16

    The single twin boundary with crystallographic orientation relationship (1{sup ¯}1{sup ¯}1{sup ¯})//(111) [01{sup ¯}1]//[011{sup ¯}] was created by wafer bonding. Electron diffraction patterns and high-resolution transmission electron microscopy images demonstrated the well control of the rotation angle between the bonded pair. At the twin boundary, one unit of wurtzite structure was found between two zinc-blende matrices. High-angle annular dark-field scanning transmission electron microscopy images showed Cd- and Te-terminated for the two bonded portions, respectively. The I-V curve across the twin boundary showed increasingly nonlinear behavior, indicating a potential barrier at the bonded twin boundary.

  6. Infrared differential interference contrast microscopy for overlay metrology on 3D-interconnect bonded wafers

    NASA Astrophysics Data System (ADS)

    Ku, Yi-sha; Shyu, Deh-Ming; Lin, Yeou-Sung; Cho, Chia-Hung

    2013-04-01

    Overlay metrology for stacked layers will be playing a key role in bringing 3D IC devices into manufacturing. However, such bonded wafer pairs present a metrology challenge for optical microscopy tools by the opaque nature of silicon. Using infrared microscopy, silicon wafers become transparent to the near-infrared (NIR) wavelengths of the electromagnetic spectrum, enabling metrology at the interface of bonded wafer pairs. Wafers can be bonded face to face (F2F) or face to back (F2B) which the stacking direction is dictated by how the stacks are carried in the process and functionality required. For example, Memory stacks tend to use F2B stacking enables a better managed design. Current commercial tools use single image technique for F2F bonding overlay measurement because depth of focus is sufficient to include both surfaces; and use multiple image techniques for F2B overlay measurement application for the depth of focus is no longer sufficient to include both stacked wafer surfaces. There is a need to specify the Z coordinate or stacking wafer number through the silicon when visiting measurement wafer sites. Two shown images are of the same (X, Y) but separate Z location acquired at focus position of each wafer surface containing overlay marks. Usually the top surface image is bright and clear; however, the bottom surface image is somewhat darker and noisier as an adhesive layer is used in between to bond the silicon wafers. Thus the top and bottom surface images are further processed to achieve similar brightness and noise level before merged for overlay measurement. This paper presents a special overlay measurement technique, using the infrared differential interference contrast (DIC) microscopy technique to measure the F2B wafer bonding overlay by a single shot image. A pair of thinned wafers at 50 and 150 μm thickness is bonded on top of a carrier wafer to evaluate the bonding overlay. It works on the principle of interferometry to gain information about the optical path length of the stacked wafers, to enhance the image contrast of overlay marks features even though they are locating in different Z plane. A two dimensional mirror-symmetric overlay marks for both top and bottom processing wafers is designed and printed in each die in order to know and realize the best achievable wafer to wafer bonding processing. A self-developed analysis algorithms is used to identify the overlay error between the stacking wafers and the interconnect structures. The experimental overlay results after wafer bonding including inter-die and intra-die analysis results will be report in the full paper. Correlation of overlay alignment offset data to electrical yield, provides an early indication of bonded wafer yield.

  7. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates

    PubMed Central

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-01-01

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the “melt-back” effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 μm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude. PMID:26487465

  8. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates

    NASA Astrophysics Data System (ADS)

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-10-01

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the “melt-back” effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 μm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude.

  9. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates.

    PubMed

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-01-01

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the "melt-back" effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 μm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude. PMID:26487465

  10. Evaluation of the Technical Feasibility and Effective Cost of Various Wafer Thicknesses for the Manufacture of Solar Cells

    NASA Technical Reports Server (NTRS)

    1979-01-01

    Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.

  11. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss

    NASA Astrophysics Data System (ADS)

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-05-01

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

  12. A fast in situ approach to estimating wafer warpage profile during thermal processing in microlithography

    NASA Astrophysics Data System (ADS)

    Hu, Ni; Tay, Arthur; Tsai, Kuen-Yu

    2006-08-01

    Wafer warpage can affect device performance, reliability and linewidth control in various processing steps in microelectronics manufacturing. Early detection will minimize cost and processing time. We have previously demonstrated an on-line approach for detecting wafer warpage and the profile of the warped wafer. The proposed approach demonstrates that the profile of the wafer can be computed during thermal processing steps in the lithography sequence. However, the approach is computationally intensive and information is made available at the end of the thermal processing step. Any attempts at real-time correction of the wafer temperature are thus not possible. In this paper, we proposed an in situ approach to detect wafer warpage and its profile midway through the thermal process. Based on first principles thermal modelling, we are able to detect and estimate the profile of a warped wafer from available temperature measurements. The proposed approach can be implemented on conventional thermal processing systems. Experimental results demonstrate the feasibility and repeatability of the approach. A 75% improvement in computational time is achieved with the proposed approach.

  13. Carboxymethyl cellulose wafers containing antimicrobials: a modern drug delivery system for wound infections.

    PubMed

    Ng, Shiow-Fern; Jumaat, Nafisah

    2014-01-23

    Lyophilised wafers have been shown to have potential as a modern dressing for mucosal wound healing. The wafer absorbs wound exudates and transforms into a gel, thus providing a moist environment which is essential for wound healing. The objective of this study was to develop a carboxymethyl cellulose wafer containing antimicrobials to promote wound healing and treat wound infection. The pre-formulation studies began with four polymers, sodium carboxymethyl cellulose (NaCMC), methylcellulose (MC), sodium alginate and xanthan gum, but only NaCMC and MC were chosen for further investigation. The wafers were characterised by physical assessments, solvent loss, microscopic examination, swelling and hydration properties, drug content uniformity, drug release and efficacy of antimicrobials. Three of the antimicrobials, neomycin trisulphate salt hydrate, sulphacetamide sodium and silver nitrate, were selected as model drugs. Among the formulations, NaCMC wafer containing neomycin trisulphate exhibited the most desirable wound dressing characteristics (i.e., flexibility, sponginess, uniform wafer texture, high content drug uniformity) with the highest in vitro drug release and the greatest inhibition against both Gram positive and Gram negative bacteria. In conclusion, we successfully developed a NaCMC lyophilised wafer containing antimicrobials, and this formulation has potential for use in mucosal wounds infected with bacteria. PMID:24076463

  14. Therml & Gravitational Stress in Si Wafers; Lim. on Process Htg & Cool. Rates

    Energy Science and Technology Software Center (ESTSC)

    1997-01-14

    The MacWafer code determines maximum allowable processing temperatures and maximum heating and cooling rates for thermal processing of silicon semiconductor wafers in single and multiple wafer furnaces. The program runs interactively on Macintosh, PC, and workstation computers. Execution time is typically 20 seconds on a Macintosh 68040 processor operating at 33 MHz. Gravitational stresses and displacements are first calculated based on the user''s input of a support system consisting of a ring beneath the wafermore » and/or arbitrarily placed point supports. The maximum operating temperature is then deduced by comparing the calculated gravitational stresses with the temperature-dependent wafer strength. At lower temperatures, the difference between wafer strength and gravitational stress is used to determine the allowable thermal stress, and hence the allowable radial temperature difference across the wafer. Finally, an analytical model of radial heat transfer in a batch furnace yields the maximum heating or cooling rate as a function of the allowable temperature difference based on the user''s inputs of wafer spacing and furnace power. Outputs to the screen include plots of stress components and vertical displacement, as well as tables of maximum stresses and maximum heating and cooling rates as a function of temperature. All inputs and outputs may be directed to user-named files for further processing or graphical display.« less

  15. Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

    NASA Astrophysics Data System (ADS)

    Miki, N.; Spearing, S. M.

    2003-11-01

    Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

  16. Brush Scrub Cleaning after Spraying Ozonized Water on Si Wafer Treated by Chemical Mechanical Polishing

    NASA Astrophysics Data System (ADS)

    Kurokawa, Yoshiaki; Hayashi, Kounosuke; Nishimura, Eriko; Saito, Reiko; Maki, Kunisuke

    2008-09-01

    To clean the surface of 300-mm-diameter silicon wafers treated by chemical mechanical polishing (CMP), the following steps were performed: (1) the wafer surfaces were first terminated with hydrogen using an etching solution of hydrofluoric acid, and (2) the wafers were then spun while ozonized water was sprayed before brush scrub cleaning was performed. The number of particles more than 100 nm in diameter remaining on the wafer decreased linearly with increasing time after spraying ozonized water for approximately 5 s before brush scrub cleaning. The wafers had fewer than 10 particles after spraying ozonized water for approximately 15 s followed by brush scrub cleaning. Such a cleaning effect was not accomplished when the ozonized water was not sprayed. A model of the brush scrub cleaning process is discussed from the view point that an oxide film is first formed on the wafer surface where no particles are adhered, and then grows laterally beneath the particles. The force then applied by the brush scrubber overcomes the adhesion force between the particles and the wafer, which results in their removal when the oxide layer reaches a sufficient thickness. The growth of the oxide film was confirmed by observing the spectra obtained by attenuated total reflectance spectroscopy (ATR) using a Fourier transform infrared spectroscope (FTIR) and by X-ray photoelectron spectroscopy (XPS).

  17. Passive compliant wafer stage for single-step nano-imprint lithography

    NASA Astrophysics Data System (ADS)

    Choi, Kee-Bong; Lee, Jae Jong

    2005-07-01

    Nano-imprint lithography, which has the advantages of simplicity, low cost, high replication fidelity and relatively high throughput, requires surface contact between a template with nano patterns and a wafer that transfers the patterns. This article presents the wafer stage for single-step nano-imprint lithography. The wafer stage has a six degree-of-freedom compliant mechanism for complete contact between the surface of the template and the surface of the wafer. The compliant mechanism consists of an inner mechanism for in-plane motion and an outer mechanism for out-of-plane motion. The inner and outer mechanisms have symmetric flexures, which were machined monolithically, onto each plane to cope with thermal deformation. The wafer stage, which was designed to satisfy stiffness requirements, is analyzed with the aid of a dynamic model for a flexure mechanism and a finite element method. Experiments were conducted on the wafer stage in a nano-imprint machine, and nano patterns with linewidths of 100 and 86nm were transferred successfully. This result verifies that the proposed wafer stage can be used in nano-imprint lithography.

  18. Design of Single-Wafer Furnace and Its Rapid Thermal Processing Applications

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kuribayashi, Hiromitsu; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-11-01

    A resistively heated, vacuum- and atmospheric-pressure-compatible, single-wafer furnace (SWF) system is designed to improve the operational flexibility of conventional furnaces and the productivity of single-wafer rapid thermal processing (RTP) systems. The heat source design and system operation concepts are described. The temperature measurement/control techniques and thermal characteristics of the heat source are described. The heat transfer mechanism between the heat source and Si wafer is discussed. Temperature and process uniformity in SWF were demonstrated in TiSi formation, implant annealing and thin-oxide formation. The defect-generation phenomenon in Si wafers during atmospheric pressure RTP in a SWF system is investigated as a function of temperature, process time, wafer handling method and speed. Highly repeatable slip-free RTP results were achieved in 200-mm-diameter Si wafers processed at 1100°C for 60 s (up to 5 times) through the optimization of the wafer handling method and speed.

  19. Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010

    SciTech Connect

    Lorenz, A.

    2011-06-01

    1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

  20. Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

    NASA Technical Reports Server (NTRS)

    Okojie, Robert S. (Inventor)

    2002-01-01

    A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

  1. Validation of thermodesorption method for analysis of semi-volatile organic compounds adsorbed on wafer surface.

    PubMed

    Hayeck, Nathalie; Gligorovski, Sasho; Poulet, Irène; Wortham, Henri

    2014-05-01

    To prevent the degradation of the device characteristics it is important to detect the organic contaminants adsorbed on the wafers. In this respect, a reliable qualitative and quantitative analytical method for analysis of semi-volatile organic compounds which can adsorb on wafer surfaces is of paramount importance. Here, we present a new analytical method based on Wafer Outgassing System (WOS) coupled to Automated Thermal Desorber-Gas chromatography-Mass spectrometry (ATD-GC-MS) to identify and quantify volatile and semi-volatile organic compounds from 6", 8" and 12" wafers. WOS technique allows the desorption of organic compounds from one side of the wafers. This method was tested on three important airborne contaminants in cleanroom i.e. tris-(2-chloroethyl) phosphate (TCEP), tris-(2-chloroisopropyl) phosphate (TCPP) and diethyl phthalate (DEP). In addition, we validated this method for the analysis and quantification of DEP, TCEP and TCPP and we estimated the backside organic contamination which may contribute to the front side of the contaminated wafers. We are demonstrating that WOS/ATD-GC-MS is a suitable and highly efficient technique for desorption and quantitative analysis of organophosphorous compounds and phthalate ester which could be found on the wafer surface. PMID:24720963

  2. AWV: high-throughput cross-array cross-wafer variation mapping

    NASA Astrophysics Data System (ADS)

    Yeo, Jeong-Ho; Lee, Byoung-Ho; Lee, Tae-Yong; Greenberg, Gadi; Meshulach, Doron; Ravid, Erez; Levi, Shimon; Kan, Kobi; Shabtay, Saar; Cohen, Yehuda; Rotlevi, Ofer

    2008-03-01

    Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision (TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

  3. Mapping of Defects in Large-Area Silicon Carbide Wafers via Photoluminescence and its Correlation with Synchrotron White Beam X-Ray Topography

    SciTech Connect

    Chen, Yi; Balaji, R.; Dudley, Michael; Murthy, Madhu; Maximenko, Serguei I.; Freitas, Jamie A.

    2008-12-12

    Comparative studies of defect microstructure in 4H-SiC wafers have been carried out using photoluminescence (PL) imaging and grazing-incidence Synchrotron White Beam X-ray Topography. Images of low angle grain boundaries on the PL images correlate well with SWBXT observations, and similar correlation can be established for some micropipe images although the latter is complicated by the overall level of distortion and misorientation associated with the low angle grain boundaries and the fact that many of the micropipes are located in or close to the boundaries. This validation indicates that PL imaging may provide a rapid way of imaging such defect structures in large-scale SiC wafers.

  4. Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers Used for PV Cells: Preprint

    SciTech Connect

    Guthrey, H.; Gorman, B.; Al-Jassim, M.

    2011-07-01

    As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay (uPCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

  5. Long persistent near infrared luminescence nanoprobes LiGa5O8:Cr3+-PEG-OCH3 for in vivo imaging

    NASA Astrophysics Data System (ADS)

    Fu, Xiaoyan; Liu, Chunlin; Shi, Junpeng; Man, Huizi; Xu, Jia; Zhang, Hongwu

    2014-09-01

    The Cr3+-doped LiGa5O8 nanoparticles (LGNPs) with long-persistent near-infrared phosphorescence were obtained through a sol-gel approach followed by heat treatment at 800 °C in air. The obtained results reveal that the nanoparticles with an average diameter of 100 nm are well defined and have pure structure of LiGa5O8. After illumination for 3 min using a 254 nm UV lamp, the LGNPs exhibit strong near-infrared peak at ca. 720 nm belonging to tissue transparency window which can last for more than 1 h. Via surface modified with PEG-5000-OCH3, the LGNPs-PEG-OCH3 exhibit excellent biocompatibility and low toxicity. Under in vitro pre-excitation using a 254 nm UV lamp for 3 min, the in vivo distribution of the LGNPs-PEG-OCH3 in the abdomen can be detected in real time for more than 1 h. All the results indicate that the LGNPs-PEG-OCH3 can be used as potential nanoprobes to realize in vivo, real time and long time imaging with high sensitivity.

  6. Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

    NASA Astrophysics Data System (ADS)

    Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

    2015-02-01

    The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

  7. Novel lithography approach using feed-forward mask-based wafer CDU correction increase fab productivity and yield

    NASA Astrophysics Data System (ADS)

    Mangan, Shmoolik; Byers, Erik; Rost, Dan; Garrett, Mike; Carlson, Merri; Hickman, Craig; Finders, Jo; Luehrmann, Paul; Kazinczi, Robert; Minnaert-Janssen, Ingrid; Duray, Frank; Wisse, Baukje; Schoumans, Nicole; Reijnen, Liesbeth; Theeuwes, Thomas; Ben-Yishai, Michael; Ren, Rachel; Gibson, Ryan; Shoval, Lior; Cohen, Yaron; Elblinger, Yair; Englard, Ilan

    2009-03-01

    The extension of ArF lithography through reduced k1, immersion and double patterning techniques makes lithography a difficult challenge. Currently, the concept of simple linear flow from design to functional photo-mask is being replaced by a more complex scheme of feedback and feed-forward loops which have become part of a complex computational lithography scheme. One such novel lithography concept, called "holistic lithography", was recently introduced by ASML, as a scheme that makes the lithography process a highly efficient solution for the scaled down geometries. This approach encourages efficient utilization of computational lithography and the use of feed-forward and feed-back critical dimension (CD) and overlay correction loops. As sub-nanometer feature dimensions are reached for 3x nodes, with k1 reaching the optics limitations, Mask error enhancement factor (MEEF) values grow fast, thus making mask uniformity fingerprint and degradation throughout its life time a significant factor in printed CDU on the wafer. Whereas the consensus is on the need for growing density of intra-field data, traditional critical dimension scanning electron microscope (CDSEM) Feed backward loops to the litho-cell become unsuitable due to the high density CD measurement requirements. Earlier publications proposed implementing the core of the holistic lithography concept by combining two technologies: Applied Material's IntenCDTM and ASML DoseMapper . IntenCD metrology data is streamed in a feedforward fashion through DoseMapper and into the scanner, to create a dose compensation recipe which improves the overall CDU performance. It has been demonstrated that the IntenCD maps can be used to efficiently reduce intra-field printed CDU on printed wafers. In this paper we study the integration concept of IntenCD and DoseMapper in a production environment. We implement the feed-forward concept by feeding IntenCD inspection data into DoseMapper that is connected to ASML's TWSINCANTM XT:1900i scanner. We apply this concept on printed wafers and demonstrate significant reduction in intra-field CDU. This concept can effectively replace the feedback concept using send-ahead wafers and extensive CDSEM measurements. The result is a significant cost saving and fab productivity improvement. By routinely monitoring mask-based CDU, we propose that all photo-induced transmission degradation effects can be compensated through the same mechanism. The result would be longer intervals between cleans, improved mask lifetime, and better end of line device yield.

  8. The removal of deformed submicron particles from silicon wafers by spin rinse and megasonics

    NASA Astrophysics Data System (ADS)

    Zhang, Fan; Busnaina, Ahmed A.; Fury, Michael A.; Wang, Shi-Qing

    2000-02-01

    In order to successfully clean particulate contamination from wafer surfaces, it is necessary to understand the adhesion and deformation between the particles and the substrate in contact. The adhesion and removal mechanisms of deformed submicron particles have not been addressed in many previous studies. Submicron polystyrene latex particles (0.1-0.5 µm) were deposited on silicon wafers and removed by spin rinse and megasonic cleanings. Particle rolling is identified as the major removal mechanism for the deformed submicron particles from silicon wafers. Megasonics provides larger streaming velocity because of the extremely thin boundary layer resulting in a larger removal force that is capable of achieving complete removal of contamination particles.

  9. Wafer chamber having a gas curtain for extreme-UV lithography

    DOEpatents

    Kanouff, Michael P.; Ray-Chaudhuri, Avijit K.

    2001-01-01

    An EUVL device includes a wafer chamber that is separated from the upstream optics by a barrier having an aperture that is permeable to the inert gas. Maintaining an inert gas curtain in the proximity of a wafer positioned in a chamber of an extreme ultraviolet lithography device can effectively prevent contaminants from reaching the optics in an extreme ultraviolet photolithography device even though solid window filters are not employed between the source of reflected radiation, e.g., the camera, and the wafer. The inert gas removes the contaminants by entrainment.

  10. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sang Min; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Vukkadala, Pradeep; Awasthi, Amartya; Kim, J. H.; Veeraraghavan, Sathish; Choi, DongSub; Huang, Kevin; Dighe, Prasanna; Lee, Cheouljung; Byeon, Jungho; Dey, Soham; Sinha, Jaydeep

    2015-03-01

    Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes - which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.

  11. Development of a fixed abrasive slicing technique (FAST) for reducing the cost of photovoltaic wafers

    SciTech Connect

    Schmid, F. )

    1991-12-01

    This report examines a wafer slicing technique developed by Crystal Systems, Inc. that reduces the cost of photovoltaic wafers. This fixed, abrasive slicing technique (FAST) uses a multiwire bladepack and a diamond-plated wirepack; water is the coolant. FAST is in the prototype production stage and reduces expendable material costs while retaining the advantages of a multiwire slurry technique. The cost analysis revealed that costs can be decreased by making more cuts per bladepack and slicing more wafers per linear inch. Researchers studied the degradation of bladepacks and increased wirepack life. 21 refs.

  12. Nonnegative Matrix Factorization for Binary Data to Extract Elementary Failure Maps from Wafer Test Images

    NASA Astrophysics Data System (ADS)

    Schachtner, Reinhard; Pöppel, Gerhard; Lang, Elmar

    We introduce a probabilistic variant of nonnegative matrix factorization (NMF) applied to binary datasets. Hence we consider binary coded images as a probabilistic superposition of underlying continuous-valued basic patterns. An extension of the well-known NMF procedure to binary-valued datasets is provided to solve the related optimization problem with nonnegativity constraints. We demonstrate the performance of our method by applying it to the detection and characterization of hidden causes for failures during wafer processing. Therefore, we decompose binary coded (pass/fail) wafer test data into underlying elementary failure patterns and study their influence on the quality of single wafers.

  13. Low temperature solder process to join a copper tube to a silicon wafer

    NASA Astrophysics Data System (ADS)

    Versteeg, Christo; Scarpim de Souza, Marcio

    2014-06-01

    With the application for wafer level packages, which could be Complementary Metal-Oxide-Semiconductor (CMOS) based, and which requires a reduced atmosphere, a copper tube connection to a vacuum pump and the package is proposed. The method evaluated uses laser assisted brazing of a solder, to join the copper tube to a silicon wafer. The method was applied to a silicon wafer coated with a metallic interface to bond to the solder. The hermeticity of the joint was tested with a helium leak rate tester and the bonding energy thermal extent was verified with a thin layer of indium that melted wherever the substrate temperature rose above its melting temperature.

  14. SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

    NASA Astrophysics Data System (ADS)

    Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

    2010-05-01

    Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

  15. Shop-floor scheduling of semiconductor-wafer manufacturing

    SciTech Connect

    Resende, M.G.D.C.

    1987-01-01

    Semiconductor wafer fabrication is perhaps the most complex manufacturing process found today, with a wide range of complex issues related to production planning and scheduling. Computer-integrated manufacturing (CIM) systems make is possible, in theory, to use global factory state information for factory control decisions. The possibility of making decisions on an expanded information set raises two of the research questions treated in this dissertation: How should global information be summarized and used for decisions and how much improvement can one expect as a result, compared with decisions based on local information This research investigates lot release control and dispatching policies for shop-level scheduling of a semiconductor fab. The author introduces a closed-loop scheduling policy, called Starvation Avoidance, that makes use of global factory state information and that in simulation experiments compares favorably to traditional scheduling policies (that use local and global information) with respect to the tradeoff between throughput and queueing time. The virtual inventory of the bottleneck resource is defined to be the work content at the bottleneck of all jobs either at the bottleneck station or expected to arrive at the bottleneck within a given lead time.

  16. Detection and Characterization of Precipitates in Annealed Cz Silicon Wafers

    NASA Astrophysics Data System (ADS)

    Veve, Caroline; Gay, Nathalie; Stemmer, Michäel; Martinuzzi, Santo

    1995-09-01

    A Scanning InfraRed Microscope (S.I.R.M.), a Light Beam Induced Current mapping (L.B.I.C.), a Fourier Transform infrared spectroscope (F.T.I.R.), and a minority carrier diffusion length measurements tool have been associated to detect precipitates in annealed Czochralski (Cz) silicon wafers and to evaluate their recombination strength with or without metallic contamination. The influence of a phosphorus diffusion was also investigated. After two step annealings (750 °C - 16 h and 900 °C - 24 h or 96 h) S.I.R.M. reveals the presence of precipitates, while L.B.I.C. maps display a ring-like distribution of recombination centers and minority carrier diffusion length (L_n) collapses to 2 μm. Copper contamination does not significantly modify the preceding observations when precipitates are formed. Phosphorus diffusion near the surface shrink the precipitates revealed by M.I.R.B. but do not suppress the ring-like patterns in the L.B.I.C. maps and L_n increases slightly. These results suggest that the recombination strength of precipitates does not depend on a metallic decoration but more probably on interfacial states between the precipitates and the host crystal or on associated extended defects.

  17. OPC hotspot identification challenges: ORC vs. PWQ on wafer

    NASA Astrophysics Data System (ADS)

    Poock, Andre; McGowan, Sarah; Weisbuch, Francois; Schnasse, Guido; Ghaskadvi, Rajesh

    2008-10-01

    The identification of OPC induced litho hotspots within the product design is essential and a must to make sure that a new OPC model is working correctly and does no harm to the design and future product. Several techniques and methods for OPC verification and identification of hotspots are known and long adopted within the field. An optical rule check done by the simulation software after OPC is one way of identifying hotspots within the design of the whole chip. This is typically done by using a DRC-type width or space check on simulation contours (nominal exposure contour or process window contours). However, the pass/fail nature of this check at a single CD value requires good calibration of the simulation model to avoid false positives and ease of disposition at tapeout. Another method is the process window qualification method which uses the defect inspection of a focus exposure matrix wafer for OPC hotspot identification. However, this can not be done prior to ordering a mask. Based on a 45nm line space layer OPC qualification, we will demonstrate how optical rule check and process window qualification is performed, what the individual results will be, and how they can be used for OPC quality evaluation. The general goal of this work is to show the capabilities of optical rule check and process window qualification, compare both methods, and detect limitations.

  18. Fast wafer-level detection and control of interconnect reliability

    NASA Astrophysics Data System (ADS)

    Foley, Sean; Molyneaux, James; Mathewson, Alan

    2000-08-01

    Many of the technological advances in the semiconductor industry have led to dramatic increases in device density and performance in conjunction with enhanced circuit reliability. As reliability is improved, the time taken to characterize particular failure modes with traditional test methods is getting substantially longer. Furthermore, semiconductor customers expect low product cost and fast time-to-market. The limits of traditional reliability testing philosophies are being reached and new approaches need to be investigated to enable the next generation of highly reliable products to be tested. This is especially true in the area of IC interconnect, where significant challenges are predicted for the next decade. A number of fast, wafer level test methods exist for interconnect reliability evaluation. The relative abilities of four such methods to detect the quality and reliability of IC interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are bench-marked against conventional package level Median Time to Failure results. The Isothermal test method combine with SWEAT-type test structures is shown to be the most suitable combination for defect detection and interconnect reliability control over very short test times.

  19. Adhesive disbond detection using piezoelectric wafer active sensors

    NASA Astrophysics Data System (ADS)

    Roth, William; Giurgiutiu, Victor

    2015-04-01

    The aerospace industry continues to increase the use of adhesives for structural bonding due to the increased joint efficiency (reduced weight), even distribution of the load path and decreases in stress concentrations. However, the limited techniques for verifying the strength of adhesive bonds has reduced its use on primary structures and requires an intensive inspection schedule. This paper discusses a potential structural health monitoring (SHM) technique for the detection of disbonds through the in situ inspection of adhesive joints. This is achieved through the use of piezoelectric wafer active sensors (PWAS), thin unobtrusive sensors which are permanently bonded to the aircraft structure. The detection method discussed in this study is electromechanical impedance spectroscopy (EMIS), a local vibration method. This method detects disbonds from the change in the mechanical impedance of the structure surrounding the disbond. This paper will discuss how predictive modeling can provide valuable insight into the inspection method, and provide better results than empirical methods alone. The inspection scheme was evaluated using the finite element method, and the results were verified experimentally using a large aluminum test article, and included both pristine and disbond coupons.

  20. Evolution of grain structures during directional solidification of silicon wafers

    NASA Astrophysics Data System (ADS)

    Lin, H. K.; Wu, M. C.; Chen, C. C.; Lan, C. W.

    2016-04-01

    The evolution of grain structures, especially the types of grain boundaries (GBs), during directional solidification is crucial to the electrical properties of multicrystalline silicon used for solar cells. To study this, the electric molten zone crystallization (EMZC) of silicon wafers at different drift speeds from 2 to 6 mm/min was considered. It was found that <111> orientation was dominant at the lower drift velocity, while <112> orientation at the higher drift velocity. Most of the non-∑GBs tended to align with the thermal gradient, but some tilted toward the unfavorable grains having higher interfacial energies. On the other hand, the tilted ∑3GBs tended to decrease during grain competition, except at the higher speed, where the twin nucleation became frequent. The competition of grains separated by ∑GBs could be viewed as the interactions of GBs that two coherent ∑3n GBs turned into one ∑3nGB following certain relations as reported before. On the other hand, when ∑ GBs met non-∑ GBs, the non-∑ GBs remained which explained the decrease of ∑ GBs at the lower speed.

  1. Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology

    NASA Astrophysics Data System (ADS)

    Kitada, Hideki; Maeda, Nobuhide; Fujimoto, Koji; Mizushima, Yoriko; Nakata, Yoshihiro; Nakamura, Tomoji; Ohba, Takayuki

    2011-05-01

    Diffusion behavior of Cu in Cu through-silicon-vias (TSVs) fabricated using low-temperature plasma enhanced chemical vapor deposition (LT-PECVD) has been evaluated. Silicon oxynitride (SiON) barrier films were formed by LT-PECVD at 150 °C. Cu diffusion rate was found to increase with decreasing film density. The critical density and thickness for prevention of Cu diffusion into Si substrate have been estimated. In case of a film with density >60% of the bulk value and/or thickness >100 nm, no change of electrical resistance for stacked wafers containing TSVs was observed after 1000 cycles of thermal stress. According to above results, SiON film formed at 150 °C can be used for the TSV process without any degradation of electrical characteristics and reliability, enabling a reduction in total process temperature in the wafer-on-wafer technology.

  2. Disbond detection with piezoelectric wafer active sensors in RC structures strengthened with FRP composite overlays

    NASA Astrophysics Data System (ADS)

    Giurgiutiu, Victor; Harries, Kent; Petrou, Michael; Bost, Joel; Quattlebaum, Josh B.

    2003-12-01

    The capability of embedded piezoelectric wafer active sensors (PWAS) to perform in-situ nondestructive evaluation (NDE) for structural health monitoring (SHM) of reinforced concrete (RC) structures strengthened with fiber reinforced polymer (FRP) composite overlays is explored. First, the disbond detection method were developed on coupon specimens consisting of concrete blocks covered with an FRP composite layer. It was found that the presence of a disbond crack drastically changes the electromechanical (E/M) impedance spectrum measured at the PWAS terminals. The spectral changes depend on the distance between the PWAS and the crack tip. Second, large scale experiments were conducted on a RC beam strengthened with carbon fiber reinforced polymer (CFRP) composite overlay. The beam was subject to an accelerated fatigue load regime in a three-point bending configuration up to a total of 807,415 cycles. During these fatigue tests, the CFRP overlay experienced disbonding beginning at about 500,000 cycles. The PWAS were able to detect the disbonding before it could be reliably seen by visual inspection. Good correlation between the PWAS readings and the position and extent of disbond damage was observed. These preliminary results demonstrate the potential of PWAS technology for SHM of RC structures strengthened with FRP composite overlays.

  3. High uniform growth of 4-inch GaN wafer via flow field optimization by HVPE

    NASA Astrophysics Data System (ADS)

    Cheng, Yutian; Liu, Peng; Wu, Jiejun; Xiang, Yong; Chen, Xinjuan; Ji, Cheng; Yu, Tongjun; Zhang, Guoyi

    2016-07-01

    The uniformity of flow field inner the reactor plays a crucial role for hydride vapor phase epitaxy (HVPE) crystal growth and its more important for large scale substrate. A new nozzle structure was designed by adding a push and dilution (PD) gas pipe in the center of gas channels for a 4-inch HVPE (PD-HVPE) system. Experimental results showed that the thickness inhomogeneity of 46 μm 4-inch GaN layer could reach ±1.8% by optimizing PD gas, greatly improved from ±14% grown with conventional nozzle. The simulations of the internal flow field were consistent with our experiment, and the enhancement in uniformity should be attributed to the redistribution of GaCl and NH3 upon the wafer induced by PD pipe. The full width at half maximum (FWHM) of X-ray diffraction rocking curves for the 4-inch GaN film were about 224 and 200 arcsec for (002) and (102) reflection. The dislocation density of as-grown GaN was about 6.4×107 cm-2.

  4. Hydrogen-induced program threshold voltage degradation analysis in SONOS wafer

    NASA Astrophysics Data System (ADS)

    Lin, Qing; Zhao, Crystal; Sheng, Nan

    2016-02-01

    This paper studies the hydrogen-induced program state threshold voltage degradation in SONOS wafers, which ultimately impacts wafer sort test yield. During wafer sort step, all individual integrated circuits noted as die are tested for functional defects by applying special test patterns to them. The proportion between the passing die (good die) and the non-passing die (bad die) is sort yield. The different N2/H2 ratio in IMD1 alloy process yields differently at flash checkerboard test. And the SIMS curves were also obtained to depict the distribution profile of H+ in SONOS ONO stack structure. It is found that, the H+ accumulated in the interface between the Tunnel oxide and Si layer, contributes the charge loss in Oxynitride layer, which leads to the program threshold voltage degradation and even fall below lower specification limit, and then impacts the sort yield of SONOS wafers.

  5. Diffusion length and resistivity distribution characteristics of silicon wafer by photoluminescence

    SciTech Connect

    Baek, Dohyun; Lee, Jaehyeong; Choi, Byoungdeog

    2014-10-15

    Highlights: • Analytical photoluminescence efficiency calculation and PL intensity ratio method are developed. • Wafer resistivity and diffusion length characteristics are investigated by PL intensity ratio. • PL intensity is well correlated with resistivity, diffusion length or defect density on wafer measurement. - Abstract: Photoluminescence is a convenient, contactless method to characterize semiconductors. Its use for room-temperature silicon characterization has only recently been implemented. We have developed the PL efficiency theory as a function of substrate doping densities, bulk trap density, photon flux density, and reflectance and compared it with experimental data initially for bulk Si wafers. New developed PL intensity ratio method is able to predict the silicon wafer properties, such as doping densities, minority carrier diffusion length and bulk trap density.

  6. Trans-wafer removal of metallization using a nanosecond Tm:fiber laser

    NASA Astrophysics Data System (ADS)

    Mingareev, Ilya; Berger, Sascha; Tetz, Thomas; Abdulfattah, Ali; Sincore, Alex M.; Shah, Lawrence; Richardson, Martin C.

    2015-03-01

    By utilizing photon energies considerably smaller than the semiconductors' energy band gap, space-selective modifications can be induced in semiconductors beyond the laser-incident surface. Previously, we demonstrated that back surface modifications could be produced in 500-600 ?m thin Si and GaAs wafers independently without affecting the front surface. In this paper, we present our latest studies on trans-wafer processing of semiconductors using a self-developed nanosecond-pulsed thulium fiber laser operating at the wavelength 2 ?m. A qualitative study of underlying physical mechanisms responsible for material modification was performed. We explored experimental conditions that will enable many potential applications such as trans-wafer metallization removal for PV cell edge isolation, selective surface annealing and wafer scribing. These processes were investigated by studying the influence of process parameters on the resulting surface morphology, microstructure and electric properties.

  7. Effects of wafer noise on the detection of 20-nm defects using optical volumetric inspection

    NASA Astrophysics Data System (ADS)

    Barnes, Bryan M.; Goasmat, Francois; Sohn, Martin Y.; Zhou, Hui; Vladár, András E.; Silver, Richard M.

    2015-01-01

    Patterning imperfections in semiconductor device fabrication may either be noncritical [e.g., line edge roughness (LER)] or critical, such as defects that impact manufacturing yield. As the sizes of the pitches and linewidths decrease in lithography, detection of the optical scattering from killer defects may be obscured by the scattering from other variations, called wafer noise. Understanding and separating these optical signals are critical to reduce false positives and overlooked defects. The effects of wafer noise on defect detection are assessed using volumetric processing on both measurements and simulations with the SEMATECH 9-nm gate intentional defect array. Increases in LER in simulation lead to decreases in signal-to-noise ratios due to wafer noise. Measurement procedures illustrate the potential uses in manufacturing while illustrating challenges to be overcome for full implementation. Highly geometry-dependent, the ratio of wafer noise to defect signal should continue to be evaluated for new process architectures and production nodes.

  8. Multi-wire slurry wafering demonstrations. [slicing silicon ingots for solar arrays

    NASA Technical Reports Server (NTRS)

    Chen, C. P.

    1978-01-01

    Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

  9. A study of defects on EUV mask using blank inspection, patterned mask inspection, and wafer inspection

    SciTech Connect

    Huh, S.; Ren, L.; Chan, D.; Wurm, S.; Goldberg, K. A.; Mochi, I.; Nakajima, T.; Kishimoto, M.; Ahn, B.; Kang, I.; Park, J.-O.; Cho, K.; Han, S.-I.; Laursen, T.

    2010-03-12

    The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing. yet link data is available for understanding native defects on real masks. In this paper, a full-field EUV mask is fabricated to investigate the printability of various defects on the mask. The printability of defects and identification of their source from mask fabrication to handling were studied using wafer inspection. The printable blank defect density excluding particles and patterns is 0.63 cm{sup 2}. Mask inspection is shown to have better sensitivity than wafer inspection. The sensitivity of wafer inspection must be improved using through-focus analysis and a different wafer stack.

  10. On-wafer vector network analyzer measurements in the 220-325 Ghz frequency band

    NASA Technical Reports Server (NTRS)

    Fung, King Man Andy; Dawson, D.; Samoska, L.; Lee, K.; Oleson, C.; Boll, G.

    2006-01-01

    We report on a full two-port on-wafer vector network analyzer test set for the 220-325 GHz (WR3) frequency band. The test set utilizes Oleson Microwave Labs frequency extenders with the Agilent 8510C network analyzer. Two port on-wafer measurements are made with GGB Industries coplanar waveguide (CPW) probes. With this test set we have measured the WR3 band S-parameters of amplifiers on-wafer, and the characteristics of the CPW wafer probes. Results for a three stage InP HEMT amplifier show 10 dB gain at 235 GHz [1], and that of a single stage amplifier, 2.9 dB gain at 231 GHz. The approximate upper limit of loss per CPW probe range from 3.0 to 4.8 dB across the WR3 frequency band.

  11. Intra-wafer CDU characterization to determine process and focus contributions based on scatterometry metrology

    NASA Astrophysics Data System (ADS)

    Dusa, Mircea; Moerman, Richard; Singh, Bhanwar; Friedberg, Paul; Hoobler, Ray; Zavecs, Terry

    2004-04-01

    Current advanced lithography processes are based on a Critical Dimension (CD) budget of 10nm or less with errors caused by exposure tool, wafer substrate, wafer process, and reticle. As such, allowable CD variation across wafer becomes an important parameter to understand, control and minimize. Three sources of errors have an effect on CD Uniformity (CDU) budget, run-to-run (R2R), wafer-to-wafer (W2W) and intra-wafer. While R2R and W2W components are characterized and compensation conrol techniques were developed to minimize their contribution the intra-wafer component is more or less ignored with the consequence that its sources of errors have not been characterized and no compensation technique is available. In this paper, we propose an approach to analyze intra-wafer CD sources of variations identifying the non-random CDU behavior and connect this with disturbances caused by processing errors described by their wafer spatial coordinates. We defined a process error as disturbance and its effect as a feature response. We study the impact of modeling spatial distribution of a feature response as calculated by diffractive optical CD metrology (scatterometry) and relate it to a programmed process disturbance. Process disturbances are classified in terms of time characteristics that define their spatial distribution. We demonstrated feature response to a disturbance behavior as statistical values as well as spatial profile. We identified that CD response is not sufficient to determine the sources of process disturbance and accordingly added responses from other features, which add to detection of CDU sources of error. The added respsonses came from scatterometry principle based on model difinition of a litho patter described by its shape with characteristic features: bottom CD, resist thickness, sidewall angle and bottom antireflective layer thickness. Our results show that process errors with continuous intra-wafer variation, such as PEB and BARC thickness have larger effects on CDU compared to process errors with discrete intra-wafer behavior, such as dose and defocus. Correlation between multiple feature responses to process disturbance was characterized as spatial covariance between CD to resist thickness and CD to SWA. Spatial feature covariance enhances capability to infer sources of process disturbance from metrology data.

  12. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.

    2008-11-18

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  13. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.

    2011-07-12

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  14. Particulate performance for robotics-based wafer handling ion implant system

    NASA Astrophysics Data System (ADS)

    Nasser-Ghodsi, M.; McCarron, D.; Foley, M.; Holden, S.; Veinbachs, D.; Mooney, S.; Ward, S.

    1991-04-01

    The continued reduction in design geometries has lead to manufacturing sensitivity to particulate generation in each manufacturing step. The NV20A developed an adaptive wafer handling system for in-air wafer motion. This paper will discuss the development criteria and particulate measurement results from experiments with the system. Origins of particulates are identified as each step in the implant process is independently measured.

  15. Fast integral rigorous modeling applied to wafer topography effect prediction on 2x nm bulk technologies

    NASA Astrophysics Data System (ADS)

    Michel, J.-C.; Le Denmat, J.-C.; Tishchenko, A.; Jourlin, Y.

    2014-03-01

    Reflection by wafer topography and underlying layers during optical lithography can cause unwanted overexposure in the resist [1]. In most cases, the use of bottom anti reflective coating limits this effect. However, this solution is not always suitable because of process complexity, cost and cycle time penalty, as for ionic implantation lithography process in 28nm bulk technology. As a consequence, computational lithography solutions are currently under development to simulate and correct wafer topographical effects [2], [3]. For ionic implantation source drain (SD) photolithography step, wafer topography influences resulting in implant pattern variation are various: active silicon areas, Poly patterns, Shallow Trench Isolation (STI) and topographical transitions between these areas. In 28nm bulk SD process step, the large number of wafer stack variations involved in implant pattern modulation implies a complex modeling of optical proximity effects. Furthermore, those topography effects are expected to increase with wafer stack complexity through technology node downscaling evolution. In this context, rigorous simulation can bring significant value for wafer topography modeling evolution in R and D process development environment. Unfortunately, classical rigorous simulation engines are rapidly run time and memory limited with pattern complexity for multiple under layer wafer topography simulation. A presentation of a fast rigorous Maxwell's equation solving algorithm integrated into a photolithography proximity effects simulation flow is detailed in this paper. Accuracy, run time and memory consumption of this fast rigorous modeling engine is presented through the simulation of wafer topography effects during ionic implantation SD lithography step in 28nm bulk technology. Also, run time and memory consumption comparison is shown between presented fast rigorous modeling and classical rigorous RCWA method through simulation of design of interest. Finally, integration opportunity of such fast rigorous modeling method into OPC flow is discussed in this paper.

  16. An Evaluation Process of Polymeric Adhesive Wafer Bonding for Vertical System Integration

    NASA Astrophysics Data System (ADS)

    Kwon, Yongchai; Seok, Jongwon

    2005-06-01

    Bonding of wafers using dielectric polymer thin films as bonding adhesives is one of key approaches to monolithic vertical system integration. As the first step for the integration, properties of the polymer desired for baseline adhesive material are studied, followed by the evaluations on bonding results obtained from wafer pairs bonded between a silicon and a glass wafers. Four sequential evaluation procedures are performed after bonding; (1) optical inspection is made to measure the fraction of bonded area, (2) a razor blade test is taken to separate the bonded wafers, (3) a four-point bending method is used to measure bonding strength quantitatively, (4) FTIR is applied to analyze changes in chemical structure. Bonding integrity is evaluated how the intentionally created debond areas of the bonded wafers are changed after the subsequent thinning processes. To date, benzocyclobutene (BCB), FlareTM, and methylsilsesquioxane (MSSQ) and Parylene-N have been considered as bonding adhesives. Among these polymer materials, BCB and FlareTM are selected as initial adhesive materials after a screening process through optical inspection. Wafer pairs bonded using FlareTM have higher bond strength than those using BCB. However, the bond strength of wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k inter-level dielectrics (ILD) (a back end interconnect structure), indicating almost 100% of bonded area reproducibly. In the light of such evaluation results, BCB has been eventually selected as a baseline adhesive material for the wafer bonding prcess for vertical system integration.

  17. Influence of the Viscoelastic Properties of the Polyimide Dielectric Coating on the Wafer Warpage

    NASA Astrophysics Data System (ADS)

    Zhu, Chunsheng; Ning, Wenguo; Xu, Gaowei; Luo, Le

    2014-09-01

    Polyimide is widely used as the dielectric material in wafer level packaging. One potential problem with its application is the warpage and stress generated in the curing process. This paper investigated the material properties of polyimide and its influence on the wafer warpage. The viscoelastic properties of polyimide film were measured and a mathematical model of the properties was developed. Finite element analysis of the wafer warpage was performed and this indicates that the viscoelastic material model gave the best prediction. To better understand the causation of the warpage, curvature evolution of the polyimide-coated silicon wafer during its curing process was measured by a multi-beam optical sensor system. It was found that the warpage was mainly induced by the coefficient of thermal expansion mismatch and that the cure shrinkage of polyimide had little effect. Additionally, the effect of the cooling rate on the wafer warpage was also studied. Both simulation and experiment results showed that a slower cooling rate in the temperature range around the glass transition temperature ( T g) of polyimide will help to reduce the final wafer warpage.

  18. Determining lifetime in silicon blocks and wafers with accurate expressions for carrier density

    NASA Astrophysics Data System (ADS)

    Bowden, Stuart; Sinton, Ronald A.

    2007-12-01

    In recent years, many studies of silicon minority-carrier lifetime have been performed with quasi-steady-state photoconductance measurements. The method has been used to characterize the defect levels, surface passivation, and trapping effects in wafers by using absolutely calibrated data for minority-carrier lifetime versus minority-carrier injection level. This paper generalizes the quasi-steady-state photoconductance technique for use in thick wafers or blocks of silicon where the diffusion length or light absorption depth is much less than the sample thickness. The photogeneration and carrier diffusion profiles are calculated for special cases of interest. The measured effective lifetimes can then be used to estimate the bulk lifetime in the material, and report this lifetime at an appropriate average minority-carrier density for the measurement conditions. In this way, the results and measurement methodologies previously developed for use on wafers can be applied to single- or multi-crystalline silicon ingots or thick wafers. In thick silicon samples, long-wavelength weakly absorbed light can be used to reduce the effects of surface recombination on the measurement giving important advantages compared to the case of measuring unpassivated wafers. The generalization presented here offers advantages for accurately determining the bulk lifetime of silicon material prior to sawing into wafers and without requiring surface passivation.

  19. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    PubMed Central

    Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

    2013-01-01

    Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

  20. Time-varying wetting behavior on copper wafer treated by wet-etching

    NASA Astrophysics Data System (ADS)

    Tu, Sheng-Hung; Wu, Chuan-Chang; Wu, Hsing-Chen; Cheng, Shao-Liang; Sheng, Yu-Jane; Tsao, Heng-Kwong

    2015-06-01

    The wet cleaning process in semiconductor fabrication often involves the immersion of the copper wafer into etching solutions and thereby its surface properties are significantly altered. The wetting behavior of a copper film deposited on silicon wafer is investigated after a short dip in various etching solutions. The etchants include glacial acetic acid and dilute solutions of nitric acid, hydrofluoric acid, and tetramethylammonium hydroxide. It was found that in most cases a thin oxide layer still remains on the surface of as-received Cu wafers when they are subject to etching treatments. However, a pure Cu wafer can be obtained by the glacial acetic acid treatment and its water contact angle (CA) is about 45°. As the pure Cu wafer is placed in the ambient condition, the oxide thickness grows rapidly to the range of 10-20 Å within 3 h and the CA on the hydrophilic surface also rises. In the vacuum, it is surprising to find that the CA and surface roughness of the pure Cu wafer can grow significantly. These interesting results may be attributed to the rearrangement of surface Cu atoms to reduce the surface free energy.

  1. Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

    SciTech Connect

    Johnston, S.; Yan, F.; Dorn, D.; Zaunbrecher, K.; Al-Jassim, M.; Sidelkheir, O.; Ounadjela, K.

    2012-06-01

    Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect band images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.

  2. Nonuniformities of electrical resistivity in undoped 6H-SiC wafers

    SciTech Connect

    Li, Q.; Polyakov, A.Y.; Skowronski, M.; Sanchez, E.K.; Loboda, M.J.; Fanton, M.A.; Bogart, T.; Gamble, R.D.

    2005-06-01

    Chemical elemental analysis, temperature-dependent Hall measurements, deep-level transient spectroscopy, and contactless resistivity mapping were performed on undoped semi-insulating (SI) and lightly nitrogen-doped conducting 6H-SiC crystals grown by physical vapor transport (PVT). Resistivity maps of commercial semi-insulating SiC wafers revealed resistivity variations across the wafers between one and two orders of magnitude. Two major types of variations were identified. First is the U-shape distribution with low resistivity in the center and high in the periphery of the wafer. The second type had an inverted U-shape distribution. Secondary-ion-mass spectrometry measurements of the distribution of nitrogen concentration along the growth axis and across the wafers sliced from different locations of lightly nitrogen-doped 6H-SiC boules were conducted. The measured nitrogen concentration gradually decreased along the growth direction and from the center to the periphery of the wafers. This change gives rise to the U-like distribution of resistivity in wafers of undoped SI-SiC. The concentrations of deep electron traps exhibited similar dependence. Compensation of nitrogen donors by these traps can result in the inverted U-like distribution of resistivity. Possible reasons for the observed nonuniformities include formation of a (0001) facet in PVT growth coupled with orientation-dependent nitrogen incorporation, systematic changes of the gas phase composition, and increase of the deposition temperature during boule growth.

  3. NXE:3100 full wafer imaging performance and budget verification

    NASA Astrophysics Data System (ADS)

    van Setten, Eelco; van Ingen Schenau, Koen; O'Mahony, Mark; Hollink, Thijs; Wittebrood, Friso; Davydova, Natalia; Eurlings, Mark; Feenstra, Kees; Finders, Jo; Dusa, Mircea; Young, Stuart

    2012-02-01

    With the introduction of the NXE:3100 NA=0.25 exposure system a big step has been made to get EUV lithography ready for High Volume Manufacturing. Over the last year, 6 exposure systems have been shipped to various customers around the world, active in Logic, DRAM, MPU and Flash memory, covering all major segments in the semi-conductor industry. The integration and qualification of these systems have provided a great learning, identifying the benefits of EUV over ArF immersion and the critical parameters of the exposure tool and how to operate it. In this paper we will focus specifically on the imaging performance of the NXE:3100 EUV scanner. Having been operational for more than a year a wide range of features were evaluated for lithographic performance across the field and across wafer. CD results of 32nm contact holes, 27nm isolated and dense lines, 27nm two-bar, 22nm dense L/S with Dipole, as well as several device features will be discussed and benchmarked against the current ArF immersion performance. A budget verification will be presented showing CD and contrast budgets for a selection of lithographic features. The contribution of the resist process and the mask will be discussed as well. The litho performance optimization will be highlighted with the 27nm twobar and isolated lines features that are sensitive to the illuminator pupil shape and projection lens aberrations. We will estimate the amount of resist induced contrast loss for 27 and 22nm L/S based on measurements of Exposure Latitude and the contributors from the exposure system. We will further present on the impact of variations in the mask blank and patterned mask on imaging, with several new contributors to take into account compared to traditional transmission masks. Finally, the combined results will be projected to the NXE:3300 NA=0.33 exposure system to give an outlook for its imaging performance capabilities.

  4. Modeling of hydrophilic wafer bonding by molecular dynamics simulations

    SciTech Connect

    Litton, David A.; Garofalini, Stephen H.

    2001-06-01

    The role of moisture in hydrophilic wafer bonding was modeled using molecular dynamics computer simulations of interface formation between amorphous silica surfaces. Three different surface treatments were used in order to determine the effect of moisture on the formation of siloxane (Si{endash}O{endash}Si) bridges across the interface at two temperatures. The three surface conditions that were studied were: (a) wet interfaces containing 1 monolayer of water adsorbed at the interface (based on the room temperature bulk density of water), (b) hydroxylated interfaces with concentrations of 3{endash}5 silanols/nm2 on each surface and no excess water molecules initially in the system, and (c) pristine interfaces that had only Si and O and no water or H present. The surfaces were slowly brought together and siloxane bond formation was monitored. In the pristine interfaces, siloxane bridges formed across the interface by the coalescence of various defect species in each surface. A bimodal distribution of siloxane bond angles formed during the first 2.5 Aa of approach after the first siloxane bond was formed. These bond angles were much lower than and higher than the bulk average, indicating the formation of less stable bonds. The hydroxylated (with no excess water) and wet surfaces showed a more uniform distribution of siloxane bond angles, with no highly reactive small bond angles forming. The presence of water molecules enhanced H-bond formation across the interface, but trapped water molecules inhibited formation of the strong siloxane bridges across the interface. In real systems, high temperatures are required to remove this trapped moisture. {copyright} 2001 American Institute of Physics.

  5. Detection and characterization of trace element contamination on silicon wafers

    SciTech Connect

    Singh, Andy; Baur, Katharina; Brennan, Sean; Pianetta, Piero; Homma, Takayuki; Kubo, Nobuhiro

    2003-01-24

    Increasing the speed and complexity of semiconductor integrated circuits requires advanced processes that put extreme constraints on the level of metal contamination allowed on the surfaces of silicon wafers. Such contamination degrades the performance of the ultrathin SiO2 gate dielectrics that form the heart of the individual transistors. Ultimately, reliability and yield are reduced to levels that must be improved before new processes can be put into production. It should be noted that much of this metal contamination occurs during the wet chemical etching and rinsing steps required for the manufacture of integrated circuits and industry is actively developing new processes that have already brought the metal contamination to levels beyond the measurement capabilities of conventional analytical techniques. The measurement of these extremely low contamination levels has required the use of synchrotron radiation total reflection x-ray fluorescence (SR-TXRF) where sensitivities 100 times better than conventional techniques have been achieved. This has resulted in minimum detection limits for transition metals of 8x107 atoms/cm2. SR-TXRF studies of the amount of metal contamination deposited on a silicon surface as a function of pH and oxygen content of the etching solutions have provided insights into the mechanisms of metal deposition from solutions containing trace amounts of metals ranging from parts per trillion to parts per billion. Furthermore, by using XANES to understand the chemical state of the metal atoms after deposition, it has been possible to develop chemical models for the deposition processes. Examples will be provided for copper deposition from ultra pure water and acidic solutions.

  6. LIGA FOR LOBSTER?

    SciTech Connect

    Peele, A.G.; Irving, T.H.

    2000-09-01

    The prospect of making a lobster-eye telescope is drawing closer with recent developments in the manufacture of microchannel-plate optics. This would lead to an x-ray all-sky monitor with vastly improved sensitivity and resolution over existing and other planned instruments. We consider a new approach, using deep etch x-ray lithography, to making a lobster-eye lens that offers certain advantages even over microchannel-plate technology.

  7. High aspect ratio nano-fabrication of photonic crystal structures on glass wafers using chrome as hard mask.

    PubMed

    Hossain, Md Nazmul; Justice, John; Lovera, Pierre; McCarthy, Brendan; O'Riordan, Alan; Corbett, Brian

    2014-09-01

    Wafer-scale nano-fabrication of silicon nitride (Si x N y ) photonic crystal (PhC) structures on glass (quartz) substrates is demonstrated using a thin (30 nm) chromium (Cr) layer as the hard mask for transferring the electron beam lithography (EBL) defined resist patterns. The use of the thin Cr layer not only solves the charging effect during the EBL on the insulating substrate, but also facilitates high aspect ratio PhCs by acting as a hard mask while deep etching into the Si x N y . A very high aspect ratio of 10:1 on a 60 nm wide grating structure has been achieved while preserving the quality of the flat top of the narrow lines. The presented nano-fabrication method provides PhC structures necessary for a high quality optical response. Finally, we fabricated a refractive index based PhC sensor which shows a sensitivity of 185 nm per RIU. PMID:25116111

  8. FTIR analysis of PZT damage during wafer level transfer of thermo-piezoelectric SI3N4 cantilevers on the CMOS-wafer for nano data storage applications

    NASA Astrophysics Data System (ADS)

    Kim, Young-sik; Hyeok Jin, Won; Ahn, Sung Hoon; Sunyong Lee, Caroline

    2007-12-01

    Degradation of lead zirconate titanate (PZT) during wafer level bonding of thermo-piezoelectric cantilevers with a CMOS-wafer was investigated. It was found that the polyimide film which serves as a height adjustment during wafer level bonding between cantilevers and the CMOS-wafer caused significant damage in the PZT sensor when polyimide was coated entirely on the PZT capacitor followed by heating to 300 °C for the bonding process. Fourier transform infrared spectroscopy (FTIR) was used to analyze the reaction product that caused PZT capacitor damage. Three different types of samples were analyzed using FTIR: a sample with coated polyimide only, a sample with a PZT capacitor with no polyimide exposed and a sample with a PZT capacitor where the polyimide has been coated, heated and then removed. NH2 or NH3+ peaks from the sample with the polyimide exposed PZT capacitor were found and these peaks were not detected on the sample with the PZT capacitor or on the polyimide coated sample only. These hydrogen ions contained in the NH2 or NH3 stretch during heating can lead to hydrogen atmosphere annealing which can attack PZT significantly. FTIR analysis therefore confirmed that polyimide reacted with the PZT capacitor to damage its piezoelectric properties.

  9. Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers

    NASA Astrophysics Data System (ADS)

    Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

    2009-03-01

    As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

  10. Clean Transfer of Wafer-Scale Graphene via Liquid Phase Removal of Polycyclic Aromatic Hydrocarbons.

    PubMed

    Kim, Hyun Ho; Kang, Boseok; Suk, Ji Won; Li, Nannan; Kim, Kwang S; Ruoff, Rodney S; Lee, Wi Hyoung; Cho, Kilwon

    2015-05-26

    Pentacene (C22H14), a polycyclic aromatic hydrocarbon, was used as both supporting and sacrificing layers for the clean and doping-free graphene transfer. After successful transfer of graphene to a target substrate, the pentacene layer was physically removed from the graphene surface by using intercalating organic solvent. This solvent-mediated removal of pentacene from graphene surface was investigated by both theoretical calculation and experimental studies with various solvents. The uses of pentacene and appropriate intercalation solvent enabled graphene transfer without forming a residue from the supporting layer. Such residues tend to cause charged impurity scattering and unintentional graphene doping effects. As a result, this clean graphene exhibited extremely homogeneous surface potential profiles over a large area. A field-effect transistor fabricated using this graphene displayed a high hole (electron) mobility of 8050 cm(2)/V·s (9940 cm(2)/V·s) with a nearly zero Dirac point voltage. PMID:25809112

  11. Efficient optimization of high vacuum chemical vapor deposition of niobium oxide on full wafer scale

    NASA Astrophysics Data System (ADS)

    Dabirian, A.; Kuzminykh, Y.; Harada, S.; Parsons, C.; Sandu, S. C.; Wagner, E.; Benvenuti, G.; Rushworth, S.; Muralt, P.; Hoffmann, P.

    2010-02-01

    A systematic study of niobium oxide deposition using niobium tetraethoxy-dimethyl-amino-ethoxide (Nb(OEt)4(dmae)) precursor is presented. The deposition process was conducted in a high-vacuum chemical vapor deposition machine with precursor flux gradient capability. An efficient optimization of the deposition process was achieved and both mass-transport- and chemical-reaction-limited regimes were identified.

  12. Wafer-scale growth of large arrays of perovskite microplate crystals for functional electronics and optoelectronics

    PubMed Central

    Wang, Gongming; Li, Dehui; Cheng, Hung-Chieh; Li, Yongjia; Chen, Chih-Yen; Yin, Anxiang; Zhao, Zipeng; Lin, Zhaoyang; Wu, Hao; He, Qiyuan; Ding, Mengning; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

    2015-01-01

    Methylammonium lead iodide perovskite has attracted intensive interest for its diverse optoelectronic applications. However, most studies to date have been limited to bulk thin films that are difficult to implement for integrated device arrays because of their incompatibility with typical lithography processes. We report the first patterned growth of regular arrays of perovskite microplate crystals for functional electronics and optoelectronics. We show that large arrays of lead iodide microplates can be grown from an aqueous solution through a seeded growth process and can be further intercalated with methylammonium iodide to produce perovskite crystals. Structural and optical characterizations demonstrate that the resulting materials display excellent crystalline quality and optical properties. We further show that perovskite crystals can be selectively grown on prepatterned electrode arrays to create independently addressable photodetector arrays and functional field effect transistors. The ability to grow perovskite microplates and to precisely place them at specific locations offers a new material platform for the fundamental investigation of the electronic and optical properties of perovskite materials and opens a pathway for integrated electronic and optoelectronic systems. PMID:26601297

  13. Heteroepitaxial growth of wafer scale highly oriented graphene using inductively coupled plasma chemical vapor deposition

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Xu, Hai; Li, Linjun; Yang, Yang; Fu, Qiang; Bao, Xinhe; Loh, Kian Ping

    2016-06-01

    The chemical vapor deposition (CVD) of graphene on Cu has attracted much attention because of its industrial scalability. Herein, we report inductively coupled plasma-assisted CVD of epitaxially grown graphene on (111)-textured Cu film alloyed with a small amount of Ni, where large area high quality graphene film can be grown in less than 5 min at 800 °C, thus affording industrial scalability. The epitaxially grown graphene films on (111)-textured Cu contain grains which are predominantly aligned with the Cu lattice and about 10% of 30°-rotated grains (anti-grains). Such graphene films are exclusively monolayer and possess good electrical conductivity, high carrier mobility, and room temperature quantum Hall effect. Magnetoresistance measurements reveal that the reduction of the grain sizes from 150 nm to 50 nm produce increasing Anderson localization and the appearance of a transport gap. Owing to the presence of grain boundaries in these anti-grains, epitaxially grown graphene films possess n-type characteristics and exhibit ultra-high sensitivity to adsorbates.

  14. Room-temperature wafer scale bonding using smoothed Au seal ring surfaces for hermetic sealing

    NASA Astrophysics Data System (ADS)

    Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki

    2016-01-01

    We evaluated room-temperature bonding characteristics of electroplated Au surfaces smoothed by the lift-off and imprint methods. As a result, we found that smoothed surfaces enable strong bonding; on the other hand, electroplated rough surfaces result in very weak bonding. In transmission electron microscopy observations, no delamination was observed at the bonding interface bonded at room temperature using a smooth surface prepared by the lift-off method. Moreover, the hermeticity of the bonding interface prepared using smoothed surfaces was evaluated using diaphragm structures. As a result, we confirmed that good hermetic sealing was achieved using the electroplated Au surface smoothed by the lift-off method.

  15. P/N InP solar cells on Ge wafers

    NASA Technical Reports Server (NTRS)

    Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

    1994-01-01

    Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented indicating InP/Ge has more power output than GaAs/Ge cells at fluences in excess of this value.

  16. Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule

    SciTech Connect

    Emanuel Sachs Tonio Buonassisi

    2013-01-16

    The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the wafer. In addition, it was found to be suitable for growing very large crystals. The equipment used was simple and inexpensive to operate. Reasonable solar cells were fabricated on re-crystallized material.

  17. Enhanced broadband near-infrared luminescence in transparent silicate glass ceramics containing Yb3+ ions and Ni2+-doped LiGa5O8 nanocrystals

    NASA Astrophysics Data System (ADS)

    Wu, Botao; Ruan, Jian; Ren, Jinjun; Chen, Danping; Zhu, Congshan; Zhou, Shifeng; Qiu, Jianrong

    2008-01-01

    Spectral properties of Yb3+/Ni2+ codoped transparent silicate glass ceramics containing LiGa5O8 nanocrystals were investigated. The near-infrared emission intensity of Ni2+ was largely increased with Yb3+ codoping due to Yb3+→Ni2+ energy transfer. The qualitative calculation of the energy transfer constant Cs-a and rate Ps-a showed that the Yb3+→Ni2+ energy transfer was much greater than in the opposite direction. Yb3+/Ni2+ codoped glass ceramics with 0.75mol% Yb2O3 exhibited a near-infrared emission with full width at half maximum of 290nm and fluorescent lifetime of 920μs. The glass ceramics are promising for broadband optical amplification.

  18. Design and fabrication of a 1-DOF drive mode and 2-DOF sense mode micro-gyroscope using SU-8 based UV-LIGA process

    NASA Astrophysics Data System (ADS)

    Verma, Payal; Juneja, Sucheta; Savelyev, Dmitry A.; Khonina, Svetlana N.; Gopal, Ram

    2016-04-01

    This paper presents design and fabrication of a 1-DOF (degree-of-freedom) drive mode and 2-DOF sense mode micro-gyroscope. It is an inherently robust structure and offers a high sense frequency bandwidth. The proposed design utilizes resonance of the1-DOF drive mode oscillator and employs dynamic amplification concept in sense modes to increase the sensitivity while maintaining robustness. The 2-DOF in the sense direction renders the device immune to process imperfections and environmental effects. The design is simulated using FEA software (CoventorWare®). The device is designed considering process compatibility with SU-8 based UV-LIGA process, which is an economical fabrication technique. The complete fabrication process is presented along with SEM images of the fabricated device. The device has 9 µm thick Nickel as the key structural layer with an overall reduced key structure size of 2.2 mm by 2.1 mm.

  19. Meso-scale machining capabilities and issues

    SciTech Connect

    BENAVIDES,GILBERT L.; ADAMS,DAVID P.; YANG,PIN

    2000-05-15

    Meso-scale manufacturing processes are bridging the gap between silicon-based MEMS processes and conventional miniature machining. These processes can fabricate two and three-dimensional parts having micron size features in traditional materials such as stainless steels, rare earth magnets, ceramics, and glass. Meso-scale processes that are currently available include, focused ion beam sputtering, micro-milling, micro-turning, excimer laser ablation, femto-second laser ablation, and micro electro discharge machining. These meso-scale processes employ subtractive machining technologies (i.e., material removal), unlike LIGA, which is an additive meso-scale process. Meso-scale processes have different material capabilities and machining performance specifications. Machining performance specifications of interest include minimum feature size, feature tolerance, feature location accuracy, surface finish, and material removal rate. Sandia National Laboratories is developing meso-scale electro-mechanical components, which require meso-scale parts that move relative to one another. The meso-scale parts fabricated by subtractive meso-scale manufacturing processes have unique tribology issues because of the variety of materials and the surface conditions produced by the different meso-scale manufacturing processes.

  20. Stress diagnostics and crack detection in full-size silicon wafers using resonance ultrasonic vibrations

    NASA Astrophysics Data System (ADS)

    Byelyayev, Anton

    Non-destructive monitoring of residual elastic stress in silicon wafers is a matter of strong concern for modern photovoltaic industry. The excess stress can generate cracks within the crystalline structure, which further may lead to wafer breakage. Cracks diagnostics and reduction in multicrystalline silicon, for example, are ones of the most important issues in photovoltaics now. The industry is intent to improve the yield of solar cells fabrication. There is a number of techniques to measure residual stress in semiconductor materials today. They include Raman spectroscopy, X-ray diffraction and infrared polariscopy. None of these methods are applicable for in-line diagnostics of residual elastic stress in silicon wafers for solar cells. Moreover, the method has to be fast enough to fit in solar cell sequential production line. In photovoltaics, fast in-line quality control has to be performed within two seconds per wafer to match the throughput of the production lines. During this Ph.D. research we developed the resonance ultrasonic vibration (RUV) approach to diagnose residual stress non-destructively in full-size multicrystalline silicon wafers used in solar cell manufacturing. This method is based on excitation of longitudinal resonance ultrasonic vibrations in the material using an external piezoelectric transducer combined with high sensitive ultrasonic probe and data acquisition of the frequency response to make the method suitable for in-line diagnostics during wafer and cell manufacturing. Theoretical and experimental analyses of the vibration mode in single crystal and multicrystalline silicon wafers were used to provide a benchmark reference analysis and validation of the approach. Importantly, we observed a clear trend of increasing resonance frequency of the longitudinal vibration mode with higher average in-plane stress obtained with scanning infrared polariscopy. Using the same experimental approach we assessed a fast crack detection and length determination in full-size solar-grade crystalline silicon wafers. We demonstrated on a set of identical non-processed crystalline Si wafers with introduced periphery cracks that the crack shifts a selected RUV peak to a lower frequency and increases the resonance peak's half-width. Both characteristics are gradually increased with the length of the crack. This was confirmed also theoretically by performing finite element analysis of longitudinal vibrations of wafers with cracks. The frequency shift and peak half-width were found to be reliable indicators of the crack appearance in silicon wafers suitable for mechanical quality control and fast wafer's inspection. Resonance ultrasonic vibrations metrology is a promising technique to provide quality control in full-size silicon wafers. This approach has the potential to be further developed into a diagnostic tool to address the needs of silicon wafer manufacturers, both in the microelectronic and the solar cell industries.

  1. Design, fabrication and measurement of a novel 140 GHz folded waveguide based on SU-8 UV-LIGA technology

    NASA Astrophysics Data System (ADS)

    Xie, Fuqiang; Ding, Guifu; Zhao, Xiaolin; Cheng, Ping

    2015-08-01

    In an RF MEMS field, a folded waveguide is the core structure of a traveling wave tube as a slow-wave structure. 140 GHz is an important atmospheric working window. In this paper, the dispersion property and interaction impedance of a novel 140 GHz folded waveguide were analyzed and simulated using CST Microwave Studio. The beam-wave interaction in the folded waveguide was also simulated, using CST Particle Studio. The output power gain of the folded waveguide reached 24.5 dB at 140 GHz when the emission voltage was 12.7 kV and the emission current was 0.15 A. The simulation process provided structure parameters for further micromachining. Furthermore, to analyze the effect of structure fabrication errors, CST was used to simulate the dispersion and interaction impedance by adding tolerance to some important structure parameters. Finally, multi-step SU-8 UV-LIGA technology was adopted for micromachining the folded waveguide. To ensure adhesion between the SU-8 photoresist and substrate, a thin TiO2 film was formed on the surface of the Ti substrate. In the end, test results showed that the reflection coefficient S 11 and transmission coefficient S 21 were near -28.1 dB and -1.2 dB respectively. Moreover, the output power gain was close to 23 dB at 140 GHz. Good accordance between the simulation and experimental results indicated a reasonable design and high precision of microfabrication by SU-8 UV-LIGA technology.

  2. Structural Damage Detection with Piezoelectric Wafer Active Sensors

    NASA Astrophysics Data System (ADS)

    Giurgiutiu, Victor

    2011-07-01

    Piezoelectric wafer active sensors (PWAS) are lightweight and inexpensive enablers for a large class of damage detection and structural health monitoring (SHM) applications. This paper starts with a brief review of PWAS physical principles and basic modelling and continues by considering the various ways in which PWAS can be used for damage detection: (a) embedded guided-wave ultrasonics, i.e., pitch-catch, pulse-echo, phased arrays, thickness mode; (b) high-frequency modal sensing, i.e., the electro-mechanical (E/M) impedance method; (c) passive detection, i.e., acoustic emission and impact detection. An example of crack-like damage detection and localization with PWAS phased arrays on a small metallic plate is given. The modelling of PWAS detection of disbond damage in adhesive joints is achieved with the analytical transfer matrix method (TMM). The analytical methods offer the advantage of fast computation which enables parameter studies and carpet plots. A parametric study of the effect of crack size and PWAS location on disbond detection is presented. The power and energy transduction between PWAS and structure is studied analytically with a wave propagation method. Special attention is given to the mechatronics modeling of the complete transduction cycle from electrical excitation into ultrasonic acoustic waves by the piezoelectric effect, the transfer through the structure, and finally reverse piezoelectric transduction to generate the received electric signal. It is found that the combination of PWAS size and wave frequency/wavelength play an important role in identifying transduction maxima and minima that could be exploited to achieve an optimum power-efficient design. The multi-physics finite element method (MP-FEM), which permits fine discretization of damaged regions and complicated structural geometries, is used to study the generation of guided waves in a plate from an electrically excited transmitter PWAS and the capture of these waves as electric signals at a receiver PWAS. Wave diffraction from a hole damage is illustrated through time-frame snapshots. The paper ends with conclusions and suggestions for further work.

  3. Rinsing of wafers after wet processing: Simulation and experiments

    NASA Astrophysics Data System (ADS)

    Chiang, Chieh-Chun

    In semiconductor manufacturing, a large amount (50 billion gallons for US semiconductor fabrication plants in 2006) of ultrapure water (UPW) is used to rinse wafers after wet chemical processing to remove ionic contaminants on surfaces. Of great concern are the contaminants left in narrow (tens of nm), high-aspect-ratio (5:1 to 20:1) features (trenches, vias, and contact holes). The International Technology Roadmap for Semiconductors (ITRS) stipulates that ionic contaminant levels be reduced to below ˜ 10 10 atoms/cm2. Understanding the bottlenecks in the rinsing process would enable conservation of rinse water usage. A comprehensive process model has been developed on the COMSOL platform to predict the dynamics of rinsing of narrow structures on patterned SiO 2 substrates initially cleaned with NH4OH. The model considers the effect of various mass-transport mechanisms, including convection and diffusion/dispersion, which occur simultaneously with various surface phenomena, such as adsorption and desorption of impurities. The influences of charged species in the bulk and on the surface, and their induced electric field that affect both transport and surface interactions, have been addressed. Modeling results show that the efficacy of rinsing is strongly influenced by the rate of desorption of adsorbed contaminants, mass transfer of contaminants from the mouth of the feature to the bulk liquid, and the trench aspect ratio. Detection of the end point of rinsing is another way to conserve water used for rinsing after wet processing. The applicability of electrochemical impedance spectroscopy (EIS) to monitor rinsing of Si processed in HF with and without copper contaminant was explored. In the first study, the effect of the nature of surface state (flat band, depletion, or accumulation) of silicon on rinsing rate was investigated. The experimental results show that the state of silicon could affect rinsing kinetics through modulation of ion adsorption. In the second study, silicon was intentionally contaminated by spiking HF with copper ions, cleaned in dilute HCl and then rinsed, and the entire process was followed by continuous impedance measurements. The measured impedance values at different stages have been correlated to the nature of the silicon surface, as characterized by scanning electron microscope (SEM) and inductively coupled plasma mass spectrometry (ICP-MS) methods.

  4. Radiation, temperature, and vacuum effects on piezoelectric wafer active sensors

    NASA Astrophysics Data System (ADS)

    Giurgiutiu, Victor; Postolache, Cristian; Tudose, Mihai

    2016-03-01

    The effect of radiation, temperature, and vacuum (RTV) on piezoelectric wafer active sensors (PWASs) is discussed. This study is relevant for extending structural health monitoring (SHM) methods to space vehicle applications that are likely to be subjected to harsh environmental conditions such as extreme temperatures (hot and cold), cosmic radiation, and interplanetary vacuums. This study contains both theoretical and experimental investigations with the use of electromechanical impedance spectroscopy (EMIS). In the theoretical part, analytical models of circular PWAS resonators were used to derive analytical expressions for the temperature sensitivities of EMIS resonance and antiresonance behavior. Closed-form expressions for frequency and peak values at resonance and antiresonance were derived as functions of the coefficients of thermal expansion, {α }1, {α }2, {α }3; the Poisson ratio, ν and its sensitivity, \\partial ν /\\partial T; the relative compliance gradient (\\partial {s}11E/\\partial T)/{s}11E; and the Bessel function root, z and its sensitivity, \\partial z/\\partial T. In the experimental part, tests were conducted to subject the PWAS transducers to RTV conditions. In one set of experiments, several RTV exposure, cycles were applied with EMIS signatures recorded at the beginning and after each of the repeated cycles. In another set of experiments, PWAS transducers were subjected to various temperatures and the EMIS signatures were recorded at each temperature after stabilization. The processing of measured EMIS data from the first set of experiments revealed that the resonance and antiresonance frequencies changed by less than 1% due to RTV exposure, whereas the resonance and antiresonance amplitudes changed by around 15%. After processing an individual set of EMIS data from the second set of experiments, it was determined that the relative temperature sensitivity of the antiresonance frequency ({f}{{AR}}/{f}{{AR}}) is approximately 63.1× {10}-6/^\\circ {{C}} and the relative temperature sensitivity of the antiresonance amplitude (ReZ) is approximately 3.31× {10}-3/^\\circ {{C}}. A tentative statistical analysis and comparative plots of the data from sets of PWAS transducers revealed that the trends observed on an individual PWAS are also observed on the entire set of PWAS transducers. The article concludes with a summary, conclusions, and suggestions for further work.

  5. Behavior of piezoelectric wafer active sensor in various media

    NASA Astrophysics Data System (ADS)

    Kamas, Tuncay

    The dissertation addresses structural health monitoring (SHM) techniques using ultrasonic waves generated by piezoelectric wafer active sensors (PWAS) with an emphasis on the development of theoretical models of standing harmonic waves and guided waves. The focal objective of the research is to extend the theoretical study of electro-mechanical coupled PWAS as a resonator/transducer that interacts with standing and traveling waves in various media through electro-mechanical impedance spectroscopy (EMIS) method and guided wave propagation. The analytical models are developed and the coupled field finite element analysis (CF-FEA) models are simulated and verified with experiments. The dissertation is divided into two parts with respect to the developments in EMIS methods and GWP methods. In the first part, analytical and finite element models have been developed for the simulation of PWAS-EMIS in in-plane (longitudinal) and out-of-plane (thickness) mode. Temperature effects on free PWAS-EMIS are also discussed with respect to the in-plane mode. Piezoelectric material degradation on certain electrical and mechanical properties as the temperature increases is simulated by our analytical model for in-plane circular PWAS-EMIS that agrees well with the sets of experiments. Then the thickness mode PWAS-EMIS model was further developed for a PWAS resonator bonded on a plate-like structure. The latter analytical model was to determine the resonance frequencies for the normal mode expansion method through the global matrix method by considering PWAS-substrate and proof mass-PWAS-substrate models. The proof mass concept was adapted to shift the systems resonance frequencies in thickness mode. PWAS in contact with liquid medium on one of its surface has been analytically modeled and simulated the electro-mechanical response of PWAS with various liquids with different material properties such as the density and the viscosity. The second part discusses the guided wave propagation in elastic structures. The feature guided waves in thick structures and in high frequency range are discussed considering weld guided quasi-Rayleigh waves. Furthermore, the weld guided quasi Rayleigh waves and their interaction with damages in thick plates and thick walled pipes are examined by the finite element models and experiments. The dissertation finishes with a summary of contributions followed by conclusions, and suggestions for future work.

  6. Safety and efficacy of carmustine (BCNU) wafers for metastatic brain tumors

    PubMed Central

    Ene, Chibawanye I.; Nerva, John D.; Morton, Ryan P.; Barkley, Ariana S.; Barber, Jason K.; Ko, Andrew L.; Silbergeld, Daniel L.

    2016-01-01

    Background: Carmustine (BCNU) wafers (Gliadel) prolongs local disease control and progression-free survival (PFS) in patients with malignant gliomas. However, in metastatic brain tumors, there is a paucity of evidence in support of its safety and efficacy. The goal of this study was to assess the safety and efficacy of Gliadel wafers in patients with metastatic brain tumors. Methods: We retrospectively reviewed the University of Washington experience with Gliadel wafers for metastatic brain tumors between 2000 and 2015. Results: Gliadel wafers were used in 14 patients with metastatic brain tumors during the period reviewed. There were no postoperative seizures, strokes, or hemorrhages. There was one postoperative wound infection necessitating return to the operating room. The mean time to tumor progression (n = 7) and death (n = 5) after Gliadel wafer implantation was 2.5 and 2.9 years, respectively. Age was the only variable affecting PFS in patients receiving Gliadel wafers. Patients <53 years old (n = 7) had a PFS of 0.52 years, whereas patients >53 years old (n = 7) had a PFS of 4.29 years (P = 0.02). There was no significant difference in PFS in relation to presenting Karnofsky Performance Status (P = 0.26), number of brain metastasis (P = 0.82), tumor volume (P = 0.54), prior surgery (P = 0.57), or prior radiation (P = 0.41). There were no significant differences in the mean survival in relationship to any variable including age. Conclusions: BCNU wafers are a safe and a potentially efficacious adjunct to surgery and radiation for improving local disease control in metastatic brain tumors. Larger studies, however, are needed to examine overall efficacy and tumor specific efficacy. PMID:27217968

  7. Inspection of mechanical and electrical properties of silicon wafers using terahertz tomography and spectroscopy

    NASA Astrophysics Data System (ADS)

    Arnold, Thomas; Muehleisen, Wolfgang; Schicker, Johannes; Hirschl, Christina

    2015-05-01

    Two different THz applications in the semiconductor industry were explored and validated against established reference measurement techniques and simulations. The first application investigated the possibility of measuring mechanical deformation behaviour of silicon wafers. Time-domain THz tomography mapping scans were carried out to measure wafer thickness and flatness, both in the native state and under different external mechanical loads. These measurements were carried out for a variety of wafers, and the ensuing deformation maps used to validate newly developed numerical simulation models for wafer deformation, and vice versa. In the second part of this paper, carrier dynamics of optically injected charges were investigated by THz spectroscopy. THz pump/probe measurements were carried out in transmission and reflection arrangements on silicon wafers illuminated by a metal halide light source. The light source generates free charge carriers in the semiconductor material that affect the transmission and reflection properties of the semiconductor material. The results of the THz measurements are compared to established standard techniques, like microwave-detected photo-conductance decay (MWPCD) or quasi-steady-state photo conductance (QSSPC) measurements. The defective areas identified with the THz measurements are in good agreement with the defective areas identified by the reference methods. A common benefit of time-domain THz measurements is that the wafer thickness, which is an important measure for the interaction volume of the THz radiation with the semiconductor material, can be calculated from the time- domain signals. The results indicate that THz spectroscopy and imaging can be valuable tools for defect analysis and quality control of silicon wafers, especially since the measurement is fully contact-free and can determine mechanical and electrical properties within a single modality.

  8. The role of Gliadel wafers in the treatment of newly diagnosed GBM: a meta-analysis

    PubMed Central

    Xing, Wei-kang; Shao, Chuan; Qi, Zhen-yu; Yang, Chao; Wang, Zhong

    2015-01-01

    Background Standard treatment for high-grade glioma (HGG) includes surgery followed by radiotherapy and/or chemotherapy. Insertion of carmustine wafers into the resection cavity as a treatment for malignant glioma is currently a controversial topic among neurosurgeons. Our meta-analysis focused on whether carmustine wafer treatment could significantly benefit the survival of patients with newly diagnosed glioblastoma multiforme (GBM). Method We searched the PubMed and Web of Science databases without any restrictions on language using the keywords “Gliadel wafers”, “carmustine wafers”, “BCNU wafers”, or “interstitial chemotherapy” in newly diagnosed GBM for the period from January 1990 to March 2015. Randomized controlled trials (RCTs) and cohort studies/clinical trials that compared treatments designed with and without carmustine wafers and which reported overall survival or hazard ratio (HR) or survival curves were included in this study. Moreover, the statistical analysis was conducted by the STATA 12.0 software. Results Six studies including two RCTs and four cohort studies, enrolling a total of 513 patients (223 with and 290 without carmustine wafers), matched the selection criteria. Carmustine wafers showed a strong advantage when pooling all the included studies (HR =0.63, 95% confidence interval (CI) =0.49–0.81; P=0.019). However, the two RCTs did not show a statistical increase in survival in the group with carmustine wafer compared to the group without it (HR =0.51, 95% CI =0.18–1.41; P=0.426), while the cohort studies demonstrated a significant survival increase (HR =0.59, 95% CI =0.44–0.79; P<0.0001). Conclusion Carmustine-impregnated wafers play a significant role in improving survival when used for patients with newly diagnosed GBM. More studies should be designed for newly diagnosed GBM in the future. PMID:26170620

  9. Quantitative Secondary Ion Mass Spectrometry Analysis of Carbon and Fluorine Impurities on Silicon Wafers Stored in Polymer Carrier Cases

    NASA Astrophysics Data System (ADS)

    Yamazaki, Hideyuki; Tamaoki, Makiko; Oohashi, Masaya

    2000-08-01

    We have investigated the carbon and fluoride contaminants on silicon wafers during their storage in quartz-glass boxes equipped with carrier cases made of either polypropylene (PP), polybutylene-terephthalate (PBT), or perfluoroalkoxy polymer (PFA). The adsorbed organic contaminants on the wafer surfaces were identified by time-of-flight secondary-ion mass spectrometry (TOF-SIMS). The concentrations of contaminants on the wafer surface have been measured as a function of wafer storage positions as well as carrier case storage time. For quantitative analyses, secondary-ion mass spectrometry (SIMS) combined with the encapsulation method was employed, and carbon ({12C-}) and fluorine ({19F-}) ions were detected. It has been found that the amount of adsorbed contaminants on the surface of silicon wafers depend on both the wafer storage conditions and the carrier case materials.

  10. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Powell, J. Anthony (Inventor)

    1991-01-01

    This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  11. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

    1992-01-01

    A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  12. Microwave ECR plasma electron flood for low pressure wafer charge neutralization

    NASA Astrophysics Data System (ADS)

    Vanderberg, Bo; Nakatsugawa, Tomoya; Divergilio, William

    2012-11-01

    Modern ion implanters typically use dc arc discharge Plasma Electron Floods (PEFs) to neutralize wafer charge. The arc discharge requires using at least some refractory metal hardware, e.g. a thermionically emitting filament, which can be undesirable in applications where no metallic contamination is critical. rf discharge PEFs have been proposed to mitigate contamination risks but the gas flows required can result in high process chamber pressures. Axcelis has developed a microwave electron cyclotron resonance (ECR) PEF to provide refractory metals contamination-free wafer neutralization with low gas flow requirement. Our PEF uses a custom, reentrant cusp magnet field providing ECR and superior electron confinement. Stable PEF operation with extraction slits sized for 300 mm wafers can be attained at Xe gas flows lower than 0.2 sccm. Electron extraction currents can be as high as 20 mA at absorbed microwave powers < 70 W. On Axcelis' new medium current implanter, plasma generation has proven robust against pressure transients caused by, for example, photoresist outgassing by high power ion beams. Charge monitor and floating potential measurements along the wafer surface corroborate adequate wafer charge neutralization for low energy, high current ion beams.

  13. Automated defect review of the wafer bevel with a defect review scanning electron microscope

    NASA Astrophysics Data System (ADS)

    McGarvey, Steve; Kanezawa, Masakazu

    2009-03-01

    One of the few remaining bastions of non-regulated Integrated Circuit defectivity is the wafer bevel. Recent internal Integrated Circuit Manufacturing studies have suggested that the edge bevel may be responsible for as much as a two to three percent yield loss during a defect excursion on the manufacturing line and a one to two percent yield loss during ongoing wafer manufacturing. A new generation of defect inspection equipment has been introduced to the Research and Development, Integrated Circuit, MEM's and Si wafer manufacturing markets that has imparted the ability for the end equipment user to detect defects located on the bevel of the wafer. The inherent weakness of the current batch of wafer bevel inspection equipment is the lack of automatic discrete defect classification data into multiple, significant classification bins and the lack of discrete elemental analysis data. Root cause analysis is based on minimal discrete defect analysis as a surrogate for a statistically valid sampling of defects from the bevel. This paper provides a study of the methods employed with a Hitachi RS-5500EQEQ Defect Review Scanning Electron Microscope (DRSEM) to automatically capture high resolution/high magnification images and collect elemental analysis on a statistically valid sample of the discrete defects that were located by a bevel inspection system.

  14. New sensing wafer technique for artifact-free transient temperature measurements in PEB processes

    NASA Astrophysics Data System (ADS)

    Sun, Mei H.; Cohen, Barney M.; Quli, Farhat; Renken, Wayne G.

    2003-05-01

    A system for monitoring the transient and steady state temperature profiles during the deep UV (DUV) post exposure bake (PEB) is described. The system, called Accura°C, consists of a sensor wafer, a wireless electronics unit and software on a laptop computer. To monitor temperature platinum resistance temperature detectors (RTDs) are embedded into silicon wafers. A flexible high temperature printed circuit (PC) ribbon cable connects the wireless electronics unit to the wafer. The system robot moves both the sensor wafer and electronics unit through the system. Communication between the electronics unit and a laptop computer is accomplished by a Bluetooth RF link. The RF link enables the laptop computer to analyze the temperature measurements in real time. The rechargeable batteries in the electronics unit allow detailed examination of all process chambers. Further the long operating time and real time data stream provide for bake chamber optimization such as tuning. The sensor integration into the wafer provides accurate, artifact free measurements of the rapid temperature changes during PEB ramps.

  15. Surface Formation of Single Silicon Wafer Polished with Nano-sized Al2O3 Powders

    NASA Astrophysics Data System (ADS)

    Sun, Yu-li; Zuo, Dun-wen; Zhu, Yong-wei; Wang, Min

    2007-12-01

    Ice polishing single silicon wafers with nano-sized Al2O3 abrasives can be known as ice fixed abrasives chemical mechanical polishing (IFA-CMP). TAn abrasive slurry was made of nano-sized Al2O3 particles dispersed in de-ionized water with a surfactant and the slurry was frozen to form an ice polishing pad. Then polishing tests of blanket silicon wafers with the above ice polishing pad were carried out. The morphologies and surface roughness of the polished silicon wafers were observed and examined on an atomic force microscope. The subsurface damage was assessed by means of cross-section transmission electron microscopy. The surface chemical constituents of the polished silicon wafers were characterized using X-ray photoelectron spectroscopy in order to gain insight into the chemical mechanisms in the process. Scratch resistance of the single silicon wafer was measured by nanoscratching using a nanoindenter to explore the mechanical removal mechanism. The results show that a super smooth surface with an average roughness of 0.367 nm is obtained within 1000 nm × 1000 nm and there is a perfect silicon diamond structure without any microcracks in the subsurface. The removal of material is dominated by the coactions of ductile regime machining and chemical corrosion. In the end, a model of material removal of IFA-CMP is built.

  16. Design and fabrication of a wafer-level lens module using UV polymer and glass lenses

    NASA Astrophysics Data System (ADS)

    Choi, Minseog; Lee, Eunsung; Jung, Kyudong; Kim, Woonbae

    2010-08-01

    Wafer-level lens module comprising of a glass lens as well as polymer lenses is developed for 5 mega-pixel mobile phone camera. A few institutes and companies have been tried wafer-level lens modules so far, but all of them are made of only UV curable polymer lenses which have the limitation in resolving power. We designed and fabricated waferlevel lens module which comprises of a glass lens and two UV curable polymer lenses. Glass lenses are molded one by one and reconstructed as an array on a wafer by the specially designed precision alignment technique. Polymer lenses are fabricated by typical replication and UV curing process. Optical evaluation is carried out and it is shown that the quality of the images captured by the fabricated wafer-level lens module is comparable with that of a commercial 5 mega pixel phone camera. It is expected that the hybrid type wafer level lens module (with glass and polymer lenses) is a promising solution for the high resolution and low cost phone camera in the future.

  17. Dissolving oral clonazepam wafers in the acute treatment of prolonged seizures.

    PubMed

    Troester, Matthew M; Hastriter, Eric V; Ng, Yu-Tze

    2010-12-01

    Klonopin (clonazepam; Genentech Inc, South San Francisco, California) oral wafers are benzodiazepines with anticonvulsive and anxiolytic properties. Our institution has been prescribing clonazepam wafers for acute treatment of prolonged seizures for years. Patients' size determined dosing at 0.25, 0.5, 1, or 2 mg wafers. We proceeded to obtain evidence for efficacy. Hospital Institutional Review Board approval was obtained for anonymous patient survey. All children who had been prescribed clonazepam wafers over a 6-year period at our institution were mailed detailed questionnaires. Three hundred eighty-one questionnaires were mailed with 88 replies but only 56 with meaningful data. Average age was 12.1 years. There were 31 males. Efficacy was defined as stopping seizure within 10 minutes, >50% of the time. Thirty-eight of the 56 (68%) patients met this criterion. From these 38 patients, 19 (50%) had seizures stop within 1 minute. Overall results were comparable to Diastat (rectal diazepam; Valeant Pharmaceuticals International, Aliso Viejo, California). Clonazepam wafers are an effective acute therapy for prolonged seizures. PMID:20413800

  18. Gated Silicon Drift Detector Fabricated from a Low-Cost Silicon Wafer

    PubMed Central

    Matsuura, Hideharu; Sakurai, Shungo; Oda, Yuya; Fukushima, Shinya; Ishikawa, Shohei; Takeshita, Akinobu; Hidaka, Atsuki

    2015-01-01

    Inexpensive high-resolution silicon (Si) X-ray detectors are required for on-site surveys of traces of hazardous elements in food and soil by measuring the energies and counts of X-ray fluorescence photons radially emitted from these elements. Gated silicon drift detectors (GSDDs) are much cheaper to fabricate than commercial silicon drift detectors (SDDs). However, previous GSDDs were fabricated from 10-kΩ·cm Si wafers, which are more expensive than 2-kΩ·cm Si wafers used in commercial SDDs. To fabricate cheaper portable X-ray fluorescence instruments, we investigate GSDDs formed from 2-kΩ·cm Si wafers. The thicknesses of commercial SDDs are up to 0.5 mm, which can detect photons with energies up to 27 keV, whereas we describe GSDDs that can detect photons with energies of up to 35 keV. We simulate the electric potential distributions in GSDDs with Si thicknesses of 0.5 and 1 mm at a single high reverse bias. GSDDs with one gate pattern using any resistivity Si wafer can work well for changing the reverse bias that is inversely proportional to the resistivity of the Si wafer. PMID:26007742

  19. Characterization of traps in SOI wafers by transconductance characteristics of MOSFETs

    NASA Astrophysics Data System (ADS)

    Hanajiri, Tatsuro; Nakajima, Yoshikata; Tomita, Hideki; Aoto, Kenichi; Toyabe, Toru; Morikawa, Takitaro; Sugano, Takuo

    2003-03-01

    We characterized trap states in bonded SOI wafers and SIMOX wafers. By the analogy of Terman method using high frequency C-V characteristics, we estimated the distribution of density of trap states from DC transconductance of SOI MOSFETs in detail. As a result, we found that SIMOX wafers have accepter-like electron traps near the conduction band edge and donor-like hole traps near the valence band edge in the forbidden band of Si at SOI/BOX interfaces with the density of more than 10E12 (cm-2·eV-1). Our DC transconductance technique is practical to characterize trap states in thin SOI layers and to design ultra thin SOI MOSFETs, because it enables us to characterize energy distributions of trap states at FOX/SOI interface and at SOI/BOX interface of MOSFETs separately without any additional process or any special test structure. We also simulated Id-Vd characteristics of SOI MOSFETs with various carrier lifetimes and measured Id-Vd characteristics of MOSFETs fabricated on bonded SOI wafers and SIMOX wafers with various substrate bias conditions. Consequently we concluded that high-density trap states at SOI/BOX interface are effective to suppress kink effect in SOI MOSFETs. This work was partially supported by the Asahi Glass Foundation.

  20. Silymarin released from sterile wafers restores glucose impaired endothelial cell migration.

    PubMed

    Gadad, Pramod C; Matthews, Kerr H; Knott, Rachel M

    2013-11-30

    Reduced oxygen tension combined with high glucose concentration leads to chronic wounds in diabetic patients. Delayed wound healing is due in part to impaired angiogenesis as a result of reduced endothelial cell migration. Topical applications, in the form of sterile lyophilised wafers hold promise for the treatment of chronic diabetic wounds. In this study wafers containing silymarin were prepared using xanthan gum and sterilised with 25 and 40 kGy gamma radiation. The rheological properties of xanthan gels, before and after lyophilisation, were measured and it was concluded that an increased dose of gamma rays (40 kGy) increased the viscosity coefficient and yield stress of silymarin wafers. HPLC analysis indicated that 89-90% of silymarin was retained in the wafers after irradiation. Dermal microvascular cell migration studies in the presence of high glucose and reduced oxygen tension levels, using novel radial migration and wound healing assays developed 'in house', were also undertaken. Silymarin, when formulated as a lyophilised wafer, successfully retained its ability to overcome the high glucose induced reduction in endothelial cell migration. PMID:24055598