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1

CCD wafer scale integration  

Microsoft Academic Search

Wafer scale CCD photodetector arrays of 26 million pixels or more are being fabricated on a limited production basis today. This paper provides an introduction to CCD wafer scale integration with an emphasis on common wafer scale CCD design architectures, applications and fabrication processes. Examples of wafer scale CCD products are reviewed, and a triple poly, double metal wafer scale

Paul P. Suni

1995-01-01

2

The influence of wafer elasticity on acoustic waves during LIGA development.  

SciTech Connect

During acoustically stimulated LIGA development, a wafer receives sound waves from both sides at a wide variety of incidence angles that vary in time depending on the orientation of the wafer relative to the multiple transducers that are typically actuated in a periodic sequence. It is important to understand the influence of these variables on the transmission of energy through the wafer as well as the induced motion of the wafer itself because these processes impact the induced acoustic streaming of the fluid within features, the mechanism presently thought responsible for enhanced development of LIGA features. In the present work, the impact of wafer elasticity on LIGA development is investigated. Transmission waves, wafer bending waves, and the related concepts such as critical bending frequency, mechanical impedance, coincidence, and resonance, are discussed. Supercritical-frequency incident waves induce supersonic bending waves in the wafer. Incident wave energy is channeled into three components, transmitted, reflected and energy deposited to the wafer, depending on the wafer material, thickness and wave incidence angle. Results show at normal incidence for a 1-mm PMMA wafer, about 47% of the wave energy is deposited in the wafer. The wafer gains almost half of the incident energy, a result that agrees well with the Bankert et a1 measurements. In LIGA development, transmitted waves may sometimes produce strong acoustic motion of the developer on the wafer backside, especially for the so-called coincidence case in which almost all incident wave energy transfers to the backside. Wafer bending waves cause wafer oscillation at high frequency, promoting the development process, but features shaking may weaken their attachments to the substrate. Resonance is not likely for the entire wafer, but may occur in short and wide wafer feature columns, which are least likely to break away from the substrate, perhaps resulting in good agitation of the fluid in adjacent feature cavities.

Ting, Aili

2003-12-01

3

An interconnect structure for wafer scale neurocomputers  

Microsoft Academic Search

Silicon technology has two limitations: fabrication defects and limited interconnect. The authors believe the fault-tolerance of neural network models can compensate for fabrication defects. In this paper the authors present the design of an interconnect structure for wafer scale neural network emulation based on CMOS silicon technology that solves the interconnect problem. Thus, massively parallel, wafer scale neurocomputer architectures are

M. Rudnick; D. Hammerstrom

1988-01-01

4

An interconnect structure for wafer scale neurocomputers  

SciTech Connect

Silicon technology has two limitations: fabrication defects and limited interconnect. The authors believe the fault-tolerance of neural network models can compensate for fabrication defects. In this paper the authors present the design of an interconnect structure for wafer scale neural network emulation based on CMOS silicon technology that solves the interconnect problem. Thus, massively parallel, wafer scale neurocomputer architectures are feasible. Their design is part of the Cognitive Architecture Project (CAP) at the Oregon Graduate Center. The CAP architecture is a hybrid using analog computation and multiplexed digital interconnect. The long term goal is to emulate a million nodes, each with a thousand connections, on a single wafer.

Rudnick, M.; Hammerstrom, D.

1988-09-01

5

Integrated optical waveguides in polyimide for wafer scale integration  

Microsoft Academic Search

Optical interconnections promise several key advantages over their electrical counterparts such as large bandwidth and reduced propagation delay. The limitations of electrical interconnections become even more significant for wafer scale integration (WSI), and wafer scale hybrid packaging (WSHP) because of the length of wafer scale interconnections. The authors investigate the possibility of using optically transparent organic dielectrics such as certain

R. Selvaraj; H. T. Lin; J. F. McDonald

1988-01-01

6

Wafer-scale micro-optics fabrication  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

Voelkel, Reinhard

2012-07-01

7

Infrared spectroscopy of wafer-scale graphene.  

PubMed

We report spectroscopy results from the mid- to far-infrared on wafer-scale graphene, grown either epitaxially on silicon carbide or by chemical vapor deposition. The free carrier absorption (Drude peak) is simultaneously obtained with the universal optical conductivity (due to interband transitions) and the wavelength at which Pauli blocking occurs due to band filling. From these, the graphene layer number, doping level, sheet resistivity, carrier mobility, and scattering rate can be inferred. The mid-IR absorption of epitaxial two-layer graphene shows a less pronounced peak at 0.37 ± 0.02 eV compared to that in exfoliated bilayer graphene. In heavily chemically doped single-layer graphene, a record high transmission reduction due to free carriers approaching 40% at 250 ?m (40 cm(-1)) is measured in this atomically thin material, supporting the great potential of graphene in far-infrared and terahertz optoelectronics. PMID:22077967

Yan, Hugen; Xia, Fengnian; Zhu, Wenjuan; Freitag, Marcus; Dimitrakopoulos, Christos; Bol, Ageeth A; Tulevski, George; Avouris, Phaedon

2011-12-27

8

Soft Configurable Wafer Scale Integration: Design, Implementation and Yield Analysis.  

National Technical Information Service (NTIS)

Soft-Configurable Wafer Scale Integration uses software controlled switches to connect up the fault-free parts of a wafer. Compared to hard configuration, the soft configurable approach has the advantages of providing low-cost connections and runtime faul...

M. G. Blatt

1990-01-01

9

IGBT scaling principle toward CMOS compatible wafer processes  

NASA Astrophysics Data System (ADS)

A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

Tanaka, Masahiro; Omura, Ichiro

2013-02-01

10

A wafer scale fail bit analysis system for VLSI memory yield improvement  

Microsoft Academic Search

A wafer-scale fail bit analysis system which outputs an entire wafer fail bit map (FBM) by using a data compaction technique and testing structure is developed. With this system, process defect locations on a wafer can easily be electrically recognized quickly. The processing time of wafer-scale fail bit analysis is reduced to only 2% of that required by the conventional

Y. Sakai; J. Sawada; W. Sakamoto; J. Murato; H. Kawamoto; K. Sakai; K. Nakamuta

1990-01-01

11

Architectural yield analysis of random defects in wafer scale integration  

Microsoft Academic Search

Wafer-scale integration yield concepts are examined. New models of yield are defined and their utility is shown by analyzing the architectural and topological yield of some regular structures. Yield concepts are reviewed, the idea of architectural yield is defined, a mathematical framework for studying such yield is established, and assumptions are discussed. These are applied to architectural goals involving binary

J. Czechowski; E. H. Rogers; M.-J. Chung

1989-01-01

12

Liga developer apparatus system  

DOEpatents

A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

Boehme, Dale R. (Pleasanton, CA); Bankert, Michelle A. (San Francisco, CA); Christenson, Todd R. (Albuquerque, NM)

2003-01-01

13

Wafer scale patterning by soft UV-Nanoimprint Lithography  

Microsoft Academic Search

We present first results on wafer scale patterning within one imprint step only, using Soft UV-Nanoimprint Lithography (UV-NIL). In this process, flexible transparent stamps, fabricated by cast moulding ensure a conformal contact, whereas the usage of low viscosity UV-curable resists allows three-dimensional pattern generation at low pressure (<1 bar) and room temperature. Technical aspects that will be covered in this

U. Plachetka; M. Bender; A. Fuchs; B. Vratzov; T. Glinsner; F. Lindner; H. Kurz

2004-01-01

14

A strategy to prepare wafer scale bismuth compound superstructures.  

PubMed

Epitaxial wafer scale superstructures of bismuth compounds are synthesized. Single crystalline ?-Bi2O3 films are obtained by sputtering amorphous BiOx onto (001)-oriented strontium titanate with a buffer layer, followed by thermal crystallization. This is used as the precursor for the growth of the superstructures. The superstructures of bismuth compounds reveal anisotropic physical properties that are related to their unique morphology. PMID:23754697

Guo, Chuan Fei; Zhang, Jianming; Wang, Meng; Tian, Ye; Liu, Qian

2013-07-22

15

Activities of LIGA and Nano LIGA Technologies at BSRF  

NASA Astrophysics Data System (ADS)

Beijing Synchrotron Radiation Facility (BSRF ) is a partly dedicated synchrotron radiation ( SR) source operated in either parasitic or dedicated mode. LIGA research at BSRF started from 1993 and focused in the first two steps of deep X-ray lithography and electroplating. Scanning exposure chamber of deep X-ray lithography was first built in 1996 on a 3W1 wiggler beamline with very hard X-ray and high X-ray density. We used the system for the research of LIGA deep X-ray lithography for many years, and found that the wiggler beamline does not meet the LIGA deep X-ray lithography for its disadvantages of small and bad uniform X-ray spot of 30mm on the wafer in horizontal and the very high X-ray power density on the wafer which causes the distortion of resist structures by the large heat load on the resist. In 2001 we used a bending magnet beamline (3B1) as deep X-ray lithography instead of wiggler beamline. The 3B1 beamline is divided to be 3B1B as LIGA deep X-ray lithography and 3B1A as nano X-ray lithography. The electroplating is used to make the mechanical parts and mold insert with nickel and copper materials for different applications.

Yi, F.; Zhang, J.; Xie, C.; Wang, D.; Chen, D.

2006-04-01

16

Investigations of Wafer Scale Etching with Xenon Difluoride  

NASA Astrophysics Data System (ADS)

A good and uniform bulk silicon wafer etching method can be applied to the wafer thinning process in MEMS and 3D applications. In this study, the use of a Xenon Difluoride (XeF2) gas-phase etching system, operating at room temperature, has been investigated for bulk silicon wafer thinning. We investigated the Si-wafer surface morphology and profile following each XeF2 etching process cycle. Theoretical results are used to compare with the experimental results as well. A clean wafer surface by proper surface treatments is significant to achieve a uniform surface profile and morphology for XeF2 etching. A proper design of etching cycle with nitrogen ambient during etching is necessary to achieve the fastest and uniform silicon etching rate. The silicon etching rate is reported as a function of etching pressure, nitrogen pressure, and etching duration.

Chen, K. N.; Hoivik, N.; Lin, C. Y.; Young, A.; Ieong, M.; Shahidi, G.

2006-03-01

17

Wafer-scale arrays of epitaxial ferroelectric nanodiscs and nanorings.  

PubMed

Wafer-scale arrays of well-ordered Pb(Zr(0.2)Ti(0.8))O3 nanodiscs and nanorings were fabricated on the entire area (10 mm x 10 mm) of the SrRuO3 bottom electrode on an SrTiO3 single-crystal substrate using the laser interference lithography (LIL) process combined with pulsed laser deposition. The shape and size of the nanostructures were controlled by the amount of PZT deposited through the patterned holes and the temperature of the post-crystallization steps. X-ray diffraction and transmission electron microscopy confirmed that (001)-oriented PZT nanostructures were grown epitaxially on the SrRuO3(001) bottom electrode layer covering the (001)-oriented single-crystal substrate. The domain structures of PZT nano-islands were characterized by reciprocal space mapping using synchrotron x-ray radiation. Ferroelectric properties of each PZT nanostructure were characterized by scanning force microscopy in the piezoresponse mode. PMID:19417246

Han, Hee; Ji, Ran; Park, Yong Jun; Lee, Sung Kyun; Le Rhun, Gwenael; Alexe, Marin; Nielsch, Kornelius; Hesse, Dietrich; Gösele, Ulrich; Baik, Sunggi

2009-01-01

18

Sub100 micron pitch stencil printing for wafer scale bumping  

Microsoft Academic Search

This paper presents recent work on solder paste printing for wafer-level bumping at sub 100mum pitch using Pb-free solder paste with IPC type-6 (15-5mum) particle size distributions. Consistent sized paste deposits have been produced onto wafers at such a pitch using stencil printing. Furthermore, a stencil printing evaluation has determined the impact that the print parameters have on the reproducibility

M. P. Y. Desmulliez; R. W. Kay; E. Abraham; E. de Gourcuff; G. J. Jackson; H. A. H. Steen; C. Liu; P. P. Conway

2005-01-01

19

Fabrication of wafer level chip scale packaging for optoelectronic devices  

Microsoft Academic Search

A novel, simple processing and wafer level packaging method for a 4×4 Resonant Cavity LEDs chip with individual array is under development. Palladium\\/Gold (Pd\\/Au) alloys are used as p-type contacts and as rewiring metallization for optoelectronic devices to improve the fabrication process. By use of these alloys we have found a reduction of a factor of 10 in the resistance

K. L. Jim; G. E. Faulkner; D. C. O'Brien; D. J. Edwards; J. H. Lau

1999-01-01

20

100GHz Transistors from Wafer-Scale Epitaxial Graphene  

Microsoft Academic Search

The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon

Y.-M. Lin; C. Dimitrakopoulos; K. A. Jenkins; D. B. Farmer; H.-Y. Chiu; A. Grill; Ph. Avouris

2010-01-01

21

Wafer-Scale Flexible Surface Acoustic Wave Devices Based on an AlN/Si Structure  

NASA Astrophysics Data System (ADS)

Wafer-scale flexible surface acoustic wave (SAW) devices based on AlN/silicon structure are demonstrated. The final fabricated devices with a 50?m-thickness silicon wafer exhibit good flexibility with a bending curvature radius of 8 mm. Measurements under free and bending conditions are carried out, showing that the central frequency shifts little as the curvature changes. SAW devices with central frequency about 191.9MHz and Q-factor up to 600 are obtained. The flexible technology proposed is directly applied to the wafer silicon substrate in the last step, providing the potential of high performance flexible wafer-scale devices by direct integration with mature CMOS and MEMS technology.

Zhang, Cang-Hai; Yang, Yi; Zhou, Chang-Jian; Shu, Yi; Tian, He; Wang, Zhe; Xue, Qing-Tang; Ren, Tian-Ling

2013-07-01

22

Wafer-Scale Manufacturing of Bulk Shape-Memory-Alloy Microactuators Based on Adhesive Bonding of Titanium–Nickel Sheets to Structured Silicon Wafers  

Microsoft Academic Search

This paper presents a concept for the wafer-scale manufacturing of microactuators based on the adhesive bonding of bulk shape-memory-alloy (SMA) sheets to silicon microstructures. Wafer-scale integration of a cold-state deformation mechanism is provided by the deposition of stressed films onto the SMA sheet. A concept for heating of the SMA by Joule heating through a resistive heater layer is presented.

Stefan Braun; Niklas Sandstrom; GÖran Stemme; Wouter van der Wijngaart

2009-01-01

23

Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging  

Microsoft Academic Search

This paper presents a fabrication method to achieve through-wafer interconnects (TWIs) by etching, filling and grinding in sequence. Based on this method, advanced chip scale packaging (CSP) is performed. Compared to flip-chip technology, silicon based sensors or actuators, especially large scale detector arrays, can be assembled into a system with the sensing surface upwards, and electrical signals can then be

Fan Ji; Seppo Leppävuori; Ismo Luusua; Kimmo Henttinen; Simo Eränen; Iiro Hietanen; Mikko Juntunen

2008-01-01

24

Toward wafer-scale patterning of freestanding intermetallic nanowires  

NASA Astrophysics Data System (ADS)

Individual metal alloy nanowires of constant diameter and high aspect ratio have previously been self-assembled at selected locations on atomic force microscope (AFM) probes by the method reported in Yazdanpanah et al (2005 J. Appl. Phys. 98 073510). This process relies on the room temperature crystallization of an ordered phase of silver-gallium. A parallel version of this method has been implemented in which a substrate, either an array of micromachined tips (similar to tips on AFM probes) or a lithographically patterned planar substrate, is brought into contact with a continuous, nearly planar film of melted gallium. In several runs, freestanding wires are fabricated with diameters of 40-400 nm, lengths of 4-80 µm, growth rates of 80-170 nm s - 1 and, most significantly, with yields of up to 97% in an array of 422 growth sites. These results demonstrate the feasibility of developing a batch manufacturing process for the decoration of wafers of AFM tips and other structures with selectively patterned freestanding nanowires.

Jalilian, Romaneh; Rivera, Jose; Askari, Davood; Arva, Sreenath; Rathfon, Jeremy M.; Cohn, Robert W.; Yazdanpanah, Mehdi M.

2011-07-01

25

Wafer-scale growth of single-crystal monolayer graphene on reusable hydrogen-terminated germanium.  

PubMed

The uniform growth of single-crystal graphene over wafer-scale areas remains a challenge in the commercial-level manufacturability of various electronic, photonic, mechanical, and other devices based on graphene. Here, we describe wafer-scale growth of wrinkle-free single-crystal monolayer graphene on silicon wafer using a hydrogen-terminated germanium buffer layer. The anisotropic twofold symmetry of the germanium (110) surface allowed unidirectional alignment of multiple seeds, which were merged to uniform single-crystal graphene with predefined orientation. Furthermore, the weak interaction between graphene and underlying hydrogen-terminated germanium surface enabled the facile etch-free dry transfer of graphene and the recycling of the germanium substrate for continual graphene growth. PMID:24700471

Lee, Jae-Hyun; Lee, Eun Kyung; Joo, Won-Jae; Jang, Yamujin; Kim, Byung-Sung; Lim, Jae Young; Choi, Soon-Hyung; Ahn, Sung Joon; Ahn, Joung Real; Park, Min-Ho; Yang, Cheol-Woong; Choi, Byoung Lyong; Hwang, Sung-Woo; Whang, Dongmok

2014-04-18

26

DynAMITe: a wafer scale sensor for biomedical applications  

NASA Astrophysics Data System (ADS)

In many biomedical imaging applications Flat Panel Imagers (FPIs) are currently the most common option. However, FPIs possess several key drawbacks such as large pixels, high noise, low frame rates, and excessive image artefacts. Recently Active Pixel Sensors (APS) have gained popularity overcoming such issues and are now scalable up to wafer size by appropriate reticule stitching. Detectors for biomedical imaging applications require high spatial resolution, low noise and high dynamic range. These figures of merit are related to pixel size and as the pixel size is fixed at the time of the design, spatial resolution, noise and dynamic range cannot be further optimized. The authors report on a new rad-hard monolithic APS, named DynAMITe (Dynamic range Adjustable for Medical Imaging Technology), developed by the UK MI-3 Plus consortium. This large area detector (12.8 cm × 12.8 cm) is based on the use of two different diode geometries within the same pixel array with different size pixels (50 ?m and 100 ?m). Hence the resulting device can possess two inherently different resolutions each with different noise and saturation performance. The small and the large pixel cameras can be reset at different voltages, resulting in different depletion widths. The larger depletion width for the small pixels allows the initial generated photo-charge to be promptly collected, which ensures an intrinsically lower noise and higher spatial resolution. After these pixels reach near saturation, the larger pixels start collecting so offering a higher dynamic range whereas the higher noise floor is not important as at higher signal levels performance is governed by the Poisson noise of the incident radiation beam. The overall architecture and detailed characterization of DynAMITe will be presented in this paper.

Esposito, M.; Anaxagoras, T.; Fant, A.; Wells, K.; Konstantinidis, A.; Osmond, J. P. F.; Evans, P. M.; Speller, R. D.; Allinson, N. M.

2011-12-01

27

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging  

NASA Astrophysics Data System (ADS)

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

2014-07-01

28

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.  

PubMed

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-01

29

Wafer-scale nanoconical frustum array crystalline silicon solar cells: promising candidates for ultrathin device applications.  

PubMed

A high photocurrent of 36.96 mA cm(-2) was achieved for wafer-scaled crystalline Si solar cells with hexagonal nanoconical frustum arrays at the surface. Optical simulations showed that the expected photocurrent of 10 ?m thick nanostructured cells could slightly exceed the Lambertian limit. PMID:25001318

Cho, Yunae; Gwon, Minji; Park, Hyeong-Ho; Kim, Joondong; Kim, Dong-Wook

2014-07-24

30

On the chemo-mechanical polishing for nano-scale surface finish of brittle wafers.  

PubMed

Chemo-mechanical polishing (CMP) has been a common method to produce nano-scale surface finish of brittle wafers. This paper provides a relatively comprehensive review on the CMP of silicon, silicon carbide and sapphire including both patents and papers. The discussion includes the limitations and further research directions of the CMP technology, the material removal mechanisms, and the control and optimization of the CMP for brittle wafers. The paper concluded that the usage of mix- or coated- abrasives may improve the CMP in terms of less subsurface damage and higher material removal rate. PMID:20415661

Wang, Y G; Zhang, L C

2010-06-01

31

Comprehensive investigation of sequential plasma activated Si\\/Si bonded interfaces for nano-integration on the wafer scale  

Microsoft Academic Search

The sequentially plasma activated bonding of silicon wafers has been investigated to facilitate the development of chemical free, room temperature and spontaneous bonding required for nanostructure integration on the wafer scale. The contact angle of the surface and the electrical and nanostructural behavior of the interface have been studied. The contact angle measurements show that the sequentially plasma (reactive ion

M. G. Kibria; F. Zhang; T. H. Lee; M. J. Kim; M. M. R. Howlader

2010-01-01

32

LIGA Micromachining: Infrastructure Establishment  

SciTech Connect

LIGA is a micromachining technology that uses high energy x-rays from a synchrotron to create patterns with small lateral dimensions in a deep, non-conducting polymeric resist. Typical dimensions for LIGA parts are microns to tens of microns in lateral size, and hundreds of microns to millimeters in depth. Once the resist is patterned, metal is electrodeposited in the features to create metal microparts, or to create a metal mold for subsequent replication. The acronym LIGA comes from the German words for lithography, electroforming, and molding, and the technology has been under worldwide development for more than a decade. over the last five years, a full-service capability to produce metal microparts using the LIGA process has been established at Sandia national Laboratories, California. This report describes the accomplishments made during the past two years in infrastructure establishment funded by a Laboratory Directed Research and Development (LDRD) project entitled ''LIGA Micromachining.'' Specific topics include photoresist processing for LIGA mask making, x-ray scanning equipment, plating bath instrumentation, plating uniformity, and software architecture.

Alfredo M. Morales; Barry V. Hess; Dale R. Boehme; Jill M. Hruby; John S. Krafcik; Robert H. Nilson; Stewart K. Griffiths; William D. Bonivert

1999-02-01

33

Self-adaptive phosphor coating technology for wafer-level scale chip packaging  

NASA Astrophysics Data System (ADS)

A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.

Linsong, Zhou; Haibo, Rao; Wei, Wang; Xianlong, Wan; Junyuan, Liao; Xuemei, Wang; Da, Zhou; Qiaolin, Lei

2013-05-01

34

Assembly of LIGA using Electric Fields  

SciTech Connect

The goal of this project was to develop a device that uses electric fields to grasp and possibly levitate LIGA parts. This non-contact form of grasping would solve many of the problems associated with grasping parts that are only a few microns in dimensions. Scaling laws show that for parts this size, electrostatic and electromagnetic forces are dominant over gravitational forces. This is why micro-parts often stick to mechanical tweezers. If these forces can be controlled under feedback control, the parts could be levitated, possibly even rotated in air. In this project, we designed, fabricated, and tested several grippers that use electrostatic and electromagnetic fields to grasp and release metal LIGA parts. The eventual use of this tool will be to assemble metal and non-metal LIGA parts into small electromechanical systems.

FEDDEMA, JOHN T.; WARNE, LARRY K.; JOHNSON, WILLIAM A.; OGDEN, ALLISON J.; ARMOUR, DAVID L.

2002-04-01

35

Wafer-Scale Assembly of Highly Ordered Semiconductor Nanowire Arrays by Contact Printing  

NASA Astrophysics Data System (ADS)

Controlled and uniform assembly of "bottom-up" nanowire (NW) materials with high scalability has been one of the significant bottleneck challenges facing the potential integration of nanowires for both nano and macro electronic circuit applications. Many efforts have focused on tackling this challenge, and while significant progress has been made, still most presented approaches lack either the desired controllability in the positioning of nanowires or the needed uniformity over large scales. Here, we demonstrate wafer-scale assembly of highly ordered, dense, and regular arrays of NWs with high uniformity and reproducibility through a simple contact printing process. We demonstrate contact printing as a versatile strategy for direct transfer and controlled positioning of various NW materials into complex structural configurations on substrates. The assembled NW pitch is shown to be readily modulated through the surface chemical treatment of the receiver substrate, with the highest density approaching ~8 NW/um, ~95% directional alignment and wafer-scale uniformity. Furthermore, we demonstrate that our printing approach enables large-scale integration of NW arrays for various device structures on both Si and plastic substrates, with a controlled semiconductor channel width, and therefore ON current, ranging from a single NW (~10 nm) and up to ~250 um, consisting of a parallel array of over 1,250 NWs.

Fan, Zhiyong; Ho, Johnny C.; Jacobson, Zachery A.; Yerushalmi, Roie; Alley, Robert L.; Razavi, Haleh; Javey, Ali

2008-01-01

36

Transformable functional nanoscale building blocks with wafer-scale silicon nanowires.  

PubMed

Through the fusion of electrostatics and mechanical dynamics, we demonstrate a transformable silicon nanowire (SiNW) field effect transistor (FET) through a wafer-scale top-down approach. By felicitously taking advantage of the proposed electrostatic SiNW-FET with mechanically movable SiNWs, all essential logic gates, including address decoders, can be monolithically integrated into a single device. The unification of various functional devices, such as pn-diodes, FETs, logic gates, and address decoders, can therefore eliminate the complex fabrication issues associated with nanoscale integration. These results represent a step toward the creation of multifunctional and flexible nanoelectronics. PMID:21254772

Choi, Sung-Jin; Ahn, Jae-Hyuk; Han, Jin-Woo; Seol, Myeong-Lok; Moon, Dong-Il; Kim, Sungho; Choi, Yang-Kyu

2011-02-01

37

Wafer-scale assembly of highly ordered semiconductor nanowire arrays by contact printing.  

PubMed

Controlled and uniform assembly of "bottom-up" nanowire (NW) materials with high scalability presents one of the significant bottleneck challenges facing the integration of nanowires for electronic applications. Here, we demonstrate wafer-scale assembly of highly ordered, dense, and regular arrays of NWs with high uniformity and reproducibility through a simple contact printing process. The assembled NW pitch is shown to be readily modulated through the surface chemical treatment of the receiver substrate, with the highest density approaching approximately 8 NW/mum, approximately 95% directional alignment, and wafer-scale uniformity. Such fine control in the assembly is attained by applying a lubricant during the contact printing process which significantly minimizes the NW-NW mechanical interactions, therefore enabling well-controlled transfer of nanowires through surface chemical binding interactions. Furthermore, we demonstrate that our printing approach enables large-scale integration of NW arrays for various device structures on both rigid silicon and flexible plastic substrates, with a controlled semiconductor channel width ranging from a single NW ( approximately 10 nm) up to approximately 250 microm, consisting of a parallel array of over 1250 NWs and delivering over 1 mA of ON current. PMID:17696563

Fan, Zhiyong; Ho, Johnny C; Jacobson, Zachery A; Yerushalmi, Roie; Alley, Robert L; Razavi, Haleh; Javey, Ali

2008-01-01

38

A Wafer-Scale Etching Technique for High Aspect Ratio Implantable MEMS Structures.  

PubMed

Microsystem technology is well suited to batch fabricate microelectrode arrays, such as the Utah electrode array (UEA), intended for recording and stimulating neural tissue. Fabrication of the UEA is primarily based on the use of dicing and wet etching to achieve high aspect ratio (15:1) penetrating electrodes. An important step in the array fabrication is the etching of electrodes to produce needle-shape electrodes with sharp tips. Traditional etching processes are performed on a single array, and the etching conditions are not optimized. As a result, the process leads to variable geometries of electrodes within an array. Furthermore, the process is not only time consuming but also labor-intensive. This report presents a wafer-scale etching method for the UEA. The method offers several advantages, such as substantial reduction in the processing time, higher throughput and lower cost. More importantly, the method increases the geometrical uniformity from electrode to electrode within an array (1.5 ± 0.5 % non-uniformity), and from array to array within a wafer (2 ± 0.3 % non-uniformity). Also, the etching rate of silicon columns, produced by dicing, are studied as a function of temperature, etching time and stirring rate in a nitric acid rich HF-HNO(3) solution. These parameters were found to be related to the etching rates over the ranges studied and more-importantly affect the uniformity of the etched silicon columns. An optimum etching condition was established to achieve uniform shape electrode arrays on wafer-scale. PMID:20706618

Bhandari, R; Negi, S; Rieth, L; Solzbacher, F

2010-07-01

39

Wafer-scale high-throughput ordered growth of vertically aligned ZnO nanowire arrays.  

PubMed

This article presents an effective approach for patterned growth of vertically aligned ZnO nanowire (NW) arrays with high throughput and low cost at wafer scale without using cleanroom technology. Periodic hole patterns are generated using laser interference lithography on substrates coated with the photoresist SU-8. ZnO NWs are selectively grown through the holes via a low-temperature hydrothermal method without using a catalyst and with a superior control over orientation, location/density, and as-synthesized morphology. The development of textured ZnO seed layers for replacing single crystalline GaN and ZnO substrates extends the large-scale fabrication of vertically aligned ZnO NW arrays on substrates of other materials, such as polymers, Si, and glass. This combined approach demonstrates a novel method of manufacturing large-scale patterned one-dimensional nanostructures on various substrates for applications in energy harvesting, sensing, optoelectronics, and electronic devices. PMID:20681617

Wei, Yaguang; Wu, Wenzhuo; Guo, Rui; Yuan, Dajun; Das, Suman; Wang, Zhong Lin

2010-09-01

40

Wafer-scale process and materials optimization in cross-flow atomic layer deposition  

NASA Astrophysics Data System (ADS)

The exceptional thickness control (atomic scale) and conformality (uniformity over nanoscale 3D features) of atomic layer deposition (ALD) has made it the process of choice for numerous applications from microelectronics to nanotechnology, and for a wide variety of ALD processes and resulting materials. While its benefits derive from self-terminated chemisorbed reactions of alternatively supplied gas precursors, identifying a suitable process window in which ALD's benefits are realized can be a challenge, even in favorable cases. In this work, a strategy exploiting in-situ gas phase sensing in conjunction with ex-situ measurements of the film properties at the wafer scale is employed to explore and optimize the prototypical Al2O3 ALD process. Downstream mass-spectrometry is first used to rapidly identify across the [H2O x Al(CH3)3] process space the exposure conditions leading to surface saturation. The impact of precursor doses outside as well as inside the parameter space outlined by mass-spectrometry is then investigated by characterizing film properties across 100 mm wafer using spectroscopic ellipsometry, CV and IV electrical characterization, XPS and SIMS. Under ideal dose conditions, excellent thickness uniformity was achieved (1sigma/mean<1%) in conjunction with a deposition rate and electrical properties in good agreement with best literature data. As expected, under-dosing of precursor results in depletion of film growth in the flow direction across the wafer surface. Since adsorbed species are reactive with respect to subsequent dose of the complementary precursor, such depletion magnifies non-uniformities as seen in the cross-flow reactor, thereby decorating deviations from a suitable ALD process recipe. Degradation of the permittivity and leakage current density across the wafer was observed though the film composition remained unchanged. Upon higher water dose in the over-exposure regime, deposition rates increased by up to 40% while the uniformity degraded. In contrast, overdosing of TMA and ozone (used for comparison to water) did not affect the process performances. These results point to complex saturation dynamics of water dependent on partial pressure and potential multilayer adsorption caused by hydrogen-bonding.

Lecordier, Laurent Christophe

41

Face-to-face transfer of wafer-scale graphene films.  

PubMed

Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene. PMID:24336218

Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H; Loh, Kian Ping

2014-01-01

42

Face-to-face transfer of wafer-scale graphene films  

NASA Astrophysics Data System (ADS)

Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene.

Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

2014-01-01

43

Novel top-down wafer-scale fabrication of single crystal silicon nanowires.  

PubMed

A new low-cost, top-down nanowire fabrication technology is presented not requiring nanolithography and suitable for any conventional microtechnology cleanroom facility. This novel wafer-scale process technology uses a combination of angled thin-film deposition and etching of a metal layer in a precisely defined cavity with a single micrometer-scale photolithography step. Electrically functional silicon and metallic nanowires with lengths up to several millimeters, lateral widths of 100 nm, and thicknesses 20 nm have been realized and tested. Device characterization includes a general description of device operation, electrochemical biasing, and sensitivity for sensor applications followed by electrical measurements showing linear i-v characteristics with specific contact resistivity rhoc approximately 4 x 10-4 ohm's cm2 and electrochemical behavior of the oxidized silicon nanowires is described with the site-binding model. PMID:19199755

Tong, Hien Duy; Chen, Songyue; van der Wiel, Wilfred G; Carlen, Edwin T; van den Berg, Albert

2009-03-01

44

Wafer scale imprint uniformity evaluated by LSPR spectroscopy: a high volume characterization method for nanometer scale structures.  

PubMed

We exploit the localized surface-plasmon resonance (LSPR) of terahertz gold gammadion structures for wafer scale critical dimension metrology of nanostructures. The proposed characterization method, LSPR spectroscopy, is based on optical transmission measurements and is benchmarked against numerical simulations of imprinted structures characterized by atomic force microscopy. There is a fair agreement between the two methods and the simulations enable the translation of optical spectra to critical dimensions of the physical structures, a concept known from scatterometry. The results demonstrate the potential of LSPR spectroscopy as an alternative characterization method to scanning electron microscopy, atomic force microscopy and scatterometry. PMID:22948403

Jeppesen, Claus; Lindstedt, Daniel Nilsson; Vig, Asger Laurberg; Kristensen, Anders; Mortensen, N Asger

2012-09-28

45

Wafer scale fabrication of submicron chessboard gratings using phase masks in proximity lithography  

NASA Astrophysics Data System (ADS)

One and two dimensional grating structures with submicron period have a huge number of applications in optics and photonics. Such structures are conventionally fabricated using interference or e-beam lithography. However, both technologies have significant drawbacks. Interference lithography is limited to rather simple geometries and the sequential writing scheme of e-beam lithography leads to time consuming exposures for each grating. We present a novel fabrication technique for this class of microstructures which is based on proximity lithography in a mask aligner. The technology is capable to pattern a complete wafer within less than one minute of exposure time and offers thereby high lateral resolution and a reliable process. Our advancements compared to standard mask aligner lithography are twofold: First of all, we are using periodic binary phase masks instead of chromium masks to generate an aerial image of high resolution and exceptional light efficiency at certain distances behind the mask. Second, a special mask aligner illumination set-up is employed which allows to precisely control the incidence angles of the exposure light. This degree of freedom allows both, to shape the aerial image (e. g. transformation of a periodic spot pattern into a chessboard pattern) and to increase its depth of focus considerably. That way, our technology enables the fabrication of high quality gratings with arbitrary geometry in a fast and stable wafer scale process.

Stuerzebecher, Lorenz; Harzendorf, Torsten; Fuchs, Frank; Zeitner, Uwe D.

2012-02-01

46

Wafer scale nano-membranes supported on a silicon microsieve using thin-film transfer technology  

NASA Astrophysics Data System (ADS)

A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independent of the thin film, which is later transferred onto it by fusion bonding, thus providing flexibility in design and processing steps. Using this thin-film transfer technique, nano-membranes down to 50 nm thickness are fabricated. The fabrication of different kinds of membranes made of inorganic, metallic and polymer materials is presented here. Apart from dense nano-membranes, perforated membranes are fabricated using this modular approach. One of the main areas of interest for such membranes is in fluidics, where the low thickness and high strength of the supported nano-membranes are a big advantage.

Unnikrishnan, Sandeep; Jansen, Henri; Berenschot, Erwin; Elwenspoek, Miko

2008-06-01

47

Wafer-scale, three-dimensional helical porous thin films deposited at a glancing angle.  

PubMed

Minimization of helices opens a door to impose novel functions derived from the dimensional shrinkage of optical, mechanical and electronic devices. Glancing angle deposition (GLAD) enables one to deposit three-dimensional helical porous thin films (HPTFs) composed of separated spiral micro/nano-columns. GLAD integrates a series of advantageous features, including one-step deposition, wafer-scale production with mono-handedness of spirals, flexible engineering of spiral materials and dimensions, and the adaption to various kinds of substrates. Herein, we briefly review the fabrication of HPTFs by GLAD, specific growth mechanisms, physical properties in structures, mechanics and chiral optics, and the emerging applications in green energy. A prospective outlook is presented to illuminate some promising developments in enantioselection, bio-dynamic analyses, wirelessly-controlled drug delivery and mass production. PMID:24838479

Huang, Zhifeng; Bai, Fan

2014-07-24

48

Wafer-scale nanopatterning and translation into high-performance piezoelectric nanowires.  

PubMed

The development of a facile method for fabricating one-dimensional, precisely positioned nanostructures over large areas offers exciting opportunities in fundamental research and innovative applications. Large-scale nanofabrication methods have been restricted in accessibility due to their complexity and cost. Likewise, bottom-up synthesis of nanowires has been limited in methods to assemble these structures at precisely defined locations. Nanomaterials such as PbZr(x)Ti(1-x)O(3) (PZT) nanowires (NWs)--which may be useful for nonvolatile memory storage (FeRAM), nanoactuation, and nanoscale power generation--are difficult to synthesize without suffering from polycrystallinity or poor stoichiometric control. Here, we report a novel fabrication method which requires only low-resolution photolithography and electrochemical etching to generate ultrasmooth NWs over wafer scales. These nanostructures are subsequently used as patterning templates to generate PZT nanowires with the highest reported piezoelectric performance (d(eff) ? 145 pm/V). The combined large-scale nanopatterning with hierarchical assembly of functional nanomaterials could yield breakthroughs in areas ranging from nanodevice arrays to nanodevice powering. PMID:20939584

Nguyen, Thanh D; Nagarah, John M; Qi, Yi; Nonnenmann, Stephen S; Morozov, Anatoli V; Li, Simonne; Arnold, Craig B; McAlpine, Michael C

2010-11-10

49

High speed wafer scale bulge testing for the determination of thin film mechanical properties  

PubMed Central

A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50–150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 ?m in width comprised of 720±10 nm thick low pressure chemical vapor deposited silicon nitride with ?20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to ?8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (?350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young’s modulus was estimated for the films assuming a Poisson’s ratio of v=0.25. Calculations to determine Young’s modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young’s modulus for the smaller membranes. The deflection measurements of three 1200×1200 ?m2 Si3N4?x membranes were taken at increased pressures (>25 kPa) to increase nonlinearity and better determine Young’s modulus. This pressure-deflection data were fit to an analytical solution and Young’s modulus estimated to be 257±3 GPa, close to those previously reported in literature.

Orthner, M. P.; Rieth, L. W.; Solzbacher, F.

2010-01-01

50

Development of Three Dimensional LIGA Process to Fabricate Spiral Microcoil  

NASA Astrophysics Data System (ADS)

The LIGA process has been developed as a 2.5-dimensional processing method on Si wafers to date. However, we have succeeded in extending the LIGA process to 3D for the first time. 3D-LIGA was achieved by the technical development of 3D X-ray lithography and worm injection molding replication technology with unscrewing. These technologies began from the development of equipment and have developed into quite original technologies. By combining this 3D-LIGA process with a metallization technique that consists of flat and smooth electroplating and isotropic chemical etching, a spiral copper microstructure with a linewidth of 10 ?m, a pitch of 20 ?m and a thickness of 2 ?m was formed on a cylindrical surface made from LCP with a length of 1 mm and a diameter of 0.48 mm. Furthermore, we applied the process to fabricate a spiral microcoil and estimated the electrical properties of the microcoil. The numbers of turns were 15, the inductance was 91 nH and the quality factor was 5.8 for a frequency of 1 GHz. Direct-current resistance was measured as 99 ?.

Mekaru, Harutaka; Kusumi, Shinji; Sato, Noriaki; Shimizu, Masami; Yamashita, Michiru; Shimada, Osamu; Hattori, Tadashi

2005-07-01

51

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy  

PubMed Central

The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (“metasurfaces”) can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent.

Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

2013-01-01

52

Atomic layer lithography of wafer-scale nanogap arrays for extreme confinement of electromagnetic waves.  

PubMed

Squeezing light through nanometre-wide gaps in metals can lead to extreme field enhancements, nonlocal electromagnetic effects and light-induced electron tunnelling. This intriguing regime, however, has not been readily accessible to experimentalists because of the lack of reliable technology to fabricate uniform nanogaps with atomic-scale resolution and high throughput. Here we introduce a new patterning technology based on atomic layer deposition and simple adhesive-tape-based planarization. Using this method, we create vertically oriented gaps in opaque metal films along the entire contour of a millimetre-sized pattern, with gap widths as narrow as 9.9 Å, and pack 150,000 such devices on a 4-inch wafer. Electromagnetic waves pass exclusively through the nanogaps, enabling background-free transmission measurements. We observe resonant transmission of near-infrared waves through 1.1-nm-wide gaps (?/1,295) and measure an effective refractive index of 17.8. We also observe resonant transmission of millimetre waves through 1.1-nm-wide gaps (?/4,000,000) and infer an unprecedented field enhancement factor of 25,000. PMID:23999053

Chen, Xiaoshu; Park, Hyeong-Ryeol; Pelton, Matthew; Piao, Xianji; Lindquist, Nathan C; Im, Hyungsoon; Kim, Yun Jung; Ahn, Jae Sung; Ahn, Kwang Jun; Park, Namkyoo; Kim, Dai-Sik; Oh, Sang-Hyun

2013-01-01

53

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy.  

PubMed

The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures ("metasurfaces") can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

Wang, Dongxing; Zhu, Wenqi; Best, Michael D; Camden, Jon P; Crozier, Kenneth B

2013-01-01

54

High throughput ultralong (20 cm) nanowire fabrication using a wafer-scale nanograting template.  

PubMed

Nanowires are being actively explored as promising nanostructured materials for high performance flexible electronics, biochemical sensors, photonic applications, solar cells, and secondary batteries. In particular, ultralong (centimeter-long) nanowires are highly attractive from the perspective of electronic performance, device throughput (or productivity), and the possibility of novel applications. However, most previous works on ultralong nanowires have issues related to limited length, productivity, difficult alignment, and deploying onto the planar substrate complying with well-matured device fabrication technologies. Here, we demonstrate a highly ordered ultralong (up to 20 cm) nanowire array, with a diameter of 50 nm (aspect ratio of up to 4,000,000:1), in an unprecedented large (8 in.) scale (2,000,000 strands on a wafer). We first devised a perfectly connected ultralong nanograting master template on the whole area of an 8 in. substrate using a top-down approach, with a density equivalent to that achieved with e-beam lithography (100 nm). Using this large-area, ultralong, high-density nanograting template, we developed a fast and effective method for fabricating up to 20 cm long nanowire arrays on a plastic substrate, composed of metal, dielectric, oxide, and ferroelectric materials. As a suggestion of practical application, a prototype of a large-area aluminum wire grid polarizer was demonstrated. PMID:23899099

Yeon, Jeongho; Lee, Young Jae; Yoo, Dong Eun; Yoo, Kyoung Jong; Kim, Jin Su; Lee, Jun; Lee, Jeong Oen; Choi, Seon-Jin; Yoon, Gun-Wook; Lee, Dong Wook; Lee, Gi Seong; Hwang, Hae Chul; Yoon, Jun-Bo

2013-09-11

55

Double oxide deposition and etching nanolithography for wafer-scale nanopatterning with high-aspect-ratio using photolithography  

NASA Astrophysics Data System (ADS)

We report a nanolithography technique for the high aspect-ratio nanostructure manufacturing using DODE (double oxide deposition and etching) process. Conventional microfabrication processes are integrated to manufacture nanostructure arrays with sub-100 nm of linewidth. This lithography method is developed to overcome resolution limits of photolithography. High aspect-ratio nanostructures with sub-100 nm of lindewidth were fabricated on wafer-scale substrate without nanolithography techniques. The DODE lithography process presented enabled to pave a way to overcome limitations of nanolithography processes and allowed to manufacture large-scale nanostructures using photolithography and thin film deposition and dry etching processes.

Seo, Jungho; Cho, Hanchul; Lee, Ju-kyung; Lee, Jinyoung; Busnaina, Ahmed; Lee, HeaYeon

2013-07-01

56

Integrated modeling of chemical mechanical planarization/polishing (CMP) for integrated circuit fabrication: From particle scale to die and wafer scales  

NASA Astrophysics Data System (ADS)

Chemical mechanical planarization/polishing (CMP) has obtained broad applications in sub-micron integrated circuit (IC) fabrication in recent years. These applications include inter-layer dielectrics planarization, copper damascene process and shallow trench isolation. However, the broad applications of CMP are often limited by a general lack of understanding of the process. With the technology nodes going to 65nm, a more predictable, controllable and reproducible CMP process is needed. Modeling and simulation of CMP will be critical to satisfy the requirements. This work aims to model the CMP process at three scales, namely, particle scale, die scale and wafer scale. The particle-scale model is to understand the roles and interactions of consumable parameters in CMP. The topography and material properties of the pad, abrasive particle size and size distribution, abrasive weight concentration and slurry chemicals influencing the passivation rate of wafer surface are identified as the most important parameters in the CMP material removal process. Based on the model, they contribute to the material removal through two parameters; one, the number of active abrasives over the wafer-pad interface, and the other, material removal by a single active abrasive. The number of active abrasives first depends on the pad topography and abrasive weight concentration. A rough pad can capture more abrasives. A larger abrasive weight concentration indicates a larger number of abrasives per unit volume of slurry. Further, the abrasive size distribution is critical for the number. Only a small portion of abrasives on the tail of the distribution function are involved in the material removal process. This portion is a function of the gap between wafer and pad over the contact area with abrasives in-between. Only abrasives larger than the gap, which is determined by the wafer-pad contact ratio (function of pad topography and pad Young's modulus) and pad hardness, can be involved in the material removal process. The material removed by a single active abrasive is determined by the size of abrasive and force applied on the abrasives. The force is a function of wafer-pad contact area ratio. The average size of active abrasives depends on the abrasive size distribution. The roles of abrasive size distribution in material removal are therefore two fold. While the portion is increased with the gap, the size of active abrasives becomes smaller. (Abstract shortened by UMI.)

Luo, Jianfeng

2003-10-01

57

On-wafer level packaging of RF MEMS devices for Ka-band applications  

Microsoft Academic Search

In this paper, on-wafer level packaging technology for RF MEMS is described, and then a novel packaging design for RF MEMS devices with different fabrication technology at millimeter-wave band is presented. The discussed RF MEMS devices on naked wafer includes a MEMS filter and a distributed MEMS transmission line (DMTL) phase shifter, which are fabricated using LIGA and micromachined technology,

Qun Wu; Bo-Shi Jin; Xun-Jun He; Kai Tang; Fang Zhang; Jong-Chul Lee

2006-01-01

58

Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics  

NASA Astrophysics Data System (ADS)

Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

2014-02-01

59

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.  

PubMed

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

60

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking  

PubMed Central

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-01-01

61

Stationary Optical Concentrator Designs and Wafer Scale Monolithic Integration of Semiconductor Devices for Next Generation Photovoltaic Panels  

NASA Astrophysics Data System (ADS)

A major barrier in utilizing solar energy for large scale deployment is the cost of the photovoltaic (PV) systems. Several approaches have been used for the cost reduction such as by modifying PV system designs in addition to enhancing the efficiency of solar cells. Due to the high cost of materials, minimizing the use of solar cells such as in concentrator type systems is highly attractive for reducing the cost of the PV modules by focusing the incident light onto the PV cell. However concentrator PV systems (CPV) require constant tracking of the sun and hence are complex in design and expensive to operate, except in limited situations such as large scale PV power plants. It is desirable to design new concentrator type systems that do not require continuous tracking of the sun. These systems could ultimately reduce the PV system cost to a minimum while maximizing the power conversion efficiency. In this thesis we propose a simple design for a stationary concentrator photovoltaic (SCPV) system that could significantly reduce the cost of generating electricity using PV devices. Using optical ray tracing simulations, we have been able to design SCPV systems that could reduce the PV module cost by 2--10 times without compromising on the power conversion efficiency of the system. Another alternative approach for sustainable high efficiency PV system design is to develop low cost PV cells for terrestrial applications. To meet the demands of low cost and large scale production, larger and thinner (or flexible) substrates are required. We demonstrated the feasibility of fabricating monolithic interconnected PV devices at the wafer scale (2 inch wafers). In this study, GaSb PV cells grown on semi-insulating GaAs were used as the model material. Crucial device fabrication steps such as a selective etching process have been developed that is necessary for isolating individual devices on the wafer and interconnecting them with sub-micron scale accuracy. Selective etching of GaSb and GaAs has been developed for isolation of GaSb devices on semi-insulating GaAs substrates. Smooth side wall morphology and desirable depth profile of the etched structures have been accomplished using optimized etching conditions presented in this thesis. Device fabrication of series interconnected GaSb PV cells on a GaAs substrate with single-sided metal contacts has been successfully demonstrated.

Kim, Jung Min

62

Modeling electrodeposition for LIGA microdevice fabrication  

SciTech Connect

To better understand and to help optimize the electroforming portion of the LIGA process, we have developed one and two-dimensional numerical models describing electrode-position of metal into high aspect-ratio molds. The one-dimensional model addresses dissociation, diffusion, electromigration, and deposition of multiple ion species. The two-dimensional model is limited to a single species, but includes transport induced by forced flow of electrolyte outside the mold and by buoyancy associated with metal ion depletion within the mold. To guide model development and to validate these models, we have also conducted a series of laboratory experiments using a sulfamate bath to deposit nickel in cylindrical molds having aspect ratios up to twenty-five. The experimental results indicate that current densities well in excess of the diffusion-limited currents may still yield metal deposits of acceptable morphology. However, the numerical models demonstrate that such large ion fluxes cannot be sustained by convection within the mold resulting from flow across the mold top. Instead, calculations suggest that the observed enhancement of transport probably results from natural convection within the molds, and that buoyancy-driven flows may be critical to metal ion transport even in micron-scale features having very large aspect ratios. Taking advantage of this enhanced ion transport may allow order-of-magnitude reductions in electroforming times for LIGA microdevice fabrication. 42 refs., 14 figs., 1 tab.

Griffiths, S.K.; Nilson, R.H.; Bradshaw, R.W. [and others

1998-02-01

63

Room-temperature epitaxial electrodeposition of single-crystalline germanium nanowires at the wafer scale from an aqueous solution.  

PubMed

Direct epitaxial growth of single-crystalline germanium (Ge) nanowires at room temperature has been performed through an electrodeposition process on conductive wafers immersed in an aqueous bath. The crystal growth is based on an electrochemical liquid-liquid-solid (ec-LLS) process involving the electroreduction of dissolved GeO2(aq) in water at isolated liquid gallium (Ga) nanodroplet electrodes resting on single-crystalline Ge or Si supports. Ge nanowires were electrodeposited on the wafer scale (>10 cm(2)) using only common glassware and a digital potentiostat. High-resolution electron micrographs and electron diffraction patterns collected from cross sections of individual substrate-nanowire contacts in addition to scanning electron micrographs of the orientation of nanowires across entire films on substrates with different crystalline orientations, supported the notion of epitaxial nanowire growth. Energy dispersive spectroscopic elemental mapping of single nanowires indicated the Ga(l) nanodroplet remains affixed to the tip of the growing nanowire throughout the nanowire electrodeposition process. Current-voltage responses measured across many individual nanowires yielded reproducible resistance values. The presented data cumulatively show epitaxial growth of covalent group IV nanowires is possible from the reduction of a dissolved oxide under purely benchtop conditions. PMID:24417670

Fahrenkrug, Eli; Gu, Junsi; Jeon, Sunyeol; Veneman, P Alexander; Goldman, Rachel S; Maldonado, Stephen

2014-02-12

64

Design and fabrication of a LIGA milliengine  

SciTech Connect

This paper reports on the design and fabrication of a new milliscale magnetic actuator that is ideally suited for LIGA processing. LIGA processing permits the fabrication of millisized machine elements that cannot be fabricated by conventional miniature machining techniques because of their small feature sizes. The Milliengine is a magnetically driven device that utilizes a unique design to extend the 2-dimensional fabrication capability of LIGA to create 3-dimensional machinery.

Garcia, E.J.; Christenson, T.R.; Polosky, M.A.; Jojola, A.A.

1997-04-01

65

C- and L-band erbium-doped waveguide lasers with wafer-scale silicon nitride cavities.  

PubMed

We report on integrated erbium-doped waveguide lasers designed for silicon photonic systems. The distributed Bragg reflector laser cavities consist of silicon nitride waveguide and grating features defined by wafer-scale immersion lithography and a top erbium-doped aluminum oxide layer deposited as the final step in the fabrication process. The resulting inverted ridge waveguide yields high optical intensity overlap with the active medium for both the 0.98 ?m pump (89%) and 1.5 ?m laser (87%) wavelengths with a pump-laser intensity overlap of >93%. We obtain output powers of up to 5 mW and show lasing at widely spaced wavelengths within both the C and L bands of the erbium gain spectrum (1536, 1561, and 1596 nm). PMID:23862218

Purnawirman; Sun, J; Adam, T N; Leake, G; Coolbaugh, D; Bradley, J D B; Shah Hosseini, E; Watts, M R

2013-06-01

66

Wafer-scale integration of group III-V lasers on silicon using transfer printing of epitaxial layers  

NASA Astrophysics Data System (ADS)

The hard-drive and electronic industries can benefit by using the properties of light for power transfer and signalling. However, the integration of silicon electronics with lasers remains a challenge, because practical monolithic silicon lasers are not currently available. Here, we demonstrate a strategy for this integration, using an elastomeric stamp to selectively release and transfer epitaxial coupons of GaAs to realize III-V lasers on a silicon substrate by means of a wafer-scale printing process. Low-threshold continuous-wave lasing at a wavelength of 824 nm is achieved from Fabry-Pérot ridge waveguide lasers operating at temperatures up to 100 °C. Single and multi-transverse mode devices emit total optical powers of >60 mW and support modulation bandwidths of >3 GHz. This fabrication strategy opens a route to the low-cost integration of III-V photonic devices and circuits on silicon and other substrates.

Justice, John; Bower, Chris; Meitl, Matthew; Mooney, Marcus B.; Gubbins, Mark A.; Corbett, Brian

2012-09-01

67

Erasable diffractive grating couplers in silicon on insulator for wafer scale testing  

NASA Astrophysics Data System (ADS)

Test points are essential in allowing optical circuits on a wafer to be autonomously tested after selected manufacturing steps, hence allowing poor performance or device failures to be detected early and to be either repaired using direct write methods, or a cessation of further processing to reduce fabrication costs. Grating couplers are a commonly used method for efficiently coupling light from an optical fibre to a silicon waveguide. They are relatively easy to fabricate and they allow light to be coupled into/out from any location on the device without the need for polishing, making them good candidates for an optical test point. A fixed test point can be added for this purpose, although traditionally these grating devices are fabricated by etching the silicon waveguide, and hence this permanently adds loss and leads to a poor performing device when placed into use after testing. We demonstrate a similar device utilising a refractive index change induced by lattice disorder. Raman data collected suggests this lattice damage is reversible, allowing a laser to subsequently erase the grating coupler.

Topley, R.; Martinez-Jimenez, G.; O'Faolain, L.; Healy, N.; Mailis, S.; Thomson, D. J.; Gardes, F. Y.; Peacock, A. C.; Payne, D. N. R.; Mashanovich, G. Z.; Reed, G. T.

2014-03-01

68

Wafer-scale fabrication of patterned carbon nanofiber nanoelectrode arrays: a route for development of multiplexed, ultrasensitive disposable biosensors.  

PubMed

One of the major limitations in the development of ultrasensitive electrochemical biosensors based on one-dimensional nanostructures is the difficulty involved with reliably fabricating nanoelectrode arrays (NEAs). In this work, we describe a simple, robust and scalable wafer-scale fabrication method to produce multiplexed biosensors. Each sensor chip consists of nine individually addressable arrays that uses electron beam patterned vertically aligned carbon nanofibers (VACNFs) as the sensing element. To ensure nanoelectrode behavior with higher sensitivity, VACNFs were precisely grown on 100 nm Ni dots with 1 microm spacing on each micro pad. Pretreatments by the combination of soaking in 1.0 M HNO(3) and electrochemical etching in 1.0M NaOH dramatically improved the electrode performance, indicated by the decrease of redox peak separation in cyclic voltammogram (DeltaE(p)) to approximately 100 mV and an approximately 200% increase in steady-state currents. The electrochemical detection of the hybridization of DNA targets from E. coli O157:H7 onto oligonucleotide probes were successfully demonstrated. The 9 arrays within the chip were divided into three groups with triplicate sensors for positive control, negative control and specific hybridization. The proposed method has the potential to be scaled up to NxN arrays with N up to 10, which is ideal for detecting a myriad of organisms. In addition, such sensors can be used as a generic platform for many electroanalysis applications. PMID:19303281

Arumugam, Prabhu U; Chen, Hua; Siddiqui, Shabnam; Weinrich, Jarret A P; Jejelowo, Ayodeji; Li, Jun; Meyyappan, M

2009-05-15

69

Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics.  

PubMed

Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V. PMID:24256403

Heo, Jinseong; Byun, Kyung-Eun; Lee, Jaeho; Chung, Hyun-Jong; Jeon, Sanghun; Park, Seongjun; Hwang, Sungwoo

2013-12-11

70

Miniature Inchworm Actuators Fabricated by Use of LIGA  

NASA Technical Reports Server (NTRS)

Miniature inchworm actuators that would have relatively simple designs have been proposed for applications in which there are requirements for displacements of the order of microns or tens of microns and for the ability to hold their positions when electric power is not applied. The proposed actuators would be members of the class of microelectromechanical systems (MEMS), but would be designed and fabricated following an approach that is somewhat unusual for MEMS. Like other MEMS actuators, the proposed inchworm actuators could utilize thermoplastic, bimetallic, shape-memory-alloy, or piezoelectric actuation principles. The figure depicts a piezoelectric inchworm actuator according to the proposal. As in other inchworm actuators, linear motion of an extensible member would be achieved by lengthening and shortening the extensible member in synchronism with alternately clamping and releasing one and then the other end of the member. In this case, the moving member would be the middle one; the member would be piezoelectric and would be shortened by applying a voltage to it. The two outer members would also be piezoelectric; the release of the clamps on the upper or lower end would be achieved by applying a voltage to the electrodes on the upper or lower ends, respectively, of these members. Usually, MEMS actuators cannot be fabricated directly on the side walls of silicon wafers, yet the geometry of this actuator necessitates such fabrication. The solution, according to the proposal, would be to use the microfabrication technique known by the German acronym LIGA - "lithographie, galvanoformung, abformung," which means lithography, electroforming, molding. LIGA involves x-ray lithography of a polymer film followed by selective removal of material to form a three-dimensional pattern from which a mold is made. Among the advantages of LIGA for this purpose are that it is applicable to a broad range of materials, can be used to implement a variety of designs, including those of structures >1 mm high, affords submicron precision, and is amenable to mass production at relatively low unit cost. Fabrication of the proposed actuators would involve some technological risks - in particular, in the integration of electrode connection lines and placement of actuator elements. It will also be necessary to perform an intensive study of the feasibility of growing piezoelectric crystals onto LIGA molds.

Yang, Eui-Hyeok

2003-01-01

71

Wafer-scale laser lithography. I. Pyrolytic deposition of metal microstructures. [For ultra-large scale integrated circuits  

SciTech Connect

Mechanisms for laser-driven pyrolytic deposition of micron-scale metal structures on crystalline silicon have been studied. Models have been developed to predict temporal and spatial propeties of laser-induced pyrolytic deposition processes. An argon ion laser-based apparatus has been used to deposit metal by pyrolytic decomposition of metal alkyl and carbonyl compounds, in order to evaluate the models. These results of these studies are discussed, along with their implications for the high-speed creation of micron-scale metal structures in ultra-large scale integrated circuit systems. 4 figures.

Herman, I.P.; Hyde, R.A.; McWilliams, B.M.; Weisberg, A.H.; Wood, L.L.

1982-01-01

72

100 mm wafer-scale InP-based (?=1.6 ?m) epitaxial transfer for hybrid silicon evanescent lasers  

Microsoft Academic Search

We report the large epitaxial transfer of 100 mm InP\\/InGaAs\\/InP wafers to Silicon-on-insulator (SOI) substrates through a low-temperature (300degC) O2 plasma- assisted wafer bonding process. Efficient vertical outgassing channels (VOCs) are developed to eliminate the fundamental obstacle of interfacial voids in bonding due to intrinsic chemical reactions. Generated gas species of H2O and H2 can quickly diffuse to VOCs, etched

Di Liang; Alexander W. Fang; John E. Bowers

2008-01-01

73

Injection molding of polymeric LIGA HARMs  

Microsoft Academic Search

The primary goal of an ongoing research effort at LSU is to develop the three-step LIGA process to inexpensively manufacture\\u000a high aspect ratio microstructures (HARMs). The first two steps of the process (lithography and electroplating) produce a metallic\\u000a mold insert that can be used as a template for molding microstructures. The final step of LIGA is molding. This paper focuses

M. S. Despa; K. W. Kelly; J. R. Collier

1999-01-01

74

Wafer Scale Distributed Radio.  

National Technical Information Service (NTIS)

Modem silicon technology offers ultrafast transistors, with fT > 200 GHz in today's 45nm CMOS and fT > 300 GHz in SiGe. While extremely fast, these transistors suffer from several limitations which affect the performance of high dynamic range analog and R...

A. M. Niknejad B. Nikolic E. Alon J. Rabaey

2009-01-01

75

Imaging ATUM ultrathin section libraries with WaferMapper: a multi-scale approach to EM reconstruction of neural circuits  

PubMed Central

The automated tape-collecting ultramicrotome (ATUM) makes it possible to collect large numbers of ultrathin sections quickly—the equivalent of a petabyte of high resolution images each day. However, even high throughput image acquisition strategies generate images far more slowly (at present ~1 terabyte per day). We therefore developed WaferMapper, a software package that takes a multi-resolution approach to mapping and imaging select regions within a library of ultrathin sections. This automated method selects and directs imaging of corresponding regions within each section of an ultrathin section library (UTSL) that may contain many thousands of sections. Using WaferMapper, it is possible to map thousands of tissue sections at low resolution and target multiple points of interest for high resolution imaging based on anatomical landmarks. The program can also be used to expand previously imaged regions, acquire data under different imaging conditions, or re-image after additional tissue treatments.

Hayworth, Kenneth J.; Morgan, Josh L.; Schalek, Richard; Berger, Daniel R.; Hildebrand, David G. C.; Lichtman, Jeff W.

2014-01-01

76

Photoluminescence of Single GaN/InGaN Nanorod Light Emitting Diode Fabricated on a Wafer Scale  

NASA Astrophysics Data System (ADS)

Nanorod arrays were fabricated on a blue InGaN/GaN single quantum well (QW) LED wafer using nanoimprint lithography. A regular hexagonal lattice of nanorods was made at a pitch of 2 ?m producing single quantum disks in the nanorods with diameter of ˜400 nm. Time integrated micro-photoluminescence was performed to investigate the emission properties of top down processed single nanorods at 4.2 K. Micro-photoluminescence maps were made to study the spatial isolation of the photoluminescence emission, showing a good contrast ratio between nanorods. Excitation power dependent studies show screening of the quantum confined Stark effect for both the unprocessed wafer and the single nanorod. At low excitation powers, localised states appearing as sharp peaks in the photoluminescence spectrum were visible with a density of approximately four peaks per nanorod.

Chan, Christopher C. S.; Zhuang, YiDing; Reid, Benjamin P. L.; Jia, Wei; Holmes, Mark J.; Alexander-Webber, Jack A.; Nakazawa, Shingo; Shields, Philip A.; Allsopp, Duncan W. E.; Taylor, Robert A.

2013-08-01

77

Fast and robust hydrogen sensors based on discontinuous palladium films on polyimide, fabricated on a wafer scale  

Microsoft Academic Search

Fast hydrogen sensors based on discontinuous palladium (Pd) films on supporting polyimide layers, fabricated by a cost-efficient and full-wafer compatible process, are presented. The films, deposited by electron-beam evaporation with a nominal thickness of 1.5 nm, consist of isolated Pd islands that are separated by nanoscopic gaps. On hydrogenation, the volume expansion of Pd brings initially separated islands into contact

T. Kiefer; L. G. Villanueva; F. Fargier; F. Favier; J. Brugger

2010-01-01

78

A 5 mm ×5 mm ×1.37 mm hermetic FBAR duplexer for PCS handsets with wafer-scale packaging  

Microsoft Academic Search

We describe the design and measured performance of a 5 mm ×5 mm ×1.37 mm antenna duplexer for the U.S. PCS band (Tx: 1850-1910 MHz, Rx: 1930-1990 MHz) for cellular handsets based on FBAR (film acoustic resonator) technology. The FBARs are fabricated in a silicon-based IC process technology and are hermetically sealed in a wafer-level packaging process. Two dice, Tx

P. D. Bradley; R. Ruby; A. Barfknecht; F. Geefay; C. Han; G. Gan; Y. Oshmyansky

2002-01-01

79

Laparoscopic Decortication of Hilar Renal Cysts Using LigaSure  

PubMed Central

Background and Objectives: In this study, we evaluated the safety and efficacy of using the LigaSure sealing system (Valleylab, Boulder, Colorado) for laparoscopic decortication of symptomatic hilar renal cysts. Methods: Seventeen patients underwent laparoscopic decortication of hilar renal cysts with the LigaSure system. Our study included only symptomatic, Bosniak type 1, simple and symptomatic renal cysts. The operative route, transperitoneal or retroperitoneal, was planned according to the location confirmed by computed tomography. The patients' symptoms were preoperatively and postoperatively evaluated by the Wong-Baker visual pain scale. Operative measures and radiologic outcomes were prospectively evaluated. Results: The mean age of the patients was 56.4 years, and the mean follow-up period was 12.5 months. Preoperative computed tomography showed only a single cyst in 15 patients (88.2%) and showed two separate cysts in 2 cases (11.8%). The cysts were located in the perihilar region close to the vascular structure in all patients. A transperitoneal approach was used in 9 patients, and a retroperitoneal approach was used in 8 patients. The mean operative time and hospitalization time were 56.4 minutes and 1.2 days, respectively. Minor complications were observed in 3 patients. Symptomatic and radiologic success rates of 94.2% and 100%, respectively, were achieved. Conclusion: Laparoscopic decortication of symptomatic hilar renal cysts—first reported in the literature in this study—using the LigaSure sealing system is feasible, effective, and safe, even if the cyst is located in the perihilar area.

Tepeler, Abdulkadir; Gunes, Mustafa; S?lay, Mesrur Selcuk; Akman, Tolga; Akcay, Muzaffer; Armagan, Abdullah; Onol, Sinasi Yavuz

2014-01-01

80

Laser wafering for silicon solar.  

SciTech Connect

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

81

Nano-scale origins of recombination activity and optical properties of extended defects in mc-Si wafers and PV cells  

NASA Astrophysics Data System (ADS)

Multicrystalline silicon (mc-Si) is the most used absorber in photovoltaic (PV) cells at present. If efficiencies are to improve in this established technology a better understanding of how minority carrier lifetimes are reduced is necessary. The capture of minority carriers by states associated with extended defects is known to play a major role in reducing minority carrier lifetimes. Energy levels introduced into the silicon bandgap often have electrical activity or optical signatures that can provide clues as to the structural or chemical origin of a particular level. This work utilizes electron beam induced current (EBIC), cathodoluminescence (CL) imaging and spectroscopy, photoluminescence (PL) imaging, and nano-scale chemical analysis to provide new insight into the origin of the electrical and optical properties of extended defects in mc-Si wafers and PV cells. A new interpretation of the temperature dependence of EBIC contrast is formulated based on observations of an anomalous form of the contrast vs. temperature curves as well as evidence of high impurity content. In addition an attempt is made to determine the origin of specific types of defect related emission as well as how this emission is influenced by processing steps applied to mc-Si wafers. Nano-scale chemical analysis is used to reveal the origin of the observed luminescence.

Guthrey, Harvey L., IV

82

Fast and robust hydrogen sensors based on discontinuous palladium films on polyimide, fabricated on a wafer scale  

NASA Astrophysics Data System (ADS)

Fast hydrogen sensors based on discontinuous palladium (Pd) films on supporting polyimide layers, fabricated by a cost-efficient and full-wafer compatible process, are presented. The films, deposited by electron-beam evaporation with a nominal thickness of 1.5 nm, consist of isolated Pd islands that are separated by nanoscopic gaps. On hydrogenation, the volume expansion of Pd brings initially separated islands into contact which leads to the creation of new electrical pathways through the film. The supporting polyimide layer provides both sufficient elasticity for the Pd nanoclusters to expand on hydrogenation and a sufficiently high surface energy for good adhesion of both film and contacting electrodes. The novel order of the fabrication processes involves a dicing step prior to the Pd deposition and stencil lithography for the patterning of microelectrodes. This allows us to preserve the as-deposited film properties. The devices work at room temperature, show response times of a few seconds and have a low power consumption of some tens of nW.

Kiefer, T.; Villanueva, L. G.; Fargier, F.; Favier, F.; Brugger, J.

2010-12-01

83

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology  

NASA Astrophysics Data System (ADS)

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 ?m SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

84

Layer-controlled, wafer-scale, and conformal synthesis of tungsten disulfide nanosheets using atomic layer deposition.  

PubMed

The synthesis of atomically thin transition-metal disulfides (MS2) with layer controllability and large-area uniformity is an essential requirement for their application in electronic and optical devices. In this work, we describe a process for the synthesis of WS2 nanosheets through the sulfurization of an atomic layer deposition (ALD) WO3 film with systematic layer controllability and wafer-level uniformity. The X-ray photoemission spectroscopy, Raman, and photoluminescence measurements exhibit that the ALD-based WS2 nanosheets have good stoichiometry, clear Raman shift, and bandgap dependence as a function of the number of layers. The electron mobility of the monolayer WS2 measured using a field-effect transistor (FET) with a high-k dielectric gate insulator is shown to be better than that of CVD-grown WS2, and the subthreshold swing is comparable to that of an exfoliated MoS2 FET device. Moreover, by utilizing the high conformality of the ALD process, we have developed a process for the fabrication of WS2 nanotubes. PMID:24252136

Song, Jeong-Gyu; Park, Jusang; Lee, Wonseon; Choi, Taejin; Jung, Hanearl; Lee, Chang Wan; Hwang, Sung-Hwan; Myoung, Jae Min; Jung, Jae-Hoon; Kim, Soo-Hyun; Lansalot-Matras, Clement; Kim, Hyungjun

2013-12-23

85

Synthesis of wafer-scale uniform molybdenum disulfide films with control over the layer number using a gas phase sulfur precursor  

NASA Astrophysics Data System (ADS)

We describe a method for synthesizing large-area and uniform molybdenum disulfide films, with control over the layer number, on insulating substrates using a gas phase sulfuric precursor (H2S) and a molybdenum metal source. The metal layer thickness was varied to effectively control the number of layers (2 to 12) present in the synthesized film. The films were grown on wafer-scale Si/SiO2 or quartz substrates and displayed excellent uniformity and a high crystallinity over the entire area. Thin film transistors were prepared using these materials, and the performances of the devices were tested. The devices displayed an on/off current ratio of 105, a mobility of 0.12 cm2 V-1 s-1 (mean mobility value of 0.07 cm2 V-1 s-1), and reliable operation.We describe a method for synthesizing large-area and uniform molybdenum disulfide films, with control over the layer number, on insulating substrates using a gas phase sulfuric precursor (H2S) and a molybdenum metal source. The metal layer thickness was varied to effectively control the number of layers (2 to 12) present in the synthesized film. The films were grown on wafer-scale Si/SiO2 or quartz substrates and displayed excellent uniformity and a high crystallinity over the entire area. Thin film transistors were prepared using these materials, and the performances of the devices were tested. The devices displayed an on/off current ratio of 105, a mobility of 0.12 cm2 V-1 s-1 (mean mobility value of 0.07 cm2 V-1 s-1), and reliable operation. Electronic supplementary information (ESI) available: Schematic illustration of the CVD system and AFM and HRTEM measurements. See DOI: 10.1039/c3nr05993f

Lee, Youngbin; Lee, Jinhwan; Bark, Hunyoung; Oh, Il-Kwon; Ryu, Gyeong Hee; Lee, Zonghoon; Kim, Hyungjun; Cho, Jeong Ho; Ahn, Jong-Hyun; Lee, Changgu

2014-02-01

86

Batch transfer of LIGA microstructures by selective electroplating and bonding  

Microsoft Academic Search

A flip-chip batch transfer process for LIthographie, Galvanoformung and Abformung (LIGA) microstructures has been demonstrated by selective electroplating and bonding. Single layer LIGA microstructures with thickness of 200 ?m are fabricated on a dummy substrate first. They are then batch transferred to an IC substrate by means of bonding via electroplating. After the selective bonding process, the originally fixed microstructures

Li-Wei Pan; Liwei Lin

2001-01-01

87

Silicon Wafer Polishing  

NSDL National Science Digital Library

This Quicktime animation demostrates the final polishing and cleaning processes required for creating semiconductor devices and integrated circuits. This animation is the sixth in a series of how silicon wafers are created. The previous animation showing silicon wafer lapping can be seen here. The next animation in this sequence about the optional silicon wafer epitaxy process can be seen here.

2009-10-21

88

Fabrication of LIGA mold insert using Ni-PTFE composite micro-electroforming  

Microsoft Academic Search

The LIGA process, which combines deep X-ray lithography with electroforming and polymer molding, is a main fabrication method for producing MEMS. And hot embossing is one of the main processing techniques for polymer microfabrication, which helps the LIGA (UV-LIGA) technology to achieve low cost mass production. And electroforming of LIGA mold insert with lower surface energy and friction coefficient is

Yuhua Guo; Gang Liu; Ying Xiong; Xuelin Zhu; Wang Jun; Yangchao Tian

2006-01-01

89

Silicon Wafer Lapping  

NSDL National Science Digital Library

This Quicktime animation shows how the machining process of "lapping" removes controlled amounts of silicon from a wafer in order to ensure flatness of the silicon wafer. This process removes particles and improves the quality of the wafer after they are cut. This animation is the fifth in a series of how silicon wafers are created.The previous animation showing silicon ingot edge profiling can be seen here.The next animation in this sequence about silicon wafer polishing can be seen here.

2010-02-08

90

Micro-grippers for assembly of LIGA parts  

SciTech Connect

This paper describes ongoing testing of two microgrippers for assembly of LIGA (Lithographie Galvanoformung Abformung) parts. The goal is to place 100 micron outside diameter (OD) LIGA gears with a 50 micron inner diameter hole onto pins ranging from 35 to 49 microns. The first micro gripper is a vacuum gripper made of a 100 micron OD stainless steel tube. The second micro gripper is a set of tweezers fabricated using the LIGA process. Nickel, Permalloy, and copper materials are tested. The tweezers are actuated by a collet mechanism which is closed by a DC linear motor.

Feddema, J.; Polosky, M.; Christenson, T.; Spletzer, B.; Simon, R.

1997-12-31

91

Wafer and piece-wise Si tip transfer technologies for applications in scanning probe microscopy  

Microsoft Academic Search

A novel tip transfer technology is proposed for applications in scanning probe microscopy (SPM). The technology is based on the concept of fabricating tips on an independent wafer and transferring them onto the target wafer. The transfer is also feasible on a full 4-in wafer scale. This is especially attractive for postprocessing CMOS wafers, e.g., for atomic force microscopy chips

Terunobu Akiyama; Urs Staufer; Nicolaas F. de Rooij

1999-01-01

92

Cantilevered multilevel LIGA devices and methods  

DOEpatents

In the formation of multilevel LIGA microstructures, a preformed sheet of photoresist material, such as polymethylmethacrylate (PMMA) is patterned by exposure through a mask to radiation, such as X-rays, and developed using a developer to remove the exposed photoresist material. A first microstructure is then formed by electroplating metal into the areas from which the photoresist has been removed. Additional levels of microstructure are added to the initial microstructure by covering the first microstructure with a conductive polymer, machining the conductive polymer layer to reveal the surface of the first microstructure, sealing the conductive polymer and surface of the first microstructure with a metal layer, and then forming the second level of structure on top of the first level structure. In such a manner, multiple layers of microstructure can be built up to allow complex cantilevered microstructures to be formed.

Morales, Alfredo Martin (Pleasanton, CA); Domeier, Linda A. (Danville, CA)

2002-01-01

93

Modeling electrodeposition in LIGA microfabrication using an arbitrary-Lagrangian-Eulerian formulation for moving-boundary tracking with repeated re-meshing.  

SciTech Connect

Electrodeposition is a key process in LIGA (Lithographie, Galvanoformung, Abformung - German words for lithography, electroplating and molding) - microfabrication, which is increasingly demonstrated to be a viable technology for fabricating micro-devices or parts. LIGA Electrodeposition involves complex multi-physics phenomena: (1) diffusion, migration, and convection of charged species in a centimeter-scale electrolyte-bath region and in micron-scale featurecavity or trench regions; (2) homogeneous and heterogeneous electrochemical reactions; and (3) moving deposition surface or surfaces on which metal ions (e.g., {approx} i) are electrochemically reduced to form a pure metal or an alloy.

Chen, Ken Shuang

2003-06-01

94

Miniature Scroll Pumps Fabricated by LIGA  

NASA Technical Reports Server (NTRS)

Miniature scroll pumps have been proposed as roughing pumps (low - vacuum pumps) for miniature scientific instruments (e.g., portable mass spectrometers and gas analyzers) that depend on vacuum. The larger scroll pumps used as roughing pumps in some older vacuum systems are fabricated by conventional machining. Typically, such an older scroll pump includes (1) an electric motor with an eccentric shaft to generate orbital motion of a scroll and (2) conventional bearings to restrict the orbital motion to a circle. The proposed miniature scroll pumps would differ from the prior, larger ones in both design and fabrication. A miniature scroll pump would include two scrolls: one mounted on a stationary baseplate and one on a flexure stage (see figure). An electromagnetic actuator in the form of two pairs of voice coils in a push-pull configuration would make the flexure stage move in the desired circular orbit. The capacitance between the scrolls would be monitored to provide position (gap) feedback to a control system that would adjust the drive signals applied to the voice coils to maintain the circular orbit as needed for precise sealing of the scrolls. To minimize power consumption and maximize precision of control, the flexure stage would be driven at the frequency of its mechanical resonance. The miniaturization of these pumps would entail both operational and manufacturing tolerances of <1 m. Such tight tolerances cannot be achieved easily by conventional machining of high-aspect-ratio structures like those of scroll-pump components. In addition, the vibrations of conventional motors and ball bearings exceed these tight tolerances by an order of magnitude. Therefore, the proposed pumps would be fabricated by the microfabrication method known by the German acronym LIGA ( lithographie, galvanoformung, abformung, which means lithography, electroforming, molding) because LIGA has been shown to be capable of providing the required tolerances at large aspect ratios.

Wiberg, Dean; Shcheglov, Kirill; White, Victor; Bae, Sam

2009-01-01

95

A smart material microamplification mechanism fabricated using LIGA  

NASA Astrophysics Data System (ADS)

A unique microamplification mechanism formed through the merging of smart material and microelectromechanical system concepts is presented. This microamplification device increases the useful actuation stroke of piezoceramic material through the amplification of piezoceramic strain. The technology demonstrated has utility as a microactuation mechanism for driving micropiezomotors, hearing aid transducers and precision optical switches. The microamplifier, approximately 0964-1726/7/1/012/img1, is composed of electroplated nickel and was constructed using LIGA. An overview of microactuator system requirements and the advantages of scaling the flexure based amplifier illustrates the utility of the new device. The microamplifier is a radically scaled version of a mesoscopic mechanism. An analytical discussion of the operation is presented along with a finite-element analysis of the static and dynamic properties of the microlever. The analytical study is used to develop the operation principles and expected performance of the microamplifier. Experimental static and dynamic testing results are presented that confirm the analytical study. The mechanism has a mean amplification ratio of 5.48, an elastic stroke range of 8 0964-1726/7/1/012/img2m and a fundamental frequency of 82 kHz.

Pokines, Brett J.; Garcia, Ephrahim

1998-02-01

96

Scalability potential in ELTRAN(R) SOI-epi wafer  

Microsoft Academic Search

For coming device applications, advanced requirements for silicon-on-insulator (SOI) wafers are increasing. One of the most important items is scalability that includes scaling up of the wafer diameter and scaling down of the SOI layer thickness (tSOI). 300 mm wafers and ultra thin SOI with tSOI less than 100 nm will be required according to the ITRS (SIA, 1999). 300

M. Ito; K. Yamagata; H. Miyabayashi; T. Yonehara

2000-01-01

97

In-device enzyme immobilization: wafer-level fabrication of an integrated glucose sensor  

Microsoft Academic Search

Wafer-level fabrication of integrated enzyme-based BioMEMS usually requires high temperature wafer-bonding techniques such as anodic bonding. Enzymes denature at comparatively low temperatures. Thus, enzymes need to be immobilized after wafer bonding. A convenient in-device immobilization method is presented allowing wafer-level patterning of enzymes inside micro-scale flow channels after wafer bonding. Enzymes are entrapped in a poly(vinyl alcohol)-styrylpyridinium (PVA-SbQ) membrane crosslinked

Stefan Zimmermann; Doerte Fienbork; Albert W. Flounders; Dorian Liepmann

2004-01-01

98

Wafer characteristics via reflectometry  

DOEpatents

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Sopori, Bhushan L. (Denver, CO)

2010-10-19

99

Reciprocating Saw for Silicon Wafers  

NASA Technical Reports Server (NTRS)

Concept increases productivity and wafer quality. Cutting wafers from silicon ingots produces smooth wafers at high rates with reduced blade wear. Involves straight reciprocating saw blade and slight rotation of ingot between cutting strokes. Many parallel blades combined to cut many wafers simultaneously from ingot.

Morrison, A. D.; Collins, E. R., Jr.

1985-01-01

100

Wafer level reliability testing: An idea whose time has come  

NASA Technical Reports Server (NTRS)

Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

Trapp, O. D.

1987-01-01

101

Recent Developments in Microsystems Fabricated by the Liga-Technique  

NASA Technical Reports Server (NTRS)

As an example of microsystems fabricated by the LIGA-technique (x-ray lithography, electroplating and molding), three systems are described and characterized: a triaxial acceleration sensor system, a micro-optical switch, and a microsystem for the analysis of pollutants. The fabrication technologies are reviewed with respect to the key components of the three systems: an acceleration sensor, and electrostatic actuator, and a spectrometer made by the LIGA-technique. Aa micro-pump and micro-valve made by using micromachined tools for molding and optical fiber imaging are made possible by combining LIGA and anisotropic etching of silicon in a batch process. These examples show that the combination of technologies and components is the key to complex microsystems. The design of such microsystems will be facilitated is standardized interfaces are available.

Schulz, J.; Bade, K.; El-Kholi, A.; Hein, H.; Mohr, J.

1995-01-01

102

Thinning of PLZT ceramic wafers for sensor integration  

NASA Astrophysics Data System (ADS)

Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300?m. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10?m, the surface roughness was below 1nm in rms, and the flatness was better than ?/5.

Jin, Na; Liu, Weiguo

2010-08-01

103

1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics  

SciTech Connect

The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

Lorenz, Adam [1366 Technologies] [1366 Technologies

2013-08-30

104

RF W-band wafer-to-wafer transition  

Microsoft Academic Search

Multiwafer silicon designs must provide an avenue for electrical signals to flow from wafer to wafer. For this purpose, a two-layer electrical bond is proposed to provide electrical connection between two coplanar waveguides printed on the adjacent faces of two vertically stacked silicon wafers. In addition to serving as a versatile low-temperature thermocompression wafer bond, loss of approximately 0.1 dB

Katherine J. Herrick; Linda P. B. Katehi

2001-01-01

105

On the design and fabrication of metal molds in LIGA  

Microsoft Academic Search

Most previous research on electroplating in LIGA has been focused on electrodeposition of metal into high aspect ratio resist cavities. The process in which the metal grows up crossing the top of resist cavities has been largely neglected. In this process, various defects may occur. A typical defect is the hole- formation at the top of electroplated metal mold, especially

Yuhua Guo; Yangchao Tian; R. Du

2008-01-01

106

Investigation of the LIGA process to fabricate microchannel plates  

Microsoft Academic Search

This paper describes the development of microchannel plate prototypes with aspect ratios of 20:1 and a variety of microchannel geometries. The LIGA process is utilized to fabricate nickel molds up to 150 ?m in height with planarized surfaces. A novel application of spin-on glass is developed to obtain glass structures in Ni molds. A reverse electroplating is used to remove

Robin H. Liu; M. J. Vasile; Jost Goettert; David J. Beebe

1997-01-01

107

HMIC wafer level packaging  

Microsoft Academic Search

HMIC, an acronym for Heterolithic Microwave Integrated Circuits, is fundamentally a wafer level substrate which combines low, RF loss tangent glass with micromachined silicon to produce three dimensional circuitry with the capability to make RF, DC, and thermal vias as the device input and output. Using this technology both active and passive RF devices have been produced which have demonstrated

T. Boles; D. Hoag; M. Barter; R. Giacchino; P. Hogan; J. Goodrich

2009-01-01

108

HMIC wafer level packaging  

Microsoft Academic Search

HMIC, an acronym for heterolithic microwave integrated circuits, is fundamentally a wafer level substrate which combines low, RF loss tangent glass with micromachined silicon to produce three dimensional circuitry with the capability to make RF, DC, and thermal vias as the device input and output. Using this technology both active and passive RF devices have been produced which have demonstrated

T. Boles; D. Hoag; M. Barter; R. Giacchino; P. Hogan; J. Goodrich

2009-01-01

109

Etching Of Semiconductor Wafer Edges  

DOEpatents

A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

2003-12-09

110

Laser Wafering for Silicon Solar.  

National Technical Information Service (NTIS)

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire s...

B. Jared B. Sweatt T. A. Friedman

2011-01-01

111

Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter  

NASA Technical Reports Server (NTRS)

The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

Chen, C. P.; Leipold, M. H.

1984-01-01

112

Novel coupled-cavity TWT structure using two-step LIGA fabrication  

Microsoft Academic Search

In order to make millimeter-wave sources practical, improved fabrication methods are required. The use of Lithographie, Galvanoformung, Abformung; German acronym (LIGA) to fabricate a coupled-cavity traveling-wave tube (TWT) is presented. The proposed circuit design will focus on two-step LIGA fabrication and dual in-line ladder structure with a rectangular beam tunnel. The fabrication sequence of two-step LIGA is illustrated and the

Young-Min Shin; Gun-Sik Park; G. P. Scheitrum; B. Arfin

2003-01-01

113

Compact micropumping system based on LIGA fabricated microparts  

Microsoft Academic Search

This report presents design, fabrication and testing of a magnetically actuated microgear pumps based on the LIGA technology. These micropumps exhibit flow rates between 0.5 and 8.5ml\\/min and head pressures up to 100cm-H2O. Geometries are determined for an optimal magnetic coupling, resulting in a linear behavior of the flow rate versus rotation speed.

M. Matteucci; F. Pérennès; B. Marmiroli; P. Miotti; L. Vaccari; A. Gosparini; A. Turchet; E. Di Fabrizio

2006-01-01

114

Wafer-scale high-throughput ordered arrays of Si and coaxial Si/Si(1-x)Ge(x) wires: fabrication, characterization, and photovoltaic application.  

PubMed

We have developed a method combining lithography and catalytic etching to fabricate large-area (uniform coverage over an entire 5-in. wafer) arrays of vertically aligned single-crystal Si nanowires with high throughput. Coaxial n-Si/p-SiGe wire arrays are also fabricated by further coating single-crystal epitaxial SiGe layers on the Si wires using ultrahigh vacuum chemical vapor deposition (UHVCVD). This method allows precise control over the diameter, length, density, spacing, orientation, shape, pattern and location of the Si and Si/SiGe nanowire arrays, making it possible to fabricate an array of devices based on rationally designed nanowire arrays. A proposed fabrication mechanism of the etching process is presented. Inspired by the excellent antireflection properties of the Si/SiGe wire arrays, we built solar cells based on the arrays of these wires containing radial junctions, an example of which exhibits an open circuit voltage (V(oc)) of 650 mV, a short-circuit current density (J(sc)) of 8.38 mA/cm(2), a fill factor of 0.60, and an energy conversion efficiency (?) of 3.26%. Such a p-n radial structure will have a great potential application for cost-efficient photovoltaic (PV) solar energy conversion. PMID:21749059

Pan, Caofeng; Luo, Zhixiang; Xu, Chen; Luo, Jun; Liang, Renrong; Zhu, Guang; Wu, Wenzhuo; Guo, Wenxi; Yan, Xingxu; Xu, Jun; Wang, Zhong Lin; Zhu, Jing

2011-08-23

115

Wafer thinning for high-density, through-wafer interconnects  

NASA Astrophysics Data System (ADS)

Thinning of micromachined wafers containing trenches and cavities to realize through-chip interconnects is presented. Successful thinning of wafers by lapping and polishing until the cavities previously etched by deep reactive ion etching are reached is demonstrated. The possible causes of damage to the etched structures are investigated. The trapping of particles in the cavities and suitable cleaning procedures to address this issue are studied. The results achieved so far allow further processing of the thinned wafers to form through wafer interconnections by copper electroplating. Further improvement of the quality of thinned surfaces can be achieved by alternative cleaning procedures.

Wang, Lianwei; Visser, Cassan C. G.; de Boer, Charles R.; Laros, M.; van der Vlist, W.; Groeneweg, J.; Craciun, G.; Sarro, Pasqualina M.

2003-01-01

116

Augmented reality for wafer prober  

NASA Astrophysics Data System (ADS)

The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

Gilgenkrantz, Pascal

2011-02-01

117

Low temperature full wafer adhesive bonding of structured wafers  

Microsoft Academic Search

In this paper, we present a technology for void free low temperature full wafer adhesive bonding of structured wafers. Benzocyclobutene (BCB) is used as the intermediate bonding material. BCB bonds well with various materials and does not release significant amounts of by-products during the curing process. Thus void-free bond interfaces can be achieved. Cured BCB coatings have an excellent resistance

F. Niklaus; H. Andersson; P. Enoksson; G. Stemme

2001-01-01

118

Gettering Silicon Wafers with Phosphorus  

NASA Technical Reports Server (NTRS)

Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

Daiello, R. V.

1983-01-01

119

Cloning and Molecular Characterization of an Immunogenic LigA Protein of Leptospira interrogans  

PubMed Central

A clone expressing a novel immunoreactive leptospiral immunoglobulin-like protein A of 130 kDa (LigA) from Leptospira interrogans serovar pomona type kennewicki was isolated by screening a genomic DNA library with serum from a mare that had recently aborted due to leptospiral infection. LigA is encoded by an open reading frame of 3,675 bp, and the deduced amino acid sequence consists of a series of 90-amino-acid tandem repeats. A search of the NCBI database found that homology of the LigA repeat region was limited to an immunoglobulin-like domain of the bacterial intimin binding protein of Escherichia coli, the cell adhesion domain of Clostridium acetobutylicum, and the invasin of Yersinia pestis. Secondary structure prediction analysis indicates that LigA consists mostly of beta sheets with a few alpha-helical regions. No LigA was detectable by immunoblot analysis of lysates of the leptospires grown in vitro at 30°C or when cultures were shifted to 37°C. Strikingly, immunohistochemistry on kidney from leptospira-infected hamsters demonstrated LigA expression. These findings suggest that LigA is specifically induced only in vivo. Sera from horses, which aborted as a result of natural Leptospira infection, strongly recognize LigA. LigA is the first leptospiral protein described to have 12 tandem repeats and is also the first to be expressed only during infection. Thus, LigA may have value in serodiagnosis or as a protective immunogen in novel vaccines.

Palaniappan, Raghavan U. M.; Chang, Yung-Fu; Jusuf, S. S. D.; Artiushin, S.; Timoney, John F.; McDonough, Sean P.; Barr, Steve C.; Divers, Thomas J.; Simpson, Kenneth W.; McDonough, Patrick L.; Mohammed, Hussni O.

2002-01-01

120

Fabrication of Compound Refractive X-ray Lenses Using LIGA Process and Performance Tests  

SciTech Connect

Recent advances of X-ray microscopy technology enable the visualization of some micro/nano-scale objects which optical microscopy and electron microscopy cannot be used to observe. The X-ray microscopy can be applied to observe the internal structure of a thicker sample than the electron microscopy can, and its spatial resolution is higher than that of the optical microscopy. Moreover, it has a powerful element specific imaging ability. For further improving the X-ray microscope, it is indispensable to make X-ray optics for focusing X-rays more effectively. Recently, various X-ray lenses such as diffraction lenses of FZP(Fresnel zone plate) and spatter-sliced FZT, total reflection lenses of K-B(Kirkpatrick-Baez) mirror and Wolter mirror, and refractive lens of CRL(compound refractive lens) were introduced. Compared with the other types of lenses, CRL is easy to fabricate and handle. In this study, we designed and fabricated various types of CRLs using LIGA(LIthographie, Galvanoformung, Abformtechnik) process, and used PMMA(Poly(methyl methacrylate)) material as the material of CRL. Their performances are tested with varying parameters such as parabolic/kinoform shape, radius of curvature, wall thickness between adjacent lenses, and width of lenses. The performance tests were carried out by using a simple synchrotron X-ray imaging method. The tests results revealed that hard x-rays could be condensed well by the CRL of PMMA material at the focal point we expect We captured sample images one-dimensionally magnified by CRLs. Furthermore, we found which parameter is more effective for enhancing focus efficiency and which parameter should be considered more carefully in the fabrication process of LIGA.

Lee, Jin Pyoung [School of Environmental Science and Engineering, POSTECH, Pohang, 790-784 (Korea, Republic of); Kim, Guk Bae [Dept. of Mechanical Engineering, POSTECH, Pohang, 790-784 (Korea, Republic of); Kim, Jong Hyun; Chang, Suk Sang [Pohang Accelerator Laboratory, POSTECH, Pohang, 790-784 (Korea, Republic of); Lee, Sang Joon [Dept. of Mechanical Engineering, POSTECH, Pohang, 790-784 (Korea, Republic of); School of Environmental Science and Engineering, POSTECH, Pohang, 790-784 (Korea, Republic of)

2007-01-19

121

Enhanced adhesion for LIGA microfabrication by using a buffer layer  

DOEpatents

The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

Bajikar, Sateesh S. (San Jose, CA); De Carlo, Francesco (Darien, IL); Song, Joshua J. (Naperville, IL)

2001-01-01

122

MEMS Wafer-level Packaging Technology Using LTCC Wafer  

NASA Astrophysics Data System (ADS)

This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature co-fired ceramic (LTCC) wafer, in which multi-layer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of micro electro mechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (-40°C×30min/+125°C×30min) by diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection methods; The electrical connection is established by porous Au bumps, which are a part of Au vias exposed in wet-etched cavities on the LTCC wafer. 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

Mohri, Mamoru; Esashi, Masayoshi; Tanaka, Shuji

123

Characterization of Sidewall and Planar Surfaces of Electroformed LIGA Parts  

SciTech Connect

The nature of surfaces and the way they interact with each other during sliding contact can have a direct bearing on the performance of a microelectromechanical (MEMS) device. Therefore, a study was undertaken to characterize the surfaces of LIGA fabricated Ni and Cu components. Sidewall and planar surfaces were examined by scanning electron microscopy (SEM) and atomic force microscopy (AFM). Surface roughness was quantified using the AFM. Post-processing (e.g. lapping, removal of polymer film) can profoundly influence the morphology of LIGA components. Edge rounding and smearing of ductile materials during lapping can result in undesirable sidewall morphologies. By judicious selection of AFM scan sizes, the native roughness ({approximately}10 nm RMS) can be distinguished from that arising due to post processing, e.g. scratches, debris, polymer films. While certain processing effects on morphology such as those due to lapping or release etch can be controlled, the true side wall morphology appears to be governed by the morphology of the polymer mold or by the electroforming process itself, and may be much less amenable to modification.

PRASAD,SOMURI V.; HALL,AARON C.; DUGGER,MICHAEL T.

2000-10-01

124

Wafer Replacement Cluster Tool (Presentation);  

SciTech Connect

This presentation on wafer replacement cluster tool discusses: (1) Platform for advanced R and D toward SAI 2015 cost goal--crystal silicon PV at area costs closer to amorphous Si PV, it's 15% efficiency, inexpensive substrate, and moderate temperature processing (<800 C); (2) Why silicon?--industrial and knowledge base, abundant and environmentally benign, market acceptance, and good efficiency; and (3) Why replace wafers?--expensive, high embedded energy content, and uses 50-100 times more silicon than needed.

Branz, H. M.

2008-04-01

125

Advanced Modelling of Silicon Wafer Solar Cells  

NASA Astrophysics Data System (ADS)

Modelling of solar cells today is general practice in research and widely-used in industry. Established modelling software is typically limited to one dimension and/or to small scales. Additionally, novel effects, like, e.g., the use of diffractive structures or luminescent materials, are not established. In this paper we discuss how the combination of different modelling techniques can be used to overcome these limitations. In this context two examples are presented. The first example concerns the combination of the open source simulation software PC1D with circuit modelling to investigate the effect of local shunts on the global characteristics of a silicon wafer solar cell. For the investigated example (4.5 cm2 cell area) we find that a local point shunt reduces the solar cell efficiency by 4% relative. The second example concerns the modelling of diffractive gratings for thin silicon wafer solar cells. For this purpose, we use the rigorous coupled wave analysis to simulate Sentaurus technical computer-aided design (TCAD) is combined with the rigorous coupled wave analysis, a method to solve Maxwell's equations for periodic structures. Here we show that a grating can be used to improve the absorption in a thin silicon wafer solar cell considerably.

Peters, Marius; Fajun, Ma; Siyu, Guo; Hoex, Bram; Blaesi, Benedikt; Glunz, Stefan; Aberle, Armin; Luther, Joachim

2012-10-01

126

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.  

PubMed

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

2014-08-15

127

Design and Reliability in Wafer Level Packaging  

Microsoft Academic Search

Wafer Level Packaging (WLP) has the highest potential for future single chip packages because the WLP is intrinsically a chip size package. The package is completed directly on the wafer then singulated by dicing for the assembly. All packaging and testing operations of the dice are replaced by whole wafer fabrication and wafer level testing. Therefore, it becomes more cost-effective

Xuejun Fan; Qiang Han

2008-01-01

128

Spinner For Etching Of Semiconductor Wafers  

NASA Technical Reports Server (NTRS)

Simple, inexpensive apparatus coats semiconductor wafers uniformly with hydrofluoric acid for etching. Apparatus made in part from small commercial electric-fan motor. Features bowl that collects acid. Silicon wafer placed on platform and centered on axis; motor switched on. As wafer spins, drops of hydrofluoric acid applied from syringe. Centrifugal force spreads acid across wafer in fairly uniform sheet.

Lombardi, Frank

1989-01-01

129

Selective area growth of InP in shallow trench isolation on large scale Si(001) wafer using defect confinement technique  

NASA Astrophysics Data System (ADS)

Heterogeneous integration of III-V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III-V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III-V virtual substrates on large-scale Si substrates.

Merckling, C.; Waldron, N.; Jiang, S.; Guo, W.; Richard, O.; Douhard, B.; Moussa, A.; Vanhaeren, D.; Bender, H.; Collaert, N.; Heyns, M.; Thean, A.; Caymax, M.; Vandervorst, W.

2013-07-01

130

Wafer bonding for MEMS and CMOS integration  

NASA Astrophysics Data System (ADS)

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.

Dragoi, V.; Pabo, E.; Burggraf, J.; Mittendorfer, G.

2011-05-01

131

Two-dimensional modeling of nickel electrodeposition in LIGA microfabrication.  

SciTech Connect

Two-dimensional processes of nickel electrodeposition in LIGA microfabrication were modeled using the finite-element method and a fully coupled implicit solution scheme via Newtons technique. Species concentrations, electrolyte potential, flow field, and positions of the moving deposition surfaces were computed by solving the species-mass, charge, and momentum conservation equations as well as pseudo-solid mesh-motion equations that employ an arbitrary Lagrangian-Eulerian (ALE) formulation. Coupling this ALE approach with repeated re-meshing and re-mapping makes it possible to track the entire transient deposition processes from start of deposition until the trenches are filled, thus enabling the computation of local current densities that influence the microstructure and functional/mechanical properties of the deposit.

Evans, Gregory Herbert (Sandia National Laboratories, Livermore, CA); Chen, Ken Shuang

2003-07-01

132

Fabrication of Spiral Micro-Coil Utilizing LIGA Process  

NASA Astrophysics Data System (ADS)

We developed a method for fabricating a three-dimensional spiral micro-inductor with high inductance using the LIGA process. The spiral inductor created had a diameter of 0.5mm, and a length of 1mm. The width of the spiral line was 10µm, the pitch was 20µm, and the number of turns was 15. It was made of plated copper. The master was a brass round bar coated with PMMA resist. Deep X-ray lithography was employed to fabricate a master for a metallic mold at the NewSUBARU synchrotron radiation facility, University of Hyogo. The inductor core was made of resin by injection molding. It has a spiral micro flute on the surface. We chose the worm injection molding technique in order to avoid the parting line across the spiral line. The worm injection molding was the method─for demolding the work such as that used in loosening a screw.

Shimada, Osamu; Kusumi, Shinji; Mekaru, Harutaka; Sato, Noriaki; Shimizu, Masami; Yamashita, Michiru; Hattori, Tadashi

133

Wafer characteristics via reflectometry and wafer processing apparatus and method  

DOEpatents

An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

Sopori, Bhushan L. (Denver, CO)

2007-07-03

134

Nano-particle laser removal from silicon wafers  

NASA Astrophysics Data System (ADS)

A laser shock cleaning (LSC) technique as a new dry cleaning methodology has been applied to remove micro and nano-scale inorganic particulate contaminants. Shock wave is generated in the air just above the wafer surface by focusing intensive laser beam. The velocity of shock wave can be controlled to 10,000 m/sec. The sub-micron sized silica and alumina particles are attempted to remove from bare silicon wafer surfaces. More than 95% of removal efficiency of the both particles are carried out by the laser-induced airborne shock waves. In the final, a removal of nano-scale slurry particles from real patterned wafers are successfully demonstrated by LSC after chemical-mechanical polishing (CMP) process.

Lee, J. M.; Cho, S. H.; Kim, T. H.; Park, Jin-Goo; Busnaina, Ahmed A.

2003-11-01

135

Can LigaSure™ be used to perform sleeve gastrectomy? - Tensile strength and histological changes.  

PubMed

Abstract Introduction: LigaSure™ was developed as an alternative to suture ligatures, hemoclips and staplers for ligating vessels and tissue bundles. The aim of the present study was to determine whether LigaSure can be used as a welding instrument in the performance of laparoscopic sleeve gastrectomy. Material and methods: Gastric specimens were assigned into four groups. Group 1 - specimens remained with the staple line intact. Group 2 - the staple line was oversewn. Group 3 - the staple line was resected with LigaSure. Group 4 - staple line was resected with LigaSure and the seal was oversewn. In all specimens the pressure tolerance was assessed using a portable sensor. Results: In group 1 the leak pressure was 34.7 ± 11.7 whereas in group 2 specimens the pressure increased three-fold (101.9 ± 21.4). The LigaSure seal alone (group 3) achieved a mean pressure of 13.7 mmHg. However, in group 4 there was an exponential increase on their burst strength up to 142 mmHg (p = 0.0005). Conclusion: According to our results, LigaSure could be used to perform laparoscopic sleeve gastrectomy with reduction of staple-line bleeding and, when reinforced with a running suture, it achieves a strength that approaches that of staples plus oversewing. PMID:24359311

Lopez, Julio; Vilallonga, Ramon; Targarona, Eduardo M; Balague, Carmen; Enriquez, Lenin; Rivera, Ramon; Balibrea, Jose M; Perez-Ochoa, Francisco; Rodriguez, Karime; Baeza, Miguel; Reyes, Arturo

2014-06-01

136

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Vosen, S.R.

1999-07-27

137

High-order wafer alignment in manufacturing  

NASA Astrophysics Data System (ADS)

Requirements for ever tightening overlay control are driving improvements in tool set up and matching procedures, APC processes, and wafer alignment techniques in an attempt to address both systematic and non systematic sources of overlay error. Thermal processes used in semiconductor manufacturing have been shown to have drastic and unpredictable impacts on lithography overlay control. Traditional linear alignment can accommodate symmetric and linearly uniform wafer distortions even if these defects vary in magnitude wafer to wafer. However linear alignment cannot accommodate asymmetric wafer distortions caused by variations in film stresses and rapid thermal processes. Overlay improvement techniques such as Corrections per Exposure can be used to compensate for known systematic errors. However, systematic corrections applied on a lot by lot basis cannot account for variations in wafer to wafer grid distortions caused by semiconductor processing. With High Order Wafer Alignment, the sample size of wafer alignment data is significantly increased and modeled to correct for process induced grid distortions. HOWA grid corrections are calculated and applied for each wafer. Improved wafer to wafer overlay performance was demonstrated. How HOWA corrections propagate level to level in a typical alignment tree as well as the interaction of mixing and matching high order wafer alignment with traditional linear alignment used on less overlay critical levels. This evaluation included the evaluating the impact of overlay offsets added by systematic tool matching corrections, product specific corrections per exposure and 10 term APC process control.

Pike, Michael; Felix, Nelson; Menon, Vinayan; Ausschnitt, Christopher; Wiltshire, Timothy; Meyers, Sheldon; Kim, Won; Minghetti, Blandine

2012-03-01

138

Measurements of Slurry Film Thickness and Wafer Drag during CMP  

Microsoft Academic Search

d Intel Corporation, Santa Clara, California 95052-8119, USA Chemical mechanical planarization ~CMP! is a process widely used for the manufacture of silicon integrated circuits. In this work, we measured the thickness of the slurry film between the wafer and the pad during polish while simultaneously measuring the frictional drag. All experiments are performed on a 1:2 scale laboratory tabletop rotary

J. Lu; C. Rogers; V. P. Manno; A. Philipossian; S. Anjur; M. Moinpourd

2004-01-01

139

Development of Magnesium Wafer Cells.  

National Technical Information Service (NTIS)

The purpose of this development contract is to design a practical magnesium wafer battery which performs satisfactorily after storage for various periods at ambient temperatures up to 160F. The initial phase of development includes the design of a cell an...

T. S. Hungate

1966-01-01

140

Development of Magnesium Wafer Cells.  

National Technical Information Service (NTIS)

This paper discusses the development of magnesium wafer cells. The principal physical condition causing constructional difficulties in both the 1-3/4 X 3-1/4 inch and 1-1/8 X 1-1/8 inch cell size batteries was the evolution of gas during storage and disch...

L. W. Eaton

1968-01-01

141

Wafer level packaging of MEMS  

Microsoft Academic Search

Wafer level packaging methods of MEMS are described. These play important roles to reduce cost and to improve reliability. MEMS structures on silicon chips are encapsulated with bonded caps or with shells fabricated by surface micromachining, and electrical interconnections are made from the cavity. Vacuum packaging methods are also described.

M. Esashi

2009-01-01

142

Dynamic wafer handling process in semiconductor manufacturing  

Microsoft Academic Search

In semiconductor manufacturing, wafers are transferred using wafer handling robots. Typically a pick-measure-place method is used to transfer wafers accurately between stations. The measurement step is performed using an aligner, which is time-consuming. To increase wafer transfer efficiency, it is desirable to speed up the measurement or place it in parallel with other operations. Hence two optic sensors are installed

Heping Chen; Ben Mooring; Harold Stern

2011-01-01

143

NREL Core Program; Session: Wafer Silicon (Presentation)  

SciTech Connect

This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

Wang, Q.

2008-04-01

144

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Technical Reports Server (NTRS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

145

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Astrophysics Data System (ADS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-02-01

146

Wafer-to-Wafer Alignment for Three-Dimensional Integration: A Review  

Microsoft Academic Search

This paper presents a review of the wafer-to-wafer alignment used for 3-D integration. This technology is an im- portant manufacturing technique for advanced microelectronics and microelectromechanical systems, including 3-D integrated circuits, advanced wafer-level packaging, and microfluidics. Commercially available alignment tools provide prebonding wafer-to-wafer misalignment tolerances on the order of 0.25 µm. However, better alignment accuracy is required for increasing demands

Sang Hwui Lee; Kuan-Neng Chen; James Jian-Qiang Lu

2011-01-01

147

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress  

NASA Astrophysics Data System (ADS)

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Brunner, Timothy A.; Menon, Vinayan C.; Wong, Cheuk Wun; Gluschenkov, Oleg; Belyansky, Michael P.; Felix, Nelson M.; Ausschnitt, Christopher P.; Vukkadala, Pradeep; Veeraraghavan, Sathish; Sinha, Jaydeep K.

2013-10-01

148

An aluminum resist substrate for microfabrication by LIGA.  

SciTech Connect

Resist substrates used in the LIGA process must provide high initial bond strength between the substrate and resist, little degradation of the bond strength during x-ray exposure, acceptable undercut rates during development, and a surface enabling good electrodeposition of metals. Additionally, they should produce little fluorescence radiation and give small secondary doses in bright regions of the resist at the substrate interface. To develop a new substrate satisfying all these requirements, we have investigated secondary resist doses due to electrons and fluorescence, resist adhesion before exposure, loss of fine features during extended development, and the nucleation and adhesion of electrodeposits for various substrate materials. The result of these studies is a new anodized aluminum substrate and accompanying methods for resist bonding and electrodeposition. We demonstrate successful use of this substrate through all process steps and establish its capabilities via the fabrication of isolated resist features down to 6 {micro}m, feature aspect ratios up to 280 and electroformed nickel structures at heights of 190 to 1400 {micro}m. The minimum mask absorber thickness required for this new substrate ranges from 7 to 15 {micro}m depending on the resist thickness.

Kelly, James J.; Boehme, Dale R.; Hauck, Cheryl A. (Lawrence Berkeley National Laboratory, Berkeley, CA); Yang, Chu-Yeu Peter; Hunter, Luke L.; Griffiths, Stewart K.; McLean, Dorrance E.; Aigeldinger, Georg; Hekmaty, Michelle A.; Hachman, John T.; Losey, Matthew W.; Skala, Dawn M.; Korellis, John S.; Friedmann, Thomas Aquinas (Sandia National Laboratories, Albuquerque, NM); Yang, Nancy Y. C.; Lu, Wei-Yang

2005-04-01

149

LIGA-fabricated compact mm-wave linear accelerator cavities.  

SciTech Connect

Millimeter-wave rf cavities for use in linear accelerators, free-electron lasers, and mm-wave undulatory are under development at Argonne National Laboratory. Typical cavity dimensions are in the 1000 mm range, and the overall length of the accelerator structure, which consists of 30-100 cavities, is about 50-100 mm. An accuracy of 0.2% in the cavity dimensions is necessary in order to achieve a high Q-factor of the cavity. To achieve this these structures are being fabricated using deep X-ray lithography, electroforming, and assembly (LIGA). The first prototype cavity structures are designed for 108 GHz and 2p/3-mode operation. Input and output couplers are integrated with the cavity structures. The cavities are fabricated on copper substrates by electroforming copper into 1-mm-thick PMMA resists patterned by deep x-ray lithography and polishing the copper down to the desired thickness. These are fabricated separately and subsequently assembled with precision spacing and alignment using microspheres, optical fibers, or microfabricated spacers/alignment pieces. Details of the fabrication process, alignment, and assembly work are presented in here.

Song, J.J.; Bajikar, S.S.; DeCarlo, F.; Kang, Y.W.; Kustom, R.L.; Mancini, D.C.; Nassiri, A.; Lai, B.; Feinerman, A.D.; White, V.

1998-03-23

150

Comparing Team Performance of the English Premier League, Serie A, and La Liga for the 2008-2009 Season  

Microsoft Academic Search

Three of the most celebrated football leagues in the world include the English Premier League (EPL), Italy’s Serie A, and Spain’s La Liga. To date, little football research has been conducted that attempts to determine why these leagues are so successful. What is it that the EPL, La Liga, and Serie A do that fosters such a high caliber of

Joel Oberstone

2011-01-01

151

The LIGA technique-A novel concept for microstructures and the combination with Si-technologies by injection molding  

Microsoft Academic Search

The LIGA technique originally developed to fabricate separation nozzles for the enrichment of uranium has been expanded into a universal technology for the fabrication of microstructures with high aspect ratio and free lateral shaping. The LIGA process consists of three basic process steps: deep-etch lithography by means of synchrotron radiation, electroforming, and plastic molding. The choice of materials ranges from

W. Menz; W. Bacher; M. Harmening; A. Michel

1991-01-01

152

Wafer Manufacturing and Slicing Using Wiresaw  

NASA Astrophysics Data System (ADS)

Wafer manufacturing (or wafer production) refers to a series of modern manufacturing processes of producing single-crystalline or poly-crystalline wafers from crystal ingot (or boule) of different sizes and materials. The majority of wafers are single-crystalline silicon wafers used in microelectronics fabrication although there is increasing importance in slicing poly-crystalline photovoltaic (PV) silicon wafers as well as wafers of different materials such as aluminum oxide, lithium niobate, quartz, sapphire, III-V and II-VI compounds, and others. Slicing is the first major post crystal growth manufacturing process toward wafer production. The modern wiresaw has emerged as the technology for slicing various types of wafers, especially for large silicon wafers, gradually replacing the ID saw which has been the technology for wafer slicing in the last 30 years of the 20th century. Modern slurry wiresaw has been deployed to slice wafers from small to large diameters with varying wafer thickness characterized by minimum kerf loss and high surface quality. The needs for slicing large crystal ingots (300 mm in diameter or larger) effectively with minimum kerf losses and high surface quality have made it indispensable to employ the modern slurry wiresaw as the preferred tool for slicing. In this chapter, advances in technology and research on the modern slurry wiresaw manufacturing machines and technology are reviewed. Fundamental research in modeling and control of modern wiresaw manufacturing process are required in order to understand the cutting mechanism and to make it relevant for improving industrial processes. To this end, investigation and research have been conducted for the modeling, characterization, metrology, and control of the modern wiresaw manufacturing processes to meet the stringent precision requirements of the semiconductor industry. Research results in mathematical modeling, numerical simulation, experiments, and composition of slurry versus wafer quality are presented. Summary and further reading are also provided.

Kao, Imin; Chung, Chunhui; Moreno Rodriguez, Roosevelt

153

Development of a 3-Dimensional LIGA Process and Application to Fabricate a Spiral Microcoil  

NASA Astrophysics Data System (ADS)

LIGA process has been developed in the 2.5-dimensional world. We introduced new technologies of a 3D X-ray lithography and a worm injection molding with an unscrewing demolding mechanism, and succeeded in the deployment of a three- dimensional LIGA process. Furthermore, it succeeded to fabricate a spiral microcoil using 3D-LIGA process and a metallization technique combined flat and smooth electroplating and isotropic chemical etching. A diameter of the microcoil was 0.5 mm and the length was 1 mm. The width of coil lines was 10 ?m, and the pitch was 20 ?m. Also the characteristics as an inductor of this microcoil is such that the inductance and the quality factor at the frequency of 1 GHz was 91 nH and 5.8, respectively.

Mekaru, Harutaka; Kusumi, Shinji; Sato, Noriaki; Shimizu, Masami; Yamashita, Michiru; Shimada, Osamu; Hattori, Tadashi

154

Does LigaSure™ reduce fluid drainage in axillary dissection? A randomized prospective clinical trial  

PubMed Central

Background: Axillary lymph node dissection (ALND) is an integral part of breast cancer treatment. It is required in about 40–50% of patients. The placement of a drain in the axilla after an operation is current surgical practice. Short surgical stay programmes increase operating efficiency and reduce medical care costs, without compromising quality of care. LigaSure™ is a new haemostatic device that uses bipolar energy to seal vessels. The aim of this study is to determine whether axillary dissection with LigaSure™ reduces the time of wound drainage, the duration of surgical intervention and the volume of drainage after treatment. Patients and methods: This study is a prospective randomized controlled trial. A total of 100 women with breast cancer who needed axillary dissection were randomized into the LigaSure™ or conventional axillary dissection group. Levels I to III lymph node dissection was performed. A closed suction drain was always placed in the axilla and removed after 6–8 days or when fluid amount was <60 cc in the previous 24 hours. Results: There were no significant differences between the two groups when considering the duration of surgical procedure: average duration was 70.7 ± 24.66 minutes for LigaSure™ patients, while in the conventional dissection group the mean was 70.6 ± 22.47 minutes (p=0.98). Total amount of drained fluid was 624.49 cc in the LigaSure™ axillary dissection group and 792.96 in the conventional ALND group; this difference did not achieve statistical significance (p=0.09); the duration of draining was also similar, with no statistical difference (p=0.15). Conclusions: The present study did not show clear advantages in LigaSure™ use for ALND, although it represents a good haemostatic device, especially in abdominal surgery.

Antonio, M; Pietra, T; Domenico, LG; Massimo, D; Ignazio, R; Antonio, N; Luigi, C

2007-01-01

155

A MEMS-Based Micro Biopsy Actuator for the Capsular Endoscope Using LiGA Process  

NASA Astrophysics Data System (ADS)

This paper presents a LiGA (German acronym for LIthografie, Galvanoformung, Abformung) based micro biopsy actuator for the capsular endoscope. The proposed fabricated actuator aims to extract sample tissues inside small gastric intestines, that cannot be reached by conventional biopsy. The actuator size is 10 mm in diameter and 1.8 mm in length. The mechanism is of a slider-crank type. The actuator consists of trigger, rotational module, and micro biopsy tool. The core components are fabricated using the LiGA process, for overcoming the limitations in accuracy of conventional precision machining.

Park, Sunkil; Koo, Kyo-In; Kim, Gil-Sub; Bang, Seoung Min; Song, Si Young; Chu, Chong Nam; Jeon, Doyoung; Cho, Dongil ``Dan''

2007-01-01

156

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging  

NASA Astrophysics Data System (ADS)

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

2013-03-01

157

Low temperature, high strength, wafer-to-wafer bonding  

SciTech Connect

This paper reports on high strength bonds which can be formed between portions of silicon wafer coated with reflowed BPSG at temperatures as low as 160[degrees]C. Both a novel modified cantilever beam analysis, and crude physical methods attest to the strength of the bonds formed. Strong bonds between thermal oxides also have been observed, indicating that neither boron nor phosphorous are essential to the process. Preparation cleanliness may be the key to low temperature, high strength bonding,. Recent work in the glass sol-gel area supports the hypothesis that this process is the result of a low temperature condensation reaction.reaction.

Fleming, J.G.; Roherty-Osmun, E.; Godshall, N.A. (Sandia National Labs., Albuquerque, NM (United States))

1992-11-01

158

Thin film effects in ultrasonic wafer thermometry  

Microsoft Academic Search

We use an ultrasonic technique where the temperature dependence of lowest order anti-symmetric Lamb wave velocity in the silicon wafer is utilized for in-situ temperature measurement in the 20-1000°C range. In almost all wafer processing steps, one or more layers of thin films are present on the wafers. The effects of these films on temperature sensitivity is investigated. A theoretical

F. L. Degertekin; J. Pei; B. V. Honein; B. T. Khuri-Yakub; K. C. Saraswat

1994-01-01

159

Metal Enhanced Fluorescence on Silicon Wafer Substrates  

PubMed Central

We report on the fluorescence enhancement induced by silver island film (SIF) deposited on a silicon wafer. The model immunoassay was studied on silvered and unsilvered wafers. The fluorescence brightness of Rhodamine Red X increased about 300% on the SIF, while the lifetime was reduced by several fold and the photostability increased substantially. We discuss potential uses of silicon wafer substrates in multiplex assays in which the fluorescence is enhanced due to the SIF, and the multiplexing is achieved by using micro transponders.

Gryczynski, I.; Matveeva, E.G.; Sarkar, P.; Bharill, S.; Borejdo, J.; Mandecki, W.; Akopova, I.; Gryczynski, Z.

2008-01-01

160

Performance Evaluations of Ceramic Wafer Seals  

NASA Technical Reports Server (NTRS)

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

161

The hardness assurance wafer probe - HAWP  

NASA Astrophysics Data System (ADS)

Complete radiation sensitivity assessments of integrated circuits can now be performed at the wafer level using a new system, the Hardness Assurance Wafer Probe, HAWP. This system utilizes a pulsed Nd:YAG infrared laser impinging on the backside of the wafer to evaluate the transient behavior of the circuits. A low energy X ray source collimated to a single die site actually performs total dose irradiations. Finally, special electrical measurements are used to enable a prediction of the neutron sensitivity of bipolar devices. The HAWP System is described and correlations of wafer probe results to conventional radiation tests for a digital part type are provided.

King, E. E.; Tettemer, G. L.; Linderman, P. B.; Micheletti, P. E.

1983-12-01

162

MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads  

DOEpatents

In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

2013-12-03

163

The LIGA technique and its potential for microsystems-a survey  

Microsoft Academic Search

The LIGA technique, which is being developed at the Research Center Karlsruhe, offers the possibility to manufacture microstructures with arbitrary lateral geometry, lateral dimensions down to below 1 ?m and aspect ratios up to 500 from a variety of materials (metals, plastics, and ceramics). The basic steps of X-ray lithography, electroplating, and plastic molding, are briefly described. Examples of applications

Walter Bacher; W. Menz; J. Mohr

1995-01-01

164

Dynamic determination of Young's modulus of electroplated nickel used in LIGA technique  

Microsoft Academic Search

Mechanical properties of materials involved in the fabrication of new microactuators have to be well characterized in order to be used in CAD and for the simulation of Microsystems. To achieve that goal, we present a study of the Young's modulus E of electroplated nickel used in the LIGA technique. This mechanical parameter was obtained by the analysis of vibration

H Majjad; S Basrour; P Delobelle; M Schmidt

1999-01-01

165

Fabrication of 3D High Aspect Ratio Micro-Fluidic Components Using Laser Machining and LIGA  

Microsoft Academic Search

The fabrication of a microdevice often requires the combination of several techniques in its processing sequence. This allows for the benefits of individual techniques to fabricate an optimised product. In this paper, we present a complementary process involving laser micromachining and LIGA for the fabrication of a microflask. Examples of the benefits of this tandem include the removal of resist

Richard L. Barber; Muralidhar Ghantasala; Terence W. Turney; Erol Harvey

166

Strength of Si wafers with microcracks: A theoretical model  

Microsoft Academic Search

Wafer breakage is a major problem in the photovoltaic industry and becomes more serious as the industry attempts to use thinner wafers. It is well established that the poor strength of PV wafers is primarily due to the presence of residual microcracks, which are generated by cutting and wafering procedures and are not removed by subsequent etching of the wafers.

Przemyslaw Rupnowski; Bhushan Sopori

2008-01-01

167

Characterization of 300 mm silicon-polished and EPI wafers  

Microsoft Academic Search

Maturity of 300 mm polished wafers and early epi wafers were evaluated in respects of particles, flatness, metal contamination, and epitaxy thickness. Data of 300 mm polished wafers showed encouraging characteristics comparable to state-of-the-art 200 mm prime wafers. Preliminary characterization of 300 mm epi wafers revealed that dominant localized light scatterers (LLS) with sizes more than 1 ?m were epitaxy

Steven Shih; Chi Au; Zach Yang; Troy Messina; Randal K. Goodall; Howard R. Huff

1999-01-01

168

Preparation and Characterization of PZT Wafers  

NASA Astrophysics Data System (ADS)

Piezoelectric materials have recently attracted a lot of attention for ultrasonic structural health monitoring (shm) in aerospace, defence and civilian sectors, where they can act as both actuators and sensors. Incidentally, piezoelectric materials in the form of wafers (pwas-piezoelectric wafer active sensor, approx. 5-10 mm square and 0.2-0.3 mm thickness) are inexpensive, non intrusive and non-resonant wide band devices that can be surface-mounted on existing structures, inserted between the layers of lap joints or embedded inside composite materials. The material of choice for piezoelectric wafers is lead zirconate titanate (PZT) of composition close to morphotropic phase boundary [pb(zr0.52 ti0.48)o3]. However, an excess pbo is normally added to pzt as a densification aid and also to make up for the lead loss during high temperature sintering. Hence, it is of paramount importance to know how the shift of the lead content from the morphotropic composition affects the piezoelectric and mechanical properties of the sintered wafers, keeping in view the importance of mechanical properties of wafers in shm. In the present study, we observed that with the increase in the lead content of the sintered wafers, the dielectric and piezoelectric constants decreased. However, the elastic modulus, hardness and fracture toughness of the wafers increased with increasing lead content in the composition. Hence, the lead content in the sintered wafers should be optimized to get acceptable piezoelectric and mechanical

Seal, A.; Rao, B. S. S. Chandra; Kamath, S. V.; Sen, A.; Maiti, H. S.

2008-07-01

169

Wafer-Level ANA Calibrations at NIST  

Microsoft Academic Search

The National Institute of Standards and Technology has begun a program supporting on-wafer scattering parameter measurements. In contrast to many previous NIST endeavors, this program seeks to transfer methodology into industrial measurement laboratories. The subject of this paper is the development of calibration techniques and algorithms, rather than physical standards, for the measurement of on-wafer scattering parameters. In particular, we

Roger Marks; Kurt Phillips

1989-01-01

170

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs  

Microsoft Academic Search

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and\\/or burn-in parts in wafer form. After the parts are

Eugene M. Chow; David K. Fork; Christopher L. Chua; Koenraad Van Schuylenbergh; Thomas Hantschel

2009-01-01

171

Switchable static friction of piezoelectric composite--silicon wafer contacts  

NASA Astrophysics Data System (ADS)

The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and a silicon wafer counter surface rests solely on the matrix region of the piezocomposite surface. When actuated, the piezoelectric ceramic fibers protrude from the surface and the wafer rests solely on these protrusions. A threefold decrease in engineering static friction coefficient upon actuation of the piezocomposite was observed: from ?* = 1.65 to ?* = 0.50. These experimental results could be linked to the change in contact surface area and roughness using capillary adhesion theory, which relates the adhesive force to the number and size of the contacting asperities for the different surface states.

van den Ende, D. A.; Fischer, H. R.; Groen, W. A.; van der Zwaag, S.

2013-04-01

172

Development of megasonic cleaning for silicon wafers  

NASA Technical Reports Server (NTRS)

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Mayer, A.

1980-01-01

173

Automated array assembly task in-depth study of silicon wafer surface texturizing  

NASA Technical Reports Server (NTRS)

Several aspects of silicon wafer surface texturizing were studied. A low cost cleaning method that utilizes recycled Freon in an ultrasonic vapor degreaser to remove organic and inorganic contaminants from the surface of silicon wafers as received from silicon suppliers was investigated. The use of clean dry air and high throughout wafer batch drying techniques was shown to lower the cost of wafer drying. A two stage texturizing process was examined for suitability in large scale production. Also, an in-depth gettering study with the two stage texturizing process was performed for the enhancement of solar cell efficiency, minimization of current versus voltage curve dispersion, and improvement in process reproducibility. The 10% efficiency improvement goal was exceeded for the near term implementation of flat plate photovoltaic cost reduction.

Jones, G. T.; Rhee, S. S.

1979-01-01

174

Optical properties of LiGaS(2): an ab initio study and spectroscopic ellipsometry measurement.  

PubMed

Electronic and optical properties of lithium thiogallate crystal, LiGaS(2), have been investigated by both experimental and theoretical methods. The plane-wave pseudopotential method based on DFT theory has been used for band structure calculations. The electronic parameters of Ga 3d orbitals have been corrected by the DFT+U methods to be consistent with those measured with x-ray photoemission spectroscopy. Evolution of optical constants of LiGaS(2) over a wide spectral range was determined by developed first-principles theory and dispersion curves were compared with optical parameters defined by spectroscopic ellipsometry in the photon energy range 1.2-5.0 eV. Good agreement has been achieved between theoretical and experimental results. PMID:21694014

Atuchin, V V; Lin, Z S; Isaenko, L I; Kesler, V G; Kruchinin, V N; Lobanov, S I

2009-11-11

175

A Transdermal Drug Delivery System Based on LIGA Technology and Soft Lithography  

NASA Astrophysics Data System (ADS)

This report presents a transdermal drug delivery system based on LIGA fabricated microparts. It is a portable device combining a magnetically actuated micro gear pump with a microneedle array. The fluidic behaviour of the system is analyzed in order to predict its performance according to the dimension of the microparts and then compared to experimental data. The manufacturing process of both micropump and microneedle array are described.

Matteucci, Marco; Perennes, Frederic; Marmiroli, Benedetta; di Fabrizio, Enzo

2007-01-01

176

Rapid replication of polymeric and metallic high aspect ratio microstructures using PDMS and LIGA technology  

Microsoft Academic Search

This paper present a method of rapid replication of polymeric high aspect ratio microstructures (HARMs) and a method of rapid\\u000a reproduction of metallic micromold inserts for HARMs using polydimethylsiloxane (PDMS) casting and standard LIGA processes.\\u000a A high aspect ratio (HAR) metallic micromold insert, featuring a variety of test microstructures made of electroplated nickel\\u000a with 15:1 height-to-width ratio for 300 ?m

K. Kim; J.-B. Lee; H. Manohara; Y. Desta; M. Murphy; C. H. Ahn

2002-01-01

177

Influence of gold thin-film interlayers on anodic bonding of copper microstructures produced by LIGA  

Microsoft Academic Search

Neither pure copper nor solid gold can be anodically bonded to glass. It is only the gold coating on the copper which allows\\u000a a joint to be built up as a result of the copper ions diffusing into the gold layer, but not many of them being able to migrate\\u000a into the glass. To encapsulate microstructures produced by the LIGA

A. Gerlach; D. Maas; D. Seidel

1998-01-01

178

Diamond-like nanocomposite coatings for LIGA-fabricated nickel alloy parts.  

SciTech Connect

A commercial plasma enhanced chemical vapor deposition (PECVD) technique with planetary substrate rotation was used to apply a thin (200-400 nm thick) conformal diamond-like carbon (DLC) coating (known as a diamond-like nanocomposite (DLN)) on LIGA fabricated Ni-Mn alloy parts. The PECVD technique is known to overcome the drawbacks associated with the line-of-sight nature of physical vapor deposition (PVD) and substrate heating inherent with traditional chemical vapor deposition (CVD). The purpose of the present study is to characterize the coverage, adhesion, and tribological (friction and wear) behavior of DLN coatings applied to planar and sidewall surfaces of small featured LIGA Ni-Mn fabricated parts, e.g. 280 {micro}m thick sidewalls. Friction and wear tests were performed in dry nitrogen, dry air, and air with 50% RH at Hertzian contact pressures ranging from 0.3 to 0.6 GPa. The friction coefficient of bare Ni-Mn alloy was determined to be 0.9. In contrast, low friction coefficients ({approx}0.02 in dry nitrogen and {approx}0.2 in 50% RH air) and minimal amount of wear were exhibited for the DLN coated LIGA Ni-Mn alloy parts and test coupons. This behavior was due to the ability of the coating to transfer to the rubbing counterface providing low interfacial shear at the sliding contact; resultantly, coating one surface was adequate for low friction and wear. In addition, a 30 nm thick titanium bond layer was determined to be necessary for good adhesion of DLN coating to Ni-Mn alloy substrates. Raman spectroscopy and cross-sectional SEM with energy dispersive x-ray analysis revealed that the DLN coatings deposited by the PECVD with planetary substrate rotation covered both the planar and sidewall surfaces of LIGA fabricated parts, as well as narrow holes of 300 {micro}m (0.012 inch) diameter.

Prasad, Somuri V.; Scharf, Thomas W.

2005-03-01

179

Forming electrical interconnections through semiconductor wafers  

NASA Technical Reports Server (NTRS)

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Anthony, T. R.

1981-01-01

180

Everything Wafers: A Guide to Semiconductor Substrates  

NSDL National Science Digital Library

This website contains information on characteristics and properties of semiconductor wafers. Topics include types of substrates, process dependent characteristics, properties of semiconductors, cleaving, etching and other topics, along with related terms and links.

2012-11-29

181

A LigA Three-Domain Region Protects Hamsters from Lethal Infection by Leptospira interrogans  

PubMed Central

The leptospiral LigA protein consists of 13 bacterial immunoglobulin-like (Big) domains and is the only purified recombinant subunit vaccine that has been demonstrated to protect against lethal challenge by a clinical isolate of Leptospira interrogans in the hamster model of leptospirosis. We determined the minimum number and location of LigA domains required for immunoprotection. Immunization with domains 11 and 12 was found to be required but insufficient for protection. Inclusion of a third domain, either 10 or 13, was required for 100% survival after intraperitoneal challenge with Leptospira interrogans serovar Copenhageni strain Fiocruz L1-130. As in previous studies, survivors had renal colonization; here, we quantitated the leptospiral burden by qPCR to be 1.2×103 to 8×105 copies of leptospiral DNA per microgram of kidney DNA. Although renal histopathology in survivors revealed tubulointerstitial changes indicating an inflammatory response to the infection, blood chemistry analysis indicated that renal function was normal. These studies define the Big domains of LigA that account for its vaccine efficacy and highlight the need for additional strategies to achieve sterilizing immunity to protect the mammalian host from leptospiral infection and its consequences.

Coutinho, Mariana L.; Choy, Henry A.; Kelley, Melissa M.; Matsunaga, James; Babbitt, Jane T.; Lewis, Michael S.; Aleixo, Jose Antonio G.; Haake, David A.

2011-01-01

182

TOPICAL REVIEW: Wafer level packaging of MEMS  

Microsoft Academic Search

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass-Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in

Masayoshi Esashi

2008-01-01

183

Fabrication of wafer-level thermocompression bonds  

Microsoft Academic Search

Thermocompression bonding of gold is a promising technique for achieving low temperature, wafer-level bonding. The fabrication process for wafer bonding at 300°C via compressing gold under 7 MPa of pressure is described in detail. One of the issues encountered in the process development was e-beam source spitting, which resulted in micrometer diameter sized Au on the surfaces, and made bonding

Christine H. Tsau; S. M. Spearing; M. A. Schmidt

2002-01-01

184

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner  

NASA Technical Reports Server (NTRS)

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

2013-01-01

185

Design and fabrication of in situ UV-LIGA assembled robust nickel micro check valves for compact hydraulic actuators  

NASA Astrophysics Data System (ADS)

Compact robust hydraulic actuators (pumps) are very important for space-related applications because of their capabilities in producing much larger forces per unit volume/mass than existing technologies. PZT stacks (pusher) have been widely identified for developing compact actuators (pump), but valves to match the inherent properties of PZT, in terms of high frequency (up to 100 kHz), load support (up to 100 MPa) and desired flow rate, are missing. The authors have developed novel robust solid nickel microvalve arrays using an in situ UV-LIGA assembling process. A high frequency and large pressure support capability has been realized analytically by elaborating the scaling law, in combination with a stiff material such as nickel. Large flow rate was realized by utilizing a microvalve array, instead of using a single valve. By doing this, all major requirements, in terms of frequency match, load support, as well as small amount of valve mass (payload), have been met. The reliability of the valve is assured by using a curved valve flap so that low stress can be maintained, in combination with a mechanical robust nickel valve stopper.

Li, Bo; Chen, Quanfang

2005-10-01

186

Fabricating capacitive micromachined ultrasonic transducers with wafer-bonding technology  

Microsoft Academic Search

Introduces a new method for fabricating capacitive micromachined ultrasonic transducers (CMUTs) that uses a wafer bonding technique. The transducer membrane and cavity are defined on an SOI (silicon-on-insulator) wafer and on a prime wafer, respectively. Then, using silicon direct bonding in a vacuum environment, the two wafers are bonded together to form a transducer. This new technique, capable of fabricating

Yongli Huang; A. Sanli Ergun; E. Haeggstrom; Mohammed H. Badi; B. T. Khuri-Yakub

2003-01-01

187

Simultaneous double side grinding of silicon wafers: a literature review  

Microsoft Academic Search

Silicon wafers are the most widely used substrates for fabricating integrated circuits (ICs). The quality of ICs depends directly on the quality of silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Simultaneous double side grinding (SDSG) is one of the processes to flatten the wire-sawn wafers. This paper reviews the literature on SDSG of

Z. C. Li; Z. J. Pei; Graham R. Fisher

2006-01-01

188

A GRINDING-BASED MANUFACTURING METHOD FOR SILICON WAFERS: GENERATION MECHANISMS OF CENTRAL BUMPS ON GROUND WAFERS  

Microsoft Academic Search

Most integrated circuits (IC) are fabricated using silicon wafers. The continuing shrinkage of the size of IC features has imposed more and more stringent requirements on the wafer flatness. Furthermore, wafer manufacturers are under constant pressure to reduce the wafer cost. The traditional lapping-based manufacturing method is unable to satisfy the ever-increasing demand for better flatness and lower cost. Previous

Wangping Sun; Z. J. Pei; Graham R. Fisher

2006-01-01

189

Porous solid ion exchange wafer for immobilizing biomolecules  

DOEpatents

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

Arora, Michelle B. (Woodridge, IL); Hestekin, Jamie A. (Morton Grove, IL); Lin, YuPo J. (Naperville, IL); St. Martin, Edward J. (Libertyville, IL); Snyder, Seth W. (Lincolnwood, IL)

2007-12-11

190

Tra.Q — Laser marking for single wafer identification — Production experience from 100 million wafers  

Microsoft Academic Search

Single wafer identification is a mandatory element of a modern solar cell production [1]. It accelerates the efficiency roadmap of the solar cell and fosters the cost reduction roadmap of the fabrication. The laser marking concept Tra.Q creates an individual code on each and every wafer. This makes process optimization and quality control easier and faster. The solar cells are

Sven Wanka; David Rychtarik; Jorg Muller; Steffen Geissler; Philip Kappe; Marco Spallek; Uli vom Bauer; Christoph Ludwig; Peter Wawer

2011-01-01

191

Recent developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking  

Microsoft Academic Search

This paper will focus on recent results of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. We report on bonding quality, wafer-to-wafer alignment accuracy and electrical connectivity. Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers. A particular concern is related to the planarization (e.g. CMP) of Cu-SiO2 hybrid surfaces: copper dishing and erosion

I. Radu; D. Landru; G. Gaudin; G. Riou; C. Tempesta; F. Letertre; L. Di Cioccio; P. Gueguen; T. Signamarcheix; C. Euvrard; J. Dechamp; L. Clavelier; M. Sadaka

2010-01-01

192

Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics  

SciTech Connect

Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

None

2010-01-15

193

Wafer-fused semiconductor radiation detector  

DOEpatents

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

2002-01-01

194

Modeling and fabrication of micro 3K-2-type planetary gear reducer utilizing SU-8 photoresist as alternative LIGA technology  

NASA Astrophysics Data System (ADS)

The LIGA type process, utilizing SU-8 photoresist as alternative LIGA technology, can fabricate high aspect ratio microstructures without employing synchrotron light and suitable X-ray mask. Based on LIGA type process in this paper, detailed investigations of the modeling and fabrication of micro 3K-2 type planetary gear reducer, such as the modeling and design of micro reducer, CAD of micro gear mask, SU-8 UV photolithography, micro electroforming, micro molding, have been performed. And 400 um thickness sun gear, 400 um thickness planet gear, 200 um thickness fixed inner gear, and 200 um thickness rotary inner gear, whose teeth are 15,11,36,39 respectively, have been obtained. Utilizing these gears, the micro reducer whose modulus, outer diameter and velocity ratio are 0.03, 2mm, 44.2:1, has been assembled and applied in (phi) 2mm micro electro magnetic motor successfully.

Zhang, Weiping; Chen, Wenyuan; Chen, Di; Chen, Xiaomei; Wu, Xiaosheng; Xu, Zhengfu

2001-10-01

195

Making Porous Luminescent Regions In Silicon Wafers  

NASA Technical Reports Server (NTRS)

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

196

Multi-dimensional multi-species modeling of transient electrodeposition in LIGA microfabrication.  

SciTech Connect

This report documents the efforts and accomplishments of the LIGA electrodeposition modeling project which was headed by the ASCI Materials and Physics Modeling Program. A multi-dimensional framework based on GOMA was developed for modeling time-dependent diffusion and migration of multiple charged species in a dilute electrolyte solution with reduction electro-chemical reactions on moving deposition surfaces. By combining the species mass conservation equations with the electroneutrality constraint, a Poisson equation that explicitly describes the electrolyte potential was derived. The set of coupled, nonlinear equations governing species transport, electric potential, velocity, hydrodynamic pressure, and mesh motion were solved in GOMA, using the finite-element method and a fully-coupled implicit solution scheme via Newton's method. By treating the finite-element mesh as a pseudo solid with an arbitrary Lagrangian-Eulerian formulation and by repeatedly performing re-meshing with CUBIT and re-mapping with MAPVAR, the moving deposition surfaces were tracked explicitly from start of deposition until the trenches were filled with metal, thus enabling the computation of local current densities that potentially influence the microstructure and frictional/mechanical properties of the deposit. The multi-dimensional, multi-species, transient computational framework was demonstrated in case studies of two-dimensional nickel electrodeposition in single and multiple trenches, without and with bath stirring or forced flow. Effects of buoyancy-induced convection on deposition were also investigated. To further illustrate its utility, the framework was employed to simulate deposition in microscreen-based LIGA molds. Lastly, future needs for modeling LIGA electrodeposition are discussed.

Evans, Gregory Herbert (Sandia National Laboratories, Livermore, CA); Chen, Ken Shuang

2004-06-01

197

Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage  

NASA Astrophysics Data System (ADS)

This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ?50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (? 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu-precipitates (upto 50 nm) compresses Si-lattice to facilitate Si-XII/III

Kulshreshtha, Prashant Kumar

198

Across wafer CD uniformity optimization by wafer film scheme at double patterning lithography process  

NASA Astrophysics Data System (ADS)

The Double Patterning lithography (DPL) process is a well known method to overcome the k1 limit below 0.25, but the pattern final performance (OVL/CD) get more sensitive with the initial core CD uniformity, one of the main factors is across wafer CD uniformity control. Previous improvements applying scanner dose or PEB temperature multi-zone control, the others use the vacuum PEB plate design. In this study, we adopt various DPL sacrificial layers to modify wafer warpage level, it can adjust a suitable wafer warpage profile. By this method, we can achieve 30% CD uniformity improvement without the scanner dose/ PEB multi-zone heating compensation,

Lin, Hsiao-Chiang; Li, Yang-Liang; Wang, Shiuan-Chuan; Liu, Chien-Hung; Wang, Zih-Song; Hsuh, Jhung-Yuin

2014-04-01

199

Laser technology for wafer dicing and microvia drilling for next generation wafers (Invited Paper)  

NASA Astrophysics Data System (ADS)

Laser micromaching systems are being used in mainstream high-volume semiconductor applications. Two of those processes, via drilling and thin wafer dicing, are discussed in this paper. Via drilling has been proven viable for forming through chip and blind vias. The inherent flexibility of the laser process makes it possible to control via depth, diameter and sidewall slope. As a mask-less process, laser via drilling can be cost affective and highly flexible in its application. Thin wafer dicing reduces the breakage and damage to thin silicon wafers. A new process has been developed that improves the die strength of laser singulated devices beyond that obtained using conventional sawing techniques.

Toftness, Richard F.; Boyle, Adrian; Gillen, David

2005-04-01

200

Determination of Surface Roughness of InP (001) Wafers by X-ray Scattering.  

National Technical Information Service (NTIS)

The surface roughness of polished InP (001) wafers were examined by x-ray reflectivity and crystal truncation rod (CTR) measurements. The root-mean-square roughness and the lateral correlation scale were obtained by both methods. The scattering intensitie...

S. F. Cui J. H. Li M. Li C. R. Li Y. S. Gu Z. H. Mai Y. T. Wang Y. Zhuang

1994-01-01

201

Scanning holographic scatterometer for wafer surface inspection  

NASA Astrophysics Data System (ADS)

The semiconductor industry requires ever smaller semiconductor structures with faster response times and more function per unit area of each chip. In addition, the industry is changing from 200 mm to 300 mm diameter wafers with fewer defects and rapid detection at all processing stages. To meet these needs, defect data must be processed in near-real-time to expedite correction of processing problems at the earliest possible stage. Under a Small Business Innovation Research (SBIR) program, sponsored by the Air Force Manufacturing Technology Division at Wright Laboratory, Dayton, Ohio, Sentec Corporation has developed a revolutionary technology for contaminant particle detection on unpatterned semiconductor wafers. A key to the Sentec technology is detection, not of the intensity of backscattered energy from particles or defects, but of the amplitude of the electro-magneitc field of this backscattered energy. This new technology will allow the detection of particles that are significantly smaller than those which can be reliably located using current scatterometers. The technical concepts for a stand-alone particle detection tool have been created. It uses a continuous scanning mechanism to perform high-speed examinations of target wafers. This tool, also, has the capability of quantifying the microroughness or background haze of a subject wafer and presenting that information separate from the contamination particle data. During the course of this project, three patent applications were filed.

Klooster, Alex; Marks, James; Hanson, Kael; Sawatari, Takeo

2004-05-01

202

Apparatus for edge etching of semiconductor wafers  

NASA Technical Reports Server (NTRS)

A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

Casajus, A.

1986-01-01

203

Low-temperature full wafer adhesive bonding  

Microsoft Academic Search

We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 µm and 18 µm. The tested polymer materials were benzocyclobutene (BCB)

Frank Niklaus; Peter Enoksson; Edvard Kälvesten; Göran Stemme

2001-01-01

204

Compliant Wafer Level Package for Enhanced Reliability  

Microsoft Academic Search

Wafer level package (WLP) volumes are steadily increasing due to their small package size and low manufacturing cost. However, applications to date have been mostly limited to die smaller than 5mm x 5mm. Solder joint fatigue due to stresses generated by the CTE mismatch between the die and the printed circuit board (PCB) limits adoption of WLP for large dies.

Guilian Gao; Bel Haba; Vage Oganesian; Ken Honer; David Ovrutsky; Charles Rosenstein; Ekaterina Axelrod; Felix Hazanovich; Yulia Aksenton

2007-01-01

205

Wafer-level package interconnect options  

Microsoft Academic Search

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare

Jayaprakash Balachandran; Steven Brebels; Geert Carchon; Maarten Kuijk; Walter De Raedt; Bart K. J. C. Nauwelaers; Eric Beyne

2006-01-01

206

Contactless magnetically levitated silicon wafer transport system  

Microsoft Academic Search

A new magnetically levitated wafer transport system is developed for the semiconductor fabrication process to get rid of the particle and oil contaminations that normally exist in conventional transport systems. The transport system consists of levitation, stabilization tracks, and a propelling system. Stabilities needed for levitation in the transport system are achieved by an antagonistic property produced in the tracks

K. H. Park; S. K. Lee; J. H. Yi; S. H. Kim; Y. K. Kwak; I. A. Wang

1996-01-01

207

Bubble-domain circuit wafer evaluation coil set  

NASA Technical Reports Server (NTRS)

Coil structures have been designed to permit nondestructive testing of bubble wafers. Wafers can be electrically or optically inspected and operated from quasi-static frequency to maximum device operating frequency.

Chen, T. T.; Williams, J. L.

1975-01-01

208

Wafer plane inspection for advanced reticle defects  

NASA Astrophysics Data System (ADS)

Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

2008-06-01

209

Evaluation of the damaged layers formed during the wafer processing of InP wafers  

Microsoft Academic Search

Double-crystal X-ray diffraction and X-ray topography were used to characterize InP wafers at various stages of polishing. InP Sn-doped single crystals were grown by the conventional LEC technique. The wafers cut from the single-crystal ingots were first lapped on both sides by alumina powders removing 80 microns from each face, etched by bromine-methanol, and then mirror-polished by Br-methanol removing 10

Y. Takahashi; T. Fukui; O. Oda

1987-01-01

210

A MEMS guide plate for a high temperature testing of a wafer level packaged die wafer  

Microsoft Academic Search

This paper describes the design and fabrication of a MEMS guide plate, which was used for a vertical probe card to test a\\u000a wafer level packaged die wafer. The size of the fabricated MEMS guide plate was 10.6 × 10.6 cm. The MEMS guide plate consisted\\u000a of 8,192 holes to insert pogo pins, and four holes for bolting between the guide plate and

Woo-Chang Choi; Jee-Youl Ryu

2011-01-01

211

Design, Process, and Reliability of Wafer Level Packaging  

Microsoft Academic Search

\\u000a Wafer level packaging (WLP) has been growing continuously in electronics packaging due to its low cost in batch manufacturing\\u000a and the potential of enabling wafer test and burn-in. A variety of wafer level packages have been devised, among which four\\u000a important categories are identified including thin film redistribution and bumping, encapsulated package, compliant interconnect,\\u000a and wafer level underfill. This chapter

Zhuqing Zhang; C. Wong

212

Fabrication of PMMA Microchip of Capillary Electrophoresis by Optimized UV-LIGA Process  

NASA Astrophysics Data System (ADS)

Design and fabrication of microfluidic devices on polymethylmethacrylate (PMMA) substrates for electrochemical analysis applications using improved UV-LIGA process are described. The micro-channel structures are transferred from Nickel mould into the plastic plates by hot embossing method. During the mould fabrication, the exposure process is optimized for the large ratio of exposed area to unexposed area of negative photo-resist (SU-8), then non-planar electroforming technique is used for the large line space of the SU8 photoresist mold. Microelectrodes for electrochemical detection are fabricated on other blank PMMA plates through lift-off process. Then these substrates with microchannels are bonded to PMMA plates with microelectrodes by thermal bonding method based on surface modification. In this study, the PMMA microchips of capillary electrophoresis for electrochemical detection (CE-ECD Chips) have been demonstrated by electrophoretic separation of L-ascorbic and uric acid. The results indicate that the fabrication of CE chips by this improved UV-LIGA process has potential of mass production with low cost.

Zhu, Xuelin; Liu, Gang; Xiong, Ying; Guo, Yuhua; Tian, Yangchao

2006-04-01

213

Development of ultra-low impedance Through-wafer Micro-vias  

NASA Astrophysics Data System (ADS)

Concurrent with our microcalorimeter array fabrication for Constellation-X technology development, we are developing ultra-low impedance Through-Wafer Micro-Vias (TWMV) as electrical interconnects for superconducting circuits. The TWMV will enable the electrical contacts of each detector to be routed to contacts on the backside of the array. There, they can be bump-bonded to a wiring fan-out board which interfaces with the front-end Superconducting Quantum Interference Device readout. We are concentrating our developmental efforts on ultra-low impedance copper and superconducting aluminum TWMV in 300-400 micron thick silicon wafers. For both schemes, a periodic pulse-reverse electroplating process is used to fill or coat micron-scale through-wafer holes of aspect ratios up to 20. Here we discuss the design, fabrication process, and recent electro-mechanical test results of Al and Cu TWMV at room and cryogenic temperatures.

Finkbeiner, F. M.; Adams, C.; Apodaca, E.; Chervenak, J. A.; Fischer, J.; Doan, N.; Li, M. J.; Stahle, C. K.; Brekosky, R. P.; Bandler, S. R.; Figueroa-Feliciano, E.; Lindeman, M. A.; Kelley, R. L.; Saab, T.; Talley, D. J.

2004-03-01

214

In-situ ultrasonic thermometry of semiconductor wafers  

Microsoft Academic Search

We report a temperature measurement technique based on the temperature dependence of acoustic wave velocity in silicon wafers. The zeroth order antisymmetric Lamb wave is excited in the wafer using the quartz pins which support the wafer during processing. Extensional waves are generated in the quartz pin by a PZT-SH transducer and the acoustic energy is coupled to the Lamb

F. L. Degertekin; J. Pei; Y. J. Lee; B. T. Khuri-Yakub; K. C. Saraswat

1993-01-01

215

Wafer LMC accuracy improvement by adding mask model  

NASA Astrophysics Data System (ADS)

Mask effect will be more sensitive for wafer printing in high-end technology. For advance only using current wafer model can not predict real wafer behavior accurately because it do not concern real mask performance (CD error, corner rounding..). Generally, we use wafer model to check whether our OPC results can satisfy our requirements (CD target). Through simulation on post-OPC patterns by using wafer model, we can check whether these post-OPC patterns can meet our target. Hence, accuracy model can help us to predict real wafer printing results and avoid OPC verification error. To Improve simulation verification accuracy at wafer level and decrease false alarm. We must consider mask effect like corner rounding and line-end shortening...etc in high-end mask. UMC (United Microelectronics Corporation) has cooperated with Brion and DNP to evaluate whether the wafer LMC (Lithography Manufacturability Check) (Brion hot spots prediction by simulation contour) accuracy can be improved by adding mask model into LMC verification procedure. We combine mask model (DNP provide 45nm node Poly mask model) and wafer model (UMC provide 45nm node Poly wafer model) then build up a new model that called M-FEM (Mask Focus Energy Matrix model) (Brion fitting M-FEM model). We compare the hotspots prediction between M-FEM model and baseline wafer model by LMC verification. Some different hotspots between two models were found. We evaluate whether the hotspots of M-FEM is more close to wafer printing results.

Lo, Wei Cyuan; Cheng, Yung Feng; Chen, Ming Jui; Haung, Peter; Chang, Stephen; Tsujimoto, Eiji

2010-03-01

216

X-ray transmission lenses by deep x-ray lithography and LIGA technique: first results and fundamental limits  

NASA Astrophysics Data System (ADS)

Today's dimensionality of microtechnology enables the fabrication of precise objects, like diffraction limited x- ray transmission optics. Based on deep x-ray/LIGA technology, first results are presented concerning the fabrication and modelling of parabolic and massive-serial focalizing x-ray transmission lenses in PMMA, as opposed to standard grazing incidence reflection optics. The theoretical performance limitations of such optical systems are derived and stem from fundamental physical properties like the anomalous dispersion properties of the used materials. Parabolic x-ray transmission lenses are limited to very small numerical apertures, but behave optically like any ideal transmission lens would do. The advantages of deep x-ray LIGA technology are its favorable surface roughness and inherent precision. Unlike silicon micromachining, LIGA technique profits from a larger choice of possible materials. The importance of low-Z compounds like Lithium or Be/B is pointed out, together with necessary new techniques in the framework of LIGA, like electroplating from organic solutions.

Kupka, Roland K.; Bouamrane, Faycal; Roulliay, Marc; Megtert, Stephan

1999-03-01

217

Development of a W-band Serpentine Waveguide Amplifier based on a UV- LIGA Microfabricated Copper Circuit.  

National Technical Information Service (NTIS)

We are developing a 95 GHz, 200 W, wideband vacuum electronic amplifier based on a 20 kV, 120 mA electron beam. The serpentine circuit is fabricated by multilayer UV-LIGA using an embedded polymer monofilament, which produces an all-copper monolithic stru...

A. M. Cook C. D. Joye D. P. Chernin J. P. Calame K. T. Nguyen

2013-01-01

218

Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force  

Microsoft Academic Search

This paper reports about a novel wafer-level integration technique of discrete surface mount devices (SMDs). It enables wafer-level mounting of plural kinds of SMDs on a silicon (Si)-wafer using vibration and gravity force. Deep holes with 400-m depth are formed on the surface of a Si-wafer by deep reactive ion etching process after general integrated circuit process for positioning of

Minoru Sudou; Hidekuni Takao; Kazuaki Sawada; Makoto Ishida

2007-01-01

219

Low temperature IC-compatible wafer-to-wafer bonding with embedded micro channels for integrated sensing systems  

Microsoft Academic Search

In this work, a low temperature wafer-to-wafer bonding technique is demonstrated. The technology can be implemented on a variety of materials serving as planar substrates in the microelectronics industry. As an integral part of this technique, one of the wafers to be bonded contains a patterned micro molded layer on the surface with a thickness range of 2 ?m to

A. Bruno Frazier

1995-01-01

220

Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology  

NASA Astrophysics Data System (ADS)

Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances. Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported. Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure mechanism. The kinetic and thermodynamic analysis of the annealing-induced interfacial transformation process has been performed based upon the temporal measurements of interface electrical conductivity and micromorphologies. Finally, the feasibility of using the combination of low-temperature grown amorphous alpha-(Ga, As) materials and wafer-bonding technology to fabricate GaSb semiconductor on GaAs substrates to potentially create GaSb-on-insulator structure has been demonstrated.

Shi, Fang Frank

221

Top-Gated Graphene Field-Effect Transistors Using Graphene on Si (111) Wafers  

Microsoft Academic Search

In this letter, we report the first experimental demonstration of wafer-scale ambipolar field-effect transistor (FET) on Si (111) substrates by synthesizing a graphene layer on top of 3C-SiC(111)\\/Si(111) substrates. With lateral scaling of the source-drain distance to 1 ?m in a top-gated layout, the ON-state current of 225 ?A\\/?m and peak transconductance of > 40 ?S\\/?m were obtained at Vds

J. S. Moon; D. Curtis; S. Bui; T. Marshall; D. Wheeler; I. Valles; S. Kim; E. Wang; X. Weng; M. Fanton

2010-01-01

222

TOPICAL REVIEW: Wafer level packaging of MEMS  

NASA Astrophysics Data System (ADS)

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass-Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review.

Esashi, Masayoshi

2008-07-01

223

Devices using resin wafers and applications thereof  

SciTech Connect

Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL); St. Martin, Edward (Libertyville, IL); Arora, Michelle (Woodridge, IL); de la Garza, Linda (Woodridge, IL)

2009-03-24

224

VLED for Si wafer-level packaging  

NASA Astrophysics Data System (ADS)

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-02-01

225

ELTRAN® (SOI-Epi Wafer™) Technology  

Microsoft Academic Search

\\u000a ELTRAN® (Epitaxial Layer TRANsfer), which is the first manufacturable and commercially available product using Porous Si,\\u000a has been originated, developed and produced in Canon Inc., Japan. The last established technique is highly reproducible splitting\\u000a in the Porous Si layer by Water Jet and reuse the seed wafer several times. The thicknesses of both SOI and the buried oxide\\u000a layers are

Takao Yonehara; Kifofumi Sakaguchi

226

Encapsulation challenges for wafer level packaging  

Microsoft Academic Search

The interest of user for WLP has been raised because of benefits such as reduced package thickness, fan-out capability, high I\\/O, substrate-less process, integration of passives into structure, good thermal and electrical performance. The objective of this paper is to delineate technical challenges and issues that potential adopter of wafer level molding will face, technological solution availability and the broad

E. K. Th; J. Y. Hao; J. P. Ding; Q. F. Li; W. L. Chan; S. C. Ho; H. M. Huang; Y. J. Jiang

2009-01-01

227

Precipitating Chromium Impurities in Silicon Wafers  

NASA Technical Reports Server (NTRS)

Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

Salama, A. M.

1982-01-01

228

Evaluation of the damaged layers formed during the wafer processing of InP wafers  

NASA Astrophysics Data System (ADS)

Double-crystal X-ray diffraction and X-ray topography were used to characterize InP wafers at various stages of polishing. InP Sn-doped single crystals were grown by the conventional LEC technique. The wafers cut from the single-crystal ingots were first lapped on both sides by alumina powders removing 80 microns from each face, etched by bromine-methanol, and then mirror-polished by Br-methanol removing 10 microns from one side. The wafers were evaluated after each wafering process and then evaluated after etching for various times to reveal the depth of damaged layers. The diffraction technique revealed high levels of damage in both as-cut and as-lapped samples but no damage in the polished samples. However, the technique of X-ray topography was more sensitive than the diffraction technique, revealing microcracks (in the as-cut and the lapped wafers) at the etch depths insensitive to the diffraction technique; the mirror-polished samples were again shown to be free from damage.

Takahashi, Y.; Fukui, T.; Oda, O.

1987-04-01

229

Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size  

NASA Astrophysics Data System (ADS)

For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.

Kim, Hee Yeoun; Yang, Chungmo; Park, Jae Hong; Jung, Ho; Kim, Taehyun; Kim, Kyung Tae; Lim, Sung Kyu; Lee, Sang Woo; Mitchell, Jay; Hwang, Wook Joong; Lee, Kwyro

2013-06-01

230

Equipment for On-Wafer Testing From 220 to 325 GHz  

NASA Technical Reports Server (NTRS)

A system of electronic instrumentation, constituting the equivalent of a two-port vector network analyzer, has been developed for use in on-wafer measurement of key electrical characteristics of semiconductor devices at frequencies from 220 to 325 GHz. A prior system designed according to similar principles was reported in Equipment for On-Wafer Testing at Frequencies Up to 220 GHz (NPO-20760), NASA Tech Briefs, Vol. 25, No. 11 (November 2001), page 42. As one would expect, a major source of difficulty in progressing to the present higher-frequency-range system was the need for greater mechanical precision as wavelengths shorten into the millimeter range, approaching the scale of mechanical tolerances of prior systems. The system (see figure) includes both commercial off-the-shelf and custom equipment. As in the system of the cited prior article, the equipment includes test sets that are extended versions of commercial network analyzers that function in a lower frequency range. The extension to the higher frequency range is accomplished by use of custom frequency-extension modules that contain frequency multipliers and harmonic mixers. On-wafer measurement is made possible by waveguide wafer probes that were custom designed and built for this wavelength range, plus an on-wafer calibration substrate designed for use with these probes. In this case, the calibration substrate was specially fabricated by laser milling. The system was used to make the first on-wafer measurements of a semiconductor device in the frequency range from 220 to 320 GHz. Some of the measurement results showed that the device had gain.

Samoska, Lorene; Peralta, Alejandro; Dawson, Douglas; Lee, Karen; Boll, Greg; Oleson, Chuck

2006-01-01

231

?-Device fabrication and packaging below 300°C utilizing plasma-assisted wafer-to-wafer bonding  

NASA Astrophysics Data System (ADS)

Wafer-to-wafer bonding techniques, such as anodic bonding or high temperature silicon direct fusion bonding, have been in development since the late 1960's and became key technologies for MEMS manufacturing. Plasma assisted wafer bonding is an emerging method offering several advantages over traditional bonding techniques. This technology was first discovered and patented in the early 1990's and has been used in SOI production for the past five years. Now plasma activation benefits are being used to enable 3D integration and advanced MEMS device fabrication and packaging. The main advantage of plasma assisted bonding is that high strength direct bonds between substrates, like Si, glass or polymers, can be achieved already below 300°C.

Kirchberger, Herwig; Pelzer, Rainer; Farrens, Sharon

2006-12-01

232

Evaluation of the damaged layers formed during the wafer processing of InP wafers  

SciTech Connect

InP is now becoming a very promising material for substrates in the application of laser diodes, light emitting diodes, and high speed FET's. In this context, high quality polishing is desired in such a way that no damaged layer is detected. However, very little attention has been paid to the quantitative characterization of the polishing process. There is only a report concerned with the characterization of mirror-polished InP wafers. In the present work, the authors applied double-crystal x-ray diffraction and x-ray topography for the evaluation of InP wafers in various polishing stages.

Takahashi, Y.; Fukui, T.; Oda, O.

1987-04-01

233

Oral immunization with Escherichia coli expressing a lipidated form of LigA protects hamsters against challenge with Leptospira interrogans serovar Copenhageni.  

PubMed

Leptospirosis is a potentially fatal zoonosis transmitted by reservoir host animals that harbor leptospires in their renal tubules and shed the bacteria in their urine. Leptospira interrogans serovar Copenhageni transmitted from Rattus norvegicus to humans is the most prevalent cause of urban leptospirosis. We examined L. interrogans LigA, domains 7 to 13 (LigA7-13), as an oral vaccine delivered by Escherichia coli as a lipidated, membrane-associated protein. The efficacy of the vaccine was evaluated in a susceptible hamster model in terms of the humoral immune response and survival from leptospiral challenge. Four weeks of oral administration of live E. coli expressing LigA7-13 improved survival from intraperitoneal (i.p.) and intradermal (i.d.) challenge by L. interrogans serovar Copenhageni strain Fiocruz L1-130 in Golden Syrian hamsters. Immunization with E. coli expressing LigA7-13 resulted in a systemic antibody response, and a significant LigA7-13 IgG level after the first 2 weeks of immunization was completely predictive of survival 28 days after challenge. As in previous LigA vaccine studies, all immunized hamsters that survived infection had renal leptospiral colonization and histopathological changes. In summary, an oral LigA-based vaccine improved survival from leptospiral challenge by either the i.p. or i.d. route. PMID:24478102

Lourdault, Kristel; Wang, Long-Chieh; Vieira, Ana; Matsunaga, James; Melo, Rita; Lewis, Michael S; Haake, David A; Gomes-Solecki, Maria

2014-02-01

234

Wafer-scale synthesis of monodisperse synthetic magnetic multilayer nanorods.  

PubMed

A double exposure technique has been used to fabricate nanoimprint stamps for making monodisperse nanorods with controllable lengths. The nanorod length is defined by a normal photolithography projection process whereas the nanorod width is defined by an edge-lithography process using a soft polydimethylsiloxane (PDMS) contact mask. Taking advantage of edge-lithography, the nanorod width can be less than the diffraction limit of the exposure light. Using these nanorod stamps, synthetic magnetic multilayer (SMM) nanorods have been fabricated using nanoimprint lithography, resulting in a length variation of ?3%. Nanorod magnetic properties have been characterized in both longitudinal and in-plane transverse directions of the nanorods. A theoretical model has been established to explain the magnetic responses and has revealed that both shape anisotropy and interlayer interactions are important in determining the properties of SMM nanorods. PMID:24329003

Zhang, Mingliang; Bechstein, Daniel J B; Wilson, Robert J; Wang, Shan X

2014-01-01

235

Super-flat wafer chucks: from simulation and testing to a complete 300mm wafer chuck with low wafer deformation between pins  

NASA Astrophysics Data System (ADS)

Berliner Glas is a privately owned, mid-sized manufacturer of precision opto-mechanics in Germany. One specialty of Berliner Glas is the design and production of high performance vacuum and electrostatic wafer chucks. Driven by the need of lithography and inspection for smaller overlay values, we pursue the production of an ideally flat wafer chuck. An ideally flat wafer chuck holds a wafer with a completely flat backside and without lateral distortion within the wafer surface. Key parameters in influencing the wafer chucks effective flatness are thermal performance and thermal management, roughness of the surface, choice of materials and the contact area between wafer and wafer chuck. In this presentation we would like to focus on the contact area. Usually this is decreased as much as possible to avoid sticking effects and the chance of trapped particles between the chuck surface and the backside of the wafer. This can be realized with a pin structure on the chuck surface. Making the pins smaller and moving pins further apart from each other makes the contact area ever smaller but also adds new challenges to achieve a flat and undistorted wafer on the chuck. We would like to address methods of designing and evaluating such a pin structure. This involves not only the capability to simulate the ideal pattern of pins on the chuck's surface, for which we will present 2D and 3D simulation results. As well, we would like to share first results of our functional models. Finally, measurement capability has to be ensured, which means improving and further development of Fizeau flatness test interferometers.

Müller, Renate; Afanasiev, Kanstantin; Ziemann, Marcel; Schmidt, Volker

2014-04-01

236

Wafer bonding of gallium arsenide on sapphire  

Microsoft Academic Search

\\u000a $1\\\\overline{1} 02$  ) sapphire in a micro-cleanroom at room temperature under hydrophilic or hydrophobic surface conditions. Subsequent heating\\u000a up to 500 °C increased the bond energy of the GaAs-on-sapphire (GOS) wafer pair close to the fracture energy of the bulk material.\\u000a The bond energy was measured as a function of the temperature. Since the thermal expansion coefficients of GaAs and sapphire\\u000a are close to

P. Kopperschmidt; G. Kästner; S. Senz; D. Hesse; U. Gösele

1997-01-01

237

Recent Advances in Machining of Silicon Wafers for Semiconductor Applications  

Microsoft Academic Search

Silicon wafers are used world-wide for the production of microchips. Silicon is a hard and brittle material. Conversion of\\u000a silicon ingots into polished wafers requires much processing including machining and chemical processing. The machining is\\u000a critical to high-quality standards. With the development of new components, the eletronic industries require hgher standards\\u000a for total thickness variation and also wafer warp. This

P. S. Sreejith; G. Udupa; Y. B. M. Noor; B. K. A. Ngoi

2001-01-01

238

Improvement in WL-CSP reliability by wafer thinning  

Microsoft Academic Search

WL-CSP is a low profile, true chip sue package that is entirely built on a wafer using front-end and back end processing. The wafers can be batch-processed in a fab, which reduces the number of materials and packaging steps, reduces inventory, and allows for wafer level burn in and test. This technology is driven by cost, sue, and ease of

Li Wetz; Jeny White; Beth Keser

2003-01-01

239

Through-wafer copper electroplating for three-dimensional interconnects  

Microsoft Academic Search

Through-wafer electrical connections are becoming increasingly important for three-dimensional integrated circuits, microelectromechanical systems packaging and radio-frequency components. In this paper, we report our current results on the formation of through-wafer metal plugs using the copper electroplating technique. Several approaches for via filling are investigated, such as filling before or after wafer thinning. Among the methods experimented, the one-side Cu plating

N T Nguyen; E Boellaard; N P Pham; V G Kutchoukov; G Craciun; P M Sarro

2002-01-01

240

Laser technology for wafer dicing and microvia drilling for next generation wafers (Invited Paper)  

Microsoft Academic Search

Laser micromaching systems are being used in mainstream high-volume semiconductor applications. Two of those processes, via drilling and thin wafer dicing, are discussed in this paper. Via drilling has been proven viable for forming through chip and blind vias. The inherent flexibility of the laser process makes it possible to control via depth, diameter and sidewall slope. As a mask-less

Richard F. Toftness; Adrian Boyle; David Gillen

2005-01-01

241

Thermal spray and cold spray analysis of density, porosity, and tensile Specimens for use with LIGA applications  

SciTech Connect

This analysis provides a preliminary investigation into using Twin-Wire Arc Thermal Spray and Cold Spray as material deposition processes for LIGA applications. These spray material processes were studied to make an initial determination of their potential as alternatives to producing mechanical parts via the electroplating process. Three materials, UltraMachinable{reg_sign} Stainless Steel, BondArc{reg_sign}, and aluminum, were sprayed using Thermal Spray. Only aluminum was sprayed using the Cold Spray process. Following the spray procedure, the test specimens were released from a copper mold and then tested. Three tests, density, tensile strength, and porosity, were performed on the specimens to determine the spray effect on material properties. Twin-Wire Arc Thermal Spray did not demonstrate adequate deposition properties and does not appear to be a good process candidate for LIGA. However, Cold Spray yielded better density results and warrants further investigation to analyze the minimum feature size produced by the process.

DECKER,MERLIN K.; SMITH,MARK F.

2000-02-01

242

Micro-miniature gas chromatograph column disposed in silicon wafers  

DOEpatents

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Yu, Conrad M. (Antioch, CA)

2000-01-01

243

Neutron guidance by internal reflections in thin silicon wafers  

NASA Astrophysics Data System (ADS)

We have performed cold neutron longitudinal transmission measurements through single crystal silicon wafers of 200 ?m thickness and 50 mm length which have been coated on both sides with nickel to form microguides. Rocking curve measurements with neutrons of a wavelength of 7 Å have been conducted on assemblies of straight wafers placed end-to-end for neutron pathways in silicon from 50 to 200 mm, and on curved wafers. In addition, transmission measurements have been carried out on a straight wafer as a function of wavelength. We find that the reflectivity for the internal silicon-nickel interface is 0.988±0.005.

Grüning, U.; Magerl, A.; Mildner, D. F. R.

1992-04-01

244

Micro-miniature gas chromatograph column disposed in silicon wafers  

SciTech Connect

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Yu, C.M.

2000-05-30

245

Novel wafer stepper with violet LED light source  

NASA Astrophysics Data System (ADS)

Novel wafer stepper by using contact or proximity printing will be developed, using violet LED light source to replace Hg Arc. lamp or laser. Mirror, filter and condenser lens for Hg Arc. Lamp or laser and reduction lens for projection printing can be discarded. Reliability and manufacturing cost of wafer stepper can be improved. Exposure result by using IP3600 resist and wafer stepper with violet LED light source (wave-length 360nm to 410 nm) will be obtained. This novel wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist with sub-micron to 100 micron thickness.

Ting, Yung-Chiang; Shy, Shyi-Long

2014-03-01

246

Thermal spray and cold spray analysis of density, porosity, and tensile Specimens for use with LIGA applications  

Microsoft Academic Search

This analysis provides a preliminary investigation into using Twin-Wire Arc Thermal Spray and Cold Spray as material deposition processes for LIGA applications. These spray material processes were studied to make an initial determination of their potential as alternatives to producing mechanical parts via the electroplating process. Three materials, UltraMachinable{reg_sign} Stainless Steel, BondArc{reg_sign}, and aluminum, were sprayed using Thermal Spray. Only

MERLIN K. DECKER; MARK F. SMITH

2000-01-01

247

Micro-optical devices based on free-space optics with LIGA micro-optical benches: examples and perspectives  

Microsoft Academic Search

Microtechnology offers the possibility to fabricate photonic devices. Especially the LIGA technique allows the fabrication of micro-optical benches for free-space optical set-ups, with mounts for inserting hybrid components structured to micrometer accuracy well aligned to each other. These optical benches are not only used to build up passive optical devices but also opto-mechanical systems have been realized. Also concepts to

Juergen Mohr; Jost Goettert; Andre Mueller

1996-01-01

248

Fabrication of the 3 Dimension Resist Microstructure Using X-Ray Diffraction and Applying to LIGA Process  

NASA Astrophysics Data System (ADS)

The LIGA process consists of lithography, electroforming and molding has attracted attention in microstructure fabrication techniques. At the molding process of LIGA process, it is difficult to pull out from the mold that is assumed especially in the case of high aspect ratio structures. However, release from mold is improved by tapered structure. In this research, we have proposed a method for achieving tapered structure using the diffraction exposure technique which makes use of diffraction phenomenon. Diffraction is caused by providing a clearance between a resist structure and an X-ray mask. The fabricated structure was the lines and intermediate space whose processed depth was 200 µm and designated the taper angle of 5 degrees as set point. The variable parameters were the slit width, the X-ray dose and the gap between the X-ray mask and the resist structure. It is controlled that discovering the conditions for taper angle 5 degrees and inspecting the relationship between a taper angle and a mold releasability by electroforming and the molding of the LIGA process. We have fabricated the mold with taper angle of 2.5 degrees by electroforming. The Ni mold could partially copy the master pattern well.

Sawa, Yoshitaka; Tanabiki, Kyo; Noda, Daiji; Hattori, Tadashi

249

Wafer level hermetic package and device testing of a SOI-MEMS switch for biomedical applications  

Microsoft Academic Search

We have designed a wafer level chip scale package for a bi-stable SOI-MEMS dc switch using a silicon-glass hermetic seal with through the lid feedthroughs. Bonded at 365 °C, 230 V and 250 kg, they pass the fine\\/gross leak test after thermal cycling and mechanical shock\\/vibration according to MIL-STD-833, fulfilling the requirements for biomedical applications. The measured shear strength is

Rogier A. M. Receveur; Michael Zickar; Cornel Marxer; Vincent Larik; Nicolaas F. de Rooij

2006-01-01

250

Reaction Engineering of Through-Chip Via Filling for Wafer-Level 3D Packaging  

Microsoft Academic Search

Through-chip vias, 170 microns in depth and 10 to 35 microns in diameter were filled by electrodeposition of copper. The process was optimized for reliability and speed through a combination of process modeling, electro-analytical studies and pilot scale plating on 8-inch wafers in a commercial process unit. The approach is based on use of reverse pulses and oxygen diffusers to

D. P. Barkey; J. Callahan; A. Keigler; Z. Liu; A. Ruff; J. Trezza; B. Wu

2007-01-01

251

Determination of bending stress of Si wafer using concentrated load  

Microsoft Academic Search

The technique of concentrated load with a simple O-ring supporter is used to measure the deflection of Si wafers. The load varies so that the ratio of the deflection to the wafer thickness changes from 0 to 1. For some samples, this ratio goes up to 1.4 at which the samples are fractured. It is observed in the experiment that

L. D. Chen; M. J. Zhang; S. Zhang

1994-01-01

252

Embedded PZT Wafer Sensors for Structural Health Monitoring  

Microsoft Academic Search

Recent advances in structural integrity evaluation have led to the development of PZT wafer sensors (PWAS) which can be embedded or surface mounted for both acoustic emission (AE) and ultrasonic (UT) modes, which forms an integrated approach for Structural Health Monitoring (SHM) of aerospace structures. For the fabrication of PWAS wafers, soft PZT formulation (SP-5H Grade containing dopants like BA,

R. Gangadharan; C. R. L. Murthy; M. R. Bhat; A. Sen; N. Das; A. Seal

2007-01-01

253

Sealing of adhesive bonded devices on wafer level  

Microsoft Academic Search

In this paper, we present a low temperature wafer-level encapsulation technique to hermetically seal adhesive bonded microsystem structures by cladding the adhesive with an additional diffusion barrier. Two wafers containing cavities for MEMS devices were bonded together using benzocyclobutene (BCB). The devices were sealed by a combined dicing and self-aligning etching technique and by finally coating the structures with evaporated

Joachim Oberhammer; Frank Niklaus; Göran Stemme

2004-01-01

254

Particulate contamination removal from wafers using plasmas and mechanical agitation  

DOEpatents

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Selwyn, Gary S. (Los Alamos, NM)

1998-01-01

255

Height Inspection of Wafer Bumps Without Explicit 3-D Reconstruction  

Microsoft Academic Search

Die bonding in the semiconductor industry requires placement of solder bumps not on PCBs but on wafers. Such wafer bumps, which are much miniaturized from their counterparts on printed circuit boards (PCBs), require their heights meet rigid specifications. Yet the small size, the lack of texture, and the mirror-like nature of the bump surface make the inspection task a challenge.

Mei Dong; Ronald Chung; Edmund Y. Lam; Kenneth S. M. Fung

2010-01-01

256

Shift scheduling for steppers in the semiconductor wafer fabrication process  

Microsoft Academic Search

In this paper, an approach is proposed for scheduling stepper machines that are acting as bottleneck machines in the semiconductor wafer fabrication process. We consider the problem of scheduling the steppers for an 8 hour shift, determining which types of wafer lots to work on each machine. The scheduling objective is to find the optimal stepper allocations such that the

Sooyoung Kim; Seung-Hee Yea; Bokang Kim

2002-01-01

257

Room Temperature Si\\/Si Wafer Direct Bonding in Air  

Microsoft Academic Search

Wafer direct bonding technique offers flexible and inexpensive ways to fabricate novel semiconductor devices. But its application is much limited by high temperature process and void problem. In this study, room temperature Si\\/Si wafer direct bonding has been performed using sequential plasma pretreatment prior to bonding. A shorter O2 reactive ion etching (RIE) pretreatment (~10 s) and followed by N2

Chenxi Wang; Eiji Higurashi; T. Suga

2007-01-01

258

Alternative facility layouts for semiconductor wafer fabrication facilities  

Microsoft Academic Search

Semiconductor wafer fabrication facilities are widely acknowledged to be among the most complicated industrial systems from a production planning and control point of view. The design of most wafer fabrication facilities has followed the process layout, where similar machines are located together. This feeds to complex, reentrant product flows through the facility. In this paper, we examine the effects on

Christopher D. Geiger; Rieko Hase; Christos G. Takoudis; Reha Uzsoy

1997-01-01

259

P/N Inp Solar Cells on Ge Wafers.  

National Technical Information Service (NTIS)

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick ...

S. Wojtczuk S. Vernon E. A. Burke

1994-01-01

260

Germanium on sapphire by wafer bonding  

NASA Astrophysics Data System (ADS)

This paper describes the creation of a germanium on sapphire platform, via wafer bonding technology, for system-on-a-chip applications. Similar thermal coefficients of expansion between germanium (5.8 × 10 -6 K -1) and sapphire (5 × 10 -6 K -1) make the bonding of germanium to sapphire a reality. Germanium directly bonded to sapphire results in microvoid generation during post bond annealing. Inclusion of an interface layer such as silicon dioxide layer by plasma enhanced chemical vapour deposition, prior to bonding, results in a microvoid free bond interface after annealing. Grinding and polishing of the subsequent germanium layer has been achieved leaving a thick germanium on sapphire (GeOS) substrate. Submicron GeOS layers have also been achieved with hydrogen/helium co-implantation and layer transfer. Circular geometry transistors exhibiting a field effect mobility of 890 cm 2/V s have been fabricated onto the thick germanium on sapphire layer.

Baine, P. T.; Gamble, H. S.; Armstrong, B. M.; M cNeill, D. W.; Mitchell, S. J. N.; Low, Y. H.; Rainey, P. V.

2008-12-01

261

Wafer Inspection in the Photolithography Process  

NSDL National Science Digital Library

This is a description for a learning module from Maricopa Advanced Technology Education Center. This PDF describes the module; access may be purchased by visiting the MATEC website. In this module, your learners begin to master the sensitive after develop inspection (ADI) methods that follow photolithography. MATEC describes macro- and micro-inspection techniques and distinguishes qualitative (inspection) from quantitative (metrology) methods. The chief focus is on teaching learners to examine wafers under an optical microscope; a simulated microscope is also provided in a computer-based training (CBT) format. The module covers edge bead inspection and provides extensive practice in flash boundary inspection, including evaluating Nikon crosses, overlay boxes, scanning electronic microscope features, resolution bars, Verniers, and product identification numbers.

2012-12-03

262

Reduction of Thermal Conductivity in Wafer-Bonded Silicon  

SciTech Connect

Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

2006-11-27

263

A novel technique for cleaning semiconductor wafers using ultrasonic transducer  

NASA Astrophysics Data System (ADS)

An experiment was designed based on U.S. Patent no. 6,766,813 which describes a process that effectively cleans a semiconductor wafer with the help of ultrasonic vibrations. The semiconductor wafer was freely supported by a hollow cylindrical box made of foam. Two commonly occurring contaminants found on wafers in the industry are silicon and silicon dioxide. Micrometer sizes of these two materials were used to replicate contaminants that commonly occur in the industry. The wafer was then excited with the help of an ultrasonic transducer in the aim of knocking off these contaminants from the surface of the semiconductor wafer. Particle counts were taken with the help of a modified optical microscope before and after applying the ultrasonic vibration in order to determine the effectiveness of this technique.

Nakade, Rugved; Yow, Raylon; Sayka, Tony; Sardar, Dhiraj

2006-10-01

264

Microsystems and wafer processes for volume production of highly reliable fiber optic components for telecom and datacom-application  

Microsoft Academic Search

In realizing an efficient volume production of highly reliable active fiberoptic components the microsystem-technique was one of the most important factors. Micro-mechanical methods allow large scale fabrication of micro optical silicon lenses with methods, machines and materials using standard semiconductor wafer technology. With micromechanical processes, such as anodic bonding of optical components and special solder bonding techniques, it is possible

H. L. Althaus; W. Gramann; K. Panzer

1998-01-01

265

Rapid defect detections of bonded wafer using near infrared polariscope  

NASA Astrophysics Data System (ADS)

In modern field of microelectronics and MEMS, wafer bonding has emerged as an important processing step in wide range of manufacturing applications. During the manufacturing process, even in the modern clean room, small defects result from trapped particles and gas bubbles exist at bonded interface. Defects and trapped particles may exist on the top and bottom of the wafers, or at the interface of bonded wafer pair. These inclusions will generate high stress around debond region at the wafers bonded interface. In this paper, inspection at the bonded interface will be the interest of investigation. Since silicon wafer is opaque to visible light, defect detection at the bonded interface of silicon wafer is not possible. Due to the fact that silicon wafer is transparent to wavelength greater than 1150nm, an Near Infrared Polariscope which has showed some promises on residual stress measurement on silicon devices has been adapted and developed. This method is based on the well known photoelastic principles, where the stress variations are measured based on the changes of light propagation velocity in birefringence material. The results are compared and contrast with conventional Infrared Transmission Imaging tool (IRT) which is widely used to inspect the bonded silicon wafer. In this research, the trapped particles that are not visible via conventional infrared transmission method are identified via the generated residual stress pattern. The magnitude of the residual stress fields associated with each defect is examined qualitatively and quantitatively. The stress field generated at the wafers bonded interface will looks like a 'butterfly' pattern. Wafer pairs Pyrex-Si and Si-Si bonded interface will be examined.

Ng, Chi Seng; Asundi, Anand K.

2011-09-01

266

Photoablation characteristics of novel polyimides synthesized for high-aspect-ratio excimer laser LIGA process  

NASA Astrophysics Data System (ADS)

The photoablation properties of two soluble polyimides DMDB/6FDA and OT/6FDA with thicknesses of over 300 µm, synthesized by the polycondensation of a hexafluoropropyl group contained in a dianhydride with two kinds of diamines, are investigated using a 248 nm krypton fluoride (KrF) laser. The incorporation of the hexafluoropropyl group into the chemical structure gives these two polyimides higher etching rates than Kapton (a commercial polyimide film which is difficult to dissolve). The etching rates of synthesized polyimides are about 0.1-0.5 µm/pulse over a fluence range of 0.25-2.25 J cm-2. The photothermal mechanism for DMDB/6FDA contributes about 19% of etching depth at a laser fluence of 0.82 J cm-2. Moreover, the number of laser pulses seriously affects the taper angle of microstructures, especially at low fluence. Near-vertical side-wall structures can be built at high fluence (~2 J cm-2). Fresnel patterns with a thickness of 300 µm and a linewidth of 10 µm were fabricated, with an attainable aspect ratio of around 30. After photoablation, the complementary metallic microstructures were also fabricated by a sequential electroplating procedure. Then, those two new polyimides could be dissolved easily in most common solvents (such as THF, DMSO, NMP and DMF). These results indicate that these two soluble polyimides are highly suitable for use in the KrF laser LIGA process.

Yang, Chii-Rong; Hsieh, Yu-Sheng; Hwang, Guang-Yeu; Lee, Yu-Der

2004-04-01

267

The influence of feature sidewall tolerance on minimum absorber thickness for LIGA x-ray masks  

SciTech Connect

Minimizing mask absorber thickness is an important practical concern in producing very small features by the LIGA process. To assist in this minimization, the authors have developed coupled numerical models describing both the exposure and development of a thick PMMA resist. The exposure model addresses multi-wavelength, one-dimensional x-ray transmission through multiple beam filters, through the mask substrate and absorber, and the subsequent attenuation and photon absorption in the PMMA resist. The development model describes one-dimensional dissolution of a feature and its sidewalls, taking into account the variation in absorbed dose through the PMMA thickness. These exposure and development models are coupled in a single interactive code, permitting the automated adjustment of mask absorber thickness to yield a prescribed sidewall taper or dissolution distance. They have used this tool to compute the minimum required absorber thickness yielding a prescribed sidewall tolerance for exposures performed at the ALS, SSRL and NSLS synchrotron sources. Results are presented as a function of the absorbed dose for a range of the prescribed sidewall tolerance, feature size, PMMA thickness, mask substrate thickness and the development temperature.

S. K. Griffiths; J. M. Hruby; A. Ting

1999-02-01

268

Bubble-Free Silicon Wafer Bonding in a Non-Cleanroom Environment  

Microsoft Academic Search

Bubble-free bonding of 4-inch silicon wafers on either silicon or quartz wafers is achieved outside a cleanroom. Two wafers are stacked horizontally in a rack with the two mirror-polished surfaces facing each other. In order to avoid wafer contact during hydrophilization, cleaning, and drying, the wafers are separated in the rack by teflon spacers introduced at the wafer edges. After

R. Stengl; K.-Y. Ahn; U. Gösele

1988-01-01

269

Double exposure as a method to correct on-wafer CD variations: a proposal  

NASA Astrophysics Data System (ADS)

Keeping across-field CD variation on the wafer within the tight limits imposed by 28nm and other advanced technologies is a challenge, particularly in a foundry where designs of different customers are realized. We propose a cost-efficient, fast, and flexible method to improve CD uniformity and correct reticle or design-induced variation, by applying a second exposure to the wafer, in the form of a grey scale map created with a low grade correction reticle. Compared to CD correction by subsequent modification of the primary reticle, this method has the potential of much higher spatial resolution and simpler logistics, which make it an attractive alternative especially for prototyping and lowvolume production.

Hotzel, Arthur; Bald, Holger

2012-02-01

270

Techniques for the evaluation of outgassing from polymeric wafer pods  

SciTech Connect

In recent years there has been increasing interest in using wafer-level isolation environments or pods (microenvironments) to provide a more controllable, cleaner wafer environment during wafer processing. It has been shown that pods can be effective in reducing the amount of particulate contamination on wafers during manufacturing. However, there have also been studies that indicate that pods and wafer boxes can be the source of condensible, molecular organic contamination. This paper summarizes the work that has been performed during the past year at Sandia National Laboratories` Contamination Free Manufacturing Research Center (CFMRC) on (1) devising standard, low-temperature, high sensitivity techniques to detect outgassing of volatile organic compounds (VOCs) from polymers used to construct wafer pods and (2) development of a technique that can be used to continuously measure the condensible contamination within pods so that the pod environment can be monitored during manufacturing. Although these techniques have been developed specifically for assessing contamination threats from wafer pods, they can be used to evaluate other potential contamination sources. The high sensitivity outgassing techniques can be used to evaluate outgassing of volatiles from other clean-room materials and the real-time outgassing sensor can be used to monitor contamination condensation in non-pod environments such as ballroom-type cleanrooms and minienvironments.

McIntyre, D.C.; Liang, A.; Thornberg, S.M.; Bender, S.F.; Lujan, R.D.; Blewer, R.S. [Sandia National Labs., Albuquerque, NM (United States); Bowers, W.D. [Femtometrics, Costa Mesa, CA (United States)

1994-03-01

271

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.  

PubMed

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association J Pharm Sci. PMID:24700434

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

272

Wafer-level vacuum/hermetic packaging technologies for MEMS  

NASA Astrophysics Data System (ADS)

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

273

Optima XE Single Wafer High Energy Ion Implanter  

SciTech Connect

The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny [Axcelis Technologies, Inc. 108 Cherry Hill Drive, Beverly, MA 01915 (United States)

2008-11-03

274

Extraction and Analysis of Noise Parameters of On Wafer HEMTs up to 26.5 GHz  

SciTech Connect

This paper presents a procedure for extracting the four noise parameters of on wafer scaled HEMTs based on AlGaAs/GaAs heterostructure. This procedure relies on 50-{omega} noise figure measurements up to 26.5 GHz by determining the equivalent temperatures associated to the intrinsic resistances of the small signal equivalent circuit. The non-quasi-static effect associated to the gate-drain resistance R{sub gd} is accounted for by the noise model. A good agreement between measured and simulated noise figure is obtained and scaling of the noise parameters is reported.

Caddemi, Alina; Crupi, Giovanni; Macchiarella, Alessio [Dipartimento di Fisica della Materia e Ingegneria Elettronica, University of Messina, Salita Sperone 31, 98166-Messina (Italy)

2009-04-23

275

On-Wafer Testing of Circuits Through 220 GHz  

NASA Technical Reports Server (NTRS)

We have jointly developed the capability to perform on-wafer s-parameter and noise figure measurements through 220 GHz. S-parameter test sets have been developed covering full waveguide bands of 90-140 GHz (WR-08) and 140-220 GHz (WR-05). The test sets have been integrated with coplanar probes to allow accurate measurements on-wafer. We present the design and performance of the test sets and wafer probes. We also present calibration data as well as measurements of active circuits at frequencies as high as 215 GHz.

Gaier, Todd; Samoska, Lorene; Oleson, Charles; Boll, Greg

1999-01-01

276

The uses of Man-Made diamond in wafering applications  

NASA Technical Reports Server (NTRS)

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Fallon, D. B.

1982-01-01

277

Arthroscopic wafer procedure for ulnar impaction syndrome.  

PubMed

Ulnar impaction syndrome is abutment of the ulna on the lunate and triquetrum that increases stress and load, causing ulnar-sided wrist pain. Typically, ulnar-positive or -neutral variance is seen on a posteroanterior radiograph of the wrist. The management of ulnar impaction syndrome varies from conservative, symptomatic treatment to open procedures to shorten the ulna. Arthroscopic management has become increasingly popular for management of ulnar impaction with ulnar-positive variance of less than 3 mm and concomitant central triangular fibrocartilage complex tears. This method avoids complications associated with open procedures, such as nonunion and symptomatic hardware. The arthroscopic wafer procedure involves debridement of the central triangular fibrocartilage complex tear, along with debridement of the distal pole of the ulna causing the impaction. Debridement of the ulna arthroscopically is taken down to a level at which the patient is ulnar neutral or slightly ulnar negative. Previous studies have shown good results with relief of patient symptoms while avoiding complications seen with open procedures. PMID:24749031

Colantoni, Julie; Chadderdon, Christopher; Gaston, R Glenn

2014-02-01

278

Arthroscopic Wafer Procedure for Ulnar Impaction Syndrome  

PubMed Central

Ulnar impaction syndrome is abutment of the ulna on the lunate and triquetrum that increases stress and load, causing ulnar-sided wrist pain. Typically, ulnar-positive or -neutral variance is seen on a posteroanterior radiograph of the wrist. The management of ulnar impaction syndrome varies from conservative, symptomatic treatment to open procedures to shorten the ulna. Arthroscopic management has become increasingly popular for management of ulnar impaction with ulnar-positive variance of less than 3 mm and concomitant central triangular fibrocartilage complex tears. This method avoids complications associated with open procedures, such as nonunion and symptomatic hardware. The arthroscopic wafer procedure involves debridement of the central triangular fibrocartilage complex tear, along with debridement of the distal pole of the ulna causing the impaction. Debridement of the ulna arthroscopically is taken down to a level at which the patient is ulnar neutral or slightly ulnar negative. Previous studies have shown good results with relief of patient symptoms while avoiding complications seen with open procedures.

Colantoni, Julie; Chadderdon, Christopher; Gaston, R. Glenn

2014-01-01

279

Application of EEM fluorescence spectroscopy in understanding of the "LIGA" phenomenon in the Bay of Biscay (France)  

NASA Astrophysics Data System (ADS)

Marine mucilage is present in all oceans over the world, and in particular in the Mediterranean Sea and in the Pacific Ocean. Surface water warming and hydrodynamic processes can favor the coalescence of marine mucilage, large marine aggregates representing an ephemeral and extreme habitat for biota. DOM is a heterogeneous, complex mixture of compounds, including extracellular polymeric substances (EPS), with wide ranging chemical properties and it is well known to interact with pollutants and to affect their transport and their fate in aquatic environment. The LIGA French research program focuses on tracing colloidal dissolved organic matter (DOM) sources and cycling in the Bay of Biscay (South Western French coast). This ephemeral phenomenon (called "LIGA" in the South West of France) has been observed more than 750 times since 2010. It presents a great ecological impact on marine ecosystems and has been shown to be concomitant with the development of pathogen organisms. A one-year intensive survey of fluorescent DOM was undertaken. From April 2013 until May 2014, water samples were monthly collected from the Adour River (main fresh water inputs) and from 2 sites in the Bay of Biscay at 3 depths of the water column (surface water, at the maximum of chlorophyll-a, and deep water). Moreover, intensified samplings took place from the appearance of the phenomenon twice a week during 4 weeks. UV/visible absorbance and excitation emission matrix (EEM) fluorescence spectroscopy combined with PARAFAC and PCA analyses have been used to characterize colloidal DOM in the Bay of Biscay in order to estimate DOM sources as well as spatial and temporal variability of DOM properties. The preliminary results, obtained for about 70 samples of this survey, have already highlighted spatial and temporal variations of DOM optical properties and a peculiar fluorescent component (exc300nm/em338nm) was detected while the LIGA phenomenon arises. The appearance of this specific fluorescence signal seems to be correlated with high freshwater and terrestrial DOM inputs combined with physical forcing (flows, swell) as well as a rise in temperature and sunshine. This work already allowed us to identify different sources of colloidal DOM in the Bay of Biscay and highlighted a specific fingerprint of the LIGA phenomenon. The combination of EEM fluorescence spectroscopy with PARAFAC and PCA analyses appears thus to be a very powerful tool for the long term monitoring of such a phenomenon and would be very useful for a better understanding of the biogeochemical processes in marine environments and of the marine colloidal DOM ecodynamics.

Parot, Jérémie; Susperregui, Nicolas; Rouaud, Vanessa; Dubois, Laurent; Anglade, Nathalie; Parlanti, Edith

2014-05-01

280

Scales  

ScienceCinema

Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain — a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

281

Scales  

SciTech Connect

Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain — a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

Murray Gibson

2007-04-27

282

Scales  

ScienceCinema

Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain ? a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

Murray Gibson

2010-01-08

283

Particle deposition on silicon wafers during wet cleaning processes  

NASA Astrophysics Data System (ADS)

A model of particle contamination on Si wafers during wet cleaning processes has been established. This model takes into account both the van der Waals and electrostatic forces and has the particularity of assimilating the particles to pin-point charges subjected to the electrical field generated by the wafers. The hydrodynamics generated by the passage of the wafers through the air-liquid interface is also taken into account. This approach highlights two contamination mechanisms: at the air-liquid interface and within the solution and also the physical parameters controlling the depositions. All of these parameters were characterized in water for specific particles (C, Si3N4, SiO2, SiC, Al2O3) and specific wafers (p-doped, (100) oriented, with hydrophilic and hydrophobic surfaces). These measurements enabled qualitative forecasts of interface particle contamination and quantitative forecasts of particle contamination in solution to be obtained.

Mouche, L.; Tardif, F.; Derrien, J.

1994-06-01

284

Positron studies of plasma-treated silicon wafers  

NASA Astrophysics Data System (ADS)

Wafers of silicon treated with rf oxygen and hydrogen plasma have been studied with the Herodotus slow positron beam. Doppler broadening measurements reveal the influence of temperature and time on defect profiles beneath the surfaces.

van der Werf, D. P.; Nathwani, M.; Towner, A.; Taylor, J. W.; Morton, R.; Knights, A. P.; Rice-Evans, P. C.; Szekeres, A.

1997-05-01

285

Photoelastic characterization of Si wafers by scanning infrared polariscope  

NASA Astrophysics Data System (ADS)

A small amount of birefringence caused by the photoelastic effect from residual strains, crystal-defects-induced strains, and process-induced strains in Si wafers has been measured by using an improved version of a scanning infrared polariscope (SIRP). The SIRP presented here has high sensitivity sufficient to detect the small amount of strain induced near the wafer-supporting finger by the wafer weight itself. It is found that an anomalous amount of strain is induced by slip-line generation during the thermal process and also that a concentric ring pattern of strain is induced by OSF rings. From these results, it is suggested that SIRP is very useful for Si wafer inspection and Si process evaluation in various phases.

Fukuzawa, M.; Yamada, M.

2001-07-01

286

Mask contribution to intra-field wafer overlay  

NASA Astrophysics Data System (ADS)

Shrinking wafer overlay budgets raise the importance of careful characterization and control of the contributing components, a trend accelerated by multi-patterning immersion lithography [1]. Traditionally, the mask contribution to wafer overlay has been estimated from measurement of a relatively small number of standard targets. There are a number of studies on test masks and standard targets of the impact of mask registration on wafer overlay [2],[3]. In this paper, we show the value of a more comprehensive characterization of mask registration on a product mask, across a wide range of spatial frequencies and patterns. The mask measurements will be used to obtain an accurate model to predict mask contribution to wafer overlay and correct for it.

Chou, William; Chang, Hsien-Min; Chen, Chao Yin; Wagner, M.; Roeth, K.-D.; Czerkas, S.; Ferber, M.; Daneshpanah, M.; Laske, F.; Chiang, R.; Klein, S.

2014-04-01

287

Efficient data transmission from silicon wafer strip detectors  

SciTech Connect

An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

1991-01-01

288

Efficient data transmission from silicon wafer strip detectors  

SciTech Connect

An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

1991-12-31

289

Proceedings of the Low-Cost Solar Array Wafering Workshop  

NASA Technical Reports Server (NTRS)

The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

Morrison, A. D.

1982-01-01

290

9nm node wafer defect inspection using visible light  

NASA Astrophysics Data System (ADS)

Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

Zhou, Renjie; Edwards, Chris; Popescu, Gabriel; Goddard, Lynford L.

2014-04-01

291

A silicon wafer packaging solution for HB-LEDs  

Microsoft Academic Search

In this paper we present HyLED, a silicon wafer packaging solution for high-brightness LEDs. The associated technology is batch micro-machining\\/metallisation processing of silicon wafers allowing significant reduction of the final device size. The presented package is multi-functional where the micro-machined cavity acts as reflector, thermal conductor and reservoir for the silicone\\/colour conversion substance. The base material, silicon, has excellent mechanical

Tom Murphy; Steen Weichel; Steven Isaacs; Jochen Kuhmann

2007-01-01

292

Surface integrity of silicon wafers in ultra precision machining  

Microsoft Academic Search

Silicon wafers are the most extensively used material for integrated circuit (IC) substrates. Before taking the form of a\\u000a wafer, a single crystal silicon ingot must go through a series of machining processes, including slicing, lapping, surface\\u000a grinding, edge profiling, and polishing. A key requirement of the processes is to produce extremely flat surfaces on work\\u000a pieces up to 350 mm

H. T. Young; H. T. Liao; H. Y. Huang

2006-01-01

293

Porous silicon optical microcavity biosensor on silicon-on-insulator wafer for sensitive DNA detection.  

PubMed

Silicon-on-insulator (SOI) wafer is one of the most appealing platforms for optical integrated circuit with the potential to realize high performance Ultra Large Scale Integration (ULSI) and device miniaturization. In this work, based on simulations to obtain appropriate optical properties of a porous silicon microcavity (PSM), we successfully fabricated a highly efficient PSM on SOI wafer by electrochemical etching for DNA detection at optical wavelength 1555.0 nm. The narrow resonance peak with a full width at half maximum about 26.0 nm in the reflectance spectrum gives a high Q factor which causes high sensitivity for sensing performance. The sensitivity of this sensor is investigated through 19-base pair DNA hybridization in the PSM by surface modification using a standard cross link chemistry method. The red shift of the reflectance spectra shows a good linear relationship with complementary DNA concentration, ranging from 0.625 to 12.500 ?M, and the detection limit is 43.9 nM. This optical PSM on SOI is highly sensitive, fast responsive, easy to fabricate and low-costly, that will broadly benefit to develop a new optical label-free biosensor on SOI wafer and has a great potential for biochips based on integrated optical devices. PMID:23395728

Zhang, Hongyan; Jia, Zhenhong; Lv, Xiaoyi; Zhou, Jun; Chen, Liangliang; Liu, Rongxia; Ma, Ji

2013-06-15

294

Power-scalable 1.57 microm mode-locked semiconductor disk laser using wafer fusion.  

PubMed

We report the first (to our knowledge) wafer-fused high-power passively mode-locked semiconductor disk laser operating at 1.57 microm wavelength. An InP-based active medium was fused with GaAs/AlGaAs distributed Bragg reflector on a 2 inch wafer level, resulting in an integrated monolithic gain mirror. An intracavity wedged diamond heat-spreader capillary bonded to the gain chip provides efficient heat removal from the gain structure without disturbing the spectrum of the mode-locked laser. The laser produces over 0.6 W of average output power at 15 degrees C with 16 ps pulse width. The total output power accounting for all output beams emerging from the cavity was 0.86 W. The results reveal an essential advantage of wafer fusion processing of disparate materials over monolithically grown InP-based gain structures and demonstrate the high potential of this technique for power scaling of long-wavelength semiconductor disk lasers. PMID:19838252

Saarinen, Esa J; Puustinen, Janne; Sirbu, Alexei; Mereuta, Alexandru; Caliman, Andrei; Kapon, Eli; Okhotnikov, Oleg G

2009-10-15

295

Monitoring Dielectric Thin-Film Production on Product Wafers Using Infrared Emission Spectroscopy  

SciTech Connect

Monitoring of dielectric thin-film production in the microelectronics industry is generally accomplished by depositing a representative film on a monitor wafer and determining the film properties off line. One of the most important dielectric thin films in the manufacture of integrated circuits is borophosphosilicate glass (BPSG). The critical properties of BPSG thin films are the boron content, phosphorus content and film thickness. We have completed an experimental study that demonstrates that infrared emission spectroscopy coupled with multivariate analysis can be used to simultaneous y determine these properties directly from the spectra of product wafers, thus eliminating the need of producing monitor wafers. In addition, infrared emission data can be used to simultaneously determine the film temperature, which is an important film production parameter. The infrared data required to make these determinations can be collected on a time scale that is much faster than the film deposition time, hence infrared emission is an ideal candidate for an in-situ process monitor for dielectric thin-film production.

NIEMCZYK,THOMAS M.; ZHANG,SONGBIAO; HAALAND,DAVID M.

2000-12-18

296

Nanoscale friction and wear properties of silicon wafer under different lubrication conditions  

NASA Astrophysics Data System (ADS)

The nanoscale friction and wear properties of single crystal silicon wafer under different lubrication conditions are studied in this paper. The experiments were performed with Si3N4 ball sliding on the surface of silicon wafer under four different lubrication conditions: dry friction, water lubrication, hydrogen peroxide lubrication and the static hydrogen peroxide dry friction. The results from the experiments have been analyzed showing the different friction and wear properties of the silicon wafer in different lubrication conditions. It is concluded that the wear rates under the water lubrication and under the hydrogen peroxide lubrication are both small, the chemical reactions are facilitated by the mechanical processes when the load and the sliding speed reach certain levels. This is mainly resulted by the enhanced lubricant performance with the formed silicon hydroxide Si(OH)4 film. Under the water lubrication, the wear is found in a way of material removed in molecule scale. Under the hydrogen peroxide lubrication, the wear is mainly caused by the spalling of micro-cracks. Under the dry friction condition, the wear is found being adhesive wear. And under the static peroxide dry friction, the wear is prevailing adhesive wear. These results are essential and valuable to the development of the efficient and environmental-friendly slurry for the chemical mechanical polishing (CMP) process.

Chen, Xiaochun; Zhao, Yongwu; Wang, Yongguang; Zhou, Hailan; Ni, Zhifeng; An, Wei

2013-10-01

297

Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

2012-11-01

298

SUEX process optimization for ultra-thick high-aspect ratio LIGA imaging  

NASA Astrophysics Data System (ADS)

The focus of this paper is on the use of SUEX Thick Dry Film Sheet (TDFS) laminates which DJ DevCorp is developing as a thick resist material in optical and X-ray lithography. Preliminary thick dry film sheets up to 1mm thickness were successfully prepared and patterned at the CAMD X-ray beamlines and presented at HARMST 2007. Recently, new results have been published using SUEX resist sheets in UV lithography showing great market potential including plating molds for metal microparts, polymer MEMS, multilayer microfluidics structures, BioMEMS, medical devices, wafer level packaging processes, and displays. The SUEX TDFS are available in a range of thicknesses from 100?m to 1mm or more and are pre-cut into a number of standard wafer sizes. This new material is a modified epoxy formulation containing an antimony-free photo acid generator (PAG) prepared under a highly controlled solvent-less process which provides uniform coatings between two throw-away layers of protective polyester film. As part of our initial studies resist layers of 250, 500 and 1000?m were laminated onto regular silicon wafers using a hot roll laminator at a speed of 1ft/min at 75°C. The entire substrate preparation takes about 1 hour and with practice users can prepare up to 10 substrates in this time which are typically ready to use within 2 hours. In our efforts to develop a commercially viable product we have conducted experiments using standard equipment available at CAMD (Quintel UV aligner and CAMD XRLM 1 and 4 beamline). Initial X-ray exposure tests were done with a bottom dose ranging between 100 and 400 J/cm3 and a top/bottom dose ratio of less than 3 for sheets up to 2mm in thickness. Exposure time for typical conditions of the CAMD storage ring (ring current ranging between 100 and 160mA, beam lifetime of about 10hrs at 100mA ring current) is about 10-15min for a 4' wafer. After exposure the samples were immediately post exposure baked between 70°C and 110°C using a convection oven, taken out and cooled to RT then relaxed up to 3 days before development to reduce stress. Development was done in PGMEA for up to 3 hours for the 1000?m thick samples followed by a short IPA rinse and drying in air. Very high aspect ratios of 100 or more have been routinely patterned with nearly perfectly straight sidewalls (~1-1.5?m deviation for a 1mm tall structure) and excellent image fidelity.

Johnson, Donald W.; Goettert, Jost; Singh, Varshni; Yemane, Dawit

2011-03-01

299

Using Multiple Implant Regions To Reduce Development Wafer Usage  

NASA Astrophysics Data System (ADS)

The cost of new process development has risen significantly with larger wafer sizes and the increased number of fabrication steps needed to create advanced devices. The high value of each 300 mm development wafer has spurred efforts to find a way to explore more than a single process setting with each wafer. Traditional methods of defining multiple spatially distinct implant regions on a single wafer achieve poor utilization of device die. The need for efficient utilization of the die and wide process latitude for defining multiple implant regions per wafer has led to the development of an implant proximity mask (vMask™), which permits sharply defined borders between implant regions that may have different species, energy, angle, or dose. The capability of this system to achieve multiple spatially resolved implant conditions per wafer with high die utilization and using the same process parameters as production implants will be described. Specifically, results for measurement of the uniform process area, process repeatability, and cleanliness will illustrate the potential of this technique to dramatically reduce implant process development costs.

Walther, S. R.; Falk, S.; Mehta, S.; Erokhin, Y.; Nunan, P.

2006-11-01

300

Thermomechanical global response of the EUVL wafer during exposure  

NASA Astrophysics Data System (ADS)

Extreme ultraviolet lithography (EUVL) is one of the leading technologies for Next-Generation Lithography. Continued progress in its development will be facilitated by characterizing all sources of distortion in the chip fabrication process. These include the thermal distortions of the wafer caused by deposited EUVL energy during scanning exposure. Absorbed energy from the beam produces temperature increases and structural displacements in the wafer, which directly contribute to pattern placement errors and image blur. Because of the vacuum conditions of EUVL systems, wafer chucking will be electrostatic, which has a number of advantages over mechanical clamping systems. The goals of this research are to predict the transient temperature increases and corresponding displacements (locally and globally) consistent with the thermomechanical boundary conditions of the wafer. Both thermal and structural finite element models were constructed to numerically simulate wafer exposure. The response of the wafer is relatively sensitive to the interface conditions between the substrate and electrostatic chuck. Thus, parametric studies of the response to changes in the contact conductance and the friction coefficient were performed and are presented in this paper.

Chang, Jaehyuk; Martin, Carl J.; Engelstad, Roxann L.; Lovell, Edward G.

2002-07-01

301

Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis  

SciTech Connect

This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

Tobin, K.W.

2003-05-22

302

High aspect ratio through-wafer interconnections for 3D-microsystems  

Microsoft Academic Search

Closely spaced, through-wafer interconnects are of large interest in RF MEMS and MEMS packaging. In this paper, a suitable technique to realize large arrays of small size through-wafer holes is presented. This approach is based on macroporous silicon formation in combination with wafer thinning. Very high aspect ratio (? 100) structures are realized. The wafers containing the large arrays of

L. Wang; A. Nichelatti; H. Schellevis; C. de Boer; C. Visser; T. N. Nguyen; P. M. Sarro

2003-01-01

303

Strategy and metrics for wafer handling automation in legacy semiconductor fab  

Microsoft Academic Search

We present a systematic approach for converting a legacy wafer fab from manual wafer handling to fully automatic wafer handling. Our strategy began by quantifying the need for automation in terms of impact on die yield, identifying a seven percent die loss associated with scratches from wafer handling. We then addressed the fundamental changes in production equipment and processes as

R. L. Guldi; D. E. Paradis; M. T. Whitfield; F. D. Poag; D. P. Jensen

1999-01-01

304

Electrochemical method for defect delineation in silicon-on-insulator wafers  

DOEpatents

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, Terry R. (Albuquerque, NM); Jones, Howland D. T. (Albuquerque, NM); Kelly, Michael J. (Albuquerque, NM); Medernach, John W. (Albuquerque, NM); Stevenson, Joel O. (Albuquerque, NM); Tsao, Sylvia S. (Albuquerque, NM)

1991-01-01

305

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.  

PubMed

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging. PMID:22966554

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

306

Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications  

Microsoft Academic Search

Among the many 3D technology options that are being explored today, the 3D-stacked IC approach has become a mature and economically viable technology and provides the highest density for 3D interconnects to date. One approach for IC stacking pursued by imec is the integration of Through Silicon Vias with extreme wafer thinning and backside processing on full CMOS wafers. This

Anne Jourdain; Thibault Buisson; Alain Phommahaxay; Augusto Redolfi; Sarasvathi Thangaraju; Youssef Travaly; Eric Beyne; Bart Swinnen

2011-01-01

307

Applications of the silicon wafer direct-bonding technique to electron devices  

NASA Astrophysics Data System (ADS)

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Furukawa, K.; Nakagawa, A.

1989-11-01

308

Improving on-wafer CD correlation analysis using advanced diagnostics and across-wafer light-source monitoring  

NASA Astrophysics Data System (ADS)

With the implementation of multi-patterning ArF-immersion for sub 20nm integrated circuits (IC), advances in equipment monitoring and control are needed to support on-wafer yield performance. These in-situ equipment monitoring improvements, along with advanced litho-cell corrections based on on-wafer measurements, enable meeting stringent overlay and CD control requirements for advanced lithography patterning. The importance of light-source performance on lithography pattering (CD and overlay) has been discussed in previous publications.[1-3] Recent developments of Cymer ArF light-source metrology and on-board monitoring enable end-users to detect, for each exposed wafer, changes in the near-field and far-field spatial profiles and polarization performance, [4-6] in addition to the key `optical' scalar parameters, such as bandwidth, wavelength and energy. The major advantage of this capability is that the key performance metrics are sampled at rates matched to wafer performance, e.g. every exposure field across the wafer, which is critical for direct correlation with on-wafer performance for process control and excursion detection.

Alagna, Paolo; Zurita, Omar; Rechtsteiner, Gregory; Lalovic, Ivan; Bekaert, Joost

2014-04-01

309

Wafer-Level Packaging for RF Applications Using High-Resistivity Polycrystalline Silicon Substrate Technology  

Microsoft Academic Search

High-resistivity polycrystalline silicon (HRPS) wafers are explored as a novel low-cost and low-loss substrate in Wafer-Level Chip-Size Packaging (WLCSP) for RF applications. The WLCSP solution we demonstrate is based on adhesive bonding of a HRPS wafer to a silicon wafer with active devices. After bonding, the IC wafer is thinned below 50 µm and selectively removed to expose its front-side

A. Polyakov; S. Sinaga; P. M. Mendes; M. Bartek; J. H. Correia; J. N. Burghartz

310

Determination of surface roughness of InP (001) wafers by x-ray scattering  

NASA Astrophysics Data System (ADS)

The surface roughness of polished InP (001) wafers were examined by x-ray reflectivity and crystal truncation rod (CTR) measurements. The root-mean-quare roughness and the lateral correlation scale were obtained by both methods. The scattering intensities in the scans transverse to the specular reflection rod were found to contain two components. A simple surface model of surface faceting is proposed to explain the experimental data. The sensitivities of the two methods to the surface structure and the role of the resolution functions in the CTR measurements are discussed.

Cui, S. F.; Li, J. H.; Li, M.; Li, C. R.; Gu, Y. S.; Mai, Z. H.; Wang, Y. T.; Zhuang, Y.

1994-10-01

311

100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices  

SciTech Connect

A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

OLIVER,ANDREW D.; MATZKE,CAROLYN M.

2000-04-06

312

40 Gbit/s silicon modulators fabricated on 200-mm and 300-mm SOI wafers  

NASA Astrophysics Data System (ADS)

We present 40 Gbit/s optical modulators based on different types of phase shifters (lateral pn, pipin, and interleaved pn junction phase). Those structures were processed both on 200 and 300mm SOI wafers, available in large-scale microelectronic foundries. Both Ring Resonators (RR) and Mach Zehnder (MZ) modulators were fabricated. As an example, MZ modulator based on 0.95 mm long interleaved pn junction phase shifter delivered a high ER of 7.8 dB at 40 Gbit/s with low optical loss of only 4 dB. Ring modulator was also fabricated and characterized at high-speed, exhibiting 40 Gbit/s.

Marris-Morini, Delphine; Baudot, Charles; Fédéli, Jean-Marc; Rasigade, Gilles; Vuillet, Nathalie; Souhaité, Aurélie; Ziebell, Melissa; Rivalin, Pierette; Olivier, Ségolène; Crozat, Paul; Bouville, David; Menezo, Sylvie; Boeuf, Frédéric; Vivien, Laurent

2014-03-01

313

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?  

NASA Astrophysics Data System (ADS)

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Green, Martin A.

2014-03-01

314

Microwave Induced Direct Bonding of Single Crystal Silicon Wafers  

NASA Technical Reports Server (NTRS)

We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

Budraa, N. K.; Jackson, H. W.; Barmatz, M.

1999-01-01

315

Interferometric and confocal techniques for testing of silicon wafers  

NASA Astrophysics Data System (ADS)

The paper provides new insights into Silicon wafer measurements in context of technological problems of developing a sophisticated measurement technique, which harnesses helium atom beam as a probe. Nano-resolution imaging techniques such as scanning tunnelling microscopy (STM) and atomic force microscopy (AFM) are well-know in surface science. A scanning helium atom microscope, where a focused beam of low energy, neutral helium atoms is used as an imaging probe is a new concept creating non-destructive and non-invasive surface investigation tool in science and industry. This paper is focused on measurements of flatness and thickness of the wafer, which is used as a deflecting mirror of the helium beam. Two -optics based- measurement techniques are presented: scanning confocal system and the Fizeau interferometer. The latter is applied as a quick reference device placed close to the production line whereas the former offers high accuracy flatness and thickness maps of the wafers.

Galas, J.; Litwin, D.; Sitarek, S.; Surma, B.; Piatkowski, B.; Miros, A.

2006-05-01

316

Wafer bonding using microwave heating of parylene intermediate layers  

NASA Astrophysics Data System (ADS)

This paper describes a novel wafer bonding technique using microwave heating of parylene intermediate layers. The bonding is achieved by parylene deposition and thermal lamination using microwave heating. Variable frequency microwave heating provides uniform, selective and rapid heating for parylene intermediate layers. The advantages of this bonding technique include short bonding time, low bonding temperature, relatively high bonding strength, less void generation and low thermal stress. In addition, the intermediate layer material, parylene, is chemically stable and biocompatible. This bonding technique can be used for structured wafers also because parylene provides a conformal coating. Therefore, this is a very attractive bonding tool for many MEMS devices. The bonding strength and uniformity were evaluated using diverse tools. Fracture mechanisms and the effects of bonding parameters and an adhesion promoter were also investigated. The bonding with a structured wafer was also successfully demonstrated.

Noh, Hong-seok; Moon, Kyoung-sik; Cannon, Andrew; Hesketh, Peter J.; Wong, C. P.

2004-04-01

317

Monitoring of acoustic emission activity using thin wafer piezoelectric sensors  

NASA Astrophysics Data System (ADS)

Acoustic emission (AE) is a well-known technique for monitoring onset and propagation of material damage. The technique has demonstrated utility in assessment of metallic and composite materials in applications ranging from civil structures to aerospace vehicles. While over the course of few decades AE hardware has changed dramatically with the sensors experiencing little changes. A traditional acoustic emission sensor solution utilizes a thickness resonance of the internal piezoelectric element which, coupled with internal amplification circuit, results in relatively large sensor footprint. Thin wafer piezoelectric sensors are small and unobtrusive, but they have seen limited AE applications due to low signal-to-noise ratio and other operation difficulties. In this contribution, issues and possible solutions pertaining to the utility of thin wafer piezoelectrics as AE sensors are discussed. Results of AE monitoring of fatigue damage using thin wafer piezoelectric and conventional AE sensors are presented.

Trujillo, Blaine; Zagrai, Andrei; Meisner, Daniel; Momeni, Sepand

2014-03-01

318

Optical evaluation of ingot fixity in semiconductor wafer slicing  

NASA Astrophysics Data System (ADS)

The fixity of an ingot may greatly affect the quality of wafers produced during a wire saw process and improved mechanical clamping is a means for improving ingot fixity. Here, an optical technique that is based on laser beam deflection is described. The technique was demonstrated on ingot assemblies subjected to impulse loads within a prescribed range using an original and improved clamping system. The technique revealed that the ingot assembly had lower degrees of mean displacement and standard displacement deviation under the improved clamping system. The data on warp obtained from the actual production of wafers corroborates this finding. The technique described is an effective method of quantitatively evaluating the fixity of ingots in a wafer wire saw process.

Ng, T. W.; Nallathamby, R.

2004-11-01

319

Characterizing SOI Wafers By Use Of AOTF-PHI  

NASA Technical Reports Server (NTRS)

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

320

Microsystems and wafer processes for volume-production of highly reliable fiber optic components for telecom and datacom-application  

Microsoft Academic Search

In development and fabrication of highly reliable active fiber optic components, first the application of great fields of microsystem techniques enabled the breakthrough in volume-production. Micro-mechanical methods allowed the big scale fabrication of microoptical silicon lenses with methods, machines and materials of the semiconductor technology on wafer. With the simultaneous application of micro-mechanical methods, such as anodic bonding processes of

Hans L. Althaus; Wolfgang Gramann; K. Panter

1997-01-01

321

450mm wafer patterning with jet and flash imprint lithography  

NASA Astrophysics Data System (ADS)

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

322

Digital model planning and computerized fabrication of orthognathic surgery wafers.  

PubMed

Conventional orthognathic wafers are made by a process involving manual movement of stone dental models and acrylic laboratory fabrication. In addition, a facebow record and semi-adjustable articulator system are required for maxillary osteotomy cases. This paper introduces a novel process of producing both intermediate and final orthognathic surgical wafers using a combination of computerized digital model simulation and three-dimensional print fabrication, without the need for either a facebow record or the additional ionizing radiation exposure associated with cone beam computerized tomography. PMID:24235100

Cousley, Richard R J; Turner, Mark J A

2014-03-01

323

Wafer CD variation for random units of track and polarization  

NASA Astrophysics Data System (ADS)

After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle MTT and wafer intra-field MTT is shown for ENG process without polarization. The influence of different exposure conditions - with and without polarization of scanner laser source - on the average CD value for isolated and dense structures is demonstrated.

Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

2012-03-01

324

Computationally Efficient Modeling of Wafer Temperatures in an LPCVD Furnace  

Microsoft Academic Search

ABSTRACT This paper,presents a new,first principles thermal,model,to predict wafer temperatures,within a hot-wall Low Pressure Chemical,Vapor Deposition (LPCVD) furnace based,on furnace,wall temperatures,as measured,by thermocouples.,This model,is based,on an energy,balance,of the furnace system,with the following features: (a) the model,is a transformed,linear model,which,captures,the nonlinear,relationship between,the furnace wall temperature distribution and the wafer temperature distribution, (b) the model can be solved with a direct algorithm

Qinghua He; S. Joe Qin; Anthony J. Toprac

325

An application of selective electrochemical wafer thinning for silicon characterization  

SciTech Connect

A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

1990-01-01

326

Apparatus and method for measuring the thickness of a semiconductor wafer  

DOEpatents

Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

Ciszek, T.F.

1995-03-07

327

B-cell-specific peptides of leptospira interrogans LigA for diagnosis of patients with acute leptospirosis.  

PubMed

Leptospirosis is a reemerging infectious disease that is underdiagnosed and under-recognized due to low-sensitivity and cumbersome serological tests. Rapid reliable alternative tests are needed for early diagnosis of the disease. Considering the importance of the pathogenesis-associated leptospiral LigA protein expressed in vivo, we have evaluated its application in the diagnosis of the acute form of leptospirosis. The C-terminal coding sequence of ligA (ligA-C) was cloned into pET15b and expressed in Escherichia coli. Furthermore, the B-cell-specific epitopes were predicted and were synthesized as peptides for evaluation along with recombinant LigA-C. Epitope 1 (VVIENTPGK), with a VaxiJen score of 1.3782, and epitope 2 (TALSVGSSK), with a score of 1.2767, were utilized. A total of 140 serum samples collected from leptospirosis cases during the acute stage of the disease and 138 serum samples collected from normal healthy controls were utilized for evaluation. The sensitivity, specificity, positive predictive value, and negative predictive value were calculated for the recombinant LigA-C-specific IgM enzyme-linked immunosorbent assay (ELISA) and were found to be 92.1%, 97.7%, 92.8%, and 97.5%, respectively. Epitopes 1 and 2 used in the study showed 5.1 to 5.8% increased sensitivity over recombinant LigA-C in single and combination assays for IgM antibody detection. These findings suggest that these peptides may be potential candidates for the early diagnosis of leptospirosis. PMID:24403522

Kanagavel, Murugesan; Shanmughapriya, Santhanam; Anbarasu, Kumarasamy; Natarajaseenivasan, Kalimuthusamy

2014-03-01

328

Variable Control Design and its Application to Wafer Scanners  

Microsoft Academic Search

A variable control design is presented. The validity of such a design in dealing with linear performance trade-offs is demonstrated on a reticle stage motion system of an industrial wafer scanner. Performance is achieved by continuously balancing stability margins over disturbance rejection properties. This is done by a nonlinear state-dependent element in the feedback loop. Apart from performance, design rules

Marcel Heertjes; Nathan van de Wouw

2006-01-01

329

Optical Alignment Optimizations for Reducing Wafer-Induced Shift  

NASA Astrophysics Data System (ADS)

Detecting the position of wafers after chemical mechanical polishing (CMP) is a critical issue in current and forthcoming IC manufacturing. A wafer alignment system must be highly accurate for all processes. To satisfy such requirements, we have studied and analyzed factors that have made alignment difficult. From the results of the studies, we have developed new optical alignment optimizations that improve the accuracy of FIA (wafer alignment sensor of Nikon’s exposure system) and examined them. The approaches are optimizing the focus position based on new classification of measurement errors, developing an advanced algorithm for position determination, and selecting a suitable mark design. The new classification method classifies measurement errors into errors caused by light amplitude errors and errors caused by phase errors. In the experiment, we have fabricated special wafers that make it possible to evaluate the influence of CMP processes on the alignment accuracy. The simulation and experimental results show that overlay error decreases markedly with the new alignment optimizations. FIA with these new optimizations will be highly accurate and suitable alignment sensor for CMP and other processes of future-generation LSI production.

Sugaya, Ayako; Kanaya, Yuho; Nakajima, Shinichi; Nagayama, Tadashi; Shiraishi, Naomasa

2004-11-01

330

Multi-wafer slicing with a fixed abrasive  

NASA Technical Reports Server (NTRS)

A wafering machine having a multiplicity of wire cutting blades supported by a bladehead reciprocally moving past a workpiece supported by a holder that rocks about an axis perpendicular to the wires at a frequency less than the reciprocation of the bladehead.

Schmid, Frederick (Inventor); Khattak, Chandra P. (Inventor); Smith, Maynard B. (Inventor)

1988-01-01

331

Spatial heterodyne interferometry techniques and applications in semiconductor wafer manufacturing  

NASA Astrophysics Data System (ADS)

Spatial heterodyning is an interferometric technique that allows a full complex optical wavefront to be recorded and quickly reconstructed with a single image capture. Oak Ridge National Laboratory (ORNL) has combined a high-speed, image capture technique with a Fourier reconstruction algorithm to produce a method for recovery of both the phase and magnitude of the optical wavefront. Single frame spatial heterodyne interferometry (SHI) enables high-speed inspection applications such as those needed in the semiconductor industry. While the wide range of materials on wafers make literal interpretation of surface topology difficult, the wafers contain multiple copies of the same die and die-to-die comparisons are used to locate defects in high-aspect-ratio structures such as contacts, vias, and trenches that are difficult to detect with other optical techniques. Metrology with SHI has also been investigated by ORNL, in particular the use of SHI to perform metrology of line widths and heights on photolithographic masks for semiconductor wafer production. Several types of masks are currently in use with phase shifting techniques being employed to extend the wafer printing resolution. With the ability to measure the phase of the wavefront, SHI allows a more complete inspection and measurement of the phase shifting regions.

Bingham, Philip R.; Tobin, Kenneth W.; Hanson, Gregory R.; Simpson, John T.

2004-08-01

332

A reclaiming process for solar cell silicon wafer surfaces.  

PubMed

The low yield of epoxy film and Si3N4 thin-film deposition is an important factor in semiconductor production. A new design system using a set of three lamination-shaped electrodes as a machining tool and micro electro-removal as a precision reclaiming process of the Si3N4 layer and epoxy film removal from silicon wafers of solar cells surface is presented. In the current experiment, the combination of the small thickness of the anode and cathodes corresponds to a higher removal rate for the thin films. The combination of the short length of the anode and cathodes combined with enough electric power produces fast electroremoval. A combination of the small edge radius of the anode and cathodes corresponds to a higher removal rate. A higher feed rate of silicon wafers of solar cells combined with enough electric power produces fast removal. A precise engineering technology constructed a clean production approach for the removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers from solar cells that can reduce pollution and lower cost. PMID:21446525

Pa, P S

2011-01-01

333

Evaluating the eye fatigue problem in wafer inspection  

Microsoft Academic Search

After develop inspection (ADI) and after etching inspection (AEI) are the main inspection tasks in the wafer manufacturing fab. Because of the detailed and tiny circuit patterns, ADI and AEI are carried out with the aid of a microscope. ADI and AEI inspectors frequently complain about visual fatigue problems. In this study, we focused on evaluating the effects of display

Mao-Jiun J. Wang; Chung-Lun Huang

2004-01-01

334

Thermomechanical Design of Resilient Contact Systems for Wafer Level Packaging  

Microsoft Academic Search

Wafer level packaging (WLP) technologies are cost effective packaging solutions which are used increasingly. Second level reliability, i.e. mainly the thermo-mechanical reliability during thermal cycling, is a major concern of WLP. To avoid excessive solder straining, solder balls have been replaced by resilient interconnects, which can adopt the main part of the thermal mismatch deformation. One solution combining an increased

Rainer Dudek; Hans Walter; Ralf Doering; Bernd Michel; Thorsten Meyer; Joerg Zapf; Harry Hedler

2006-01-01

335

Ultra-Gradient Test Cavity for Testing SRF Wafer Samples  

SciTech Connect

A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

2010-11-01

336

Promise of silicon wafer microguides for future neutron optical elements  

NASA Astrophysics Data System (ADS)

The usually large cross section of the incident neutron beam is divided in the microguide into a large number of thin slices. This allows the neutron beam to be deviated by a large angle within a short distance and enables the design of an efficient neutron lens by giving the stack an appropriate shape. We present a novel approach for high quality microguides by using thin and thus flexible single crystal silicon wafers as the neutron transmitting medium, coated with optimized neutron reflecting thin-film materials. A crucial issue concerns the reflection coefficient R of the silicon thin-film interface. We have performed neutron transmission measurements through commercially available 200 micrometers thin wafers coated in both sides with nickel. Various rocking curves have been taken on assemblies of straight wafers with neutron pathways from 50 to 200 mm in silicon, and on curved wafers. A reflectivity value of 0.988 +/- 0.005 has been found for a neutron wavelength of 7 angstroms.

Mildner, David F. R.; Chen-Mayer, Huaiyu H.; Magerl, Andreas; Gruening, U.

1992-11-01

337

Price Estimates for the Production of Wafers from Silicon Ingots.  

National Technical Information Service (NTIS)

Some photovoltaic modules are made from solar cells using ribbon silicon. Most solar cells, however, are produced from wafers sliced from crystalline silicon ingots. Unfortunately, the cost of the slicing process is a major part of the cost of producing s...

A. R. Mokashi

1982-01-01

338

Wafer yield prediction by the Mahalanobis-Taguchi system  

Microsoft Academic Search

The distribution of yield from the production lines is concentrated at a high-yield area and tapers down to the lower-yield area. Production management would find it useful if the yield of individual wafers could be forecast. The yield is determined by the variability of electrical characteristics and dust. In this study, only the variability of electrical characteristics was discussed. One

M. Asada

2001-01-01

339

Prediction of thermo-mechanical integrity of wafer backend processes  

Microsoft Academic Search

More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function\\/product integration will increase the importance of thermomechanical reliability, as confirmed by the ITRS (International technology roadmap for semiconductors; [1]). Since most of the

V. Gonda; J. M. J. Den Toonder; J. Beijer; G. Q. Zhang; W. D. van Driel; R. J. O. M. Hoofman; L. J. Ernst

2004-01-01

340

Automatically Dressing Blades in Silicon-Wafer Cutting  

NASA Technical Reports Server (NTRS)

Inserts incorporated in support beams for silicon ingots automatically "dress" cutting blade during wafer slicing. Segments of blade-dressing material placed at regular intervals in graphite beam. Blade cuts into segments and dressed without operator intervention and without interrupting regular machine operation. Manual dressing eliminated, and production rates increased.

Morrison, A. D.

1985-01-01

341

Crack propagation and fracture in silicon wafers under thermal stress  

PubMed Central

The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing.

Danilewsky, Andreas; Wittge, Jochen; Kiefl, Konstantin; Allen, David; McNally, Patrick; Garagorri, Jorge; Elizalde, M. Reyes; Baumbach, Tilo; Tanner, Brian K.

2013-01-01

342

Efficient simulation and optimization of wafer topographies in double patterning  

NASA Astrophysics Data System (ADS)

As the technology marches towards the 32nm node and beyond in semiconductor manufacturing, double patterning and double exposure techniques are currently regarded as the potential candidates to produce lines and spaces (L&S) and contact holes (C/H), respectively. In this paper, the Waveguide method, a rigorous electromagnetic field (EMF) solver, is employed to investigate the impact of wafer topographies on two specific double patterning techniques. At first, the topography effects induced by the first patterning on the second lithography process in a lithography-etch-lithographyetch (LELE) process are demonstrated. A new methodology of the bottom anti-reflective coating (BARC) optimization is proposed to reduce the impact of wafer topography on resist profiles. Additionally, an optical proximity correction (OPC) of the second lithography mask is demonstrated to compensate the wafer topography induced asymmetric deformations of line ends. Rigorous EMF simulations of lithographic exposures are also applied to investigate wafer topography effects in a freezing process. The difference between the optical properties of the frozen (first) resist and the second resist potentially causes linewidth variations. Quantitative criteria for tolerable refractive index and extinction differences between the two resist materials are given. The described studies can be used for the optimizations of topographic waferstacks, the OPC of the second litho mask, and for the development of resist materials with appropriate optical properties.

Shao, Feng; Evanschitzky, Peter; Fühner, Tim; Erdmann, Andreas

2009-03-01

343

An improved on-wafer noise measurement technique  

Microsoft Academic Search

A novel on-wafer resistive noise source useful for noise characterization of microwave devices with the cold noise power measurement technique is described. The noise source enhances measurement accuracy by providing a calibrated noise temperature directly at the device reference plane. A procedure for determining the excess noise ratio of the noise source is presented, and the overall technique is validated

P. Beland; L. Roy; S. Labonte; M. Stubbs

1998-01-01

344

Wafer level sealing characterization method using Si micro cantilevers  

Microsoft Academic Search

In this study, a wafer level sealing characterization method using the pressure dependence of the mechanical quality factor of Si micro cantilevers has been developed. Since the equation for design of a cantilever near fixed walls in free molecular flow regime has not been derived, a new equation has been proposed. We determine that the minimum measurable pressure necessary for

Hironao Okada; Toshihiro Itoh; Tadatomo Suga

2008-01-01

345

Interface defects in integrated hybrid semiconductors by wafer bonding  

NASA Astrophysics Data System (ADS)

The integration of materials by wafer bonding offers novel device fabrication for applications in micromechanics, microelectronics, and optoelectronics. Two mirror-polished surfaces are brought into intimate contact by adhesive forces regardless of their crystallography, crystalline orientation and lattice mismatch. Followed by a thermal treatment at several hundred degrees centigrade, the interface energy of the material combination is increased to energies of covalent interatomic bonds. Attempts to break the bond lead to fracturing of the materials. In particular, thermomechanic stress in dissimilar material combinations may result in bending, gliding and cracking of the bonded wafers during annealing. The bonding interface of various hybrid semiconductor materials was studied by transmission electron microscopy. Occasionally, microscopic imperfections at the bonding interface were found in Si/Si, Si/GaAs, GaAs/GaAs, GaAs/Al 2O 3, GaAs/InP and moreover Al 2O 3/Al 2O 3 bonded wafer pairs. The imperfections were identified as voids, negative crystals, and oxide-containing precipitates ranging from 5 to 20 nm in diameter. Microscopic defects at the bonding interface in integrated bulk materials do not affect the mechanical and electrical properties of the device very much. However, in bonding of thin films the defects or precipitates may thread through the thin film, if the diameter of the precipitate surpasses the thickness of the film. These pinholes-containing thin films have a high leakage current, low electrical breakthrough and crystallographic disorder. Epitaxy of material on a pinholes containing, disordered surface results on deposition of bicystalline grains. In between the grains tilt grain boundaries were observed raising from the bonding interface. Bonding related defects at the interface can be avoided by alternative bonding techniques like UHV wafer bonding and low temperature wafer bonding.

Kopperschmidt, P.; Senz, St.; Scholz, R.

2001-12-01

346

Advanced FTIR technology for the chemical characterization of product wafers  

NASA Astrophysics Data System (ADS)

Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers. .

Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

2001-01-01

347

High throughput wafer defect monitor for integrated metrology applications in photolithography  

NASA Astrophysics Data System (ADS)

The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

Rao, Nagaraja; Kinney, Patrick; Gupta, Anand

2008-04-01

348

Effects of wafer curvature caused by film stress on the chemical mechanical polishing process  

Microsoft Academic Search

A theoretical model based on two-body contact theory is established to simulate the contact pressure distribution arising\\u000a from wafer curvature which is caused by film stress during CMP process. Both wafer and pad deformations during the contact\\u000a process are considered. The profiles of the contact pressure distribution for wafers with different curvature radius are simulated.\\u000a The influences of wafer curvature

Lixiao Wu

2009-01-01

349

Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers for PV Cells  

SciTech Connect

As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay ({mu}PCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

Guthrey, H.; Gorman, B.; Al-Jassim, M.

2011-01-01

350

Material nonlinear characteristics of the 3203HD PZT wafer under high electric fields  

Microsoft Academic Search

In this paper, material nonlinear behavior of a PZT wafer (3203HD, CTS) under high electric fields and stress is experimentally investigated and the nonlinearity of the PZT wafer is numerically simulated. Empirical functions that can represent the nonlinear behavior of the PZT wafer have been extracted based on the measured piezoelectric strain under stress. The functions are implemented in an

Sangki Lee; Sung-Hoon Jang; Young Sung Kim; Hoon Cheol Park; Kwang Joon Yoon

2005-01-01

351

A Two-Wafer Approach for Integration of Optical MEMS and Photonics on Silicon Substrate  

Microsoft Academic Search

This letter reports a novel two-wafer approach which demonstrates an integration of optical microelectromechanical system (MEMS) devices and photonics on a silicon substrate. The great advantage of this novel wafer bonding scheme is the ability to maintain the optical axis of the optical MEMS device at the same axis as the optical components. The bonded two wafers which are partially

Qingxin Zhang; Jing Zhang; Mingbin Yu; Chee Wei Tan; Guo-Qiang Lo; Dim-Lee Kwong

2010-01-01

352

Comparison of surface polishing techniques used for InP wafers  

Microsoft Academic Search

InP wafers prepared using different polishing and mounting methods were compared by Makyoh topography, which is capable of detecting extremely small surface height variations. In some wafers a cellular surface ridge structure due to uneven mounting wax distribution was observed. It is shown that the ridge structure can be completely eliminated by the optimisation of the wafer mounting procedure or

Z. Laczik; G. R. Booker; A. Mowbray

1995-01-01

353

CMOS wafer bonding for back-side illuminated image sensors fabrication  

Microsoft Academic Search

Backside illuminated CMOS image sensors were developed in order to encompass the pixel area limitation due to metal interconnects. In this technology the fully processed CMOS wafer is bonded to a blank carrier wafer and then back-thinned in order to open the photosensitive sensor area. The process flows of the two main competing wafer bonding technologies used for this manufacturing

V. Dragoi; A. Filbert; S. Zhu; G. Mittendorfer

2010-01-01

354

High speed SOI CMOS image sensor with pinned photodiode on handle wafer  

Microsoft Academic Search

We have fabricated SOI CMOS active pixel image sensor with pinned photodiode on handle wafer. The structure of one pixel is a four-transistor type active pixel image sensor, which consists of a reset and a source follower transistor on seed wafer, and is comprised of a photodiode, a transfer gate, and a floating diffusion on handle wafer. The photodiode could

Yong-soo Cho; H. Takao; K. Sawada; M. Ishida; Sie-young Choi

2007-01-01

355

Scheduling cluster tools in wafer fabrication using candidate list and simulated annealing  

Microsoft Academic Search

This paper presents a new method for scheduling cluster tools in semiconductor fabrication. A cluster tool consists of a group of single-wafer chambers organized around a wafer transport device, or robot. The cluster fabrication considered consists of serial cluster tools. Due to constraints imposed by multiple routes of each type of wafer and machines with no buffer, it is very

Seong Jin Yim; Doo Yong Lee

1998-01-01

356

Scheduling cluster tools in wafer fabrication using candidate list and simulated annealing  

Microsoft Academic Search

This paper presents a new method for scheduling cluster tools in semiconductor fabrication. A cluster tool consists of a group of single-wafer chambers organized around a wafer transport device, or robot. Cluster fabrication system considered in this paper consists of serial cluster tools. Due to constraints imposed by multiple routes of each wafer type and machines with no buffer, it

Seong Jin Yim; Doo Yong Lee

1999-01-01

357

Yield prediction via spatial modeling of clustered defect counts across a wafer map  

Microsoft Academic Search

In this paper we propose spatial modeling approaches for clustered defects observed using an Integrated Circuit (IC) wafer map. We use the spatial location of each IC chip on the wafer as a covariate for the corresponding defect count listed in the wafer map. Our models are based on a Poisson regression, a negative binomial regression, and Zero-Inflated Poisson (ZIP)

Suk Joo Bae; Jung Yoon Hwang

2007-01-01

358

Ultra thin-wafer technology for a new 600 V-NPT-IGBT  

Microsoft Academic Search

In this paper the method of manufacturing 100 ?m thin IGBT wafers is described. The key topic of new deposition processes reducing the bow of very thin wafers is discussed as well as improvements in equipment and wafer handling. These measurements are the basis to realize for the first time 600 V Non-Punch-Through IGBTs with their advantages of cost effective

T. Laska; M. Matschitsch; W. Scholz

1997-01-01

359

Simultaneous Temperature Measurement of Wafers in Chemical Mechanical Polishing of Silicon Dioxide Layer  

Microsoft Academic Search

The wafer temperature in chemical mechanical polishing (CMP) of silicon dioxide layers was measured. When the temperatures of both the polishing slurry and the polishing pad were controlled at 8° C, the measured wafer temperatures were 10-20° C. The temperature distribution affected the thickness of the polished oxide layer. When the wafer temperature was high, the oxide layer removal rate

Fumitoshi Sugimoto; Yoshihiro Arimoto; Takashi Ito

1995-01-01

360

The effect of patterns on thermal stress during rapid thermal processing of silicon wafers  

Microsoft Academic Search

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport

Jeffrey P. Hebb; Klavs F. Jensen

1998-01-01

361

Compliant meso-scale grinding of silicon  

Microsoft Academic Search

In this research, the need to create complex three-dimensional free-form shapes in silicon wafers for MEMS applications has been identified. Meso-scale grinding was chosen to perform the three-dimensional machining of silicon, among several other machining methods. Traditionally, ultra-rigid ultra-precision machines are used to machine silicon wafers in order to achieve ductile material removal mode to minimize grinding induced surface and

Bo Jiang

2004-01-01

362

Slumping of Si wafers at high temperature  

NASA Astrophysics Data System (ADS)

Space X-ray imaging telescopes have delivered unique observations that have been significantly contributing to many important discoveries of current astrophysics. For future telescopes with a larger collecting area and a better angular resolution, the limiting factor is their X-ray reflecting mirror array. Therefore, for a successful construction of future lightweight and highly reflecting X-ray mirrors, new cost-effective technologies and progressive materials are needed. Currently, the very promising materials are silicon foils which are commercially produced on a large scale. We focused on the plastic deformation of thin monocrystalline silicon foils, which was necessary for the precise thermal forming of the foils to 3D shapes. To achieve the plastic deformation, we applied forced slumping at temperatures from 1200 to 1400°C. The final shapes and the surface quality of the foils were measured using a Taylor Hobson contact profilometer and examined with an Atomic Forced Microscopy. We studied the effects of temperature, applied slumping force, heattreatment time, crystal orientation, and furnace atmosphere on the shape and surface quality of the formed foils.

Mika, M.; Jankovsky, O.; Simek, P.; Lutyakov, O.; Havlikova, R.; Sofer, Z.; Hudec, R.; Pina, L.; Inneman, A.; Sveda, L.; Marsikova, V.

2013-05-01

363

Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy  

NASA Astrophysics Data System (ADS)

All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on transmission and mobility are quantitatively discussed.

Altan, Hakan

364

Wafer-level packaging with compression-controlled seal ring bonding  

DOEpatents

A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Farino, Anthony J

2013-11-05

365

Fabrication of GaN wafers for electronic and optoelectronic devices  

NASA Astrophysics Data System (ADS)

The fabrication of GaN wafers from GaN boules (ingots) is described. Gallium nitride boules were grown by hydride vapor phase epitaxy and sliced and sized into wafer blanks. The GaN wafer blanks were lapped and polished. The gallium-side of the wafer was finished with a chemical mechanical polish (CMP) process, which removed surface and subsurface damage, yielding GaN wafers ready for homoepitaxial growth. The CMP polished surface produced a root-mean-square (RMS) surface roughness of 0.3 nm on a 10 × 10 ?m 2 scan area.

Xu, Xueping; Vaudo, R. P.; Brandes, G. R.

2003-07-01

366

Localized induction heating solder bonding for wafer level MEMS packaging  

NASA Astrophysics Data System (ADS)

This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was heated using induction heating causing the solder to reflow. The experiment results show that it took less than 1 min to complete the bonding process. In addition, the MEMS devices experienced a temperature of only 110 °C during bonding, thus thin film materials would not be damaged. Moreover, the bond strength between silicon and silicon wafer was higher than 18 MPa. The step height of the feed-through wire (acting as the electrical feed-through of the bonded region) is sealed by the electroplated film. Thus, the flatness and roughness of the electroplated surface are recovered by the solder reflow, and the package for preventing water leakage can be achieved. The integration of the surface micromachined devices with the proposed packaging techniques was demonstrated.

Yang, Hsueh-An; Wu, Mingching; Fang, Weileun

2005-02-01

367

Joint Rigidity Assessment with Piezoelectric Wafers and Acoustic Waves  

NASA Astrophysics Data System (ADS)

There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an `L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

Montoya, Angela C.; Maji, Arup K.

2010-02-01

368

Chemical method for producing smooth surfaces on silicon wafers  

DOEpatents

An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

Yu, Conrad (Antioch, CA)

2003-01-01

369

A gas chromatographic air analyzer fabricated on a silicon wafer  

NASA Technical Reports Server (NTRS)

A miniature gas analysis system has been built based on the principles of gas chromatography (GC). The major components are fabricated in silicon using photolithography and chemical etching techniques, which allows size reductions of nearly three orders of magnitude compared to conventional laboratory instruments. The chromatography system consists of a sample injection valve and a 1.5-m-long separating capillary column, which are fabricated on a substrate silicon wafer. The output thermal conductivity detector is separately batch fabricated and integrably mounted on the substrate wafer. The theory of gas chromatography has been used to optimize the performance of the sensor so that separations of gaseous hydrocarbon mixtures are performed in less than 10 s. The system is expected to find application in the areas of portable ambient air quality monitors, implanted biological experiments, and planetary probes.

Terry, S. C.; Jerman, J. H.; Angell, J. B.

1979-01-01

370

Metal adsorbent for alkaline etching aqua solutions of Si wafer  

NASA Astrophysics Data System (ADS)

High performance adsorbent is expected to be synthesized for the removal of Ni and Cu ions from strong alkaline solution used in the surface etching process of Si wafer. Fibrous adsorbent was synthesized by radiation-induce emulsion graft polymerization onto polyethylene nonwoven fabric and subsequent amination. The reaction condition was optimized using 30 L reaction vessel and nonwoven fabric, 0.3 m width and 18 m long. The resulting fibrous adsorbent was evaluated by 48 wt% NaOH and KOH contaminated with Ni and Cu ions, respectively. The concentration levels of Ni and Cu ions was reduced to less than 1 ?g/kg (ppb) at the flow rate of 10 h-1 in space velocity. The life of adsorbent was 30 times higher than that of the commercialized resin. This novel adsorbent was commercialized as METOLATE® since the ability of adsorption is remarkably higher than that of commercial resin used practically in Si wafer processing.

Tamada, Masao; Ueki, Yuji; Seko, Noriaki; Takeda, Toshihide; Kawano, Shin-ichi

2012-08-01

371

Designing DWDM multiplexers on SiON wafers  

NASA Astrophysics Data System (ADS)

I propose an integrated multiplexer/demultiplexer that use a concave blazed diffraction grating on SiON wafer. The paper presents a technology that overcome existing issues regarding implementation of such a microoptic device. Two types of similar integrated systems were developed but both of them have not minimized chromatic, astigmatism and spherical aberrations. Both systems use gold coating for vertical walls of diffraction grating that has reflection index lower than aluminum for wavelength used. Technology proposed in this paper minimizes the chromatic, astigmatism and spherical aberrations. Also is used aluminum for coating of vertical walls of diffraction grating. SiON wafer is etched with Argon plasma through photoresist mask with thickness of 0,8 ?m for grating configuration allowing reusing of the photoresist in next stage of coating. This makes possible that coating through liftoff to be aligned to vertical walls of concave diffraction grating, eliminating positioning errors due to coating mask.

Dragnea, Laurentiu

2010-09-01

372

Wafer-fused VECSELs emitting in the 1310nm waveband  

NASA Astrophysics Data System (ADS)

Optically pumped wafer fused 1310 nm VECSELs have the advantage of high output power and wavelength agility. Gain mirrors in these lasers are formed by direct bonding of InAlGaAs/InP active cavities to Al(Ga)As/GaAs DBRs. We present for the first time Watt-level 1310 nm wafer-fused VCSELs based on gain mirrors with heat dissipation in the "flip-chip" configuration. Even though output power levels in this approach is lower than with intra-cavity diamond heat-spreaders, the "flip-chip configuration demonstrates higher quality optical emission and is preferable for industrial applications in optical amplifiers, intra-cavity doubled lasers, etc.

Sirbu, A.; Pierscinski, K.; Mereuta, A.; Iakovlev, V.; Caliman, A.; Micovic, Z.; Volet, N.; Rautiainen, J.; Heikkinen, J.; Lyytikainen, J.; Rantamäki, A.; Okhotnikov, O.; Kapon, E.

2014-03-01

373

Micromachining of silicon wafer in air and under water  

Microsoft Academic Search

Laser ablation micro-machining tests are conducted on silicon wafer, both in air and under flowing water stream, with the use of 355nm-X AVIA laser. Effects of laser pulse frequency, power level, scan velocity and focal plane position on the associated laser spatter deposition (in air), irradiated areas (under flowing water film) and taper are investigated. It shows that low frequency,

L. M. Wee; E. Y. K. Ng; A. H. Prathama; H. Zheng

2011-01-01

374

Surface micromachined tunable resonant cavity LED using wafer bonding  

Microsoft Academic Search

Surface micromachining and wafer bonding techniques have been integrated to fabricate a dual-use resonant cavity tunable LED\\/photodetector operating at 1.5 micrometers . The device has a tuning range of 75 nm, and a spectral linewidth of 4 nm, with an extinction ratio of greater than 20 dB throughout the tuning range. The device has potential applications in WDM networks and

Gina L. Christenson; Alex T. Tran; Zuhua Zhu; Yu-Hwa Lo; Minghwei Hong; J. P. Mannaerts; Rajaram J. Bhat

1997-01-01

375

Dominant iron gettering mechanism in p/p+ silicon wafers  

NASA Astrophysics Data System (ADS)

Fe gettering mechanisms in p/p+ epitaxial Si were investigated under controlled contamination and annealing cycles. The dominant Fe gettering mechanism is the Fermi level controlled coulomb attraction between Fe+ and B- in the p+ substrate of the p/p+ wafers. Oxygen precipitates do not appear to contribute when using normal cooling rates following heat treatments. The epi-substrate interfacial strain plays no role in Fe gettering.

Lin, Wen; Benton, J. L.; Pinacho, R.; Ramappa, D. A.; Henley, W.

2000-07-01

376

Tiny silicon nano-wires synthesis on silicon wafers  

Microsoft Academic Search

Tiny silicon nano-wires (SiNWs) were synthesized on silicon wafers by the chemical vapor deposition (CVD) technique. The morphology and structure of tiny SiNWs were analyzed by means of transmission electron microscopy (TEM), scanning electron microscopy (SEM) and X-ray diffraction (XRD), respectively. The results indicate that the tiny SiNWs were part-crystalline structure and were about 3 nm in minimal diameter. Based

Junjie Niu; Jian Sha; Yujie Ji; Deren Yang

2004-01-01

377

Performance limiting micropipe defects in silicon carbide wafers  

Microsoft Academic Search

Reports on the characteristics of a major defect in mass-produced silicon carbide wafers which severely limits the performance of silicon carbide power devices. Micropipe defects originating in 4H- and 6H-SiC substrates were found to cause pre-avalanche reverse-bias point failures in most epitaxially-grown pn junction devices of 1 mm2 or larger in area. Until such defects are significantly reduced from their

Philip G. Neudeck; Anthony J. Powell

1994-01-01

378

Implications of wafer design for manufacturing practices on photomask manufacturing  

NASA Astrophysics Data System (ADS)

Focus on Design for Manufacturing (DFM) in semiconductor device design has increased as semiconductor manufacturing technology has become more complex. Many of the techniques developed to improve wafer yield and manufacturability can also be applied to the photomask manufacturing process. For example, for the last several technology nodes, semiconductor manufacturers have known that pattern density and uniformity can have significant impact on wafer processes such as etching and chemical mechanical polishing. Photomask manufacturing can also be impacted by pattern density and its uniformity. Some of these DFM practices can be beneficial if applied directly to photomask manufacturing while some of them can make photomask manufacturing significantly more difficult. Optical proximity correction (OPC), which involves convoluting the design shape to account for optical, physical and chemical processes, is increasingly required to support advanced lithography; some of the operational parameters of the OPC, such as the fragmentation run length, challenge mask resolution capability, image fidelity, defect inspection, mask repair, and dimensional metrology of photomasks. Sub-resolution assist features (SRAFs), which are utilized to create robust wafer lithography are often the most challenging mask features to create. The size and placement of SRAFs on photomasks are factors that impact photomask manufacturability in terms of image resolution, inspection, and dispositioning criteria. As OPC and other DFM processes become more widely deployed in an effort to make robust wafer manufacturing processes, the photomask maker needs to be involved to evaluate the implications to photomask manufacturing and assist in optimizing these DFM procedures to maximally benefit both the photomask and semiconductor manufacturing processes.

Watts, Andrew; Rankin, Jed; Magg, Christopher

2005-11-01

379

SCREEN PRINTABLE POLYMERS FOR WAFER LEVEL PACKAGING: A TECHNOLOGY ASSESSMENT  

Microsoft Academic Search

Screen print patterning is an attractive alternative to traditional semiconductor photo-lithography. Our work compared the pattern resolution and mechanical resistance of screen-printed polymers versus spin-on methods. Optical microscopy of screen-printed coatings reveal sharp edge features as well as masked off saw streets and I\\/Os across the wafer. Thickness comparisons are made between the 2 methodologies. Design rules for screen fabrication,

James Clayton; Michael J. Hodgin

380

Wafer-level radiometric performance testing of uncooled microbolometer arrays  

NASA Astrophysics Data System (ADS)

A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 ?m AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 ?m pixel size and 160x120, 52 ?m pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

2014-03-01

381

Reticle and wafer CD variation for different dummy pattern  

NASA Astrophysics Data System (ADS)

Dummy pattern fill is added to a layout of a reticle for the purpose of raising the pattern-density of specific regions. The pattern-density has also an influence on different process-steps which were performed when manufacturing a reticle (e.g. proximity effect of electron beam exposure process, developer, and etch-processes). Although the reticle processes are set up to compensate the influence of the pattern density, dummy pattern can have an influence onto the reticle CD. When the isolated features become "nested" by insertion of dummy pattern, the reticle CD variation is even larger because nested features exacerbate the proximity effect of an electron beam. Another reason is that the etch ratio as well as the develop dynamics during the reticle manufacturing process are slightly dependent on the local pattern-density of pattern. With different dummy pattern around the main feature, the final reticle CD will be changed. Wafer CD of main feature is also dependant on the surrounding patterns which will induce different boundary conditions for wafer exposure. We have investigated three manufacturing sites for a 28nm first-metal layer reticle. Two of them were manufactured with a comparable process using the same advanced reticle binary blank material. For the third site a different reticle blank material with a relatively thin absorber layer thickness was used which was made with a comparable reticle process. The optical proximity correction (OPC) test patterns were designed with two different dummy patterns. The CD differences of the three reticles will be demonstrated for different dummy pattern and will be discussed individually. All three reticles have been exposed and the respective wafer critical dimension through pitch (CDTP) and linearity performance is demonstrated. Also the line-end performance for two dimensional (2D) structures is shown for the three sites of the reticle. The wafer CD difference for CDTP, linearity, and 2D structures are also discussed.

Ning, GuoXiang; Buergel, Christian; Ackmann, Paul; Staples, Marc; Thamm, Thomas; Lim, Chin Teong; Leschok, Andre; Roling, Stefan; Zhou, Anthony; Gn, Fang Hong; Richter, Frank

2012-11-01

382

Effect of heat according to wafer size on the removal rate and profile in CMP process  

NASA Astrophysics Data System (ADS)

The effect of wafer size on the removal rate and profile during chemical mechanical polishing was investigated with two representative thin films: SiO2 and Cu, which were used as the dielectric and interconnection, respectively. Experiments were conducted using SiO2 and Cu blanket wafers with 100, 200, and 300 mm diameters, while the results for 450 mm diameter wafers were estimated using geometric calculation. The experimental results showed that the heat generated by an increase in the wafer size affects the removal rate and the Within-Wafer Non-uniformity (WIWNU). In particular, the polishing temperature is one of the most important factors affecting the removal rate and profile in the Cu CMP process. An optimum slurry flow rate may exist for each wafer size, which should be carefully considered, particularly when using 450 mm diameter wafers in the semiconductor industry.

Park, Yeongbong; Lee, Youngkyun; Lee, Hyunseop; Jeong, Haedo

2013-11-01

383

Microstructuring and wafering of silicon with laser chemical processing  

NASA Astrophysics Data System (ADS)

Laser processing is an important application for fabrication of silicon solar cells, e.g. buried contacts, laser fired contacts or edge isolation. At Fraunhofer ISE a liquid-jet guided laser is used for Laser Chemical Processing (LCP). Both the fundamentals of laser material ablation with this system and the application of various processes for solar cell fabrication are investigated. The applications are divided into two main areas: Microstructuring and deep laser cutting (wafering) of silicon substrates. Microstructuring contains the investigation and characterization of laser induced damage and selective emitter formation for n- and p-type emitters depending on laser parameters and liquid properties. One of the most important and industrially relevant topics at the moment is the formation of a selective highly doped emitter under the metal fingers of solar cells. Wafering deals with the evaluation of suitable laser parameters, adequate chemicals or chemical additives and the understanding of ablation processes by simulation and experimental work. In this presentation newest results concerning n-type doping for varying laser and liquid parameters will be presented with regard to cell efficiency and contact resistance. Furthermore a short overview of promising LCP applications will be given, e.g. p-type doping and wafering.

Hopman, Sybille; Fell, Andreas; Mayer, Kuno; Rodofili, Andreas; Granek, Filip

2010-02-01

384

Automatic classification of spatial signatures on semiconductor wafer maps  

NASA Astrophysics Data System (ADS)

This paper describes spatial signature analysis (SSA), a cooperative research project between SEMATECH and Oak Ridge National Laboratory for automatically analyzing and reducing semiconductor wafermap defect data to useful information. Trends towards larger wafer formats and smaller critical dimensions have caused an exponential increase in the volume of visual and parametric defect data which must be analyzed and stored, therefore necessitating the development of automated tools for wafer defect analysis. Contamination particles that did not create problems with 1 micron design rules can now be categorized as killer defects. SSA is an automated wafermap analysis procedure which performs a sophisticated defect clustering and signature classification of electronic wafermaps. This procedure has been realized in a software system that contains a signature classifier that is user-trainable. Known examples of historically problematic process signatures are added to a training database for the classifier. Once a suitable training set has been established, the software can automatically segment and classify multiple signatures from a standard electronic wafermap file into user-defined categories. It is anticipated that successful integration of this technology with other wafer monitoring strategies will result in reduced time-to-discovery and ultimately improved product yield.

Tobin, Kenneth W., Jr.; Gleason, Shaun S.; Karnowski, Thomas P.; Cohen, Susan L.; Lakhani, Fred

1997-07-01

385

Method for making circular tubular channels with two silicon wafers  

DOEpatents

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

Yu, C.M.; Hui, W.C.

1996-11-19

386

Characterization and mitigation of overlay error on silicon wafers with nonuniform stress  

NASA Astrophysics Data System (ADS)

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. While uniform process-induced stress is easily corrected, non-uniform stress across the wafer is much more problematic, often resulting in non-correctable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such non-uniform stress. We will describe a Patterned Wafer Geometry (PWG) tool, which uses optical methods to measure the geometry of in-process wafers. PWG data can be related to In-Plane Distortion (IPD) of the wafer through the PIR (Predicted IPD Residual) metric. This paper will explore the relationship between the PIR data and measured overlay data on Engineered Stress Monitor (ESM) wafers containing various designed stress variations. The process used to fabricate ESM wafers is quite versatile and can mimic many different stress variation signatures. For this study, ESM wafers were built with strong across-wafer stress variation and another ESM wafer set was built with strong intrafield stress variation. IPD was extensively characterized in two different ways: using standard overlay error metrology and using PWG metrology. Strong correlation is observed between these two independent sets of data, indicating that the PIR metric is able to clearly see wafer distortions. We have taken another step forward by using PIR data from the PWG tool to correct process-induced overlay error by feedforward to the exposure tool, a novel method that we call PWG-FF. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Brunner, T.; Menon, V.; Wong, C.; Felix, N.; Pike, M.; Gluschenkov, O.; Belyansky, M.; Vukkadala, P.; Veeraraghavan, S.; Klein, S.; Hoo, C. H.; Sinha, J.

2014-03-01

387

Effects of Wafer Precleaning and Plasma Irradiation to Wafer Surfaces on Plasma-Assisted Surface-Activated Direct Bonding  

NASA Astrophysics Data System (ADS)

The plasma-assisted surface-activated bonding technique enables one to directly bond heterogeneous materials. The surface roughness of wafers is an important factor for achieving bonding. The effects of precleaning and plasma surface activation processes on the surface roughness are investigated for silicon-on-insulator (SOI), Ce-substituted yttrium iron garnet (Ce:YIG), InP and LiNbO3. We found that an appropriate precleaning process reduces the surface roughness. Also, the oxygen plasma irradiation to the wafer surface for 10 or 30 s smoothens the surfaces. We achieved the bonding of SOI-Ce:YIG with a strength greater than 1.8 MPa, which is sufficient for application to silicon waveguide optical isolators and circulators.

Takei, Ryohei; Yoshida, Kohei; Mizumoto, Tetsuya

2010-08-01

388

Gas cluster ion beam processing of gallium antimonide wafers for surface and sub-surface damage reduction  

NASA Astrophysics Data System (ADS)

In order to bring low-power epitaxy-based gallium antimonide (GaSb) electronics and electro-optics to market, high-quality GaSb substrates with smooth surfaces and no surface damage are required. Here, a novel final polishing technique, gas cluster ion beam (GCIB) processing, is shown to improve the surface finish of chemical-mechanical polished (CMP) 50 mm (1 0 0) GaSb wafers by etching and smoothing CMP surface atoms through the sub-surface damage. For the first time, a fluorine-based gas cluster ion beam is reported for GCIB surface etching and smoothing of GaSb material. For the selected processing sequence, the surface roughness of a high-quality, 0.70 nm RMS GaSb wafer was reduced to 0.18 nm RMS without any observed changes in the full-widths at half-maximum (FWHM) of the (4 0 0) and (1 1 1) X-ray peaks of 14 and 20 arcsec, respectively. Results indicate that the GCIB process did not contribute to wafer surface or sub-surface polish damage. In a second case, a GCIB etch removed 200 nm of material from a non-optimal CMP (1 0 0) GaSb surface and reduced the full-width at half-maximum (1 1 1) X-ray peak from 76 to 52 arcsec in conjunction with a surface roughness decrease from 0.70 to 0.35 nm RMS. The data suggests that GCIB processing appears to be promising as a final GaSb wafer polish with an etch rate compatible for large scale manufacturing.

Li, X.; Goodhue, W. D.; Santeufeimio, C.; Tetreault, T. G.; MacCrimmon, R.; Allen, L. P.; Bliss, D.; Krishnaswami, K.; Sung, C.

2003-09-01

389

Wafer level hermetic package and device testing of a SOI-MEMS switch for biomedical applications  

NASA Astrophysics Data System (ADS)

We have designed a wafer level chip scale package for a bi-stable SOI-MEMS dc switch using a silicon-glass hermetic seal with through the lid feedthroughs. Bonded at 365 °C, 230 V and 250 kg, they pass the fine/gross leak test after thermal cycling and mechanical shock/vibration according to MIL-STD-833, fulfilling the requirements for biomedical applications. The measured shear strength is 114 ± 26 N in correspondence with the theoretically expected 100 N. Ruthenium microcontacts are a factor of 100 more robust than gold microcontacts, being stable over 106 cycles measured in a N2 atmosphere inside the package presented here. Future work will include a more extensive bond quality assessment and continued microcontact reliability measurements.

Receveur, Rogier A. M.; Zickar, Michael; Marxer, Cornel; Larik, Vincent; de Rooij, Nicolaas F.

2006-04-01

390

Two-dimensional X-ray waveguides: fabrication by wafer-bonding process and characterization  

NASA Astrophysics Data System (ADS)

The fabrication of two-dimensionally confining X-ray waveguides enables the generation of nanoscopic X-ray beams. First applications of such waveguides for lens-less holographic imaging have already been demonstrated, but were limited by the fabrication methods and the design. To overcome these limitations, we present here the fabrication process for a second generation of X-ray waveguide with air or vacuum as guiding channel, based on e-beam lithography, ion etching and subsequent wafer bonding. This is a first step towards waveguides fulfilling requirements of high transmission and high confinement, since the process can be scaled down to smaller channel dimensions from the present structures. We address the structuring method used and present results of first X-ray characterization at synchrotron beamlines, under two entirely different beam settings, corresponding to the coupling of a coherent beam and an incoherent beam.

Kohlstedt, A.; Kalbfleisch, S.; Salditt, T.; Reiche, M.; Gösele, U.; Lima, E.; Willmott, P.

2008-04-01

391

Results on aligned SiO2\\/SiO2 direct wafer-to-wafer low temperature bonding for 3D integration  

Microsoft Academic Search

To meet future 3D stacking requirements on wafer-to-wafer level, we successfully demonstrate oxide-oxide direct bonding on 200 mm with and without copper level utilizing face-to-face alignment and bonding within one process module as well as on the same chuck.

A. Garnier; M. Angermayer; L. Di Cioccio; P. Gueguen; T. Wagenleitner

2009-01-01

392

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements  

NASA Astrophysics Data System (ADS)

Controlling overlay errors resulting from wafer processing, such as film deposition, is essential for meeting overlay budgets in future generations of devices. Out-of-plane distortions induced on the wafer due to processing are often monitored through high-resolution wafer geometry measurements. While such wafer geometry measurements provide information about the wafer distortion, mechanics models are required to connect such measurements to overlay errors, which result from in-plane distortions. The aim of this paper is to establish fundamental connections between the out-ofplane distortions that are characterized in wafer geometry measurements and the in-plane distortions on the wafer surface that lead to overlay errors. First, an analytical mechanics model is presented to provide insight into the connection between changes in wafer geometry and overlay. The analytical model demonstrates that the local slope of the change in wafer shape induced by the deposition of a residually stressed film is related to the induced overlay for simple geometries. Finite element modeling is then used to consider realistic wafer geometries and assess correlations between the local slope of the wafer shape change induced by the deposition of a stressed film and overlay. As established previously, overlay errors only result when the stresses in the film are non-uniform, thus the finite element study considers wafers with several different nonuniform residual stress distributions. Correlation between overlay and a metric based on a corrected wafer slope map is examined. The results of the modeling and simulations are discussed and compared to recently published experimental results.

Turner, K. T.; Vukkadala, P.; Veeraraghavan, S.; Sinha, J. K.

2014-04-01

393

Improvements in 0.5-micron production wafer steppers  

NASA Astrophysics Data System (ADS)

i-line wafer steppers have become the tool of choice for submicron production of advanced integrated circuits. These tools are now being extended to provide the required resolution, linewidth control, and overlay performance for devices with 16 Mb packing densities. To achieve this a manufacturing environment, suitable control procedures should be designed to minimize process and equipment variations. The primary goal of this paper is to characterize and quantify the ability of current generation steppers to meet or exceed the 100 nm AA (single machine) and the 175 nm BC (stepper to any other stepper in a production area) overlay requirements for half-micron production. For this, an overlay experiment using one reference and 12 randomly selected steppers was performed. Two Point through the lens alignment was used to reference wafer to reticle. Stages with three interferometrically controlled axes having both standard and enhanced resolution were used in the experiment. Features to improve stage positioning and overlay accuracy are discussed. To generate the required data, accurately calibrated reference wafers are used. The results were compared with a metrology model, which was used to optimize the matching of stepper lens and stage grid distortions so that optimum matching performance is achieved. The results then clearly predict whether all steppers meet the stringent overlay requirements for half-micron lithography in a production environment. In addition, experimental results show half-micron resolution performance with a number of commercially available i-line photoresists. Lens performance as affected by a phase-shifted reticle tooling are also examined to determine its potential benefit to 0.5 micron and sub-0.5 micron production.

Luehrmann, Paul F.; de Mol, Chris G.; van Hout, Frits J.; George, Richard A.; van der Putten, Harrie B.

1991-07-01

394

Alternative fabrication process for edgeless detectors on 6 in. wafers  

NASA Astrophysics Data System (ADS)

VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150 ?m thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 5×5 and 1×1 cm2 edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.4×1.4 cm2 Medipix2 edgeless pixel detectors were also fabricated.This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100 ?m from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50-70 nA/cm2 and 580-660 pF/cm2 at, respectively, 40 V reverse bias for the p-on-n. For the n-on-n design these parameters were 116-118 nA/cm2 and 930-960 pF/cm2. The breakdown voltages were above 150 V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13-28 V.

Kalliopuska, Juha; Eränen, Simo; Virolainen, Tuula

2011-05-01

395

Multiproject wafers: not just for million-dollar mask sets  

NASA Astrophysics Data System (ADS)

With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task dictates careful consideration of the alternative methods.

Morse, Richard D.

2003-06-01

396

New criterion about the topography of W-CMP wafer's alignment mark  

NASA Astrophysics Data System (ADS)

Alignment error that originates in the actual wafer process is one of the factors to deteriorate total overlay accuracy. This error has been called wafer induced shift (WIS). WIS occurs through a change of alignment marks topography under the actual wafer processing. To quantify mark asymmetry WIS, we study the mark asymmetry on tungsten chemical mechanical polishing (CMP) wafers by using an atomic force microscope and define new criterion in this paper. The mark topography of CMP process wafers are measured by AFM and quantified using the new criterion. The asymmetry of the mark topography can be quantified by measuring the profiles of an alignment mark across the wafers. It has been proven, that the rotation error is caused by the asymmetry of the mark topography and the asymmetry is not related to the line width of the mark.

Ina, Hideki; Matsumoto, Takahiro; Sentoku, Koichi; Matsuyama, Katsuhiro; Katagiri, Kazuhiko

2003-05-01

397

Addressable Inverter Matrix Tests Integrated-Circuit Wafer  

NASA Technical Reports Server (NTRS)

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Buehler, Martin G.

1988-01-01

398

Advanced Ceramic Wafer Seals Demonstrated at 2000 deg. F  

NASA Technical Reports Server (NTRS)

Durable, high-temperature sliding seals are required in advanced hypersonic engines and around movable control surfaces on future vehicles. These seals must operate at temperatures of 2000 to 2500 F, limit hot gas flow, remain resilient for multiple cycles, and resist scrubbing damage against rough surfaces. Current seal designs do not meet these demanding requirements, so the NASA Glenn Research Center is developing advanced seals and preload devices to overcome these shortfalls. An advanced ceramic wafer seal design and two silicon nitride compression spring designs were evaluated in a series of compression, scrub, and flow tests.

Dunlap, Patrick H.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2005-01-01

399

Three-dimensional wafer stacking with vertical interconnects  

US Patent & Trademark Office Database

Described are three-dimensional stacked semiconductor structures having one or more vertical interconnects. Vertical stacking relies on vertical interconnects and wafer bonding using a patternable polymer. The polymer is preferably lithographically patternable and photosensitive. Curing of the polymer is preselected from about 35% to up to about 100%, depending on a desired outcome. When fabricated, such vertically stacked structures include electrical interconnects provided by solder reflow. Solder reflow temperature is bounded by a curing and glass transition temperatures of a polymer used for bonding.

2014-06-03

400

Characterization of wafer charging mechanisms and oxide survival prediction methodology  

SciTech Connect

Unipolar, EEPROM-based peak potential sensors and current sensors have been used to characterize the I-V relationship of charging transients which devices normally experience during the course of ion implantation. The results indicate that the charging sources may appear to behave like current-sources or voltage-sources, depending on the impedance of the load. This behavior may be understood in terms of plasma concepts. The ability to empirically characterize the I-V characteristics of charging sources using the CHARM-2 monitor wafers opens the way for prediction of failure rates of oxides subjected to specific processes, if the oxide Q{sub bd} distributions are known.

Lukaszek, W.; Dixon, W. [Stanford Univ., CA (United States). Center for Integrated Systems; Vella, M. [Lawrence Berkeley Lab., CA (United States). Accelerator and Fusion Research Div.; Messick, C.; Reno, S.; Shideler, J. [National Semiconductor, West Jordan, UT (United States)

1994-04-01

401

THz quantum cascade lasers with wafer bonded active regions.  

PubMed

We demonstrate terahertz quantum-cascade lasers with a 30 ?m thick double-metal waveguide, which are fabricated by stacking two 15 ?m thick active regions using a wafer bonding process. By increasing the active region thickness more optical power is generated inside the cavity, the waveguide losses are decreased and the far-field is improved due to a larger facet aperture. In this way the output power is increased by significantly more than a factor of 2 without reducing the maximum operating temperature and without increasing the threshold current. PMID:23188348

Brandstetter, M; Deutsch, C; Benz, A; Cole, G D; Detz, H; Andrews, A M; Schrenk, W; Strasser, G; Unterrainer, K

2012-10-01

402

Propagation of Nd-laser pulses through crystalline silicon wafers  

SciTech Connect

Propagation of pulses from an Nd:YAG laser (wavelength, 1.064 {mu}m; pulse duration, 270 ns; pulse energy, 225 {mu}J) through crystalline silicon wafers is studied experimentally. Mathematical modelling of the process is performed: the heat conduction equation is solved numerically, the temperature dependences of the absorption and refraction of a substance, as well as generation of nonequilibrium carriers by radiation are taken into account. The constructed model satisfactorily explains the experimentally observed intensity oscillations of transmitted radiation. (interaction of laser radiation with matter)

Kirichenko, N A; Kuzmin, P G; Shcherbina, M E [Wave Research Center, A.M. Prokhorov General Physics Institute, Russian Academy of Sciences, Moscow (Russian Federation)

2011-07-31

403

Network analyzer calibration for cryogenic on-wafer measurements  

SciTech Connect

A cryogenic probe station for on-wafer microwave measurements has been developed at Sandia National Laboratories to explore the basic device physics and characterize advanced components for low-temperature applications. The station was designed to operate over a temperature range of 20 to 300 K with a frequency range of DC to 50 GHz. Due to the vacuum and the low temperature environment, the use of microwave probes and the calibration of network analyzer measurements are somewhat elaborate. This paper presents guidelines for probe use and calibration in this environment.

Hietala, V.M.; Housel, M.S.; Caldwell, R.B.

1994-04-01

404

Retrospective comparison of Traditional vs. LigaSure impact dissection during pancreatoduodenectomy: how to save money by using an expensive device.  

PubMed

Pancreatoduodenectomy is an exceptional procedure that requires an extensive dissection of the supramesocolic region extended to the first jejunal limb. Lymphadenectomy, required for cancer, increases the dissection surface. The extensive preparation of the area is traditionally conducted with bipolar ormonopolar instruments, while clips, ligatures, and sutures are used for haemostasis. LigaSure™ vessel sealing(LSVS; Valleylab, Boulder, CO) is a technology that obtains vessel closure by using the body's own collagen and elastin to create a permanent fusion zone. This is obtained by a combination of forceps pressure and radio frequency. This effect has been improved by the introduction of the Force Triad™ (Valleylab, Boulder,CO) energy platform, controlled by TissueFect™ (Valleylab, Boulder, CO) sensing technology. With this device, the surgeon is able to fuse vessels up to 7 mm, lymphatics, tissue bundles, and pulmonary vasculature in a fast-seal cycle of almost 4 seconds. In our daily practice of open surgery we observe a rapid improvement of abdominal drainage output with a drastic reduction of protein loss. Its practical significance is, in our opinion, that we obtain a rapid recovery of normal serum protein levels with a low number of blood/plasmasac transfusions and a real improvement of anastomosis healing. Moreover, the efficacy and the speed of work of the device allow us to reduce the operating time significantly but safely. We performed a retrospective analysis of the data of 20 pancreatic resections conducted both with traditional dissection and with the Liga-Sure Impact device with Force Triad platform in order to verify whether observed data were real. Our clinical results show that the use of the LigaSure Impact device with Force Triad energy platform is really useful in open surgery to save operating time, number of postoperative days, and hemoderivate administration. PMID:24081851

Piccinni, Giuseppe; Pasculli, Alessandro; D'Ambrosio, Erasmina; Gurrado, Angela; Lissidini, Germana; Testini, Mario

2013-09-01

405

A 2–40 GHz Probe Station Based Setup for On-Wafer Antenna Measurements  

Microsoft Academic Search

A probe station based setup for on-wafer antenna measurements is presented. The setup allows for measurement of return loss and radiation patterns of an on-wafer antenna-hence-forth referred to as the antenna under test (AUT), radiating at broadside and fed through a coplanar waveguide (CPW). It eliminates the need for wafer dicing and custom-built test fixtures with coaxial connectors or waveguide

Koen Van Caekenberghe; Kenneth M. Brakora; Wonbin Hong; Karan Jumani; Dahan Liao; Mustafa Rangwala; Yun-Zhen Wee; Xinen Zhu; Kamal Sarabandi

2008-01-01

406

Type conversion of boron-doped silicon wafers by 3MeV proton irradiation  

Microsoft Academic Search

Proton irradiation was conducted on Czochralski (Cz) and floating zone (Fz) boron-doped p-type Si wafers at room temperature with the doses ranging from 1×1013 cm-2 to 2×10 15 cm-2. A p-n junction formed in the Cz wafers when the dose reached a value between 1.0×1013 cm-2 and 3×1013 cm-2 while a p-n-p structure formed in the Fz wafers. The formation

Min-Doo Chun; Donghwan Kim; Jaebum Choo; Joo-Youl Huh

2000-01-01

407

Comparison of surface polishing techniques used for InP wafers  

NASA Astrophysics Data System (ADS)

InP wafers prepared using different polishing and mounting methods were compared by Makyoh topography, which is capable of detecting extremely small surface height variations. In some wafers a cellular surface ridge structure due to uneven mounting wax distribution was observed. It is shown that the ridge structure can be completely eliminated by the optimisation of the wafer mounting procedure or by the use of a "free floating" double sided polishing technique.

Laczik, Z.; Booker, G. R.; Mowbray, A.

408

Residual polishing damage and surface quality of commercial InP wafers: A scanning PL study  

Microsoft Academic Search

The photoluminescence (PL) method has been used to investigate defects associated with surface polishing damage present in as-received commercial (100) LEC InP wafers. The wafers were chemically angle-polished to produce a surface bevel angle of ~ 0.01 ° using the method previously developed by Huber, but were not subsequently defect etched. For ‘as-polished’ wafers, total-light RT 2-D scanning PL images

Z. Laczik; G. R. Booker; A. Mowbray

1996-01-01

409

Study of low temperature GaAs\\/InP wafer bonding  

Microsoft Academic Search

The low temperature bonding of GaAs\\/InP wafers is successfully realized by a new surface treatment at 380°. The properties of the bonded structures are studied in terms of the interface shape, electrical and optical characteristic. The low temperature bonding of GaAs\\/InP wafers is successfully realized by a new surface treatment at 380°. In this method, the surfaces of two wafers

Xingyan Wang; Hui Huang; Qi Wang; Xiaomin Ren; Yongqing Huang

2005-01-01

410

Plasma-assisted InP-to-Si low temperature wafer bonding  

Microsoft Academic Search

The applicability of wafer bonding as a tool to integrate the dissimilar material system InP-to-Si is presented and discussed with recent examples of InP-based optoelectronic devices on Si. From there, the lowering of annealing temperature in wafer bonding by plasma-assisted bonding is the essence of this review paper. Lower annealing temperatures would further launch wafer bonding as a competitive technology

Donato Pasquariello; Klas Hjort

2002-01-01

411

Mirror polishing of InP wafer surfaces with NaOCl-citric acid  

Microsoft Academic Search

This paper describes new polishing solutions using NaOCl and citric acid for polishing InP wafers. The NaOCl solution and citric acid in water are separately supplied and mixed on a polishing pad. The liberated chlorine in the mixed solution etches the InP wafer surfaces. Mirror polished InP wafers with good surface roughness are prepared with an optimized solution; Rmax is

Y. Morisawa; I. Kikuma; N. Takayama; M. Takeuchi

1996-01-01

412

Low-Frequency-Noise Spectroscopy of SIMOX and Bonded SOI Wafers  

Microsoft Academic Search

Pseudo-MOSFET structures with metal source, drain, and guard electrodes are used to measure the low-frequency-noise characteristics of Separation by IMplantation of OXygen (SIMOX) and bonded silicon-on-insulator (SOI) wafers. The noise power spectra in the devices made from bonded SOI wafers are almost an order of magnitude lower than those made from SIMOX wafers. This is attributed to the lower interface

Vadim A. Kushner; Dieter K. Schroder; Trevor J. Thornton

2007-01-01

413

Automated array assembly task in-depth study of silicon wafer surface texturizing  

NASA Technical Reports Server (NTRS)

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

414

Efficient heterojunction solar cells on p-type crystal silicon wafers  

Microsoft Academic Search

Efficient crystalline silicon heterojunction solar cells are fabricated on p-type wafers using amorphous silicon emitter and back contact layers. The independently confirmed AM1.5 conversion efficiencies are 19.3% on a float-zone wafer and 18.8% on a Czochralski wafer; conversion efficiencies show no significant light-induced degradation. The best open-circuit voltage is above 700 mV. Surface cleaning and passivation play important roles in

Qi Wang; M. R. Page; E. Iwaniczko; Yueqin Xu; L. Roybal; R. Bauer; B. To; H.-C. Yuan; A. Duda; F. Hasoon; Y. F. Yan; D. Levi; D. Meier; Howard M. Branz; T. H. Wang

2010-01-01

415

Efficient heterojunction solar cells on p-type crystal silicon wafers  

NASA Astrophysics Data System (ADS)

Efficient crystalline silicon heterojunction solar cells are fabricated on p-type wafers using amorphous silicon emitter and back contact layers. The independently confirmed AM1.5 conversion efficiencies are 19.3% on a float-zone wafer and 18.8% on a Czochralski wafer; conversion efficiencies show no significant light-induced degradation. The best open-circuit voltage is above 700 mV. Surface cleaning and passivation play important roles in heterojunction solar cell performance.

Wang, Qi; Page, M. R.; Iwaniczko, E.; Xu, Yueqin; Roybal, L.; Bauer, R.; To, B.; Yuan, H.-C.; Duda, A.; Hasoon, F.; Yan, Y. F.; Levi, D.; Meier, D.; Branz, Howard M.; Wang, T. H.

2010-01-01

416

Improved surface quality of anisotropically etched silicon {111} planes for mm-scale optics  

NASA Astrophysics Data System (ADS)

We have studied the surface quality of millimetre-scale optical mirrors produced by etching CZ and FZ silicon wafers in potassium hydroxide to expose the {111} planes. We find that the FZ surfaces have four times lower noise power at spatial frequencies up to 500?mm-1. We conclude that mirrors made using FZ wafers have higher optical quality.

Cotter, J. P.; Zeimpekis, I.; Kraft, M.; Hinds, E. A.

2013-11-01

417

Ultra light-weight and high-resolution X-ray mirrors using DRIE and X-ray LIGA techniques for space X-ray telescopes  

Microsoft Academic Search

We are developing novel ultra light-weight and high-resolution X-ray micro pore optics for space X-ray telescopes. In our\\u000a method, curvilinear micro pore structures are firstly fabricated by silicon deep reactive ion etching (DRIE) or X-ray LIGA\\u000a processes. Secondly, side walls of the micro structures are smoothed by magnetic field assisted finishing and\\/or hydrogen\\u000a annealing techniques for high reflectivity mirrors. Thirdly,

Yuichiro EzoeIkuyuki; Ikuyuki Mitsuishi; Utako Takagi; Masaki Koshiishi; Kazuhisa Mitsuda; Noriko Y. Yamasaki; Takaya Ohashi; Fumiki Kato; Susumu Sugiyama; Raul E. Riveros; Hitomi Yamaguchi; Shinya Fujihira; Yoshiaki Kanamori; Kohei Morishita; Kazuo Nakajima; Ryutaro Maeda

2010-01-01

418

Rapid, large area mapping of defect concentration in semiconductor wafers by infrared absorption  

NASA Astrophysics Data System (ADS)

We report a fast, nondestructive method of mapping defect concentrations over large areas of semiconductor wafers. The method uses a platinum silicide staring focal plane array (FPA) camera to image wafers quickly and with high resolution in the near infrared band. The camera collects data simultaneously from 78,000 points on a 100 mm diameter wafer. For each point, the defect-related absorption coefficient was determined and converted to defect density. The entire process requires about 5 min. This method was demonstrated by measuring and mapping EL2 concentration in undoped semi-insulating liquid encapsulated Czochralski gallium arsenide wafers.

Leahy, D. J.; Mooney, J. M.; Alexander, M. N.; Chi, M. M.; Mil'shtein, S.

1998-03-01

419

Mirror polishing of InP wafer surfaces with NaOCl-citric acid  

NASA Astrophysics Data System (ADS)

This paper describes new polishing solutions using NaOCl and citric acid for polishing InP wafers. The NaOCl solution and citric acid in water are separately supplied and mixed on a polishing pad. The liberated chlorine in the mixed solution etches the InP wafer surfaces. Mirror polished InP wafers with good surface roughness are prepared with an optimized solution; Rmax is 0.8 nm and Ra is 0.1 nm. No damage is observed on the mirror-finish surfaces of the InP wafers.

Morisawa, Y.; Kikuma, I.; Takayama, N.; Takeuchi, M.

1996-02-01

420

How accurate are rapid prototyped (RP) final orthognathic surgical wafers? A pilot study.  

PubMed

Computer packages have been introduced to simulate the movements of the jaw in three dimensions to facilitate planning of treatment. After final 3-dimensional virtual planning, a rapid prototype wafer can be manufactured and used in theatre. Our aim was to assess the accuracy of rapid prototyping of virtual wafers derived from laser scanned dental models using CAD/CAM software. Upper and lower plaster models from 10 orthognathic patients, the articulated models, and the conventional wafers were scanned. The virtual wafers were made from CAD/CAM software, and printed on a stereolithographic printer. We also scanned the articulated models with rapid prototype wafers in place. The validity of the final rapid prototype wafer was measured by the accuracy with which upper and lower models related to one another. The absolute mean error of the rapid prototype wafer when aligned with the dental models was 0.94 (0.09) mm. The absolute distance of the 2 models articulated by conventional and rapid prototype wafers ranged from 0.04 - 1.73mm. The rapid prototype wafers were able to orientate the upper and lower dental models with an absolute mean error of 0.94 (0.09) mm, but it ranged from 0.04-1.73mm. PMID:24933576

Shqaidef, Abedalrahman; Ayoub, Ashraf F; Khambay, Balvinder S

2014-09-01

421

Pressureless wafer bonding by turning hillocks into abnormal grain growths in Ag films  

NASA Astrophysics Data System (ADS)

We demonstrate pressureless wafer bonding using silver abnormal grain growth caused by stress migration at 250 °C, which is very low for a direct solid-state bonding temperature. The bonding achieved a die-shear strength of more than 50 MPa, which exceeds the fracture toughness of Si wafer. Various deposition temperatures for the silver films, i.e., initial residual stress, reveal that the bonding process is driven by thermomechanical stress. Abnormal grain growth is induced at the contact interface instead of hillocks growing on the film surface. Pressureless wafer bonding can be applied to advanced devices such as thin-wafer multi-chip integrations.

Oh, Chulmin; Nagao, Shijo; Kunimune, Teppei; Suganuma, Katsuaki

2014-04-01

422

Dual-Side Wafer Processing and Resonant Tunneling Transistor Applications  

SciTech Connect

We describe dual-side wafer processing and its application to resonant tunneling transistors in a planar configuration. The fabrication technique utilizes a novel flip-chip, wafer thinning process called epoxy-bond and stop-etch (EBASE) process, where the substrate material is removed by selective wet etching and stopped at an etch-stop layer. This EBASE method results in a semiconductor epitaxial layer that is typically less than a micron thick and has a mirror-finish, allowing backside gates to be placed in close proximity to frontside gates. Utilizing this technique, a resonant tunneling transistor--the double electron layer tunneling transistor (DELTT)--can be fabricated in a fully planar configuration, where the tunneling between two selectively-contacted 2DEGs in GaAs or InGaAs quantum wells is modulated by surface Schottky gate. Low temperature electrical characterization yields source-drain I-V curves with a gate-tunable negative differential resistance.

Moon, J.S.; Simmons, J.A.; Wendt, J.R.; Hietala, V.M.; Reno, J.L.; Baca, W.E.; Blount, M.A.

1999-07-20

423

Laser-Assisted Chemical Polishing of Silicon (112) Wafers  

NASA Astrophysics Data System (ADS)

Pulsed laser-assisted chemical etching (PLACE) offers an advanced, novel substrate preparation method for molecular beam epitaxy (MBE) growth of mercury cadmium telluride on silicon (112) wafers. By controlling the laser fluence, the chemical etch process is refined into a final polish step. PLACE offers surface roughness on the order of chemical mechanical polishing standards and has been verified by 488-nm Raman and high-resolution x-ray diffraction as causing no surface or subsurface damage. To the contrary, experiments show that using PLACE not only alters the surface chemically but also removes subsurface damage through recrystallization reaching micron depths. The process occurs in a modular vacuum chamber that could conceivably be transferred between tools so that vacuum is not broken between polishing and MBE deposition. PLACE can achieve ultra-high-purity and fine dimensional control since it is a dry process relying on pyrolytic vapor-phase reactions initiated, and constrained, by a pulsed laser. Since the process is a function of laser fluence and optics, it is imminently scalable to 6-inch wafer sizes and beyond.

Dandekar, Niru; Chivas, Robert; Silverman, Scott; Kou, Xiaolu; Goorsky, Mark

2012-10-01

424

Cryogenic wafer-level MWIR camera: laboratory demonstration  

NASA Astrophysics Data System (ADS)

We present a compact infrared cryogenic multichannel camera with a wide field of view equal to 120°. By merging the optics with the detector, the concept has to be compatible with both cryogenic constraints and wafer-level fabrication. For this, we take advantage of the progress in micro-optics to design a multichannel optical architecture directly integrated on the detector. This wafer-level camera uses state of art microlenses with a high sag height. The additional mass of the optics is sufficiently small to be compatible with the cryogenic environment of the Dewar. The performance of this camera will be discussed. Its characterization has been carried out in terms of modulation transfer function and noise equivalent temperature difference (NETD). The optical system is limited by the diffraction. By cooling the optics, we achieve a very low NETD equal to 15 mK compared with traditional infrared cameras. A postprocessing algorithm that aims at reconstructing a well-sampled image from the set of undersampled raw subimages produced by the camera is proposed and validated on experimental images.

Druart, G.; De La Barrière, F.; Chambon, M.; Guérineau, N.; Lasfargues, G.; Fendler, M.

2013-06-01

425

Reticle process monitoring and qualification based on reticle CDU and wafer CDU correlation  

NASA Astrophysics Data System (ADS)

Reticle process of record (POR) sometimes needs fine tuning for some reasons such as multiple layer process, better critical dimension uniformity (CDU) or new etch chamber. The sidewall angle and corner rounding will be varied due to the reticle processing tuned comparing to previous POR. However, because the reticle critical dimension (CD) measurement is based on middle side lobe measurement or other algorithm, the reticle CD cannot reflect the changes of reticle sidewall angle and corner rounding variation which are critical for 65nm node and below. Each of the scanner, wafer process, reticle and metrology tool contributes to the intra-field wafer CD. Normally, the reticle contribution to the wafer CDU should be as small as possible, that is less than 33%. By averaging all wafer CD of individual features to obtain a wafer CD reference independent of feature location and wafer die, the correlation of wafer measurement to target (MTT) and reticle MTT can be obtained. The correlation can accurately qualify and monitor the tuning processing of reticle. We have manufactured two masks for active layer of 65nm tech node by different reticle process. One used the original POR process of active layer, while another used multi-layer-reticle (MLR) process. The correlations between wafer CDU and reticle CDU of these reticles are demonstrated for both isolated and dense features in vertical and horizontal direction, respectively. Similar experiments were implemented and the correlations for both dense and isolated structures are demonstrated as well, for two different POR process for first metal layer of 40nm tech node. Referring to the wafer and reticle MTT correlation, the contribution of reticle CDU to wafer CDU can be used as an evaluation methodology for reticle processing. The wafer and reticle CDU correlations for 45nm node poly and contact layers POR process are also demonstrated.

Ning, Guoxiang; Choi, Byoung Il; Holfeld, Christian; Ngow, Yee Ta; Tan, Sia Kim; Tchikoulaeva, Anna; Gn, Fang Hong

2011-10-01

426

Reaching a CD uniformity of below 3 nm for 300 mm post-etch wafers by adjusting the CD distribution of ADI wafers  

Microsoft Academic Search

Obtaining good post-etching CD uniformity is getting more and more important in advanced processes such as 90 nm, 65 nm, and even 45nm for 300 mm wafers. But process noise greatly impacts the CD uniformity, especially etching bias and metrology noise. To achieve a CD uniformity of below 3 nm for 300 mm post-etch wafers, the metrology noise and process

Jie-Wei Sun; Yong-Fa Huang; Sho-Shen Lee; Chun-Chi Yu; Benjamin S. Lin; Steven Fu; Mike Slessor

2005-01-01

427

Meso-scale machining capabilities and issues  

SciTech Connect

Meso-scale manufacturing processes are bridging the gap between silicon-based MEMS processes and conventional miniature machining. These processes can fabricate two and three-dimensional parts having micron size features in traditional materials such as stainless steels, rare earth magnets, ceramics, and glass. Meso-scale processes that are currently available include, focused ion beam sputtering, micro-milling, micro-turning, excimer laser ablation, femto-second laser ablation, and micro electro discharge machining. These meso-scale processes employ subtractive machining technologies (i.e., material removal), unlike LIGA, which is an additive meso-scale process. Meso-scale processes have different material capabilities and machining performance specifications. Machining performance specifications of interest include minimum feature size, feature tolerance, feature location accuracy, surface finish, and material removal rate. Sandia National Laboratories is developing meso-scale electro-mechanical components, which require meso-scale parts that move relative to one another. The meso-scale parts fabricated by subtractive meso-scale manufacturing processes have unique tribology issues because of the variety of materials and the surface conditions produced by the different meso-scale manufacturing processes.

BENAVIDES,GILBERT L.; ADAMS,DAVID P.; YANG,PIN

2000-05-15

428

Improvement of the surface quality of polished InP wafers  

Microsoft Academic Search

Indium phosphide wafers are often used as epi ready wafers. Especially for MOVPE grown structures, the electrical conduction at the interface between the semi insulating substrate and the epitaxial layer is a crucial issue. Silicon contamination is the origin of the interface conduction. We demonstrate that TOF-SIMS is a very powerful technique to characterise the surface and investigate any contamination

G. Jacob; P. Regreny; N. Thomas; H. Hardtdegen

1997-01-01

429

Across wafer focus mapping and its applications in advanced technology nodes  

Microsoft Academic Search

The understanding of focus variation across a wafer is crucial to CD control (both ACLV and AWLV) and pattern fidelity on the wafer and chip levels. This is particularly true for the 65nm node and beyond, where focus margin is shrinking with the design rules, and is turning out to be one of the key process variables that directly impact

Gary Zhang; Stephen DeMoor; Scott Jessen; Qizhi He; Winston Yan; Sopa Chevacharoenkul; Venugopal Vellanki; Patrick Reynolds; Joe Ganeshan; Jan Hauschild; Marco Pieters

2006-01-01

430

Evaluation of the Wafer-Level Voltage Ramp Test for Oxide Integrity.  

National Technical Information Service (NTIS)

This report has two objectives. First, it provides both an overview and a critique of the Joint Electronic Devices Engineering Council (JEDEC) 14.2 Committee on Wafer Level Reliability standard, JESD-35, 'Procedure for the Wafer-Level Testing of Thin Diel...

S. L. Drager

1996-01-01

431

Wafer level packaging technology development for CMOS image sensors using Through Silicon Vias  

Microsoft Academic Search

In this paper a low temperature dasiavia-lastrdquo technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. In the first part of this paper, the steps of the through silicon vias (TSV) technology will be presented: glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps like

J. Charbonnier; D. Henry; F. Jacquet; B. Aventurier; C. Brunet-Manquat; G. Enyedi; N. Bouzaida; V. Lapras; N. Sillon

2008-01-01

432

Low Voltage Soi CMOS Image Sensor with Pinned Photodiode on Handle Wafer  

Microsoft Academic Search

We have fabricated 32 × 32 SOI CMOS active pixel image sensor with pinned photodiode on handle wafer in order to reduce dark current, transfer charge completely, and improve spectral response. The four transistor type active pixel image sensor is comprised of reset and source follower transistors on SOI seed wafer, while the pinned photodiode, transfer gate, and floating diffusion

Yong-Soo Cho; Sie Young Choi; H. Takao; K. Sawada; M. Ishida

2006-01-01

433

Quantitative analysis of in situ wafer bowing measurements for III-nitride growth on sapphire  

Microsoft Academic Search

Wafer bowing measurements have been recently developed into an efficient tool for MOVPE and MBE process optimization. In combination with temperature and reflectance measurements they are applied for direct but mostly qualitative evaluation of III-nitride epitaxial growth processes. In this work, applying a quantitative analysis of wafer bowing throughout the full epitaxial process, we are able to trace the lattice

F. Brunner; A. Knauer; T. Schenk; M. Weyers; J.-T. Zettler

2008-01-01

434

Advanced ultrapure water systems with low dissolved oxygen for native oxide free wafer processing  

Microsoft Academic Search

In the manufacture of submicron or deep submicron ULSIs, it is important to completely suppress native oxide growth on the silicon wafer surfaces. In a wet process, dissolved oxygen must be removed from the ultrapure water used for the final rinsing of the wafer. Two independent systems for the supply of ultrapure water, augmented with new techniques to remove dissolved

Yasuyuki Yagi; Takashi Imaoka; Y. Ksama; Tadahiro Ohmi

1992-01-01

435

High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging  

Microsoft Academic Search

In this paper, we propose an equivalent circuit model of through wafer via which has height of 90 mum and diameter of 75 mum. The equivalent circuit model composed of RLCG components is developed based on the physical configuration of through wafer via. Then, the parameter values of the equivalent circuit model are fitted to the measured s-parameters up to

Chunghyun Ryu; Jiwang Lee; Hyein Lee; Kwangyong Lee; Taesung Oh; Joungho Kim

2006-01-01

436

Pioneering breakthroughs in implant monitor wafer cost reduction at 300 mm  

NASA Astrophysics Data System (ADS)

The semiconductor industry has been full of news regarding the transition to 300 mm wafers. In 1998, SEMICONDUCTOR300 (SC300) was the first to demonstrate the capability to produce integrated products on 300 mm wafers. To meet the challenge of maintaining quality while simultaneously reducing cost and ramping SC300 into pilot manufacturing, the authors have investigated the use of an overlay implant technique. A single 300 mm wafer is used to collect particle, high dose, and low dose information from a Eaton GSD HE-3 ion implanter. The implants, a high dose As+ 80 KeV 3E14 followed by a low dose As+ 60 KeV 3E11 damage implant, are measured using a KLA/Tencor Rs100 sheet resistance measurement tool with a 3 mm edge exclusion. In addition to verifying the technique at 300 mm, the paper presents overlay implant data collected using externally reclaimed wafers, currently one third the cost of prime 300 mm wafers, and explores the possibility of reusing implanted monitor wafers by re-annealing the wafers and repeating the low dose damage implant. Initial data is also presented for implants performed on the backside of 300 mm wafers.

Zeakes, Jason S.; Breeden, Terry A.

1999-08-01

437

Temperature Compensation in SAW Filters by Tri-Layer Wafer Engineering  

Microsoft Academic Search

Bonded wafer concept is modified by introduction of a third layer that is used for compensation (or even overcompensation) of wafer warping thus increasing the amount of stress at the upper surface of the piezoelectric LiTaO3 layer resulting in significant improvement of temperature coefficient of frequency (TCF), that may become zero or even positive. We have successfully demonstrated variants of

K. Bhattacharjee; A. Shvetsov; S. Zhgoon

2007-01-01

438

3D integration with AC coupling for wafer-level assembly  

Microsoft Academic Search

This paper presents a solution of stacked chips using a capacitive communication from electrodes at the last metal layer with a wafer level assembly process. The wafer level approach instead of the die level allows high throughput and enables further optimization of the capacitive structures. To reach a good AC coupling an additional passivation layer was deposited then planarized and

M. Scandiuzzo; L. Perugini; R. Cardu; M. Innocenti; R. Canegallo

2009-01-01

439

Recent progress in copper-based wafer bonding for 3-D ICs application  

Microsoft Academic Search

This article discusses thermo-compression bonding (also known as diffusion bonding) of metallic copper and its application in 3-D stacking of ICs. Bonding process is described and characterization results are presented. A survey on recent progress of copper-based wafer bonding, particularly low temperature process, and its application for on wafer 3-D ICs are presented.

Chuan Seng Tan

2008-01-01

440

Imprinted laminate wafer-level packaging for SAW ID-tags and SAW delay line sensors  

Microsoft Academic Search

We have developed a wafer-level packaging solu- tion for surface acoustic wave devices using imprinted dry film resist (DFR). The packaging process involves the preparation of an imprinted dry film resist that is aligned and laminated to the device wafer and requires one additional lithography step to define the package outline. Two commercial dry film solu- tions, SU-8 and TMMF,

Jan H. Kuypers; Shuji Tanaka; Masayoshi Esashi

2011-01-01

441

Infrared spectroscopy as a probe of fundamental processes in microelectronics: silicon wafer cleaning and bonding  

Microsoft Academic Search

In this paper, we review our recent infrared studies of the fundamental physical and chemical processes occurring at the interface of bonded silicon wafers, as a function of surface preparation and annealing temperature. We present a brief overview of the practical aspects of silicon-wafer bonding and the techniques used to evaluate the interface integrity, which highlight the need for fundamental

M. K. Weldon; V. E. Marsico; Y. J. Chabal; D. R. Hamann; S. B. Christman; E. E. Chaban

1996-01-01

442

Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer Fabrication  

Microsoft Academic Search

This paper concerns performance modeling of semiconductor manufacturing operations. More specifically, it focuses on queueing network models for an analysis of wafer fabrication facilities. The congestion problems that plague wafer fabrication facilities are described in general terms, and several years' operating data from one particular facility are summarized. A simple queueing network model of that facility is constructed, and the

HONG CHEN; J. MICHAEL HARRISON; AVI MANDELBAUM; ANN VAN ACKERE; LAWRENCE M. WEIN

1988-01-01

443

Effect of lubricant environment on saw damage in silicon wafers  

NASA Technical Reports Server (NTRS)

The chemomechanical effect of lubricant environments on the inner diameter (ID) sawing induced surface damage in Si wafers was tested for four different lubricants: water, dielectric oil, and two commercial cutting solutions. The effects of applying different potential on Si crystals during the sawing were also tested. It is indicated that the number and depth of surface damage are sensitive to the chemical nature of the saw lubricant. It is determined that the lubricants that are good catalysts for breaking Si bonds can dampen the out of plane blade vibration more effectively and produce less surface damage. Correlations between the applied potential and the depth of damage in the dielectric oil and one of the commercial cutting solutions and possible mechanisms involved are discussed.

Kuan, T. S.; Shih, K. K.; Vanvechten, J. A.; Westdorp, W. A.

1982-01-01

444

Characterization of semiconductor surface-emitting laser wafers  

SciTech Connect

The development of epitaxial semiconductor surface-emitting lasers has begun in recent years. These lasers are ultra-short (few {mu}m) Fabry-Perot resonators comprising epitaxial multilayer semiconductor mirrors and quantum well active regions. The resonators are single crystals grown along the lasing axis by molecular beam epitaxy (MBE) or chemical vapor deposition (CVD). They offer significant advances over conventional cleaved, edge-emitting lasers for creating lasers with single elements of 2 dimensional arrays, low beam divergence, engineered active regions, single longitudinal modes, and improved temperature characteristics. To realize the high potential of these new laser structures, techniques for characterizing the laser wafer after growth and between fabrication steps must be developed. In this paper we discuss several optical techniques that we have developed for this emerging surface-emitting laser technology.

Gourley, P.L.; Vawter, G.A.; Brennan, T.M.; Hammons, B.E.

1990-01-01

445

Visible luminescence from silicon wafers subjected to stain etches  

NASA Technical Reports Server (NTRS)

Etching of Si in a variety of solutions is known to cause staining. These stain layers consist of porous material similar to that produced by anodic etching of Si in HF solutions. In this work, photoluminescence peaked in the red from stain-etched Si wafers of different dopant types, concentrations, and orientations produced in solutions of HF:HNO3:H2O was observed. Luminescence is also observed in stain films produced in solutions of NaNO2 in HF, but not in stain films produced in solutions of CrO3 in HF. The luminescence spectra are similar to those reported recently for porous Si films produced by anodic etching in HF solutions. However, stain films are much easier to produce, requiring no special equipment.

Fathauer, R. W.; George, T.; Ksendzov, A.; Vasquez, R. P.

1992-01-01

446

Chemical strategies for die/wafer submicron alignment and bonding.  

SciTech Connect

This late-start LDRD explores chemical strategies that will enable sub-micron alignment accuracy of dies and wafers by exploiting the interfacial energies of chemical ligands. We have micropatterned commensurate features, such as 2-d arrays of micron-sized gold lines on the die to be bonded. Each gold line is functionalized with alkanethiol ligands before the die are brought into contact. The ligand interfacial energy is minimized when the lines on the die are brought into registration, due to favorable interactions between the complementary ligand tails. After registration is achieved, standard bonding techniques are used to create precision permanent bonds. We have computed the alignment forces and torque between two surfaces patterned with arrays of lines or square pads to illustrate how best to maximize the tendency to align. We also discuss complex, aperiodic patterns such as rectilinear pad assemblies, concentric circles, and spirals that point the way towards extremely precise alignment.

Martin, James Ellis; Baca, Alicia I.; Chu, Dahwey; Rohwer, Lauren Elizabeth Shea

2010-09-01

447

Imaging of electrically detected magnetic resonance of a silicon wafer.  

PubMed

An imaging technique of electrically detected magnetic resonance (EDMR) was newly developed. Because the EDMR signal is obtained from paramagnetic recombination centers, one may expect the image to represent the distribution of defect and/or impurity sites in the sample. We successfully obtained EDMR images of a light-illuminated silicon plate 8 mm in width and 15 mm in length, which was cut from a silicon wafer (n-type, 100 Omega cm), under ESR irradiation at a frequency of 890 MHz (wavelength, 340 mm). The reproducibility of the EDMR image obtained from a sample was amply satisfactory. When the oxidized surface of the silicon was removed, the EDMR signal disappeared. Although the EDMR signal reappeared when the surface of the sample became reoxidized, the EDMR image obtained was slightly different from the earlier one. This finding shows that the EDMR image obtained from the sample shows the distribution of defects at the Si/SiO(2) interface. PMID:11700087

Sato, T; Yokoyama, H; Ohya, H; Kamada, H

2001-11-01

448

Imaging of Electrically Detected Magnetic Resonance of a Silicon Wafer  

NASA Astrophysics Data System (ADS)

An imaging technique of electrically detected magnetic resonance (EDMR) was newly developed. Because the EDMR signal is obtained from paramagnetic recombination centers, one may expect the image to represent the distribution of defect and/or impurity sites in the sample. We successfully obtained EDMR images of a light-illuminated silicon plate 8 mm in width and 15 mm in length, which was cut from a silicon wafer ( n-type, 100 ? cm), under ESR irradiation at a frequency of 890 MHz (wavelength, 340 mm). The reproducibility of the EDMR image obtained from a sample was amply satisfactory. When the oxidized surface of the silicon was removed, the EDMR signal disappeared. Although the EDMR signal reappeared when the surface of the sample became reoxidized, the EDMR image obtained was slightly different from the earlier one. This finding shows that the EDMR image obtained from the sample shows the distribution of defects at the Si/SiO 2 interface.

Sato, Toshiyuki; Yokoyama, Hidekatsu; Ohya, Hiroaki; Kamada, Hitoshi

2001-11-01

449

Plasma ashing using microwaves via slot antenna for 300-mm wafers  

NASA Astrophysics Data System (ADS)

We developed a downflow asher which incorporates a large-sized microwave excited plasma source with a slot antennas, for 300 mm wafers. An ashing rate of 4.5 micrometer/min and uniformity of plus or minus 5.1% were obtained at a wafer temperature of 250 degrees Celsius. The ashing rate was approximately fourfold and the uniformity level was similar to those obtained with conventional downflow asher. The newly developed asher incorporates: (1) a high-density plasma source with slot antennas, (2) a processing chamber the shape of which is optimized by gas flow simulations and (3) a compact, high- speed wafer transportation system with an originally developed vacuum robot which is primarily responsible for the high ashing rate. The maximum overall throughput, including that of the transportation system, is 160 wafers/h. Application of this system to the ashing of 300 mm wafers is expected.

Furuya, Masaaki; Kano, Masaaki; Terai, Fujio; Aoki, Katsuaki; Yamauchi, Takeshi; Yamada, Katsuya; Tamai, Koichi; Azumano, Hidehito

1999-09-01

450

Modelling wafer bow in silicon-polycrystalline CVD diamond substrates for GaN-based devices  

NASA Astrophysics Data System (ADS)

Composite silicon-polycrystalline chemical vapour deposition (CVD) diamond wafers are potential substrates for GaN-based devices for use in harsh environments due to their high thermal conductivity and chemical stability. When cooled from a typical diamond deposition temperature of approximately 800 to 25 °C wafer bowing arises from a mismatch in the coefficients of thermal expansion of silicon and polycrystalline diamond. In this paper 100 mm diameter silicon-polycrystalline diamond wafers have been modelled using ANSYS finite element software to investigate their bowing behaviour as a function of temperature and geometry. The maximum bow of a wafer occurred where the thicknesses of both the silicon and polycrystalline diamond layers was almost identical; this has been confirmed using analytical methods. Strategies are discussed for reducing wafer bow.

Edwards, M. J.; Bowen, C. R.; Allsopp, D. W. E.; Dent, A. C. E.