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1

Wafer scale photonic-die attachment  

Microsoft Academic Search

A diebonding system has been developed for the bonding of photonic chips, such as lasers and photo detectors, at a rate suitable for low cost manufacturing. This system is designed for wafer scale diebonding, making it compatible with wafer scale fabrication. This system combines the passive positional optical alignment of photonic chips on a silicon or glass wafer board surface

Robert Boudreau; Ping Zhou; Terry Bowen

1998-01-01

2

A radix-8 wafer scale FFT processor  

Microsoft Academic Search

Wafer Scale Integration promises radical improvements in the performance of digital signal processing systems. This paper describes the design of a radix-8 systolic (pipeline) fast Fourier transform processor for implementation with wafer scale integration. By the use of the radix-8 FFT butterfly wafer that is currently under development, continuous data rates of 160 MSPS are anticipated for FFTs of up

Earl E. Swartzlander Jr.; Vijay K. Jain; Hiroomi Hikawa

1992-01-01

3

Gallium Arsenide wafer scale integration  

NASA Astrophysics Data System (ADS)

Gallium Arsenide (GaAs) digital MESFET technology has recently begun to appear in the semiconductor marketplace. The initial commercial offerings are at the small to medium scale integration levels. The high speed of these parts would seem to be very attractive for designers of high performance signal processing equipment. Persistent yield problems, however, have prevented the appearance of large scale integrated circuits. As a result, intrapackage and interpackage signal propagation problems such as coupling, parasitics and delay are likely to negate much of the benefits of the fast MESFET logic devices for large systems constructed with such small scale building blocks. An early packaging concept, Wafer Scale Integration (WSI), which could possibly be used to address some of these limitations is reexamined.

McDonald, J. F.; Taylor, G.; Steinvorth, R.; Donlan, B.; Bergendahl, A. S.

1985-08-01

4

CMOS compatible wafer scale adhesive bonding for circuit transfer  

Microsoft Academic Search

Reports on a transfer technique for CMOS circuits based on a newly developed bonding technique, namely wafer scale adhesive bonding using epoxies. The circuit transfer sequence consists of three steps: bonding a CMOS processed SIMOX wafer to a Pyrex glass wafer, thinning the SIMOX wafer down to the buried oxide and exposing the contact pads. A test chip was designed

S. van der Green; Maartein Rosmeulen; Philippe Jansen; Kris Baert; Ludo Deferm

1997-01-01

5

Wafer-scale micro-optics fabrication  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

Voelkel, Reinhard

2012-07-01

6

Parallel Assembly of LIGA Components  

SciTech Connect

In this paper, a prototype robotic workcell for the parallel assembly of LIGA components is described. A Cartesian robot is used to press 386 and 485 micron diameter pins into a LIGA substrate and then place a 3-inch diameter wafer with LIGA gears onto the pins. Upward and downward looking microscopes are used to locate holes in the LIGA substrate, pins to be pressed in the holes, and gears to be placed on the pins. This vision system can locate parts within 3 microns, while the Cartesian manipulator can place the parts within 0.4 microns.

Christenson, T.R.; Feddema, J.T.

1999-03-04

7

Wafer-Scale Microtensile Testing of Thin Films  

Microsoft Academic Search

This paper reports on the mechanical characterization of thin films using the microtensile technique performed for the first time at the wafer scale. Multiple test structures are processed and sequentially measured on the same silicon substrate, thus eliminating delicate handling of individual samples. The current layout uses 26 test structures evenly distributed over a 4-in wafer, each of them carrying

JoÃo Gaspar; Marek E. Schmidt; Jochen Held; Oliver Paul

2009-01-01

8

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off  

NASA Astrophysics Data System (ADS)

We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

Mieda, Eiko; Maeda, Tatsuro; Miyata, Noriyuki; Yasuda, Tetsuji; Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki; Aoki, Takeshi; Yamamoto, Taketsugu; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko; Ogawa, Arito; Kikuchi, Toshiyuki; Kunii, Yasuo

2015-03-01

9

Wafer-scale aluminum nano-plasmonics  

NASA Astrophysics Data System (ADS)

The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

2014-09-01

10

Scaling wafer stresses and thermal processes to large wafers 1 Presented at the TCMCTF '97. 1  

Microsoft Academic Search

Gravitational stresses limit maximum temperatures for processing semiconductor wafers. Allowable rates of heating and cooling are also limited by the combined affects of thermal and gravitational stresses, particularly in batch processing of stacked wafers. With increasing wafer diameter these limitations become more severe, requiring such measures as improved wafer support to maintain a desired processing temperature or increased wafer spacing

Robert H Nilson; Stewart K Griffiths

1998-01-01

11

LIGA Micromachining  

NSDL National Science Digital Library

This YouTube video, created by Southwest Center for Microsystems Education (SCME), provides an overview of the LIGA (Lithography, Electroplating, and Molding) technique for micromachining. The lecture runs for 7:25 seconds and describes LIGA as part of micromachining fabrication, including lithography, process, and post-process steps. More information can be found on the SCME website. 

12

Wafer level and substrate level chip scale packaging  

Microsoft Academic Search

Wafer level chip scale packaging (CSP) is gaining more momentum as a low cost, high performance solution for portable products. The design demands for portable products is particularly difficult since the designer must find solutions that provide a smaller footprint and higher performance, but at the same time must be cost competitive with current packaging offerings. To date, the fine

J. L. Young

1999-01-01

13

Liga developer apparatus system  

DOEpatents

A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

Boehme, Dale R. (Pleasanton, CA); Bankert, Michelle A. (San Francisco, CA); Christenson, Todd R. (Albuquerque, NM)

2003-01-01

14

Wafer-scale nanowell array patterning based electrochemical impedimetric immunosensor.  

PubMed

We have reported that nanowell array (NWA) can enhance electrochemical detection of molecular binding events by controlling the binding sites of the captured molecules. Using NWA biosensor based amperometric analysis, we have detected biological macromolecules such as DNA, protein or aptamers at low concentrations. In this research, we developed an impedimetric immunosensor based on wafer-scale NWA for electrochemical detection of stress-induced-phosphoprotein-1 (STIP-1). In order to develop NWA sensor through the cost-effective combination of high-throughput nanopattern, the NWA electrode was fabricated on Si wafer by krypton-fluoride (KrF) stepper semiconductor process. Finally, 12,500,000 ea nanowell with a 500 nm diameter was fabricated on 4 mm × 2 mm substrate. Next, by using these electrodes, we measured impedance to quantify antigen binding to the immunoaffinity layer. The limit of detection (LOD) of the NWA was improved about 100-fold compared to milli-sized electrodes (4 mm × 2 mm) without an NWA. These results suggest that wafer-scale NWA immunosensor will be useful for biosensing applications because their interface response is appropriate for detecting molecular binding events. PMID:24013070

Lee, JuKyung; Cho, SiHyeong; Lee, JungHwan; Ryu, HeonYul; Park, JinGoo; Lim, SunHee; Oh, ByungDo; Lee, ChangWoo; Huang, Wilber; Busnaina, Ahmed; Lee, HeaYeon

2013-12-01

15

Fabrication of phone-camera module using wafer-scale UV embossing process  

Microsoft Academic Search

We have developed a compact and cost-effective camera module on the basis of wafer-scale-replica processing. A multiple-layered structure of several aspheric lenses in a mobile-phone camera module is first assembled by bonding multiple glass-wafers on which 2-dimensional replica arrays of identical aspheric lenses are UV-embossed, followed by dicing the stacked wafers and packaging them with image sensor chips. This wafer-scale

Dong-Ik Shin; Sung-Kwa Kim; Ho-Seop Jeong; SeokCheon Lee; YoungSu Jin; JungEun Noh; HyeRan Oh; KiUn Lee; Dong Ho Shin; Seok Ho Song

2006-01-01

16

Fabrication and characterization of a novel wafer-level chip scale package for MEMS devices  

Microsoft Academic Search

This paper reports a hermetic MEMS package structure with silicon wafer as bonded cap at wafer-level scale. CMP followed by spraying chemical smoothing process is utilized to thin the N(100) silicon cap wafer to the thickness of 150 mum after wafer-level Cu\\/Sn isothermal solidification bonding. Method for the thinning process and parameters for Cu\\/Sn isothermal solidification bonding process are researched

Yuhan Cao; Le Luo

2009-01-01

17

Wafer-scale fabrication of nanoapertures using corner lithography.  

PubMed

Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated--based on a theoretical foundation including a statistical analysis--with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures. PMID:23792365

Burouni, Narges; Berenschot, Erwin; Elwenspoek, Miko; Sarajlic, Edin; Leussink, Pele; Jansen, Henri; Tas, Niels

2013-07-19

18

Investigations of Wafer Scale Etching with Xenon Difluoride  

Microsoft Academic Search

A good and uniform bulk silicon wafer etching method can be applied to the wafer thinning process in MEMS and 3D applications. In this study, the use of a Xenon Difluoride (XeF2) gas-phase etching system, operating at room temperature, has been investigated for bulk silicon wafer thinning. We investigated the Si-wafer surface morphology and profile following each XeF2 etching process

K. N. Chen; N. Hoivik; C. Y. Lin; A. Young; M. Ieong; G. Shahidi

2006-01-01

19

Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays  

NASA Technical Reports Server (NTRS)

The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

2009-01-01

20

Laser removal of Aluminum links for applications in wafer scale integrated circuits  

E-print Network

of testing increases in geometric progression. [I j . Journal model is IEEZ Transactions ss I lcctron JJesices. A. WAFER SCALE INTEGRATION CONCEPTS Wafer scale integration (WSI) is sn alternative approach to creating very com- plex systems incorporating... algorithms, a linear array of working circuits was created. The decision on which chips should be connected in to the array is postponed until sll wafer processing was complete. This could be accomplished by 100 % yield (not attainable) or through a fault...

Parikh, Harshavadan B.

1987-01-01

21

Investigations of Wafer Scale Etching with Xenon Difluoride  

NASA Astrophysics Data System (ADS)

A good and uniform bulk silicon wafer etching method can be applied to the wafer thinning process in MEMS and 3D applications. In this study, the use of a Xenon Difluoride (XeF2) gas-phase etching system, operating at room temperature, has been investigated for bulk silicon wafer thinning. We investigated the Si-wafer surface morphology and profile following each XeF2 etching process cycle. Theoretical results are used to compare with the experimental results as well. A clean wafer surface by proper surface treatments is significant to achieve a uniform surface profile and morphology for XeF2 etching. A proper design of etching cycle with nitrogen ambient during etching is necessary to achieve the fastest and uniform silicon etching rate. The silicon etching rate is reported as a function of etching pressure, nitrogen pressure, and etching duration.

Chen, K. N.; Hoivik, N.; Lin, C. Y.; Young, A.; Ieong, M.; Shahidi, G.

2006-03-01

22

Pressure Waves Induced by Megasonic Agitation in a LIGA Development Tank  

SciTech Connect

Megasonic agitation is used to improve the uniformity of the LIGA{sup 1} development process. To investigate the acoustic wave fields induced by megasonic agitation, we compute wave fields for a development tank containing a submerged wafer and for a typical trench-like feature on the wafer face. This separate treatment of these two problems is advantageous, because the length scales of the tank and the feature differ by three to four orders of magnitude. A spectral method based on Green's functions is used to construct the acoustic wave field, avoiding the alternative of solving partial differential equations over the entire domain. The total acoustic wave field is obtained by superposing of the primary wave field and the first reflected wave field, which are computed in sequence without any need for iterations. The wafer interference to the wave field is treated directly by a priori recognition of shadow regions in the primary field and a concept of boundary of dependence in the reflected field. Unlike a divergent wave field produced by ultrasonic agitation, results show that the wave field in the tank becomes narrowly focused at megasonic frequencies such that the most effective agitation is confined in a region directly above the acoustic source; this numerical expectation has been verified analytically and further confirmed experimentally by Sandia's LIGA Group.{sup [13]} The amplitude of the focused wave pressure is proportional to square root of the wave frequency. The wave pattern in a feature cavity also depends strongly on the orientation of the wafer and the aspect ratio of the cavity. It is concluded that the LIGA development process will be greatly accelerated, if the orientation and the location of the immersed wafer is arranged so that the wafer spends more time in the focused wave field of high frequency agitation.

Aili Ting

2002-08-01

23

Sub100 micron pitch stencil printing for wafer scale bumping  

Microsoft Academic Search

This paper presents recent work on solder paste printing for wafer-level bumping at sub 100mum pitch using Pb-free solder paste with IPC type-6 (15-5mum) particle size distributions. Consistent sized paste deposits have been produced onto wafers at such a pitch using stencil printing. Furthermore, a stencil printing evaluation has determined the impact that the print parameters have on the reproducibility

M. P. Y. Desmulliez; R. W. Kay; E. Abraham; E. de Gourcuff; G. J. Jackson; H. A. H. Steen; C. Liu; P. P. Conway

2005-01-01

24

Fabrication of phone-camera module using wafer-scale UV embossing process  

NASA Astrophysics Data System (ADS)

We have developed a compact and cost-effective camera module on the basis of wafer-scale-replica processing. A multiple-layered structure of several aspheric lenses in a mobile-phone camera module is first assembled by bonding multiple glass-wafers on which 2-dimensional replica arrays of identical aspheric lenses are UV-embossed, followed by dicing the stacked wafers and packaging them with image sensor chips. This wafer-scale processing leads to at least 95% yield in mass-production, and potentially to a very slim phone with camera-module less than 2 mm in thickness. We have demonstrated a VGA camera module fabricated by the wafer-scale-replica processing with various UV-curable polymers having refractive indices between 1.4 and 1.6, and with three different glass-wafers of which both surfaces are embossed as aspheric lenses having 230 ?m sag-height and aspheric-coefficients of lens polynomials up to tenth-order. We have found that precise compensation in material shrinkage of the polymer materials is one of the most technical challenges, in order to achieve a higher resolution in wafer-scaled lenses for mobile-phone camera modules.

Shin, Dong-Ik; Kim, Sung-Kwa; Jeong, Ho-Seop; Lee, Seok Cheon; Jin, YoungSu; Noh, JungEun; Oh, HyeRan; Lee, KiUn; Shin, Dong Ho; Song, Seok Ho

2006-02-01

25

Wafer-scale fabrication of plasmonic crystals from patterned silicon templates prepared by nanosphere lithography.  

PubMed

By combining nanosphere lithography with template stripping, silicon wafers were patterned with hexagonal arrays of nanowells or pillars. These silicon masters were then replicated in gold by metal evaporation, resulting in wafer-scale hexagonal gratings for plasmonic applications. In the nanosphere lithography step, two-dimensional colloidal crystals of 510 nm diameter polystyrene spheres were assembled at the air-water interface and transferred to silicon wafers. The spheres were etched in oxygen plasma in order to define their size for masking of the silicon wafer. For fabrication of metallic nanopillar arrays, an alumina film was grown over the nanosphere layer and the spheres were then removed by bath sonication. The well pattern was defined in the silicon wafer by reactive ion etching in a chlorine plasma. For fabrication of metal nanowell arrays, the nanosphere monolayer was used directly as a mask and exposed areas of the silicon wafer were plasma-etched anisotropically in SF6/Ar. Both techniques could be used to produce subwavelength metal replica structures with controlled pillar or well diameter, depth, and profile, on the wafer scale, without the use of direct writing techniques to fabricate masks or masters. PMID:23614608

Hall, Anthony Shoji; Friesen, Stuart A; Mallouk, Thomas E

2013-06-12

26

100GHz Transistors from Wafer-Scale Epitaxial Graphene  

Microsoft Academic Search

The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon

Y.-M. Lin; C. Dimitrakopoulos; K. A. Jenkins; D. B. Farmer; H.-Y. Chiu; A. Grill; Ph. Avouris

2010-01-01

27

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging  

NASA Astrophysics Data System (ADS)

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

2014-07-01

28

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.  

PubMed

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-01

29

Toward wafer-scale patterning of freestanding intermetallic nanowires.  

PubMed

Individual metal alloy nanowires of constant diameter and high aspect ratio have previously been self-assembled at selected locations on atomic force microscope (AFM) probes by the method reported in Yazdanpanah et al (2005 J. Appl. Phys. 98 073510). This process relies on the room temperature crystallization of an ordered phase of silver-gallium. A parallel version of this method has been implemented in which a substrate, either an array of micromachined tips (similar to tips on AFM probes) or a lithographically patterned planar substrate, is brought into contact with a continuous, nearly planar film of melted gallium. In several runs, freestanding wires are fabricated with diameters of 40-400 nm, lengths of 4-80 µm, growth rates of 80-170 nm s( - 1) and, most significantly, with yields of up to 97% in an array of 422 growth sites. These results demonstrate the feasibility of developing a batch manufacturing process for the decoration of wafers of AFM tips and other structures with selectively patterned freestanding nanowires. PMID:21673382

Jalilian, Romaneh; Rivera, Jose; Askari, Davood; Arva, Sreenath; Rathfon, Jeremy M; Cohn, Robert W; Yazdanpanah, Mehdi M

2011-07-22

30

Wafer-scale metasurface for total power absorption, local field enhancement and single  

E-print Network

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule. Effective electric and magnetic currents supported by SIOM metasurface We perform electromagnetic simulations of a 1 m Ã? 1 m area that models the SEM image of the SIOM metasurface shown as Figure S1a

31

On the chemo-mechanical polishing for nano-scale surface finish of brittle wafers.  

PubMed

Chemo-mechanical polishing (CMP) has been a common method to produce nano-scale surface finish of brittle wafers. This paper provides a relatively comprehensive review on the CMP of silicon, silicon carbide and sapphire including both patents and papers. The discussion includes the limitations and further research directions of the CMP technology, the material removal mechanisms, and the control and optimization of the CMP for brittle wafers. The paper concluded that the usage of mix- or coated- abrasives may improve the CMP in terms of less subsurface damage and higher material removal rate. PMID:20415661

Wang, Y G; Zhang, L C

2010-06-01

32

Sacrificial layer for the fabrication of electroformed cantilevered LIGA microparts  

NASA Astrophysics Data System (ADS)

The use of silver filled PMMA as a sacrificial layer for the fabrication of multilevel LIGA microparts is presented. In this technique, a bottom level of standard electroformed LIGA parts is first produced on a metallized substrate such as a silicon wafer. A methyl methacrylate formulation mixed with silver particles is then cast and polymerized around the bottom level of metal parts to produce a conducting sacrificial layer. A second level of PMMA x-ray resist is adhered to the bottom level of metal parts and conducting PMMA and patterned to form another level of electroformed features. This presentation will discuss some the requirements for the successful fabrication of multilevel, cantilevered LIGA microparts. It will be shown that by using a silver filled PMMA, a sacrificial layer can be quickly applied around LIGA components; cantilevered microparts can be electroformed; and the final parts can be quickly released by dissolving the sacrificial layer in acetone.

Morales, Alfredo M.; Aigeldinger, Georg; Bankert, Michelle A.; Domeier, Linda A.; Hachman, John T.; Hauck, Cheryl; Keifer, Patrick N.; Krafcik, Karen L.; McLean, Dorrance E.; Yang, Peter C.

2003-01-01

33

Control of wafer-scale non-uniformity in chemical-mechanical planarization by face-up polishing  

E-print Network

Chemical-mechanical planarization (CMP) is a key process in the manufacture of ultra-large-scale-integrated (ULSI) semiconductor devices. A major concern in CMP is non-uniform planarization, or polishing, at the wafer-scale ...

Mau, Catherine (Catherine K.)

2008-01-01

34

Wafer Scale Homogeneous Bilayer Graphene Films by Chemical Vapor Deposition  

E-print Network

we report homogeneous bilayer graphene films over at least a 2 in. Ã? 2 in. area, synthesized of large scale single-layer graphene on metal substrate.20-24 However, the synthesis of uniform bilayer graphene film over at least 2 in. Ã? 2 in. area, limited only by our synthesis apparatus. Our method

Zhong, Zhaohui

35

ISOTROPIC ETCHING OF 111 SCS FOR WAFER-SCALE MANUFACTURING OF PERFECTLY HEMISPHERICAL SILICON MOLDS  

E-print Network

are XeF2 and HF-Nitric acid etching. XeF2 is a gas phase etch, in which the XeF2 sublimates at room temperature to etch silicon according to the equation: 4 2 2 2 SiFXeSiXeF ++ (4) Surface roughness and higherISOTROPIC ETCHING OF 111 SCS FOR WAFER-SCALE MANUFACTURING OF PERFECTLY HEMISPHERICAL SILICON MOLDS

Afshari, Ehsan

36

On-Chip High Variable Inductor Using Wafer-Level Chip-Scale Package Technology  

Microsoft Academic Search

In this paper, the authors propose an on-chip high-Q variable inductor embedded in wafer-level chip-scale package (WL-CSP). The variable inductor has a metal plate and a spiral inductor fabricated by the WL-CSP technology. The metal plate can be moved by a microelectromechanical systems (MEMS) actuator, and the inductance is varied according to the position of the metal plate. At the

Kenichi Okada; Hirotaka Sugawara; Hiroyuki Ito; Kazuhisa Itoi; Masakazu Sato; Hiroshi Abe; Tatsuya Ito; Kazuya Masu

2006-01-01

37

LIGA Micromachining: Infrastructure Establishment  

SciTech Connect

LIGA is a micromachining technology that uses high energy x-rays from a synchrotron to create patterns with small lateral dimensions in a deep, non-conducting polymeric resist. Typical dimensions for LIGA parts are microns to tens of microns in lateral size, and hundreds of microns to millimeters in depth. Once the resist is patterned, metal is electrodeposited in the features to create metal microparts, or to create a metal mold for subsequent replication. The acronym LIGA comes from the German words for lithography, electroforming, and molding, and the technology has been under worldwide development for more than a decade. over the last five years, a full-service capability to produce metal microparts using the LIGA process has been established at Sandia national Laboratories, California. This report describes the accomplishments made during the past two years in infrastructure establishment funded by a Laboratory Directed Research and Development (LDRD) project entitled ''LIGA Micromachining.'' Specific topics include photoresist processing for LIGA mask making, x-ray scanning equipment, plating bath instrumentation, plating uniformity, and software architecture.

Alfredo M. Morales; Barry V. Hess; Dale R. Boehme; Jill M. Hruby; John S. Krafcik; Robert H. Nilson; Stewart K. Griffiths; William D. Bonivert

1999-02-01

38

Wafer-scale transfer of vertically aligned carbon nanotube arrays.  

PubMed

The first critical step in making vertically aligned carbon nanotube (VACNT)-based thermal interface materials is to transfer the VACNTs on a large scale. Although VACNTs have been transferred by several methods, they were only transferred inadvertently in most cases. Here we report well-controlled weak-oxidation-assisted transfer of VACNTs. Specifically, after a short time of weak oxidation, we found that VACNTs could be easily detached from the native growth substrates, and thus, a freestanding VACNT film was obtained. Then the VACNTs could be assembled onto specific substrates for its real applications. More importantly, the repeated growth-transfer synthesis of VACNT arrays can be realized in one batch by introducing an additional process of weak oxidation in chemical vapor deposition, which makes the strategy more effective. Surprisingly, no degradation in the quality was observed before and after the weak oxidation according to thermogravimetric analysis and Raman spectra of VACNTs. Enhanced thermal and mechanical properties were achieved after reactive ion etching (RIE) and subsequent metallization of the surfaces of the VACNTs, and this might be due to the removal of impurities such as amorphous carbon and entangled CNTs by RIE. These findings provide an efficient approach for transferring VACNTs, which is important for the application of VACNTs in thermal management. PMID:25490088

Wang, Miao; Li, Taotao; Yao, Yagang; Lu, Huifen; Li, Qiang; Chen, Minghai; Li, Qingwen

2014-12-31

39

Wafer scale interdigitated nanoelectrode devices functionalized using a MEMS-based deposition system.  

PubMed

This paper reports on a methodology to elaborate interdigitated nanoelectrode devices (INDs) at the wafer scale, relying on a mix-and-match process which combines proximity optical lithography and electron beam lithography. An optimum exposure dose allowed fabricating nanodevices, at the wafer level, with a successful yield of 97%. The final devices are bonded onto conventional TO-8 packages. Electrical characterization in a short-circuited nanoelectrode is performed, revealing a 230 µ? cm resistivity value at 23?°C. A MEMS-based spotter made of cantilevers (called Bioplume) has been used to obtain precise functionalization of the INDs with sub-picoliter volume solutions. These INDs are the basis of multiple tunnel junction nanodevices, intended to serve as novel highly sensitive nanobiosensors. PMID:22361922

Martinez-Rivas, A; Carcenac, F; Saya, D; Séverac, C; Nicu, L; Vieu, C

2012-03-16

40

Microfluidic design and fabrication of wafer-scale varifocal liquid lens  

NASA Astrophysics Data System (ADS)

Microfluidic design and fabrication was developed for wafer-scale varifocal liquid lens which is slim less than 0.9mm. The liquid-filled varifocal lens has advanced functions such as auto macro and focusing to obtain a high quality of image. This varifocal lens is similar to human eye and it consists of main Si frame which has penetrated inner hole, upside-bonded PDMS (polydimethylsiloxane) elastomer membrane, downside-bonded glass plate and optical fluid confined by these structures. Si frame, which has a circular hole for tunable lens chamber, several holes for actuator chamber and micro-fluidic channels between chambers, is fabricated using thin Si wafer and microelectromechanical system (MEMS) processes. When optical fluid is filled the internal cavity by conventional injection, void trapping which degrades optical performance or filling impossibility happens because of high aspect ratio between lens diameter and thickness for slim liquid lens. To prevent these problems, we developed wafer-based microfabrications of seal line dispensing, accurate dropping of optical fluid, pressing & bonding process in vacuum and UV sealant curing. Afterward, electro-active polymer actuators, which push the optical fluid to change the lens shape, was attached on the PDMS membrane of liquid lens wafer and sawing process of 9.4mm*9.0mm chip size followed. Finally, the varifocal liquid lens which is slim less than 0.6mm thickness (0.9mm included actuators), tunable more than 20diopter changes of refractive power, guaranteed reliability of 300,000 repetitions and suitable for mass production, was realized.

Lee, Jeong-Yub; Choi, Seung-Tae; Lee, Seung-Wan; Kim, Woonbae

2009-08-01

41

A Wafer-Scale Etching Technique for High Aspect Ratio Implantable MEMS Structures  

PubMed Central

Microsystem technology is well suited to batch fabricate microelectrode arrays, such as the Utah electrode array (UEA), intended for recording and stimulating neural tissue. Fabrication of the UEA is primarily based on the use of dicing and wet etching to achieve high aspect ratio (15:1) penetrating electrodes. An important step in the array fabrication is the etching of electrodes to produce needle-shape electrodes with sharp tips. Traditional etching processes are performed on a single array, and the etching conditions are not optimized. As a result, the process leads to variable geometries of electrodes within an array. Furthermore, the process is not only time consuming but also labor-intensive. This report presents a wafer-scale etching method for the UEA. The method offers several advantages, such as substantial reduction in the processing time, higher throughput and lower cost. More importantly, the method increases the geometrical uniformity from electrode to electrode within an array (1.5 ± 0.5 % non-uniformity), and from array to array within a wafer (2 ± 0.3 % non-uniformity). Also, the etching rate of silicon columns, produced by dicing, are studied as a function of temperature, etching time and stirring rate in a nitric acid rich HF-HNO3 solution. These parameters were found to be related to the etching rates over the ranges studied and more-importantly affect the uniformity of the etched silicon columns. An optimum etching condition was established to achieve uniform shape electrode arrays on wafer-scale. PMID:20706618

Bhandari, R; Negi, S; Rieth, L.; Solzbacher, F

2010-01-01

42

Comprehensive investigation of sequential plasma activated Si/Si bonded interfaces for nano-integration on the wafer scale.  

PubMed

The sequentially plasma activated bonding of silicon wafers has been investigated to facilitate the development of chemical free, room temperature and spontaneous bonding required for nanostructure integration on the wafer scale. The contact angle of the surface and the electrical and nanostructural behavior of the interface have been studied. The contact angle measurements show that the sequentially plasma (reactive ion etching plasma followed by microwave radicals) treated surfaces offer highly reactive and hydrophilic surfaces. These highly reactive surfaces allow spontaneous integration at the nanometer scale without any chemicals, external pressure or heating. Electrical characteristics show that the current transportation across the nanobonded interface is dependent on the plasma parameters. High resolution transmission electron microscopy results confirm nanometer scale bonding which is needed for the integration of nanostructures. The findings can be applied in spontaneous integration of nanostructures such as nanowires/nanotubes/quantum dots on the wafer scale. PMID:20208123

Kibria, M G; Zhang, F; Lee, T H; Kim, M J; Howlader, M M R

2010-04-01

43

Comprehensive investigation of sequential plasma activated Si/Si bonded interfaces for nano-integration on the wafer scale  

NASA Astrophysics Data System (ADS)

The sequentially plasma activated bonding of silicon wafers has been investigated to facilitate the development of chemical free, room temperature and spontaneous bonding required for nanostructure integration on the wafer scale. The contact angle of the surface and the electrical and nanostructural behavior of the interface have been studied. The contact angle measurements show that the sequentially plasma (reactive ion etching plasma followed by microwave radicals) treated surfaces offer highly reactive and hydrophilic surfaces. These highly reactive surfaces allow spontaneous integration at the nanometer scale without any chemicals, external pressure or heating. Electrical characteristics show that the current transportation across the nanobonded interface is dependent on the plasma parameters. High resolution transmission electron microscopy results confirm nanometer scale bonding which is needed for the integration of nanostructures. The findings can be applied in spontaneous integration of nanostructures such as nanowires/nanotubes/quantum dots on the wafer scale.

Kibria, M. G.; Zhang, F.; Lee, T. H.; Kim, M. J.; Howlader, M. M. R.

2010-04-01

44

Wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible biomedical platform.  

PubMed

We present wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible parylene platform, as progress toward sustainably powering biomedical microsystems suitable for implantable and wearable applications. All-solid-state, low-profile (<30 ?m), and high-density (up to ~500 ?F/mm(2)) micro-supercapacitors are formed on an ultrathin (~20 ?m) freestanding parylene film by a wafer-scale parylene packaging process in combination with a polyaniline (PANI) nanowire growth technique assisted by surface plasma treatment. These micro-supercapacitors are highly flexible and shown to be resilient toward flexural stress. Further, direct integration of micro-supercapacitors into a radio frequency (RF) rectifying circuit is achieved on a single parylene platform, yielding a complete RF energy harvesting microsystem. The system discharging rate is shown to improve by ~17 times in the presence of the integrated micro-supercapacitors. This result suggests that the integrated micro-supercapacitor technology described herein is a promising strategy for sustainably powering biomedical microsystems dedicated to implantable and wearable applications. PMID:25653069

Maeng, Jimin; Meng, Chuizhou; Irazoqui, Pedro P

2015-02-01

45

Face-to-face transfer of wafer-scale graphene films.  

PubMed

Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene. PMID:24336218

Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H; Loh, Kian Ping

2014-01-01

46

Wafer scale imprint uniformity evaluated by LSPR spectroscopy: a high volume characterization method for nanometer scale structures.  

PubMed

We exploit the localized surface-plasmon resonance (LSPR) of terahertz gold gammadion structures for wafer scale critical dimension metrology of nanostructures. The proposed characterization method, LSPR spectroscopy, is based on optical transmission measurements and is benchmarked against numerical simulations of imprinted structures characterized by atomic force microscopy. There is a fair agreement between the two methods and the simulations enable the translation of optical spectra to critical dimensions of the physical structures, a concept known from scatterometry. The results demonstrate the potential of LSPR spectroscopy as an alternative characterization method to scanning electron microscopy, atomic force microscopy and scatterometry. PMID:22948403

Jeppesen, Claus; Lindstedt, Daniel Nilsson; Vig, Asger Laurberg; Kristensen, Anders; Mortensen, N Asger

2012-09-28

47

Wafer-scale design of lightweight and transparent electronics that wraps around hairs  

NASA Astrophysics Data System (ADS)

Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-?m thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12?V and above 1?MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

Salvatore, Giovanni A.; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

2014-01-01

48

Wafer-scale, three-dimensional helical porous thin films deposited at a glancing angle  

NASA Astrophysics Data System (ADS)

Minimization of helices opens a door to impose novel functions derived from the dimensional shrinkage of optical, mechanical and electronic devices. Glancing angle deposition (GLAD) enables one to deposit three-dimensional helical porous thin films (HPTFs) composed of separated spiral micro/nano-columns. GLAD integrates a series of advantageous features, including one-step deposition, wafer-scale production with mono-handedness of spirals, flexible engineering of spiral materials and dimensions, and the adaption to various kinds of substrates. Herein, we briefly review the fabrication of HPTFs by GLAD, specific growth mechanisms, physical properties in structures, mechanics and chiral optics, and the emerging applications in green energy. A prospective outlook is presented to illuminate some promising developments in enantioselection, bio-dynamic analyses, wirelessly-controlled drug delivery and mass production.

Huang, Zhifeng; Bai, Fan

2014-07-01

49

Wafer-scale MoS2 thin layers prepared by MoO3 sulfurization  

NASA Astrophysics Data System (ADS)

Atomically thin molybdenum disulfide (MoS2) layers have attracted great interest due to their direct-gap property and potential applications in optoelectronics and energy harvesting. Meanwhile, they are extremely bendable, promising for applications in flexible electronics. However, the synthetic approach to obtain large-area MoS2 atomic thin layers is still lacking. Here we report that wafer-scale MoS2 thin layers can be obtained using MoO3 thin films as a starting material followed by a two-step thermal process, reduction of MoO3 at 500 °C in hydrogen and sulfurization at 1000 °C in the presence of sulfur. Spectroscopic, optical and electrical characterizations reveal that these films are polycrystalline and with semiconductor properties. The obtained MoS2 films are uniform in thickness and easily transferable to arbitrary substrates, which make such films suitable for flexible electronics or optoelectronics.Atomically thin molybdenum disulfide (MoS2) layers have attracted great interest due to their direct-gap property and potential applications in optoelectronics and energy harvesting. Meanwhile, they are extremely bendable, promising for applications in flexible electronics. However, the synthetic approach to obtain large-area MoS2 atomic thin layers is still lacking. Here we report that wafer-scale MoS2 thin layers can be obtained using MoO3 thin films as a starting material followed by a two-step thermal process, reduction of MoO3 at 500 °C in hydrogen and sulfurization at 1000 °C in the presence of sulfur. Spectroscopic, optical and electrical characterizations reveal that these films are polycrystalline and with semiconductor properties. The obtained MoS2 films are uniform in thickness and easily transferable to arbitrary substrates, which make such films suitable for flexible electronics or optoelectronics. Electronic supplementary information (ESI) available. See DOI: 10.1039/c2nr31833d

Lin, Yu-Chuan; Zhang, Wenjing; Huang, Jing-Kai; Liu, Keng-Ku; Lee, Yi-Hsien; Liang, Chi-Te; Chu, Chih-Wei; Li, Lain-Jong

2012-09-01

50

Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits  

E-print Network

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on ...

Shaver, David C.

51

Toward the synthesis of wafer-scale single-crystal graphene on copper foils.  

PubMed

In this research, we constructed a controlled chamber pressure CVD (CP-CVD) system to manipulate graphene's domain sizes and shapes. Using this system, we synthesized large (~4.5 mm(2)) single-crystal hexagonal monolayer graphene domains on commercial polycrystalline Cu foils (99.8% purity), indicating its potential feasibility on a large scale at low cost. The as-synthesized graphene had a mobility of positive charge carriers of ~11,000 cm(2) V(-1) s(-1) on a SiO(2)/Si substrate at room temperature, suggesting its comparable quality to that of exfoliated graphene. The growth mechanism of Cu-based graphene was explored by studying the influence of varied growth parameters on graphene domain sizes. Cu pretreatments, electrochemical polishing, and high-pressure annealing are shown to be critical for suppressing graphene nucleation site density. A pressure of 108 Torr was the optimal chamber pressure for the synthesis of large single-crystal monolayer graphene. The synthesis of one graphene seed was achieved on centimeter-sized Cu foils by optimizing the flow rate ratio of H(2)/CH(4). This work should provide clear guidelines for the large-scale synthesis of wafer-scale single-crystal graphene, which is essential for the optimized graphene device fabrication. PMID:22966902

Yan, Zheng; Lin, Jian; Peng, Zhiwei; Sun, Zhengzong; Zhu, Yu; Li, Lei; Xiang, Changsheng; Samuel, E Loïc; Kittrell, Carter; Tour, James M

2012-10-23

52

Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale  

PubMed Central

We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13?×?107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production. PMID:24289275

2013-01-01

53

Wafer-scale arrays of nonvolatile polymer memories with microprinted semiconducting small molecule/polymer blends.  

PubMed

Nonvolatile ferroelectric-gate field-effect transistors (Fe-FETs) memories with solution-processed ferroelectric polymers are of great interest because of their potential for use in low-cost flexible devices. In particular, the development of a process for patterning high-performance semiconducting channel layers with mechanical flexibility is essential not only for proper cell-to-cell isolation but also for arrays of flexible nonvolatile memories. We demonstrate a robust route for printing large-scale micropatterns of solution-processed semiconducting small molecules/insulating polymer blends for high performance arrays of nonvolatile ferroelectric polymer memory. The nonvolatile memory devices are based on top-gate/bottom-contact Fe-FET with ferroelectric polymer insulator and micropatterned semiconducting blend channels. Printed micropatterns of a thin blended semiconducting film were achieved by our selective contact evaporation printing, with which semiconducting small molecules in contact with a micropatterned elastomeric poly(dimethylsiloxane) (PDMS) mold were preferentially evaporated and absorbed into the PDMS mold while insulating polymer remained intact. Well-defined micrometer-scale patterns with various shapes and dimensions were readily developed over a very large area on a 4 in. wafer, allowing for fabrication of large-scale printed arrays of Fe-FETs with highly uniform device performance. We statistically analyzed the memory properties of Fe-FETs, including ON/OFF ratio, operation voltage, retention, and endurance, as a function of the micropattern dimensions of the semiconducting films. Furthermore, roll-up memory arrays were produced by successfully detaching large-area Fe-FETs printed on a flexible substrate with a transient adhesive layer from a hard substrate and subsequently transferring them to a nonplanar surface. PMID:24070419

Bae, Insung; Hwang, Sun Kak; Kim, Richard Hahnkee; Kang, Seok Ju; Park, Cheolmin

2013-11-13

54

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy  

PubMed Central

The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (“metasurfaces”) can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

2013-01-01

55

High throughput ultralong (20 cm) nanowire fabrication using a wafer-scale nanograting template.  

PubMed

Nanowires are being actively explored as promising nanostructured materials for high performance flexible electronics, biochemical sensors, photonic applications, solar cells, and secondary batteries. In particular, ultralong (centimeter-long) nanowires are highly attractive from the perspective of electronic performance, device throughput (or productivity), and the possibility of novel applications. However, most previous works on ultralong nanowires have issues related to limited length, productivity, difficult alignment, and deploying onto the planar substrate complying with well-matured device fabrication technologies. Here, we demonstrate a highly ordered ultralong (up to 20 cm) nanowire array, with a diameter of 50 nm (aspect ratio of up to 4,000,000:1), in an unprecedented large (8 in.) scale (2,000,000 strands on a wafer). We first devised a perfectly connected ultralong nanograting master template on the whole area of an 8 in. substrate using a top-down approach, with a density equivalent to that achieved with e-beam lithography (100 nm). Using this large-area, ultralong, high-density nanograting template, we developed a fast and effective method for fabricating up to 20 cm long nanowire arrays on a plastic substrate, composed of metal, dielectric, oxide, and ferroelectric materials. As a suggestion of practical application, a prototype of a large-area aluminum wire grid polarizer was demonstrated. PMID:23899099

Yeon, Jeongho; Lee, Young Jae; Yoo, Dong Eun; Yoo, Kyoung Jong; Kim, Jin Su; Lee, Jun; Lee, Jeong Oen; Choi, Seon-Jin; Yoon, Gun-Wook; Lee, Dong Wook; Lee, Gi Seong; Hwang, Hae Chul; Yoon, Jun-Bo

2013-09-11

56

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy.  

PubMed

The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures ("metasurfaces") can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

Wang, Dongxing; Zhu, Wenqi; Best, Michael D; Camden, Jon P; Crozier, Kenneth B

2013-01-01

57

A wafer-scale backplane-assisted resonating nanoantenna array SERS device created by tunable thermal dewetting nanofabrication  

NASA Astrophysics Data System (ADS)

A tunable lithography-less nanofabrication process using a metal thin-film thermal dewetting technique has been developed to fabricate wafer-scale and uniform plasmonic substrates at low cost for optimal performance in surface enhanced Raman scattering (SERS) applications. The relationship between the tunable parameters of this process and the corresponding optical and plasmonic characteristic is investigated both experimentally and theoretically to understand the deterministic design of an optimal SERS device with a three-dimensional plasmonic nanoantenna structure. The enhancement of SERS using various nanoplasmonic particle sizes, structure lengths, lateral hot spot spacings and resonating effects are examined and demonstrated. We achieve a uniform optimal enhancement factor of 1.38 × 108 on a 4 in wafer-scale SERS substrate with a backplane-assisted resonating nanoantenna array design. Sensitive environmental nitrate sensing, vitamin detection and oligonucleotide identification are demonstrated on the high-performance SERS device.

Chang, Te-Wei; Ranjan Gartia, Manas; Seo, Sujin; Hsiao, Austin; Logan Liu, Gang

2014-04-01

58

A wafer-scale backplane-assisted resonating nanoantenna array SERS device created by tunable thermal dewetting nanofabrication.  

PubMed

A tunable lithography-less nanofabrication process using a metal thin-film thermal dewetting technique has been developed to fabricate wafer-scale and uniform plasmonic substrates at low cost for optimal performance in surface enhanced Raman scattering (SERS) applications. The relationship between the tunable parameters of this process and the corresponding optical and plasmonic characteristic is investigated both experimentally and theoretically to understand the deterministic design of an optimal SERS device with a three-dimensional plasmonic nanoantenna structure. The enhancement of SERS using various nanoplasmonic particle sizes, structure lengths, lateral hot spot spacings and resonating effects are examined and demonstrated. We achieve a uniform optimal enhancement factor of 1.38 × 10(8) on a 4 in wafer-scale SERS substrate with a backplane-assisted resonating nanoantenna array design. Sensitive environmental nitrate sensing, vitamin detection and oligonucleotide identification are demonstrated on the high-performance SERS device. PMID:24633089

Chang, Te-Wei; Gartia, Manas Ranjan; Seo, Sujin; Hsiao, Austin; Liu, Gang Logan

2014-04-11

59

Crack-release transfer method of wafer-scale grown graphene onto large-area substrates.  

PubMed

We developed a crack-release graphene transfer technique for opening up possibilities for the fabrication of graphene-based devices. Graphene film grown on metal catalysts/SiO2/Si wafer should be scathelessly peeled for sequent transferring to a target substrate. However, when the graphene is grown on the metal catalyst on a silicon substrate, there is a large tensile stress resulting from the difference of the coefficient of thermal expansion in the catalyst and silicon. The conventional methods of detaching graphene from metal catalysts were found to induce considerable mechanical damage on graphene films during separation processes including metal wet etching. Here we report a new technique wherein bubbles generated by electrolysis reaction separate thin metal catalysts from the SiO2/Si wafer. The dry attachment of graphene to the target wafer was processed utilizing a wafer to wafer bonding technique in a vacuum. We measured the microscopic image, Raman spectra, and electrical properties of the transferred graphene. The optical and electrical properties of the graphene transferred by the bubbles/dry method are better than those of the graphene obtained by mechanical/wet transfer. PMID:24967530

Lee, Jooho; Kim, Yongsung; Shin, Hyeon-Jin; Lee, ChangSeung; Lee, Dongwook; Lee, Sunghee; Moon, Chang-Yul; Lee, Su Chan; Kim, Sun Jun; Ji, Jae Hoon; Yoon, Hyong Seo; Jun, Seong Chan

2014-08-13

60

Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors  

SciTech Connect

Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300?mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700?cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

Kim, SangHyeon, E-mail: dadembyora@mosfet.t.u-tokyo.ac.jp, E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); JST-CREST, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Yokoyama, Masafumi; Nakane, Ryosho [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Li, Jian; Kao, Yung-Chung [IntelliEPI, Inc., 1250 E. Collins Blvd., Richardson, Texas 75081 (United States)

2014-07-28

61

Wafer-scale near-perfect ordered porous alumina on substrates by step and flash imprint lithography.  

PubMed

Nanoporous anodic aluminum oxide (AAO) has been widely used for the development of various functional nanostructures. So far, highly ordered AAO on substrates could only be prepared using a nanoindentation method via hard stamping and lithographic techniques that are not scalable to a wafer-scale. Here we report on a step and flash imprint lithography (SFIL)-based method to fabricate a near-perfect ordered AAO with square and hexagonal lattice configuration on silicon substrate over 4 in. wafer areas. SFIL was used to prepattern a polymer mask layer, and wet-etching process was employed to transfer the nanopatterns to aluminum (Al) films, thus creating ordered nanoindentation on the Al surface. The ordered nanoindentation guides the growth of nanochannels in the anodization step to create the ordered nanoporous structures. The proposed wafer-scale process is compatible with standard semiconductor fabrication and offers substantial advantages over conventional Al patterning methods in terms of patterning areas, throughput, process simplicity, and process robustness, allowing up to 10 000 imprints or pattern transfer to the Al films. PMID:20411953

Kustandi, Tanu Suryadi; Loh, Wei Wei; Gao, Han; Low, Hong Yee

2010-05-25

62

Wafer scale fabrication of porous three-dimensional plasmonic metamaterials for the visible region: chiral and beyond.  

PubMed

We report on a wafer scale fabrication method of a three-dimensional plasmonic metamaterial with strong chiroptical response in the visible region of the electromagnetic spectrum. The system was comprised of metallic nanoparticles arranged in a helical fashion, with high degree of flexibility over the choice of the underlying material, as well as their geometrical parameters. This resulted in exquisite control over the chiroptical properties, most importantly the spectral signature of the circular dichroism. In spite of the large variability in the arrangement, as well as the size and shape of the constituent nanoparticles, the average chiro-optical response of the material remained uniform across the wafer, thus confirming the suitability of this system as a large area chiral metamaterial. By simply heating the substrate for a few minutes, the geometrical properties of the nanoparticles could be altered, thus providing an additional handle towards tailoring the spectral response of this novel material. PMID:23832295

Singh, Johnson Haobijam; Nair, Greshma; Ghosh, Arijit; Ghosh, Ambarish

2013-08-21

63

WaferScale Modeling of Pattern Effect in Oxide Chemical Mechanical Polishing  

E-print Network

arising from layout pattern dependency remains a major concern in oxide CMP. The severity of the pattern that the integrated wafer/die CMP model accurately predicts the resulting increase or decrease in die­level pattern, planarization length, chemical mechanical polishing, die­level variation, polishing pad, variation decomposition

Boning, Duane S.

64

Wafer-Scale Modeling of Pattern Effect in Oxide Chemical Mechanical Polishing  

E-print Network

dependency remains a major concern in oxide CMP. The severity of the pattern density effect is a function wafer/die CMP model accurately predicts the resulting increase or decrease in die-level pattern, planarization length, chemical mechanical polishing, die-level variation, polishing pad, variation decomposition

Boning, Duane S.

65

LIGA for Boomerang  

NASA Astrophysics Data System (ADS)

Boomerang is a 3GeV synchrotron radiation accelerator, currently being constructed in the State of Victoria, Australia. The outline design of two beamlines, suitable for the fabrication of MEMS devices using the LIGA process, is presented, along with an estimate of the exposure doses throughout the resist. The most commonly used resist is PMMA, which requires a minimum dose of about 4500 J/cm3 for accurate microstructure definition. Exposure with such a dose, in resist thicknesses of several hundred microns, can take hours. Fortunately, SU-8 resist is becoming more widely used as the minimum dosage required is about 35 J/cm3, leading to exposure times of only a few minutes. Although Boomerang will shorten exposure times due to its higher irradiance at the substrate, the full benefits may not be realizable due to excessive resist heating. Heating effects have been simulated and suggest that helium cooling will be essential if the glass transition temperature of the resist (100°C for PMMA, 50°C for SU-8) and thermal distortion of the mask are to be avoided. The parameters chosen in this study of the future performance of Boomerang have been inserted into a cost model. The model shows that Boomerang exposure can become competitive with other exposure methods, particularly where large quantities of devices with deep structures are required.

Lawes, Ronald A.; Arthur, Graham G.

2004-04-01

66

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays  

NASA Astrophysics Data System (ADS)

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 ?m is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 ?m × 25 ?m that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

2013-09-01

67

Wafer-scale fabrication of transistors using CVD-grown graphene and its application to inverter circuit  

NASA Astrophysics Data System (ADS)

Graphene transistors were fabricated by a wafer-scale “top-down” process using a graphene sheet formed by the chemical vapor deposition (CVD) method. The devices have a dual-gated structure with an ion-irradiated channel, in which transistor polarity can be electrostatically controlled. We demonstrated, at room temperature, an on/off operation of current and electrostatic control of transistor polarity. By combining two dual-gated transistors, a six-terminal device was fabricated with three top gates and two ion-irradiated channels. In this device, we demonstrated an inverter operation.

Nakaharai, Shu; Iijima, Tomohiko; Ogawa, Shinichi; Yagi, Katsunori; Harada, Naoki; Hayashi, Kenjiro; Kondo, Daiyu; Takahashi, Makoto; Li, Songlin; Tsukagoshi, Kazuhito; Sato, Shintaro; Yokoyama, Naoki

2015-04-01

68

Fabrication of a wafer-scale uniform array of single-crystal organic nanowire complementary inverters by nanotransfer printing  

NASA Astrophysics Data System (ADS)

We report the fabrication and electrical characterization of a wafer-scale array of organic complementary inverters using single-crystal 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-PEN) and fullerene (C60) nanowires as p- and n-channels, respectively. Two arrays of single-crystal organic nanowires were generated consecutively on desired locations of a common substrate with a desired mutual alignment by a direct printing method (liquid-bridge-mediated nanotransfer molding). Another direct printing of silver micron scale structures, as source and drain electrodes, on the substrate with the two printed nanowire arrays produced an array of complementary inverters with a bottom gate, top contact configuration. Field-effect mobilities of single-crystal TIPS-PEN and C60 nanowire field-effect transistors (FETs) in the arrays were uniform with 1.01 ± 0.14 and 0.10 ± 0.01 cm2V-1 s-1, respectively. A wafer-scale array of complementary inverters produced all by the direct printing method showed good performance with an average gain of 25 and with low variations among the inverters.

Park, Kyung Sun; Baek, Jangmi; Koo Lee, Yong-Eun; Sung, Myung Mo

2015-02-01

69

Wafer scale fabrication of porous three-dimensional plasmonic metamaterials for the visible region: chiral and beyond  

NASA Astrophysics Data System (ADS)

We report on a wafer scale fabrication method of a three-dimensional plasmonic metamaterial with strong chiroptical response in the visible region of the electromagnetic spectrum. The system was comprised of metallic nanoparticles arranged in a helical fashion, with high degree of flexibility over the choice of the underlying material, as well as their geometrical parameters. This resulted in exquisite control over the chiroptical properties, most importantly the spectral signature of the circular dichroism. In spite of the large variability in the arrangement, as well as the size and shape of the constituent nanoparticles, the average chiro-optical response of the material remained uniform across the wafer, thus confirming the suitability of this system as a large area chiral metamaterial. By simply heating the substrate for a few minutes, the geometrical properties of the nanoparticles could be altered, thus providing an additional handle towards tailoring the spectral response of this novel material.We report on a wafer scale fabrication method of a three-dimensional plasmonic metamaterial with strong chiroptical response in the visible region of the electromagnetic spectrum. The system was comprised of metallic nanoparticles arranged in a helical fashion, with high degree of flexibility over the choice of the underlying material, as well as their geometrical parameters. This resulted in exquisite control over the chiroptical properties, most importantly the spectral signature of the circular dichroism. In spite of the large variability in the arrangement, as well as the size and shape of the constituent nanoparticles, the average chiro-optical response of the material remained uniform across the wafer, thus confirming the suitability of this system as a large area chiral metamaterial. By simply heating the substrate for a few minutes, the geometrical properties of the nanoparticles could be altered, thus providing an additional handle towards tailoring the spectral response of this novel material. Electronic supplementary information (ESI) available: Experimental procedure (fabrication and characterization); effect of linear dichroism; chiroptical response for isotropic collection of helices; details of the computational model; thickness dependent red shift. See DOI: 10.1039/c3nr02666c

Singh, Johnson Haobijam; Nair, Greshma; Ghosh, Arijit; Ghosh, Ambarish

2013-07-01

70

Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales  

NASA Astrophysics Data System (ADS)

We introduce a method to fabricate solid-state nanopores with sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer using CMOS compatible semiconductor processes. Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated to have high uniformity (+/-0.5 nm) across the wafer. Arrays of nanopores were fabricated with an average size of 18 +/- 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling. Shorts between the membrane-embedded metals were occasionally created after pore formation, but the RIE based pores had a much better yield (99%) of unshorted electrodes compared to TEM drilled pores (<10%). A double-stranded DNA of length 1 kbp was translocated through the multi-layer structure RIE-based nanopore demonstrating that the pores were open. The ionic current through the pore can be modulated with a gain of 3 using embedded electrodes functioning as a gate in 0.1 mM KCl aqueous solution. This fabrication approach can potentially pave the way to manufacturable nanopore arrays with the ability to electrically control the movement of single or double-stranded DNA inside the pore with embedded electrodes.We introduce a method to fabricate solid-state nanopores with sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer using CMOS compatible semiconductor processes. Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated to have high uniformity (+/-0.5 nm) across the wafer. Arrays of nanopores were fabricated with an average size of 18 +/- 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling. Shorts between the membrane-embedded metals were occasionally created after pore formation, but the RIE based pores had a much better yield (99%) of unshorted electrodes compared to TEM drilled pores (<10%). A double-stranded DNA of length 1 kbp was translocated through the multi-layer structure RIE-based nanopore demonstrating that the pores were open. The ionic current through the pore can be modulated with a gain of 3 using embedded electrodes functioning as a gate in 0.1 mM KCl aqueous solution. This fabrication approach can potentially pave the way to manufacturable nanopore arrays with the ability to electrically control the movement of single or double-stranded DNA inside the pore with embedded electrodes. Electronic supplementary information (ESI) available: Additional data, instrumentation and data analysis methods. See DOI: 10.1039/c3nr06723h

Bai, Jingwei; Wang, Deqiang; Nam, Sung-Wook; Peng, Hongbo; Bruce, Robert; Gignac, Lynn; Brink, Markus; Kratschmer, Ernst; Rossnagel, Stephen; Waggoner, Phil; Reuter, Kathleen; Wang, Chao; Astier, Yann; Balagurusamy, Venkat; Luan, Binquan; Kwark, Young; Joseph, Eric; Guillorn, Mike; Polonsky, Stanislav; Royyuru, Ajay; Papa Rao, S.; Stolovitzky, Gustavo

2014-07-01

71

Modeling electrodeposition for LIGA microdevice fabrication  

SciTech Connect

To better understand and to help optimize the electroforming portion of the LIGA process, we have developed one and two-dimensional numerical models describing electrode-position of metal into high aspect-ratio molds. The one-dimensional model addresses dissociation, diffusion, electromigration, and deposition of multiple ion species. The two-dimensional model is limited to a single species, but includes transport induced by forced flow of electrolyte outside the mold and by buoyancy associated with metal ion depletion within the mold. To guide model development and to validate these models, we have also conducted a series of laboratory experiments using a sulfamate bath to deposit nickel in cylindrical molds having aspect ratios up to twenty-five. The experimental results indicate that current densities well in excess of the diffusion-limited currents may still yield metal deposits of acceptable morphology. However, the numerical models demonstrate that such large ion fluxes cannot be sustained by convection within the mold resulting from flow across the mold top. Instead, calculations suggest that the observed enhancement of transport probably results from natural convection within the molds, and that buoyancy-driven flows may be critical to metal ion transport even in micron-scale features having very large aspect ratios. Taking advantage of this enhanced ion transport may allow order-of-magnitude reductions in electroforming times for LIGA microdevice fabrication. 42 refs., 14 figs., 1 tab.

Griffiths, S.K.; Nilson, R.H.; Bradshaw, R.W. [and others

1998-02-01

72

Temporary bonding for Chips In Wafer processing  

Microsoft Academic Search

Chip In Wafer is a very challenging concept because this solution allows wafer scale processes for System in Package and a very high miniaturization and performance level. This paper describes a technologies developed for Chip integration In Wafer (CIW). The approach consists in reconstituting a wafer from heterogeneous chips embedded in a resin with the active sides coplanar. This paper

J.-C. Souriau; A. Jouve; N. Sillon

2009-01-01

73

Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales.  

PubMed

We introduce a method to fabricate solid-state nanopores with sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer using CMOS compatible semiconductor processes. Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated to have high uniformity (± 0.5 nm) across the wafer. Arrays of nanopores were fabricated with an average size of 18 ± 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling. Shorts between the membrane-embedded metals were occasionally created after pore formation, but the RIE based pores had a much better yield (99%) of unshorted electrodes compared to TEM drilled pores (<10%). A double-stranded DNA of length 1 kbp was translocated through the multi-layer structure RIE-based nanopore demonstrating that the pores were open. The ionic current through the pore can be modulated with a gain of 3 using embedded electrodes functioning as a gate in 0.1 mM KCl aqueous solution. This fabrication approach can potentially pave the way to manufacturable nanopore arrays with the ability to electrically control the movement of single or double-stranded DNA inside the pore with embedded electrodes. PMID:24964839

Bai, Jingwei; Wang, Deqiang; Nam, Sung-Wook; Peng, Hongbo; Bruce, Robert; Gignac, Lynn; Brink, Markus; Kratschmer, Ernst; Rossnagel, Stephen; Waggoner, Phil; Reuter, Kathleen; Wang, Chao; Astier, Yann; Balagurusamy, Venkat; Luan, Binquan; Kwark, Young; Joseph, Eric; Guillorn, Mike; Polonsky, Stanislav; Royyuru, Ajay; Papa Rao, S; Stolovitzky, Gustavo

2014-08-01

74

Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics  

SciTech Connect

Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2?V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure?wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

Sangwan, Vinod K.; Jariwala, Deep; McMorrow, Julian J.; He, Jianting; Lauhon, Lincoln J. [Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208 (United States); Everaerts, Ken [Department of Chemistry, Northwestern University, Evanston, Illinois 60208 (United States); Grayson, Matthew [Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, Illinois 60208 (United States); Marks, Tobin J., E-mail: t-marks@northwestern.edu, E-mail: m-hersam@northwestern.edu; Hersam, Mark C., E-mail: t-marks@northwestern.edu, E-mail: m-hersam@northwestern.edu [Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208 (United States); Department of Chemistry, Northwestern University, Evanston, Illinois 60208 (United States)

2014-02-24

75

Synthesis of wafer-scale hexagonal boron nitride monolayers free of aminoborane nanoparticles by chemical vapor deposition  

NASA Astrophysics Data System (ADS)

Hexagonal boron nitride (h-BN) has gained great attention as a two-dimensional material, along with graphene. In this work, high-quality h-BN monolayers were grown in wafer scale (7 × 7 cm2) on Cu substrates by using low-pressure chemical vapor deposition (LPCVD). We created h-BN monolayers that were free of polymeric aminoborane (BH2NH2) nanoparticles, which are undesirable by-products of the ammonia borane precursor, by employing a simple filtering system in the CVD process. The optical band gap of 6.06 eV and sharp and symmetric Raman peak measured at 1371 cm-1 indicate the synthesis of monolayer h-BN. In addition, spherical aberration (CS)-corrected high-resolution transmission electron microscopic images confirm the production of a single-layer hexagonal array of boron and nitrogen atoms.

Han, Jaehyun; Lee, Jun-Young; Kwon, Heemin; Yeo, Jong-Souk

2014-04-01

76

Synthesis of wafer-scale hexagonal boron nitride monolayers free of aminoborane nanoparticles by chemical vapor deposition.  

PubMed

Hexagonal boron nitride (h-BN) has gained great attention as a two-dimensional material, along with graphene. In this work, high-quality h-BN monolayers were grown in wafer scale (7 × 7 cm(2)) on Cu substrates by using low-pressure chemical vapor deposition (LPCVD). We created h-BN monolayers that were free of polymeric aminoborane (BH2NH2) nanoparticles, which are undesirable by-products of the ammonia borane precursor, by employing a simple filtering system in the CVD process. The optical band gap of 6.06 eV and sharp and symmetric Raman peak measured at 1371 cm(-1) indicate the synthesis of monolayer h-BN. In addition, spherical aberration (CS)-corrected high-resolution transmission electron microscopic images confirm the production of a single-layer hexagonal array of boron and nitrogen atoms. PMID:24633210

Han, Jaehyun; Lee, Jun-Young; Kwon, Heemin; Yeo, Jong-Souk

2014-04-11

77

Erasable diffractive grating couplers in silicon on insulator for wafer scale testing  

NASA Astrophysics Data System (ADS)

Test points are essential in allowing optical circuits on a wafer to be autonomously tested after selected manufacturing steps, hence allowing poor performance or device failures to be detected early and to be either repaired using direct write methods, or a cessation of further processing to reduce fabrication costs. Grating couplers are a commonly used method for efficiently coupling light from an optical fibre to a silicon waveguide. They are relatively easy to fabricate and they allow light to be coupled into/out from any location on the device without the need for polishing, making them good candidates for an optical test point. A fixed test point can be added for this purpose, although traditionally these grating devices are fabricated by etching the silicon waveguide, and hence this permanently adds loss and leads to a poor performing device when placed into use after testing. We demonstrate a similar device utilising a refractive index change induced by lattice disorder. Raman data collected suggests this lattice damage is reversible, allowing a laser to subsequently erase the grating coupler.

Topley, R.; Martinez-Jimenez, G.; O'Faolain, L.; Healy, N.; Mailis, S.; Thomson, D. J.; Gardes, F. Y.; Peacock, A. C.; Payne, D. N. R.; Mashanovich, G. Z.; Reed, G. T.

2014-03-01

78

Industrial applications for LIGA-fabricated micro heat exchangers  

Microsoft Academic Search

One of the well-known benefits of micro scale is enhanced heat transfer. This fact provides the motivation for fabricating a variety of micro heat exchangers using derivatives of the LIGA micromachining process. These heat exchangers can be made of polymers, nickel (electroplated or electroless), or ceramics (Si3N4 and alumina are presently being investigated). These heat exchangers are envisioned for applications

Kevin W. Kelly; Chad Harris; Lyndon S. Stephens; Christophe Marques; Dan Foley

2001-01-01

79

Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics.  

PubMed

Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V. PMID:24256403

Heo, Jinseong; Byun, Kyung-Eun; Lee, Jaeho; Chung, Hyun-Jong; Jeon, Sanghun; Park, Seongjun; Hwang, Sungwoo

2013-01-01

80

Nanogap-enhanced infrared spectroscopy with template-stripped wafer-scale arrays of buried plasmonic cavities.  

PubMed

We have combined atomic layer lithography and template stripping to produce a new class of substrates for surface-enhanced infrared absorption (SEIRA) spectroscopy. Our structure consists of a buried and U-shaped metal-insulator-metal waveguide whose folded vertical arms efficiently couple normally incident light. The insulator is formed by atomic layer deposition (ALD) of Al2O3 and precisely defines the gap size. The buried nanocavities are protected from contamination by a silicon template until ready for use and exposed by template stripping on demand. The exposed nanocavity generates strong infrared resonances, tightly confines infrared radiation into a gap that is as small as 3 nm (?/3300), and creates a dense array of millimeter-long hotspots. After partial removal of the insulators, the gaps are backfilled with benzenethiol molecules, generating distinct Fano resonances due to strong coupling with gap plasmons, and a SEIRA enhancement factor of 10(5) is observed for a 3 nm gap. Because of the wafer-scale manufacturability, single-digit-nanometer control of the gap size via ALD, and long-term storage enabled by template stripping, our buried plasmonic nanocavity substrates will benefit broad applications in sensing and spectroscopy. PMID:25423481

Chen, Xiaoshu; Ciracì, Cristian; Smith, David R; Oh, Sang-Hyun

2015-01-14

81

Wafer-scale fabrication of self-actuated piezoelectric nanoelectromechanical resonators based on lead zirconate titanate (PZT)  

NASA Astrophysics Data System (ADS)

In this paper we report an unprecedented level of integration of self-actuated nanoelectromechanical system (NEMS) resonators based on a 150?nm thick lead zirconate titanate (PZT) thin film at the wafer-scale. A top-down approach combining ultraviolet (UV) lithography with other standard planar processing technologies allows us to achieve high-throughput manufacturing. Multilayer stack cantilevers with different geometries have been implemented with measured fundamental resonant frequencies in the megahertz range and Q-factor values ranging from ~130 in air up to ~900 in a vacuum at room temperature. A refined finite element model taking into account the exact configuration of the piezoelectric stack is proposed and demonstrates the importance of considering the dependence of the beam’s cross-section upon the axial coordinate. We extensively investigate both experimentally and theoretically the transduction efficiency of the implemented piezoelectric layer and report for the first time at this integration level a piezoelectric constant of {{d}31}=15 ?fm?V?1. Finally, we discuss the current limitations to achieve piezoelectric detection.

Dezest, D.; Thomas, O.; Mathieu, F.; Mazenq, L.; Soyer, C.; Costecalde, J.; Remiens, D.; Deü, J. F.; Nicu, L.

2015-03-01

82

Facile fabrication of wafer-scale MoS2 neat films with enhanced third-order nonlinear optical performance.  

PubMed

Wafer-scale MoS2 neat films with controllable thicknesses were successfully fabricated by vacuum filtering liquid-exfoliated MoS2 dispersions. The obtained MoS2 filtered thin films were systematically characterized by UV-Vis spectroscopy, Fourier transform infrared spectroscopy (FTIR), Raman spectroscopy, atomic force microscopy (AFM) and scanning electron microscopy (SEM). It was found that the fabricated scalable MoS2 films have a smooth surface and high optical homogeneity verified by AFM and a collimated 532 nm beam, respectively. We investigated the ultrafast nonlinear optical (NLO) properties of the filtered films by an open aperture Z-scan method using 515 and 1030 nm femtosecond laser pulses. Saturable absorption was observed at both 515 and 1030 nm with the figure of merit (FOM) values as ?3.3 × 10(-12) esu cm and ?3.4 × 10(-14) esu cm, respectively. The observation of ultrafast NLO performance of the MoS2 filtered films indicates that vacuum filtration is a feasible method for the fabrication of optical thin films, which can be expanded to fabricate other two-dimensional films from the corresponding dispersions. This easy film fabrication technology will greatly enlarge the application of graphene analogues including graphene in photonic devices, especially of MoS2 as a saturable absorber. PMID:25597818

Zhang, Xiaoyan; Zhang, Saifeng; Chang, Chunxia; Feng, Yanyan; Li, Yuanxin; Dong, Ningning; Wang, Kangpeng; Zhang, Long; Blau, Werner J; Wang, Jun

2015-02-21

83

Integration of hexagonal boron nitride with quasi-freestanding epitaxial graphene: toward wafer-scale, high-performance devices.  

PubMed

Hexagonal boron nitride (h-BN) is a promising dielectric material for graphene-based electronic devices. Here we investigate the potential of h-BN gate dielectrics, grown by chemical vapor deposition (CVD), for integration with quasi-freestanding epitaxial graphene (QFEG). We discuss the large scale growth of h-BN on copper foil via a catalytic thermal CVD process and the subsequent transfer of h-BN to a 75 mm QFEG wafer. X-ray photoelectron spectroscopy (XPS) measurements confirm the absence of h-BN/graphitic domains and indicate that the film is chemically stable throughout the transfer process, while Raman spectroscopy indicates a 42% relaxation of compressive stress following removal of the copper substrate and subsequent transfer of h-BN to QFEG. Despite stress-induced wrinkling observed in the films, Hall effect measurements show little degradation (<10%) in carrier mobility for h-BN coated QFEG. Temperature dependent Hall measurements indicate little contribution from remote surface optical phonon scattering and suggest that, compared to HfO(2) based dielectrics, h-BN can be an excellent material for preserving electrical transport properties. Graphene transistors utilizing h-BN gates exhibit peak intrinsic cutoff frequencies >30 GHz (2.4× that of HfO(2)-based devices). PMID:22545808

Bresnehan, Michael S; Hollander, Matthew J; Wetherington, Maxwell; LaBella, Michael; Trumbull, Kathleen A; Cavalero, Randal; Snyder, David W; Robinson, Joshua A

2012-06-26

84

FOLDED-PATCH CHIP-SIZE ANTENNAS FOR WIRELESS MICROSYSTEMS USING WAFER-LEVEL CHIP-SCALE PACKAGING  

Microsoft Academic Search

This paper reports on design and fabrication options of an integrated folded shorted-patch chip-size antenna for applications in short-range wireless microsystems. The antenna is built using a stack of two adhesively bonded wafers with patterned metallization and through-wafer electrical interconnects. Different fabrication options based on via formation in glass and\\/or high-resistivity silicon substrates using excimer laser ablation or powder blasting

P. M. Mendes; A. Polyakov; M. Bartek; J. N. Burghartz; J. H. Correia

85

Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.  

PubMed

Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers. PMID:25365786

Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

2014-11-25

86

Highly Efficient Extraction of Mechanical and Linear and Quadratic Piezoresistive Properties of Poly-Si Films using Wafer-Scale Microtensile Testing  

Microsoft Academic Search

This paper reports on the extension of the wafer-scale microtensile technique to the piezoresistive characterization of thin-films, demonstrated for in-situ n-doped poly-Si layers. In addition to the reliable extraction of mechanical properties, this extended high-throughput method enables the acquisition of linear and, for the first time, nonlinear piezoresistive coefficients, namely the first and second order longitudinal parameters, pil,1 and pil,2,

M. E. Schmidt; J. Gaspar; J. Held; S. Kamiya; O. Paul

2009-01-01

87

Injection molding of polymeric LIGA HARMs  

Microsoft Academic Search

The primary goal of an ongoing research effort at LSU is to develop the three-step LIGA process to inexpensively manufacture\\u000a high aspect ratio microstructures (HARMs). The first two steps of the process (lithography and electroplating) produce a metallic\\u000a mold insert that can be used as a template for molding microstructures. The final step of LIGA is molding. This paper focuses

M. S. Despa; K. W. Kelly; J. R. Collier

1999-01-01

88

Slip, Crystal Orientation, and Damage Evolution During Thermal Cycling in High-Strain Wafer-Level Chip-Scale Packages  

NASA Astrophysics Data System (ADS)

Wafer-level chip-scale package samples with pre-cross-sectioned edge rows were thermally cycled to study microstructure evolution and damage development. Electron backscattered diffraction (EBSD) and high-energy x-ray diffraction were used to obtain Sn grain orientations and the average coefficient of thermal expansion normal to the board in every joint of the package for samples in the as-fabricated and thermally cycled conditions. The results indicated a near-random distribution of joint orientation. Optical, scanning electron microscopy, and EBSD methods were used to characterize microstructure changes in pre-cross-sectioned samples due to thermal cycling. Slip trace analysis and Orientation Imaging Microscopy™ (OIM) show that slip systems with high Schmid factors (estimated global shear stress based on the package neutral point) are responsible for the observed microstructure evolution during thermal cycling, which provides information about slip systems that are more easily activated. Two joints were analyzed in detail to evaluate slip activity at different stages of their thermal history. The first case showed that a solidification twin grain boundary misorientation deviated from the twin relationship due to slip activity during thermal cycling, which can influence damage development and the path of crack propagation. The second case showed a new grain orientation developing due to gradual lattice rotation about the Sn [110] axis by a continuous recrystallization mechanism. This rotation was correlated with the operation of slip system . Small tin whiskers emerged from the initially polished chip interface and grew with increasing thermal cycles until a crack developed in the solder that relieved the stress. As the local stresses are not known experimentally, this analysis provides observations that can be compared with a crystal plasticity model simulation.

Zhou, Bite; Zhou, Quan; Bieler, Thomas R.; Lee, Tae-kyu

2015-03-01

89

Si nanowire directly grown on a liquid metal substrate—towards wafer scale transferable nanowire arrays with improved visible-light sterilization  

NASA Astrophysics Data System (ADS)

Integrating vertically aligned nanowires (NWs) on a functional substrate is important for the application of NWs in wafer scale assemblies and functional devices. However, vertically aligned NWs via the current epitaxial growth route can only be prepared on crystalline wafers. A convenient method is thus presented to overcome NW substrate limitations. Liquid metal is proposed to serve as a substrate for the initial growth of vertically aligned NWs. NWs could then be harvested from the growth substrate and integrated with functional substrates. Fabricated vertically aligned silicon NWs (SiNWs) were grown on molten Sn and then integrated into a flexible transparent poly(dimethylsiloxane) film to obtain a SiNW/functional substrate device. The device showed enhanced visible-light absorption ability and refreshable visible-light bactericidal activities with a bacterial reduction rate of close to 100%, indicating that growth with molten metal as a substrate could be a promising approach for extending the function and application of NWs.

Wang, Hui; Wang, Jian-Tao; Ou, Xue-Mei; Lee, Chun-Sing; Zhang, Xiao-Hong

2014-04-01

90

Microfabrication: LIGA-X and applications  

NASA Astrophysics Data System (ADS)

X-ray LIGA (Lithography, Electrogrowth, Moulding) is one of today's key technologies in microfabrication and upcoming modern (meso)-(nano) fabrication, already used and anticipated for micromechanics (micromotors, microsensors, spinnerets, etc.), micro-optics, micro-hydrodynamics (fluidic devices), microbiology, in medicine, in biology, and in chemistry for microchemical reactors. It compares to micro-electromechanical systems (MEMS) technology, offering a larger, non-silicon choice of materials and better inherent precision. X-ray LIGA relies on synchrotron radiation to obtain necessary X-ray fluxes and uses X-ray proximity printing. Inherent advantages are its extreme precision, depth of field and very low intrinsic surface roughness. However, the quality of fabricated structures often depends on secondary effects during exposure and effects like resist adhesion. UV-LIGA, relying on thick UV resists is an alternative for projects requiring less precision. Modulating the spectral properties of synchrotron radiation, different regimes of X-ray lithography lead to (a) the mass-fabrication of classical nanostructures, (b) the fabrication of high aspect ratio nanostructures (HARNST), (c) the fabrication of high aspect ratio microstructures (HARMST), and (d) the fabrication of high aspect ratio centimeter structures (HARCST). Reviewing very recent activities around X-ray LIGA, we show the versatility of the method, obviously finding its region of application there, where it is best and other competing microtechnologies are less advantageous. An example of surface-based X-ray and particle lenses (orthogonal reflection optics (ORO)) made by X-ray LIGA is given.

Kupka, R. K.; Bouamrane, F.; Cremers, C.; Megtert, S.

2000-09-01

91

Minimum silicon wafer thickness for ID wafering  

NASA Technical Reports Server (NTRS)

An analytical model, based on fracture mechanics analysis, is proposed for estimating the minimum wafer thickness as a function of the diameter requirement for solar cells. The conditions under which the model can be applied are discussed with reference to the critical flaw size, the applied force, and the width of the side support. It is shown that the equivalent cantilever force applied during ID slicing can be estimated from the wafering mechanical yield data. The width of the wafer side support was found to be a significant factor in controlling the minimum allowable wafer thickness during slicing. Wafer side support width requirements were found to increase with decreasing wafer thickness.

Chen, C. P.

1982-01-01

92

Imaging ATUM ultrathin section libraries with WaferMapper: a multi-scale approach to EM reconstruction of neural circuits  

PubMed Central

The automated tape-collecting ultramicrotome (ATUM) makes it possible to collect large numbers of ultrathin sections quickly—the equivalent of a petabyte of high resolution images each day. However, even high throughput image acquisition strategies generate images far more slowly (at present ~1 terabyte per day). We therefore developed WaferMapper, a software package that takes a multi-resolution approach to mapping and imaging select regions within a library of ultrathin sections. This automated method selects and directs imaging of corresponding regions within each section of an ultrathin section library (UTSL) that may contain many thousands of sections. Using WaferMapper, it is possible to map thousands of tissue sections at low resolution and target multiple points of interest for high resolution imaging based on anatomical landmarks. The program can also be used to expand previously imaged regions, acquire data under different imaging conditions, or re-image after additional tissue treatments. PMID:25018701

Hayworth, Kenneth J.; Morgan, Josh L.; Schalek, Richard; Berger, Daniel R.; Hildebrand, David G. C.; Lichtman, Jeff W.

2014-01-01

93

Effect of shroud flow on high quality In x Ga 1?x N deposition in a production scale multi-wafer-rotating-disc reactor  

Microsoft Academic Search

High quality InGaN thin films and InGaN\\/GaN double heterojunction (DH) structures have been epitaxially grown on c-sapphire\\u000a substrates by MOCVD in a production scale multi-wafer-rotating-disc reactor between 770 to 840?C. We observed that shroud\\u000a flow (majority carrier gas in the reaction chamber) is the key to obtaining high quality InGaN thin films. High purity H2 as the shroud flow results

C. Yuan; T. Salagaj; W. Kroll; R. A. Stall; M. Schurman; C. Y. Hwang; Y. Li; W. E. Mayo; Y. Lu; S. Krishnankutty; R. M. Kolbas

1996-01-01

94

A practical, flip-chip, multi-layer pre-encapsulation technology for wafer-scale underfill  

Microsoft Academic Search

This paper describes the conception, development, and application of a novel materials set and methodology for fabricating assembly-ready flip chips pre-encapsulated, at the wafer level, with a low coefficient of thermal expansion (CTE) underfill. This technology is unique in that it addresses a key challenge currently facing the high density interconnect (HDI) electronics industry-how to produce cost-effectively, in a streamlined

Robert V. Burress; M. Albert Capote; Yong-Joon Lee; Howard A. Lenos; Jeffrey F. Zamora

2001-01-01

95

Silicon Wafer Epitaxy  

NSDL National Science Digital Library

This Quicktime animation shows an optional process for creating silicon epitaxial wafers. The animations shows a trichlorosilane gas being injected which creates a monocrystaline film atop the preexisting wafer. This is the seventh animation in a series of how silicon wafers are created. The previous animation showing silicon wafer polishing can be seen here.The next and final animation in this sequence about silicon wafer laser inspection can be seen here.

96

Low Temperature Curing of Polyimide Wafer Coatings  

Microsoft Academic Search

Polyimide films are commonly used on wafers as passivation layers, stress buffer layers, dry etch masks, structural layers, and re-distribution layers for chip scale packaging and wafer level packaging. These films are cured in convection or diffusion ovens at high enough temperatures (350-400 ?C) to assure adequate mechanical and electrical properties. These high temperatures can change the electrical properties of

97

The Covidien LigaSure Maryland Jaw Device.  

PubMed

Since its invention nearly 20 years ago, the Covidien LigaSure device along with its ForceTriad generator has dominated the Electrothermal Bipolar Vessel Sealing market. The LigaSure was used for surgical procedures, both open and laparoscopic. The purpose of this review is to provide evidence of the safety and utility of the LigaSure device compared to more traditional means of hemostasis and its ultrasonic competitor, particularly in laparoscopic applications. We will provide evidence related to electrothermal bipolar vessel sealing in general and look specifically at Covidien's newest product, the LigaSure Maryland Jaw Device. PMID:25431842

Zaidi, Nisar; Glover, Anthony R; Sidhu, Stanley B

2015-03-01

98

Fabrication of miniaturized electrostatic deflectors using LIGA  

NASA Astrophysics Data System (ADS)

We are currently investigating the fabrication of high precision, miniaturized, electrostatic deflectors for use in electron or ion beam micro-columns. These columns can be used in a broad array of applications including microscopy, spectroscopy and lithography. Typically, micro-columns consist of a field emitter tip, a set of micromachined miniaturized lenses and one or more electrostatic deflectors. Miniaturization of the column allows the use of simple electrostatic lenses to achieve very high performance in a package that is just a few millimeters in length. Presently, all reported microcolumns have included miniaturized but conventionally-machined octupole deflector plates. If micromachined plates are used instead, lower deflection voltage is required for deflection, and the system becomes more amenable to very high speed operation. In addition, some reduction in scan field distortion is expected. These improvements results directly from the higher degree of miniaturization, tighter dimensional control, better placement accuracy, and smoother facets offered by micromachining. Given the dimensions (100 micrometers - 1000 micrometers thick) and tolerances (1 - 10 micrometers ) required, LIGA is well suited to fabricate such miniature deflectors. This paper will describe the fabrication of the deflectors using LIGA. The Center for X-ray Optics has built an endstation at Lawrence Berkeley National Laboratory's Advanced Light Source suitable for LIGA X-ray exposures.

Jackson, Keith H.; Khan Malek, Chantal G.; Murray, Lawrence P.; Bonivert, William D.; Hruby, Jill M.; Hachman, John T.; Chang, T. H.

1995-09-01

99

LIGA microsystems aging : evaluation and mitigation.  

SciTech Connect

The deployment of LIGA structures in DP applications requires a thorough understanding of potential long term physical and chemical changes that may occur during service. While these components are generally fabricated from simple metallic systems such as copper, nickel and nickel alloys, the electroplating process used to form them creates microstructural features which differ from those found in conventional (e.g. ingot metallurgy) processing of such materials. Physical changes in non-equilibrium microstructures may occur due to long term exposure to temperatures sufficient to permit atomic and vacancy mobility. Chemical changes, particularly at the surfaces of LIGA parts, may occur in the presence of gaseous chemical species (e.g. water vapor, HE off-gassing compounds) and contact with other metallic structures. In this study, we have characterized the baseline microstructure of several nickel-based materials that are used to fabricate LIGA structures. Solute content and distribution was found to have a major effect on the electroplated microstructures. Microstructural features were correlated to measurements of hardness and tensile strength. Dormancy testing was conducted on one of the baseline compositions, nickel-sulfamate. Groups of specimens were exposed to controlled thermal cycles; subsequent examinations compared properties of 'aged' specimens to the baseline conditions. Results of our testing indicate that exposure to ambient temperatures (-54 C to 71 C) do not result in microstructural changes that might be expected to significantly effect mechanical performance. Additionally, no localized changes in surface appearance were found as a result of contact between electroplated parts.

Cadden, Charles H.; Yang, Nancy Y. C.; San Marchi, Christopher W.

2003-12-01

100

Layer-controlled, wafer-scale, and conformal synthesis of tungsten disulfide nanosheets using atomic layer deposition.  

PubMed

The synthesis of atomically thin transition-metal disulfides (MS2) with layer controllability and large-area uniformity is an essential requirement for their application in electronic and optical devices. In this work, we describe a process for the synthesis of WS2 nanosheets through the sulfurization of an atomic layer deposition (ALD) WO3 film with systematic layer controllability and wafer-level uniformity. The X-ray photoemission spectroscopy, Raman, and photoluminescence measurements exhibit that the ALD-based WS2 nanosheets have good stoichiometry, clear Raman shift, and bandgap dependence as a function of the number of layers. The electron mobility of the monolayer WS2 measured using a field-effect transistor (FET) with a high-k dielectric gate insulator is shown to be better than that of CVD-grown WS2, and the subthreshold swing is comparable to that of an exfoliated MoS2 FET device. Moreover, by utilizing the high conformality of the ALD process, we have developed a process for the fabrication of WS2 nanotubes. PMID:24252136

Song, Jeong-Gyu; Park, Jusang; Lee, Wonseon; Choi, Taejin; Jung, Hanearl; Lee, Chang Wan; Hwang, Sung-Hwan; Myoung, Jae Min; Jung, Jae-Hoon; Kim, Soo-Hyun; Lansalot-Matras, Clement; Kim, Hyungjun

2013-12-23

101

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology  

NASA Astrophysics Data System (ADS)

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 ?m SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

102

Safety and efficacy of LigaSure usage in pancreaticoduodenectomy  

PubMed Central

Background Over recent years, use of the LigaSure™ vessel sealing device has increased in major abdominal surgery to include pancreaticoduodenectomy (PD). LigaSure™ use during PD has expanded to include all steps of the procedure, including the division of the uncinate margin. This introduces the potential for thermal major vascular injury or margin positivity. The aim of the present study was to evaluate the safety and efficacy of LigaSure™ usage in PD in comparison to established dissection techniques. Methods One hundred and forty-eight patients who underwent PD from 2007 to 2012 at Robert Wood Johnson University Hospital were identified from a retrospective database. Two groups were recognized: those in which the LigaSure™ device was used (N = 114), and in those it was not (N = 34). Peri-operative outcomes were compared. Results Vascular intra-operative complications directly caused by thermal injury from LigaSure™ use occurred in 1.8% of patients. Overall vascular intra-operative complications, uncinate margin positivity, blood loss, length of stay, and complication severity were not significantly different between groups. The mean operative time was 77 min less (P < 0.010) in the LigaSure™ group. Savings per case where the LigaSure™ was used amounted to $1776.73. Conclusion LigaSure™ usage during PD is safe and effective. It is associated with decreased operative times, which may decrease operative costs in PD. PMID:23782268

Eng, Oliver S; Goswami, Julie; Moore, Dirk; Chen, Chunxia; Brumbaugh, Jennifer; Gannon, Christopher J; August, David A; Carpizo, Darren R

2013-01-01

103

Scheduling semiconductor wafer fabrication  

Microsoft Academic Search

The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer

LAWRENCE M. WEIN

1988-01-01

104

Silicon Wafer Polishing  

NSDL National Science Digital Library

This Quicktime animation demostrates the final polishing and cleaning processes required for creating semiconductor devices and integrated circuits. This animation is the sixth in a series of how silicon wafers are created. The previous animation showing silicon wafer lapping can be seen here. The next animation in this sequence about the optional silicon wafer epitaxy process can be seen here.

105

Role of wafer geometry in wafer chucking  

NASA Astrophysics Data System (ADS)

Wafer chucks are used in advanced lithography systems to hold and flatten wafers during exposure. To minimize defocus and overlay errors, it is important that the chuck provide sufficient pressure to completely chuck the wafer and remove flatness variations across a broad range of spatial wavelengths. Analytical and finite element models of the clamping process are presented here to understand the range of wafer geometry features that can be fully chucked with different clamping pressures. The analytical model provides a simple relationship to determine the maximum feature amplitude that can be chucked as a function of spatial wavelength and chucking pressure. Three-dimensional finite element simulations are used to examine the chucking of wafers with various geometries, including cases with simulated and measured shapes. The analytical and finite element results both demonstrate that geometry variations with short spatial wavelengths (e.g., high-frequency wafer shape features) present the greatest challenge to achieving complete chucking. The models and results presented here can be used to provide guidance on wafer geometry and chuck designs for advanced exposure tools.

Turner, Kevin T.; Ramkhalawon, Roshita; Sinha, Jaydeep K.

2013-04-01

106

Injection molding of LIGA and LIGA-similar microstructures using filled and unfilled thermoplastics  

NASA Astrophysics Data System (ADS)

Micromolding is a key technology for the economic production of micro-components for microsystems. It is applied in several microstructuring techniques including the LIGA process which was invented and developed at Forschungszentrum Karlsruhe. Injection molding of multiple-use LIGA tool inserts produced by deep-etch x-ray lithography and electroforming allows the economic production of components for most applications using microsystems technology. Such microstructures are produced in small and large series and commercialized by Forschungszentrum Karlsruhe and the microParts Company, Dormund, Germany, cooperating within the framework of a license agreement. Special molding machines are applied for the production of single- or multi-stepped microstructures of a few micrometers in lateral dimension and structural details in the submicrometer range. Maximum aspect ratios of several ten up to 600 are achieved. In contrast to compact disc production, the machines are equipped with a special control unit, by means of which tool temperature is often kept above the melting temperatures of the plastics processed during injection. Evacuation of the tool cavity is required for the complete filling of the microstructurized nest area of the mold. Cycle time is mainly determined by the heating and cooling of the whole molding tool. Recently, novel techniques were developed for the production of ceramic LIGA or LIGA-similar microstructures at Forschungszentrum Karlsruhe, where further development of the LIGA technique has been performed for more than a decade. Using lost plastic microstructures and sometimes even metal tools, microstructures are made of structural (e.g., aluminum oxide, zirconium oxide) and functional ceramics (e.g., PZT). Current development activities are aimed at producing lost plastic molds for metal microstructures by injection molding. Molding tests with conductively filled thermoplastics have been carried out to manufacture lost molds for e.g. spin nozzles.

Ruprecht, Robert; Bacher, Walter; Hausselt, Juergen H.; Piotter, Volker

1995-09-01

107

Silicon Wafer Lapping  

NSDL National Science Digital Library

This Quicktime animation shows how the machining process of "lapping" removes controlled amounts of silicon from a wafer in order to ensure flatness of the silicon wafer. This process removes particles and improves the quality of the wafer after they are cut. This animation is the fifth in a series of how silicon wafers are created.The previous animation showing silicon ingot edge profiling can be seen here.The next animation in this sequence about silicon wafer polishing can be seen here.

108

Hydrophobic silicon wafer bonding  

NASA Astrophysics Data System (ADS)

Wafers prepared by an HF dip without a subsequent water rinse were bonded at room temperature and annealed at temperatures up to 1100 °C. Based on substantial differences between bonded hydrophilic and hydrophobic Si wafer pairs in the changes of the interface energy with respect to temperature, secondary ion mass spectrometry (SIMS) and transmission electron microscopy (TEM), we suggest that hydrogen bonding between Si-F and H-Si across two mating wafers is responsible for room temperature bonding of hydrophobic Si wafers. The interface energy of the bonded hydrophobic Si wafer pairs does not change appreciably with time up to 150 °C. This stability of the bonding interface makes reversible room-temperature hydrophobic wafer bonding attractive for the protection of silicon wafer surfaces.

Tong, Q.-Y.; Schmidt, E.; Gösele, U.; Reiche, M.

1994-01-01

109

Micro-grippers for assembly of LIGA parts  

SciTech Connect

This paper describes ongoing testing of two microgrippers for assembly of LIGA (Lithographie Galvanoformung Abformung) parts. The goal is to place 100 micron outside diameter (OD) LIGA gears with a 50 micron inner diameter hole onto pins ranging from 35 to 49 microns. The first micro gripper is a vacuum gripper made of a 100 micron OD stainless steel tube. The second micro gripper is a set of tweezers fabricated using the LIGA process. Nickel, Permalloy, and copper materials are tested. The tweezers are actuated by a collet mechanism which is closed by a DC linear motor.

Feddema, J.; Polosky, M.; Christenson, T.; Spletzer, B.; Simon, R.

1997-12-31

110

Robust Si wafer  

Microsoft Academic Search

Heavily B- and Ge-codoped Si wafers with and without swirl defects have been characterized in comparison with lightly B-doped and heavily B-doped Si wafers (with and without swirl defects) as references. It was found that only very few slip dislocations could be observed in the heavily B- and Ge-codoped (1019atoms\\/cm3) Si wafers whereas many slip dislocations were observed in both

Xinming Huang; Tsuyoshi. Sato; Masami Nakanishi; Toshinori Taishi; Keigo Hoshikawa; Satoshi Uda

2005-01-01

111

Low temperature curing of polyimide wafer coatings  

Microsoft Academic Search

Polyimide films are commonly used on wafers as passivation layers, stress buffer layers, dry etch masks, structural layers, and re-distribution layers for chip scale packaging and wafer level packaging. These films are cured in convection or diffusion ovens at high enough temperatures (350-400°C) to assure adequate mechanical and electrical properties. These high temperatures can change the electrical properties of the

R. L. Hubbard; Z. Fathi; I. Ahmad; H. Matsutani; T. Hattori

2004-01-01

112

Modeling and analysis of 96.5Sn3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board  

Microsoft Academic Search

In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive

John H. Lau; S.-W. R. Lee

2002-01-01

113

COMIT DE COMPETICIN LIGA INTERNA FUTBOL-7 2013/2014  

E-print Network

COMITÉ DE COMPETICIÓN LIGA INTERNA FUTBOL-7 2013/2014 ACTA JORNADA nº 12 10/02/2014 GRUPO A JORNADA falta grave. JORNADA 12 ENCUENTRO: SWANN CITY ­ PUBLIYOTES FUTBOL CLUB Sanción con falta grave al equipo

Rey Juan Carlos, Universidad

114

Miniature Scroll Pumps Fabricated by LIGA  

NASA Technical Reports Server (NTRS)

Miniature scroll pumps have been proposed as roughing pumps (low - vacuum pumps) for miniature scientific instruments (e.g., portable mass spectrometers and gas analyzers) that depend on vacuum. The larger scroll pumps used as roughing pumps in some older vacuum systems are fabricated by conventional machining. Typically, such an older scroll pump includes (1) an electric motor with an eccentric shaft to generate orbital motion of a scroll and (2) conventional bearings to restrict the orbital motion to a circle. The proposed miniature scroll pumps would differ from the prior, larger ones in both design and fabrication. A miniature scroll pump would include two scrolls: one mounted on a stationary baseplate and one on a flexure stage (see figure). An electromagnetic actuator in the form of two pairs of voice coils in a push-pull configuration would make the flexure stage move in the desired circular orbit. The capacitance between the scrolls would be monitored to provide position (gap) feedback to a control system that would adjust the drive signals applied to the voice coils to maintain the circular orbit as needed for precise sealing of the scrolls. To minimize power consumption and maximize precision of control, the flexure stage would be driven at the frequency of its mechanical resonance. The miniaturization of these pumps would entail both operational and manufacturing tolerances of <1 m. Such tight tolerances cannot be achieved easily by conventional machining of high-aspect-ratio structures like those of scroll-pump components. In addition, the vibrations of conventional motors and ball bearings exceed these tight tolerances by an order of magnitude. Therefore, the proposed pumps would be fabricated by the microfabrication method known by the German acronym LIGA ( lithographie, galvanoformung, abformung, which means lithography, electroforming, molding) because LIGA has been shown to be capable of providing the required tolerances at large aspect ratios.

Wiberg, Dean; Shcheglov, Kirill; White, Victor; Bae, Sam

2009-01-01

115

Wafer warpage analysis of stacked wafers for 3D integration  

Microsoft Academic Search

The demand for wafer stacking technology has been increasing significantly. Although many technical challenges of wafer stacking have improved greatly, there are still many processing issues to be resolved. One of them is wafer warpage since it causes process and product failures such as delamination, cracking, mechanical stresses, and even electrical failure. In this study the warpage of multi-stacked wafers

Youngrae Kim; Sung-Keun Kang; Sung-Dong Kim; Sarah Eunkyung Kim

116

Wafer scale micromachine assembly method  

DOEpatents

A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.

Christenson, Todd R. (Albuquerque, NM)

2001-01-01

117

Semiconductor wafer bonding  

NASA Astrophysics Data System (ADS)

When mirror-polished, flat, and clean wafers are brought into contact, they are locally attracted to each other and adhere or bond. This phenomenon is known as semiconductor wafer bonding. Different adhesion forces (van der Waals forces, hydrogen bonding) are the reason for the bonding effect at room temperature. The different bonding mechanisms acting in dependence on the surface conditions (hydrophilic, hydrophobic) are reviewed. Variations of the properties of bonded interfaces (structural, mechanical, electrical) during annealing are discussed. The focus is on low-temperature bonding techniques. Reasons for the formation of interface defects are presented. Applications of semiconductor wafer bonding for future developments are briefly summarized.

Reiche, M.

2006-03-01

118

In-Situ Investigation of Wafer-Slurry-Pad Interactions during CMP , A. Mueller  

E-print Network

In-Situ Investigation of Wafer-Slurry-Pad Interactions during CMP N. Braun 1 , C. Gray 1 , A.Moinpour@intel.com The objective of this project is to acquire in-situ data during chemical mechanical planarization (CMP) including slurry film thickness and flow, wafer-pad contact, wafer- scale friction, and small-scale shear

White, Robert D.

119

Wafer characteristics via reflectometry  

DOEpatents

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Sopori, Bhushan L. (Denver, CO)

2010-10-19

120

SOD wafer technology  

Microsoft Academic Search

Silicon-on-diamond (SOD) structured wafer with 4-inch diameter was fabricated by the technologies of CVD diamond deposition, Si wafer bonding and thinning. Diamond thin film with high quality and low interface state density was uniformly deposited on Silicon (001) substrate, continuous H+ ion bombardment to as-grown film surface under DC bias was performed to decrease the intrinsic tensile stress in the

C. Z. Gu; Y. Sun; J. K. Jia; Z. S. Jin

2003-01-01

121

From Wafer to Package  

NSDL National Science Digital Library

This website includes an animation of finished wafer to packaged integrated Circuits. Objective: Describe the wafer to packaged device process steps. This simulation is from Module 075 of the Process & Equipment III Cluster of the MATEC Module Library (MML). You will find the animation under the heading "Process & Equipment III." To view other clusters or for more information about the MML visit http://matec.org/ps/library3/process_I.shtmlKey

122

Stable wafer-carrier system  

DOEpatents

One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

2013-10-22

123

Recent Developments in Microsystems Fabricated by the Liga-Technique  

NASA Technical Reports Server (NTRS)

As an example of microsystems fabricated by the LIGA-technique (x-ray lithography, electroplating and molding), three systems are described and characterized: a triaxial acceleration sensor system, a micro-optical switch, and a microsystem for the analysis of pollutants. The fabrication technologies are reviewed with respect to the key components of the three systems: an acceleration sensor, and electrostatic actuator, and a spectrometer made by the LIGA-technique. Aa micro-pump and micro-valve made by using micromachined tools for molding and optical fiber imaging are made possible by combining LIGA and anisotropic etching of silicon in a batch process. These examples show that the combination of technologies and components is the key to complex microsystems. The design of such microsystems will be facilitated is standardized interfaces are available.

Schulz, J.; Bade, K.; El-Kholi, A.; Hein, H.; Mohr, J.

1995-01-01

124

Wafer screening device and methods for wafer screening  

DOEpatents

Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

Sopori, Bhushan; Rupnowski, Przemyslaw

2014-07-15

125

REDUCED WAFER WARPAGE AND STRESS IN JSR DIELECTRIC FILMS  

Microsoft Academic Search

The addition of polymer dielectric films to silicon wafers is useful in producing stress reduction layers and interconnect structures for chip-scale packaging as well as 3D wafer stacks. The use of lower cure temperature materials offers several advantages including a lowered thermal budget on devices that are sensitive to electrical performance change with temperature. Unfortunately, enough stress remains from the

Robert L. Hubbard; Iftikhar Ahmad; Keith Hicks

126

1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics  

SciTech Connect

The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

Lorenz, Adam [1366 Technologies] [1366 Technologies

2013-08-30

127

Structured wafer for device processing  

DOEpatents

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Okandan, Murat; Nielson, Gregory N

2014-11-25

128

Structured wafer for device processing  

DOEpatents

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Okandan, Murat; Nielson, Gregory N

2014-05-20

129

A LIGA Fabricated Quadrupole Array for Mass Spectroscopy  

NASA Technical Reports Server (NTRS)

A linear array of nine quadrupoles was fabricated using the LIGA process. Pole heights ranging from 1 to 3 mm were fabricated using synchrotron X-ray exposures to form free standing polymethylmethacrylate (PMMA) molds into which copper, gold or nickel were electroplated.

Jackson, K.; Wiberg, D. V.; Hecht, M. H.; Orient, O. J.; Chutjian, A.; Yee, K.; Fuerstenau, S.; Brennen, R. A.; Hruby, J.; Bonivert, W.

1997-01-01

130

Etching Of Semiconductor Wafer Edges  

DOEpatents

A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

2003-12-09

131

Atomic scale fabrication of dangling bond structures on hydrogen passivated Si(0 0 1) wafers processed and nanopackaged in a clean room environment  

NASA Astrophysics Data System (ADS)

Specific surfaces allowing the ultra-high vacuum (UHV) creation of electronic interconnects and atomic nanostructures are required for the successful development of novel nanoscale electronic devices. Atomically flat and reconstructed Si(0 0 1):H surfaces are serious candidates for that role. In this work such Si:H surfaces were prepared in a cleanroom environment on 200 mm silicon wafers with a hydrogen bake and were subsequently bonded together to ensure the surface protection, and allow their transportation and storage for several months in air. Given the nature of the bonding, which was hydrophobic with weak van der Waals forces, we were then able to de-bond them in UHV. We show that the quality of the de-bonded Si:H surface enables the "at will" construction of sophisticated and complex dangling bond (DB) nanostructures by atomically precise scanning tunneling microscope (STM) tip induced desorption of hydrogen atoms. The DB structures created on slightly doped Si:H samples were characterized by scanning tunneling microscopy and spectroscopy (STM/STS) performed at 4 K. Our results demonstrate that DB nanostructures fabricated on UHV de-bonded Si(0 0 1):H wafers could be directly incorporated in future electronics as interconnects and parts of nanoscale logic circuits.

Kolmer, Marek; Godlewski, Szymon; Zuzak, Rafal; Wojtaszek, Mateusz; Rauer, Caroline; Thuaire, Aurélie; Hartmann, Jean-Michel; Moriceau, Hubert; Joachim, Christian; Szymonski, Marek

2014-01-01

132

Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter  

NASA Technical Reports Server (NTRS)

The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

Chen, C. P.; Leipold, M. H.

1984-01-01

133

Bondability of processed glass wafers  

NASA Astrophysics Data System (ADS)

The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness will result in small real area of contact, and therefore yield voids in the bonding interface. Usually, the root mean square roughness (RMS) or the mean roughness (Ra) are used as parameters to evaluate the wafer bondability. It was found from experience that for a bondable wafer surface the mean roughness must be in the subnanometer range, preferentially less than 0.5 nm. When the surface roughness exceeds a critical value, the wafers will not bond at all. However RMS and Ra were found to be not sufficient for evaluating the wafer bondability. Hence one tried to relate wafer bonding to the spatial spectrum of the wafer surface profile and indeed some empirical relations that have been found. The first, who proposed a theory on the problem of the closing gaps between contacted wafers was Stengl. This gap-closing theory was then further developed by Tong and Gosele. The elastomechanics theory was used to study the balance between the decrease of surface energy due to the bonding and the increase of elastic energy due to the distortion of the wafer. They considered the worst case by assuming that both wafers have a waviness, with a wavelength (lambda) and a height amplitude h, resulting in a gap height of 2h in a head to head position. This theory is simple and can be used in practice, for studying the formation of the voids, or for constructing design rules for the bonding of deliberately structured wafers. But it is insufficient to know what is the real area of contact in the wafer interface after contact at room temperature because the wafer surface always possesses a random distribution of the surface topography. Therefore Gui developed a continuous model on the influence of the surface roughness to wafer bonding, that is based on a statistical surface roughness model Pandraud demonstrated experimentally that direct bonding between processed glass wafers is possible. This result cannot be explained by considering the RMS value of the surfaces only, because the wafers used show a RMS value larger than 1 nm. Based on the approach exposed in reference six, a rigorous analysis of wafer bonding of these processed glass wafers is presented. We will discuss the relation between the bonding process and different waveguide technologies used for implementing optical waveguides into one or both glass wafers, and give examples of optical devices benefiting from such a bonding process.

Pandraud, Gregory; Gui, Cheng-Qun; Pigeon, Florent; Lambeck, Paul V.; Parriaux, Olivier M.

1999-09-01

134

Linear micromotors and spatial micromechanisms based on UV-LIGA  

Microsoft Academic Search

Spatial micromechanism employing compliant joints and electrothermal motors have been developed using a muitilayer UV-LIGA fabrication process. The electrothermal linear motors employ sawtooth impactors to provide a synchronized locking\\/pushing motion, allowing continuous motion without the need for a separate clamping actuator. Using electrothermal actuators, the bi-directional linear motors provide displacements of 2 mm with speeds up to 3 “\\/s and

W.-J. Cheng; D. L. DeVoe

2005-01-01

135

Design Study of Wafer Seals for Future Hypersonic Vehicles  

NASA Technical Reports Server (NTRS)

Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2005-01-01

136

Silicon cast wafer recrystallization for photovoltaic applications  

E-print Network

Current industry-standard methods of manufacturing silicon wafers for photovoltaic (PV) cells define the electrical properties of the wafer in a first step, and then the geometry of the wafer in a subsequent step. The ...

Hantsoo, Eerik T. (Eerik Torm)

2008-01-01

137

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism  

Microsoft Academic Search

With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP)

Chang-Chun Lee; Hsing-Chih Liu; Kuo-Ning Chiang

2007-01-01

138

Analysis of wafer stresses during millisecond thermal processing  

SciTech Connect

A flash lamp has been used to uniformly anneal large wafers with diameters approaching 100 mm. The equipment applies a pulse, with duration of 3-20 ms, resulting in large transient thermal gradients in the wafer. In this paper, we present separate models of the thermal reaction of this process and its effect upon the mechanical behavior, in order to predict stresses and shape changes, and to capture practical phenomenon. We further use the model to follow changes in the expected response consequent on altering process conditions, such as preheating and pulse duration, as well as exploring important issues associated with scaling to large wafer sizes. This work presents an initial description of the thermomechanical response of wafers to flash lamp annealing in the millisecond time regime and is therefore fundamental to the use of this technique in the fabrication of semiconductor devices.

Smith, M. P.; Seffen, K. A.; McMahon, R. A.; Voelskow, M.; Skorupa, W. [Department of Engineering, University of Cambridge, Trumpington Street, Cambridge CB2 1PZ (United Kingdom); Forschungszentrum Rossendorf, P.O. Box 510119, D-01314 Dresden (Germany)

2006-09-15

139

Enhanced adhesion for LIGA microfabrication by using a buffer layer  

DOEpatents

The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

Bajikar, Sateesh S. (San Jose, CA); De Carlo, Francesco (Darien, IL); Song, Joshua J. (Naperville, IL)

2001-01-01

140

Wafer level warpage modeling methodology and characterization of TSV wafers  

Microsoft Academic Search

Through-silicon-via (TSV) approach has been widely investigated recently for three-dimensional (3D) electronic packaging integration. TSV wafer warpage is one of the most challenges for successfully subsequent processes. In this work, wafer level warpage modeling methodology has been developed by finite element analysis (FEA) method using equivalent material model. The developed modeling methodology has been verified by numerical results and experiment

F. X. Che; H. Y. Li; Xiaowu Zhang; S. Gao; K. H. Teo

2011-01-01

141

MEMS Wafer-level Packaging Technology Using LTCC Wafer  

NASA Astrophysics Data System (ADS)

This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature co-fired ceramic (LTCC) wafer, in which multi-layer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of micro electro mechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (-40°C×30min/+125°C×30min) by diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection methods; The electrical connection is established by porous Au bumps, which are a part of Au vias exposed in wet-etched cavities on the LTCC wafer. 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

Mohri, Mamoru; Esashi, Masayoshi; Tanaka, Shuji

142

Manufacturing microcomponents for optical information technology using the LIGA technique  

NASA Astrophysics Data System (ADS)

Recently, splices and connectors for fibers ribbons, optical cross connects and especially planar waveguide devices have been fabricated via LIGA in combination with precision engineering techniques. LIGA combines high precision and mass production capability, necessary for products designed for applications in the telecom and datacom market. In this presentation the fabrication of three-level molding and embossing tools is presented, which have been used for the manufacturing of waveguide prestructures consisting of waveguide channels and bier-to-waveguide coupling grooves. The precision of the tools is better than 1 micrometers in all directions, which allows for simple passive pigtailing. A first product, a precision of the tool is better than 1 micrometers in all directions, which allows for simple passive pigtailing. A first product, sixfold array of 4 X 4 multimode star couplers has been realized. The molding behavior of PMMA and COC material has been tested and compared. Production and assembly was tested by fabricating a series of 300 star couplers. The average insertion los has been found better than 9dB, the uniformity better than 3dB, both measured at 830nm. THe device is designed for application in optical backplanes for high-speed computers.

Bauer, Hans-Dieter; Ehrfeld, Wolfgang; Hossfeld, Jens; Paatzsch, Thomas

1999-09-01

143

GEM-type detectors using LIGA and etchable glass technologies  

SciTech Connect

Gas electron multipliers (GEMS) have been made by a deep X-ray lithography technique (LIGA process) using synchrotron radiation on polymethylmethacrylate (PMMA) and by UV processes using a UV etchable glass. Gain, stability and rate capability for these detectors are described.The LIGA detectors described consist of PMMA sheets of various thicknesses, 125mm to 350mm, and have 150mm x 150mm square holes spaced with a pitch of 300mm. Thin copper electrodes are plated on the top and bottom surfaces using a Damascene method, followed by electroless plating of the copper onto a palladium-tin base layer. For various thicknesses of PMMA measurements have been made of absolute gain vs. voltage, time stability of gain, and rate capability. The operating gas mixture was usually Ar/CO2 (70/30) gas, but some tests were also done using P10 gas. We also made GEM-like detectors using the UV etchable glass called Foturan, patterned by exposure to UV light and subsequent etching. A few measurements using these detectors will be reported, including avalanche gain and time stability.

Ahn, S.K.; Kim, J.G.; Perez-Mendez, V.; Chang, S.; Jackson, K.H.; Kadyk, J.A.; Wenzel, W.A.; Cho, G.

2001-11-02

144

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.  

PubMed

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

2014-08-15

145

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers  

NASA Astrophysics Data System (ADS)

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

146

System for slicing wafers  

NASA Technical Reports Server (NTRS)

A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

1982-01-01

147

LIGA-based microsystem manufacturing:the electrochemistry of through-mold depostion and material properties.  

SciTech Connect

The report presented below is to appear in ''Electrochemistry at the Nanoscale'', Patrik Schmuki, Ed. Springer-Verlag, (ca. 2005). The history of the LIGA process, used for fabricating dimensional precise structures for microsystem applications, is briefly reviewed, as are the basic elements of the technology. The principal focus however, is on the unique aspects of the electrochemistry of LIGA through-mask metal deposition and the generation of the fine and uniform microstructures necessary to ensure proper functionality of LIGA components. We draw from both previously published work by external researchers in the field as well as from published and unpublished studies from within Sandia.

Kelly, James J. (Sandia National Laboratories, Livermore, CA); Goods, Steven Howard (Sandia National Laboratories, Livermore, CA)

2005-06-01

148

Study of thinned Si wafer warpage in 3D stacked wafers  

Microsoft Academic Search

3D (three-dimensional) wafer stacking technology has been developed extensively recently. One of the many technical challenges in 3D stacked wafers, and one of the most important, is wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within wafer (WIW) uniformity and even electrical failure. In this study,

Youngrae Kim; Sung-Keun Kang; Sarah Eunkyung Kim

2010-01-01

149

Development of Megasonic cleaning for silicon wafers. Final report  

SciTech Connect

The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

Mayer, A.

1980-09-01

150

Computational Modeling in Plasma Processing for 300 mm Wafers  

NASA Technical Reports Server (NTRS)

Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

1997-01-01

151

A dielectrophoretic chip packaged at wafer level  

Microsoft Academic Search

The paper presents a dielectrophoretic chip, fully enclosed, with bulk silicon electrodes fabricated using wafer-to-wafer\\u000a bonding techniques and packaged at the wafer level. The silicon electrodes, which are bonded to two glass dies, define in\\u000a the same time the walls of the microfluidic channel. The device is fabricated from a silicon wafer that is bonded (at wafer\\u000a level) anodically and

Ciprian Iliescu; Francis E. H. Tay; Guolin Xu; Li Ming Yu; Victor Samper

2006-01-01

152

Low-temperature silicon wafer-to-wafer bonding using gold at eutectic temperature  

Microsoft Academic Search

Micromechanical smart sensor and actuator systems of high complexity bemme commercially viable when realized as a multi-wafer device in which the mechanical functions are distributed over different wafers and one of the wafers is dedicated to contain the readout circuits. The individually-processed wafers can be assembled using wafer-to-wafer bonding and can be combined to one single functional electro-mechanical unit using

K. D. Wise

1994-01-01

153

Wafer bonding of 75 mm diameter GaP to AlGaInP-GaP light-emitting diode wafers  

Microsoft Academic Search

The AlGaInP\\/GaP wafer-bonded transparent-substrate (TS) light-emitting diodes (LEDs) have been shown to exhibit luminous efficiencies\\u000a exceeding many conventional lightning sources including 60 W incandescent sources. This paper will demonstrate the feasibility\\u000a of scaling wafer bonding technology to 75 mm diameter wafers and some of the unique challenges associated with this scaling.\\u000a The quality and uniformity of bonding were characterized via

I.-H. Tan; D. A. Vanderwater; J.-W. Huang; G. E. Hofler; F. A. Kish; E. I. Chen; T. D. Ostentowski

2000-01-01

154

Cloning and Molecular Characterization of an Immunogenic LigA Protein of Leptospira interrogans  

Microsoft Academic Search

A clone expressing a novel immunoreactive leptospiral immunoglobulin-like protein A of 130 kDa (LigA) from Leptospira interrogans serovar pomona type kennewicki was isolated by screening a genomic DNA library with serum from a mare that had recently aborted due to leptospiral infection. LigA is encoded by an open reading frame of 3,675 bp, and the deduced amino acid sequence consists

Raghavan U. M. Palaniappan; Yung-Fu Chang; S. S. D. Jusuf; S. Artiushin; John F. Timoney; Sean P. McDonough; Steve C. Barr; Thomas J. Divers; Kenneth W. Simpson; Patrick L. McDonough; Hussni O. Mohammed

2002-01-01

155

Injection-moulded fibre ribbon connectors for parallel optical links fabricated by the LIGA technique  

Microsoft Academic Search

Using the LIGA technique prototypes of twelve-fibre-wide ribbon connector ferrules have been developed that provide low-loss physical-contact multimode connections for parallel interfaces. The ferrules are injection moulded and the modular mould insert has been fabricated by means of microtechnology (LIGA) and electro-discharge machining. After assembling, mated couples of these ferrules show average insertion loss values of 0.35 dB and have

Karlheinz Dunkel; Hans-Dieter Bauer; Wolfgang Ehrfeld; Jens Hoßfeld; Lutz Weber; Günter Hörcher; Gottfried Müller

1998-01-01

156

Two-dimensional modeling of nickel electrodeposition in LIGA microfabrication.  

SciTech Connect

Two-dimensional processes of nickel electrodeposition in LIGA microfabrication were modeled using the finite-element method and a fully coupled implicit solution scheme via Newtons technique. Species concentrations, electrolyte potential, flow field, and positions of the moving deposition surfaces were computed by solving the species-mass, charge, and momentum conservation equations as well as pseudo-solid mesh-motion equations that employ an arbitrary Lagrangian-Eulerian (ALE) formulation. Coupling this ALE approach with repeated re-meshing and re-mapping makes it possible to track the entire transient deposition processes from start of deposition until the trenches are filled, thus enabling the computation of local current densities that influence the microstructure and functional/mechanical properties of the deposit.

Evans, Gregory Herbert (Sandia National Laboratories, Livermore, CA); Chen, Ken Shuang

2003-07-01

157

Wafer characteristics via reflectometry and wafer processing apparatus and method  

DOEpatents

An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

Sopori, Bhushan L. (Denver, CO)

2007-07-03

158

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Vosen, S.R.

1999-07-27

159

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

Vosen, Steven R. (Berkeley, CA)

1999-01-01

160

Ultrathin wafer level chip size package  

Microsoft Academic Search

The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant

Avner Badihi

2000-01-01

161

Silicon Wafer Processing Dr. Seth P. Bates  

E-print Network

Silicon Wafer Processing Dr. Seth P. Bates Applied Materials Summer, 2000 Objective To provide from blank silicon wafers. Goals The Transfer Plan provides a curriculum covering the process of manufacturing integrated circuits from the silicon wafer blanks, using the equipment manufactured by Applied

Colton, Jonathan S.

162

Dicing of optical wafer level packages  

Microsoft Academic Search

The optical wafer level packaging, developed by Schott Advanced Packaging, consists of a Silicon wafer, comprising the optical sensors, which is bonded to a glass wafer in the very first process step to protect the sensors. The package utilizes a via through contact through the Silicon by contacting the bond pads of the image sensor from the backside. By this

Dennis Tangaha; Florian Bieck

2006-01-01

163

NREL Core Program; Session: Wafer Silicon (Presentation)  

SciTech Connect

This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

Wang, Q.

2008-04-01

164

Stress analysis of stacked Si wafer in 3D WLP  

Microsoft Academic Search

In 3D wafer-stacking technology, one of the major manufacturing issues is wafer warpage because it causes process and product failures, such as delamination, cracking, mechanical stresses, and even electrical failure. In this study, the wafer warpage and local strain of thinned Si wafers in a wafer stack were investigated. A blanket Cu film was deposited on a Si wafer by

Ki-Ho Maeng; Youngrae Kim; Sung-Geun Kang; Sung-Dong Kim; Sarah Eunkyung Kim

2011-01-01

165

Assessment of thinned Si wafer warpage in 3D stacked wafers  

Microsoft Academic Search

3D (three-dimensional) wafer stacking technology has been developed extensively recently. Among many technical challenges in 3D stacked wafers the wafer warpage is one of the important processing issues to be resolved because the wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, WIW (within wafer) non-uniformity and electrical failure.

Youngrae Kim; Sung-Geun Kang; Eun-kyung Kim

2009-01-01

166

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress  

NASA Astrophysics Data System (ADS)

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Brunner, Timothy A.; Menon, Vinayan C.; Wong, Cheuk Wun; Gluschenkov, Oleg; Belyansky, Michael P.; Felix, Nelson M.; Ausschnitt, Christopher P.; Vukkadala, Pradeep; Veeraraghavan, Sathish; Sinha, Jaydeep K.

2013-10-01

167

Low-temperature hydrophobic silicon wafer bonding  

NASA Astrophysics Data System (ADS)

By introducing a nanometer-scale H trapping defective silicon layer on bonding surfaces, the bonding surface energy of bonded oxide-free, HF dipped, hydrophobic silicon wafers can reach a silicon fracture surface energy of 2500 mJ/m2 at 300 to 400 °C compared with 700 °C conventionally achieved. Adding boron atoms on bonding surfaces can reduce the surface hydrogen release temperature but would not increase the bonding energy unless a defective layer is also formed. This indicates that, in order to achieve high bonding energy, the released hydrogen must be removed from the bonding interface. Many prebonding treatments are available for low-temperature hydrophobic wafer bonding including the formation of an amorphous silicon layer by As+ implantation, by B2H6 or Ar plasma treatment, or by sputter deposition, followed by an HF dip and room temperature bonding in air. The interface amorphous layer may be recrystallized by annealing at elevated temperatures, e.g., at 450 °C for As+-implanted samples.

Tong, Q.-Y.; Gan, Q.; Hudson, G.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

2003-12-01

168

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Astrophysics Data System (ADS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-02-01

169

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Technical Reports Server (NTRS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

170

An aluminum resist substrate for microfabrication by LIGA.  

SciTech Connect

Resist substrates used in the LIGA process must provide high initial bond strength between the substrate and resist, little degradation of the bond strength during x-ray exposure, acceptable undercut rates during development, and a surface enabling good electrodeposition of metals. Additionally, they should produce little fluorescence radiation and give small secondary doses in bright regions of the resist at the substrate interface. To develop a new substrate satisfying all these requirements, we have investigated secondary resist doses due to electrons and fluorescence, resist adhesion before exposure, loss of fine features during extended development, and the nucleation and adhesion of electrodeposits for various substrate materials. The result of these studies is a new anodized aluminum substrate and accompanying methods for resist bonding and electrodeposition. We demonstrate successful use of this substrate through all process steps and establish its capabilities via the fabrication of isolated resist features down to 6 {micro}m, feature aspect ratios up to 280 and electroformed nickel structures at heights of 190 to 1400 {micro}m. The minimum mask absorber thickness required for this new substrate ranges from 7 to 15 {micro}m depending on the resist thickness.

Kelly, James J.; Boehme, Dale R.; Hauck, Cheryl A. (Lawrence Berkeley National Laboratory, Berkeley, CA); Yang, Chu-Yeu Peter; Hunter, Luke L.; Griffiths, Stewart K.; McLean, Dorrance E.; Aigeldinger, Georg; Hekmaty, Michelle A.; Hachman, John T.; Losey, Matthew W.; Skala, Dawn M.; Korellis, John S.; Friedmann, Thomas Aquinas (Sandia National Laboratories, Albuquerque, NM); Yang, Nancy Y. C.; Lu, Wei-Yang

2005-04-01

171

The LIGA technique-A novel concept for microstructures and the combination with Si-technologies by injection molding  

Microsoft Academic Search

The LIGA technique originally developed to fabricate separation nozzles for the enrichment of uranium has been expanded into a universal technology for the fabrication of microstructures with high aspect ratio and free lateral shaping. The LIGA process consists of three basic process steps: deep-etch lithography by means of synchrotron radiation, electroforming, and plastic molding. The choice of materials ranges from

W. Menz; W. Bacher; M. Harmening; A. Michel

1991-01-01

172

Wafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology  

Microsoft Academic Search

High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components (e.g. large inductors) in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate large RF passives with a spacing of >150 ?m to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form

P. M. Mendes; S. Sinaga; A. Polyakov; M. Bartek; J. N. Burghartz; J. H. Correia

2004-01-01

173

Full chip implant correction with wafer topography OPC modeling in 2x nm bulk technologies  

NASA Astrophysics Data System (ADS)

Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted overexposure by wafer topography with technology node downscaling evolution [1], [2]. Starting from 2xnm technology nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer topography which can cause drastic pattern degradation [2], [3]. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a consequence, computational lithography solutions are currently under development in order to correct wafer topographical effects on mask [3]. For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer stack. In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC flow for chip scale mask correction is presented with quality and run time penalty analysis.

Michel, J.-C.; Le Denmat, J.-C.; Sungauer, E.; Robert, F.; Yesilada, E.; Armeanu, A.-M.; Entradas, J.; Sturtevant, J. L.; Do, T.; Granik, Y.

2013-09-01

174

Wafer bonding for three dimensional (3D) integration  

NASA Astrophysics Data System (ADS)

Wafer scale 3D integration is recognized as an emerging technology to increase the performance of ICs. When bonding with processed ICs, the bonding process must be compatible with IC back-end processing. The fraction of bonded area was examined by optical inspection and BCB was selected as the baseline glue after achieving reproducible void-free bonding. Bond strength at the glue interface of bonded wafers was quantified by four-point bending. Using four point bending, the following effects of BCB glue on the bonding integrity were evaluated; (1) employment of adhesion promoter, (2) BCB glue thickness and (3) material stack. When the adhesion promoter is used, bond strength increases at both BCB bonds of 2.6 mum and 0.4 mum. These results also demonstrate that BCB glue thickness affects the bond strength at the glue interface with thicker glue layers corresponding to higher bond strength. The decrease in bond strength observed for thin BCB is due to a decrease of plastic dissipation energy, Gplastic, which is proportional to BCB thickness. In both bonded wafer pairs that include a PECVD oxide deposited silicon wafer and a glass wafer, bond strengths are linearly proportional to BCB thickness. With these results, the relationship between Gplastic , and bond breaking energy, Gtip, and BCB thickness, t is observed to be Gplastic ? 0.3 · Gtip · t. The effects of thermal cycling on bond strength and residual stress at the interface between BCB and a PECVD oxide, and the thermal stability of BCB were evaluated by four point bending and wafer curvature measurements. Stress relaxation of the PECVD oxide layer during thermal cycling leads to a decrease in the deformation energy due to residual stress, G residual, and to an increase in bond strength. In thermal cycling performed at temperatures of 350 and 400°C, it is observed that the relaxation of residual stress occurs predominantly during the first thermal cycle. Conclusively, the BCB process for wafer-to-wafer bonding applications is stabilized after four cycles at a temperature of 400°C. Thermal cycling performed at a temperature 450°C leads to cohesive failure within the BCB layer with low bond strength (<0.5 J/m2).

Kwon, Yongchai

2003-10-01

175

The influence of wafer dimensions on the contact wave velocity in silicon wafer bonding  

NASA Astrophysics Data System (ADS)

The contact wave velocity in silicon wafer bonding is experimentally found to decrease with wafer thickness and to be only weakly dependent on wafer diameter. Wafers of different thicknesses ranging from 270 to 5000 ?m, were dipped in HF:H2O before bonding to give the surfaces hydrophobic properties. A model based on energy conservation can explain the main characteristics of the experimental results. The contact wave velocity is determined by the amount of energy available as kinetic energy for the entrapped gas in the gap between the wafers. By increasing wafer thickness, the elastic energy stored in the material is increased, and the contact wave velocity is decreased.

Bengtsson, Stefan; Ljungberg, Karin; Vedde, Jan

1996-11-01

176

A 3-D wafer level hermetical packaging for MEMS  

Microsoft Academic Search

In this paper, a 3D wafer-level hermetical packaging solution for micro-electromechanical-system (MEMS) is presented. The MEMS wafer is sandwiched between a top glass wafer and a bottom Si substrate wafer. With the assistance of a gold intermediate layer, the bottom Si wafer is hermetically sealed to the MEMS wafer with 3D electric feed-through connecting the metal pads on MEMS wafer

Y F. Jinl; J. Wei; G. J. Qil; Z. F. Wang; P. C. Lim; C. K. Wong

2004-01-01

177

MIT Microsystems Technology LaboratoriesMIT Microsystems Technology LaboratoriesDavid White, Duane Boning and Aaron GowerDavid White, Duane Boning and Aaron Gower Characterization of Endpoint and Wafer LevelCharacterization of Endpoint and Wafer Level  

E-print Network

30 2814 1 Pad Positions qq Using a IR camera to monitor the CMP processUsing a IR camera to monitor CMP IR image of a copper CMP polishIR image of a copper CMP polish angle Table/Pad IR Camera ViewingOverview: Wafer Scale Endpoint Uniformity ·· Spatial Dependencies Between the Pad & WaferSpatial Dependencies

Boning, Duane S.

178

MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads  

DOEpatents

In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

2013-12-03

179

Wafer level reliability for high-performance VLSI design  

NASA Technical Reports Server (NTRS)

As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

Root, Bryan J.; Seefeldt, James D.

1987-01-01

180

Effect of Wafer Bow and Etch Patterns in Direct Wafer Bonding  

E-print Network

Direct wafer bonding has been identified as an en-abling technology for microelectromechanical systems (MEMS). As the complexity of devices increase and the bonding of multiple patterned wafers is required, there is a need ...

Spearing, S. Mark

181

Mechanics of the pad-abrasive-wafer contact in chemical mechanical polishing  

NASA Astrophysics Data System (ADS)

In chemical mechanical polishing (CMP), a rigid wafer is forced on a rough, elastomeric polishing pad, while a slurry containing abrasive particles flows through the interface. The applied pressure on the wafer is carried partially by the 2-body pad-wafer contact (direct contact) and partially by the 3-body contact of pad, wafer and abrasive particles ( particle contact). The fraction of the applied pressure carried by particle contacts is an important factor affecting the material removal rate (MRR) as the majority of the material is removed by the abrasive particles trapped between the pad asperities and the wafer. In this thesis, the contact of a rough, deformable pad and a smooth, rigid wafer in the presence of rigid abrasive particles at the contact interface is investigated by using contact mechanics and finite element (FE) modeling. The interactions between the pad, the wafer and the abrasive particles are modeled at different scales of contact, starting from particle level interactions, and gradually expanding the contact scale to the multi-asperity contact of pad and wafer. The effect of surface forces consisting of van der Waals and electrical double layer forces acting between the wafer and the abrasive particles are also investigated in this work. The wear rate due to each abrasive particle is calculated based on the wafer-abrasive particle contact force, and by considering adhesive and abrasive wear mechanisms. A passivated layer on the wafer surface with a hardness and thickness determined by the chemical effects is modeled, in order to characterize the effect of chemical reactions between slurry and wafer on the MRR. The model provides accurate predictions for the MRR as a function of pad related parameters; pad elastic modulus, pad porosity and pad topography, particle related parameters; particle size and concentration, and slurry related parameters; slurry pH, thickness and hardness of the passivated surface layer of wafer. A good qualitative agreement between the model and the experiments is found for the variation of the MRR with respect to these parameters. Furthermore, closed form equations are derived in order to optimize the CMP parameters for maximizing the material removal efficiency, which is a measure of the ability of pad to transmit the applied pressure on the abrasive particles. The optimization of the CMP parameters described in this thesis may be particularly important for the low-pressure CMP of ultra-low-k (ULK) dielectric materials, where it is difficult to achieve acceptable MRR without compromising the porous structure of ULK materials.

Bozkaya, Dincer

2009-12-01

182

Characterizing stress in ultrathin silicon wafers  

NASA Astrophysics Data System (ADS)

The aim of this letter is to calculate the mechanical grinding induced bow and stress in ultrathin silicon wafers. The reverse leakage current of a p-n junction diode fabricated on a 4in. silicon wafer was measured for wafers thinned to various thicknesses. A correlation with the residual stress was obtained through band gap narrowing effect. The analytical results were compared with experimental bow measurements using a laser profiler. The bow in 50?m thick wafer was found to be less than 2mm using the current grinding process.

Paul, Indrajit; Majeed, Bivragh; Razeeb, Kafil M.; Barton, John

2006-08-01

183

Performance Evaluations of Ceramic Wafer Seals  

NASA Technical Reports Server (NTRS)

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

184

Wafer level reliability assessment of stress-induced voiding  

Microsoft Academic Search

As device technology advances toward submicron geometry, the linewidth of VLSI metallization interconnects continues to scale down and stress-induced migration becomes an increasingly important issue. Wafer level stress-induced migration testing of metallization was introduced as a technique for obtaining greater levels of quality assurance with a shorter feedback time at an affordable cost. Slit-like voids are typically formed causing catastrophic

H. H. Hoang; R. B. MacNaughton; Y. S. Lin; M. Zamanian; F. S. Chen; E. Carpenter; L. Tullos; S. Tso; F. T. Liou

1991-01-01

185

A method to maintain wafer alignment precision during adhesive wafer bonding  

Microsoft Academic Search

In this paper, a novel method is presented that prevents aligned wafers from shifting relative to each other during adhesive bonding. The attainable pre-bond wafer alignment accuracy on commercially available bonding equipment is typically 2–5?m. However, in adhesive wafer bonding, the intermediate adhesive material must exist in a liquid-like state to wet the wafer surfaces and thereby achieve bonding. When

Frank Niklaus; Peter Enoksson; Edvard Kälvesten; Göran Stemme

2003-01-01

186

Techniques for the evaluation of outgassing from polymeric wafer pods  

Microsoft Academic Search

In recent years there has been increasing interest in using wafer-level isolation environments or pods (microenvironments) to provide a more controllable, cleaner wafer environment during wafer processing. It has been shown that pods can be effective in reducing the amount of particulate contamination on wafers during manufacturing. However, there have also been studies that indicate that pods and wafer boxes

D. C. McIntyre; A. Liang; S. M. Thornberg; S. F. Bender; R. D. Lujan; R. S. Blewer; W. D. Bowers

1994-01-01

187

In-situ wafer curvature measurements during rapid thermal annealing of Si(100) wafers  

Microsoft Academic Search

During Rapid Thermal Annealing (RTA) of silicon wafers a nonuniform temperature distribution may exist across the wafer caused by a variation of the radiation flux. Due to the thermal gradient, differences in thermal expansion introduce thermal stresses in the material. In a modified RTA system the deformation originating from the thermal stress was monitored by measurement of the wafer curvature

J. Hans F. Jongste; T. G. Oosterlaken; G. C. Bart; G. C. Janssen; Sybrand Radelaar

1995-01-01

188

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs  

Microsoft Academic Search

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and\\/or burn-in parts in wafer form. After the parts are

Eugene M. Chow; David K. Fork; Christopher L. Chua; Koenraad Van Schuylenbergh; Thomas Hantschel

2009-01-01

189

Rapid replication of polymeric and metallic high aspect ratio microstructures using PDMS and LIGA technology  

E-print Network

and standard LIGA processes. A high aspect ratio (HAR) metallic micromold insert, featuring a variety of test of polymeric HARMs, replicated PDMS HARMS were coated with a metallic sacrificial layer and electroplated in actuator sys- tems, higher sensitivity in sensor applications by virtue of large mass, and large magnetic

Lee, Jeong-Bong

190

Stress Voiding During Wafer Processing  

SciTech Connect

Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

Yost, F.G.

1999-03-01

191

Total x-ray power measurements in the Sandia LIGA program.  

SciTech Connect

Total X-ray power measurements using aluminum block calorimetry and other techniques were made at LIGA X-ray scanner synchrotron beamlines located at both the Advanced Light Source (ALS) and the Advanced Photon Source (APS). This block calorimetry work was initially performed on the LIGA beamline 3.3.1 of the ALS to provide experimental checks of predictions of the LEX-D (LIGA Exposure- Development) code for LIGA X-ray exposures, version 7.56, the version of the code in use at the time calorimetry was done. These experiments showed that it was necessary to use bend magnet field strengths and electron storage ring energies different from the default values originally in the code in order to obtain good agreement between experiment and theory. The results indicated that agreement between LEX-D predictions and experiment could be as good as 5% only if (1) more accurate values of the ring energies, (2) local values of the magnet field at the beamline source point, and (3) the NIST database for X-ray/materials interactions were used as code inputs. These local magnetic field value and accurate ring energies, together with NIST database, are now defaults in the newest release of LEX-D, version 7.61. Three dimensional simulations of the temperature distributions in the aluminum calorimeter block for a typical ALS power measurement were made with the ABAQUS code and found to be in good agreement with the experimental temperature data. As an application of the block calorimetry technique, the X-ray power exiting the mirror in place at a LIGA scanner located at the APS beamline 10 BM was measured with a calorimeter similar to the one used at the ALS. The overall results at the APS demonstrated the utility of calorimetry in helping to characterize the total X-ray power in LIGA beamlines. In addition to the block calorimetry work at the ALS and APS, a preliminary comparison of the use of heat flux sensors, photodiodes and modified beam calorimeters as total X-ray power monitors was made at the ALS, beamline 3.3.1. This work showed that a modification of a commercially available, heat flux sensor could result in a simple, direct reading beam power meter that could be a useful for monitoring total X-ray power in Sandia's LIGA exposure stations at the ALS, APS and Stanford Synchrotron Radiation Laboratory (SSRL).

Malinowski, Michael E. (Sandia National Laboratories, Livermore, CA); Ting, Aili (Sandia National Laboratories, Livermore, CA)

2005-08-01

192

Wafer-Level ANA Calibrations at NIST  

Microsoft Academic Search

The National Institute of Standards and Technology has begun a program supporting on-wafer scattering parameter measurements. In contrast to many previous NIST endeavors, this program seeks to transfer methodology into industrial measurement laboratories. The subject of this paper is the development of calibration techniques and algorithms, rather than physical standards, for the measurement of on-wafer scattering parameters. In particular, we

Roger Marks; Kurt Phillips

1989-01-01

193

The evolution of silicon wafer cleaning technology  

Microsoft Academic Search

The purity of wafer surfaces is an essential requisite for the successful fabrication of VLSI and ULSI silicon circuits. Wafer cleaning chemistry has remained essentially unchanged in the past 25 years and is based on hot alkaline and acidic hydrogen peroxide solutions, a process known as RCA Standard Clean. This is still the primary method used in the industry. What

Werner Kern

1990-01-01

194

Atmospheric downstream plasma etching of Si wafers  

Microsoft Academic Search

A dry etch technology for processing Si wafers using an atmospheric downstream plasma (ADP) source is described. Application of ADP etching for backside damage removal after grinding and wafer thinning is discussed. ADP is an inert gas thermal plasma generated by DC discharge at atmospheric pressure in the process chamber. The reactant (freon) is injected into the plasma stream outside

Oleg Siniaguine

1998-01-01

195

Wafer level vacuum packaging of MEMS sensors  

Microsoft Academic Search

A process has been developed for wafer level vacuum packaging MEMS sensors, which are fabricated from etched, single crystal silicon structures, anodically bonded to metallized glass wafers. Key objectives of the process design were to minimize the number of changes to sensor fabrication, insure a high level of vacuum integrity, and flexible enough to accommodate a wide range of sensor

Thomas F. Marinis; Joseph W. Soucy; James G. Lawrence; Megan M. Owens

2005-01-01

196

Structural Characterization of Processed Silicon Wafers  

Microsoft Academic Search

Two techniques, chemical etching and X-ray diffraction, for the characterization of process-induced defects in silicon wafers are illustrated. The types of etchants used to reveal various defects are reviewed. The use of a Lang camera for the measurements Of bulk defects and mechanical stress in silicon wafers is presented. Examples are given demonstrating the use of these two techniques: to

PETER L. FEJES; H. MING LIAW; F. d'Aragona

1983-01-01

197

Methane production using resin-wafer electrodeionization  

DOEpatents

The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

2014-03-25

198

Instrumentation for neutralization of wafer charging  

NASA Astrophysics Data System (ADS)

A detailed analysis of the physics of wafer charging, its effects on the resulting ion trajectories and energy distributions is presented. A general review of present wafer charging diagnostic instruments with emphasis on a new optical technique based upon the ion-induced photoresist damage mechanism is included. The use of this new technique to adjust the ion implanter's flood gun parameters so as to minimize wafer charging is illustrated. Experimental and theoretical results of the use of photon radiation (UV and X-ray) to induce photoconductivity as a mechanism of wafer neutralization during ion implantation are given. Special emphasis is placed on the use of a pulsed, high power, plasma X-ray source as a means of obtaining whole wafer neutralization.

Cheng, J. C.; Tripp, G. R.; Glaze, J. A.; Golin, J. R.

1985-01-01

199

Yield-driven multi-project reticle design and wafer dicing  

NASA Astrophysics Data System (ADS)

The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies has lead to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such low volume designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle design and wafer dicing introduce complexities not encountered in typical, single-project wafers. Recent works on wafer dicing adopt some assumptions to reduce the problem complexity. Although using one or more assumptions makes the problem solvable, the feasibility or performance of the solutions may be degraded. Also, the delay cost associated with schedule alignment was ignored in all previous works. In this paper we propose a general MPW flow including four main steps: (1) schedule-aware project partitioning (2) multi-project reticle floorplanning, (3) wafer shot-map definition, and (4) wafer dicing plan definition. Our project partitioner provides the best trade-off between the mask cost and delay cost. Our reticle floorplaner can automatically clone a design to better fit given production volumes. The round wafer shot-map definition step allows extracting functional dies from partially printed reticle images. Finally, our dicing planner allows multiple side-to-side dicing plans for different wafers and image rows/columns within a wafer. Experiments on industry testcases show that our methods outperform significantly not only previous methods in the literature, but also reticle floorplans manually designed by experienced engineers.

Kahng, Andrew B.; Mandoiu, Ion; Xu, Xu; Zelikovsky, Alex

2005-11-01

200

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing  

NASA Technical Reports Server (NTRS)

Several aspects of silicon wafer surface texturizing were studied. A low cost cleaning method that utilizes recycled Freon in an ultrasonic vapor degreaser to remove organic and inorganic contaminants from the surface of silicon wafers as received from silicon suppliers was investigated. The use of clean dry air and high throughout wafer batch drying techniques was shown to lower the cost of wafer drying. A two stage texturizing process was examined for suitability in large scale production. Also, an in-depth gettering study with the two stage texturizing process was performed for the enhancement of solar cell efficiency, minimization of current versus voltage curve dispersion, and improvement in process reproducibility. The 10% efficiency improvement goal was exceeded for the near term implementation of flat plate photovoltaic cost reduction.

Jones, G. T.; Rhee, S. S.

1979-01-01

201

3D structure design and reliability analysis of wafer level package with bubble-like stress buffer layer  

Microsoft Academic Search

With the present trend of multi-function and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLP) and chip scale packages (CSP) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP)

Chang-Chun Lee; Hsin-Chih Liu; Ming-Chih Yew; Kuo-Ning Chiang

2004-01-01

202

Development of megasonic cleaning for silicon wafers  

NASA Technical Reports Server (NTRS)

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Mayer, A.

1980-01-01

203

Metal Enhanced Fluorescence on Silicon Wafer Substrates  

PubMed Central

We report on the fluorescence enhancement induced by silver island film (SIF) deposited on a silicon wafer. The model immunoassay was studied on silvered and unsilvered wafers. The fluorescence brightness of Rhodamine Red X increased about 300% on the SIF, while the lifetime was reduced by several fold and the photostability increased substantially. We discuss potential uses of silicon wafer substrates in multiplex assays in which the fluorescence is enhanced due to the SIF, and the multiplexing is achieved by using micro transponders. PMID:19137060

Gryczynski, I.; Matveeva, E.G.; Sarkar, P.; Bharill, S.; Borejdo, J.; Mandecki, W.; Akopova, I.; Gryczynski, Z.

2008-01-01

204

Diamond-like nanocomposite coatings for LIGA-fabricated nickel alloy parts.  

SciTech Connect

A commercial plasma enhanced chemical vapor deposition (PECVD) technique with planetary substrate rotation was used to apply a thin (200-400 nm thick) conformal diamond-like carbon (DLC) coating (known as a diamond-like nanocomposite (DLN)) on LIGA fabricated Ni-Mn alloy parts. The PECVD technique is known to overcome the drawbacks associated with the line-of-sight nature of physical vapor deposition (PVD) and substrate heating inherent with traditional chemical vapor deposition (CVD). The purpose of the present study is to characterize the coverage, adhesion, and tribological (friction and wear) behavior of DLN coatings applied to planar and sidewall surfaces of small featured LIGA Ni-Mn fabricated parts, e.g. 280 {micro}m thick sidewalls. Friction and wear tests were performed in dry nitrogen, dry air, and air with 50% RH at Hertzian contact pressures ranging from 0.3 to 0.6 GPa. The friction coefficient of bare Ni-Mn alloy was determined to be 0.9. In contrast, low friction coefficients ({approx}0.02 in dry nitrogen and {approx}0.2 in 50% RH air) and minimal amount of wear were exhibited for the DLN coated LIGA Ni-Mn alloy parts and test coupons. This behavior was due to the ability of the coating to transfer to the rubbing counterface providing low interfacial shear at the sliding contact; resultantly, coating one surface was adequate for low friction and wear. In addition, a 30 nm thick titanium bond layer was determined to be necessary for good adhesion of DLN coating to Ni-Mn alloy substrates. Raman spectroscopy and cross-sectional SEM with energy dispersive x-ray analysis revealed that the DLN coatings deposited by the PECVD with planetary substrate rotation covered both the planar and sidewall surfaces of LIGA fabricated parts, as well as narrow holes of 300 {micro}m (0.012 inch) diameter.

Prasad, Somuri V.; Scharf, Thomas W.

2005-03-01

205

LigaSure meets endobronchial valve in a case of lung cancer with pneumoconiosis  

PubMed Central

Resection of lung cancer associated with pneumoconiosis may be difficult since fibrosis limits the exposure of hilum, and the use of stapler; yet, surgery may be complicated by persistent air leaks due to the underlying disease. In this setting, LigaSure was used to perform the tumor resection, and the postoperative treatment of air leaks in the same patient was treated with placement of endobronchial valves.

Fiorelli, Alfonso; Accardo, Marina; Vicidomini, Giovanni

2013-01-01

206

Experimental characterization of LIGA fabricated 0.22 THz TWT circuits  

Microsoft Academic Search

In this paper we report precision MEMS Fabrication using novel LIGA technique for 0.22 THz micro-metallic staggered double-vane TWT circuits. For this high aspect ratio structure negative tone photo-resist KMPR was used. The entire fabrication process starting from spin coating, UV-lithography, electroforming and mold removal processing was fully characterized. Finally, the high tolerance TWT structure with smoothness (50 - 80

Anisullah Baig; Diana Gamzina; Micheal Johnson; Calvin W. Domier; Alexander Spear; Larry R. Barnett; Neville C. Luhmann; Young-Min Shin

2011-01-01

207

Everything Wafers: A Guide to Semiconductor Substrates  

NSDL National Science Digital Library

This website contains information on characteristics and properties of semiconductor wafers. Topics include types of substrates, process dependent characteristics, properties of semiconductors, cleaving, etching and other topics, along with related terms and links.

208

Modelling deformation and fracture in confectionery wafers  

NASA Astrophysics Data System (ADS)

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

2015-01-01

209

Wafer Backside Anisotropic Wet Etching of Silicon  

NSDL National Science Digital Library

This animation, created by Southwest Center for Microsystems Education (SCME), illustrates how the "wafer backside anisotropic wet etching of silicon is used to form the pressure sensor chamber." Further information and resources can be found on the SCME website.

210

Parameter Modeling for Wafer Probe Test  

Microsoft Academic Search

This paper presents the simulation of parameters for wafer probe test by finite-element modeling with consideration of probe over-travel (OT) distance, scrub, contact friction coefficient, probe tip shapes, and diameter. The goal is to minimize the stresses in the device under the bond pad and eliminate wafer failure in probe test. In the probe test modeling, a nonlinear finite-element contact

Yong Liu; Timwah Luk; Scott Irving

2009-01-01

211

Hydrophilic low-temperature direct wafer bonding  

NASA Astrophysics Data System (ADS)

The sealing mechanism of silicon bonding interfaces is reported as a function of annealing temperature. Details of the structural and chemical interface evolution are obtained for hydrophilic silicon/silicon and silicon/silicon dioxide wafer bonding, using x-ray reflectivity and infrared spectroscopy. A two-step mechanism is demonstrated: first a partial sealing of the interface driven by cross-wafer silanol bond condensation and second a water evacuation via oxide formation at the silicon oxide interface.

Ventosa, C.; Rieutord, F.; Libralesso, L.; Morales, C.; Fournel, F.; Moriceau, H.

2008-12-01

212

Parallel RF Wafer Sort Production Testing  

Microsoft Academic Search

The increasing demand for smaller, thinner and more complex portable electronic devices is driving the chip package to incorporate multi-die and wafer-level packaging. A key benefit for multi-die packaging is that dies from different manufacturers or fabrication processes can be incorporated without taking up too much space. Wafer-level packaging has the advantage of allowing very thin chip packages, demanded by

Martin Dresler; Frank Goh; Eng-Keong Tan

213

A LigA Three-Domain Region Protects Hamsters from Lethal Infection by Leptospira interrogans  

PubMed Central

The leptospiral LigA protein consists of 13 bacterial immunoglobulin-like (Big) domains and is the only purified recombinant subunit vaccine that has been demonstrated to protect against lethal challenge by a clinical isolate of Leptospira interrogans in the hamster model of leptospirosis. We determined the minimum number and location of LigA domains required for immunoprotection. Immunization with domains 11 and 12 was found to be required but insufficient for protection. Inclusion of a third domain, either 10 or 13, was required for 100% survival after intraperitoneal challenge with Leptospira interrogans serovar Copenhageni strain Fiocruz L1-130. As in previous studies, survivors had renal colonization; here, we quantitated the leptospiral burden by qPCR to be 1.2×103 to 8×105 copies of leptospiral DNA per microgram of kidney DNA. Although renal histopathology in survivors revealed tubulointerstitial changes indicating an inflammatory response to the infection, blood chemistry analysis indicated that renal function was normal. These studies define the Big domains of LigA that account for its vaccine efficacy and highlight the need for additional strategies to achieve sterilizing immunity to protect the mammalian host from leptospiral infection and its consequences. PMID:22180800

Coutinho, Mariana L.; Choy, Henry A.; Kelley, Melissa M.; Matsunaga, James; Babbitt, Jane T.; Lewis, Michael S.; Aleixo, Jose Antonio G.; Haake, David A.

2011-01-01

214

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner  

NASA Technical Reports Server (NTRS)

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

2013-01-01

215

Wafer-size free-standing single-crystalline graphene device arrays  

NASA Astrophysics Data System (ADS)

We report an approach of wafer-scale addressable single-crystalline graphene (SCG) arrays growth by using pre-patterned seeds to control the nucleation. The growth mechanism and superb properties of SCG were studied. Large array of free-standing SCG devices were realized. Characterization of SCG as nano switches shows excellent performance with life time (>22 000 times) two orders longer than that of other graphene nano switches reported so far. This work not only shows the possibility of producing wafer-scale high quality SCG device arrays but also explores the superb performance of SCG as nano devices.

Li, Peng; Jing, Gaoshan; Zhang, Bo; Sando, Shota; Cui, Tianhong

2014-08-01

216

Porous solid ion exchange wafer for immobilizing biomolecules  

DOEpatents

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

Arora, Michelle B. (Woodridge, IL); Hestekin, Jamie A. (Morton Grove, IL); Lin, YuPo J. (Naperville, IL); St. Martin, Edward J. (Libertyville, IL); Snyder, Seth W. (Lincolnwood, IL)

2007-12-11

217

Wafer dicing process optimization and characterization for C90 low-k wafer technology  

Microsoft Academic Search

This paper presents an investigation on the effect and optimization of machining parameters for 90 nm low-k wafer topside peeling improvement in mechanical dicing operation. It is part of the continuous improvement that performed based on current established dicing recipe. The resulted outcomes to achieve are cut quality improvement, dicing yield loss reduction and device reliability enhancement for low-k wafer

Koh Wen Shi; K. Y. Yow; K. Rachel; L. Calvin

2009-01-01

218

Passive Wireless Monitoring of Wafer Cleanliness During Rinsing of Semiconductor Wafers  

Microsoft Academic Search

Semiconductor facilities consume large amounts of water, most of which is used for rinsing of wafers during cleaning steps. To optimize water use, real-time and in situ monitoring of wafer cleanliness during rinsing is necessary. Yet no prior art is real-time and in situ. In this paper, we present a passive wireless sensing system capable of measuring the residual contamination

Xu Zhang; Jun Yan; Bert Vermeire; Farhang Shadman; Junseok Chae

2010-01-01

219

Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics  

SciTech Connect

Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

None

2010-01-15

220

Wafer-fused semiconductor radiation detector  

DOEpatents

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

2002-01-01

221

Wafer bonding of gallium arsenide on sapphire  

NASA Astrophysics Data System (ADS)

Three-inch (100) gallium arsenide wafers were bonded to ( 1/line{1} 02) sapphire in a micro-cleanroom at room temperature under hydrophilic or hydrophobic surface conditions. Subsequent heating up to 500 °C increased the bond energy of the GaAs-on-sapphire (GOS) wafer pair close to the fracture energy of the bulk material. The bond energy was measured as a function of the temperature. Since the thermal expansion coefficients of GaAs and sapphire are close to each other, the bonded wafer pair is stable against thermal treatment and quenching in liquid nitrogen. During heating in different gas atmospheres, macroscopic interface bubbles and microscopic imperfections were formed within the bonding interface, which were analysed by transmission electron microscopy (TEM). These interface bubbles can be prevented by hydrophobic bonding in a hydrogen atmosphere.

Kopperschmidt, P.; Kästner, G.; Senz, S.; Hesse, D.; Gösele, U.

222

Modeling and fabrication of micro 3K-2-type planetary gear reducer utilizing SU-8 photoresist as alternative LIGA technology  

NASA Astrophysics Data System (ADS)

The LIGA type process, utilizing SU-8 photoresist as alternative LIGA technology, can fabricate high aspect ratio microstructures without employing synchrotron light and suitable X-ray mask. Based on LIGA type process in this paper, detailed investigations of the modeling and fabrication of micro 3K-2 type planetary gear reducer, such as the modeling and design of micro reducer, CAD of micro gear mask, SU-8 UV photolithography, micro electroforming, micro molding, have been performed. And 400 um thickness sun gear, 400 um thickness planet gear, 200 um thickness fixed inner gear, and 200 um thickness rotary inner gear, whose teeth are 15,11,36,39 respectively, have been obtained. Utilizing these gears, the micro reducer whose modulus, outer diameter and velocity ratio are 0.03, 2mm, 44.2:1, has been assembled and applied in (phi) 2mm micro electro magnetic motor successfully.

Zhang, Weiping; Chen, Wenyuan; Chen, Di; Chen, Xiaomei; Wu, Xiaosheng; Xu, Zhengfu

2001-10-01

223

Wafer fab mask qualification techniques and limitations  

NASA Astrophysics Data System (ADS)

Mask inspection and qualification is a must for wafer fabs to ensure and guarantee high and stable yields. Single defect events can easily cause a million dollar loss through a defect duplicating onto the wafer. Several techniques and methods for mask qualification within a wafer fab are known but not all of them are neither used nor understood regarding their limitations. Increasing effort on existing tool platforms is necessary to detect the defects of interest which are at the limit of the tools specification - On the other hand next generation tools are very sensitive and therefore consume only a negligible amount of time for recipe optimization. Knowing the limits of each inspection tool helps to balance between effort and benefit. Masks with programmed defects of 90nm and 65nm design rule were used in order to compare the different available inspection techniques. During the course of this technical work, the authors concentrate mainly on two inspection techniques. The first one inspects the reticle itself using KLA-Tencor's SLF27 (TeraStar) and SL536 (TeraScan) tools. As the reticle gets inspected itself this is the so called "direct" mask defect inspection. The second inspection technique discussed is the "indirect" mask defect inspection which consists of printing the pattern on a blank wafer and use KLA-Tencor's bright-field wafer inspection tool (2xxx series) to inspect the wafer. Data of this work will include description of the techniques, inspection results, defect maps, sensitivity analysis, effort estimation as well as limitations for both techniques for the used design rule.

Poock, Andre; Maelzer, Stephanie; Spence, Chris; Tabery, Cyrus; Lang, Michael; Schnasse, Guido; Peikert, Milko; Bhattacharyya, Kaustuve

2006-10-01

224

Design, manufacture and testing of microengineered stencils used for sub 100 micron wafer level bumping  

Microsoft Academic Search

Summary form only given. The advances of chip scale packaging technologies have induced an increase of the density of solder joints in microelectronics products. Pitch sizes are consequently due to further decrease, leading to joint structures at sub 100mum dimensions. Stencil printing for wafer bumping with fine particle solder pastes is potentially a low-cost assembly solution for fine pitch solder

N. J. Gorman; R. W. Kay; I. Roney; M. P. Y. Desmulliez

2006-01-01

225

Damage Identification in Aging Aircraft Structures with Piezoelectric Wafer Active Sensors  

E-print Network

) reduces total life cycle cost and increases safety and availability of military and commercial aircraft the advancing crack tip. For commercial aircraft, NASA's Aviation Safety Program considers a large-scale deployDamage Identification in Aging Aircraft Structures with Piezoelectric Wafer Active Sensors VICTOR

Giurgiutiu, Victor

226

Influence of Silicon on Insulator Wafer Stress Properties on Placement Accuracy of Stencil Masks  

Microsoft Academic Search

The issue of placement control is one of the key challenges of stencil mask technology. A high placement accuracy can only be achieved with a precise control of mechanical stress on a global and local scale. For this reason, the stress properties of the mask blank material -typically silicon on insulator (SOI) wafers- have to be known and adjusted properly.

Frank-Michael Kamm; Albrecht Ehrmann; Herbert Schäfer; Werner Pamler; Rainer Käsmaier; Jörg Butschke; Reinhard Springer; Ernst Haugeneder; Hans Löschner

2002-01-01

227

Making Porous Luminescent Regions In Silicon Wafers  

NASA Technical Reports Server (NTRS)

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

228

Across wafer CD uniformity optimization by wafer film scheme at double patterning lithography process  

NASA Astrophysics Data System (ADS)

The Double Patterning lithography (DPL) process is a well known method to overcome the k1 limit below 0.25, but the pattern final performance (OVL/CD) get more sensitive with the initial core CD uniformity, one of the main factors is across wafer CD uniformity control. Previous improvements applying scanner dose or PEB temperature multi-zone control, the others use the vacuum PEB plate design. In this study, we adopt various DPL sacrificial layers to modify wafer warpage level, it can adjust a suitable wafer warpage profile. By this method, we can achieve 30% CD uniformity improvement without the scanner dose/ PEB multi-zone heating compensation,

Lin, Hsiao-Chiang; Li, Yang-Liang; Wang, Shiuan-Chuan; Liu, Chien-Hung; Wang, Zih-Song; Hsuh, Jhung-Yuin

2014-04-01

229

Wafer capping of MEMS with fab-friendly metals  

NASA Astrophysics Data System (ADS)

Inertial MEMS (Micro Electro Mechanical System) sensors are normally sealed in hermetic enclosures. Some are assembled in hermetic packages but wafer level packaging has become much more important in recent years. Anodic bonding can be used to achieve wafer level seals between silicon and glass but most suppliers of inertial sensors screen print glass frit onto silicon cap wafers. After removing the organic vehicle, these patterned cap wafers are sealed to device wafer prior to wafer singulation and plastic packaging. Anodic and glass frit bonding are both cost-effective. However, they impose size, quality and performance limitations. Wafer level sealing with a metal removes some of these limitations but introduces other concerns. This paper will review the current wafer level hermetic processes followed by a description of a thermocompression metal seal technology that is compatible with IC fabrication.

Martin, Jack

2007-01-01

230

Bubble-domain circuit wafer evaluation coil set  

NASA Technical Reports Server (NTRS)

Coil structures have been designed to permit nondestructive testing of bubble wafers. Wafers can be electrically or optically inspected and operated from quasi-static frequency to maximum device operating frequency.

Chen, T. T.; Williams, J. L.

1975-01-01

231

Geometry control of recrystallized silicon wafers for solar applications  

E-print Network

The cost of manufacturing crystalline silicon wafers for use in solar cells can be reduced by eliminating the waste streams caused by sawing ingots into individual wafers. Professor Emanuel Sachs has developed a new method ...

Ruggiero, Christopher W

2009-01-01

232

Apparatus for edge etching of semiconductor wafers  

NASA Technical Reports Server (NTRS)

A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

Casajus, A.

1986-01-01

233

Localized induction heating for wafer level packaging  

Microsoft Academic Search

Localized induction heating for wafer level packaging is discussed. This paper is to investigate the relationships between the geometry of solder loop and temperature distribution in induction heating. Using finite element method (FEM) and IR thermal imager, temperature distribution and variation are explored, which shows that the temperature on the solder loops is a function of the area and edge

Mingxiang Chen; Wenming Liu; Yanyan Xi; Changyong Lin; Sheng Liu

2009-01-01

234

Scanning holographic scatterometer for wafer surface inspection  

NASA Astrophysics Data System (ADS)

The semiconductor industry requires ever smaller semiconductor structures with faster response times and more function per unit area of each chip. In addition, the industry is changing from 200 mm to 300 mm diameter wafers with fewer defects and rapid detection at all processing stages. To meet these needs, defect data must be processed in near-real-time to expedite correction of processing problems at the earliest possible stage. Under a Small Business Innovation Research (SBIR) program, sponsored by the Air Force Manufacturing Technology Division at Wright Laboratory, Dayton, Ohio, Sentec Corporation has developed a revolutionary technology for contaminant particle detection on unpatterned semiconductor wafers. A key to the Sentec technology is detection, not of the intensity of backscattered energy from particles or defects, but of the amplitude of the electro-magneitc field of this backscattered energy. This new technology will allow the detection of particles that are significantly smaller than those which can be reliably located using current scatterometers. The technical concepts for a stand-alone particle detection tool have been created. It uses a continuous scanning mechanism to perform high-speed examinations of target wafers. This tool, also, has the capability of quantifying the microroughness or background haze of a subject wafer and presenting that information separate from the contamination particle data. During the course of this project, three patent applications were filed.

Klooster, Alex; Marks, James; Hanson, Kael; Sawatari, Takeo

2004-05-01

235

Wafer fusion: materials issues and device results  

Microsoft Academic Search

A large number of novel devices have been recently demonstrated using wafer fusion to integrate materials with different lattice constants. In many cases, devices created using this technique have shown dramatic improvements over those which maintain a single lattice constant. We present device results and characterizations of the fused interface between several groups of materials

A. Black; A. R. Hawkins; N. M. Margalit; D. I. Babic; Y.-L. Chang; P. Abraham; J. E. Bowers; E. L. Hu

1997-01-01

236

Economic analysis of 450mm wafer migration  

Microsoft Academic Search

To achieve the required continuous cost reduction driven by Moore's Law, both miniaturization through technology advances and wafer size increase have been employed in order to maintain the growth and profitability of semiconductor industry. Although some technical analyses have been done for 450 mm migration, little research has been done on economic analysis to justify the decisions and thus suggest

Chen-Fu Chien; J. K. Wang; Tzu-Ching Chang; Wen-Chin Wu

2007-01-01

237

Fast Photoluminescence Imaging of Silicon Wafers  

Microsoft Academic Search

Photoluminescence (PL) imaging is demonstrated as a fast characterization tool allowing variations of the minority carrier lifetime within large area silicon wafers to be measured with high spatial resolution and with a data acquisition time of only one second. PL imaging is contactless and can therefore be applied to silicon solar cells before and after every processing stage including fully

T. Trupke; R. A. Bardos; M. D. Abbott; F. W. Chen; J. E. Cotter; A. Lorenz

2006-01-01

238

Deformation of Si(100) wafers during rapid thermal annealing  

Microsoft Academic Search

In this paper insitu wafer curvature measurements are presented that were performed during rapid thermal annealing of silicon wafers. The wafer curvature due to thermal stress originating from a nonuniform temperature distribution was measured as a function of time for a fixed setting of the illumination source power. The presence of thermal stress was clearly demonstrated. It was found that

J. F. Jongste; T. G. M. Oosterlaken; G. C. J. Bart; G. C. A. M. Janssen; S. Radelaar

1994-01-01

239

Strength of Si Wafers with Microcracks: A Theoretical Model (Poster)  

SciTech Connect

A new analytical expression that takes into account the surface, edge, and bulk properties of a wafer has been proposed to describe the strength of the brittle materials. A new proposed fracture-mechanics numerical simulation successfully predicted the strength of the cast silicon wafers. It has been shown that the predicted wafer strength distribution agrees well with the available experimental results.

Rupnowski, P.; Sopori, B.

2008-05-01

240

Temporary Bonding of Wafer to Carrier for 3D-Wafer Level Packaging  

Microsoft Academic Search

With great demand of high-end applications such as high-integration microelectronics, system-in-packaging (SiP), power application and flexible ICs, a device wafer needs to be thinned down and further structured, for example, fabrication of through-silicon via for the improved performance. Therefore, handling of ultrathin wafer (less than 100¿m in thickness) becomes a great challenge for both front-end and back-end processes. In current

M. H. Shuangwu; D. Pang; S. Nathapong; P. Marimuthu

2008-01-01

241

Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology  

NASA Astrophysics Data System (ADS)

Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances. Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported. Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure mechanism. The kinetic and thermodynamic analysis of the annealing-induced interfacial transformation process has been performed based upon the temporal measurements of interface electrical conductivity and micromorphologies. Finally, the feasibility of using the combination of low-temperature grown amorphous alpha-(Ga, As) materials and wafer-bonding technology to fabricate GaSb semiconductor on GaAs substrates to potentially create GaSb-on-insulator structure has been demonstrated.

Shi, Fang Frank

242

Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon wafers  

E-print Network

Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon microscopy, profilometer and wafer bow measurements. Plasma-activated direct bonding of DOI wafers to thermal September 2010 Keywords: Diamond-on-insulator Plasma activation Ultrananocrystalline diamond Direct bonding

Akin, Tayfun

243

A flip-chip LIGA assembly technique via electroplating L.-W. Pan, L. Lin, J. Ni  

E-print Network

A flip-chip LIGA assembly technique via electroplating L.-W. Pan, L. Lin, J. Ni Abstract A novel-EDM [1±3]. Their manufacturing processes are not compatible with IC (Integrated Circuit) fabrication- sion bonding limits potential applications. As the manufacturing technologies of high

Lin, Liwei

244

Fabrication of GaAs laser diodes on Si using low temperature bonding of MBE grown GaAs wafers with Si wafers  

Microsoft Academic Search

The conventional heteroepitaxial GaAs-on-Si growth suffers from poor III-V material quality (dislocation density of ?108 cm-2 and a residual thermal stress of ?109 dyn\\/cm2) and some process incompatibilities between the CMOS and III-V technologies. For these reasons, we have developed a heterogeneous integration scheme, which has the wafer-scale characteristics of monolithic integration and at the same time is compatible with

D. Cengher; Z. Hatzopoulos; S. Gallis; G. Deligeorgis; E. Aperathitis; M. Alexe; V. Dragoi; E. D. Kyriakis-Bitzaros; G. Halkias; A. Georgakilas

2002-01-01

245

Wafer-Scale CMP Modeling of With-in Wafer Non-Uniformity  

E-print Network

bottom of the polishing pad. In a novel CMP configuration byCMP of low-k dielectrics, usually soft polymer materials, an aggressive contact between low-k layer and pad/polymeric polishing pad, as illustrated in Figure 1. The CMP

Luo, Jianfeng; Dornfeld, David A

2003-01-01

246

Development and Optimization of Automated Dry-Wafer Separation  

E-print Network

Abstract—In a state-of-the-art industrial production line of photovoltaic products the handling and automation processes are of particular importance and implication. While processing a fully functional crystalline solar cell an as-cut photovoltaic wafer is subject to numerous repeated handling steps. With respect to stronger requirements in productivity and decreasing rejections due to defects the mechanical stress on the thin wafers has to be reduced to a minimum as the fragility increases by decreasing wafer thicknesses. In relation to the increasing wafer fragility, researches at the Fraunhofer Institutes IPA and CSP showed a negative correlation between multiple handling processes and the wafer integrity. Recent work therefore focused on the analysis and optimization of the dry wafer stack separation process with compressed air. The achievement of a wafer sensitive process capability and a high production throughput rate is the basic motivation in this research.

Tim Giesen; Christian Fischmann; Fabian Böttinger; Er Ehm; Er Verl

247

TOPICAL REVIEW: Wafer level packaging of MEMS  

NASA Astrophysics Data System (ADS)

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass-Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review.

Esashi, Masayoshi

2008-07-01

248

Devices using resin wafers and applications thereof  

DOEpatents

Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL); St. Martin, Edward (Libertyville, IL); Arora, Michelle (Woodridge, IL); de la Garza, Linda (Woodridge, IL)

2009-03-24

249

Optical cavity furnace for semiconductor wafer processing  

DOEpatents

An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

Sopori, Bhushan L.

2014-08-05

250

Molecular dynamics studies of silica wafer bonding  

NASA Astrophysics Data System (ADS)

Molecular dynamics simulations are performed to investigate the atomic processes initiated by the adhesion of two silica surfaces, which are covered with adsorbates of oxygen, hydrogen or water molecules. The calculations describe the mechanism of hydrophilic silicon wafer bonding in terms of empirical potentials assumed. The challenge of the macroscopically relevant computations is to understand and to predict the formation of covalent bonds as a function of initial silica structures, external forces, adsorbates, and annealing temperatures applied.

Timpel, Dirk; Schaible, Max; Scheerschmidt, Kurt

1999-03-01

251

VLED for Si wafer-level packaging  

NASA Astrophysics Data System (ADS)

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

252

Precipitating Chromium Impurities in Silicon Wafers  

NASA Technical Reports Server (NTRS)

Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

Salama, A. M.

1982-01-01

253

Investigation of silicon wafering by wire EDM  

Microsoft Academic Search

The new technology of silicon wafering by wire electrodischarge machining (EDM) was investigated to determine its mechanism of current-conducting and material removal. Target materials were n-type single-crystal silicon ingots with the resistivity of 7–15 cm?. It was found that the surface potential barrier of the semiconductors had a dominating effect on EDM cutting speed. Technological experiments were performed to determine

Y. F. Luo; C. G. Chen; Z. F. Tong

1992-01-01

254

On-wafer large signal pulsed measurements  

Microsoft Academic Search

The authors present an on-wafer fully automated pulse-measurement system for automatically extracting the characteristics of the nonlinear current generators of a field-effect transistor (FET) as a function of the gate-to-source and drain-to-source voltages. Measurements performed for different DC and pulse width voltage conditions make it possible to extract accurate nonlinear FET models and analyze the trapping and temperature effects. The

J. F. Vidalou; F. Grossier; M. Camiade; J. Obregon

1989-01-01

255

Dual side wafer metrology for micromachining applications  

NASA Astrophysics Data System (ADS)

Advances in micromachining (MEMS) applications such as optical components, inertial and pressure sensors, fluidic pumps and radio frequency (RF) devices are driving lithographic requirements for tighter registration, improved pattern resolution and improved process control on both sides of the substrate. Consequently, there is a similar increase in demand for advanced metrology tools capable of measuring the Dual Side Alignment (DSA) performance of the lithography systems. There are a number of requirements for an advanced DSA metrology tool. First, the system should be capable of measuring points over the entire area of the wafer rather than a narrow area near the lithography alignment targets. Secondly, the system should be capable of measuring a variety of different substrate types and thicknesses. Finally, it should be able to measure substrates containing opaque deposited films such as metals. In this paper, the operation and performance of a new DSA metrology tool is discussed. The UltraMet 100 offers DSA registration measurement at greater than 90% of a wafer's surface area, providing a true picture of a lithography tool"s alignment performance and registration yield across the wafer. The system architecture is discussed including the use of top and bottom cameras and the pattern recognition system. Experimental data is shown for tool repeatability and reproducibility over time.

Schurz, Dan; Flack, Warren W.; Anberg, Doug

2004-05-01

256

Mask-to-wafer alignment system  

DOEpatents

A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

2003-11-04

257

Wafer level test solutions for IR sensors  

NASA Astrophysics Data System (ADS)

Wafer probers provide an established platform for performing electrical measurements at wafer level for CMOS and similar process technologies. For testing IR sensors, the requirements are beyond the standard prober capabilities. This presentation will give an overview about state of the art IR sensor probing systems reaching from flexible engineering solutions to automated production needs. Cooled sensors typically need to be tested at a target temperature below 80 K. Not only is the device temperature important but also the surrounding environment is required to prevent background radiation from reaching the device under test. To achieve that, a cryogenic shield is protecting the movable chuck. By operating that shield to attract residual gases inside the chamber, a completely contamination-free test environment can be guaranteed. The use of special black coatings are furthermore supporting the removal of stray light. Typically, probe card needles are operating at ambient (room) temperature when connecting to the wafer. To avoid the entrance of heat, which can result in distorted measurements, the probe card is fully embedded into the cryogenic shield. A shutter system, located above the probe field, is designed to switch between the microscope view to align the sensor under the needles and the test relevant setup. This includes a completely closed position to take dark current measurements. Another position holds a possible filter glass with the required aperture opening. The necessary infrared sources to stimulate the device are located above.

Giessmann, Sebastian; Werner, Frank-Michael

2014-05-01

258

Temperature rise of the mask-resist assembly during LIGA exposure.  

SciTech Connect

Deep X-ray lithography on PMMA resist is used in the LIGA process. The resist is exposed to synchrotron X-rays through a patterned mask and then is developed in a liquid developer to make high aspect ratio microstructures. The limitations in dimensional accuracies of the LIGA generated microstructure originate from many sources, including synchrotron and X-ray physics, thermal and mechanical properties of mask and resist, and from the kinetics of the developer. This work addresses the thermal analysis and temperature rise of the mask-resist assembly during exposure in air at the Advanced Light Source (ALS) synchrotron. The concern is that dimensional errors generated at the mask and the resist due to thermal expansion will lower the accuracy of the lithography. We have developed a three-dimensional finite-element model of the mask and resist assembly that includes a mask with absorber, a resist with substrate, three metal holders, and a water-cooling block. We employed the LIGA exposure-development software LEX-D to calculate volumetric heat sources generated in the assembly by X-ray absorption and the commercial software ABAQUS to calculate heat transfer including thermal conduction inside the assembly, natural and forced convection, and thermal radiation. at assembly outer and/or inner surfaces. The calculations of assembly maximum temperature. have been compared with temperature measurements conducted at ALS. In some of these experiments, additional cooling of the assembly was produced by forced nitrogen flow ('nitrogen jets') directed at the mask surface. The temperature rise in the silicon mask and the mask holder comes directly from the X-ray absorption, but nitrogen jets carry away a significant portion of heat energy from the mask surface, while natural convection carries away negligibly small amounts energy from the holder. The temperature rise in PMMA resist is mainly from heat conducted from the silicon substrate backward to the resist and from the inner cavity air forward to the resist, while the X-ray absorption is only secondary. Therefore, reduction of heat flow conducted from both substrate and cavity air to the resist is essential. An improved water-cooling block is expected to carry away most heat energy along the main heat conductive path, leaving the resist at a favorable working temperature.

Ting, Aili

2004-11-01

259

?-Device fabrication and packaging below 300°C utilizing plasma-assisted wafer-to-wafer bonding  

NASA Astrophysics Data System (ADS)

Wafer-to-wafer bonding techniques, such as anodic bonding or high temperature silicon direct fusion bonding, have been in development since the late 1960's and became key technologies for MEMS manufacturing. Plasma assisted wafer bonding is an emerging method offering several advantages over traditional bonding techniques. This technology was first discovered and patented in the early 1990's and has been used in SOI production for the past five years. Now plasma activation benefits are being used to enable 3D integration and advanced MEMS device fabrication and packaging. The main advantage of plasma assisted bonding is that high strength direct bonds between substrates, like Si, glass or polymers, can be achieved already below 300°C.

Kirchberger, Herwig; Pelzer, Rainer; Farrens, Sharon

2006-01-01

260

Molecular and ionic contamination monitoring for cleanroom air and wafer surfaces  

NASA Astrophysics Data System (ADS)

Advances in the electronic industry toward large-scale integration of semiconductor devices have placed strict demands on the ability to measure and monitor ultratrace levels of impurities. Even though they have been found to have increasingly detrimental impacts on the performance and yield of semiconductor products, organic and non-metal ionic contaminants have not received the same attention as particles and metallics. Method developments for ultratrace measurements of molecular and ionic contamination are far behind the demands. This paper describes the use of different sampling and analytical techniques to assess and monitor molecular and ionic contaminants in cleanroom ambient air and on wafer surfaces. Thermal desorption gas chromatography mass spectrometry/nitrogen phosphorous detector is used for the identification and quantification of organic contaminants. Ammonium (NH4+) and inorganic anions are analyzed by using capillary electrophoresis with indirect UV detection methods. The identification and quantification of specific organic compounds, which outgas from cleanroom ULPA filters and wafer package boxes and tend to adsorb on silicon wafers, will be demonstrated. Ammonium and anion contamination for different wafer cleaning processes will be compared. The capabilities, applications, and limitations of these techniques will be discussed in further details.

Sun, Peng; Adams, Marty; Shive, Larry; Pirooz, Saeed

1997-09-01

261

"Performance Of A Wafer Stepper With Automatic Intra-Die Registration Correction."  

NASA Astrophysics Data System (ADS)

An evaluation of a wafer stepper with the new improved Philips/ASM-L phase grating alignment system is reported. It is shown that an accurate alignment system needs an accurate X-Y-0 wafer stage and an accurate reticle Z stage to realize optimum overlay accuracy. This follows from a discussion of the overlay budget and an alignment procedure model. The accurate wafer stage permits high overlay accuracy using global alignment only, thus eliminating the throughput penalty of align-by-field schemes. The accurate reticle Z stage enables an intra-die magnification control with respect to the wafer scale. Various overlay data are reported, which have been measured with the automatic metrology program of the stepper. It is demonstrated that the new dual alignment system (with the external spatial filter) has improved the ability to align to weakly reflecting layers. The results are supported by a Fourier analysis of the alignment signal. Resolution data are given for the PAS 2500 projection lenses, which show that the high overlay accuracy of the system is properly matched with submicron linewidth control. The results of a recently introduced 20mm i-line lens with a numerical aperture of 0.4 (Zeiss 10-78-58) are included.

van den Brink, M. A.; Wittekoek, S.; Linders, H. F. D.; van Hout, F. J.; George, R. A.

1987-01-01

262

Wafer-level assembly and sealing of a MEMS nanoreactor for in situ microscopy  

NASA Astrophysics Data System (ADS)

This paper presents a new process for the fabrication of MEMS-based nanoreactors for in situ atomic-scale imaging of nanoparticles under relevant industrial conditions. The fabrication of the device is completed fully at wafer level in an ISO 5 clean room and it is based on silicon fusion bonding and thin film encapsulation for sealed lateral electrical feedthroughs. The fabrication process considerably improves the performances of previous nanoreactors. The wafer-level assembly allows faster preparation of devices, hydrocarbon contamination is no longer observed and the control of the channel height leads to a better flow reproducibility. The channel is shown to be sufficiently hermetic to work in the vacuum of a transmission electron microscope while a pressure of 100 kPa is maintained inside the nanoreactor. The transparency is demonstrated by the atomic scale imaging of YBCO nanoparticles, with a line spacing resolution of 0.19 nm.

Mele, L.; Santagata, F.; Pandraud, G.; Morana, B.; Tichelaar, F. D.; Creemer, J. F.; Sarro, P. M.

2010-08-01

263

Wafer-level Accelerated Lifetesting of Individual Devices  

Microsoft Academic Search

The thermal activation energies of TriQuint Semiconductor's TQPED devices are evaluated with an innovative wafer-level technique for accelerated life testing. The method was used to determine the activation energy for. both the depletion-mode and enhancement-mode pHEMT devices. An on-wafer heating element around individual devices allowed stressing at various temperatures on the same wafer. Temperatures above 275degC were easily achieved without

D. J. M. Hamada; W. J. Roesch

2007-01-01

264

High Strength Si Wafers with Heavy B and Ge Codoping  

Microsoft Academic Search

Si wafers with heavy B and Ge codoping have been characterized in comparison with lightly B-doped and heavily B-doped Si wafers as references. It was found that only a very few slip dislocations could be observed in the heavily B- and Ge-codoped (1019 atoms\\/cm3) Si wafers, whereas many slip dislocations were observed in both the heavily B-doped (1019 atoms\\/cm3) and

Xinming Huang; Tsuyoshi Sato; Masami Nakanishi; Toshinori Taishi; Keigo Hoshikawa

2003-01-01

265

Study on Subsurface Damage Generated in Ground Si Wafer  

Microsoft Academic Search

In this paper, we study and evaluate the subsurface damage of the ground wafers to understand the effect of residual stress\\u000a on the wafer deflection. The experimental results show that two indexes of depth of the damaged layer and degree of the residual\\u000a stress are directly associated with the warpage of wafer. The degree of the damage decreases with an

Bahman Soltani Hosseini; Libo Zhou; Tatsuya Tsuruga; Jun Shimizu; Hiroshi Eda; Sumio Kamiya; Hisao Iwase

266

Improvement in WL-CSP reliability by wafer thinning  

Microsoft Academic Search

WL-CSP is a low profile, true chip sue package that is entirely built on a wafer using front-end and back end processing. The wafers can be batch-processed in a fab, which reduces the number of materials and packaging steps, reduces inventory, and allows for wafer level burn in and test. This technology is driven by cost, sue, and ease of

Li Wetz; Jeny White; Beth Keser

2003-01-01

267

Wafer-Level Membrane-Transfer Process for Fabricating MEMS  

NASA Technical Reports Server (NTRS)

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

268

Wafer-based nanostructure manufacturing for integrated nanooptic devices  

Microsoft Academic Search

The authors have developed a nanomanufacturing platform based on wafer-level nanoreplication with mold and nanopattern transfer by nanolithography. The nanoreplication process, which is based on imprinting a single-layer spin-coated ultraviolet (UV)-curable resist, achieved good nanopatterning fidelity and on-wafer uniformity with high throughput. Some manufacturing issues of the nanoreplication process, such as the impact of wafer and mold surface particles on

Jian Jim Wang; Lei Chen; Stephen Tai; Xuegong Deng; P. F. Sciortino; Jiandong Deng; Feng Liu

2005-01-01

269

Characterization of silicon wafers by transient microwave photoconductivity measurements  

NASA Astrophysics Data System (ADS)

The possibilities and limitations of characterizing single crystalline silicon wafers with a contactless, nondestructive transient photoconductivity method, i.e. the time resolved microwave (TRMC) method has been demonstrated. The bulk lifetime and the diffusion constant of minority charge carriers in n- and p-doped silicon wafers (?: 1-200 ? cm) were determined in two different ways: by varying the wafer thickness and by changing the surface recombination velocity via different etching treatments. Using electron irradiated (14 MeV) wafers, it was shown that this method can be used for the detection of changes in the bulk lifetime.

Sanders, A.; Kunst, M.

1991-09-01

270

Particulate contamination removal from wafers using plasmas and mechanical agitation  

DOEpatents

Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

Selwyn, G.S.

1998-12-15

271

Micro-miniature gas chromatograph column disposed in silicon wafers  

DOEpatents

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Yu, Conrad M. (Antioch, CA)

2000-01-01

272

Wafer level hermetic package and device testing of a SOI-MEMS switch for biomedical applications  

Microsoft Academic Search

We have designed a wafer level chip scale package for a bi-stable SOI-MEMS dc switch using a silicon-glass hermetic seal with through the lid feedthroughs. Bonded at 365 °C, 230 V and 250 kg, they pass the fine\\/gross leak test after thermal cycling and mechanical shock\\/vibration according to MIL-STD-833, fulfilling the requirements for biomedical applications. The measured shear strength is

Rogier A. M. Receveur; Michael Zickar; Cornel Marxer; Vincent Larik; Nicolaas F. de Rooij

2006-01-01

273

Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections  

NASA Astrophysics Data System (ADS)

Packaging is an emerging technology for microsystem integration. The silicon-on-insulator (SOI) wafer has been extensively employed for micromachined devices for its reliable fabrication steps and robust structures. This research reports a packaging approach for silicon-on- insulator-micro-electro-mechanical system (SOI-MEMS) devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling and electroplating. These vias provide electrical signal paths to the MEMS device, while isolating MEMS devices from the outer environment. A high-strength hermetic sealing is then achieved after anodic bonding of the through-wafer-vias-embedded SOI wafer to a Pyrex 7740 glass. Moreover, the packaged SOI-MEMS chip is compatible with surface mount technology, and provides a superior way for 3D heterogeneous integration.

Lin, Chiung-Wen; Yang, Hsueh-An; Wang, Wei Chung; Fang, Weileun

2007-06-01

274

Highly precise micro-retroreflector array fabricated by the LIGA process and its application as tapped delay line filter.  

PubMed

We report on the fabrication of a one-dimensional micro-retroreflector array with a pitch of 100 ?m. The array was fabricated by x-ray lithography and the lithographie, galvanik und abformung (LIGA) process in a 1 mm thick poly(methyl methacrylate) (PMMA) layer and subsequently covered with Au. The area of the array is 1 mm×10 mm. The high precision of the LIGA-based fabrication process allows one to use the element in spectrometers. Here, it is suggested to apply it to the implementation of a transversal filter for femtosecond pulses. We present a theoretical description of the performance of the retroreflector array as a filtering device and show experimental results. PMID:22945143

Bohling, Michael; Seiler, Thomas; Wdowiak, Boguslaw; Jahns, Jürgen; Mohr, Jürgen; Börner, Martin

2012-09-01

275

Potentials of LiGa(S 1-xSe x) 2 mixed crystals for optical frequency conversion  

NASA Astrophysics Data System (ADS)

Phase-matching conditions are considered for second harmonic generation (SHG) and optical parametric generation in LiGa(S 1-xSe x) 2 mixed crystals as a function of chemical composition under the supposition of linear dependence of refractive indices on x. It has been shown that by tuning x over the range 0-1 the SHG can be realized in XY plane for ?=2.1-7.8 ?m pumping at ?=43-90°, in YZ plane for ?=2.1-2.2 and 4.8-7.8 ?m pumping at ?=0-90°, and in XZ plane for ?=1.6-11.7 ?m pumping at ?=0-57°. The LiGa(S 1-xSe x) 2 solid solutions are also attractive for design of tunable femtosecond pulse frequency converters with saving of pump pulse duration.

Huang, J.-J.; Atuchin, V. V.; Andreev, Yu. M.; Lanskii, G. V.; Pervukhina, N. V.

2006-07-01

276

Microfabrication of fine electron beam tunnels using UV-LIGA and embedded polymer monofilaments for vacuum electron devices  

NASA Astrophysics Data System (ADS)

Vacuum electron devices require electron beams to be transported through hollow channels that pass through an electromagnetic slow-wave circuit. These electron 'beam tunnels' are shrinking toward sizes smaller than traditional techniques can manage as the operating frequencies push toward the THz. A novel technique is described and experimentally demonstrated that uses polymer monofilaments of arbitrary cross-sectional shape combined with ultraviolet photolithography (UV-LIGA) of SU-8 photoresists. This combination of monofilaments and SU-8 structures comprises a 3D mold around which copper is electroformed to produce high-quality beam tunnels of arbitrary length and size along with the electromagnetic circuits. True round beam tunnels needed for upper-millimeter wave and THz vacuum electron devices can now be fabricated in a single UV-LIGA step. These techniques are also relevant to microfluidic devices and other applications requiring very small, straight channels with aspect ratios of several hundred or more.

Joye, Colin D.; Calame, Jeffrey P.; Nguyen, Khanh T.; Garven, Morag

2012-01-01

277

Wafer-scale Meniscus Alignment of Carbon Nanotubes  

Microsoft Academic Search

Making single-walled carbon nanotubes (SWNTs) a possible next-generation transistor nanotechnology requires control of their chirality, length, placement, and alignment. We develop a method for controlled placement and alignment of SWNTs using mechanical meniscus action. In this technique, we suspend surfactant-coated SWNTs in aqueous solution and place the solution between two surfaces of differing hydrophobicity, forming a meniscus. We drag this

Joshua Wood; Vineet Nazareth; Joseph Lyding

2010-01-01

278

Bio\\/chemical microsystem designed for wafer scale testing  

Microsoft Academic Search

We have designed a bio\\/chemical microsystem for online monitoring of glucose concentrations during fermentation. The system contains several passive microfluidic components including an enzyme reactor, a flow lamination part and a detector. Detection is based on the reaction of hydrogen peroxide, that is produced from glucose in an enzyme reactor, with luminol. This chemiluminescent reaction generates light that is detected

Anders M. Jorgensen; Klaus B. Mogensen; Weimin Rong; Pieter Telleman; Joerg P. Kutter

2001-01-01

279

Mechanisms for room temperature direct wafer bonding  

NASA Astrophysics Data System (ADS)

Reducing the temperature needed for high strength bonding which was and is driven by the need to reduce effects of coefficient of thermal expansion mismatch, reduce thermal budgets, and increase throughput has led to the development of plasma treatment procedures capable of bonding Si wafers below 300 °C with a bond strength equivalent to Si bulk. Despite being widely used, the physical and chemical mechanisms enabling low temperature wafer bonding have remained poorly understood. We developed an understanding of the beneficial surface modifications by plasma and a model based on short range low temperature diffusion through bonding experiments combined with results from spectroscopic ellipsometry, depth resolving Auger electron spectroscopy, and transmission electron microscopy measurements. We also present experimental results showing that even at room temperature reasonable bond strength can be achieved. We conclude that the gap closing mechanism is therefore a process which balances the lowering of the total energy by minimizing the sum of the free surface energy (maximizing the contact area between the surfaces) and strain energy in the oxide at the bond interface.

Plach, T.; Hingerl, K.; Tollabimazraehno, S.; Hesser, G.; Dragoi, V.; Wimplinger, M.

2013-03-01

280

Surface activation enhanced low temperature silicon wafer bonding  

NASA Astrophysics Data System (ADS)

Direct wafer bonding technology has received great attention since 1985. It enables to realize the novel combinations of different materials for expanded functionality and provides a versatile device technology for transferring device layers to another wafer for further processing or device integration onto one wafer. Silicon direct wafer bonding has found a wide range of applications including Silicon-on-Insulator (SOI) wafers, micromechanical devices, and sensors and actuators. One of the challenges facing this technology is to achieve strong bonding at low temperatures that can survive post-wafer bonding processing. This dissertation presents the results of developing new wafer bonding processes for achieving high bonding energy at low temperatures. For thermal oxide covered silicon wafer bonding, dilute HF solution has been used to etch the wafers prior to room temperature bonding. The bonding energy has been significantly enhanced which reached silicon fracture energy after annealed at 100°C for 45 hours. For native oxide covered silicon wafers, the pre-treatment in dilute HNO3 and dilute HF mixtures has been found to be able to enhance the bonding energy at low temperatures. This is attributed to the incorporation of fluorine in native oxide during the pre-treatment. Various approaches have also been explored for hydrophobic silicon wafer bonding. Both boron doped surface layers and the amorphous surface layers have demonstrated an ability to significantly enhance the bonding energy at low temperatures, with silicon fracture energy achieved at 300--400°C for hydrophobically bonded pairs. The thermal management of heterojunction bipolar transistor (HBT) circuits fabricated by Symmetric Intrinsic HBT (SIHBT) processing was also studied in this research project using simulation method. Design criteria of selecting the surrogate substrates, interconnection dimension, and dielectric materials for the optimization of thermal management have been obtained.

Gan, Qing

281

An all-glass chip-scale MEMS package with variable cavity pressure  

Microsoft Academic Search

A dielectric, chip-scale MEMS packaging method is discussed. The packaging method uses wafer-to-wafer bonding of micromachined glass wafers with a reflowed, glass, sealing ring. The glass wafers are micromachined and have metal and silicon structures patterned on them with metal and fluidic feedthroughs. A variety of getters and sealing designs are disclosed to vary the pressure of the microcavity by

Douglas Sparks; Jacob Trevino; Sonbol Massoud-Ansari; Nader Najafi

2006-01-01

282

Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design  

NASA Technical Reports Server (NTRS)

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

2014-01-01

283

Wafer-Level Encapsulation and Sealing of Electrostatic HARPSS Transducers  

E-print Network

Wafer-Level Encapsulation and Sealing of Electrostatic HARPSS Transducers Siavash Pourkamali* and Farrokh Ayazi School of Electrical and Computer Engineering, Georgia Institute of Technology Atlanta, GA-film wafer-level encapsulation technique for packaging and CMOS integration of MEMS sensors and actuators

Ayazi, Farrokh

284

Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint  

SciTech Connect

This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

Rupnowski, P.; Sopori, B.

2008-05-01

285

Defect detection in unpolished Si wafers by digital shearography  

Microsoft Academic Search

Defects in silicon wafers have been of great scientific and technological interest since before the earliest days of the silicon transistor. Recently much attention has been focused on crystal originated pits on the polished surface of the wafer. These defects have been shown to contribute to gate dielectric breakdown. The present work relates to surface and\\/or subsurface defect inspection systems

Ganesha Udupa; B. K. A. Ngoi; H. C. Freddy Goh; M. N. Yusoff

2004-01-01

286

Determination of bending stress of Si wafer using concentrated load  

Microsoft Academic Search

The technique of concentrated load with a simple O-ring supporter is used to measure the deflection of Si wafers. The load varies so that the ratio of the deflection to the wafer thickness changes from 0 to 1. For some samples, this ratio goes up to 1.4 at which the samples are fractured. It is observed in the experiment that

L. D. Chen; M. J. Zhang; S. Zhang

1994-01-01

287

Influence of bonding atmosphere on low-temperature wafer bonding  

Microsoft Academic Search

The influence of bonding atmosphere was investigated for the wafer bonding at 25~200°C using a surface activated bonding method. The results of the analysis of activated Si surfaces under different vacuum background and the residual gases in vacuum before and after Ar fast atom beam irradiation is reported. Based on the analysis, bonding of Si wafers in nitrogen atmosphere is

Ying-Hui Wang; Tadatomo Suga

2010-01-01

288

Improved method of dicing integrated circuit wafers into chips  

NASA Technical Reports Server (NTRS)

Method employing a pressure chamber is used for dicing semiconductor single-crystal wafers, containing integrated circuits, into small chips along pre-scribed lines. Uniform bending of the scribed wafer over the convex surface of a perforated hemisphere, breaks it cleanly into individual chips without damaging the circuits.

Litant, I.; Scapicchio, A. J.

1969-01-01

289

Particulate contamination removal from wafers using plasmas and mechanical agitation  

DOEpatents

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Selwyn, Gary S. (Los Alamos, NM)

1998-01-01

290

Analysis of wafer stresses during millisecond thermal processing  

Microsoft Academic Search

A flash lamp has been used to uniformly anneal large wafers with diameters approaching 100 mm. The equipment applies a pulse, with duration of 3-20 ms, resulting in large transient thermal gradients in the wafer. In this paper, we present separate models of the thermal reaction of this process and its effect upon the mechanical behavior, in order to predict

M. P. Smith; K. A. Seffen; R. A. McMahon; M. Voelskow; W. Skorupa

2006-01-01

291

Analysis of wafer stresses during millisecond thermal processing  

Microsoft Academic Search

A flash lamp has been used to uniformly anneal large wafers with diameters approaching 100 mm. The equipment applies a pulse, with duration of 3–20 ms, resulting in large transient thermal gradients in the wafer. In this paper, we present separate models of the thermal reaction of this process and its effect upon the mechanical behavior, in order to predict

M. P. Smith; K. A. Seffen; R. A. McMahon; M. Voelskow; W. Skorupa

2006-01-01

292

Wafer-level calibration of stress sensing test chips  

Microsoft Academic Search

Piezoresistive sensors are a powerful tool for measurement of surface stress states in semiconductor die used within electronic packages. A new wafer-level method for calibrating on-chip piezoresistive stress sensors is presented, in which an entire circular silicon wafer (potentially containing hundreds of fabricated stress sensing chips) is supported on its edge as a simply supported plate and loaded using a

J. C. Suhling; R. A. Cordes; Y. L. Kang; R. C. Jaeger

1994-01-01

293

Contactless Characterization of Silicon Wafers Dieter K. Schroder  

E-print Network

strength thin film. The sensor electrode is held above the wafer by a porous ceramic air bearing, which provides for a very stable distance from the wafer as long as the load on the air bearing does not change, shown in Fig. 1. Pressurizing a bellows provides the controlled load. As air escapes through the porous

Schroder, Dieter K.

294

Laser induced stress wave thermometry applied to silicon wafer processing  

E-print Network

during rapid thermal processing (RTP) of silicon wafers. Wafers of 0.76mm thickness and 200 mm diameter are used in the study at temperatures ranging from 23 to 400°C. The waveguide modes generated are identified with the aid of the orthotropic...

Rabroker, George Andrew

2000-01-01

295

Meta-analysis of stapled hemorrhoidopexy vs LigaSure hemorrhoidectomy  

PubMed Central

AIM: To compare outcome of stapled hemorrhoidopexy (SH) vs LigaSure hemorrhoidectomy (LH) by a meta-analysis of available randomized controlled trials (RCTs). METHODS: Databases, including PubMed, EMBASE, the Cochrane Library, and the Science Citation Index updated to December 2012, were searched. The main outcomes measured were operating time, early postoperative pain, postoperative urinary retention and bleeding, wound problems, gas or fecal incontinence, anal stenosis, length of hospital stay, residual skin tags, prolapse, and recurrence. The meta-analysis was performed using the free software Review Manager. Differences observed between the two groups were expressed as the odds ratio (OR) with 95%CI. A fixed-effects model was used to pool data when statistical heterogeneity was not present. If statistical heterogeneity was present (P < 0.05), a random-effects model was used. RESULTS: The initial search identified 10 publications. After screening, five RCTs published as full articles were included in this meta-analysis. Among the five studies, all described a comparison of the patient baseline characteristics and showed that there was no statistically significant difference between the two groups. Although most of the analyzed outcomes were similar between the two operative techniques, the operating time for SH was significantly longer than for LH (P < 0.00001; OR= -6.39, 95%CI: -7.68 - -5.10). The incidence of residual skin tags and prolapse was significantly lower in the LH group than in the SH group [2/111 (1.8%) vs 16/105 (15.2%); P = 0.0004; OR= 0.17, 95%CI: 0.06-0.45). The incidence of recurrence after the procedures was significantly lower in the LH group than in the SH group [2/173 (1.2%) vs 13/174 (7.5%); P = 0.003; OR= 0.21, 95%CI: 0.07-0.59]. CONCLUSION: Both SH and LH are probably equally valuable techniques in modern hemorrhoid surgery. However, LigaSure might have slightly favorable immediate postoperative results and technical advantages. PMID:23922480

Yang, Jun; Cui, Pei-Jing; Han, Hua-Zhong; Tong, Da-Nian

2013-01-01

296

Facile and Scalable Route to Wafer-Size Patterned Graphene  

NASA Astrophysics Data System (ADS)

Graphene-based nanoelectronic devices are promising as an alternative to silicon-based nanodevices in the future. Producing graphene sheets and patterned structures as device building blocks is an important step to graphene-based nanodevice fabrication. It is highly desirable to assemble graphene sheets at specific locations and into desired patterns on large scale. Several methods have been reported for patterning graphene nanostructure. However, all of these methods involve either sophisticated instruments or were rather high cost and low throughput, hindering their large-scale fabrication and practical applications. We developed a simple and efficient method to covalently immobilize graphene on silicon wafers. Patterned structures were fabricated where the feature sizes could be conveniently controlled from micron to millimeters. The formation of patterned graphene layers was confirmed by Raman spectroscopy, optical and atomic force microscopy. Evidence of covalent bond formation was provided by X-ray photoelectron spectroscopy. In addition, this method can be readily applied to other substrates. This approach represents a new route for solution-based graphene fabrication, allowing graphene sheets and patterned graphene structures to be fabricated on virtually any surface.

Liu, Li-Hong; Yan, Mingdi

2010-03-01

297

Reduction of Thermal Conductivity in Wafer-Bonded Silicon  

SciTech Connect

Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

2006-11-27

298

Approaching new metrics for wafer flatness: an investigation of the lithographic consequences of wafer non-flatness  

NASA Astrophysics Data System (ADS)

Flatness of the incoming silicon wafer is one major contributor to the ultimate focusing limitation of modern exposure tools. Exposure tools are designed to chuck wafers without creating non-flatness and then use focus control to follow as closely as possible the chucked wafer front surface topography. The smaller size of the exposure slit in a step-and-scan exposure tool, as compared to the previous generation full-field stepper tool, helps minimize the impact of chucked wafer non-flat topography. However, to maintain high throughput and improve critical dimension uniformity (CDU) at sub-wavelength line-widths requires continuous improvement in the incoming silicon wafer flatness. In this paper we report extensive experimental results that review existing wafer flatness metrics and propose the addition of a new metric. The new metric emulates the scanning motion of exposure by integrating the defocus that each point on the wafer experiences during exposure. We show that this method is in better spatial agreement with measured defocus in step-and-scan exposure tools. Simple metrics of moving average (MA) defocus prediction analysis will be defined and shown to correlate very well to post exposure defocus data. These experiments were enabled by the creation of special 300-nm wafers by MEMC. These special wafers include sites with a wide variation in flatness. Prior to exposure the wafers were measured with a high-resolution optical flatness metrology tool (WaferSight by ADE) to obtain industry standard thickness variation (flatness) data. Incoming wafer flatness data is used to predict wafer suitability for lithography at the desired device geometry node (e.g., 90 nm). The flatness data was processed and characterized using both standard metrics (SFQR) and the new MA analysis. The relationship between the industry standard metric (SFQR) and similar metrics applied to MA analysis will be presented. Full two-dimensional maps are used to present spatial correlations and permit simple physical insights into the flatness data sets. Measurements of chucked wafer flatness were made on the same wafers using ASML TWINSCAN in-line metrology. These measurements correlate very well to thickness-based flatness. Un-chucked wafer flatness metrics (SFQR and MA) are shown to correlate well to post exposure defocus data when an appropriate site size is used. This result is discussed in relationship to the industry-accepted practice of specifying un-chucked wafer flatness. Lithography performance tests were made to prove the relevance of the different flatness metrics. The same special wafers are used for lithography performance tests. These tests achieve excellent correlation between post-exposure full-wafer focus control results and predictions based on both SFQ (industry standard) and MA re-mapping of the flatness data. The relationship between measured critical dimension (CD) and defocus is also explored. Point-by-point analysis of CD residual versus measured defocus data nicely follows a Bossung curve. We also show that residual CD values predicted from defocus correlate well with measured values. These experiments confirm the application of industry standard wafer flatness measurements to step-and-scan lithography when appropriately using current metrics. They also present the potential for improved metrics based on the MA defocus prediction analysis to help drive continuous improvement of wafer flatness for advanced step-and-scan lithography.

Valley, John F.; Poduje, Noel; Sinha, Jaydeep; Judell, Neil; Wu, Jie; Boonman, Marc; Tempelaars, Sjef; van Dommelen, Youri; Kattouw, Hans; Hauschild, Jan; Hughes, William; Grabbe, Alexis; Stanton, Les

2004-05-01

299

Mixing And Matching Of Wafer Steppers And Wafer Scanners For Cost-Effective, High-Volume Device Production  

NASA Astrophysics Data System (ADS)

The mixing and matching of Step-and-Repeat Alignment systems and wafer scanners is a viable method of providing the high levels of overlay accuracy and resolution that are now required in the manufacturing of the most advanced devices such as 1 MBIT DRAMs. At the same time, significant reduction of the production costs, especially on large wafers, are realized. The utilization of scanner systems allows very high wafer throughput, in excess of 100 wafers/hour. The utilization of Step-and-Repeat Alignment systems allows the reduction of overlay errors to less than 0.3 micron (98%). The mixing of equipment has been enhanced by the introduction of Universal Mix-and-Match Prealigners on the Micralign scanner systems. These prealigners are capable of simulating the performance of any Step-and-Repeat Alignment system prealigner by the use of wafer edge mapping techniques and special prealigner simulation algorithms in software. Using these prealigners, device arrays and alignment keys are accurately positioned on the wafers. This allows the implementation of automatic alignment systems and the maintenance of high wafer throughputs on the scanner systems. New developments in metrology equipment now allow the use of automated overlay measurement systems for the mapping of overlay errors on wafers. The extraction of equipment overlay correction factors is now possible. The implementation of such systems will allow <= 0.4-micron overlay processes, such as 1 MBIT DRAMs, to be run routinely on mixed equipment.

Sewell, Harry; Gansfried, Myles

1986-08-01

300

MAPPER alignment sensor evaluation on process wafers  

NASA Astrophysics Data System (ADS)

MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing. In order to reduce costs and to minimize the footprint of this tool a new alignment sensor has been developed; based on technologies used for DVD optical heads. A wafer with an alignment mark is scanned with the sensor, resulting in an intensity pattern versus position. From this pattern the mark position can be calculated. Evaluations have been made over the performance of this type of sensor using different mark designs at several lithography process steps for FEOL and BEOL manufacturing. It has been shown that sub-nanometer reproducibility (3? std) of alignment mark readings can be achieved while being robust against various process steps.

Vergeer, N.; Lattard, L.; de Boer, G.; Couweleers, F.; Dave, D.; Pradelles, J.; Bustos, J.

2013-03-01

301

Piezoresistive stress sensors on (110) silicon wafers  

NASA Technical Reports Server (NTRS)

Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

Kang, Y. L.; Suhling, J. C.; Jaeger, R. C.

1992-01-01

302

Overlay Tolerances For VLSI Using Wafer Steppers  

NASA Astrophysics Data System (ADS)

In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his merchandise appear as attractive as possible, the lithographer is frequently placed in the position of having to explain subtle issues in order to justify his decisions. It is the purpose of this paper to provide that explanation.

Levinson, Harry J.; Rice, Rory

1988-01-01

303

Comparison and Efficacy of LigaSure and Rubber Band Ligature in Closing the Inflamed Cecal Stump in a Rat Model of Acute Appendicitis  

PubMed Central

Safety of either LigaSure or rubber band in closing inflamed appendiceal stump in acute appendicitis has been less investigated. In this study, cecal ligation followed by resecting inflamed cecum was performed to mimic appendectomy in a rat model of acute appendicitis. Rats were sacrificed immediately (Group A) and 7 days (Group B) after cecal resection, respectively. The cecal stumps were closed by silk ligature (S), 5?mm LigaSure (L), or rubber band (R). Seven days after cecal resection, the LigaSure (BL) and silk subgroups (BS) had significantly less intra-abdominal adhesion and better laparotomy wound healing than rubber band subgroup (BR). The initial bursting pressure at cecal stump was comparable among the three methods; along with tissue healing process, both BL and BS provided a higher bursting pressure than BR 7 days after appendectomy. BL subgroup had more abundant hydroxyproline deposition than BS and BR subgroup. Furthermore, serum TNF-? in BR group kept persistently increasing along with time after cecal resection. Thus, the finding that LigaSure but not rubber band is safe in sealing off the inflamed cecal stump in rat model of acute appendicitis suggests the possibility of applying LigaSure for appendectomy via single port procedure or natural orifice transluminal endoscopic surgery (NOTES). PMID:25699264

Yeh, Chun-Chieh; Jan, Chia-Ing; Yang, Horng-Ren; Jeng, Long-Bin; Su, Wen-Pang

2015-01-01

304

Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch  

NASA Astrophysics Data System (ADS)

In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

2012-05-01

305

Infrared study of Si surfaces and bonded Si wafers  

NASA Astrophysics Data System (ADS)

Attenuated total reflection (ATR) spectra of hydrophobic and hydrophilic Si wafers, Si wafers with thermally grown 0268-1242/14/1/009/img2 layers and bonded Si wafers were investigated. It was found that the surface of the as-prepared hydrophobic wafer is terminated by hydrogen and water molecules while the IR spectra of the hydrophilic wafer demonstrate only the presence of water molecules at the surface. ATR spectra of Si wafers covered by a thermally grown 0268-1242/14/1/009/img2 layer exhibit a number of the strong absorption bands. The analysis of ATR spectra and the single-transmission spectra allows these modes to be assigned to combinational phonon bands in 0268-1242/14/1/009/img2. The use of a double-bonded Si structure allows the influence of the outer surfaces to be excluded. The wafer bonding leads to the appearance of siloxane and hydroxyl groups at the buried interface whose absorption bands were observed in ATR spectra.

Milekhin, A.; Friedrich, M.; Hiller, K.; Wiemer, M.; Gessner, T.; Zahn, D. R. T.

1999-01-01

306

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.  

PubMed

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. PMID:24700434

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

307

A phase 3 trial of local chemotherapy with biodegradable carmustine (BCNU) wafers (Gliadel wafers) in patients with primary malignant glioma.  

PubMed Central

A previous placebo-controlled trial has shown that biodegradable 1,3-bis (2-chloroethyl)-1-nitrosourea (BCNU) wafers (Gliadel wafers) prolong survival in patients with recurrent glioblastoma multiforme. A previously completed phase 3 trial, also placebo controlled, in 32 patients with newly diagnosed malignant glioma also demonstrated a survival benefit in those patients treated with BCNU wafers. Because of the small number of patients in that trial, a larger phase 3 trial was performed to confirm these results. Two hundred forty patients were randomized to receive either BCNU or placebo wafers at the time of primary surgical resection; both groups were treated with external beam radiation postoperatively. The two groups were similar for age, sex, Karnofsky performance status (KPS), and tumor histology. Median survival in the intent-to-treat group was 13.9 months for the BCNU wafer-treated group and 11.6 months for the placebo-treated group (log-rank P -value stratified by country = 0.03), with a 29% reduction in the risk of death in the treatment group. When adjusted for factors affecting survival, the treatment effect remained positive with a risk reduction of 28% ( P = 0.03). Time to decline in KPS and in 10/11 neuroperformance measures was statistically significantly prolonged in the BCNU wafer-treated group ( P wafer-treated group vs. 0.8% in the placebo-treated group) and intracranial hypertension (9.1% in the BCNU wafer-treated group vs. 1.7% in the placebo group). This study confirms that local chemotherapy with BCNU wafers is well tolerated and offers a survival benefit to patients with newly diagnosed malignant glioma. PMID:12672279

Westphal, Manfred; Hilt, Dana C.; Bortey, Enoch; Delavault, Patrick; Olivares, Robert; Warnke, Peter C.; Whittle, Ian R.; Jääskeläinen, Juha; Ram, Zvi

2003-01-01

308

Monitoring Dielectric Thin-Film Production on Product Wafers Using Infrared Emission Spectroscopy  

SciTech Connect

Monitoring of dielectric thin-film production in the microelectronics industry is generally accomplished by depositing a representative film on a monitor wafer and determining the film properties off line. One of the most important dielectric thin films in the manufacture of integrated circuits is borophosphosilicate glass (BPSG). The critical properties of BPSG thin films are the boron content, phosphorus content and film thickness. We have completed an experimental study that demonstrates that infrared emission spectroscopy coupled with multivariate analysis can be used to simultaneous y determine these properties directly from the spectra of product wafers, thus eliminating the need of producing monitor wafers. In addition, infrared emission data can be used to simultaneously determine the film temperature, which is an important film production parameter. The infrared data required to make these determinations can be collected on a time scale that is much faster than the film deposition time, hence infrared emission is an ideal candidate for an in-situ process monitor for dielectric thin-film production.

NIEMCZYK,THOMAS M.; ZHANG,SONGBIAO; HAALAND,DAVID M.

2000-12-18

309

Nanoscale friction and wear properties of silicon wafer under different lubrication conditions  

NASA Astrophysics Data System (ADS)

The nanoscale friction and wear properties of single crystal silicon wafer under different lubrication conditions are studied in this paper. The experiments were performed with Si3N4 ball sliding on the surface of silicon wafer under four different lubrication conditions: dry friction, water lubrication, hydrogen peroxide lubrication and the static hydrogen peroxide dry friction. The results from the experiments have been analyzed showing the different friction and wear properties of the silicon wafer in different lubrication conditions. It is concluded that the wear rates under the water lubrication and under the hydrogen peroxide lubrication are both small, the chemical reactions are facilitated by the mechanical processes when the load and the sliding speed reach certain levels. This is mainly resulted by the enhanced lubricant performance with the formed silicon hydroxide Si(OH)4 film. Under the water lubrication, the wear is found in a way of material removed in molecule scale. Under the hydrogen peroxide lubrication, the wear is mainly caused by the spalling of micro-cracks. Under the dry friction condition, the wear is found being adhesive wear. And under the static peroxide dry friction, the wear is prevailing adhesive wear. These results are essential and valuable to the development of the efficient and environmental-friendly slurry for the chemical mechanical polishing (CMP) process.

Chen, Xiaochun; Zhao, Yongwu; Wang, Yongguang; Zhou, Hailan; Ni, Zhifeng; An, Wei

2013-10-01

310

Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

2012-11-01

311

Application of EEM fluorescence spectroscopy in understanding of the "LIGA" phenomenon in the Bay of Biscay (France)  

NASA Astrophysics Data System (ADS)

Marine mucilage is present in all oceans over the world, and in particular in the Mediterranean Sea and in the Pacific Ocean. Surface water warming and hydrodynamic processes can favor the coalescence of marine mucilage, large marine aggregates representing an ephemeral and extreme habitat for biota. DOM is a heterogeneous, complex mixture of compounds, including extracellular polymeric substances (EPS), with wide ranging chemical properties and it is well known to interact with pollutants and to affect their transport and their fate in aquatic environment. The LIGA French research program focuses on tracing colloidal dissolved organic matter (DOM) sources and cycling in the Bay of Biscay (South Western French coast). This ephemeral phenomenon (called "LIGA" in the South West of France) has been observed more than 750 times since 2010. It presents a great ecological impact on marine ecosystems and has been shown to be concomitant with the development of pathogen organisms. A one-year intensive survey of fluorescent DOM was undertaken. From April 2013 until May 2014, water samples were monthly collected from the Adour River (main fresh water inputs) and from 2 sites in the Bay of Biscay at 3 depths of the water column (surface water, at the maximum of chlorophyll-a, and deep water). Moreover, intensified samplings took place from the appearance of the phenomenon twice a week during 4 weeks. UV/visible absorbance and excitation emission matrix (EEM) fluorescence spectroscopy combined with PARAFAC and PCA analyses have been used to characterize colloidal DOM in the Bay of Biscay in order to estimate DOM sources as well as spatial and temporal variability of DOM properties. The preliminary results, obtained for about 70 samples of this survey, have already highlighted spatial and temporal variations of DOM optical properties and a peculiar fluorescent component (exc300nm/em338nm) was detected while the LIGA phenomenon arises. The appearance of this specific fluorescence signal seems to be correlated with high freshwater and terrestrial DOM inputs combined with physical forcing (flows, swell) as well as a rise in temperature and sunshine. This work already allowed us to identify different sources of colloidal DOM in the Bay of Biscay and highlighted a specific fingerprint of the LIGA phenomenon. The combination of EEM fluorescence spectroscopy with PARAFAC and PCA analyses appears thus to be a very powerful tool for the long term monitoring of such a phenomenon and would be very useful for a better understanding of the biogeochemical processes in marine environments and of the marine colloidal DOM ecodynamics.

Parot, Jérémie; Susperregui, Nicolas; Rouaud, Vanessa; Dubois, Laurent; Anglade, Nathalie; Parlanti, Edith

2014-05-01

312

Characterization and management of wafer stress for various pattern densities in 3D integration technology  

Microsoft Academic Search

In the current 3D integration technology, the control of wafer warp is needed to ensure uniform photolithography, good bonding areas and other major processes that requires flat wafer surface. In this paper, we found out that the wafer warpage was increased with increasing TSV density. The highest wafer warpage was observed after Cu annealing base on step by step warpage

X. F. Pang; T. T. Chua; H. Y. Li; E. B. Liao; W. S. Lee; F. X. Che

2010-01-01

313

Residual Stress Analysis in Thin Device Wafer Using Piezoresistive Stress Sensor  

Microsoft Academic Search

In this paper, piezoresistive stress sensors have been used to analyze the residual stress in thin device wafers. For the analysis, device wafers having piezoresistive stress sensors were fabricated. The stress sensors were then calibrated to determine the piezoresistive coefficients. The analysis of residual stress in device wafers was carried out after thinning the device wafers to three different thicknesses

Aditya Kumar; Xiaowu Zhang; Qing Xin Zhang; Ming Chinq Jong; Guanbo Huang; Lee Wen Sheng Vincent; Vaidyanathan Kripesh; Charles Lee; John H. Lau; Dim Lee Kwong; Venky Sundaram; Rao R. Tummula; Georg Meyer-Berg

2011-01-01

314

High productivity multiple DUT CV test for MEMS microphone wafer with automatic correction  

Microsoft Academic Search

Productivity in MEMS wafer process is getting more and more important as mass production on 200 mm wafer is increasing. Multiple DUT parallel CV test is a high productive way for MEMS Microphone wafer test process, however, in case of the one of two electrodes is connected to the wafer substrate with some contact resistance, interference among DUTs has an

S. Inuzuka

2010-01-01

315

RF MEMS Switch with Wafer Level Package Utilizing Frit Glass Bonding  

Microsoft Academic Search

This paper reports experimental results of RF characteristics up to 20 GHz of a RF MEMS switch applied with wafer level packaging. A glass wafer is used as a package substrate on which frit glass is printed as material to seal the MEMS devices. The package wafer is bonded to a device wafer, which consists of actuators and base substrates.

M. Fujii; I. Kimura; T. Satoh; K. Imanaka

2002-01-01

316

Electrochemical method for defect delineation in silicon-on-insulator wafers  

DOEpatents

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, Terry R. (Albuquerque, NM); Jones, Howland D. T. (Albuquerque, NM); Kelly, Michael J. (Albuquerque, NM); Medernach, John W. (Albuquerque, NM); Stevenson, Joel O. (Albuquerque, NM); Tsao, Sylvia S. (Albuquerque, NM)

1991-01-01

317

Distribution of polishing times for a wafer with different patterned polishing pads during CMP and CCMP  

Microsoft Academic Search

During chemical-mechanical polishing (CMP), the polishing pad is placed under a wafer and it completely covers the wafer. Compensating CMP (CCMP) decreases the polishing pad wear and enhances end-point detection (EDP). In CCMP, a polishing pad is placed above the wafer and does not completely cover the wafer. Regardless of CMP or CCMP, there are grooved patterns on the polishing

Zone-Ching Lin; Chein-Chung Chen

2010-01-01

318

Evaluation of Stresses in Thin Device Wafer using Piezoresistive Stress Sensor  

Microsoft Academic Search

In this work, piezoresistive stress sensors have been used to evaluate the stresses in thin device wafer. For the evaluation, device wafers having piezoresistive stress sensors were fabricated. The stress sensors were then calibrated to determine the piezoresistive coefficients. The evaluation of stresses in device wafer was carried out after thinning the device wafers to three different thicknesses ranging from

Aditya Kumar; Xiaowu Zhang; Q. X. Zhang; M. C. Jong; G. B. Huang; L. Vincent; V. Kripesh; C. Lee; J. H. Lau; D. L. Kwong; V. Sundaram; R. R. Tummula; G. Meyer-Berg

2008-01-01

319

Effect of handling stress on resonance ultrasonic vibrations in thin silicon wafers  

Microsoft Academic Search

Resonance Ultrasonic Vibration (RUV) metrology offers a sensitive non-destructive real-time solution to silicon wafer crack detection. The stresses generated in the wafers by the handling device used in the RUV method may have a significant influence on the effectiveness of this method, particularly for thinner wafers. The handling stresses produced by different designs of the vacuum wafer holders and their

Hao Wu; Shreyes N. Melkote; A. Belyaev; I. Tarasov; Deven Cruson; S. Ostapenko

2010-01-01

320

9nm node wafer defect inspection using visible light  

NASA Astrophysics Data System (ADS)

Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

Zhou, Renjie; Edwards, Chris; Popescu, Gabriel; Goddard, Lynford L.

2014-04-01

321

Multiple internal reflection spectroscopy of bonded silicon wafers  

NASA Astrophysics Data System (ADS)

Interfaces of bonded hydrophilic and hydrophobic wafer pairs are studied by multiple internal reflection spectroscopy after annealing at 1100 °C. Si H x and SiO H stretching modes are still present in bonded hydrophilic wafers. Interfaces of bonded hydrophobic wafers, prepared by joining HF-etched surfaces without de-ionized water rinsing, are characterized by the dominance of hydrides (SiH, SiH2, SiH3). Their concentration is about 100 times higher than for bonded hydrophilic wafers. Comparison with the ATR-spectra of HF-treated surfaces showed appreciable shifts in the peak positions indicating that Si H bonds might be involved in the bonding process.

Reiche, M.; Hopfe, S.; Gösele, U.; Tong, Q. Y.

1995-07-01

322

Proceedings of the Low-Cost Solar Array Wafering Workshop  

NASA Technical Reports Server (NTRS)

The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

Morrison, A. D.

1982-01-01

323

Wafer bonding : mechanics-based models and experiments  

E-print Network

Direct wafer bonding has emerged as an important technology in the manufacture of silicon-on-insulator substrates (SOI), microelectromechanical systems (MEMS), and three-dimensional integrated circuits (3D IC's). While the ...

Turner, Kevin Thomas, 1977-

2004-01-01

324

A ultra-high-vacuum wafer-fusion-bonding system.  

PubMed

The design of heterojunction devices is typically limited by material integration constraints and the energy band alignment. Wafer bonding can be used to integrate material pairs that cannot be epitaxially grown together due to large lattice mismatch. Control of the energy band alignment can be provided by formation of interface dipoles through control of the surface chemistry. We have developed an ultra-high-vacuum system for wafer-fusion-bonding semiconductors with in situ control and measurement of surface properties relevant to interface dipoles. A wafer-fusion-bonding chamber with annealing capabilities was integrated into an ultra-high-vacuum system with a sputtering chamber and an x-ray photoelectron spectroscopy system for preparing and measuring the surface chemistry of wafers prior to bonding. The design of the system along with initial results for the fusion-bonded InGaAs/Si heterojunction is presented. PMID:22667658

McKay, Kyle; Wolter, Scott; Kim, Jungsang

2012-05-01

325

Characterization of hydrophobic bonded silicon wafers  

NASA Astrophysics Data System (ADS)

Direct bonding of silicon-to-silicon has been recognized as an interesting method for creating novel device geometries and structures and it has so far been used for the preparation of power devices and sensors. The influence of the bonded interface on electrical performance is then of great interest. In this contribution the interface region of hydrophobic bonded n-type silicon wafers have been studied and a comparison is made between samples before and after an exposure to low doses of 9.5 MeV protons to see the effect of the interface on point defect kinetics. The samples were studied using current-voltage (IV), capacitance-voltage (CV), deep level transient spectroscopy (DLTS), secondary ion mass spectrometry (SIMS) and scanning electron microscopy (SEM). During reverse bias there is a dramatic increase in leakage current when the depletion region reaches the bonded interface region. Due to the high leakage currents DLTS measurements could not be performed directly at the interface. However, in contrast to previous studies, no deep levels are discovered in the interface region of non-irradiated samples and, furthermore, no influence of the bonded interface on the concentration and depth distribution of irradiation induced defects could be detected. This suggests that the irradiation induced defects are unaffected by the bonded interface. At the interface a boron peak is detected by SIMS.

Keskitalo, Niclas; Tiensuu, Stefan; Hallén, Anders

2002-01-01

326

Arthroscopic wafer procedure for ulnar impaction syndrome.  

PubMed

Ulnar impaction syndrome is abutment of the ulna on the lunate and triquetrum that increases stress and load, causing ulnar-sided wrist pain. Typically, ulnar-positive or -neutral variance is seen on a posteroanterior radiograph of the wrist. The management of ulnar impaction syndrome varies from conservative, symptomatic treatment to open procedures to shorten the ulna. Arthroscopic management has become increasingly popular for management of ulnar impaction with ulnar-positive variance of less than 3 mm and concomitant central triangular fibrocartilage complex tears. This method avoids complications associated with open procedures, such as nonunion and symptomatic hardware. The arthroscopic wafer procedure involves debridement of the central triangular fibrocartilage complex tear, along with debridement of the distal pole of the ulna causing the impaction. Debridement of the ulna arthroscopically is taken down to a level at which the patient is ulnar neutral or slightly ulnar negative. Previous studies have shown good results with relief of patient symptoms while avoiding complications seen with open procedures. PMID:24749031

Colantoni, Julie; Chadderdon, Christopher; Gaston, R Glenn

2014-02-01

327

Performance of Ultra Hard Carbon Wear Coatings on Microgears Fabricated by Liga  

SciTech Connect

Stiction and friction are of concern for the reliable, long-term application of Ni-alloy micromachines. We have found that the application of a 30-70 nm hard carbon coating produces a significant reduction in the friction coefficient and wear rate of electroformed Ni substrates in reciprocating sliding contact under simulated MEMS operating conditions. To evaluate the performance of coated components, a series of 70-pm-thick microgears ranging in diameter from 0.2 to 2.2 mm were fabricated from electroformed Ni via standard LIGA processes and fixtured on posts in preparation for the coating procedure. A pulsed vacuum- arc deposition process was used to deposit a carbon coating on the gears with the plasma incident at a shallow angle to the gears' top surface. A sample bias of -2 keV was used in order to produce a coating with relatively low stress and good adhesion while maintaining high hardness. This coating process is known to be somewhat comformal to the component surfaces. The coating uniformity, particularly in the high-aspect-ratio areas between the gear teeth, was evaluated with micro-Raman spectroscopy. It is shown that the coating can be applied uniformly on the top gear surface. Between the gear teeth the coating was the same thickness as on top of the gear down to a point 50 ~m below the top surface. Below that point (i.e. between 50 and 70 Lm), the coating thickness is somewhat thinner, but is still present. These results demonstrate that it is possible to a deposit hard carbon coating on microgears to reduce friction and wear in micromachines.

Ager III, J.W.; Brown, I.G.; Christenson, T.R.; Dugger, M.T.; Follstaedt, D.M.; Knapp, J.A.; Monteiro, O.R.

1998-12-18

328

Silicon wafer direct bonding without hydrophilic native oxides  

NASA Astrophysics Data System (ADS)

Silicon wafer direct bonding was accomplished between two surfaces which had no hydrophilic native oxide layers. Prior to bonding, two wafers were dipped in conv-HF solution (approximately = 49% aq.) to remove the native oxide layers and then immersed in deionized water. It is suggested that the OH groups which substitute the F atoms terminated on the small portion of the surface play an important role in this conv-HF-treated bonding.

Himi, Hiroaki; Matsui, Masaki; Fujino, Seiji; Hattori, Tadashi

1994-01-01

329

A wafer-level approach to device lifetesting  

Microsoft Academic Search

An innovative wafer-level methodology is introduced and used to determine the thermal activation energies of TriQuint semiconductor’s TQPED devices. Activation energies of 2.77eV and 2.44eV are calculated for the depletion-mode and enhancement-mode devices, respectively. This accelerated lifetest technique utilizes a special reliability test structure that includes an on-wafer heating element around the device under test (DUT). The heating element easily

Dorothy June M. Hamada; William J. Roesch

2008-01-01

330

Automated reticle inspection data analysis for wafer fabs  

NASA Astrophysics Data System (ADS)

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-03-01

331

Automated reticle inspection data analysis for wafer fabs  

NASA Astrophysics Data System (ADS)

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2008-10-01

332

Automated reticle inspection data analysis for wafer fabs  

NASA Astrophysics Data System (ADS)

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

333

Thermomechanical analysis of a wafer level packaging by induction heating  

Microsoft Academic Search

In this paper, a non-linear and one-directional coupled finite element framework has been implemented to simulate induction heating process of wafer-level packaging. Based on numerical results of induction heating, thermally-caused warpages and stresses of the single-sided ceramic wafer have been evaluated. Some primary experiments have also been conducted to verify the numerical method. Using three-dimensional models, the temperature distribution, thermally-caused

Wenming Liu; Mingxiang Chen; Yanyan Xi; Changyong Lin; Sheng Liu

2008-01-01

334

Si-to-Si wafer bonding using evaporated glass  

Microsoft Academic Search

Anodic bonding of Si to Si four inch wafers using evaporated glass was performed in air at temperatures ranging from 300°C to 450°C. Although annealing of Si\\/glass structures around 340°C for 15 minutes eliminates stress, the bonded wafer pairs exhibit compressive stress. Pull testing revealed maximum bond strengths greater than 50 N\\/mm2 and an average bond strength of 30 N\\/mm2

R. de Reus; M. Lindahl

1997-01-01

335

Wafer Pattern Defect Detection: An Automatic Inspection Technique  

NASA Astrophysics Data System (ADS)

A system to automatically inspect wafers for pattern defects has recently been developed. With this apparatus, the patterns of two neighboring chips are converted into video signals, which are then electronically compared by sophisticated hybrid circuitry to determine any differences between them. The discrepancies, if any, are recognized as defects. The inspection results are processed with a built-in microcomputer and the defect coordinates are stored in memory. By accessing them, the wafer is moved into exact position for post-inspection confirmation and close examination of each defect by the operator through a microscope. The defective wafer pattern is also displayed on a video monitor. In addition, it is possible to draw a defect map by utilizing an X-Y plotter interfaced to the inspection system. The system is equipped with two inspection modes for maximum versatility. The video signal can be generated by either bright-field or dark-field imaging methods. The user may therefore select the mode most compatible to a specific wafer and its requirements. Typical applications of this system include: - to detect pattern defects on the finished wafer (after photoresist developing an e, etching) that may have occured during the various production processes. - to detect repeating defects resulting from inconsistencies on an arrayed reticle used in the wafer stepping process. (The importance of this feature will become increas-ingly evident as direct wafer steppers become the workhorses of the VLSI era.) - to monitor various processing factors, such as foreign particle contamination. The performance and efficiency of such an automatic wafer inspection system will undoubtedly lead to its replacing the current conventional method of manual microscopic examination by the human eye in the near future. This is supported by the inclusion of data collected by end users of this system.

Uchiyama, Yasushi; Awamura, Daikichi; Nakashima, Katsuyoshi

1983-11-01

336

Downgrade decision for control\\/dummy wafers in a fab  

Microsoft Academic Search

Control and dummy (C\\/D) wafers are indispensable materials used in a semiconductor fab. C\\/D wafers stored in a high-grade buffer can be downgraded to several low-grade buffers. The downgrade decision is to determine the amount to downgrade for each of these low-grade buffers. Previous literature solves the downgrade decision by considering only the instantaneous WIP information, which is a short-term

Muh-Cherng Wu; C. S. Chien; K. S. Lu

2005-01-01

337

Shape bifurcation of an elastic wafer due to surface stress  

Microsoft Academic Search

A geometrically nonlinear analysis was proposed for the deformation of a free standing elastically isotropic wafer caused\\u000a by the surface stress change on one surface. The link between the curvature and the change in surface stress was obtained\\u000a analytically from energetic consideration. In contrast to the existing linear analysis, a remarkable consequence is that,\\u000a when the wafer is very thin

Yan Kun; He Ling-hui; Liu Ren-huai

2003-01-01

338

Stress rate and proof-testing of silicon wafers  

NASA Technical Reports Server (NTRS)

Fracture mechanics test methods were applied to evaluate the proof-test characteristics of single-crystal silicon wafers. The results indicate that the strength distribution of silicon wafers is truncated by proof-testing. No subcritical crack growth occurred during proof-loading, as inferred from the lack of a stress-rate effect on strength. Mechanical proof-testing appears to be an effective method for eliminating weak samples before cell processing.

Chen, C. P.; Leipold, M. H.

1985-01-01

339

SUEX process optimization for ultra-thick high-aspect ratio LIGA imaging  

NASA Astrophysics Data System (ADS)

The focus of this paper is on the use of SUEX Thick Dry Film Sheet (TDFS) laminates which DJ DevCorp is developing as a thick resist material in optical and X-ray lithography. Preliminary thick dry film sheets up to 1mm thickness were successfully prepared and patterned at the CAMD X-ray beamlines and presented at HARMST 2007. Recently, new results have been published using SUEX resist sheets in UV lithography showing great market potential including plating molds for metal microparts, polymer MEMS, multilayer microfluidics structures, BioMEMS, medical devices, wafer level packaging processes, and displays. The SUEX TDFS are available in a range of thicknesses from 100?m to 1mm or more and are pre-cut into a number of standard wafer sizes. This new material is a modified epoxy formulation containing an antimony-free photo acid generator (PAG) prepared under a highly controlled solvent-less process which provides uniform coatings between two throw-away layers of protective polyester film. As part of our initial studies resist layers of 250, 500 and 1000?m were laminated onto regular silicon wafers using a hot roll laminator at a speed of 1ft/min at 75°C. The entire substrate preparation takes about 1 hour and with practice users can prepare up to 10 substrates in this time which are typically ready to use within 2 hours. In our efforts to develop a commercially viable product we have conducted experiments using standard equipment available at CAMD (Quintel UV aligner and CAMD XRLM 1 and 4 beamline). Initial X-ray exposure tests were done with a bottom dose ranging between 100 and 400 J/cm3 and a top/bottom dose ratio of less than 3 for sheets up to 2mm in thickness. Exposure time for typical conditions of the CAMD storage ring (ring current ranging between 100 and 160mA, beam lifetime of about 10hrs at 100mA ring current) is about 10-15min for a 4' wafer. After exposure the samples were immediately post exposure baked between 70°C and 110°C using a convection oven, taken out and cooled to RT then relaxed up to 3 days before development to reduce stress. Development was done in PGMEA for up to 3 hours for the 1000?m thick samples followed by a short IPA rinse and drying in air. Very high aspect ratios of 100 or more have been routinely patterned with nearly perfectly straight sidewalls (~1-1.5?m deviation for a 1mm tall structure) and excellent image fidelity.

Johnson, Donald W.; Goettert, Jost; Singh, Varshni; Yemane, Dawit

2011-04-01

340

Applications of the silicon wafer direct-bonding technique to electron devices  

NASA Astrophysics Data System (ADS)

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Furukawa, K.; Nakagawa, A.

1989-11-01

341

Applications of the silicon wafer direct-bonding technique to electron devices  

NASA Astrophysics Data System (ADS)

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Furukawa, K.; Nakagawa, A.

1990-01-01

342

High Throughput, Noncontact System for Screening Silicon Wafers Predisposed to Breakage During Solar Cell Production  

SciTech Connect

We describe a non-contact, on-line system for screening wafers that are likely to break during solar cell/module fabrication. The wafers are transported on a conveyor belt under a light source, which illuminates the wafers with a specific light distribution. Each wafer undergoes a dynamic thermal stress whose magnitude mimics the highest stress the wafer will experience during cell/module fabrication. As a result of the stress, the weak wafers break, leaving only the wafers that are strong enough to survive the production processes. We will describe the mechanism of wafer breakage, introduce the wafer system, and discuss the results of the time-temperature (t-T) profile of wafers with and without microcracks.

Sopori, B.; Rupnowski, P.; Basnyat, P.; Mehta, V.

2011-01-01

343

Scale  

ERIC Educational Resources Information Center

The common approach to scaling, according to Christopher Dede, a professor of learning technologies at the Harvard Graduate School of Education, is to jump in and say, "Let's go out and find more money, recruit more participants, hire more people. Let's just keep doing the same thing, bigger and bigger." That, he observes, "tends to fail, and fail…

Schaffhauser, Dian

2009-01-01

344

Epitaxial silicon carbide on a 6? silicon wafer  

NASA Astrophysics Data System (ADS)

The results of the growth of silicon-carbide films on silicon wafers with a large diameter of 150 mm (6?) by using a new method of solid-phase epitaxy are presented. A SiC film growing on Si wafers was studied by means of spectral ellipsometry, SEM, X-ray diffraction, and Raman scattering. As follows from the studies, SiC layers are epitaxial over the entire surface of a 150-mm wafer. The wafers have no mechanical stresses, are smooth, and do not have bends. The half-width of the X-ray rocking curve (FWHM?- ?) of the wafers varies in the range from 0.7° to 0.8° across the thickness layer of 80-100 nm. The wafers are suitable as templates for the growth of SiC, AlN, GaN, ZnO, and other wide-gap semiconductors on its surface using standard CVD, HVPE, and MBE methods.

Kukushkin, S. A.; Lukyanov, A. V.; Osipov, A. V.; Feoktistov, N. A.

2014-01-01

345

Chip-Scale Quadrupole Mass Filters for Portable Mass Spectrometry  

E-print Network

We report the design, fabrication, and characterization of a new class of chip-scale quadrupole mass filter (QMF). The devices are completely batch fabricated using a wafer-scale process that integrates the quadrupole ...

Cheung, Kerry

346

Neural network control of a plasma gate etch: Early steps in wafer-to-wafer process control  

Microsoft Academic Search

A gate oxide thickness controller for a plasma etch reactor has been developed. This controller is for 0.9-?m technology. By monitoring certain processes, signatures are fed forward into a neural network trained by the backpropagation method. It is possible to predict in real time the correct over-etch time on a wafer-by-wafer basis. Computer simulations indicate that the neural network is

E. A. Rietman; S. H. Patel; E. R. Lory

1993-01-01

347

Development of Wafer-Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV Wafers  

Microsoft Academic Search

Through-silicon via (TSV) technology has been widely investigated recently for 3-D electronic packaging integration. Reducing TSV wafer warpage is one of the most challenging concerns for successfully subsequent processes. In this paper, a wafer-level warpage modeling methodology has been developed by the finite element analysis method using an equivalent material model. The developed modeling methodology has been verified by numerical

Faxing Che; Hongyu Y. Li; Xiaowu Zhang; Shan Gao; Kenghwa H. Teo

2012-01-01

348

Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis  

SciTech Connect

This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

Tobin, K.W.

2003-05-22

349

Improving on-wafer CD correlation analysis using advanced diagnostics and across-wafer light-source monitoring  

NASA Astrophysics Data System (ADS)

With the implementation of multi-patterning ArF-immersion for sub 20nm integrated circuits (IC), advances in equipment monitoring and control are needed to support on-wafer yield performance. These in-situ equipment monitoring improvements, along with advanced litho-cell corrections based on on-wafer measurements, enable meeting stringent overlay and CD control requirements for advanced lithography patterning. The importance of light-source performance on lithography pattering (CD and overlay) has been discussed in previous publications.[1-3] Recent developments of Cymer ArF light-source metrology and on-board monitoring enable end-users to detect, for each exposed wafer, changes in the near-field and far-field spatial profiles and polarization performance, [4-6] in addition to the key `optical' scalar parameters, such as bandwidth, wavelength and energy. The major advantage of this capability is that the key performance metrics are sampled at rates matched to wafer performance, e.g. every exposure field across the wafer, which is critical for direct correlation with on-wafer performance for process control and excursion detection.

Alagna, Paolo; Zurita, Omar; Rechtsteiner, Gregory; Lalovic, Ivan; Bekaert, Joost

2014-04-01

350

40 Gbit/s silicon modulators fabricated on 200-mm and 300-mm SOI wafers  

NASA Astrophysics Data System (ADS)

We present 40 Gbit/s optical modulators based on different types of phase shifters (lateral pn, pipin, and interleaved pn junction phase). Those structures were processed both on 200 and 300mm SOI wafers, available in large-scale microelectronic foundries. Both Ring Resonators (RR) and Mach Zehnder (MZ) modulators were fabricated. As an example, MZ modulator based on 0.95 mm long interleaved pn junction phase shifter delivered a high ER of 7.8 dB at 40 Gbit/s with low optical loss of only 4 dB. Ring modulator was also fabricated and characterized at high-speed, exhibiting 40 Gbit/s.

Marris-Morini, Delphine; Baudot, Charles; Fédéli, Jean-Marc; Rasigade, Gilles; Vuillet, Nathalie; Souhaité, Aurélie; Ziebell, Melissa; Rivalin, Pierette; Olivier, Ségolène; Crozat, Paul; Bouville, David; Menezo, Sylvie; Boeuf, Frédéric; Vivien, Laurent

2014-03-01

351

100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices  

SciTech Connect

A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

OLIVER,ANDREW D.; MATZKE,CAROLYN M.

2000-04-06

352

Transparent masks for aligned deep x-ray lithography/LIGA: low-cost high-performance alternative using glass membranes  

NASA Astrophysics Data System (ADS)

Deep x-ray lithography/LIGA has proven to be a well established framework of x-ray based technologies for the fabrication of microstructures and pseudo three-dimensional objects. Inherently, x-ray lithography/LIGA is not fully three-dimensional because of the principle of simple shadow printing onto resists of constant thickness. Thus, it would be impossible to obtain 3D spheres, but series of stacked monolithic 2D cylinders. Hence, until recently, LIGA was mainly concerned with simple uni-level (1D) monolithic structures, using optically opaque mask-membranes like Be, Si or Ti with grown-on Au absorbers. In the course for mastering pseudo three-dimensional microstructures like micro-coils or electromagnetic applications, an alignment in between the lithographic steps becomes necessary which requires optically transparent membrane materials, if optical alignment is chosen. Diamond or SiC membranes are the actual suitable materials for such purposes, but their pricing and/or process robustness inhibit their frequent use in simple projects. We would like to report on a new promising material: a glued-on thin glass membrane. The advantages are incomparably lower costs compared to Diamond or SiC technologies, a considerable ease of fabrication, handling, quite favorable mechanical/optical properties, sufficient for lithographic purposes and multi-level deep x-ray lithography/LIGA activities.

Kupka, Roland K.; Megtert, Stephan; Roulliay, Marc; Bouamrane, Faycal

1998-09-01

353

Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering  

NASA Astrophysics Data System (ADS)

Silicon wafer breakage has become a major concern for all semiconductor fabrication lines because it is brittle, and thus high stresses are easily induced in its manufacture. The production cost of devices significantly increases even for a breakage loss of a few percent if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant. In this investigation, we develop a brand new approach to reducing breakage by using a charge-coupled device (CCD) to capture the cross-section image of the wafer at its edge; the data measured at the edge can be used to determine overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength, and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in the wafer bulk before failure. We also describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unidentified causes. Our analysis gives the optimal front size (B1), edge widths (A1,A2), and bevel angle (?) for the edge profiles of wafers to prevent wafer breakage. Briefly, when a suitable material and suitable process control approaches are utilized, silicon wafer breakage can be prevented. This is the first investigation providing evidence that whole-wafer strength is an important issue. We present a physical model to explain why wafer fracture has become an increasingly serious problem as the diameter of wafers has increased. The control of wafer edge geometry has been demonstrated to be an effective means of protecting wafers with large diameters against breakage. This model reveals that the breakage rate of wafers can be reduced by controlling the uniformity of the differences between the front size and the rear edge widths during the wafer manufacturing process.

Chen, Po-Ying; Tsai, Ming-Hsing; Yeh, Wen-Kuan; Jing, Ming-Haw; Chang, Yukon

2009-12-01

354

Scales  

ScienceCinema

Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain ? a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

Murray Gibson

2010-01-08

355

Very high magnification optical characterization of global and local distortion of Si wafers after laser spike annealing  

Microsoft Academic Search

The understanding of macro- and micro-scale wafer shape changes during device fabrication process steps is becoming very critical in developing and optimizing advanced technology node devices in which new materials such as Ni, NiPt and\\/or Ge are introduced. We have developed a non-contact, in-line process and\\/or material property monitoring method which uses various forms (reflection, diffraction, interference and scattering) of

Woo Sik Yoo; T. Ueda; T. Ishigaki; K. Kang

2009-01-01

356

The quality of 200 mm diameter epitaxial Si wafers for advanced CMOS technology monitored using synchrotron X-ray topography  

Microsoft Academic Search

The control and characterisation of wafer defect and strain distributions is of crucial importance for the development of advanced Ultra Large Scale Integration (ULSI) circuits. Within the IC manufacturing sector 0.35 ?m linewidth-based advanced Complementary Metal Oxide Semiconductor (CMOS) logic has recently emerged at a high level of maturity, to be closely followed by an even more demanding 0.25 ?m

Patrick J. McNally; A. N. Danilewsky; J. W. Curley; A Reader; R. Rantamäki; T. Tuomi; M. Bolt; M. Taskinen

1999-01-01

357

Wafer-level filling of microfabricated atomic vapor cells based on thin-film deposition and photolysis of cesium azide  

Microsoft Academic Search

The thin-film deposition and photodecomposition of cesium azide are demonstrated and used to fill arrays of miniaturized atomic resonance cells with cesium and nitrogen buffer gas for chip-scale atomic-based instruments. Arrays of silicon cells are batch fabricated on wafers into which cesium azide is deposited by vacuum thermal evaporation. After vacuum sealing, the cells are irradiated with ultraviolet radiation, causing

Li-Anne Liew; John Moreland; Vladislav Gerginov

2007-01-01

358

Surface quality of silicon wafer improved by hydrodynamic effect polishing  

NASA Astrophysics Data System (ADS)

Differing from the traditional pad polishing, hydrodynamic effect polishing (HEP) is non-contact polishing with the wheel floated on the workpiece. A hydrodynamic lubricated film is established between the wheel and the workpiece when the wheel rotates at a certain speed in HEP. Nanoparticles mixed with deionized water are employed as the polishing slurry, and with action of the dynamic pressure, nanoparticles with high chemisorption due to the high specific surface area can easily reacted with the surface atoms forming a linkage with workpiece surface. The surface atoms are dragged away when nanoparticles are transported to separate by the flow shear stress. The development of grand scale integration put extremely high requirements on the surface quality on the silicon wafer with surface roughness at subnanometer and extremely low surface damage. In our experiment a silicon sample was processed by HEP, and the surface topography before and after polishing was observed by the atomic force microscopy. Experiment results show that plastic pits and bumpy structures on the initial surface have been removed away clearly with the removal depth of 140nm by HEP process. The processed surface roughness has been improved from 0.737nm RMS to 0.175nm RMS(10?m×10?m) and the section profile shows peaks of the process surface are almost at the same height. However, the machining ripples on the wheel surface will duplicate on the silicon surface under the action of the hydrodynamic effect. Fluid dynamic simulation demonstrated that the coarse surface on the wheel has greatly influence on the distribution of shear stress and dynamic pressure on the workpiece surface.

Peng, Wenqiang; Guan, Chaoliang; Li, Shengyi

2014-08-01

359

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?  

NASA Astrophysics Data System (ADS)

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Green, Martin A.

2014-03-01

360

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness  

SciTech Connect

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

Fong, Theodore E.

2013-05-06

361

Silicon wafer bonding studied by infrared absorption spectroscopy  

NASA Astrophysics Data System (ADS)

The interface of hydrophilic and hydrophobic Si wafers joined at room temperature is studied using multiple internal transmission infrared absorption spectroscopy as a function of 30-min annealing steps in N2 atmosphere up to 1100 °C. For hydrophilic wafers, water molecules are observed up to 300 °C, silanol groups up to 900 °C, and hydrogen up to 1000 °C. The absence of water spectral features above 300 °C implies that, if present, water molecules are mostly oriented in a plane parallel to the interface. For the hydrophobic wafers, the temperature dependence of the Si-H stretch spectra shows that the majority of H does not participate in the bonding, pointing to the role of impurities or defects.

Feijoó, Diego; Chabal, Y. J.; Christman, S. B.

1994-11-01

362

Silicon Wafer Direct Bonding without Hydrophilic Native Oxides  

NASA Astrophysics Data System (ADS)

Silicon wafer direct bonding was accomplished between two surfaces which had no hydrophilic native oxide layers. Prior to bonding, two wafers were dipped in conc-HF solution ( ˜49% aq.) to remove the native oxide layers and then immersed in deionized water. The level of bonding was evaluated by X-ray topography, high resolution transmission electron microscopy (HRTEM) and tensile strength measurement. It was found that the bonded wafer pairs were void-free and had good bonding strength. HRTEM observation showed that the crystal lattice was continuous and had only small distortions and precipitates. Spreading resistance (SR) measurement across the interface showed that the electric resistance did not increase at the bonding interface. It is suggested that the OH groups which substitute the F atoms terminated on the small portion of the surface play an important role in this conc-HF-treated bonding.

Himi, Hiroaki; Matsui, Masaki; Fujino, Seiji; Hattori, Tadashi

1994-01-01

363

Wafer Fusion for Integration of Semiconductor Materials and Devices  

SciTech Connect

We have developed a wafer fusion technology to achieve integration of semiconductor materials and heterostructures with widely disparate lattice parameters, electronic properties, and/or optical properties for novel devices not now possible on any one substrate. Using our simple fusion process which uses low temperature (400-600 C) anneals in inert N{sub 2} gas, we have extended the scope of this technology to examine hybrid integration of dissimilar device technologies. As a specific example, we demonstrate wafer bonding vertical cavity surface emitting lasers (VCSELs) to transparent AlGaAs and GaP substrates to fabricate bottom-emitting short wavelength VCSELs. As a baseline fabrication technology applicable to many semiconductor systems, wafer fusion will revolutionize the way we think about possible semiconductor devices, and enable novel device configurations not possible by epitaxial growth.

Choquette, K.D.; Geib, K.M.; Hou, H.Q.; Allerman, A.A.; Kravitz, S.; Follstaedt, D.M.; Hindi, J.J.

1999-05-01

364

Microwave Induced Direct Bonding of Single Crystal Silicon Wafers  

NASA Technical Reports Server (NTRS)

We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

Budraa, N. K.; Jackson, H. W.; Barmatz, M.

1999-01-01

365

Silicon carbide wafer bonding by modified surface activated bonding method  

NASA Astrophysics Data System (ADS)

4H-SiC wafer bonding has been achieved by the modified surface activated bonding (SAB) method without any chemical-clean treatment and high temperature annealing. Strong bonding between the SiC wafers with tensile strength greater than 32 MPa was demonstrated at room temperature under 5 kN force for 300 s. Almost the entire wafer has been bonded very well except a small peripheral region and few voids. The interface structure was analyzed to verify the bonding mechanism. It was found an amorphous layer existed as an intermediate layer at the interface. After annealing at 1273 K in vacuum for 1 h, the bonding tensile strength was still higher than 32 MPa. The interface changes after annealing were also studied. The results show that the thickness of the amorphous layer was reduced to half after annealing.

Suga, Tadatomo; Mu, Fengwen; Fujino, Masahisa; Takahashi, Yoshikazu; Nakazawa, Haruo; Iguchi, Kenichi

2015-03-01

366

Silicon wafer temperature monitoring using all-fiber laser ultrasonics  

NASA Astrophysics Data System (ADS)

Laser-ultrasonics is a very attractive technique for in-line process control in the semiconductor industry as it is compatible with the clean room environment and offers the capability to inspect parts at high-temperature. We describe measurements of the velocity of laser-generated Lamb waves in silicon wafers as a function of temperature using fiber- optic laser delivery and all-fiber interferometric sensing. Fundamental anti-symmetric Lamb-wave modes were generated in 5 inches < 111 > silicon wafers using a Nd:YAG laser coupled to a large-core multimode fiber. Generation was also performed using an array of sources created with a diffraction grating. For detection a compact fiber-optic sensor was used which is well suited for industrial environments as it is compact, rugged, stable, and low-cost. The wafers were heated up to 1000 degrees C and the temperature correlated with ultrasonic velocity measurements.

Alcoz, Jorge J.; Duffer, Charles E.

1998-03-01

367

450mm wafer patterning with jet and flash imprint lithography  

NASA Astrophysics Data System (ADS)

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

368

Toward 300 mm wafer-scalable high-performance polycrystalline chemical vapor deposited graphene transistors.  

PubMed

The largest applications of high-performance graphene will likely be realized when combined with ubiquitous Si very large scale integrated (VLSI) technology, affording a new portfolio of "back end of the line" devices including graphene radio frequency transistors, heat and transparent conductors, interconnects, mechanical actuators, sensors, and optical devices. To this end, we investigate the scalable growth of polycrystalline graphene through chemical vapor deposition (CVD) and its integration with Si VLSI technology. The large-area Raman mapping on CVD polycrystalline graphene on 150 and 300 mm wafers reveals >95% monolayer uniformity with negligible defects. About 26,000 graphene field-effect transistors were realized, and statistical evaluation indicates a device yield of ? 74% is achieved, 20% higher than previous reports. About 18% of devices show mobility of >3000 cm(2)/(V s), more than 3 times higher than prior results obtained over the same range from CVD polycrystalline graphene. The peak mobility observed here is ? 40% higher than the peak mobility values reported for single-crystalline graphene, a major advancement for polycrystalline graphene that can be readily manufactured. Intrinsic graphene features such as soft current saturation and three-region output characteristics at high field have also been observed on wafer-scale CVD graphene on which frequency doubler and amplifiers are demonstrated as well. Our growth and transport results on scalable CVD graphene have enabled 300 mm synthesis instrumentation that is now commercially available. PMID:25198884

Rahimi, Somayyeh; Tao, Li; Chowdhury, Sk Fahad; Park, Saungeun; Jouvray, Alex; Buttress, Simon; Rupesinghe, Nalin; Teo, Ken; Akinwande, Deji

2014-10-28

369

An application of selective electrochemical wafer thinning for silicon characterization  

SciTech Connect

A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

1990-01-01

370

Computationally Efficient Modeling of Wafer Temperatures in an LPCVD Furnace  

Microsoft Academic Search

ABSTRACT This paper,presents a new,first principles thermal,model,to predict wafer temperatures,within a hot-wall Low Pressure Chemical,Vapor Deposition (LPCVD) furnace based,on furnace,wall temperatures,as measured,by thermocouples.,This model,is based,on an energy,balance,of the furnace system,with the following features: (a) the model,is a transformed,linear model,which,captures,the nonlinear,relationship between,the furnace wall temperature distribution and the wafer temperature distribution, (b) the model can be solved with a direct algorithm

Qinghua He; S. Joe Qin; Anthony J. Toprac

371

Overview of recent direct wafer bonding advances and applications  

NASA Astrophysics Data System (ADS)

Direct wafer bonding processes are being increasingly used to achieve innovative stacking structures. Many of them have already been implemented in industrial applications. This article looks at direct bonding mechanisms, processes developed recently and trends. Homogeneous and heterogeneous bonded structures have been successfully achieved with various materials. Active, insulating or conductive materials have been widely investigated. This article gives an overview of Si and SiO2 direct wafer bonding processes and mechanisms, silicon-on-insulator type bonding, diverse material stacking and the transfer of devices. Direct bonding clearly enables the emergence and development of new applications, such as for microelectronics, microtechnologies, sensors, MEMs, optical devices, biotechnologies and 3D integration.

Moriceau, H.; Rieutord, F.; Fournel, F.; Le Tiec, Y.; Di Cioccio, L.; Morales, C.; Charvet, A. M.; Deguet, C.

2010-12-01

372

Wafer test of the LHCb Outer Tracker TDC-Chip  

E-print Network

The OTIS-TDC is the front end readout chip for the LHCb Outer Tracker. It is designed to measure drift times with a resolution better than 1 ns. As the chip will be directly mounted to its board, the test have to be performed on the wafer itself. As the testing period for 7 000 chips was only three weeks, many test routines have been implemented on a FPGA. Each chip is subjected to detailed probe testing to ensure the full functionality as well as a good performance. Overall 47 wafer have been tested. From the chips passing the test 2 000 have been used in the Outer Tracker front end electronic.

Knopf, Jan; Stange, U; Trunk, U; Uwer, U; Wiedner, D

2007-01-01

373

Correlation of the structural properties of a Pt seed layer with the perpendicular magnetic anisotropy features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 junctions via a 12-inch scale Si wafer process  

NASA Astrophysics Data System (ADS)

We elucidated the interfacial-perpendicular magnetic anisotropy (i-PMA) features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 magnetic-tunnel-junctions as functions of the structural properties of the Pt seed layer including its thickness and ex situ annealing temperature. All of the samples were prepared in a 12-inch silicon wafer process for real industry applications. The observations of the M-H loops emphasize that a thinner Pt seed layer and a high ex situ annealing temperature enhance the surface roughness of the seed layer, providing better i-PMA characteristics. HR-TEM images of the samples were evaluated to understand the structural effects of thin and thick Pt seed layers.

Chae, Kyo-Suk; Lee, Du-Yeong; Shim, Tae-Hun; Hong, Jin-Pyo; Park, Jea-Gun

2013-10-01

374

Bonding silicon-on-insulator to glass wafers for integrated bio-electronic Hyun S. Kima)  

E-print Network

borosilicate glass is a typical material that con- tains sodium oxide Na2O . The presence of mobile metal ions rinse, the SOI wafers are bonded to glass wafers in a vacuum chamber. This is performed at a temperature

Eom, Chang Beom

375

Characterization, modeling, and design of an electrostatic chuck with improved wafer temperature uniformity  

NASA Astrophysics Data System (ADS)

The resulting temperature distribution of a silicon wafer held by an electrostatic chuck (ESC) in an electron-cyclotron-resonance chemical vapor deposition (ECR-CVD) reactor is characterized and modeled. The effects of the clamping voltage VESC, pressure between the ESC and wafer PHe, and the surface finish and pattern on the ESC are investigated. Heat transfer coefficients between the wafer and various ESCs are determined experimentally. A model is developed to predict the temperature distribution at the surface of the wafer, and used to explain the experimentally observed temperature variations both within wafer and between different chucks. The model is then used to aid in the design of an ESC which provides improved temperature uniformity at the wafer surface. The results of this study indicate: (a) the thermal resistances across the interface between the wafer and ESC control both the absolute wafer temperature and the wafer temperature uniformity; (b) the surface roughness of the ESC and the size of the ``contact'' regions are major design factors controlling the absolute temperature of the wafer—the temperature can be adjusted by varying the value of VESC and fine tuned by adjusting the value of PHe; (c) the nonuniform temperature distribution across the wafer surface is dictated by the surface pattern on the ESC, the variation in surface roughness, and the size of the ESC relative to the wafer; (d) wafer temperature variations from chuck to chuck are reduced by controlling the surface finish of the ESC and by ensuring that PHe is a dominant heat transfer mechanism; and (e) maximum uniformity in the temperature of the wafer is obtained when the radius of the ESC is matched as closely as possible to that of the wafer. We have shown that numerical heat transfer models can be used to optimize the geometry of the ESC to provide a uniform distribution of temperature across the surface of the wafer.

Olson, Kurt A.; Kotecki, David E.; Ricci, Anthony J.; Lassig, Stephan E.; Husain, Anwar

1995-02-01

376

Residual stress analysis on silicon wafer surface layers induced by ultra-precision grinding  

Microsoft Academic Search

Grinding residual stresses of silicon wafers affect the performance of IC circuits. Based on the wafer rotation ultra-precision\\u000a grinding machine, the residual stress distribution along grinding marks and ground surface layer depth of the ground wafers\\u000a are investigated using Raman microspectroscopy. The results show that the ground wafer surfaces mainly present compressive\\u000a stress. The vicinity of pile-ups between two grinding

Yinxia Zhang; Dong Wang; Wei Gao; Renke Kang

2011-01-01

377

Mechanical Properties of Heat-treated CZ-Si Wafers from Brittle to Ductile Temperature Range  

Microsoft Academic Search

Four point bending tests were performed on heat-treated CZ-Si wafers at various temperatures. The fracture stress at room temperature does not change with heat treatments if the wafer has surface-denuded zones. However, the yield stresses of wafers at 700°C are remarkebly lowered by such treatments. The heat-treated CZ wafers are deformed plastically at relatively low temperatures and deformation twins appear

Kiyoshi Yasutake; Junichi Murakami; Masataka Umeno; Hideaki Kawabe

1982-01-01

378

Analysis of stresses and breakage of crystalline silicon wafers during handling and transport  

Microsoft Academic Search

A significant challenge in using thinner and larger crystalline silicon wafers for solar cell manufacture is the reduced yield due to higher wafer breakage rates. At a given process step, wafer\\/cell breakage depends on the stresses produced in the wafer\\/cell due to prior processing, handling and\\/or transport and on the presence of structural defects such as cracks. Specifically, analysis of

Xavier F. Brun; Shreyes N. Melkote

2009-01-01

379

Effects of wafer curvature caused by film stress on the chemical mechanical polishing process  

Microsoft Academic Search

A theoretical model based on two-body contact theory is established to simulate the contact pressure distribution arising\\u000a from wafer curvature which is caused by film stress during CMP process. Both wafer and pad deformations during the contact\\u000a process are considered. The profiles of the contact pressure distribution for wafers with different curvature radius are simulated.\\u000a The influences of wafer curvature

Lixiao Wu

2009-01-01

380

Wafer level encapsulation for system in package generation  

Microsoft Academic Search

Within this paper, encapsulation technologies as transfer molding and printing have been investigated; focusing on the feasibility of reliable wafer encapsulation and the suitability of current materials. For these processes the potential of 3D structuring during the encapsulation has been evaluated. An electroless metallization process and laser techniques for structuring the metallization layer have been investigated for reliable interconnections. Summarized

T. Braun; K.-F. Becker; M. Koch; V. Bader; D. Manessis; A. Neumann; A. Ostmann; R. Aschenbrenner; H. Reichl

2003-01-01

381

Localized induction heating solder bonding for wafer level MEMS packaging  

Microsoft Academic Search

This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was heated using induction heating causing the solder to reflow. The experiment results show that it took less than 1 min to complete the bonding process. In addition, the MEMS devices experienced a temperature of only 110 °C during bonding, thus

Hsueh-An Yang; Mingching Wu; Weileun Fang

2005-01-01

382

Fabricating a Microcomputer on a Single Silicon Wafer  

NASA Technical Reports Server (NTRS)

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

Evanchuk, V. L.

1983-01-01

383

Cycle time reduction at cluster tool in semiconductor wafer fabrication  

Microsoft Academic Search

Cluster tools have gained a lot of importance in today's semiconductor manufacturing. Cluster tools are machines that combine several processing steps in one machine. A cluster tools basically consists of one or more loadlocks where wafers enter and exit the cluster tool, two or more processing chambers where the processes are performed, and one or more handlers which transport the

Aye Nyein Swe; Amit Kumar Gupta; Appa Iyer Sivakumar; Peter Lendermann

2006-01-01

384

Vibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements  

E-print Network

Vibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements I. Kao (PI), S the yield per crystal and to reduce the cost. In this paper, the vibration model of wiresaw system of vibration indicate the interference of excitation and natural frequencies in the vibration patterns

Kao, Imin

385

Computationally efficient modeling of wafer temperatures in an LPCVD furnace  

Microsoft Academic Search

This paper presents a new first principles thermal model to predict wafer temperatures within a hot-wall Low Pressure Chemical Vapor Deposition (LPCVD) furnace based on furnace wall temperatures as measured by thermocouples. This model is based on an energy balance of the furnace system with the following features: (a) the model is a transformed linear model which captures the nonlinear

Qinghua He; S. Joe Qin; Anthony J. Toprac

2003-01-01

386

Hermetic wafer bonding based on rapid thermal processing  

Microsoft Academic Search

Hermetic wafer bonding based on rapid thermal processing (RTP) has been demonstrated for the first time. Microcavities encapsulated between glass and silicon substrate have been sealed with aluminum solder by using RTP at 990°C for 2s. Reliability experiments of IPA leak and autoclave accelerated tests show that 100% of survival rate can be achieved. The best encapsulation results are accomplished

Mu Chiao; Liwei Lin

2001-01-01

387

Localized induction heating solder bonding for wafer level MEMS packaging  

Microsoft Academic Search

This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. The electroplated magnetic film was heated up using the induction heating, and leaded to solder reflow. It took only several seconds to complete the solder reflow and bonding process. The measurement results showed that the temperature of device region was only 110°C during heating.

Hsueh-An Yang; Mingching Wu; Weileun Fang

2004-01-01

388

Selective induction heating for wafer level bonding and packaging  

Microsoft Academic Search

Selective induction heating for wafer level bonding is presented. The purpose of this paper is to investigate the relationships between the geometry of solder loop and temperature distribution in induction heating. Using finite element method (FEM) and IR thermal imager, temperature distribution and variation are explored, which shows that the temperature on the solder loops is a function of the

Mingxiang Chen; Wenming Liu; Yanyan Xi; Changyong Lin; C. P. Wong; Sheng Liu

2009-01-01

389

Crack propagation and fracture in silicon wafers under thermal stress.  

PubMed

The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing. PMID:24046487

Danilewsky, Andreas; Wittge, Jochen; Kiefl, Konstantin; Allen, David; McNally, Patrick; Garagorri, Jorge; Elizalde, M Reyes; Baumbach, Tilo; Tanner, Brian K

2013-08-01

390

MECHANICAL STRESS TESTS ON MC-SI WAFERS WITH MICROCRACKS  

Microsoft Academic Search

Micro crack detection and mechanical twist tests have been performed on as-cut wafers for solar cell production. A relation between the mechanical strength and crack length has been suggested. There is no indication of growth of crack length from repeated stress tests below the critical stress. It was found that edge cracks are more critical than interior cracks of same

Jörgen Gustafsson; Hanna Larsson; Hans Jørgen Solheim; Tobias Boström

391

Ultra-Gradient Test Cavity for Testing SRF Wafer Samples  

SciTech Connect

A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

2010-11-01

392

Wafer yield prediction by the Mahalanobis-Taguchi system  

Microsoft Academic Search

The distribution of yield from the production lines is concentrated at a high-yield area and tapers down to the lower-yield area. Production management would find it useful if the yield of individual wafers could be forecast. The yield is determined by the variability of electrical characteristics and dust. In this study, only the variability of electrical characteristics was discussed. One

M. Asada

2001-01-01

393

Multi-wafer slicing with a fixed abrasive  

NASA Technical Reports Server (NTRS)

A wafering machine having a multiplicity of wire cutting blades supported by a bladehead reciprocally moving past a workpiece supported by a holder that rocks about an axis perpendicular to the wires at a frequency less than the reciprocation of the bladehead.

Schmid, Frederick (Inventor); Khattak, Chandra P. (Inventor); Smith, Maynard B. (Inventor)

1988-01-01

394

THIN GLASS OPTIC AND SILICON WAFER DEFORMATION AND KINEMATIC CONSTRAINT  

Microsoft Academic Search

To meet these assembly and metrology challenges, we present how thin materials such as silicon and glass wafers deform and how they can be constrained to minimize these effects. Both analytical calculations and finite element analyses (FEA) are utilized to understand the effects of gravity on foil deformation while varying parameters such as foil thickness and angle of inclination. Friction

Craig R. Forest; Mireille Akilian; Guillaume Vincent; Alexandre Lamure; Mark L. Schattenburg

2003-01-01

395

Vacuum wafer-level packaging for MEMS applications  

NASA Astrophysics Data System (ADS)

For several kinds of MEMS (gyrometers, accelerometers, RF MEMS, bolometers, vacuum allows a significant improvement of performances. Leti has developed a high performance sensor operating at a pressure lower than 10-3 mbar. In a first phase, a ceramic vacuum packaging has been developed: the device is encapsulated in a cavity containing a getter. However, this technique increases considerably the fabrication costs, because it is made at the chip level. For that reason, Leti has also developed wafer-level vacuum packaging process. The process to manufacture encapsulated devices is presented in this paper. The vacuum function is obtained thanks to an additional wafer (glass or silicon wafer), which supports getters. This wafer is bonded by an hermetic bonding. Characterisation of different kinds of bonding, in term of hermeticity, is presented. First chips manufactured with this process have been tested. The vacuum level in the cavities has been measured, and was lower than 10-3 mbar. Moreover, vacuum evolution during 6 months does not show pressure increase. This process can be easily adapted to several MEMS applications. With these experiments, Leti has so proved the possibility of manufacturing low cost vacuum packaged MEMS.

Caplet, Stephane; Sillon, Nicolas; Delaye, Marie-Therese; Berruyer, Pascale

2003-01-01

396

A mechanical screening method for glass passivated wafers  

Microsoft Academic Search

The paper presents a method for the improvement of product reliability based on screening at the wafer fabrication stage, which is time and money saving for manufacturer. It relates to the manufacture of automotive rectifier diodes in DO21 case. The aim was to establish a mechanical screening procedure based on the correlation between the resistance to applied pressure of glass

B. T. Bucheru; F. Turtudau; A. Ichim; R. Iosif; V. A. Marinescu

1999-01-01

397

Wafer level glass frit bonding for MEMS hermetic packaging  

Microsoft Academic Search

Wafer level bonding is widely applied in the manufacture of sensors, actuators and CMOS MEMS. Bonding technology includes direct bonding, anodic bonding, eutectic bonding, adhesive bonding and glass frit bonding. Glass frit bonding has pattern-able, excellent sealing performances, high bonding strength, don't need apply any voltage during bonding process and less CTE mismatch compared to glass and silicon is more

Jin-Sheng Chang; Jing-Yuan Lin; Shu-Ching Ho; Yao-Jung Lee

2010-01-01

398

Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence  

E-print Network

imaging. The photoluminescence intensity from such wafers is dominated by surface recombination, which photoluminescence intensity. This method may be useful in monitoring mixes of crystal orientations an inhomogeneity in the effective lifetime after pas- sivation through atomic layer deposition (ALD). While

399

A novel gold deposition process for wafer applications  

Microsoft Academic Search

The deposition of nickel and gold layers as under bump metallurgy (UBM) for wafer bump applications has been established as a viable means of ensuring adhesion and bond reliability. These nickel\\/gold layers can be used in subsequent processes that employ either wire bonding directly to die pads or screened and reflowed solder paste for connectivity to next level substrates. This

N. Brown; E. Douglass

2003-01-01

400

Wafer Slicing and Wire Saw Manufacturing Technology I. Kao (PI)  

E-print Network

this abrasive slurry cutting process and to optimize it. As a sequel to this understanding, control tools can applications than the traditional use of the process. An evaluation of wire saw cutting process has shown to cut very thin wafers from large diameter crystalline ingots of semiconductor materials, has emerged

Kao, Imin

401

Wafer Probe Station, Low Noise Amplifiers, and Wideband Feed Developments  

E-print Network

and for IF amps in THz receivers 3. Recent SiGe LNA developments 4. 1 to 20 and 8 to 50 GHz LNA designs 5. Quad-ridge flared horn wideband feeds #12;Wafer Fabrication of LNA's and Other Radiometer Components 20-Sep-2011

Weinreb, Sander

402

A through-wafer interconnect in silicon for RFICs  

Microsoft Academic Search

In order to minimize ground inductance in RFICs, we have developed a high-aspect ratio, through-wafer interconnect (or substrate via) in silicon that features a silicon nitride barrier liner and completely filled Cu core. We have fabricated vias with a nominal aspect ratio of 30 and verified the integrity of the insulating liner in vias with an aspect ratio of eight.

Joyce H. Wu; Jörg Scholvin; Jesús A. del Alamo

2004-01-01

403

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment  

NASA Technical Reports Server (NTRS)

Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

2013-01-01

404

Generation of dislocations introduced by bending stress in a Si wafer  

Microsoft Academic Search

Distribution and morphology for dislocations introduced in (001) Si wafers subjected to bending stress at 800°, 900°, and 1100°C were investigated. For wafers bent around a [110] axis at 900° and 1100°C, straight dislocations appeared along the [110] direction only near the neutral plane, and were absent at the surfaces where bending stress is greatest. However, for wafers bent at

R. Sawada; T. Karaki; J. Watanabe

1983-01-01

405

Development of a novel Wafer-Level-Packaging technology using laminating process  

Microsoft Academic Search

We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some Jisso techniques to WLP manufacturing processes. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the developed

Yoshio Okayama; Yasuyuki Yanase; Kouichi Saitou; Hajime Kobayashi; Mayumi Nakasato; Tetsuya Yamamoto; Ryosuke Usui; Yasunori Inoue

2009-01-01

406

Formation of Surface Microcrack for Separation of Nonmetallic Wafers Into Chips  

Microsoft Academic Search

High quality separation of wafers into chips is important to the electronic industry. Since chips often operate at a high power level ~Bar-Cohen @1#, Suhir @2#! wafers with high quality edges are required. Most of the defects, e.g., microcracks, dislocations, etc., form during cutting. During heating, the defects at the edge of a wafer ~with a size larger than some

T. Elperin; A. Kornilov; G. Rudin

2009-01-01

407

High-yield dicing of anodically bonded silicon–glass wafers by pressure-induced fracture  

Microsoft Academic Search

This paper describes a technique that uses applied force to dice anodically bonded silicon–glass wafers with high yields. The chips are suspended to the wafer by anchors; when pressure is applied to a chip, stress concentrates at the narrow anchors, which then fracture and release the chip from the wafer. Anchor fracturing has been used to dice crystalline and non-crystalline

R R Robaina; M J Lopez-Martinez; R Perez-Castillejos; J A Plaza

2012-01-01

408

Microfluidic probe: a new tool for integrating microfluidic environments and electronic wafer-probing  

E-print Network

of the wafer,1,3,4,10,11 a permanently bonded glass or polymer layer that contains the channels and input the wafers into specifically sized chips to fit into the clamp and further, they are often incompatibleMicrofluidic probe: a new tool for integrating microfluidic environments and electronic wafer

Reed, Mark

409

Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs  

E-print Network

architectures/technologies for future chips is wafer-level three-dimensional (3D) integration [1,2], i approach, where fully processed wafers (with multilevel on-chip interconnects) are aligned and bonded thermal- coefficient-of-expansion (TCE) matched glass wafers, (2) mechanical bonding strength tests using

Salama, Khaled

410

Wafer Level Surface Activated Bonding Tool for MEMS M. M. R. Howlader,a,z  

E-print Network

glass, and quartz wafers cleaned by a low energy argon ion source in a vacuum have been successfully to be applicable in chip size and wafer level optoelectronic6 and MEMS7 packaging. This tech- nique has already, we have found low adhesion between ionic crystals like quartz, glass wafers, and other materials

Howlader, Matiar R

411

CMP Pad Break-in Time Reduction in Silicon Wafer Polishing  

Microsoft Academic Search

This paper investigated the correlation between the surface conditions of the polishing pad and the break-in phenomena during silicon wafer polishing. The break-in is defined as pad conditioning to insure first polishing is consistent with second and following wafer polishing. A piezoelectric force sensor and an infrared (IR) sensor were installed on a silicon wafer polisher. The signals for friction

H. D. Jeong; K. H. Park; K. K. Cho

2007-01-01

412

A Material Removal Model for CMP Based on the Contact Mechanics of Pad, Abrasives, and Wafer  

E-print Network

A Material Removal Model for CMP Based on the Contact Mechanics of Pad, Abrasives, and Wafer Dinçer, Massachusetts 02115, USA Applied pressure in chemical mechanical polishing CMP is shared by the two-body pad­wafer and the three-body pad­abrasive­ wafer contacts. The fraction of applied pressure transferred through

Müftü, Sinan

413

Determining Pad-Wafer Contact using Dual Emission Laser Induced Fluorescence Caprice Gray1  

E-print Network

operating during CMP requires knowledge of the nature of the pad-wafer contact. Dual Emission Laser Induced during CMP. Interactions between the polishing pad surface and the wafer can then be deduced from It is beneficial to understand polishing pad-wafer contact during chemical mechanical polishing (CMP) so we can

White, Robert D.

414

Full-field wafer level thin film stress measurement by phase-stepping shadow Moire´  

Microsoft Academic Search

A wafer topography measurement system has been designed and demonstrated based on shadow Moire´. Three-step phase-stepping and phase unwarping techniques are also incorporated to enhance the system resolution. Wafer curvatures or bows can be achieved by analyzing the Moire´ fringe patterns and film stress can be obtained subsequently by transforming this wafer curvature using a conversion equation such as Stoney's

Kuo-Shen Chen; Terry Yuan-Fang Chen; Chia-Cheng Chuang; I.-K. Lin

2004-01-01

415

Semiconductor thin film transfer by wafer bonding and advanced ion implantation layer splitting technologies  

Microsoft Academic Search

Wafer bonding is an attractive technology for modern semiconductor and microelectronic industry due to its variability in allowing combination of materials. Initially, the bonding of wafers of the same material, such as silicon-silicon wafer bonding has been major interest. In the meantime, research interest has shifted to the bonding of dissimilar materials such as silicon to quartz or to sapphire.

Tien-Hsi Lee

1998-01-01

416

Evaluating different sampling techniques for process control using automated patterned wafer inspection systems  

Microsoft Academic Search

To evaluate sampling for automated defect inspections, a series of four inspection areas ranging from <1 cm2 to >4 cm2 were performed. Using an automated patterned wafer inspection system, 20 wafers were inspected for each of the sample sizes. Inspected die were selected in a random pattern across the wafer and remained the same for each inspection. The inspected area

Dennis Lazaroff; David Bakker; Derek R. Granath

1991-01-01

417

Modeling of hydrophilic wafer bonding by molecular dynamics simulations David A. Litton and Stephen H. Garofalinia)  

E-print Network

of glues or high pressures1­5 and an excellent review of wafer bonding is available.6 InterfacesModeling of hydrophilic wafer bonding by molecular dynamics simulations David A. Litton and Stephen for publication 31 December 2000 The role of moisture in hydrophilic wafer bonding was modeled using molecular

Garofalini, Stephen H.

418

First-principles calculations of the structural, elastic, electronic and optical properties of orthorhombic LiGaS 2 and LiGaSe 2  

NASA Astrophysics Data System (ADS)

The structural, electronic and optical properties of two orthorhombic crystals, LiGaS 2 and LiGaSe 2, were calculated using the density functional theory. The optimized unit cells are in good agreement with experimental data. The mechanical stability of LiGaS 2 and LiGaSe 2 has been confirmed by calculation of the elastic constants. The band structures, density of states were obtained. It is shown that the two crystals belong to the semiconductors with a direct energy band gap of about 3.12 and 2.34 eV. The bonding properties were analyzed according to the electronic structural data. The optical properties including the dielectric spectra, absorption spectra, refractive index, extinction coefficient, reflectivity and energy-loss spectra were also calculated and the results indicate that the two compounds are promising mid-IR crystal materials.

Ma, Tian-hui; Yang, Chun-hui; Xie, Ying; Sun, Liang; Lv, Wei-qiang; Wang, Rui; Ren, Yu-lan

2010-01-01

419

Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding  

Microsoft Academic Search

This paper presents on a novel chip-to-wafer (C2W) three- dimensional (3D) integration technology with well-controlled template alignment and wafer-level bonding, enabling precise alignment, few thermal cycles and high throughput of 3D system fabrication. The key processes are investigated and discussed in detail, including chip edge definition, template fabrication, C2W alignment and wafer-level bonding. The C2W 3D integration technology is successfully

Qianwen Chen; Dingyou Zhang; Zheyao Wang; Litian Liu; James Jian-Qiang Lu

2011-01-01

420

Wafer-level packaging with compression-controlled seal ring bonding  

DOEpatents

A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Farino, Anthony J

2013-11-05

421

Load induced stresses and plastic deformation in 450 mm silicon wafers  

NASA Astrophysics Data System (ADS)

The authors present the physical basis for estimation of gravitational constraints in 450mm silicon wafers subjected to high temperature processes. They have identified and quantified the relevant phenomena to predict the mechanical behavior of very large silicon wafers horizontally stacked and ring- or pointlike supported in a vertical-type furnace. It is shown that load induced stress at the supports increases directly proportional with increasing wafer diameter, although the weight of the wafer increases with the square of diameter. The results allow the optimization for a defect-free high temperature treatment of 450mm wafer used for leading edge device fabrication in future.

Fischer, A.; Kissinger, G.

2007-09-01

422

Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy  

NASA Astrophysics Data System (ADS)

All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on transmission and mobility are quantitatively discussed.

Altan, Hakan

423

Optimization of wafer-back pressure profile in chemical mechanical planarization  

NASA Astrophysics Data System (ADS)

In chemical mechanical planarization (CMP), a rotating wafer is pressed facedown against a rotating pad, while a slurry is dragged into the pad--wafer interface to assist in planarizing the wafer surface. Due to stress concentration, the interfacial contact stress near the wafer edge generally is much higher than that near the wafer center, resulting in spatially nonuniform material removal rate and hence imperfect planarity of the wafer surface. Here, integrating theories of fluid film lubrication and two-dimensional contact mechanics, we calculate the interfacial contact stress and slurry pressure distributions. In particular, the possibility of using a multizone wafer-back pressure profile to improve the contact stress uniformity is examined, by studying a practical case. The numerical results indicate that using a two-zone wafer-back pressure profile with optimized zonal sizes and pressures can increase the ``usable'' wafer surface area by as much as 12%. Using an optimized three- zone wafer-back pressure profile, however, does not much further increase the usable wafer surface area.

Yang, Tian-Shiang; Wang, Yao-Chen; Hu, Ian

2008-11-01

424

Influence of the bonding front propagation on the wafer stack curvature  

SciTech Connect

The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

Navarro, E. [SOITEC—Parc Technologique des Fontaines, 38190 Bernin (France); SIMaP—Grenoble-INP, 1340 rue de la Piscine, 38402 St. Martin d'Hères (France); Bréchet, Y. [SIMaP—Grenoble-INP, 1340 rue de la Piscine, 38402 St. Martin d'Hères (France); Barthelemy, A.; Radu, I. [SOITEC—Parc Technologique des Fontaines, 38190 Bernin (France); Pardoen, T. [Institute of Mechanics, Materials and Civil Engineering (iMMC), Université catholique de Louvain, B-1348 Louvain-la-Neuve (Belgium); Raskin, J.-P. [Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM), Université catholique de Louvain, B-1348 Louvain-la-Neuve (Belgium)

2014-08-11

425

Effect of heat according to wafer size on the removal rate and profile in CMP process  

NASA Astrophysics Data System (ADS)

The effect of wafer size on the removal rate and profile during chemical mechanical polishing was investigated with two representative thin films: SiO2 and Cu, which were used as the dielectric and interconnection, respectively. Experiments were conducted using SiO2 and Cu blanket wafers with 100, 200, and 300 mm diameters, while the results for 450 mm diameter wafers were estimated using geometric calculation. The experimental results showed that the heat generated by an increase in the wafer size affects the removal rate and the Within-Wafer Non-uniformity (WIWNU). In particular, the polishing temperature is one of the most important factors affecting the removal rate and profile in the Cu CMP process. An optimum slurry flow rate may exist for each wafer size, which should be carefully considered, particularly when using 450 mm diameter wafers in the semiconductor industry.

Park, Yeongbong; Lee, Youngkyun; Lee, Hyunseop; Jeong, Haedo

2013-11-01

426

Influence of the bonding front propagation on the wafer stack curvature  

NASA Astrophysics Data System (ADS)

The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

Navarro, E.; Bréchet, Y.; Barthelemy, A.; Radu, I.; Pardoen, T.; Raskin, J.-P.

2014-08-01

427

Towards large size substrates for III-V co-integration made by direct wafer bonding on Si  

NASA Astrophysics Data System (ADS)

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

2014-08-01

428

Localized induction heating solder bonding for wafer level MEMS packaging  

NASA Astrophysics Data System (ADS)

This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was heated using induction heating causing the solder to reflow. The experiment results show that it took less than 1 min to complete the bonding process. In addition, the MEMS devices experienced a temperature of only 110 °C during bonding, thus thin film materials would not be damaged. Moreover, the bond strength between silicon and silicon wafer was higher than 18 MPa. The step height of the feed-through wire (acting as the electrical feed-through of the bonded region) is sealed by the electroplated film. Thus, the flatness and roughness of the electroplated surface are recovered by the solder reflow, and the package for preventing water leakage can be achieved. The integration of the surface micromachined devices with the proposed packaging techniques was demonstrated.

Yang, Hsueh-An; Wu, Mingching; Fang, Weileun

2005-02-01

429

Ion beam studies of hydrogen implanted Si wafers  

NASA Astrophysics Data System (ADS)

We have studied silicon-on-insulator (SOI) materials with two different ion beam analysis methods. The SOI samples were implanted with boron and hydrogen ions. After implantation the wafers were annealed, and some of them were bonded to thermally oxidized silicon wafers. The damage in silicon single crystal due to ion implantations has been studied by Rutherford Backscattering in the channeling mode (RBS/C). The content of the ion-implanted hydrogen has been studied by elastic recoil detection analysis (ERDA) method. The strength of the implanted region after thermal annealings were measured with the crack opening method. The boron implantation before hydrogen implantation resulted to shallower implantation depth and lower splitting temperature than in samples implanted with hydrogen only. The boron implantation after hydrogen implantation did not influence the splitting temperature and RBS spectra showed that B implantation drove the H deeper to the sample.

Nurmela, A.; Henttinen, K.; Suni, T.; Tolkki, A.; Suni, I.

2004-06-01

430

Wafer-fused VECSELs emitting in the 1310nm waveband  

NASA Astrophysics Data System (ADS)

Optically pumped wafer fused 1310 nm VECSELs have the advantage of high output power and wavelength agility. Gain mirrors in these lasers are formed by direct bonding of InAlGaAs/InP active cavities to Al(Ga)As/GaAs DBRs. We present for the first time Watt-level 1310 nm wafer-fused VCSELs based on gain mirrors with heat dissipation in the "flip-chip" configuration. Even though output power levels in this approach is lower than with intra-cavity diamond heat-spreaders, the "flip-chip configuration demonstrates higher quality optical emission and is preferable for industrial applications in optical amplifiers, intra-cavity doubled lasers, etc.

Sirbu, A.; Pierscinski, K.; Mereuta, A.; Iakovlev, V.; Caliman, A.; Micovic, Z.; Volet, N.; Rautiainen, J.; Heikkinen, J.; Lyytikainen, J.; Rantamäki, A.; Okhotnikov, O.; Kapon, E.

2014-03-01

431

Chemical method for producing smooth surfaces on silicon wafers  

DOEpatents

An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

Yu, Conrad (Antioch, CA)

2003-01-01

432

Cost of Czochralski wafers as a function of diameter  

NASA Technical Reports Server (NTRS)

The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

Leipold, M. H.; Radics, C.; Kachare, A.

1980-01-01

433

Wafer-level radiometric performance testing of uncooled microbolometer arrays  

NASA Astrophysics Data System (ADS)

A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 ?m AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 ?m pixel size and 160x120, 52 ?m pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

2014-03-01

434

Wafer level bonding using localized radio-frequency induction heating  

Microsoft Academic Search

A wafer level bonding technique by localized induction heating has been developed and demonstrated in this paper. A suitable\\u000a fabrication process scheme has also been established for the localized induction heating and bonding. It takes only about\\u000a 20 seconds to complete the bonding process. The temperatures of solder loops and the central area of solder loops are above\\u000a 300°C and

MingXiang Chen; WenMing Liu; YanYan Xi; ChangYong Lin; Sheng Liu

2010-01-01

435

Electro Energy Bipolar Wafer Cell Battery Technology for PHEV Applications  

Microsoft Academic Search

Electro Energy, Inc. (EEI) has developed a bipolar battery utilizing a patented wafer cell design, applicable to both NiMH and Li-Ion chemistries. This battery is particularly suitable for meeting the high-voltage, high- energy demands of modern and emerging plug-in hybrid vehicles (PHEVs). EEI's battery technology has the potential to provide a rebuttal to the most common argument for not developing

J. Dailey; K. M. Abraham; R. Plivelich; J. Landi; M. Klein

2007-01-01

436

Interface traps and Pb centers in oxidized (100) silicon wafers  

Microsoft Academic Search

The band-gap energy distribution of Pb centers on oxidized (100) Si wafers has been determined and compared with interface electrical trap density Dit. Two different Pb centers are observed on (100) Si: Pb0, which has the structure ?Si?Si3, and is essentially identical to the sole Pb center observed on (111) Si; and Pb1, of presently uncertain identity, but clearly different

Gary J. Gerardi; Edward H. Poindexter; Philip J. Caplan; Noble M. Johnson

1986-01-01

437

Silicon wafer temperature monitoring using all-fiber laser ultrasonics  

Microsoft Academic Search

Laser-ultrasonics is a very attractive technique for in-line process control in the semiconductor industry as it is compatible with the clean room environment and offers the capability to inspect parts at high-temperature. We describe measurements of the velocity of laser-generated Lamb waves in silicon wafers as a function of temperature using fiber- optic laser delivery and all-fiber interferometric sensing. Fundamental

Jorge J. Alcoz; Charles E. Duffer

1998-01-01

438

Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy  

Microsoft Academic Search

All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump\\/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest

Hakan Altan

2005-01-01

439

Towards reduced impact of EUV mask defectivity on wafer  

NASA Astrophysics Data System (ADS)

The defectivity challenges of extreme ultraviolet (EUV) masks, that need to be addressed before production readiness of EUV lithography is assured from the mask perspective, are twofold. First, the EUV-specific defect type relating to the multi-layer (ML) mirror, the so-called ML-defects, require to become more detectable than they are printable. This not only requires proven capability of blank inspection, but also the existence of satisfactory printability mitigation strategies (comprising avoidance, pattern shift methodology, compensation repair). Both these assets need to become available within the mask supply chain, as there is little that can still be done about such residual defects at the wafer fab. In a production phase, finding unexpected printing ML-defects is unacceptable. It is shown how the specific way-of-working in use at imec, starting from the printed wafer, contributes to related learning and identification of remaining gaps, in getting this issue fully dealt with. The second challenge relates to particle contamination during use of the reticle at the wafer fab. Avoiding overlaycritical particles on the backside of NXE3100 reticles is facilitated by the established way-of-working. Minimizing the occurrence of particles "hopping" between reticles via the electrostatic clamp of the scanner (so-called clamp-traveling particles) is a major driver for appropriate mask cleaning. The latter may not have negative impact by frequent use, in view of the highly vulnerable EUV mask stack, and especially for the present "black-border" solution in which the ML is etched away at the image border on the reticle. A lot of effort is spent into monitoring of NXE3100 reticles for particle adders on the pattern side. This is realized by comparing past and present mask defect maps obtained by inspection of printed wafers with subsequent repeater analysis.

Jonckheere, R.; Van den Heuvel, D.; Pacco, A.; Pollentier, I.; Baudemprez, B.; Jehoul, C.; Hermans, J.; Hendrickx, E.

2014-07-01

440

Thin-film resistance thermometers on silicon wafers  

Microsoft Academic Search

We have fabricated Pt thin-film resistors directly sputtered on silicon substrates to evaluate their use as resistance thermal detectors (RTDs). This technique was chosen to achieve more accurate temperature measurements of large silicon wafers during semiconductor processing. High-purity (0.999 968 mass fraction) platinum was sputter deposited on silicon test coupons using titanium and zirconium bond coats. These test coupons were

Kenneth G Kreider; Dean C Ripple; William A Kimes

2009-01-01

441

Wafer inspection as alternative approach to mask defect qualification  

NASA Astrophysics Data System (ADS)

Defect inspection is one of the major challenges in the manufacturing process of photomasks. The absence of any printing defect on patterned mask is an ultimate requirement for the mask shop, and an increasing effort is spent in order to detect and subsequently eliminate these defects. Current DUV inspection tools use wavelengths five times or more larger than the critical defect size on advanced photomasks. This makes the inspectability of high-end mask patterns (including strong OPC and small SRAF's) and sufficient defect sensitivity a real challenge. The paper evaluates the feasibility of inspecting the printed wafer as an alternative way for the high-sensitivity defect inspection of photomasks. Defects originating in the mask can efficiently be filtered as repeated defects in the various dies on wafer. Using a programmed-defect mask of 65-nm technology, a reliable detection of the printing defects was achieved with an optimized inspection process. These defects could successfully be traced back to the photomask in a semi-automated process in order to enable a following repair step. This study shows that wafer inspection is able to provide a full defect qualification of advanced photomasks with the specific advantage of assessing the actual printability of arbitrary defects.

Holfeld, Christian; Katzwinkel, Frank; Seifert, Uwe; Mothes, Andreas; Peters, Jan Hendrik

2007-10-01

442

Whole wafer magnetostriction metrology for magnetic films and multilayers  

NASA Astrophysics Data System (ADS)

The requirements for metrology of magnetostriction in complex multilayers and on whole wafers present challenges. An elegant technique based on radius of curvature deformation of whole wafers in a commercial metrology tool is described. The method is based on the Villari effect through application of strain to a film by introducing a radius of curvature. Strain can be applied tensilely and compressively depending on the material. The design, while implemented on 3? wafers, is scalable. The approach removes effects arising from any shape anisotropy that occurs with smaller samples, which can lead to a change in magnetic response. From the change in the magnetic anisotropy as a function of the radius, saturation magnetostriction ?s can be determined. Dependence on film composition and film thickness was studied to validate the radius of curvature approach with other techniques. ?s decreases from positive values to negative values through an increase in Ni concentration around the permalloy composition, and ?s also increases with a decrease in film thickness, in full agreement with previous reports. We extend the technique by demonstrating the technique applied to a multi-layered structure. These results verify the validity of the method and are an important step to facilitate further work in understanding how manipulation of multilayered films can offer tailored magnetostriction.

Hill, C. B.; Hendren, W. R.; Bowman, R. M.; McGeehin, P. K.; Gubbins, M. A.; Venugopal, V. A.

2013-04-01

443

Microstructuring and wafering of silicon with laser chemical processing  

NASA Astrophysics Data System (ADS)

Laser processing is an important application for fabrication of silicon solar cells, e.g. buried contacts, laser fired contacts or edge isolation. At Fraunhofer ISE a liquid-jet guided laser is used for Laser Chemical Processing (LCP). Both the fundamentals of laser material ablation with this system and the application of various processes for solar cell fabrication are investigated. The applications are divided into two main areas: Microstructuring and deep laser cutting (wafering) of silicon substrates. Microstructuring contains the investigation and characterization of laser induced damage and selective emitter formation for n- and p-type emitters depending on laser parameters and liquid properties. One of the most important and industrially relevant topics at the moment is the formation of a selective highly doped emitter under the metal fingers of solar cells. Wafering deals with the evaluation of suitable laser parameters, adequate chemicals or chemical additives and the understanding of ablation processes by simulation and experimental work. In this presentation newest results concerning n-type doping for varying laser and liquid parameters will be presented with regard to cell efficiency and contact resistance. Furthermore a short overview of promising LCP applications will be given, e.g. p-type doping and wafering.

Hopman, Sybille; Fell, Andreas; Mayer, Kuno; Rodofili, Andreas; Granek, Filip

2010-02-01

444

Novel analytical methods for the characterization of oral wafers.  

PubMed

This study aims at compensating the lack of adequate methods for the characterization of the novel dosage forms buccal wafers by applying recent advanced analytical techniques. Fast-dissolving oral wafers need special methods for assessing their properties in drug development and quality control. For morphologic investigations, scanning electron microscopy (SEM) and near-infrared chemical imaging (NIR-CI) were used. Differences in the distribution of the active pharmaceutical ingredient within wafers can be depicted by NIR-CI. Film thickness was determined by micrometer screw and coating thickness gauge revealing no significant differences between the obtained values. To distinguish between the mechanical properties of different polymers, tensile test was performed. Suitable methods to predict disintegration behaviour are thermomechanical analysis and contact angle measurement. The determination of drug release was carried out by three different methods. Fibre-optic sensor systems allow an online measurement of the drug release profiles and the thorough analysis even within the first seconds of disintegration and drug dissolution. PMID:19482082

Garsuch, Verena; Breitkreutz, Jörg

2009-09-01

445

Wafer level hermetic package and device testing of a SOI-MEMS switch for biomedical applications  

NASA Astrophysics Data System (ADS)

We have designed a wafer level chip scale package for a bi-stable SOI-MEMS dc switch using a silicon-glass hermetic seal with through the lid feedthroughs. Bonded at 365 °C, 230 V and 250 kg, they pass the fine/gross leak test after thermal cycling and mechanical shock/vibration according to MIL-STD-833, fulfilling the requirements for biomedical applications. The measured shear strength is 114 ± 26 N in correspondence with the theoretically expected 100 N. Ruthenium microcontacts are a factor of 100 more robust than gold microcontacts, being stable over 106 cycles measured in a N2 atmosphere inside the package presented here. Future work will include a more extensive bond quality assessment and continued microcontact reliability measurements.

Receveur, Rogier A. M.; Zickar, Michael; Marxer, Cornel; Larik, Vincent; de Rooij, Nicolaas F.

2006-04-01

446

Versatile wafer-level hermetic packaging technology using anodically-bondable LTCC wafer with compliant porous gold bumps spontaneously formed in wet-etched cavities  

Microsoft Academic Search

This paper reports simple and versatile technology for hermetically capping MEMS with a wet-etched LTCC (low temperature cofired ceramic) wafer by standard anodic bonding process, in which the MEMS and Au vias in the LTCC wafer are electrically connected by porous Au bumps. The porous Au bump is spontaneously formed from a part of the Au via by wet-etching the

Shuji Tanaka; Mamoru Mohri; Atsushi Okada; Hideyuki Fukushi; Masayoshi Esashi

2012-01-01

447

Wafer-level sandwiched packaging for high-yield fabrication of high-performance mems inertial sensors  

Microsoft Academic Search

A wafer-level sandwiched packaging technology is developed for micromechanical sensors such as inertial sensors, which comprise movable parts, e.g. spring-mass structures. Via a thin polymer intermediate layer of benzocyclobuene (BCB), a pre-micromachined silicon cap wafer is aligned bonded with the sensor-chip wafer. Prior to the BCB bonding, the sensor-chip wafer was formed by anodic bonding a Pyrex-7740 glass wafer to

Kun Zhang; Wei Jiang; Xinxin Li

2008-01-01

448

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements  

NASA Astrophysics Data System (ADS)

Controlling overlay errors resulting from wafer processing, such as film deposition, is essential for meeting overlay budgets in future generations of devices. Out-of-plane distortions induced on the wafer due to processing are often monitored through high-resolution wafer geometry measurements. While such wafer geometry measurements provide information about the wafer distortion, mechanics models are required to connect such measurements to overlay errors, which result from in-plane distortions. The aim of this paper is to establish fundamental connections between the out-ofplane distortions that are characterized in wafer geometry measurements and the in-plane distortions on the wafer surface that lead to overlay errors. First, an analytical mechanics model is presented to provide insight into the connection between changes in wafer geometry and overlay. The analytical model demonstrates that the local slope of the change in wafer shape induced by the deposition of a residually stressed film is related to the induced overlay for simple geometries. Finite element modeling is then used to consider realistic wafer geometries and assess correlations between the local slope of the wafer shape change induced by the deposition of a stressed film and overlay. As established previously, overlay errors only result when the stresses in the film are non-uniform, thus the finite element study considers wafers with several different nonuniform residual stress distributions. Correlation between overlay and a metric based on a corrected wafer slope map is examined. The results of the modeling and simulations are discussed and compared to recently published experimental results.

Turner, K. T.; Vukkadala, P.; Veeraraghavan, S.; Sinha, J. K.

2014-04-01

449

Highly uniform growth of 2-inch GaN wafers with a multi-wafer HVPE system  

NASA Astrophysics Data System (ADS)

A new nozzle structure was developed in an improved multi-wafer hybrid vapor phase epitaxy (IHVPE) system by adding an inner dilution gas (ID) pipe between V and III groups gas channels. Experimental results showed that the thickness distribution of 2-inch GaN layer depended strongly on the flow rate of ID gas. The uniformity of film can arrive at ±3-4% by optimizing ID gas, which was better than that of ±30% grown in the old conventional multi-wafer hybrid vapor phase epitaxy (CHVPE) system. Meanwhile, the crystal quality and surface morphology were also greatly improved for GaN film by using the new reactor structure. The FWHM values of (002) and (102) were reduced from 342? and 806? to 207? and 254?, respectively. AFM result of surface roughness (RMS, 10 ?m×10 ?m) of GaN layer was also lowered from 1.226 nm to 0.798 nm. It was partly because of the suppression of parasitic polycrystalline deposition due to the ID gas. This simple and economic method could provide an effective solution to simultaneously fabricate multiple GaN wafer with good thickness uniformity, high crystal quality and low cost.

Liu, Nanliu; Wu, Jiejun; Li, Wenhui; Luo, Ruihong; Tong, Yuzhen; Zhang, Guoyi

2014-02-01

450

Chip-scale atomic magnetometer Peter D. D. Schwindt,a)  

E-print Network

of the sensor is a microfabricated rubidium vapor cell that is made by anodically bonding a glass waferChip-scale atomic magnetometer Peter D. D. Schwindt,a) Svenja Knappe, Vishal Shah,b) Leo Hollberg. The device's design is amenable to wafer-level fabrication in which wa- fers containing hundreds of each

Bentz, Dale P.

451

Improved surface quality of anisotropically etched silicon {111} planes for mm-scale integrated optics  

E-print Network

We have studied the surface quality of millimeter-scale optical mirrors produced by etching CZ and FZ silicon wafers in potassium hydroxide to expose the $\\{111\\}$ planes. We find that the FZ surfaces have four times lower noise power at spatial frequencies up to $500\\, {mm}^{-1}$. We conclude that mirrors made using FZ wafers have higher optical quality.

Cotter, J P; Kraft, M; Hinds, E A

2013-01-01

452

Improved surface quality of anisotropically etched silicon {111} planes for mm-scale optics  

NASA Astrophysics Data System (ADS)

We have studied the surface quality of millimetre-scale optical mirrors produced by etching CZ and FZ silicon wafers in potassium hydroxide to expose the {111} planes. We find that the FZ surfaces have four times lower noise power at spatial frequencies up to 500?mm-1. We conclude that mirrors made using FZ wafers have higher optical quality.

Cotter, J. P.; Zeimpekis, I.; Kraft, M.; Hinds, E. A.

2013-11-01

453

On the residual stress and fracture strength of crystalline silicon wafers  

NASA Astrophysics Data System (ADS)

This letter reports on residual stress measurement in thin crystalline silicon wafers with a full-field near-infrared polariscope. Residual stress is analyzed in combination with observed surface defects, and the results are related to measured fracture strength variation in the wafers. Measurements indicate that there is a sawing process-related residual stress in the as-cut wafers, and that etch-removal of ˜5 ?m from the wafer surface eliminates a damage layer that can significantly reduce the residual stress in the wafer, and therefore increases the observed fracture strength. There is a corresponding 2 to 3 ?m reduction in the observed characteristic defect size after etching. Fracture strength anisotropy observed in the wafers is related to defect orientation (scratching grooves and microcracks) caused by the sawing process.

Yang, Chris; Mess, Frank; Skenes, Kevin; Melkote, Shreyes; Danyluk, Steven

2013-01-01

454

Plasma-assisted InP-to-Si low temperature wafer bonding  

Microsoft Academic Search

The applicability of wafer bonding as a tool to integrate the dissimilar material system InP-to-Si is presented and discussed with recent examples of InP-based optoelectronic devices on Si. From there, the lowering of annealing temperature in wafer bonding by plasma-assisted bonding is the essence of this review paper. Lower annealing temperatures would further launch wafer bonding as a competitive technology

Donato Pasquariello; Klas Hjort

2002-01-01

455

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing  

NASA Technical Reports Server (NTRS)

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

456

Optical pressure sensor head fabrication using ultrathin silicon wafer anodic bonding  

Microsoft Academic Search

A technology for fabricating fiber optically interrogated pressure sensors is described. This technology is based on anodic bonding of ultra-thin silicon wafers to patterned, micro-machined glass wafers, providing low-cost fabrication of optical pressure sensor heads that operate with reproducible technical characteristics in various dynamic ranges. Pressure sensors using 10, 20 and 50 micron thick silicon wafers for membranes have been

Michael H. Beggans; Dentcho I. Ivanov; Steven G. Fu; Thomas G. Digges; Kenneth R. Farmer

1999-01-01

457

A Material Removal Model for CMP Based on the Contact Mechanics of Pad, Abrasives, and Wafer  

Microsoft Academic Search

Applied pressure in chemical mechanical polishing CMP is shared by the two-body pad-wafer and the three-body pad-abrasive- wafer contacts. The fraction of applied pressure transferred through the particle contacts is a significant factor as most of the material removal is due to abrasive particles trapped in the pad-wafer interface. In this work, the contact of a rough, deformable pad and

Dinc?er Bozkaya; Sinan Mu?ftu?

2009-01-01

458

Photoelastic strain measurement in GaP (100) wafers under external stresses  

Microsoft Academic Search

The sign of the absolute value of residual strain measured in LEC-grown GaP wafers with scanning infrared polariscope (SIRP)\\u000a has been determined by measuring the residual strain in the round-shape wafer with and without compressive load to the diametric\\u000a edges. Since the external stress induced by the compressive load is additive to the residual strain in wafer, the residual\\u000a strain

M. Fukuzawa; M. Yamada

2008-01-01

459

Low temperature plasma-assisted wafer bonding and bond-interface stress characterization  

Microsoft Academic Search

This paper presents the development and characterization of a low temperature plasma-assisted direct wafer bonding process for structured silicon wafer pairs. We have achieved spontaneous bonding at room temperature with a surface energy of up to 1.2 J\\/m2. It turned out that the bonding process is not deteriorated by the history of the wafers, even after etching for several hours.

A. Doll; F. Goldschmidtboeing; P. Woias

2004-01-01

460

Prestressed Ceramic Coatings for Enhanced Reliability of Silicon Wafer Fracture Strength  

Microsoft Academic Search

The objective of this paper is to investigate thin, solid, prestressed ceramic films as a means of enhancing the reliability of silicon semiconductor wafers stressed in bending. To characterize the effect of thin films on strength, one-micrometer ceramic films were deposited on wafers using plasma-enhanced chemical-vapor deposition. The modulus of rupture (MOR) of the coated wafers was determined from four-point

Karl Yoder; Mike Dwyer; N. D'Souza

2007-01-01

461

Science and technology of plasma activated direct wafer bonding  

NASA Astrophysics Data System (ADS)

This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

Roberds, Brian Edward

462

Alternative fabrication process for edgeless detectors on 6 in. wafers  

NASA Astrophysics Data System (ADS)

VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150 ?m thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 5×5 and 1×1 cm2 edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.4×1.4 cm2 Medipix2 edgeless pixel detectors were also fabricated.This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100 ?m from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50-70 nA/cm2 and 580-660 pF/cm2 at, respectively, 40 V reverse bias for the p-on-n. For the n-on-n design these parameters were 116-118 nA/cm2 and 930-960 pF/cm2. The breakdown voltages were above 150 V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13-28 V.

Kalliopuska, Juha; Eränen, Simo; Virolainen, Tuula

2011-05-01

463

Wafer-level manufacturing technology of glass microlenses  

NASA Astrophysics Data System (ADS)

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

464

Transfer of InP epilayers by wafer bonding  

NASA Astrophysics Data System (ADS)

Wafer bonding increases the freedom of design in the integration of dissimilar materials. For example, it is interesting to combine III-V compounds that have direct band gap and high mobility with silicon (Si) that is extensively used in microelectronic applications. The interest to integrate III-V-based materials with Si arises primarily from two types of applications: smart pixels for optical intra- and inter-chip interconnects in the so-called optoelectronic integrated circuits, and optoelectronic devices using some material advantages of combining III-V with Si. Also, in the III-V industry larger substrates are crucial for higher efficiency in high-volume production, and especially so for monolithic microwave integrated circuits (MMIC). For indium phosphide (InP) the development of large-area substrates has not been able to keep up with market demands. One way to circumvent this problem is to use silicon substrates that are large-area, low-cost, and mechanically strong with high thermal conductivity. In addition, silicon is transparent at the emission wavelengths most often used in InP-based optoelectronics. Unfortunately, the large lattice-mismatch, 8.1%, between silicon and InP, has limited the success of heteroepitaxial growth. Hence, one alternative to be reviewed is InP-to-Si wafer bonding. When a direct semiconductor interface is not needed there are several other means of wafer bonding, e.g. adhesive, eutectic, and solid-state. These processes can be used for direct integration of small islets of epitaxially thin InP microelectronics onto other substrates, e.g. by transferring of InP-based epilayers to a Si-based microwave circuit by pick-and-place, BCB resist adhesive bonding and sacrificing of the InP substrate.

Hjort, Klas

2004-08-01

465

Pressureless wafer bonding by turning hillocks into abnormal grain growths in Ag films  

NASA Astrophysics Data System (ADS)

We demonstrate pressureless wafer bonding using silver abnormal grain growth caused by stress migration at 250 °C, which is very low for a direct solid-state bonding temperature. The bonding achieved a die-shear strength of more than 50 MPa, which exceeds the fracture toughness of Si wafer. Various deposition temperatures for the silver films, i.e., initial residual stress, reveal that the bonding process is driven by thermomechanical stress. Abnormal grain growth is induced at the contact interface instead of hillocks growing on the film surface. Pressureless wafer bonding can be applied to advanced devices such as thin-wafer multi-chip integrations.

Oh, Chulmin; Nagao, Shijo; Kunimune, Teppei; Suganuma, Katsuaki

2014-04-01

466

Improved quality control of silicon wafers using novel off-line air pocket image analysis  

NASA Astrophysics Data System (ADS)

Air pockets (APK) occur randomly in Czochralski (Cz) grown silicon (Si) crystals and may become included in wafers after slicing and polishing. Previously the only APK of interest were those that intersected the front surface of the wafer and therefore directly impacted device yield. However mobile and other electronics have placed new demands on wafers to be internally APK-free for reasons of thermal management and packaging yield. We present a novel, recently patented, APK image processing technique and demonstrate the use of that technique, off-line, to improve quality control during wafer manufacturing.

Valley, John F.; Sanna, M. Cristina

2014-08-01

467

The optimization of CD uniformity and measurement on mask and wafer  

NASA Astrophysics Data System (ADS)

As pattern size is shrinking, required mask CD specification is tighter and its effect on wafer patterning is more severe. To enhance the device performance, wafer CD uniformity should be enhanced and controlled by mask global CD uniformity. Mask global CD uniformity usually can be enhanced by mask process and optimal fogging effect correction. To enhance the mask global CD uniformity on mask, resist process and FEC (Fogging Effect Correction), reliable CD measurement tool and methods are necessary. Recently, group CD using OCD(Spectroscopic Ellipsometer) or AIMS(Aerial Image Measurement and Simulation) is used to represent global CD variation on mask. These methods are removing local CD variation on mask. Because local CD variation on wafer is large compared with the effect of local CD variation of mask, global CD uniformity can be measured with suppressed local CD variation [1]. In this paper, local CD variation of mask and wafer is evaluated, and area CD and smoothing methods are used to measure CD on mask and wafer, and the correlation of global CD of mask and field CD of wafer are evaluated. By these methods, CD measurement repeatability can be enhanced to get closer correlation of mask and wafer. Close correlation makes fine CD correction on mask to get better field CD uniformity on wafer. And the repeatability of field to field CD uniformity of wafer is evaluated according to measurement tool of CD-SEM and scatterometry.

Choi, Yongkyoo; Kim, Munsik; Han, Oscar

2007-05-01

468

Determination of wafer center position during the transfer process by using the beam-breaking method  

NASA Astrophysics Data System (ADS)

A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human-machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions.

Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

2014-09-01

469

Thermal oxidation of polycrystalline and single crystalline aluminum nitride wafers  

Microsoft Academic Search

Two types of aluminum nitride (AlN) samples were oxidized in flowing oxygen between 900C and 1150C for up to 6 h—highly\\u000a (0001) textured polycrystalline AlN wafers and low defect density AlN single crystals. The N-face consistently oxidized at\\u000a a faster rate than the Al-face. At 900C and 1000C after 6 h, the oxide was 15% thicker on the N-face than

Z. Gu; J. H. Edgar; S. A. Speakman; D. Blom; J. Perrin; J. Chaudhuri

2005-01-01

470

Characterization of wafer charging mechanisms and oxide survival prediction methodology  

SciTech Connect

Unipolar, EEPROM-based peak potential sensors and current sensors have been used to characterize the I-V relationship of charging transients which devices normally experience during the course of ion implantation. The results indicate that the charging sources may appear to behave like current-sources or voltage-sources, depending on the impedance of the load. This behavior may be understood in terms of plasma concepts. The ability to empirically characterize the I-V characteristics of charging sources using the CHARM-2 monitor wafers opens the way for prediction of failure rates of oxides subjected to specific processes, if the oxide Q{sub bd} distributions are known.

Lukaszek, W.; Dixon, W. [Stanford Univ., CA (United States). Center for Integrated Systems; Vella, M. [Lawrence Berkeley Lab., CA (United States). Accelerator and Fusion Research Div.; Messick, C.; Reno, S.; Shideler, J. [National Semiconductor, West Jordan, UT (United States)

1994-04-01

471

New mixed LiGa0.5In0.5Se2 nonlinear crystal for the mid-IR  

NASA Astrophysics Data System (ADS)

LiGaSe2 and LiInSe2 are promising nonlinear crystals for conversion of laser radiation to the mid-IR spectral range which are transparent down to the visible and UV. We successfully grew a new mixed crystal as a solid solution in the system LiGaSe2 - LiInSe2, with a composition of LiGa0.5In0.5Se2 which has the same orthorhombic structure (mm2) as the parent compounds (LiGaSe2 and LiInSe2). The new crystal is more technological with regard to the growth process in comparison with LiGaSe2 and LiInSe2 since its homogeneity range is broader in the phase diagram. We established that about 10% of the Li ions are foun