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1

Design automation for wafer scale integration  

SciTech Connect

Wafer scale integration (WSI) is a technique for implementing large digital systems on a single wafer. This thesis describes a system of design automation tools developed to aid in the implementation of wafer scale integrated systems. An overview of wafer scale integration is given with fabrication details and yield considerations discussed. The Wafer architectural Design Language (WDL) used to describe and specify a system architecture to the development system is introduced along with a compiler that translates the high level WDL description into net lists and other internal data bases. Interactive placement tools used to map the system architecture onto the functional die sites on a wafer are described. A very fast line probe router was developed to perform the custom wafer level routing need to personalize each wafer. Router data structures, algorithms, techniques, and results are discussed in detail. Sample wafer scale architectures and the result of their WSI implementations are shown. Also presented is the Wafer Transmission Module (WTM) a packaging technology related to wafer scale integration.

Donlan, B.J.

1986-01-01

2

An interconnect structure for wafer scale neurocomputers  

Microsoft Academic Search

Silicon technology has two limitations: fabrication defects and limited interconnect. The authors believe the fault-tolerance of neural network models can compensate for fabrication defects. In this paper the authors present the design of an interconnect structure for wafer scale neural network emulation based on CMOS silicon technology that solves the interconnect problem. Thus, massively parallel, wafer scale neurocomputer architectures are

M. Rudnick; D. Hammerstrom

1988-01-01

3

An interconnect structure for wafer scale neurocomputers  

SciTech Connect

Silicon technology has two limitations: fabrication defects and limited interconnect. The authors believe the fault-tolerance of neural network models can compensate for fabrication defects. In this paper the authors present the design of an interconnect structure for wafer scale neural network emulation based on CMOS silicon technology that solves the interconnect problem. Thus, massively parallel, wafer scale neurocomputer architectures are feasible. Their design is part of the Cognitive Architecture Project (CAP) at the Oregon Graduate Center. The CAP architecture is a hybrid using analog computation and multiplexed digital interconnect. The long term goal is to emulate a million nodes, each with a thousand connections, on a single wafer.

Rudnick, M.; Hammerstrom, D.

1988-09-01

4

Wafer-scale micro-optics fabrication  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

Voelkel, Reinhard

2012-07-01

5

ORIGINAL ARTICLE Wafer-scale fabricated thermo-pneumatically tunable  

E-print Network

ORIGINAL ARTICLE Wafer-scale fabricated thermo-pneumatically tunable microlenses Wei Zhang, Hans on polyacrylate membranes integrated with compact on-chip thermo-pneumatic actuation fabricated using full Keywords: optofluidics; thermo-pneumatic actuation; tunable microlens; wafer-scale fabrication INTRODUCTION

Cai, Long

6

Wafer-Scale Microtensile Testing of Thin Films  

Microsoft Academic Search

This paper reports on the mechanical characterization of thin films using the microtensile technique performed for the first time at the wafer scale. Multiple test structures are processed and sequentially measured on the same silicon substrate, thus eliminating delicate handling of individual samples. The current layout uses 26 test structures evenly distributed over a 4-in wafer, each of them carrying

JoÃo Gaspar; Marek E. Schmidt; Jochen Held; Oliver Paul

2009-01-01

7

Wafer-scale aluminum nano-plasmonics  

NASA Astrophysics Data System (ADS)

The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

2014-09-01

8

Parallel Assembly of LIGA Components  

SciTech Connect

In this paper, a prototype robotic workcell for the parallel assembly of LIGA components is described. A Cartesian robot is used to press 386 and 485 micron diameter pins into a LIGA substrate and then place a 3-inch diameter wafer with LIGA gears onto the pins. Upward and downward looking microscopes are used to locate holes in the LIGA substrate, pins to be pressed in the holes, and gears to be placed on the pins. This vision system can locate parts within 3 microns, while the Cartesian manipulator can place the parts within 0.4 microns.

Christenson, T.R.; Feddema, J.T.

1999-03-04

9

Wafer Scale Homogeneous Bilayer Graphene Films by Chemical Vapor Deposition  

E-print Network

are fabricated using mechanical exfoliation of graphite,15-18 which have limited sizes of µm2 and are certainlyWafer Scale Homogeneous Bilayer Graphene Films by Chemical Vapor Deposition Seunghyun Lee gap opening in bilayer graphene opens a new door for making semiconducting graphene without aggressive

Zhong, Zhaohui

10

Liga developer apparatus system  

DOEpatents

A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

Boehme, Dale R. (Pleasanton, CA); Bankert, Michelle A. (San Francisco, CA); Christenson, Todd R. (Albuquerque, NM)

2003-01-01

11

Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays  

NASA Technical Reports Server (NTRS)

The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

2009-01-01

12

High speed wafer scale bulge testing for the determination of thin film mechanical properties  

Microsoft Academic Search

A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50-150 mm)

M. P. Orthner; L. W. Rieth; F. Solzbacher

2010-01-01

13

Development of Three Dimensional LIGA Process to Fabricate Spiral Microcoil  

Microsoft Academic Search

The LIGA process has been developed as a 2.5-dimensional processing method on Si wafers to date. However, we have succeeded in extending the LIGA process to 3D for the first time. 3D-LIGA was achieved by the technical development of 3D X-ray lithography and worm injection molding replication technology with unscrewing. These technologies began from the development of equipment and have

Harutaka Mekaru; Shinji Kusumi; Noriaki Sato; Masami Shimizu; Michiru Yamashita; Osamu Shimada; Tadashi Hattori

2005-01-01

14

Laser removal of Aluminum links for applications in wafer scale integrated circuits  

E-print Network

LASER REMOVAL OF ALUMINUM LINKS FOR APPLICATIONS IN WAFER SCALE INTEGRATED CIRCUITS A Thesis by HARSHAVADAN B. PARIKH Submitted to the Graduate College of Texas A&M University in partial fulfillment of the requirement for the degree... of MASTER OF SCIENCE May 1987 Major Subject: Electrical Engineering LASER REMOVAL OF ALUMINUM LINKS FOR APPLICATIONS IN WAFER SCALE INTEGRATED CIRCUITS A Thesis HARSHAVADAN B. PARIKH Approved ss to style snd content by: M. H, Weichold (Chairman...

Parikh, Harshavadan B.

2012-06-07

15

Wafer-scale fabrication of plasmonic crystals from patterned silicon templates prepared by nanosphere lithography.  

PubMed

By combining nanosphere lithography with template stripping, silicon wafers were patterned with hexagonal arrays of nanowells or pillars. These silicon masters were then replicated in gold by metal evaporation, resulting in wafer-scale hexagonal gratings for plasmonic applications. In the nanosphere lithography step, two-dimensional colloidal crystals of 510 nm diameter polystyrene spheres were assembled at the air-water interface and transferred to silicon wafers. The spheres were etched in oxygen plasma in order to define their size for masking of the silicon wafer. For fabrication of metallic nanopillar arrays, an alumina film was grown over the nanosphere layer and the spheres were then removed by bath sonication. The well pattern was defined in the silicon wafer by reactive ion etching in a chlorine plasma. For fabrication of metal nanowell arrays, the nanosphere monolayer was used directly as a mask and exposed areas of the silicon wafer were plasma-etched anisotropically in SF6/Ar. Both techniques could be used to produce subwavelength metal replica structures with controlled pillar or well diameter, depth, and profile, on the wafer scale, without the use of direct writing techniques to fabricate masks or masters. PMID:23614608

Hall, Anthony Shoji; Friesen, Stuart A; Mallouk, Thomas E

2013-06-12

16

Study on Board Level Drop Reliability of Wafer Level Chip Scale Package with Leadfree Solder  

Microsoft Academic Search

Wafer level chip scale package (WLCSP) is a promising packaging technology to accommodate the demand for small, portable handheld electronic. This bare-die bumped package is able to offer significant area savings, improve package electrical parasitics and power dissipation performance over substrate-based BGA packages. However, its board level reliability especially mechanical performance under shock impact is a great concern for handheld

Zhang Xueren; Zhu Wenhui; P. Edith; Tan Hien Boon

2008-01-01

17

Wafer-Scale Fabrication of Nanofluidic Arrays and Networks Using Nanoimprint Lithography and Lithographically Patterned Nanowire  

E-print Network

Wafer-Scale Fabrication of Nanofluidic Arrays and Networks Using Nanoimprint Lithography of nanofluidic channels (up to 1 mm in length) filled with solutions of either fluorescent dye or 20 nm diameter-replica process was also used to create a large two-dimensional network of crossed nanofluidic channels. Large

18

Wafer-scale nanoconical frustum array crystalline silicon solar cells: promising candidates for ultrathin device applications.  

PubMed

A high photocurrent of 36.96 mA cm(-2) was achieved for wafer-scaled crystalline Si solar cells with hexagonal nanoconical frustum arrays at the surface. Optical simulations showed that the expected photocurrent of 10 ?m thick nanostructured cells could slightly exceed the Lambertian limit. PMID:25001318

Cho, Yunae; Gwon, Minji; Park, Hyeong-Ho; Kim, Joondong; Kim, Dong-Wook

2014-08-21

19

On the chemo-mechanical polishing for nano-scale surface finish of brittle wafers.  

PubMed

Chemo-mechanical polishing (CMP) has been a common method to produce nano-scale surface finish of brittle wafers. This paper provides a relatively comprehensive review on the CMP of silicon, silicon carbide and sapphire including both patents and papers. The discussion includes the limitations and further research directions of the CMP technology, the material removal mechanisms, and the control and optimization of the CMP for brittle wafers. The paper concluded that the usage of mix- or coated- abrasives may improve the CMP in terms of less subsurface damage and higher material removal rate. PMID:20415661

Wang, Y G; Zhang, L C

2010-06-01

20

Control of wafer-scale non-uniformity in chemical-mechanical planarization by face-up polishing  

E-print Network

Chemical-mechanical planarization (CMP) is a key process in the manufacture of ultra-large-scale-integrated (ULSI) semiconductor devices. A major concern in CMP is non-uniform planarization, or polishing, at the wafer-scale ...

Mau, Catherine (Catherine K.)

2008-01-01

21

Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments.  

PubMed

We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the microchannels, and alignment precision. Experiments on lipid bilayers with electrophysiological recordings using a model pore-forming polypeptide are demonstrated. PMID:25284632

Bomer, Johan G; Prokofyev, Alexander V; van den Berg, Albert; Le Gac, Séverine

2014-12-01

22

Drop impact life prediction model for wafer level chip scale packages  

Microsoft Academic Search

The demand for small, portable handheld electronic devices has led OEMs to reduce packaging sizes of all types and to create many choices to meet market demand. Wafer-level chip scale package (WL-CSP) is the newest technology to compete with CSP and near-CSP packaging, and has evolved under JEDEC MO-211 standard. This bare-die bumped package is able to reduce single-gate logic

Kim Yong Goh; Jing-en Luan; Tong Yan Tee

2005-01-01

23

A hydrogen separation module based on wafer-scale micromachined palladium-silver alloy membranes  

Microsoft Academic Search

A thin but strong and defect free palladium-silver (Pd-Ag) alloy membrane is fabricated with a sequence of well-known thin film and micromachining techniques. A microfabrication process also creates a robust wafer-scale membrane module, which is easy to be integrated into a membrane holder to have gastight connections to the outer world. The microfabricated membranes have been tested to determine the

H. D. TonKa; F. C. Gielens; H. T. Hoanga; J. W. Berenschota; M. J. De Boer; J. G. E. Gardeniers; H. V. Jansen; W. Nijdam; C. J. M. van Rijn; M. C. Elwenspoeka

2003-01-01

24

Self-adaptive phosphor coating technology for wafer-level scale chip packaging  

NASA Astrophysics Data System (ADS)

A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.

Linsong, Zhou; Haibo, Rao; Wei, Wang; Xianlong, Wan; Junyuan, Liao; Xuemei, Wang; Da, Zhou; Qiaolin, Lei

2013-05-01

25

CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.  

PubMed

Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits. PMID:19086836

Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

2009-01-01

26

Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices  

PubMed Central

In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32?A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50?kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

2014-01-01

27

Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices  

NASA Astrophysics Data System (ADS)

In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices.

Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

2014-01-01

28

Novel Fabrication Techniques for Wafer-Scale Graphene Drum NanoElectroMechanical Resonators  

NASA Astrophysics Data System (ADS)

Graphene NanoElectroMechanical Systems (NEMS) have shown excellent mass sensitivity as well as resonant and oscillatory behaviors that are desirable in mass sensors and active elements in Radio Frequency Integrated Circuit (RFIC) design. Out of many structures proposed for graphene NEMS, it has been recently shown that a drum resonator exhibits higher Q-factor than other structures such as a bar resonator. However, fabricating a large array of drum graphene resonator has been problematic because liquid or gas can be trapped inside the drum. Such issues led to designs with a hole in the center of a drum or with a drainage trench, either at the cost of additional lithography step or lowered Q-factor. Here, we demonstrate two novel fabrication methods that are free of the trapping without any compromise in additional lithography step or Q-factor degradation. In one method, wafer scale graphene is dry-stamped on prefabricated leads, holes and local gates. In the other method, an resist strip with a circular hole at the center holds graphene underneath. I will discuss direct electrical readout and characterization of devices using these two methods. These drum structures may provide a practical way to achieve wafer scale high Q graphene NEMS.

Lee, Sunwoo; Chen, Changyao; Deshpande, Vikram V.; Lee, Gwan Hyoung; Storch, Isaac; Zhang, Congchun; Yu, Young-Jun; Kim, Philip; McEuen, Paul; Hone, James

2012-02-01

29

Wafer scale imprint uniformity evaluated by LSPR spectroscopy: a high volume characterization method for nanometer scale structures.  

PubMed

We exploit the localized surface-plasmon resonance (LSPR) of terahertz gold gammadion structures for wafer scale critical dimension metrology of nanostructures. The proposed characterization method, LSPR spectroscopy, is based on optical transmission measurements and is benchmarked against numerical simulations of imprinted structures characterized by atomic force microscopy. There is a fair agreement between the two methods and the simulations enable the translation of optical spectra to critical dimensions of the physical structures, a concept known from scatterometry. The results demonstrate the potential of LSPR spectroscopy as an alternative characterization method to scanning electron microscopy, atomic force microscopy and scatterometry. PMID:22948403

Jeppesen, Claus; Lindstedt, Daniel Nilsson; Vig, Asger Laurberg; Kristensen, Anders; Mortensen, N Asger

2012-09-28

30

Uniformity study of wafer-scale InP-to-silicon hybrid integration  

NASA Astrophysics Data System (ADS)

In this paper we study the uniformity of up to 150 mm in diameter wafer-scale III-V epitaxial transfer to the Si-on-insulator substrate through the O2 plasma-enhanced low-temperature (300°C) direct wafer bonding. Void-free bonding is demonstrated by the scanning acoustic microscopy with sub-?m resolution. The photoluminescence (PL) map shows less than 1 nm change in average peak wavelength, and even improved peak intensity (4% better) and full width at half maximum (41% better) after 150 mm in diameter epitaxial transfer. Small and uniformly distributed residual strain in all sizes of bonding, which is measured by high-resolution X-ray diffraction Omega-2Theta mapping, and employment of a two-period InP-InGaAsP superlattice at the bonding interface contributes to the improvement of PL response. Preservation of multiple quantum-well integrity is also verified by high-resolution transmission electron microscopy.

Liang, Di; Chapman, David C.; Li, Youli; Oakley, Douglas C.; Napoleone, Tony; Juodawlkis, Paul W.; Brubaker, Chad; Mann, Carl; Bar, Hanan; Raday, Omri; Bowers, John E.

2011-04-01

31

Advancing quasi-freestanding epitaxial graphene electronics through integration of wafer scale hexagonal boron nitride dielectrics  

NASA Astrophysics Data System (ADS)

A key limitation to graphene based electronics is graphene's interaction with dielectric interfaces. SiO2 and various high-k gate dielectrics can introduce scattering from charged surface states, impurities, and surface optical phonons; degrading the transport properties of graphene. Hexagonal boron nitride (h-BN) exhibits an atomically smooth surface that is expected to be free of dangling bonds, leading to an interface that is relatively free of surface charge traps and adsorbed impurities. Additionally, the decreased surface optical phonon interaction from h-BN is expected to further reduce scattering. While h-BN gated graphene FETs have been demonstrated on a small scale utilizing CVD grown or exfoliated graphene, integrating quasi-freestanding epitaxial graphene (QFEG) with h-BN gate dielectrics on a wafer scale has not been explored. We present results from the first large scale CVD growth of h-BN and its subsequent transfer to a 75mm QFEG wafer. The effects of growth conditions on the thickness and quality of the h-BN film and its potential and limitations as a gate dielectric to QFEG are discussed. The introduction of charged impurities during the transfer process resulted in an average degradation in mobility of only 9%. Despite the slight degradation, we show that h-BN is highly beneficial compared to high-k dielectrics when the charged impurity concentration of QFEG is below 5x1012cm-2. Here we show improvements in mobility of >3x and intrinsic cutoff frequency of >2x compared to HfO2.

Bresnehan, Michael S.; Hollander, Matthew J.; Marucci, Rebecca L.; LaBella, Michael; Trumbull, Kathleen A.; Cavalero, Randal; Snyder, David W.; Robinson, Joshua A.

2012-09-01

32

Wafer-scale fabrication of silicon nanowire arrays with controllable dimensions  

NASA Astrophysics Data System (ADS)

A novel and facile method was successfully developed to fabricate wafer-scale Si nanowire arrays with well-controlled sizes through the in-situ porous anodic alumina (PAA) template-assisted wet-etching process. The diameter and filling ratio (inter-wire spacing) of the as-prepared Si nanowires are determined by the size and density of pores in the in-situ PAA templates, which can be tailored independently by adjusting the anodization voltages and the immersion time of PAA templates in phosphoric acid. The length of Si nanowires can be more than one hundred micrometers long, which is controlled by adjusting the wet-etching time. Moreover, this method is compatible with complex Si surface topology for creating desirable 3-dimensional hybrid micro/nano-structures. Such Si nanowire arrays exhibit ultralow reflectance and interesting wettability that are of great importance to photovoltaics and thermal management applications.

Wang, Wei; Li, Dan; Tian, Miao; Lee, Yung-Cheng; Yang, Ronggui

2012-09-01

33

Wafer-scale design of lightweight and transparent electronics that wraps around hairs  

NASA Astrophysics Data System (ADS)

Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-?m thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12?V and above 1?MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

Salvatore, Giovanni A.; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

2014-01-01

34

Wafer-scale MoS2 thin layers prepared by MoO3 sulfurization  

NASA Astrophysics Data System (ADS)

Atomically thin molybdenum disulfide (MoS2) layers have attracted great interest due to their direct-gap property and potential applications in optoelectronics and energy harvesting. Meanwhile, they are extremely bendable, promising for applications in flexible electronics. However, the synthetic approach to obtain large-area MoS2 atomic thin layers is still lacking. Here we report that wafer-scale MoS2 thin layers can be obtained using MoO3 thin films as a starting material followed by a two-step thermal process, reduction of MoO3 at 500 °C in hydrogen and sulfurization at 1000 °C in the presence of sulfur. Spectroscopic, optical and electrical characterizations reveal that these films are polycrystalline and with semiconductor properties. The obtained MoS2 films are uniform in thickness and easily transferable to arbitrary substrates, which make such films suitable for flexible electronics or optoelectronics.Atomically thin molybdenum disulfide (MoS2) layers have attracted great interest due to their direct-gap property and potential applications in optoelectronics and energy harvesting. Meanwhile, they are extremely bendable, promising for applications in flexible electronics. However, the synthetic approach to obtain large-area MoS2 atomic thin layers is still lacking. Here we report that wafer-scale MoS2 thin layers can be obtained using MoO3 thin films as a starting material followed by a two-step thermal process, reduction of MoO3 at 500 °C in hydrogen and sulfurization at 1000 °C in the presence of sulfur. Spectroscopic, optical and electrical characterizations reveal that these films are polycrystalline and with semiconductor properties. The obtained MoS2 films are uniform in thickness and easily transferable to arbitrary substrates, which make such films suitable for flexible electronics or optoelectronics. Electronic supplementary information (ESI) available. See DOI: 10.1039/c2nr31833d

Lin, Yu-Chuan; Zhang, Wenjing; Huang, Jing-Kai; Liu, Keng-Ku; Lee, Yi-Hsien; Liang, Chi-Te; Chu, Chih-Wei; Li, Lain-Jong

2012-09-01

35

High speed wafer scale bulge testing for the determination of thin film mechanical properties  

NASA Astrophysics Data System (ADS)

A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50-150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 ?m in width comprised of 720±10 nm thick low pressure chemical vapor deposited silicon nitride with ˜20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to ˜8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (˜350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young's modulus was estimated for the films assuming a Poisson's ratio of v =0.25. Calculations to determine Young's modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young's modulus for the smaller membranes. The deflection measurements of three 1200×1200 ?m2 Si3N4-x membranes were taken at increased pressures (>25 kPa) to increase nonlinearity and better determine Young's modulus. This pressure-deflection data were fit to an analytical solution and Young's modulus estimated to be 257±3 GPa, close to those previously reported in literature.

Orthner, M. P.; Rieth, L. W.; Solzbacher, F.

2010-05-01

36

A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI  

Microsoft Academic Search

A data direct implementation (DDI) technique for reasoning hardware using a large area FPGA or a wafer scale FPGA is proposed. In the DDI design methodology, the features in the past case data are extracted and converted to the truth tables using a genetic algorithm, and the truth tables (evolved truth tables) are synthesized to the logic circuits. Whereas the

Moritoshi Yasunaga; Ikuo Yoshihara; Jung Hwan Kim

2000-01-01

37

Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale  

PubMed Central

We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13?×?107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production. PMID:24289275

2013-01-01

38

Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale  

NASA Astrophysics Data System (ADS)

We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production.

Ho, Jian-Wei; Wee, Qixun; Dumond, Jarrett; Tay, Andrew; Chua, Soo-Jin

2013-12-01

39

Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale.  

PubMed

We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13?×?107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production. PMID:24289275

Ho, Jian-Wei; Wee, Qixun; Dumond, Jarrett; Tay, Andrew; Chua, Soo-Jin

2013-01-01

40

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy  

NASA Astrophysics Data System (ADS)

The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (``metasurfaces'') can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent.

Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

2013-10-01

41

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy  

PubMed Central

The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (“metasurfaces”) can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

2013-01-01

42

Wafer-scale highly-transparent and superhydrophilic sapphires for high-performance optics.  

PubMed

We reported the wafer-scale highly-transparent and superhydrophilic sapphires with antireflective subwavelength structures (SWSs) which were fabricated by dry etching using thermally dewetted gold (Au) nanomasks. Their optical transmittance properties were experimentally and theoretically investigated. The density, size, and period of the thermally dewetted Au nanopatterns can be controlled by the Au film thickness. For the sapphire with both-side SWSs at 5 nm of Au film, the average total transmittance (T(avg)) of ~96.5% at 350-800 nm was obtained, indicating a higher value than those of the flat sapphire (T(avg)~85.6%) and the sapphire with one-side SWSs (T(avg)~91%), and the less angle-dependent transmittance property was observed. The calculated transmittance results also showed a similar tendency to the measured data. The SWSs enhanced significantly the surface hydrophilicity of sapphires, exhibiting a water contact angle (?(c)) of < 5° for Au film of 5 nm compared to ?(c)~37° of the flat sapphire. PMID:23187471

Leem, Jung Woo; Yu, Jae Su

2012-11-19

43

14C autoradiography with a novel wafer scale CMOS Active Pixel Sensor  

NASA Astrophysics Data System (ADS)

14C autoradiography is a well established technique for structural and metabolic analysis of cells and tissues. The most common detection medium for this application is film emulsion, which offers unbeatable spatial resolution due to its fine granularity but at the same time has some limiting drawbacks such as poor linearity and rapid saturation. In recent years several digital detectors have been developed, following the technological transition from analog to digital-based detection systems in the medical and biological field. Even so such digital systems have been greatly limited by the size of their active area (a few square centimeters), which have made them unsuitable for routine use in many biological applications where sample areas are typically ~ 10-100 cm2. The Multidimensional Integrated Intelligent Imaging (MI3-Plus) consortium has recently developed a new large area CMOS Active Pixel Sensor (12.8 cm × 13.1 cm). This detector, based on the use of two different pixel resolutions, is capable of providing simultaneously low noise and high dynamic range on a wafer scale. In this paper we will demonstrate the suitability of this detector for routine beta autoradiography in a comparative approach with widely used film emulsion.

Esposito, M.; Anaxagoras, T.; Larner, J.; Allinson, N. M.; Wells, K.

2013-01-01

44

Wafer scale synthesis of dense aligned arrays of single-walled carbon nanotubes  

Microsoft Academic Search

Here we present an easy one-step approach to pattern uniform catalyst lines for the growth of dense, aligned parallel arrays\\u000a of single-walled carbon nanotubes (SWNTs) on quartz wafers by using photolithography or polydimethylsiloxane (PDMS) stamp\\u000a microcontact printing (µCP). By directly doping an FeCl3\\/methanol solution into Shipley 1827 photoresist or polyvinylpyrrolidone (PVP), various catalyst lines can be well-patterned\\u000a on a wafer

Weiwei Zhou; Christopher Rutherglen; Peter J. Burke

2008-01-01

45

A wafer-scale backplane-assisted resonating nanoantenna array SERS device created by tunable thermal dewetting nanofabrication  

NASA Astrophysics Data System (ADS)

A tunable lithography-less nanofabrication process using a metal thin-film thermal dewetting technique has been developed to fabricate wafer-scale and uniform plasmonic substrates at low cost for optimal performance in surface enhanced Raman scattering (SERS) applications. The relationship between the tunable parameters of this process and the corresponding optical and plasmonic characteristic is investigated both experimentally and theoretically to understand the deterministic design of an optimal SERS device with a three-dimensional plasmonic nanoantenna structure. The enhancement of SERS using various nanoplasmonic particle sizes, structure lengths, lateral hot spot spacings and resonating effects are examined and demonstrated. We achieve a uniform optimal enhancement factor of 1.38 × 108 on a 4 in wafer-scale SERS substrate with a backplane-assisted resonating nanoantenna array design. Sensitive environmental nitrate sensing, vitamin detection and oligonucleotide identification are demonstrated on the high-performance SERS device.

Chang, Te-Wei; Ranjan Gartia, Manas; Seo, Sujin; Hsiao, Austin; Logan Liu, Gang

2014-04-01

46

Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors  

NASA Astrophysics Data System (ADS)

Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm2/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

Kim, SangHyeon; Ikku, Yuki; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung; Takenaka, Mitsuru; Takagi, Shinichi

2014-07-01

47

Wafer-scale near-perfect ordered porous alumina on substrates by step and flash imprint lithography.  

PubMed

Nanoporous anodic aluminum oxide (AAO) has been widely used for the development of various functional nanostructures. So far, highly ordered AAO on substrates could only be prepared using a nanoindentation method via hard stamping and lithographic techniques that are not scalable to a wafer-scale. Here we report on a step and flash imprint lithography (SFIL)-based method to fabricate a near-perfect ordered AAO with square and hexagonal lattice configuration on silicon substrate over 4 in. wafer areas. SFIL was used to prepattern a polymer mask layer, and wet-etching process was employed to transfer the nanopatterns to aluminum (Al) films, thus creating ordered nanoindentation on the Al surface. The ordered nanoindentation guides the growth of nanochannels in the anodization step to create the ordered nanoporous structures. The proposed wafer-scale process is compatible with standard semiconductor fabrication and offers substantial advantages over conventional Al patterning methods in terms of patterning areas, throughput, process simplicity, and process robustness, allowing up to 10 000 imprints or pattern transfer to the Al films. PMID:20411953

Kustandi, Tanu Suryadi; Loh, Wei Wei; Gao, Han; Low, Hong Yee

2010-05-25

48

Double oxide deposition and etching nanolithography for wafer-scale nanopatterning with high-aspect-ratio using photolithography  

NASA Astrophysics Data System (ADS)

We report a nanolithography technique for the high aspect-ratio nanostructure manufacturing using DODE (double oxide deposition and etching) process. Conventional microfabrication processes are integrated to manufacture nanostructure arrays with sub-100 nm of linewidth. This lithography method is developed to overcome resolution limits of photolithography. High aspect-ratio nanostructures with sub-100 nm of lindewidth were fabricated on wafer-scale substrate without nanolithography techniques. The DODE lithography process presented enabled to pave a way to overcome limitations of nanolithography processes and allowed to manufacture large-scale nanostructures using photolithography and thin film deposition and dry etching processes.

Seo, Jungho; Cho, Hanchul; Lee, Ju-kyung; Lee, Jinyoung; Busnaina, Ahmed; Lee, HeaYeon

2013-07-01

49

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays  

NASA Astrophysics Data System (ADS)

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 ?m is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 ?m × 25 ?m that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

2013-09-01

50

Integrated modeling of chemical mechanical planarization/polishing (CMP) for integrated circuit fabrication: From particle scale to die and wafer scales  

NASA Astrophysics Data System (ADS)

Chemical mechanical planarization/polishing (CMP) has obtained broad applications in sub-micron integrated circuit (IC) fabrication in recent years. These applications include inter-layer dielectrics planarization, copper damascene process and shallow trench isolation. However, the broad applications of CMP are often limited by a general lack of understanding of the process. With the technology nodes going to 65nm, a more predictable, controllable and reproducible CMP process is needed. Modeling and simulation of CMP will be critical to satisfy the requirements. This work aims to model the CMP process at three scales, namely, particle scale, die scale and wafer scale. The particle-scale model is to understand the roles and interactions of consumable parameters in CMP. The topography and material properties of the pad, abrasive particle size and size distribution, abrasive weight concentration and slurry chemicals influencing the passivation rate of wafer surface are identified as the most important parameters in the CMP material removal process. Based on the model, they contribute to the material removal through two parameters; one, the number of active abrasives over the wafer-pad interface, and the other, material removal by a single active abrasive. The number of active abrasives first depends on the pad topography and abrasive weight concentration. A rough pad can capture more abrasives. A larger abrasive weight concentration indicates a larger number of abrasives per unit volume of slurry. Further, the abrasive size distribution is critical for the number. Only a small portion of abrasives on the tail of the distribution function are involved in the material removal process. This portion is a function of the gap between wafer and pad over the contact area with abrasives in-between. Only abrasives larger than the gap, which is determined by the wafer-pad contact ratio (function of pad topography and pad Young's modulus) and pad hardness, can be involved in the material removal process. The material removed by a single active abrasive is determined by the size of abrasive and force applied on the abrasives. The force is a function of wafer-pad contact area ratio. The average size of active abrasives depends on the abrasive size distribution. The roles of abrasive size distribution in material removal are therefore two fold. While the portion is increased with the gap, the size of active abrasives becomes smaller. (Abstract shortened by UMI.)

Luo, Jianfeng

2003-10-01

51

Wafer-scale fabrication of polymer-based microdevices via injection molding and photolithographic micropatterning protocols.  

PubMed

Because of their broad applications in biomedical analysis, integrated, polymer-based microdevices incorporating micropatterned metallic and insulating layers are significant in contemporary research. In this study, micropatterns for temperature sensing and microelectrode sets for electroanalysis have been implemented on an injection-molded thin polymer membrane by employing conventional semiconductor processing techniques (i.e., standard photolithographic methods). Cyclic olefin copolymer (COC) is chosen as the polymer substrate because of its high chemical and thermal stability. A COC 5-in. wafer (1-mm thickness) is manufactured using an injection molding method, in which polymer membranes (approximately 130 microm thick and 3 mm x 6 mm in area) are implemented simultaneously in order to reduce local thermal mass around micropatterned heaters and temperature sensors. The highly polished surface (approximately 4 nm within 40 microm x 40 microm area) of the fabricated COC wafer as well as its good resistance to typical process chemicals makes it possible to use the standard photolithographic and etching protocols on the COC wafer. Gold micropatterns with a minimum 5-microm line width are fabricated for making microheaters, temperature sensors, and microelectrodes. An insulating layer of aluminum oxide (Al2O3) is prepared at a COC-endurable low temperature (approximately 120 degrees C) by using atomic layer deposition and micropatterning for the electrode contacts. The fabricated microdevice for heating and temperature sensing shows improved performance of thermal isolation, and microelectrodes display good electrochemical performances for electrochemical sensors. Thus, this novel 5-in. wafer-level microfabrication method is a simple and cost-effective protocol to prepare polymer substrate and demonstrates good potential for application to highly integrated and miniaturized biomedical devices. PMID:16097789

Lee, Dae-Sik; Yang, Haesik; Chung, Kwang-Hyo; Pyo, Hyeon-Bong

2005-08-15

52

Surface microstructuring of biocompatible bone analogue material HAPEX using LIGA technique and embossing  

NASA Astrophysics Data System (ADS)

HAPEX is an artificial bone analogue composite based on hydroxyapatite and polyethylene, which can be applied for growth of bone cells. Due to its biocompatibility and favourable mechanical properties, HAPEX is used for orthopaedic implants like tympanic (middle ear) bones. The morphology of HAPEX surfaces is of high interest and it is believed that surface structuring on a micron scale might improve the growth conditions for bone cells. A new and simple approach for the microstructuring of HAPEX surfaces has been investigated using LIGA technique. LIGA is a combination of several processes, in particular lithography, electroplating and forming/moulding. For HAPEX surface structuring, arrays of dots, grids and lines with typical lateral dimension ranging from 5 ?m to 50 ?m were created on a chromium photomask and the patterns were transferred into thick SU-8 photoresist (structure height > 10 ?m) by UV lithography. Subsequently, the SU-8 structures served as moulds for electroplating nickel on Si wafers and nickel substrates. The final nickel microstructures were used as embossing master for the HAPEX material. Embossing was carried out using a conventional press (> 500 hPa) with the facility to heat the master and the HAPEX. The temperature ranged from ambient to a few degrees above glass transition temperature (Tg) of HAPEX. The paper will include details of the fabrication process and process tolerances in lateral and vertical directions. Data obtained are correlated to the temperature used during embossing.

Schneider, Andreas; Rea, Susan; Huq, Ejaz; Bonfield, William

2003-04-01

53

Development of Three Dimensional LIGA Process to Fabricate Spiral Microcoil  

NASA Astrophysics Data System (ADS)

The LIGA process has been developed as a 2.5-dimensional processing method on Si wafers to date. However, we have succeeded in extending the LIGA process to 3D for the first time. 3D-LIGA was achieved by the technical development of 3D X-ray lithography and worm injection molding replication technology with unscrewing. These technologies began from the development of equipment and have developed into quite original technologies. By combining this 3D-LIGA process with a metallization technique that consists of flat and smooth electroplating and isotropic chemical etching, a spiral copper microstructure with a linewidth of 10 ?m, a pitch of 20 ?m and a thickness of 2 ?m was formed on a cylindrical surface made from LCP with a length of 1 mm and a diameter of 0.48 mm. Furthermore, we applied the process to fabricate a spiral microcoil and estimated the electrical properties of the microcoil. The numbers of turns were 15, the inductance was 91 nH and the quality factor was 5.8 for a frequency of 1 GHz. Direct-current resistance was measured as 99 ?.

Mekaru, Harutaka; Kusumi, Shinji; Sato, Noriaki; Shimizu, Masami; Yamashita, Michiru; Shimada, Osamu; Hattori, Tadashi

2005-07-01

54

A Wafer scale active pixel CMOS image sensor for generic x-ray radiology  

NASA Astrophysics Data System (ADS)

This paper describes a CMOS Active Pixel Image Sensor developed for generic X-ray imaging systems using standard CMOS technology and an active pixel architecture featuring low noise and a high sensitivity. The image sensor has been manufactured in a standard 0.35 ?m technology using 8" wafers. The resolution of the sensor is 3360x3348 pixels of 40x40 ?m2 each. The diagonal of the sensor measures little over 190 mm. The paper discusses the floor planning, stitching diagram, and the electro-optical performance of the sensor that has been developed.

Scheffer, Danny

2007-03-01

55

Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics  

NASA Astrophysics Data System (ADS)

Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

2014-02-01

56

Wafer scale fabrication of porous three-dimensional plasmonic metamaterials for the visible region: chiral and beyond  

NASA Astrophysics Data System (ADS)

We report on a wafer scale fabrication method of a three-dimensional plasmonic metamaterial with strong chiroptical response in the visible region of the electromagnetic spectrum. The system was comprised of metallic nanoparticles arranged in a helical fashion, with high degree of flexibility over the choice of the underlying material, as well as their geometrical parameters. This resulted in exquisite control over the chiroptical properties, most importantly the spectral signature of the circular dichroism. In spite of the large variability in the arrangement, as well as the size and shape of the constituent nanoparticles, the average chiro-optical response of the material remained uniform across the wafer, thus confirming the suitability of this system as a large area chiral metamaterial. By simply heating the substrate for a few minutes, the geometrical properties of the nanoparticles could be altered, thus providing an additional handle towards tailoring the spectral response of this novel material.We report on a wafer scale fabrication method of a three-dimensional plasmonic metamaterial with strong chiroptical response in the visible region of the electromagnetic spectrum. The system was comprised of metallic nanoparticles arranged in a helical fashion, with high degree of flexibility over the choice of the underlying material, as well as their geometrical parameters. This resulted in exquisite control over the chiroptical properties, most importantly the spectral signature of the circular dichroism. In spite of the large variability in the arrangement, as well as the size and shape of the constituent nanoparticles, the average chiro-optical response of the material remained uniform across the wafer, thus confirming the suitability of this system as a large area chiral metamaterial. By simply heating the substrate for a few minutes, the geometrical properties of the nanoparticles could be altered, thus providing an additional handle towards tailoring the spectral response of this novel material. Electronic supplementary information (ESI) available: Experimental procedure (fabrication and characterization); effect of linear dichroism; chiroptical response for isotropic collection of helices; details of the computational model; thickness dependent red shift. See DOI: 10.1039/c3nr02666c

Singh, Johnson Haobijam; Nair, Greshma; Ghosh, Arijit; Ghosh, Ambarish

2013-07-01

57

Stationary Optical Concentrator Designs and Wafer Scale Monolithic Integration of Semiconductor Devices for Next Generation Photovoltaic Panels  

NASA Astrophysics Data System (ADS)

A major barrier in utilizing solar energy for large scale deployment is the cost of the photovoltaic (PV) systems. Several approaches have been used for the cost reduction such as by modifying PV system designs in addition to enhancing the efficiency of solar cells. Due to the high cost of materials, minimizing the use of solar cells such as in concentrator type systems is highly attractive for reducing the cost of the PV modules by focusing the incident light onto the PV cell. However concentrator PV systems (CPV) require constant tracking of the sun and hence are complex in design and expensive to operate, except in limited situations such as large scale PV power plants. It is desirable to design new concentrator type systems that do not require continuous tracking of the sun. These systems could ultimately reduce the PV system cost to a minimum while maximizing the power conversion efficiency. In this thesis we propose a simple design for a stationary concentrator photovoltaic (SCPV) system that could significantly reduce the cost of generating electricity using PV devices. Using optical ray tracing simulations, we have been able to design SCPV systems that could reduce the PV module cost by 2--10 times without compromising on the power conversion efficiency of the system. Another alternative approach for sustainable high efficiency PV system design is to develop low cost PV cells for terrestrial applications. To meet the demands of low cost and large scale production, larger and thinner (or flexible) substrates are required. We demonstrated the feasibility of fabricating monolithic interconnected PV devices at the wafer scale (2 inch wafers). In this study, GaSb PV cells grown on semi-insulating GaAs were used as the model material. Crucial device fabrication steps such as a selective etching process have been developed that is necessary for isolating individual devices on the wafer and interconnecting them with sub-micron scale accuracy. Selective etching of GaSb and GaAs has been developed for isolation of GaSb devices on semi-insulating GaAs substrates. Smooth side wall morphology and desirable depth profile of the etched structures have been accomplished using optimized etching conditions presented in this thesis. Device fabrication of series interconnected GaSb PV cells on a GaAs substrate with single-sided metal contacts has been successfully demonstrated.

Kim, Jung Min

58

Erasable diffractive grating couplers in silicon on insulator for wafer scale testing  

NASA Astrophysics Data System (ADS)

Test points are essential in allowing optical circuits on a wafer to be autonomously tested after selected manufacturing steps, hence allowing poor performance or device failures to be detected early and to be either repaired using direct write methods, or a cessation of further processing to reduce fabrication costs. Grating couplers are a commonly used method for efficiently coupling light from an optical fibre to a silicon waveguide. They are relatively easy to fabricate and they allow light to be coupled into/out from any location on the device without the need for polishing, making them good candidates for an optical test point. A fixed test point can be added for this purpose, although traditionally these grating devices are fabricated by etching the silicon waveguide, and hence this permanently adds loss and leads to a poor performing device when placed into use after testing. We demonstrate a similar device utilising a refractive index change induced by lattice disorder. Raman data collected suggests this lattice damage is reversible, allowing a laser to subsequently erase the grating coupler.

Topley, R.; Martinez-Jimenez, G.; O'Faolain, L.; Healy, N.; Mailis, S.; Thomson, D. J.; Gardes, F. Y.; Peacock, A. C.; Payne, D. N. R.; Mashanovich, G. Z.; Reed, G. T.

2014-03-01

59

Wafer-scale processing technology for monolithically integrated GaSb thermophotovoltaic device array on semi-insulating GaAs substrate  

NASA Astrophysics Data System (ADS)

This paper presents the entire fabrication and processing steps necessary for wafer scale monolithic integration of series interconnected GaSb devices grown on semi-insulating GaAs substrates. A device array has been fabricated on complete 50 mm (2 inch) diameter wafer using standard photolithography, wet chemical selective etching, dielectric deposition and single-sided metallization. For proof of concept of the wafer-scale feasibility of this process, six large-area series interconnected GaSb p-n junction thermophotovoltaic cells with each cell consisting of 24 small-area devices have been fabricated and characterized for its electrical connectivity. The fabrication process presented in this paper can be used for optoelectronic and electronic device technologies based on GaSb and related antimonide based compound semiconductors.

Kim, Jung Min; Dutta, Partha S.; Brown, Eric; Borrego, Jose M.; Greiff, Paul

2013-06-01

60

Automated wafer-scale fabrication of electron beam deposited tips for atomic force microscopes using pattern recognition  

Microsoft Academic Search

We present an automation technique for the growth of electron beam deposited tips on whole wafers of atomic force microscope cantilevers. This technique uses pattern recognition on scanning electron microscope images of successive magnifications to precisely place the tips on the cantilevers. We demonstrate the capabilities of the working system on a four-inch wafer of microfabricated small cantilevers with a

Johannes H Kindt; Georg E Fantner; James B Thompson; Paul K Hansma

2004-01-01

61

Epitaxial (100) iridium on A-plane sapphire: A system for wafer-scale diamond heteroepitaxy  

Microsoft Academic Search

Large-scale heteroepitaxial growth of diamond depends critically on the development of a suitable lattice-matched buffer layer and substrate system. Epitaxial (100) iridium films have been grown on terraced, vicinal a-plane (1120) alpha-Al2O3 (sapphire) by electron-beam evaporation. The epitaxial relationship, Ir(100)\\/\\/Al2O3(1120) with Ir[011]\\/\\/Al2O3[1100], was determined by x-ray diffraction and electron backscattering diffraction analysis. For a 300-nm thickness of Ir, a (200)

Z. Dai; C. Bednarski-Meinke; R. Loloee; B. Golding

2003-01-01

62

Integration of hexagonal boron nitride with quasi-freestanding epitaxial graphene: toward wafer-scale, high-performance devices.  

PubMed

Hexagonal boron nitride (h-BN) is a promising dielectric material for graphene-based electronic devices. Here we investigate the potential of h-BN gate dielectrics, grown by chemical vapor deposition (CVD), for integration with quasi-freestanding epitaxial graphene (QFEG). We discuss the large scale growth of h-BN on copper foil via a catalytic thermal CVD process and the subsequent transfer of h-BN to a 75 mm QFEG wafer. X-ray photoelectron spectroscopy (XPS) measurements confirm the absence of h-BN/graphitic domains and indicate that the film is chemically stable throughout the transfer process, while Raman spectroscopy indicates a 42% relaxation of compressive stress following removal of the copper substrate and subsequent transfer of h-BN to QFEG. Despite stress-induced wrinkling observed in the films, Hall effect measurements show little degradation (<10%) in carrier mobility for h-BN coated QFEG. Temperature dependent Hall measurements indicate little contribution from remote surface optical phonon scattering and suggest that, compared to HfO(2) based dielectrics, h-BN can be an excellent material for preserving electrical transport properties. Graphene transistors utilizing h-BN gates exhibit peak intrinsic cutoff frequencies >30 GHz (2.4× that of HfO(2)-based devices). PMID:22545808

Bresnehan, Michael S; Hollander, Matthew J; Wetherington, Maxwell; LaBella, Michael; Trumbull, Kathleen A; Cavalero, Randal; Snyder, David W; Robinson, Joshua A

2012-06-26

63

Modeling electrodeposition for LIGA microdevice fabrication  

SciTech Connect

To better understand and to help optimize the electroforming portion of the LIGA process, we have developed one and two-dimensional numerical models describing electrode-position of metal into high aspect-ratio molds. The one-dimensional model addresses dissociation, diffusion, electromigration, and deposition of multiple ion species. The two-dimensional model is limited to a single species, but includes transport induced by forced flow of electrolyte outside the mold and by buoyancy associated with metal ion depletion within the mold. To guide model development and to validate these models, we have also conducted a series of laboratory experiments using a sulfamate bath to deposit nickel in cylindrical molds having aspect ratios up to twenty-five. The experimental results indicate that current densities well in excess of the diffusion-limited currents may still yield metal deposits of acceptable morphology. However, the numerical models demonstrate that such large ion fluxes cannot be sustained by convection within the mold resulting from flow across the mold top. Instead, calculations suggest that the observed enhancement of transport probably results from natural convection within the molds, and that buoyancy-driven flows may be critical to metal ion transport even in micron-scale features having very large aspect ratios. Taking advantage of this enhanced ion transport may allow order-of-magnitude reductions in electroforming times for LIGA microdevice fabrication. 42 refs., 14 figs., 1 tab.

Griffiths, S.K.; Nilson, R.H.; Bradshaw, R.W. [and others

1998-02-01

64

Mechanisms of fatigue in LIGA Ni MEMS thin films  

Microsoft Academic Search

This paper presents the results of an experimental study of the mechanisms of fatigue in LIGA Ni micro-electro-mechanical systems (MEMS) thin films with micro-scale columnar and nano-scale equiaxed grains. Stress-life behavior is reported for films with thicknesses of 70 and 270?m. The stress-life data are compared with previously reported data for Ni MEMS films and bulk Ni. The films with

Y. Yang; B. I. Imasogie; S. M. Allameh; B. Boyce; K. Lian; J. Lou; W. O. Soboyejo

2007-01-01

65

Design and fabrication of a LIGA milliengine  

SciTech Connect

This paper reports on the design and fabrication of a new milliscale magnetic actuator that is ideally suited for LIGA processing. LIGA processing permits the fabrication of millisized machine elements that cannot be fabricated by conventional miniature machining techniques because of their small feature sizes. The Milliengine is a magnetically driven device that utilizes a unique design to extend the 2-dimensional fabrication capability of LIGA to create 3-dimensional machinery.

Garcia, E.J.; Christenson, T.R.; Polosky, M.A.; Jojola, A.A.

1997-04-01

66

Hydride Vapor Phase Epitaxy of GaN on NdGaO3 Substrate and Realization of Freestanding GaN Wafers with 2-inch Scale  

NASA Astrophysics Data System (ADS)

GaN thick film is grown on NdGaO3 substrate using hydride vapor phase epitaxy. To avoid decomposition of NdGaO3 substrate by NH3, a low-temperature grown GaN protective layer is adopted. Using NdGaO3 substrate and a low-temperature GaN protective layer simultaneously, 2-inch-scale GaN wafers are realized. The photoluminescence (PL) spectrum indicates strong band-edge emission without deep-level related emission. Both plan-view transmission electron microscope and cathode luminescence images suggest that the dislocation density of freestanding GaN wafers is expected to be as low as 106 cm-2.

Wakahara, Akihiro; Yamamoto, Takenori; Ishio, Kouji; Yoshida, Akira; Seki, Youji; Kainosho, Keiji; Oda, Osamu

2000-04-01

67

Industrial applications for LIGA-fabricated micro heat exchangers  

Microsoft Academic Search

One of the well-known benefits of micro scale is enhanced heat transfer. This fact provides the motivation for fabricating a variety of micro heat exchangers using derivatives of the LIGA micromachining process. These heat exchangers can be made of polymers, nickel (electroplated or electroless), or ceramics (Si3N4 and alumina are presently being investigated). These heat exchangers are envisioned for applications

Kevin W. Kelly; Chad Harris; Lyndon S. Stephens; Christophe Marques; Dan Foley

2001-01-01

68

Hydride Vapor Phase Epitaxy of GaN on NdGaO3 Substrate and Realization of Freestanding GaN Wafers with 2-inch Scale  

Microsoft Academic Search

GaN thick film is grown on NdGaO3 substrate using hydride vapor phase epitaxy. To avoid decomposition of NdGaO3 substrate by NH3, a low-temperature grown GaN protective layer is adopted. Using NdGaO3 substrate and a low-temperature GaN protective layer simultaneously, 2-inch-scale GaN wafers are realized. The photoluminescence (PL) spectrum indicates strong band-edge emission without deep-level related emission. Both plan-view transmission electron

Akihiro Wakahara; Takenori Yamamoto; Kouji Ishio; Akira Yoshida; Youji Seki; Keiji Kainosho; Osamu Oda

2000-01-01

69

Laser wafering for silicon solar.  

SciTech Connect

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

70

Nano-scale origins of recombination activity and optical properties of extended defects in mc-Si wafers and PV cells  

NASA Astrophysics Data System (ADS)

Multicrystalline silicon (mc-Si) is the most used absorber in photovoltaic (PV) cells at present. If efficiencies are to improve in this established technology a better understanding of how minority carrier lifetimes are reduced is necessary. The capture of minority carriers by states associated with extended defects is known to play a major role in reducing minority carrier lifetimes. Energy levels introduced into the silicon bandgap often have electrical activity or optical signatures that can provide clues as to the structural or chemical origin of a particular level. This work utilizes electron beam induced current (EBIC), cathodoluminescence (CL) imaging and spectroscopy, photoluminescence (PL) imaging, and nano-scale chemical analysis to provide new insight into the origin of the electrical and optical properties of extended defects in mc-Si wafers and PV cells. A new interpretation of the temperature dependence of EBIC contrast is formulated based on observations of an anomalous form of the contrast vs. temperature curves as well as evidence of high impurity content. In addition an attempt is made to determine the origin of specific types of defect related emission as well as how this emission is influenced by processing steps applied to mc-Si wafers. Nano-scale chemical analysis is used to reveal the origin of the observed luminescence.

Guthrey, Harvey L., IV

71

Wafer-scale double-layer stacked au/al2 o3 @au nanosphere structure with tunable nanospacing for surface-enhanced Raman scattering.  

PubMed

Fabricating perfect plasmonic nanostructures has been a major challenge in surface enhanced Raman scattering (SERS) research. Here, a double-layer stacked Au/Al2 O3 @Au nanosphere structures is designed on the silicon wafer to bring high density, high intensity "hot spots" effect. A simply reproducible high-throughput approach is shown to fabricate feasibly this plasmonic nanostructures by rapid thermal annealing (RTA) and atomic layer deposition process (ALD). The double-layer stacked Au nanospheres construct a three-dimensional plasmonic nanostructure with tunable nanospacing and high-density nanojunctions between adjacent Au nanospheres by ultrathin Al2 O3 isolation layer, producing highly strong plasmonic coupling so that the electromagnetic near-field is greatly enhanced to obtain a highly uniform increase of SERS with an enhancement factor (EF) of over 10(7) . Both heterogeneous nanosphere group (Au/Al2 O3 @Ag) and pyramid-shaped arrays structure substrate can help to increase the SERS signals further, with a EF of nearly 10(9) . These wafer-scale, high density homo/hetero-metal-nanosphere arrays with tunable nanojunction between adjacent shell-isolated nanospheres have significant implications for ultrasensitive Raman detection, molecular electronics, and nanophotonics. PMID:24995658

Hu, Zhaosheng; Liu, Zhe; Li, Lin; Quan, Baogang; Li, Yunlong; Li, Junjie; Gu, Changzhi

2014-10-01

72

Si nanowire directly grown on a liquid metal substrate--towards wafer scale transferable nanowire arrays with improved visible-light sterilization.  

PubMed

Integrating vertically aligned nanowires (NWs) on a functional substrate is important for the application of NWs in wafer scale assemblies and functional devices. However, vertically aligned NWs via the current epitaxial growth route can only be prepared on crystalline wafers. A convenient method is thus presented to overcome NW substrate limitations. Liquid metal is proposed to serve as a substrate for the initial growth of vertically aligned NWs. NWs could then be harvested from the growth substrate and integrated with functional substrates. Fabricated vertically aligned silicon NWs (SiNWs) were grown on molten Sn and then integrated into a flexible transparent poly(dimethylsiloxane) film to obtain a SiNW/functional substrate device. The device showed enhanced visible-light absorption ability and refreshable visible-light bactericidal activities with a bacterial reduction rate of close to 100%, indicating that growth with molten metal as a substrate could be a promising approach for extending the function and application of NWs. PMID:24622242

Wang, Hui; Wang, Jian-Tao; Ou, Xue-Mei; Lee, Chun-Sing; Zhang, Xiao-Hong

2014-04-11

73

Laparoscopic Splenectomy Using LigaSure  

PubMed Central

Background: Laparoscopic splenectomy (LS) has become the standard approach for most splenectomy cases. Bleeding is the main complication and cause for conversion. We present our experience with the LigaSure and discuss its advantage as a vessel sealing system in achieving safe vascular control. Method: Over a 3-year period, we performed 12 consecutive LS using LigaSure at a single center. A literature review of all the patients who had undergone laparoscopic splenectomy with of the LigaSure to achieve vascular control at the hilum was carried out, assessing its advantages and outcome. Results: Twelve LS were performed. Eleven of these patients had ITP, and one patient had sickle cell disease. The mean blood loss was 70mL (range, 50 to 460), and operating time was 126 minutes (range, 110 to 240). Two postoperative complications occurred: portal vein thrombosis in one case and subphrenic collection in the other. The literature review revealed 8 studies with 231 cases in which the LigaSure was used to perform laparoscopic splenectomy. A significant reduction in operating time (average 102 minutes) and intraabdominal blood loss (66mL) was observed with the LigaSure compared with endostaplers. Conclusion: The use of LigaSure and the semilateral position results in a gain of time and safety in addition to low intraoperative bleeding, need for transfusion, minimal complications and a low conversion rate. PMID:21605520

Kindy, Nayil Al; Chopra, Pradeep J.

2010-01-01

74

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology  

NASA Astrophysics Data System (ADS)

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 ?m SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

75

Wafer-scale broadband antireflective silicon fabricated by metal-assisted chemical etching using spin-coating Ag ink.  

PubMed

We report broadband antireflective disordered subwavelength structures (d-SWSs), which were fabricated on 4-inch silicon wafers by spin-coating Ag ink and metal-assisted chemical etching. The antireflection properties of the d-SWSs depend on its dimensions and heights, which were changed by the sintering temperature of the spin-coated Ag ink and etching time. The fabricated d-SWSs drastically reduced surface reflection over a wide range of wavelengths and incident angles, providing good surface uniformity. The d-SWSs with the most appropriate geometry for practical solar cell applications exhibit only 1.23% solar-weighted reflectance in the wavelength range of 300-1100 nm and average reflectance <5% up to an incident angle of 55° in the wavelength range of 300-2500 nm. This simple and low-cost nanofabrication method for antireflection could be of great importance in optical device applications because it allows mass production without any lithography processes or sophisticated equipment. PMID:21935253

Yeo, Chan Il; Song, Young Min; Jang, Sung Jun; Lee, Yong Tak

2011-09-12

76

Microfabrication: LIGA-X and applications  

NASA Astrophysics Data System (ADS)

X-ray LIGA (Lithography, Electrogrowth, Moulding) is one of today's key technologies in microfabrication and upcoming modern (meso)-(nano) fabrication, already used and anticipated for micromechanics (micromotors, microsensors, spinnerets, etc.), micro-optics, micro-hydrodynamics (fluidic devices), microbiology, in medicine, in biology, and in chemistry for microchemical reactors. It compares to micro-electromechanical systems (MEMS) technology, offering a larger, non-silicon choice of materials and better inherent precision. X-ray LIGA relies on synchrotron radiation to obtain necessary X-ray fluxes and uses X-ray proximity printing. Inherent advantages are its extreme precision, depth of field and very low intrinsic surface roughness. However, the quality of fabricated structures often depends on secondary effects during exposure and effects like resist adhesion. UV-LIGA, relying on thick UV resists is an alternative for projects requiring less precision. Modulating the spectral properties of synchrotron radiation, different regimes of X-ray lithography lead to (a) the mass-fabrication of classical nanostructures, (b) the fabrication of high aspect ratio nanostructures (HARNST), (c) the fabrication of high aspect ratio microstructures (HARMST), and (d) the fabrication of high aspect ratio centimeter structures (HARCST). Reviewing very recent activities around X-ray LIGA, we show the versatility of the method, obviously finding its region of application there, where it is best and other competing microtechnologies are less advantageous. An example of surface-based X-ray and particle lenses (orthogonal reflection optics (ORO)) made by X-ray LIGA is given.

Kupka, R. K.; Bouamrane, F.; Cremers, C.; Megtert, S.

2000-09-01

77

Scheduling semiconductor wafer fabrication  

Microsoft Academic Search

The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer

LAWRENCE M. WEIN

1988-01-01

78

Role of wafer geometry in wafer chucking  

NASA Astrophysics Data System (ADS)

Wafer chucks are used in advanced lithography systems to hold and flatten wafers during exposure. To minimize defocus and overlay errors, it is important that the chuck provide sufficient pressure to completely chuck the wafer and remove flatness variations across a broad range of spatial wavelengths. Analytical and finite element models of the clamping process are presented here to understand the range of wafer geometry features that can be fully chucked with different clamping pressures. The analytical model provides a simple relationship to determine the maximum feature amplitude that can be chucked as a function of spatial wavelength and chucking pressure. Three-dimensional finite element simulations are used to examine the chucking of wafers with various geometries, including cases with simulated and measured shapes. The analytical and finite element results both demonstrate that geometry variations with short spatial wavelengths (e.g., high-frequency wafer shape features) present the greatest challenge to achieving complete chucking. The models and results presented here can be used to provide guidance on wafer geometry and chuck designs for advanced exposure tools.

Turner, Kevin T.; Ramkhalawon, Roshita; Sinha, Jaydeep K.

2013-04-01

79

Toward wafer-scale fabrication and 3D integration of micro-solid oxide fuel cells for portable energy  

Microsoft Academic Search

Pathways to scaling up the power and voltage output of on-chip micro-solid oxide fuel cells (muSOFC) have been investigated. muSOFC arrays consisting of one thousand three hundred and thirty-two (1332) membranes have been lithographically fabricated on 4\\

Bo-Kuai Lai; Alex C. Johnson; Masaru Tsuchiya; Shriram Ramanathan

2010-01-01

80

Automated wafer transport in the wafer Fab  

Microsoft Academic Search

Through simulations with models, HP's Inkjet Supplies Business Unit has determined that intrabay material transport with automated delivery of wafers directly to process tools substantially increases the throughput of our semiconductor manufacturing facility (Fab). To fully utilize limited Fab space, an architecture using overhead track and vehicles has been selected. HP cooperated with a Supplier of automated material handling systems

U. Kaempf

1997-01-01

81

Mechanical properties of wear tested LIGA nickel.  

SciTech Connect

Strength, friction, and wear are dominant factors in the performance and reliability of materials and devices fabricated using nickel based LIGA and silicon based MEMS technologies. However, the effects of frictional contacts and wear on long-term performance of microdevices are not well-defined. To address these effects on performance of LIGA nickel, we have begun a program employing nanoscratch and nanoindentation. Nanoscratch techniques were used to generate wear patterns using loads of 100, 200, 500, and 990 {micro}N with each load applied for 1, 2, 5, and 10 passes. Nanoindentation was then used to measure properties in each wear pattern correcting for surface roughness. The results showed a systematic increase in hardness with applied load and number of nanoscratch passes. The results also showed that the work hardening coefficient determined from indentation tests within the wear patterns follows the results established from tensile tests, supporting use of a nanomechanics-based approach for studying wear.

Jungk, John Michael (University of Minnesota, Minneapolis, MN); Prasad, Somuri V. (Sandia National Laboratories, Albuquerque, NM); Gerberich, William W. (University of Minnesota, Minneapolis, MN); Moody, Neville Reid; Kennedy, Marian S. (Washington State University, Pullman, WA); Bahr, David F. (Washington State University, Pullman, WA)

2005-03-01

82

Wafer scale micromachine assembly method  

DOEpatents

A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.

Christenson, Todd R. (Albuquerque, NM)

2001-01-01

83

Industrial applications for LIGA-fabricated micro heat exchangers  

NASA Astrophysics Data System (ADS)

One of the well-known benefits of micro scale is enhanced heat transfer. This fact provides the motivation for fabricating a variety of micro heat exchangers using derivatives of the LIGA micromachining process. These heat exchangers can be made of polymers, nickel (electroplated or electroless), or ceramics (Si3N4 and alumina are presently being investigated). These heat exchangers are envisioned for applications such as gas turbine blades, mechanical seals and/or bearings, boilers, condensers, radiators, evaporators, electronic component cooling, and catalytic converters. In this paper, methods to fabricate an array of heat exchangers for different applications are described. In addition, simple analytic models that illustrate the motivation for fabricating micro cross flow heat exchanges are shown to compare favorably with experimental heat transfer results.

Kelly, Kevin W.; Harris, Chad; Stephens, Lyndon S.; Marques, Christophe; Foley, Dan

2001-10-01

84

Wafer characteristics via reflectometry  

DOEpatents

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Sopori, Bhushan L. (Denver, CO)

2010-10-19

85

Scriber for silicon wafers  

NASA Technical Reports Server (NTRS)

A device for dividing silicon wafers into rectangular chips is characterized by a base including a horizontally oriented bed with a planar support surface, a vacuum chuck adapted to capture a silicon wafer seated on the support for translation in mutually perpendicular directions. A stylus support mounted on the bed includes a shaft disposed above and extended across the bed and a truck mounted on the shaft and supported thereby for linear translation along a path extended across the bed a vertically oriented scribe has a diamond tip supported by the truck also adapted as to engage a silicon wafer captured by the chuck and positioned beneath it in order to form score lines in the surface of the wafer as linear translation is imparted to the truck. A chuck positioning means is mounted on the base and is connected to the chuck for positioning the chuck relative to the stylus.

Yamakawa, K. A.; Fortier, E. P. (inventors)

1981-01-01

86

GEM-type detectors using LIGA and etchable glass technologies  

Microsoft Academic Search

Gas electron multipliers (GEMS) have been made by a deep X-ray lithography technique (LIGA process) using synchrotron radiation on polymethylmethacrylate (PMMA) and by UV processes using a UV etchable glass. Gain, stability and rate capability for these detectors are described. The LIGA detectors described consist of PMMA sheets of various thicknesses, 125 ?m to 350 ?m, and have 150 ?m×150

S. K. Ahn; J. G. Kim; V. Perez-Mendez; S. Chang; K. H. Jackson; J. A. Kadyk; W. A. Wenzel; G. Cho

2001-01-01

87

Stable wafer-carrier system  

DOEpatents

One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

2013-10-22

88

Fabrication of LIGA mold insert using Ni-PTFE composite micro-electroforming  

Microsoft Academic Search

The LIGA process, which combines deep X-ray lithography with electroforming and polymer molding, is a main fabrication method for producing MEMS. And hot embossing is one of the main processing techniques for polymer microfabrication, which helps the LIGA (UV-LIGA) technology to achieve low cost mass production. And electroforming of LIGA mold insert with lower surface energy and friction coefficient is

Yuhua Guo; Gang Liu; Ying Xiong; Xuelin Zhu; Wang Jun; Yangchao Tian

2006-01-01

89

Wafer-scale Epitaxial Graphene Growth on the Si-face of Hexagonal SiC (0001) for High Frequency Transistors  

Microsoft Academic Search

Up to two layers of epitaxial graphene have been grown on the Si-face of two-inch SiC wafers exhibiting room-temperature Hall mobilities up to 1800 cm^2\\/Vs, measured from ungated, large, 160 micron x 200 micron Hall bars, and up to 4000 cm^2\\/Vs, from top-gated, small, 1 micron x 1.5 micron Hall bars. The growth process involved a combination of a cleaning

Christos Dimitrakopoulos; Yu-Ming Lin; Alfred Grill; Damon B. Farmer; Marcus Freitag; Yanning Sun; Shu-Jen Han; Zhihong Chen; Keith A. Jenkins; Yu Zhu; Zihong Liu; Timothy J. McArdle; John A. Ott; Robert Wisnieff; Phaedon Avouris

2010-01-01

90

Plasmonic coupling: wafer-scale double-layer stacked au/al2 o3 @au nanosphere structure with tunable nanospacing for surface-enhanced Raman scattering (small 19/2014).  

PubMed

A reproducible high-throughput approach is reported by J. J. Li, C. Z. Gu, and co-workers on page 3933 to fabricate wafer-scale double-layer stacked Au/Al2 O3 @Au(Ag) nanosphere structures with tunable nanospacing for surface-enhanced Raman scattering. This nanostructure constitutes a 3D plasmonic nanostructure with tunable nanospacing and high-density nanojunctions between adjacent Au nanospheres of ultrathin Al2 O3 isolation layers, producing highly strong plasmonic coupling so that the electromagnetic near-field is greatly enhanced to obtain a uniform increase of SERS with an enhancement factor of over 108. PMID:25292395

Hu, Zhaosheng; Liu, Zhe; Li, Lin; Quan, Baogang; Li, Yunlong; Li, Junjie; Gu, Changzhi

2014-10-01

91

1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics  

SciTech Connect

The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

Lorenz, Adam [1366 Technologies] [1366 Technologies

2013-08-30

92

Micro-grippers for assembly of LIGA parts  

SciTech Connect

This paper describes ongoing testing of two microgrippers for assembly of LIGA (Lithographie Galvanoformung Abformung) parts. The goal is to place 100 micron outside diameter (OD) LIGA gears with a 50 micron inner diameter hole onto pins ranging from 35 to 49 microns. The first micro gripper is a vacuum gripper made of a 100 micron OD stainless steel tube. The second micro gripper is a set of tweezers fabricated using the LIGA process. Nickel, Permalloy, and copper materials are tested. The tweezers are actuated by a collet mechanism which is closed by a DC linear motor.

Feddema, J.; Polosky, M.; Christenson, T.; Spletzer, B.; Simon, R.

1997-12-31

93

Etching Of Semiconductor Wafer Edges  

DOEpatents

A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

2003-12-09

94

Miniature Scroll Pumps Fabricated by LIGA  

NASA Technical Reports Server (NTRS)

Miniature scroll pumps have been proposed as roughing pumps (low - vacuum pumps) for miniature scientific instruments (e.g., portable mass spectrometers and gas analyzers) that depend on vacuum. The larger scroll pumps used as roughing pumps in some older vacuum systems are fabricated by conventional machining. Typically, such an older scroll pump includes (1) an electric motor with an eccentric shaft to generate orbital motion of a scroll and (2) conventional bearings to restrict the orbital motion to a circle. The proposed miniature scroll pumps would differ from the prior, larger ones in both design and fabrication. A miniature scroll pump would include two scrolls: one mounted on a stationary baseplate and one on a flexure stage (see figure). An electromagnetic actuator in the form of two pairs of voice coils in a push-pull configuration would make the flexure stage move in the desired circular orbit. The capacitance between the scrolls would be monitored to provide position (gap) feedback to a control system that would adjust the drive signals applied to the voice coils to maintain the circular orbit as needed for precise sealing of the scrolls. To minimize power consumption and maximize precision of control, the flexure stage would be driven at the frequency of its mechanical resonance. The miniaturization of these pumps would entail both operational and manufacturing tolerances of <1 m. Such tight tolerances cannot be achieved easily by conventional machining of high-aspect-ratio structures like those of scroll-pump components. In addition, the vibrations of conventional motors and ball bearings exceed these tight tolerances by an order of magnitude. Therefore, the proposed pumps would be fabricated by the microfabrication method known by the German acronym LIGA ( lithographie, galvanoformung, abformung, which means lithography, electroforming, molding) because LIGA has been shown to be capable of providing the required tolerances at large aspect ratios.

Wiberg, Dean; Shcheglov, Kirill; White, Victor; Bae, Sam

2009-01-01

95

The use of LigaSure in patients with hyperthyroidism  

Microsoft Academic Search

Background  Thyroidectomies of hyperthyroidic patients are known to be more blood-spattered than the operations performed for euthyroid nodular diseases and require careful hemostasis. Our purpose was to evaluate the efficacy of the use of LigaSure in patients with hyperthyroidism.Materials and methods  Between January 2004 and October 2005, 100 patients underwent total or near-total thyroidectomy. Bipolar vessel ligation system (LigaSure) was the choice

Umut Barbaros; Ye?im Erbil; Alp Bozbora; U?ur Deveci; Nihat Aksakal; Ahmet Dinçça?; Selçuk Özarma?an

2006-01-01

96

Fabrication of LIGA-Acceleration Sensors by Aligned Molding  

Microsoft Academic Search

A technology for the fabrication of movable LIGA-Microstructures by molding was developed, which enables the cheaper production\\u000a of e.g. LIGA-Acceleration Sensors [1]. For this purpose an aligned molding process had to be developed. The realized experimental\\u000a setup consists of two subsystems, the molding machine and the alignment arrangement [2]. After aligning a substrate it is\\u000a transported into the molding machine.

A. Both; W. Bacher; M. Heckele; K. D. Müller; R. Ruprecht; M. Strohrmann

1996-01-01

97

Fabrication of LIGA-acceleration sensors by aligned molding  

Microsoft Academic Search

A technology for the fabrication of movable LIGA-Microstructures by molding was developed, which enables the cheaper production\\u000a of e.g. LIGA-Acceleration Sensors [1]. For this purpose an aligned molding process had to be developed. The realized experimental\\u000a setup consists of two subsystems, the molding machine and the alignment arrangement [2]. After aligning a substrate it is\\u000a transported into the molding machine.

A. Both; W. Bacher; M. Heckele; K.-D. Müller; R. Ruprecht; M. Strohrmann

1995-01-01

98

High-precision readout circuit for LIGA acceleration sensors  

Microsoft Academic Search

For the past few years capacitive LIGA acceleration sensors have been fabricated at the Karlsruhe Nuclear Research Center. The advantages of LIGA acceleration sensors are their high zero-acceleration capacitance of 5 pF, temperature-compensated design with low offset temperature coefficient (TCO = 1.5 × 10?4 FSO K?1) and high linearity. In addition, a high-precision readout circuit has been developed. The electronic

O. Krömer; O. Fromhein; H. Gemmeke; T. Kühner; J. Mohr; M. Strohrmann

1995-01-01

99

Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter  

NASA Technical Reports Server (NTRS)

The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

Chen, C. P.; Leipold, M. H.

1984-01-01

100

Bondability of processed glass wafers  

NASA Astrophysics Data System (ADS)

The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness will result in small real area of contact, and therefore yield voids in the bonding interface. Usually, the root mean square roughness (RMS) or the mean roughness (Ra) are used as parameters to evaluate the wafer bondability. It was found from experience that for a bondable wafer surface the mean roughness must be in the subnanometer range, preferentially less than 0.5 nm. When the surface roughness exceeds a critical value, the wafers will not bond at all. However RMS and Ra were found to be not sufficient for evaluating the wafer bondability. Hence one tried to relate wafer bonding to the spatial spectrum of the wafer surface profile and indeed some empirical relations that have been found. The first, who proposed a theory on the problem of the closing gaps between contacted wafers was Stengl. This gap-closing theory was then further developed by Tong and Gosele. The elastomechanics theory was used to study the balance between the decrease of surface energy due to the bonding and the increase of elastic energy due to the distortion of the wafer. They considered the worst case by assuming that both wafers have a waviness, with a wavelength (lambda) and a height amplitude h, resulting in a gap height of 2h in a head to head position. This theory is simple and can be used in practice, for studying the formation of the voids, or for constructing design rules for the bonding of deliberately structured wafers. But it is insufficient to know what is the real area of contact in the wafer interface after contact at room temperature because the wafer surface always possesses a random distribution of the surface topography. Therefore Gui developed a continuous model on the influence of the surface roughness to wafer bonding, that is based on a statistical surface roughness model Pandraud demonstrated experimentally that direct bonding between processed glass wafers is possible. This result cannot be explained by considering the RMS value of the surfaces only, because the wafers used show a RMS value larger than 1 nm. Based on the approach exposed in reference six, a rigorous analysis of wafer bonding of these processed glass wafers is presented. We will discuss the relation between the bonding process and different waveguide technologies used for implementing optical waveguides into one or both glass wafers, and give examples of optical devices benefiting from such a bonding process.

Pandraud, Gregory; Gui, Cheng-Qun; Pigeon, Florent; Lambeck, Paul V.; Parriaux, Olivier M.

1999-09-01

101

Augmented reality for wafer prober  

NASA Astrophysics Data System (ADS)

The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

Gilgenkrantz, Pascal

2011-03-01

102

Recent Developments in Microsystems Fabricated by the Liga-Technique  

NASA Technical Reports Server (NTRS)

As an example of microsystems fabricated by the LIGA-technique (x-ray lithography, electroplating and molding), three systems are described and characterized: a triaxial acceleration sensor system, a micro-optical switch, and a microsystem for the analysis of pollutants. The fabrication technologies are reviewed with respect to the key components of the three systems: an acceleration sensor, and electrostatic actuator, and a spectrometer made by the LIGA-technique. Aa micro-pump and micro-valve made by using micromachined tools for molding and optical fiber imaging are made possible by combining LIGA and anisotropic etching of silicon in a batch process. These examples show that the combination of technologies and components is the key to complex microsystems. The design of such microsystems will be facilitated is standardized interfaces are available.

Schulz, J.; Bade, K.; El-Kholi, A.; Hein, H.; Mohr, J.

1995-01-01

103

Multi-Wafer Plasma Anodization.  

National Technical Information Service (NTIS)

A prototype multi-wafer plasma anodization apparatus was designed and constructed to investigate the multi-wafer process. The apparatus uses a hot hollow cathode to generate a dense discharge capable of yielding high oxide growth rates. The samples are pl...

W. B. Orcutt

1972-01-01

104

Silicon cast wafer recrystallization for photovoltaic applications  

E-print Network

Current industry-standard methods of manufacturing silicon wafers for photovoltaic (PV) cells define the electrical properties of the wafer in a first step, and then the geometry of the wafer in a subsequent step. The ...

Hantsoo, Eerik T. (Eerik Torm)

2008-01-01

105

Wafer Replacement Cluster Tool (Presentation);  

SciTech Connect

This presentation on wafer replacement cluster tool discusses: (1) Platform for advanced R and D toward SAI 2015 cost goal--crystal silicon PV at area costs closer to amorphous Si PV, it's 15% efficiency, inexpensive substrate, and moderate temperature processing (<800 C); (2) Why silicon?--industrial and knowledge base, abundant and environmentally benign, market acceptance, and good efficiency; and (3) Why replace wafers?--expensive, high embedded energy content, and uses 50-100 times more silicon than needed.

Branz, H. M.

2008-04-01

106

Advanced Modelling of Silicon Wafer Solar Cells  

NASA Astrophysics Data System (ADS)

Modelling of solar cells today is general practice in research and widely-used in industry. Established modelling software is typically limited to one dimension and/or to small scales. Additionally, novel effects, like, e.g., the use of diffractive structures or luminescent materials, are not established. In this paper we discuss how the combination of different modelling techniques can be used to overcome these limitations. In this context two examples are presented. The first example concerns the combination of the open source simulation software PC1D with circuit modelling to investigate the effect of local shunts on the global characteristics of a silicon wafer solar cell. For the investigated example (4.5 cm2 cell area) we find that a local point shunt reduces the solar cell efficiency by 4% relative. The second example concerns the modelling of diffractive gratings for thin silicon wafer solar cells. For this purpose, we use the rigorous coupled wave analysis to simulate Sentaurus technical computer-aided design (TCAD) is combined with the rigorous coupled wave analysis, a method to solve Maxwell's equations for periodic structures. Here we show that a grating can be used to improve the absorption in a thin silicon wafer solar cell considerably.

Peters, Marius; Fajun, Ma; Siyu, Guo; Hoex, Bram; Blaesi, Benedikt; Glunz, Stefan; Aberle, Armin; Luther, Joachim

2012-10-01

107

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers  

NASA Astrophysics Data System (ADS)

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

108

Development of Megasonic cleaning for silicon wafers. Final report  

SciTech Connect

The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

Mayer, A.

1980-09-01

109

Fabrication of a spiral microcoil using a 3D-LIGA process  

Microsoft Academic Search

LIGA processes have been developed generally in the 2.5D world. We introduced techniques of 3D X-ray lithography and worm\\u000a injection molding with a unscrewing release mechanism, and succeeded in the development to three dimensions of LIGA process.\\u000a We called this technology 3D-LIGA process, and came to be able to fabricate the plastic molded product with a spiral microstructure.\\u000a Furthermore, we

Harutaka Mekaru; Shinji Kusumi; Noriaki Sato; Masami Shimizu; Michiru Yamashita; Osamu Shimada; Tadashi Hattori

2007-01-01

110

Wafer characteristics via reflectometry and wafer processing apparatus and method  

DOEpatents

An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

Sopori, Bhushan L. (Denver, CO)

2007-07-03

111

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

Vosen, Steven R. (Berkeley, CA)

1999-01-01

112

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Vosen, S.R.

1999-07-27

113

Wafer bonding of 75 mm diameter GaP to AlGaInP-GaP light-emitting diode wafers  

Microsoft Academic Search

The AlGaInP\\/GaP wafer-bonded transparent-substrate (TS) light-emitting diodes (LEDs) have been shown to exhibit luminous efficiencies\\u000a exceeding many conventional lightning sources including 60 W incandescent sources. This paper will demonstrate the feasibility\\u000a of scaling wafer bonding technology to 75 mm diameter wafers and some of the unique challenges associated with this scaling.\\u000a The quality and uniformity of bonding were characterized via

I.-H. Tan; D. A. Vanderwater; J.-W. Huang; G. E. Hofler; F. A. Kish; E. I. Chen; T. D. Ostentowski

2000-01-01

114

Allowable silicon wafer thickness versus diameter for ingot rotation ID wafering  

NASA Technical Reports Server (NTRS)

Inner diameter (ID) wafering of ingot rotation reduce the ID saw blade diameter was investigated. The blade thickness can be reduced, resulting in minimal kerf loss. However, significant breakage of wafers occurs during the rotation wafering as the wafer thickness decreases. Fracture mechanics was used to develop an equation relating wafer thickness, diameter and fracture behavior at the point of fracture by using a model of a wafer, supported by a center column and subjected to a cantilever force. It is indicated that the minimum allowable wafer thickness does not increase appreciably with increasing wafer diameter and that fracture through the thickness rather than through the center supporting column limits the minimum allowable wafer thickness. It is suggested that the minimum allowable wafer thickness can be reduced by using a vacuum chuck on the wafer surface to enhance cleavage fracture of the center core and by using 111 ingots.

Chen, C. P.; Leipold, M. H.

1982-01-01

115

Prospective, Randomized Study: Proximate ® PPH Stapler vs. LigaSure™ for Hemorrhoidal Surgery  

Microsoft Academic Search

PURPOSE: It has been shown that for hemorrhoidal surgery both LigaSure™ and stapler cause less pain than diathermy or scissor dissection. This study has attempted to establish which of the less painful alternatives proves best in an unselected series of patients with hemorrhoidal disease. METHODS: Fifty patients were randomized to undergo stapling hemorrhoidopexy or LigaSure™ hemorrhoidectomy. Parameters investigated were pain

Matthias Kraemer; Tengis Parulava; Michael Roblick; Lothar Duschka; Heinrich Müller-Lobeck

2005-01-01

116

NREL Core Program; Session: Wafer Silicon (Presentation)  

SciTech Connect

This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

Wang, Q.

2008-04-01

117

APPLIED PHYSICS REVIEWSFOCUSED REVIEW Adhesive wafer bonding  

E-print Network

APPLIED PHYSICS REVIEWS­FOCUSED REVIEW Adhesive wafer bonding F. Niklausa Microsystem Technology 9 February 2006 Wafer bonding with intermediate polymer adhesives is an important fabrication-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive

Salama, Khaled

118

Industrial Challenges For Thin Wafer Manufacturing  

Microsoft Academic Search

Because of limited supply of Silicon, there has been an industry-driven requirement for reduction of material consumption per Wp of solar power. As a consequence, the thickness of wafers has been reduced, which in turn has introduced new challenges for the industry. During the wafer manufacturing cycle, the wafers are exposed to mechanical loads caused by sawing, manual handling, liquid

Per Arne Wang; REC Wafer

2006-01-01

119

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Technical Reports Server (NTRS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

120

Enhanced adhesion for LIGA microfabrication by using a buffer layer  

DOEpatents

The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

Bajikar, Sateesh S. (San Jose, CA); De Carlo, Francesco (Darien, IL); Song, Joshua J. (Naperville, IL)

2001-01-01

121

Low temperature wafer direct bonding  

Microsoft Academic Search

A pronounced increase of interface energy of room temperature bonded hydrophilic Si\\/Si, Si\\/SiO2, and SiO2\\/SiO 2 wafers after storage in air at room temperature, 150°C for 10-400 h has been observed. The increased number of OH groups due to a reaction between water and the strained oxide and\\/or silicon at the interface at temperatures below 110°C and the formation of

Qin-Yi Tong; Giho Cha; Roman Gafiteanu; Ulrich Gosele

1994-01-01

122

Wafer Manufacturing and Slicing Using Wiresaw  

NASA Astrophysics Data System (ADS)

Wafer manufacturing (or wafer production) refers to a series of modern manufacturing processes of producing single-crystalline or poly-crystalline wafers from crystal ingot (or boule) of different sizes and materials. The majority of wafers are single-crystalline silicon wafers used in microelectronics fabrication although there is increasing importance in slicing poly-crystalline photovoltaic (PV) silicon wafers as well as wafers of different materials such as aluminum oxide, lithium niobate, quartz, sapphire, III-V and II-VI compounds, and others. Slicing is the first major post crystal growth manufacturing process toward wafer production. The modern wiresaw has emerged as the technology for slicing various types of wafers, especially for large silicon wafers, gradually replacing the ID saw which has been the technology for wafer slicing in the last 30 years of the 20th century. Modern slurry wiresaw has been deployed to slice wafers from small to large diameters with varying wafer thickness characterized by minimum kerf loss and high surface quality. The needs for slicing large crystal ingots (300 mm in diameter or larger) effectively with minimum kerf losses and high surface quality have made it indispensable to employ the modern slurry wiresaw as the preferred tool for slicing. In this chapter, advances in technology and research on the modern slurry wiresaw manufacturing machines and technology are reviewed. Fundamental research in modeling and control of modern wiresaw manufacturing process are required in order to understand the cutting mechanism and to make it relevant for improving industrial processes. To this end, investigation and research have been conducted for the modeling, characterization, metrology, and control of the modern wiresaw manufacturing processes to meet the stringent precision requirements of the semiconductor industry. Research results in mathematical modeling, numerical simulation, experiments, and composition of slurry versus wafer quality are presented. Summary and further reading are also provided.

Kao, Imin; Chung, Chunhui; Moreno Rodriguez, Roosevelt

123

Characterization of Sidewall and Planar Surfaces of Electroformed LIGA Parts  

SciTech Connect

The nature of surfaces and the way they interact with each other during sliding contact can have a direct bearing on the performance of a microelectromechanical (MEMS) device. Therefore, a study was undertaken to characterize the surfaces of LIGA fabricated Ni and Cu components. Sidewall and planar surfaces were examined by scanning electron microscopy (SEM) and atomic force microscopy (AFM). Surface roughness was quantified using the AFM. Post-processing (e.g. lapping, removal of polymer film) can profoundly influence the morphology of LIGA components. Edge rounding and smearing of ductile materials during lapping can result in undesirable sidewall morphologies. By judicious selection of AFM scan sizes, the native roughness ({approximately}10 nm RMS) can be distinguished from that arising due to post processing, e.g. scratches, debris, polymer films. While certain processing effects on morphology such as those due to lapping or release etch can be controlled, the true side wall morphology appears to be governed by the morphology of the polymer mold or by the electroforming process itself, and may be much less amenable to modification.

PRASAD,SOMURI V.; HALL,AARON C.; DUGGER,MICHAEL T.

2000-10-01

124

GEM-type detectors using LIGA and etchable glass technologies  

SciTech Connect

Gas electron multipliers (GEMS) have been made by a deep X-ray lithography technique (LIGA process) using synchrotron radiation on polymethylmethacrylate (PMMA) and by UV processes using a UV etchable glass. Gain, stability and rate capability for these detectors are described.The LIGA detectors described consist of PMMA sheets of various thicknesses, 125mm to 350mm, and have 150mm x 150mm square holes spaced with a pitch of 300mm. Thin copper electrodes are plated on the top and bottom surfaces using a Damascene method, followed by electroless plating of the copper onto a palladium-tin base layer. For various thicknesses of PMMA measurements have been made of absolute gain vs. voltage, time stability of gain, and rate capability. The operating gas mixture was usually Ar/CO2 (70/30) gas, but some tests were also done using P10 gas. We also made GEM-like detectors using the UV etchable glass called Foturan, patterned by exposure to UV light and subsequent etching. A few measurements using these detectors will be reported, including avalanche gain and time stability.

Ahn, S.K.; Kim, J.G.; Perez-Mendez, V.; Chang, S.; Jackson, K.H.; Kadyk, J.A.; Wenzel, W.A.; Cho, G.

2001-11-02

125

Technology for integrated circuit micropackages for neural interfaces, based on gold-silicon wafer bonding  

NASA Astrophysics Data System (ADS)

Progress in the development of active neural interface devices requires a very compact method for protecting integrated circuits (ICs). In this paper, a method of forming micropackages is described in detail. The active areas of the chips are sealed in gas-filled cavities of the cap wafer in a wafer-bonding process using Au-Si eutectic. We describe the simple additions to the design of the IC, the post-processing of the active wafer and the required features of the cap wafer. The bonds, which were made at pressure and temperature levels within the range of the tolerance of complementary metal-oxide-semiconductor ICs, are strong enough to meet MIL STD 883G, Method 2019.8 (shear force test). We show results that suggest a method for wafer-scale gross leak testing using FTIR. This micropackaging method requires no special fabrication process and is based on using IC compatible or conventional fabrication steps.

Saeidi, N.; Schuettler, M.; Demosthenous, A.; Donaldson, N.

2013-07-01

126

LIGA-based microsystem manufacturing:the electrochemistry of through-mold depostion and material properties.  

SciTech Connect

The report presented below is to appear in ''Electrochemistry at the Nanoscale'', Patrik Schmuki, Ed. Springer-Verlag, (ca. 2005). The history of the LIGA process, used for fabricating dimensional precise structures for microsystem applications, is briefly reviewed, as are the basic elements of the technology. The principal focus however, is on the unique aspects of the electrochemistry of LIGA through-mask metal deposition and the generation of the fine and uniform microstructures necessary to ensure proper functionality of LIGA components. We draw from both previously published work by external researchers in the field as well as from published and unpublished studies from within Sandia.

Kelly, James J. (Sandia National Laboratories, Livermore, CA); Goods, Steven Howard (Sandia National Laboratories, Livermore, CA)

2005-06-01

127

Wafer bonding for three dimensional (3D) integration  

NASA Astrophysics Data System (ADS)

Wafer scale 3D integration is recognized as an emerging technology to increase the performance of ICs. When bonding with processed ICs, the bonding process must be compatible with IC back-end processing. The fraction of bonded area was examined by optical inspection and BCB was selected as the baseline glue after achieving reproducible void-free bonding. Bond strength at the glue interface of bonded wafers was quantified by four-point bending. Using four point bending, the following effects of BCB glue on the bonding integrity were evaluated; (1) employment of adhesion promoter, (2) BCB glue thickness and (3) material stack. When the adhesion promoter is used, bond strength increases at both BCB bonds of 2.6 mum and 0.4 mum. These results also demonstrate that BCB glue thickness affects the bond strength at the glue interface with thicker glue layers corresponding to higher bond strength. The decrease in bond strength observed for thin BCB is due to a decrease of plastic dissipation energy, Gplastic, which is proportional to BCB thickness. In both bonded wafer pairs that include a PECVD oxide deposited silicon wafer and a glass wafer, bond strengths are linearly proportional to BCB thickness. With these results, the relationship between Gplastic , and bond breaking energy, Gtip, and BCB thickness, t is observed to be Gplastic ? 0.3 · Gtip · t. The effects of thermal cycling on bond strength and residual stress at the interface between BCB and a PECVD oxide, and the thermal stability of BCB were evaluated by four point bending and wafer curvature measurements. Stress relaxation of the PECVD oxide layer during thermal cycling leads to a decrease in the deformation energy due to residual stress, G residual, and to an increase in bond strength. In thermal cycling performed at temperatures of 350 and 400°C, it is observed that the relaxation of residual stress occurs predominantly during the first thermal cycle. Conclusively, the BCB process for wafer-to-wafer bonding applications is stabilized after four cycles at a temperature of 400°C. Thermal cycling performed at a temperature 450°C leads to cohesive failure within the BCB layer with low bond strength (<0.5 J/m2).

Kwon, Yongchai

2003-10-01

128

Full chip implant correction with wafer topography OPC modeling in 2x nm bulk technologies  

NASA Astrophysics Data System (ADS)

Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted overexposure by wafer topography with technology node downscaling evolution [1], [2]. Starting from 2xnm technology nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer topography which can cause drastic pattern degradation [2], [3]. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a consequence, computational lithography solutions are currently under development in order to correct wafer topographical effects on mask [3]. For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer stack. In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC flow for chip scale mask correction is presented with quality and run time penalty analysis.

Michel, J.-C.; Le Denmat, J.-C.; Sungauer, E.; Robert, F.; Yesilada, E.; Armeanu, A.-M.; Entradas, J.; Sturtevant, J. L.; Do, T.; Granik, Y.

2013-09-01

129

Thin film effects in ultrasonic wafer thermometry  

Microsoft Academic Search

We use an ultrasonic technique where the temperature dependence of lowest order anti-symmetric Lamb wave velocity in the silicon wafer is utilized for in-situ temperature measurement in the 20-1000°C range. In almost all wafer processing steps, one or more layers of thin films are present on the wafers. The effects of these films on temperature sensitivity is investigated. A theoretical

F. L. Degertekin; J. Pei; B. V. Honein; B. T. Khuri-Yakub; K. C. Saraswat

1994-01-01

130

Effect of Wafer Bow and Etch Patterns in Direct Wafer Bonding  

E-print Network

Direct wafer bonding has been identified as an en-abling technology for microelectromechanical systems (MEMS). As the complexity of devices increase and the bonding of multiple patterned wafers is required, there is a need ...

Spearing, S. Mark

131

Performance Evaluations of Ceramic Wafer Seals  

NASA Technical Reports Server (NTRS)

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

132

Wafer level reliability for high-performance VLSI design  

NASA Technical Reports Server (NTRS)

As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

Root, Bryan J.; Seefeldt, James D.

1987-01-01

133

Recombinant ligA for leptospirosis diagnosis and ligA among the Leptospira spp. clinical isolates.  

PubMed

Rapid diagnosis for differentiation of leptospirosis from other pyrogenic infections prevailing in the same locality is imperative for proper treatment. During infection, the pathogenic Leptospira spp. express virulence factors which induce antibody responses in the infected host. In this study, 50 referenced Leptospira spp. belonging to six genomospecies and 10 L. interrogans clinical isolates were studied for the presence of a gene encoding an in vivo expressed, surface exposed, immunoglobulin-like protein, LigA, by using PCR and southern hybridization specific to the 5' terminus sequence of the DNA. LigA was also detected in the Leptospira spp. whole cell homogenates by a direct ELISA using a mouse antiserum to the C-terminal portion of recombinant LigA (cLigA) as a detection reagent. All pathogenic Leptospira spp. except one of the two strains of L. santorasai were positive for the gene and its phenotype while all of the L. borgpetersenii and L. biflexa strains were negative. Recombinant cLigA was used as an antigen in ELISAs for detecting IgM and IgG in the sera of leptospirosis patients and in the sera of patients with other febrile illnesses and healthy subjects. When acute phase sera were tested by the cLigA IgM- and IgG-ELISAs, 92% and 100% of the MAT-positive sera were positive, respectively. The diagnostic sensitivity was 100% when both IgM- and IgG-ELISAs were performed on the same acute phase sera and the results were combined. Acute and convalescence sera of patients who were Leptospira culture positive but MAT/IgM-dipstick negative gave 88% and 100% positives by combined cLigA IgM/IgG ELISAs. The diagnostic specificities for the cLigA IgM- and IgG-ELISAs were 98% and 100%, respectively. Our cLigA based-serology has a high potential for early diagnosis of leptospirosis especially when the culture and MAT results are not yet available. PMID:18079011

Srimanote, Potjanee; Wongdeethai, Nattawut; Jieanampunkul, Pathumporn; Samonkiert, Suwanna; Leepiyasakulchai, Chaniya; Kalambaheti, Thareerat; Prachayasittikul, Virapong

2008-01-01

134

A LigA Three-Domain Region Protects Hamsters from Lethal Infection by Leptospira interrogans  

Microsoft Academic Search

The leptospiral LigA protein consists of 13 bacterial immunoglobulin-like (Big) domains and is the only purified recombinant subunit vaccine that has been demonstrated to protect against lethal challenge by a clinical isolate of Leptospira interrogans in the hamster model of leptospirosis. We determined the minimum number and location of LigA domains required for immunoprotection. Immunization with domains 11 and 12

Mariana L. Coutinho; Henry A. Choy; Melissa M. Kelley; James Matsunaga; Jane T. Babbitt; Michael S. Lewis; Jose Antonio G. Aleixo; David A. Haake

2011-01-01

135

Elimination of wafer edge die yield loss for accelerometers  

Microsoft Academic Search

Residual stresses from deposition of several micron thick polysilicon film on accelerometer wafers caused wafer to warp towards edge of wafer. The average peak to valley difference for wafer flat across wafer is 16 +\\/- 1 micrometers . The photo layer following the thick polysilicon deposition process is a CD critical layer with 1 micrometers spacing to be resolved. With

Zhenjun Zhang; Kim A. Eskes

2000-01-01

136

Mechanics of the pad-abrasive-wafer contact in chemical mechanical polishing  

NASA Astrophysics Data System (ADS)

In chemical mechanical polishing (CMP), a rigid wafer is forced on a rough, elastomeric polishing pad, while a slurry containing abrasive particles flows through the interface. The applied pressure on the wafer is carried partially by the 2-body pad-wafer contact (direct contact) and partially by the 3-body contact of pad, wafer and abrasive particles ( particle contact). The fraction of the applied pressure carried by particle contacts is an important factor affecting the material removal rate (MRR) as the majority of the material is removed by the abrasive particles trapped between the pad asperities and the wafer. In this thesis, the contact of a rough, deformable pad and a smooth, rigid wafer in the presence of rigid abrasive particles at the contact interface is investigated by using contact mechanics and finite element (FE) modeling. The interactions between the pad, the wafer and the abrasive particles are modeled at different scales of contact, starting from particle level interactions, and gradually expanding the contact scale to the multi-asperity contact of pad and wafer. The effect of surface forces consisting of van der Waals and electrical double layer forces acting between the wafer and the abrasive particles are also investigated in this work. The wear rate due to each abrasive particle is calculated based on the wafer-abrasive particle contact force, and by considering adhesive and abrasive wear mechanisms. A passivated layer on the wafer surface with a hardness and thickness determined by the chemical effects is modeled, in order to characterize the effect of chemical reactions between slurry and wafer on the MRR. The model provides accurate predictions for the MRR as a function of pad related parameters; pad elastic modulus, pad porosity and pad topography, particle related parameters; particle size and concentration, and slurry related parameters; slurry pH, thickness and hardness of the passivated surface layer of wafer. A good qualitative agreement between the model and the experiments is found for the variation of the MRR with respect to these parameters. Furthermore, closed form equations are derived in order to optimize the CMP parameters for maximizing the material removal efficiency, which is a measure of the ability of pad to transmit the applied pressure on the abrasive particles. The optimization of the CMP parameters described in this thesis may be particularly important for the low-pressure CMP of ultra-low-k (ULK) dielectric materials, where it is difficult to achieve acceptable MRR without compromising the porous structure of ULK materials.

Bozkaya, Dincer

137

Modeling and fabrication of micro 3K-2-type planetary gear reducer utilizing SU8 photoresist as alternative LIGA technology  

Microsoft Academic Search

The LIGA type process, utilizing SU-8 photoresist as alternative LIGA technology, can fabricate high aspect ratio microstructures without employing synchrotron light and suitable X-ray mask. Based on LIGA type process in this paper, detailed investigations of the modeling and fabrication of micro 3K-2 type planetary gear reducer, such as the modeling and design of micro reducer, CAD of micro gear

Weiping Zhang; Wenyuan Chen; Di Chen; Xiaomei Chen; Xiaosheng Wu; Zhengfu Xu

2001-01-01

138

The evolution of silicon wafer cleaning technology  

Microsoft Academic Search

The purity of wafer surfaces is an essential requisite for the successful fabrication of VLSI and ULSI silicon circuits. Wafer cleaning chemistry has remained essentially unchanged in the past 25 years and is based on hot alkaline and acidic hydrogen peroxide solutions, a process known as RCA Standard Clean. This is still the primary method used in the industry. What

Werner Kern

1990-01-01

139

Electrostatic Wafer Chuck for Electron Beam Microfabrication  

Microsoft Academic Search

Vacuum wafer chucks are useless for electron beam microfabrication. An analysis of the required electrostatic forces and frequency response of a specimen wafer on a field plate is made. An experimental electrostatic chuck and its high voltage square wave power supply have been fabricated. Full clamping action has been provided by electrostatic pressures of 1?6 atm, and 1 atm pressures

George A. Wardly

1973-01-01

140

Designing a mechanism to cleave silicon wafers  

E-print Network

A device was designed and manufactured to precisely cleave silicon wafers. Two vacuum chucks were designed to support a 150 mm diameter silicon wafer and cleave it by providing a pure moment at a pre-etched v-notch while ...

Figueroa, Victor, 1982-

2004-01-01

141

LSA project perspective of wafering technology  

NASA Technical Reports Server (NTRS)

The economics and techniques for eliminating wafering as a part of ingot technology in the production of silicon sheets for photovoltaic applications are considered. Technical progress in both ingot and non-ingot technologies for the low cost solar array project is described in the context of process economics. The critical areas of research in wafering are delineated and their payoff potential discussed.

Koliwad, K. M.

1982-01-01

142

Wafer level packaging of silicon pressure sensors  

Microsoft Academic Search

In this paper, a new pre-packaging technique for silicon pressure sensors on the wafer level is presented. It is based on the use of UV photopatternable silicone which is deposited over the whole wafer by means of a novel device suitable for low-viscosity material coating and mask alignment. The process consists of the exposure of the deposited layer to UV

H Krassow; F Campabadal; E Lora-Tamayo

2000-01-01

143

Simulations of a SCALPEL wafer-heating correction using an adaptive Kalman filter  

Microsoft Academic Search

The high-energy (100KeV) electron imaging process used by SCALPEL causes a dynamic heat load and wafer expansion response. Despite good thermal contact between the wafer and chuck, the dynamic distortion on a die length scale is too large to allow in the overlay error budget, and is fundamentally difficult to prevent or dissipate. However, the sub-field scanning strategy of SCALPEL

Stuart T. Stanton

2001-01-01

144

Improvement in ability of wafer-formed cleaning material \\  

Microsoft Academic Search

To minimize particles on the back surface of wafer, the operator usually cleans the wafer chuck table regularly. We have introduced a new cleaning method with the use of our wafer-formed cleaning material called \\

N. Maruoka; Y. Terada; D. Uenda; M. Namikawa; T. Hayashi

2003-01-01

145

Wafer Probe Station, Low Noise Amplifiers, and Wideband Feed Developments  

E-print Network

-ridge flared horn wideband feeds #12;Wafer Fabrication of LNA's and Other Radiometer Components 20-Sep-2011. · Station can handle a 100mm diameter wafer with several thousand MMIC's · Motor-driven precision wafer

Weinreb, Sander

146

Desirable wafer edge flatness for CD control in photolithography  

Microsoft Academic Search

Desirable wafer edge flatness was investigated to obtain optimum free-standing wafer edge shape for photolithography. In order to obtain the criteria of free-standing edge shape, we clarified the desirable post-chuck flatness at edge sites in advance. We investigated a desirable free-standing wafer edge, taking into consideration both the wafer and wafer holder shape. Firstly, to obtain a desirable post-chuck wafer

Tadahito Fujisawa; Soichi Inoue; Tsuneyuki Hagiwara; Kodama Kennichi; Makoto Kobayashi; Katsuya Okumura

2003-01-01

147

Switchable static friction of piezoelectric composite—silicon wafer contacts  

NASA Astrophysics Data System (ADS)

The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and a silicon wafer counter surface rests solely on the matrix region of the piezocomposite surface. When actuated, the piezoelectric ceramic fibers protrude from the surface and the wafer rests solely on these protrusions. A threefold decrease in engineering static friction coefficient upon actuation of the piezocomposite was observed: from ?* = 1.65 to ?* = 0.50. These experimental results could be linked to the change in contact surface area and roughness using capillary adhesion theory, which relates the adhesive force to the number and size of the contacting asperities for the different surface states.

van den Ende, D. A.; Fischer, H. R.; Groen, W. A.; van der Zwaag, S.

2013-04-01

148

Effect of annealing of multi crystalline edge wafers and Cz mono crystalline wafers based on metallurgical silicon  

Microsoft Academic Search

The objective of this study has been to investigate the effect of annealing of multi crystalline edge wafers and Cz mono crystalline wafers based on metallurgically refined silicon. Sets of neighboring wafers have been annealed at different temperatures and compared with as cut wafers as well as P-gettered wafers. The wafers have been characterized by ?-PCD, QSSPC, FeB-pair splitting and

Arve Holt; Birger RetterstllJl Olaisen; Erik Enebakk; Anne-Karin Soiland

2008-01-01

149

Development of megasonic cleaning for silicon wafers  

NASA Technical Reports Server (NTRS)

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Mayer, A.

1980-01-01

150

Three wafer stacking for 3D integration.  

SciTech Connect

Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

2011-11-01

151

An aluminum resist substrate for microfabrication by LIGA.  

SciTech Connect

Resist substrates used in the LIGA process must provide high initial bond strength between the substrate and resist, little degradation of the bond strength during x-ray exposure, acceptable undercut rates during development, and a surface enabling good electrodeposition of metals. Additionally, they should produce little fluorescence radiation and give small secondary doses in bright regions of the resist at the substrate interface. To develop a new substrate satisfying all these requirements, we have investigated secondary resist doses due to electrons and fluorescence, resist adhesion before exposure, loss of fine features during extended development, and the nucleation and adhesion of electrodeposits for various substrate materials. The result of these studies is a new anodized aluminum substrate and accompanying methods for resist bonding and electrodeposition. We demonstrate successful use of this substrate through all process steps and establish its capabilities via the fabrication of isolated resist features down to 6 {micro}m, feature aspect ratios up to 280 and electroformed nickel structures at heights of 190 to 1400 {micro}m. The minimum mask absorber thickness required for this new substrate ranges from 7 to 15 {micro}m depending on the resist thickness.

Kelly, James J.; Boehme, Dale R.; Hauck, Cheryl A. (Lawrence Berkeley National Laboratory, Berkeley, CA); Yang, Chu-Yeu Peter; Hunter, Luke L.; Griffiths, Stewart K.; McLean, Dorrance E.; Aigeldinger, Georg; Hekmaty, Michelle A.; Hachman, John T.; Losey, Matthew W.; Skala, Dawn M.; Korellis, John S.; Friedmann, Thomas Aquinas (Sandia National Laboratories, Albuquerque, NM); Yang, Nancy Y. C.; Lu, Wei-Yang

2005-04-01

152

Everything Wafers: A Guide to Semiconductor Substrates  

NSDL National Science Digital Library

This website contains information on characteristics and properties of semiconductor wafers. Topics include types of substrates, process dependent characteristics, properties of semiconductors, cleaving, etching and other topics, along with related terms and links.

2012-11-29

153

Image quality and wafer level optics  

NASA Astrophysics Data System (ADS)

Increasing demand from consumers to integrate camera modules into electronic devices, such as cell phones, has driven the cost of camera modules down very rapidly. Now that most cell phones include at least one camera, consumers are starting to ask for better image quality - without compromising on the cost. Wafer level optics has emerged over the past few years as an innovative technology enabling simultaneous manufacturing of thousands of lenses, at the wafer level. Using reflow-compatible materials to manufacture these lenses permits a reduction in the cost and size of camera module, thus answering the market demand for lowering the cost. But what about image quality? The author will present image quality analysis that was conducted for both VGA and megapixel camera resolutions. Comparison between conventional camera modules and wafer level camera modules shows wafer level technology brings equivalent, if not better, image quality performance compared to conventional camera modules.

Dagan, Y.; Humpston, G.

2010-05-01

154

Fabrication of wafer-level thermocompression bonds  

Microsoft Academic Search

Thermocompression bonding of gold is a promising technique for achieving low temperature, wafer-level bonding. The fabrication process for wafer bonding at 300°C via compressing gold under 7 MPa of pressure is described in detail. One of the issues encountered in the process development was e-beam source spitting, which resulted in micrometer diameter sized Au on the surfaces, and made bonding

Christine H. Tsau; S. M. Spearing; M. A. Schmidt

2002-01-01

155

ALD Enabled Wafer Level Polymer Packaging for MEMS  

NASA Astrophysics Data System (ADS)

Wafer level polymer packaging for MEMS is a cost-effective approach that is also compatible with microelectronic packaging technologies. However, polymer packages are not hermetic and cannot be used for MEMS devices, which usually demand vacuum or low moisture environment inside the packages. This problem can be solved by applying atomic layer deposition (ALD) of nano-scaled Al 2O3 or other inorganic materials over the polymer packages. Defects and mechanical cracks in ALD coatings are major concerns for hermetic/vacuum sealing. Several techniques have been developed to inspect such defects and cracks. Assisted by the electroplating copper technique, we have reduced the defect density by 1000 times for an ultra-thin, 2-nm ALD Al2O 3 film. Such an ultra-thin coating is essential to enhance coating's mechanical toughness. The toughness is usually determined by monitoring coating's crack initiation and growth in a bending test. A real-time, non-destructive inspection technique has been developed for in-situ characterization of an ALD film coated on a surface or buried in a multilayer structure. With the knowledge and technology established, we have successfully demonstrated a wafer-level polymer packaging process for MEMS using a Pirani gauge as the vacuum sensor. The leak rate through the polymer package has been reduced by 100 times by the ALD Al2O3 coating. More importantly, we have developed models and identified issues that are critical to ALD-enabled wafer level polymer packaging for MEMS.

Zhang, Yadong

156

Transient thermal analysis of sapphire wafers subjected to thermal shocks  

Microsoft Academic Search

Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed

T. Vodenitcharova; L. C. Zhang; I. Zarudi; Y. Yin; H. Domyo; T. Ho

2006-01-01

157

A novel wafer baking system using hot air streams  

Microsoft Academic Search

This paper presents a novel wafer baking system that uses hot air streams as heating media and achieves good temperature uniformity across the entire wafer surfaces during the baking process. Wind tunnel experiments have been carried out to verify the concept of using hot air streams for wafer baking. A simple prototyping wafer baking system has been designed and fabricated,

Lan Wang; Siew Loong Chow; Ai Poh Loh; Zhi Ming Gong; Woei Wan Tan; Arthur E. B. Tay; Weng Khuen Ho

2004-01-01

158

Development of a 3-Dimensional LIGA Process and Application to Fabricate a Spiral Microcoil  

NASA Astrophysics Data System (ADS)

LIGA process has been developed in the 2.5-dimensional world. We introduced new technologies of a 3D X-ray lithography and a worm injection molding with an unscrewing demolding mechanism, and succeeded in the deployment of a three- dimensional LIGA process. Furthermore, it succeeded to fabricate a spiral microcoil using 3D-LIGA process and a metallization technique combined flat and smooth electroplating and isotropic chemical etching. A diameter of the microcoil was 0.5 mm and the length was 1 mm. The width of coil lines was 10 ?m, and the pitch was 20 ?m. Also the characteristics as an inductor of this microcoil is such that the inductance and the quality factor at the frequency of 1 GHz was 91 nH and 5.8, respectively.

Mekaru, Harutaka; Kusumi, Shinji; Sato, Noriaki; Shimizu, Masami; Yamashita, Michiru; Shimada, Osamu; Hattori, Tadashi

159

Surface-micromachined tunable resonant cavity LED using wafer bonding  

NASA Astrophysics Data System (ADS)

Surface micromachining and wafer bonding techniques have been integrated to fabricate a dual-use resonant cavity tunable LED/photodetector operating at 1.5 micrometers . The device has a tuning range of 75 nm, and a spectral linewidth of 4 nm, with an extinction ratio of greater than 20 dB throughout the tuning range. The device has potential applications in WDM networks and optical interconnects due to the small physical size, beam profile, and wafer-scale fabrication and testing possibilities. A GaAs/AlAs distributed Bragg reflector (DBR) is integrated with an InGaAsP strain-compensated multiple quantum well gain medium using wafer bonding. The InGaAsP material with a central wavelength of 1.52 micrometers is grown lattice-matched on an InP substrate. After wafer bonding, the InP substrate is removed, leaving the active layers on the GaAs-based mirror and substrate. The top DBR mirror of the resonant cavity is formed using surface micromachining techniques. The mirror consists of a 4 5 pair S1/S1O2 DBR and a T1/W support and contact layer. These materials are deposited on a sacrificial polymide layer above the InP-based gain medium. The polymide is selectively etched to release the membrane, creating an air gap between the top mirror and the epitaxial layers. When a voltage is applied between these two layers, the membrane is deflected towards the substrates, changing the Fabry-Perot cavity length, and causing a corresponding change in the resonance wavelength of the device. The device functions as a resonant cavity photodetector by reverse biasing the multiple quantum well region. The absorption bandwidth and wavelength running are identical to the emission characteristics of the same device when used as an LED.

Christenson, Gina L.; Tran, Alex T. D.; Zhu, Zuhua; Lo, Yu-Hwa; Hong, Minghwei; Mannaerts, J. P.; Bhat, Rajaram J.

1997-04-01

160

Advances in process overlay on 300-mm wafers  

NASA Astrophysics Data System (ADS)

Overlay budgets are getting tighter within 300 mm volume production and as a consequence the process effects on alignment and off-line metrology becomes more important. In a short loop experiment, with cleared reference marks in each image field, the isolated effect of processing was measured with a sub-nanometer accuracy. The examined processes are Shallow Trench Isolation (STI), Tungsten-Chemical Mechanical Processing (W-CMP) and resist spinning. The alignment measurements were done on an ASML TWINSCANT scanner and the off-line metrology measurements on a KLA Tencor. Mark type and mark position dependency of the process effects are analyzed. The mean plus 3 (sigma) of the maximum overlay after correcting batch average wafer parameters is used as an overlay performance indicator (OPI). 3 (sigma) residuals to the wafer-model are used as an indicator of the noise that is added by the process. The results are in agreement with existing knowledge of process effects on 200 mm wafers. The W-CMP process introduces an additional wafer rotation and scaling that is similar for alignment marks and metrology targets. The effects depend on the mark type; in general they get less severe for higher spatial frequencies. For a 7th order alignment mark, the OPI measured about 12 nm and the added noise about 12 nm. For the examined metrology targets the OPI is about 20 nm with an added noise of about 90 nm. Two different types of alignment marks were tested in the STI process, i.e., zero layer marks and marks that were exposed together with the STI product. The overlay contribution due to processing on both types of alignment marks is very low (smaller than 5 nm OPI) and independent on mark type. Some flyers are observed fot the zero layer marks. The flyers can be explained by the residues of oxide and nitride that is left behind in the spaces of the alignment marks. Resist spinning is examined on single layer resist and resist with an organic Bottom Anti-Reflective Coating (BARC) underneath. Single layer resist showed scaling on unsegmented marks that disappears using higher diffraction orders and/or mark segmentation. Resist with a planarizing BARC caused additional effects on the wafer edge for measurements with the red laser signal. The effects disappear using the green laser of ATHENAT.

Staecker, Jens; Arendt, Stefanie; Schumacher, Karl; Mos, Evert C.; van Haren, Richard J. F.; van der Schaar, Maurits; Edart, Remi; Demmerle, Wolfgang; Tolsma, Hoite

2002-07-01

161

Randomized Controlled Trial of LigaSure with Submucosal Dissection versus Ferguson Hemorrhoidectomy for Prolapsed Hemorrhoids  

Microsoft Academic Search

Introduction  The aim of this study was to compare the outcomes between the LigaSure vessel sealing system and the conventional closed Ferguson\\u000a hemorrhoidectomy procedure performed by diathermy.\\u000a \\u000a \\u000a \\u000a Methods  A series of 84 patients with grades III and IV hemorrhoids were randomized into two groups: (1) LigaSure hemorrhoidectomy\\u000a with submucosal dissection (42 patients) and (2) Ferguson hemorrhoidectomy (42 patients). The patient demographics, operative

Jaw-Yuan Wang; Chien-Yu Lu; Hsiang-Lin Tsai; Fang-Ming Chen; Che-Jen Huang; Yu-Sheng Huang; Tsung-Jen Huang; Jan-Sing Hsieh

2006-01-01

162

Wafer-size free-standing single-crystalline graphene device arrays  

NASA Astrophysics Data System (ADS)

We report an approach of wafer-scale addressable single-crystalline graphene (SCG) arrays growth by using pre-patterned seeds to control the nucleation. The growth mechanism and superb properties of SCG were studied. Large array of free-standing SCG devices were realized. Characterization of SCG as nano switches shows excellent performance with life time (>22 000 times) two orders longer than that of other graphene nano switches reported so far. This work not only shows the possibility of producing wafer-scale high quality SCG device arrays but also explores the superb performance of SCG as nano devices.

Li, Peng; Jing, Gaoshan; Zhang, Bo; Sando, Shota; Cui, Tianhong

2014-08-01

163

Wafer-fused semiconductor radiation detector  

DOEpatents

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

2002-01-01

164

Using wafer stacks as neutron monochromators  

NASA Astrophysics Data System (ADS)

A process to introduce a spatially homogeneous but anisotropic mosaic structure into thin, single-crystal wafers, which are then stacked and used as neutron monochromators, is described. The advantages compared to conventional techniques are good reproduceability, low cost and reduced risk of process failure. A focusing Ge(115) monochromator made from 24 wafer stacks was built for the high-resolution neutron powder diffractometer at the High Flux Beam Reactor at Brookhaven National Laboratory. Besides building "classical" monochromators for elastic neutron scattering experiments, individual wafers with a given peak reflectivity can be tilted with respect to each other to increase the reflected wavelength band ??/?. Such "fanned" arrays present a competitive alternative to monochromators using highly-oriented pyrolitic graphite (HOPG).

Vogt, T.; Passell, L.; Cheung, S.; Axe, J. D.

1994-01-01

165

Biocompatible "click" wafer bonding for microfluidic devices.  

PubMed

We introduce a novel dry wafer bonding concept designed for permanent attachment of micromolded polymer structures to surface functionalized silicon substrates. The method, designed for simultaneous fabrication of many lab-on-chip devices, utilizes a chemically reactive polymer microfluidic structure, which rapidly bonds to a functionalized substrate via"click" chemistry reactions. The microfluidic structure consists of an off-stoichiometry thiol-ene (OSTE) polymer with a very high density of surface bound thiol groups and the substrate is a silicon wafer that has been functionalized with common bio-linker molecules. We demonstrate here void free, and low temperature (< 37 °C) bonding of a batch of OSTE microfluidic layers to a silane functionalized silicon wafer. PMID:22760578

Saharil, Farizah; Carlborg, Carl Fredrik; Haraldsson, Tommy; van der Wijngaart, Wouter

2012-09-01

166

Low-cost wafer level packaging process  

NASA Astrophysics Data System (ADS)

Today, semiconductors are being connected to other components of the system through three main interconnect technologies - Wirebond, TAB and Solder bump. Of the three technologies, use of solder bump provides the lowest impedance electrical path and a high er I/O density as compared to wirebond and TAB. Wafer bumping is often accompanied by a need for redistribution of the current carrying pads on the silicon in order to reduce the substrate cost and better manufacturing yields, Besides, there is a need to deposit a metallic layer underneath the bump for good reliability of the packaged system. The two widely used processes used for depositing a thin metal film, either for redistribution or UBM are Physical Vapor Deposition and evaporation. These processes are significant contributors to the cost of the bumped wafer. In the packaging industry, there is also a drive for going towards wafers level packaging solutions in order to minimize the packaging cost and giving high production rates.

Kapoor, Rahul; Khim, Swee Y.; Hwa, Goh H.

2000-10-01

167

Dimensional errors in LIGA-produced metal structures due to thermal expansion and swelling of PMMA  

Microsoft Academic Search

Numerical methods are used to examine dimensional errors in metal structures microfabricated by the LIGA process. These errors result from elastic displacements of the PMMA mould during electrodeposition and arise from thermal expansion of the PMMA when electroforming is performed at elevated temperatures and from PMMA swelling due to absorption of water from aqueous electrolytes. Both numerical solutions and simple

S. K. Griffiths; J. A. W. Crowell; B. L. Kistler; A. S. Dryden

2004-01-01

168

Total x-ray power measurements in the Sandia LIGA program.  

SciTech Connect

Total X-ray power measurements using aluminum block calorimetry and other techniques were made at LIGA X-ray scanner synchrotron beamlines located at both the Advanced Light Source (ALS) and the Advanced Photon Source (APS). This block calorimetry work was initially performed on the LIGA beamline 3.3.1 of the ALS to provide experimental checks of predictions of the LEX-D (LIGA Exposure- Development) code for LIGA X-ray exposures, version 7.56, the version of the code in use at the time calorimetry was done. These experiments showed that it was necessary to use bend magnet field strengths and electron storage ring energies different from the default values originally in the code in order to obtain good agreement between experiment and theory. The results indicated that agreement between LEX-D predictions and experiment could be as good as 5% only if (1) more accurate values of the ring energies, (2) local values of the magnet field at the beamline source point, and (3) the NIST database for X-ray/materials interactions were used as code inputs. These local magnetic field value and accurate ring energies, together with NIST database, are now defaults in the newest release of LEX-D, version 7.61. Three dimensional simulations of the temperature distributions in the aluminum calorimeter block for a typical ALS power measurement were made with the ABAQUS code and found to be in good agreement with the experimental temperature data. As an application of the block calorimetry technique, the X-ray power exiting the mirror in place at a LIGA scanner located at the APS beamline 10 BM was measured with a calorimeter similar to the one used at the ALS. The overall results at the APS demonstrated the utility of calorimetry in helping to characterize the total X-ray power in LIGA beamlines. In addition to the block calorimetry work at the ALS and APS, a preliminary comparison of the use of heat flux sensors, photodiodes and modified beam calorimeters as total X-ray power monitors was made at the ALS, beamline 3.3.1. This work showed that a modification of a commercially available, heat flux sensor could result in a simple, direct reading beam power meter that could be a useful for monitoring total X-ray power in Sandia's LIGA exposure stations at the ALS, APS and Stanford Synchrotron Radiation Laboratory (SSRL).

Malinowski, Michael E. (Sandia National Laboratories, Livermore, CA); Ting, Aili (Sandia National Laboratories, Livermore, CA)

2005-08-01

169

Making Porous Luminescent Regions In Silicon Wafers  

NASA Technical Reports Server (NTRS)

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

170

Apparatus for edge etching of semiconductor wafers  

NASA Technical Reports Server (NTRS)

A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

Casajus, A.

1986-01-01

171

ELID supported grinding of thin sapphire wafers  

Microsoft Academic Search

Sapphire material is, due to its crystal structure, difficult to machine in an economic way. There is a request for thin, i.e. below 0.2 mm thickness, sub surface damage free wafers to produce sensor elements. ELID -- electrolytic in process dressing -- is an innovative high end grinding technology, using small grain sizes, which enable to manufacture surfaces in a

Igor Makarenko; Christian Vogt; Rolf Rascher; Peter Sperber; Thomas Stirner

2010-01-01

172

Wafer Bonded Subwavelength Metallo-Dielectric Laser  

E-print Network

core radius) operating at 77 K, as well as near-subwavelength (450-nm gain core radius) operating compatible active optical components is critical for creating integrated silicon photonic circuits that include integration of the optical gain material with a silicon-on-insulator (SOI) wafer,

Fainman, Yeshaiahu

173

Geometry control of recrystallized silicon wafers for solar applications  

E-print Network

The cost of manufacturing crystalline silicon wafers for use in solar cells can be reduced by eliminating the waste streams caused by sawing ingots into individual wafers. Professor Emanuel Sachs has developed a new method ...

Ruggiero, Christopher W

2009-01-01

174

INFLUÊNCIA DE TRATAMENTOS TERMOMECÂNICOS NAS PROPRIEDADES MECÂNICAS E ELÉTRICAS DE LIGAS Cu-Ni-Pt e Cu-Ni-Sn  

Microsoft Academic Search

RESUMO O cobre e suas ligas têm diferentes aplicações na sociedade moderna devido as excelentes propriedades elétricas, condutividade térmica, resistência à corrosão e outras propriedades. Estas aplicações podem ser em válvulas, tubulações, sistemas para absorção de energia solar, radiadores para automóveis, condutor de corrente, condutor eletrônico, elementos de termostatos. Dentre estas ligas utilizadas podemos destacar Cu-Be, Cu-Sn e Cu-Pt. O

Elias da Silva; W. A. Monteiro; Lineu Prestes

175

Fabrication of sub-micron whole-wafer SIS tunnel junctions for millimeter wave mixers  

NASA Astrophysics Data System (ADS)

As part of a program for the development of a space-qualified submmillimeter-wave mixer operating in the region of one terahertz, the authors have developed processes for the fabrication of submicron whole-wafer tunnel junctions. Using the self-aligned whole-wafer process (SAWW) with electron beam lithography they have been able to reliably fabricate high-quality (Vm above 20 mV) submicron tunnel junctions from whole-wafer Nb/AlO(x)/Nb structures. In particular, it is shown that the junction quality is independent of size down to 0.3-sq micron junction area. The problems of thin stress, anodization, registration for electron beam lithography, and lift-off, which limit the yield of good quality submicron-scale junctions are addressed.

Huq, S. E.; Blamire, M. G.; Evetts, J. E.; Hasko, D. G.; Ahmed, H.

1991-03-01

176

Fundamental characteristics of electrostatic wafer chuck with insulating sealant  

Microsoft Academic Search

In the semiconductor industry, many manufacturing processes, such as CVD or dry etching, are performed in vacuum condition. The electrostatic wafer chuck is the most preferable handling method under such circumstances. It enables retention of a wafer flat and enhanced heat transfer through the whole surface area because the wafer can firmly contact with the chuck. We have investigated the

Kyoko YATSUZUKA; Fumikazu HATAKEYAMA; Kazutoshi ASANO; Shinichiro AONUMA

1998-01-01

177

Experimental investigation and finite element analysis of bump wafer probing  

Microsoft Academic Search

The purpose of this paper is to analyze the bump height variation and probe mark profile with various bump materials for wafer probing. It is necessary to establish different material bump wafer probing criteria, because the bump height variation and probe mark area have severe influence on the sort flip chip wafers that will affects the quality of the contact

Hao-Yuan Chang; Wen-Fung Pan; Meng-Kai Shih; Yi-Shao Lai

2009-01-01

178

Strength of Si Wafers with Microcracks: A Theoretical Model (Poster)  

SciTech Connect

A new analytical expression that takes into account the surface, edge, and bulk properties of a wafer has been proposed to describe the strength of the brittle materials. A new proposed fracture-mechanics numerical simulation successfully predicted the strength of the cast silicon wafers. It has been shown that the predicted wafer strength distribution agrees well with the available experimental results.

Rupnowski, P.; Sopori, B.

2008-05-01

179

Graphic script provides quick classification of GaAs wafers  

Microsoft Academic Search

Infrared transmission topography has long been used to detect variations in gallium arsenide wafers that can cause dark-line defects that limit lifetime of GaAs lasers and solar cells. In the past, infrared transmission was measured over a whole wafer by scanning a small spot mechanically. Absorption was calculated at each location across the surface of the wafer and used to

Millard G. Mier

2000-01-01

180

In-situ ultrasonic thermometry of semiconductor wafers  

Microsoft Academic Search

We report a temperature measurement technique based on the temperature dependence of acoustic wave velocity in silicon wafers. The zeroth order antisymmetric Lamb wave is excited in the wafer using the quartz pins which support the wafer during processing. Extensional waves are generated in the quartz pin by a PZT-SH transducer and the acoustic energy is coupled to the Lamb

F. L. Degertekin; J. Pei; Y. J. Lee; B. T. Khuri-Yakub; K. C. Saraswat

1993-01-01

181

Multivariable feedback relevant system identification of a wafer stepper system  

Microsoft Academic Search

This paper discusses the approximation and feedback relevant parametric identification of a positioning mechanism present in a wafer stepper. The positioning mechanism in a wafer stepper is used in chip manufacturing processes for accurate positioning of the silicon wafer on which the chips are to be produced. The accurate positioning requires a robust and high-performance feedback controller that enables a

Raymond A. de Callafon; Paul M. J. Van den Hof

2001-01-01

182

Room temperature wafer level glass\\/glass bonding  

Microsoft Academic Search

The findings of this study report the bonding of glass\\/glass wafers by using the surface activated bonding (SAB) method at room temperature (RT) without heating. In order to bond, the glass wafers were activated by a sequential plasma activation process, in which the wafers were cleaned with reactive ion etching (RIE) oxygen radio frequency (rf) plasma and nitrogen radical microwave

M. M. R. Howlader; Satoru Suehara; Tadatomo Suga

2006-01-01

183

Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon wafers  

E-print Network

Plasma-activated direct bonding of diamond-on-insulator wafers to thermal oxide grown silicon microscopy, profilometer and wafer bow measurements. Plasma-activated direct bonding of DOI wafers to thermal September 2010 Keywords: Diamond-on-insulator Plasma activation Ultrananocrystalline diamond Direct bonding

Akin, Tayfun

184

Optical properties of LiGaS2: an ab initio study and spectroscopic ellipsometry measurement  

NASA Astrophysics Data System (ADS)

Electronic and optical properties of lithium thiogallate crystal, LiGaS2, have been investigated by both experimental and theoretical methods. The plane-wave pseudopotential method based on DFT theory has been used for band structure calculations. The electronic parameters of Ga 3d orbitals have been corrected by the DFT+U methods to be consistent with those measured with x-ray photoemission spectroscopy. Evolution of optical constants of LiGaS2 over a wide spectral range was determined by developed first-principles theory and dispersion curves were compared with optical parameters defined by spectroscopic ellipsometry in the photon energy range 1.2-5.0 eV. Good agreement has been achieved between theoretical and experimental results.

Atuchin, V. V.; Lin, Z. S.; Isaenko, L. I.; Kesler, V. G.; Kruchinin, V. N.; Lobanov, S. I.

2009-11-01

185

Fracture of GaAs Wafers  

Microsoft Academic Search

Fracture characteristics of undoped and several kinds of doped GaAs single-crystal wafers were studied. The fracture toughness value determined by four-point bending fracture test of specimens precracked by indentation at room temperature showed no difference for In-, Si-, Cr- and undoped crystals. Indentation microcracking characteristics of In-, Si- and undoped crystals and probability distribution functions of the fracture stresses of

Kiyoshi Yasutake; Yoshito Konishi; Kaoru Adachi; Kumayasu Yoshii; Masataka Umeno; Hideaki Kawabe

1988-01-01

186

Warpage Measurement of Thin Wafers by Reflectometry  

NASA Astrophysics Data System (ADS)

To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

Ng, Chi Seng; Asundi, Anand Krishna

187

Precipitating Chromium Impurities in Silicon Wafers  

NASA Technical Reports Server (NTRS)

Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

Salama, A. M.

1982-01-01

188

VLED for Si wafer-level packaging  

NASA Astrophysics Data System (ADS)

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

189

Fabrication of a 3D differential-capacitive acceleration sensor by UV-LIGA  

Microsoft Academic Search

A novel three-dimensional (3D) acceleration sensor has been fabricated by combining the low-cost UV-LIGA surface microstructuring process with a sacrificial layer technique. It detects the triaxial accelerations using three independent, yet on a common substrate-integrated, sensor elements. Each element is configured as a differential capacitor with its movable seismic mass as the middle electrode. The fabrication is a simple planar

Wenmin Qu; Christian Wenzel; Gerald Gerlach

1999-01-01

190

A Transdermal Drug Delivery System Based on LIGA Technology and Soft Lithography  

NASA Astrophysics Data System (ADS)

This report presents a transdermal drug delivery system based on LIGA fabricated microparts. It is a portable device combining a magnetically actuated micro gear pump with a microneedle array. The fluidic behaviour of the system is analyzed in order to predict its performance according to the dimension of the microparts and then compared to experimental data. The manufacturing process of both micropump and microneedle array are described.

Matteucci, Marco; Perennes, Frederic; Marmiroli, Benedetta; Di Fabrizio, Enzo

2007-01-01

191

An Experimental Study of Fracture of LIGA Ni Micro-Electro-Mechanical Systems Thin Films  

Microsoft Academic Search

This article presents the results of an experimental study of fracture in LIGA Ni micro-electro-mechanical systems (MEMS)\\u000a thin films. Microtesting techniques are developed for the study of the J-resistance curve (J-?a) behavior in compact tension (CT) thin film specimens. In-situ measurements of crack-tip strain are presented together with in-situ and ex-situ microscopic images of crack-tip deformation and fracture mechanisms. Fractographic

Y. Yang; S. Allameh; B. Boyce; K. S. Chan; W. O. Soboyejo

2007-01-01

192

Diamond-like nanocomposite coatings for LIGA-fabricated nickel alloy parts.  

SciTech Connect

A commercial plasma enhanced chemical vapor deposition (PECVD) technique with planetary substrate rotation was used to apply a thin (200-400 nm thick) conformal diamond-like carbon (DLC) coating (known as a diamond-like nanocomposite (DLN)) on LIGA fabricated Ni-Mn alloy parts. The PECVD technique is known to overcome the drawbacks associated with the line-of-sight nature of physical vapor deposition (PVD) and substrate heating inherent with traditional chemical vapor deposition (CVD). The purpose of the present study is to characterize the coverage, adhesion, and tribological (friction and wear) behavior of DLN coatings applied to planar and sidewall surfaces of small featured LIGA Ni-Mn fabricated parts, e.g. 280 {micro}m thick sidewalls. Friction and wear tests were performed in dry nitrogen, dry air, and air with 50% RH at Hertzian contact pressures ranging from 0.3 to 0.6 GPa. The friction coefficient of bare Ni-Mn alloy was determined to be 0.9. In contrast, low friction coefficients ({approx}0.02 in dry nitrogen and {approx}0.2 in 50% RH air) and minimal amount of wear were exhibited for the DLN coated LIGA Ni-Mn alloy parts and test coupons. This behavior was due to the ability of the coating to transfer to the rubbing counterface providing low interfacial shear at the sliding contact; resultantly, coating one surface was adequate for low friction and wear. In addition, a 30 nm thick titanium bond layer was determined to be necessary for good adhesion of DLN coating to Ni-Mn alloy substrates. Raman spectroscopy and cross-sectional SEM with energy dispersive x-ray analysis revealed that the DLN coatings deposited by the PECVD with planetary substrate rotation covered both the planar and sidewall surfaces of LIGA fabricated parts, as well as narrow holes of 300 {micro}m (0.012 inch) diameter.

Prasad, Somuri V.; Scharf, Thomas W.

2005-03-01

193

Optical characterization of SiC wafers  

SciTech Connect

Raman spectroscopy has been used to investigate wafers of both 4H-SiC and 6H-SiC. The two-phonon Raman spectra from both 4H- and 6H-SiC have been measured and found to be polytype dependent, consistent with changes in the vibrational density of states. They have observed electronic Raman scattering from nitrogen defect levels in both 4H- and 6H-SiC at room temperature. They have found that electronic Raman scattering from the nitrogen defect levels is significantly enhanced with excitation by red or near IR laser light. These results demonstrate that the laser wavelength is a key parameter in the characterization of SiC by Raman scattering. These results suggest that Raman spectroscopy can be used as a noninvasive, in situ diagnostic for SiC wafer production and substrate evaluation. They also present results on time-resolved photoluminescence spectra of n-type SiC wafers.

Burton, J.C.; Pophristic, M.; Long, F.H.; Ferguson, I.

1999-07-01

194

Effectiveness of the LigaSure Small Jaw Vessel-Sealing System in Hepatic Resection  

PubMed Central

Background In hepatic resection for liver tumors, reducing operation time and blood loss are important for postsurgical complication prevention. This study aimed to compare the safety and efficacy of the LigaSure Small Jaw (Covidien, Boulder, CO) with those of the Cavitation Ultrasonic Surgical Aspirator (CUSA) system (Integra Life Sciences, Plainsboro, NJ) in hepatic surgery. Methods We enrolled 102 patients with liver tumors, of whom 51 underwent liver resection with the CUSA (CUSA group) between March 2004 and April 2011. Another 51 underwent resection with the LigaSure Small Jaw (LS group) between June 2011 and July 2012. We stratified patients by time period depending on the instrument used, and compared operative duration; intraoperative bleeding; and postoperative liver function and complication rate. Results Total operation time (mean ± SD) was significantly shorter in the LS group than in the CUSA group (358.8 ± 91.7 versus 460.6 ± 146.1 min, P < 0.001). Blood loss was not significantly different between the 2 groups. Frequency of postoperative complications was lower, but not significantly, in the LS group. Conclusion The LigaSure Small Jaw may allow a shorter total operative duration than the CUSA device.

Yoshimoto, Miwa; Endo, Kanenori; Hanaki, Takehiko; Watanabe, Joji; Tokuyasu, Naruo; Sakamoto, Teruhisa; Honjo, Soichiro; Hirooka, Yasuaki; Ikeguchi, Masahide

2014-01-01

195

Equipment for On-Wafer Testing From 220 to 325 GHz  

NASA Technical Reports Server (NTRS)

A system of electronic instrumentation, constituting the equivalent of a two-port vector network analyzer, has been developed for use in on-wafer measurement of key electrical characteristics of semiconductor devices at frequencies from 220 to 325 GHz. A prior system designed according to similar principles was reported in Equipment for On-Wafer Testing at Frequencies Up to 220 GHz (NPO-20760), NASA Tech Briefs, Vol. 25, No. 11 (November 2001), page 42. As one would expect, a major source of difficulty in progressing to the present higher-frequency-range system was the need for greater mechanical precision as wavelengths shorten into the millimeter range, approaching the scale of mechanical tolerances of prior systems. The system (see figure) includes both commercial off-the-shelf and custom equipment. As in the system of the cited prior article, the equipment includes test sets that are extended versions of commercial network analyzers that function in a lower frequency range. The extension to the higher frequency range is accomplished by use of custom frequency-extension modules that contain frequency multipliers and harmonic mixers. On-wafer measurement is made possible by waveguide wafer probes that were custom designed and built for this wavelength range, plus an on-wafer calibration substrate designed for use with these probes. In this case, the calibration substrate was specially fabricated by laser milling. The system was used to make the first on-wafer measurements of a semiconductor device in the frequency range from 220 to 320 GHz. Some of the measurement results showed that the device had gain.

Samoska, Lorene; Peralta, Alejandro; Dawson, Douglas; Lee, Karen; Boll, Greg; Oleson, Chuck

2006-01-01

196

Super-flat wafer chucks: from simulation and testing to a complete 300mm wafer chuck with low wafer deformation between pins  

NASA Astrophysics Data System (ADS)

Berliner Glas is a privately owned, mid-sized manufacturer of precision opto-mechanics in Germany. One specialty of Berliner Glas is the design and production of high performance vacuum and electrostatic wafer chucks. Driven by the need of lithography and inspection for smaller overlay values, we pursue the production of an ideally flat wafer chuck. An ideally flat wafer chuck holds a wafer with a completely flat backside and without lateral distortion within the wafer surface. Key parameters in influencing the wafer chucks effective flatness are thermal performance and thermal management, roughness of the surface, choice of materials and the contact area between wafer and wafer chuck. In this presentation we would like to focus on the contact area. Usually this is decreased as much as possible to avoid sticking effects and the chance of trapped particles between the chuck surface and the backside of the wafer. This can be realized with a pin structure on the chuck surface. Making the pins smaller and moving pins further apart from each other makes the contact area ever smaller but also adds new challenges to achieve a flat and undistorted wafer on the chuck. We would like to address methods of designing and evaluating such a pin structure. This involves not only the capability to simulate the ideal pattern of pins on the chuck's surface, for which we will present 2D and 3D simulation results. As well, we would like to share first results of our functional models. Finally, measurement capability has to be ensured, which means improving and further development of Fizeau flatness test interferometers.

Müller, Renate; Afanasiev, Kanstantin; Ziemann, Marcel; Schmidt, Volker

2014-04-01

197

Characterization of mirror-polished silicon wafers by Makyoh method  

NASA Astrophysics Data System (ADS)

Makyoh, the "Magic Mirror" is a very useful tool with which to visualize local irregularities of the surface of a mirror-like polished silicon wafer. Using the Makyoh method, bright and dark spots are visible in the image of wafers projected on an instrument screen. However, these spots have not yet been correlated to specific defects on a wafer surface. First, local convex-type defects on the mirror-like surface of silicon wafers are observed with Makyoh, a flatness tester and other micro surface measurement systems. Next, we report our attempts to create actrual convex and concave shapes on silicon wafer surfaces by intentionally varying polishing conditions, and which shapes are observed. We also discuss the relationship between silicon wafer flatness and the Makyoh magic mirror image.

Tokura, Seitaro; Fujino, Nobukatsu; Ninomiya, Masaharu; Masuda, Kenji

1990-06-01

198

Wafer bonding of gallium arsenide on sapphire  

Microsoft Academic Search

\\u000a $1\\\\overline{1} 02$  ) sapphire in a micro-cleanroom at room temperature under hydrophilic or hydrophobic surface conditions. Subsequent heating\\u000a up to 500 °C increased the bond energy of the GaAs-on-sapphire (GOS) wafer pair close to the fracture energy of the bulk material.\\u000a The bond energy was measured as a function of the temperature. Since the thermal expansion coefficients of GaAs and sapphire\\u000a are close to

P. Kopperschmidt; G. Kästner; S. Senz; D. Hesse; U. Gösele

1997-01-01

199

Wafer-scale synthesis of monodisperse synthetic magnetic multilayer nanorods.  

PubMed

A double exposure technique has been used to fabricate nanoimprint stamps for making monodisperse nanorods with controllable lengths. The nanorod length is defined by a normal photolithography projection process whereas the nanorod width is defined by an edge-lithography process using a soft polydimethylsiloxane (PDMS) contact mask. Taking advantage of edge-lithography, the nanorod width can be less than the diffraction limit of the exposure light. Using these nanorod stamps, synthetic magnetic multilayer (SMM) nanorods have been fabricated using nanoimprint lithography, resulting in a length variation of ?3%. Nanorod magnetic properties have been characterized in both longitudinal and in-plane transverse directions of the nanorods. A theoretical model has been established to explain the magnetic responses and has revealed that both shape anisotropy and interlayer interactions are important in determining the properties of SMM nanorods. PMID:24329003

Zhang, Mingliang; Bechstein, Daniel J B; Wilson, Robert J; Wang, Shan X

2014-01-01

200

Diamond MEMS: wafer scale processing, devices, and technology insertion  

NASA Astrophysics Data System (ADS)

Diamond has long held the promise of revolutionary new devices: impervious chemical barriers, smooth and reliable microscopic machines, and tough mechanical tools. Yet it's been an outsider. Laboratories have been effectively growing diamond crystals for at least 25 years, but the jump to market viability has always been blocked by the expense of diamond production and inability to integrate with other materials. Advances in chemical vapor deposition (CVD) processes have given rise to a hierarchy of carbon films ranging from diamond-like carbon (DLC) to vapor-deposited diamond coatings, however. All have pros and cons based on structure and cost, but they all share some of diamond's heralded attributes. The best performer, in theory, is the purest form of diamond film possible, one absent of graphitic phases. Such a material would capture the extreme hardness, high Young's modulus and chemical inertness of natural diamond. Advanced Diamond Technologies Inc., Romeoville, Ill., is the first company to develop a distinct chemical process to create a marketable phase-pure diamond film. The material, called UNCD® (for ultrananocrystalline diamond), features grain sizes from 3 to 300 nm in size, and layers just 1 to 2 microns thick. With significant advantages over other thin films, UNCD is designed to be inexpensive enough for use in atomic force microscopy (AFM) probes, microelectromechanical machines (MEMS), cell phone circuitry, radio frequency devices, and even biosensors.

Carlisle, J. A.

2009-05-01

201

A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers  

Microsoft Academic Search

As the VLSI manufacturing technology advances into the deep sub-micron (DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which put different dies onto the same set of masks is a good cost-sharing approach. Every design needs to be produced by its desired technology process, such as 1 poly with 4 metal layers

Chien-Chang Chen; Wai-Kei Mak

2006-01-01

202

Micro-miniature gas chromatograph column disposed in silicon wafers  

DOEpatents

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Yu, Conrad M. (Antioch, CA)

2000-01-01

203

The P300: An Approach to Automated Inspection of Patterned Wafers  

NASA Astrophysics Data System (ADS)

As IC groundrules shrink, manual optical inspection of multilevel patterned wafers becomes ineffective if not impossible, and efforts to develop automatic wafer inspection systems have expanded. This paper describes one successful approach, the P300 Automatic Wafer Inspection System[1], which uses a greylevel reference comparison of adjacent cells to locate defects on periodic pattern. The defects may be either pattern anomalies or particulates. Experiments demonstrate that the P300, scanning at a rate significantly faster than a human inspector, finds over ninety percent of half micron defects and over ninety-five percent of defects one micron or larger. By basing the inspection algorithm on a cell-to-cell comparison within a frame, as opposed to the conventional chip to chip or chip to CAD database reference, the system avoids detecting false alarms caused by acceptable variations in reflectivity, film thickness, critical dimensions and overlay registration over the surface of the wafer. A simple cell-to-cell comparison, however, would he prone to detecting false alarms due to electronic and digitization noise, aliasing, vibration, and illumination non-uniformity, as well as small scale acceptable process variation. By adding a statistical test to filter out noise and an edge detector to reduce sensitivity on edges, the false positive rate has been kept below a fraction of a percent of the frames inspected. The paper will discribe the system architecture and inspection algorithms and discuss specific inspection applications.

Brecher, Virginia H.; Bonner, Raymond; Dom, Byron E.

1989-07-01

204

Modeling and fabrication of micro 3K-2-type planetary gear reducer utilizing SU-8 photoresist as alternative LIGA technology  

NASA Astrophysics Data System (ADS)

The LIGA type process, utilizing SU-8 photoresist as alternative LIGA technology, can fabricate high aspect ratio microstructures without employing synchrotron light and suitable X-ray mask. Based on LIGA type process in this paper, detailed investigations of the modeling and fabrication of micro 3K-2 type planetary gear reducer, such as the modeling and design of micro reducer, CAD of micro gear mask, SU-8 UV photolithography, micro electroforming, micro molding, have been performed. And 400 um thickness sun gear, 400 um thickness planet gear, 200 um thickness fixed inner gear, and 200 um thickness rotary inner gear, whose teeth are 15,11,36,39 respectively, have been obtained. Utilizing these gears, the micro reducer whose modulus, outer diameter and velocity ratio are 0.03, 2mm, 44.2:1, has been assembled and applied in (phi) 2mm micro electro magnetic motor successfully.

Zhang, Weiping; Chen, Wenyuan; Chen, Di; Chen, Xiaomei; Wu, Xiaosheng; Xu, Zhengfu

2001-10-01

205

Computational Assessment of the Effects of Temperature on Wafer-Level Component Boards in Drop Tests  

Microsoft Academic Search

The drop reliability of wafer-level chip-scale package (WL-CSP) component boards used in portable devices was studied by employing mechanical shock loads (JESD22-B111 standard) at different temperatures. The drop tests were carried out at room temperature (23 degC), 75 degC, 100 degC, and 125 degC. The elevated temperatures were achieved by integrated heater elements in the components. The number of drops-to-failure

Jue Li; Toni T. Mattila; Jorma K. Kivilahti

2009-01-01

206

Impact of test-fixture forward coupling on on-wafer silicon device measurements  

Microsoft Academic Search

Often, the test-fixture forward coupling is ignored during on-wafer device measurements, although existing de-embedding techniques provide means for addressing its effect. In this work it is demonstrated that large errors may occur if forward coupling is not determined and accounted for. An investigation based on basic scaling properties of MOSFETs is proposed as a benchmark test to partially verify de-embedding

Troels Emil Kolding

2000-01-01

207

A NOVEL METHOD FOR ACHIEVING VERY LOW COPS IN CZ WAFERS  

Microsoft Academic Search

INTRODUCTION: As the IC industry moves toward development of future technology nodes and application of new materials, more innovation is required at the wafer substrate level. The silicon-on-insulator (SOI) technology will be a key factor in extending planar CMOS technologies beyond sub-50nm gate sizes. Many of the process and materials constrains facing continuous device scaling are relaxed or removed for

J. L. Vasat; T. Torack

208

Fine grinding of silicon wafers: effects of chuck shape on grinding marks  

Microsoft Academic Search

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon ingot into wafers. With continuing shrinkage of feature sizes of microchips, more stringent requirement is imposed on wafer flatness. Fine grinding of silicon wafers is a patented technology to produce super flat wafers at a low cost. Six papers on fine grinding were

Wangping Sun; Z. J. Pei; G. R. Fisher

2005-01-01

209

Effect of Substrate Configuration on the Grain Structure and Morphology of Electrodeposited Ni for Prototyping LIGA  

SciTech Connect

Synchrotron X-ray lithographic molding of PMMA-Ti/Cu/Ti substrates has been developed and used in the electrodeposition of Ni microparts for prototype LIGA development at SNL, CA. Alternative molding processes that minimize x-ray beam line use and reduce processing time are of interest for the rapid fabrication of large quantities of microparts. The objective of this investigation is to examine, archive, and compare the grain structure and morphology of deposits produced from four different molding technologies currently under development. We conclude that deposit microstructure and uniformity are greatly influenced by substrate material and design configuration. The findings are summarized.

Nacy Y. C. Yang

2002-07-01

210

Fundamental characteristics of electrostatic wafer chuck with insulating sealant  

Microsoft Academic Search

The electrostatic wafer chuck is the most preferable handling method in advanced semiconductor manufacture. Even in a vacuum environment, it enables not only the ability to retain a wafer flat, but also to enhance heat transfer through the whole surface area because of firm contact. We have investigated the fundamental characteristics of an electrostatic chuck consisting of a pair of

Kyoko Yatsuzuka; Fumikazu Hatakeyama; Kazutoshi Asano; Shinichiro Aonuma

2000-01-01

211

FEA Thermal Investigation of Wafer Thinning by Plasma Etching  

Microsoft Academic Search

In this work, finite element analysis (FEA) was used to predict transient heating and temperature distribution on the wafer surface during plasma etching process as backgrind (BG) tape degradation after plasma stress relief was observed. The wafer surface temperature during plasma process was measured using temperature indicator strips and used as input temperature for FEA analysis. Parametric studies were performed

Foo Lam Wong; Radimin; M. Teo; C. Lee

2006-01-01

212

Submicron defect detection standard for patterned wafer inspection systems  

Microsoft Academic Search

Automated defect detection equipment have been used extensively for patterned wafer inspection in the semiconductor industry. These systems are used to find a variety of patterning and process defects on silicon wafers, before device completion, so that action may be directed toward eliminating the cause of the defects. The method of detection that each type of inspection system uses varies

Daniel V. Grelinger

1992-01-01

213

Alternative facility layouts for semiconductor wafer fabrication facilities  

Microsoft Academic Search

Semiconductor wafer fabrication facilities are widely acknowledged to be among the most complicated industrial systems from a production planning and control point of view. The design of most wafer fabrication facilities has followed the process layout, where similar machines are located together. This feeds to complex, reentrant product flows through the facility. In this paper, we examine the effects on

Christopher D. Geiger; Rieko Hase; Christos G. Takoudis; Reha Uzsoy

1997-01-01

214

Particulate contamination removal from wafers using plasmas and mechanical agitation  

DOEpatents

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Selwyn, Gary S. (Los Alamos, NM)

1998-01-01

215

Piezoelectric Wafer Active Sensor Embedded Ultrasonics in Beams and Plates  

E-print Network

Piezoelectric Wafer Active Sensor Embedded Ultrasonics in Beams and Plates by V. Giurgiutiu, J. Bao and experimental investigation of the fun- damental aspects of using piezoelectric wafer active sensors (PWASs of these results to in situ structural health monitoring using embedded ultrasonics. KEY WORDS--Piezoelectric

Giurgiutiu, Victor

216

Heterodyne polarimetry for measuring critical dimensions on semiconductor wafers  

Microsoft Academic Search

A new optical technique based on heterodyne polarimetry is developed for fast measurement of critical dimensions on semiconductor wafers, particularly on those of memory chips. Sub-wavelength periodical structure of a sample acts as a wire-grid polarizer, making both the amplitude and phase of the reflected laser beam dependent on geometrical dimensions and optical properties of the wafer pattern. The heterodyne

Vladimir V. Protopopov

2008-01-01

217

Development and implementation of an automated wafer transport system  

Microsoft Academic Search

The move to 300 mm wafers has prompted IC manufacturers to demand a reliable automated material handling system (AMHS). Hewlett Packard's Inkjet Supplies Business Unit has worked with a supplier to develop a system using overhead rails and vehicles with hoist mechanisms to perform direct-to-tool delivery of 200 mm podded wafers. The system is intended to increase throughput by providing

J. Sikich

1998-01-01

218

Piezoresistive stress sensors on (110) silicon wafers  

NASA Technical Reports Server (NTRS)

Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

Kang, Y. L.; Suhling, J. C.; Jaeger, R. C.

1992-01-01

219

MAPPER alignment sensor evaluation on process wafers  

NASA Astrophysics Data System (ADS)

MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing. In order to reduce costs and to minimize the footprint of this tool a new alignment sensor has been developed; based on technologies used for DVD optical heads. A wafer with an alignment mark is scanned with the sensor, resulting in an intensity pattern versus position. From this pattern the mark position can be calculated. Evaluations have been made over the performance of this type of sensor using different mark designs at several lithography process steps for FEOL and BEOL manufacturing. It has been shown that sub-nanometer reproducibility (3? std) of alignment mark readings can be achieved while being robust against various process steps.

Vergeer, N.; Lattard, L.; de Boer, G.; Couweleers, F.; Dave, D.; Pradelles, J.; Bustos, J.

2013-03-01

220

Wafer Inspection in the Photolithography Process  

NSDL National Science Digital Library

This is a description for a learning module from Maricopa Advanced Technology Education Center. This PDF describes the module; access may be purchased by visiting the MATEC website. In this module, your learners begin to master the sensitive after develop inspection (ADI) methods that follow photolithography. MATEC describes macro- and micro-inspection techniques and distinguishes qualitative (inspection) from quantitative (metrology) methods. The chief focus is on teaching learners to examine wafers under an optical microscope; a simulated microscope is also provided in a computer-based training (CBT) format. The module covers edge bead inspection and provides extensive practice in flash boundary inspection, including evaluating Nikon crosses, overlay boxes, scanning electronic microscope features, resolution bars, Verniers, and product identification numbers.

2012-12-03

221

Overlay Tolerances For VLSI Using Wafer Steppers  

NASA Astrophysics Data System (ADS)

In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his merchandise appear as attractive as possible, the lithographer is frequently placed in the position of having to explain subtle issues in order to justify his decisions. It is the purpose of this paper to provide that explanation.

Levinson, Harry J.; Rice, Rory

1988-01-01

222

A novel wafer baking system using hot air streams  

NASA Astrophysics Data System (ADS)

This paper presents a novel wafer baking system that uses hot air streams as heating media and achieves good temperature uniformity across the entire wafer surfaces during the baking process. Wind tunnel experiments have been carried out to verify the concept of using hot air streams for wafer baking. A simple prototyping wafer baking system has been designed and fabricated, and experiments of the baking process have been conducted. Good temperature uniformity across the wafer surface has been achieved. The experimental results match well with the computer fluid dynamics (CFD) simulation results. It is observed that the velocity of the airflow has significant influence on the temperature transient responses. Further optimization of the parameters of the baking system and analytical modelling studies are currently under way.

Wang, Lan; Chow, Siew Loong; Loh, Ai Poh; Gong, Zhi Ming; Tan, Woei Wan; Tay, Arthur E. B.; Ho, Weng Khuen

2004-05-01

223

Approaching new metrics for wafer flatness: an investigation of the lithographic consequences of wafer non-flatness  

NASA Astrophysics Data System (ADS)

Flatness of the incoming silicon wafer is one major contributor to the ultimate focusing limitation of modern exposure tools. Exposure tools are designed to chuck wafers without creating non-flatness and then use focus control to follow as closely as possible the chucked wafer front surface topography. The smaller size of the exposure slit in a step-and-scan exposure tool, as compared to the previous generation full-field stepper tool, helps minimize the impact of chucked wafer non-flat topography. However, to maintain high throughput and improve critical dimension uniformity (CDU) at sub-wavelength line-widths requires continuous improvement in the incoming silicon wafer flatness. In this paper we report extensive experimental results that review existing wafer flatness metrics and propose the addition of a new metric. The new metric emulates the scanning motion of exposure by integrating the defocus that each point on the wafer experiences during exposure. We show that this method is in better spatial agreement with measured defocus in step-and-scan exposure tools. Simple metrics of moving average (MA) defocus prediction analysis will be defined and shown to correlate very well to post exposure defocus data. These experiments were enabled by the creation of special 300-nm wafers by MEMC. These special wafers include sites with a wide variation in flatness. Prior to exposure the wafers were measured with a high-resolution optical flatness metrology tool (WaferSight by ADE) to obtain industry standard thickness variation (flatness) data. Incoming wafer flatness data is used to predict wafer suitability for lithography at the desired device geometry node (e.g., 90 nm). The flatness data was processed and characterized using both standard metrics (SFQR) and the new MA analysis. The relationship between the industry standard metric (SFQR) and similar metrics applied to MA analysis will be presented. Full two-dimensional maps are used to present spatial correlations and permit simple physical insights into the flatness data sets. Measurements of chucked wafer flatness were made on the same wafers using ASML TWINSCAN in-line metrology. These measurements correlate very well to thickness-based flatness. Un-chucked wafer flatness metrics (SFQR and MA) are shown to correlate well to post exposure defocus data when an appropriate site size is used. This result is discussed in relationship to the industry-accepted practice of specifying un-chucked wafer flatness. Lithography performance tests were made to prove the relevance of the different flatness metrics. The same special wafers are used for lithography performance tests. These tests achieve excellent correlation between post-exposure full-wafer focus control results and predictions based on both SFQ (industry standard) and MA re-mapping of the flatness data. The relationship between measured critical dimension (CD) and defocus is also explored. Point-by-point analysis of CD residual versus measured defocus data nicely follows a Bossung curve. We also show that residual CD values predicted from defocus correlate well with measured values. These experiments confirm the application of industry standard wafer flatness measurements to step-and-scan lithography when appropriately using current metrics. They also present the potential for improved metrics based on the MA defocus prediction analysis to help drive continuous improvement of wafer flatness for advanced step-and-scan lithography.

Valley, John F.; Poduje, Noel; Sinha, Jaydeep; Judell, Neil; Wu, Jie; Boonman, Marc; Tempelaars, Sjef; van Dommelen, Youri; Kattouw, Hans; Hauschild, Jan; Hughes, William; Grabbe, Alexis; Stanton, Les

2004-05-01

224

A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers  

Microsoft Academic Search

As the VLSI manufacturing technology advances into the deep sub-micron(DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which put different dies onto the same set of masks is a good cost-sharing approach. Every design needs to be produced by its desired technology process, such as 1 poly with 4 metal layers (1P4M),

Chien-chang Chen; Wai-kei Mak

2006-01-01

225

Mechanical and metallographic characterization of LIGA fabricated nickel and 80%Ni-20%Fe Permalloy  

SciTech Connect

A table top servohydraulic load frame equipped with a laser displacement measurement system was constructed for the mechanical characterization of LIGA fabricated electroforms. A drop in tensile specimen geometry which includes a pattern to identify gauge length via laser scanning has proven to provide a convenient means to monitor and characterize mechanical property variations arising during processing. In addition to tensile properties, hardness and metallurgical data were obtained for nickel deposit specimens of current density varying between 20 and 80 mA/cm{sup 2} from a sulfamate based bath. Data from 80/20 nickel-iron deposits is also presented for comparison. As expected, substantial mechanical property differences from bulk metal properties are observed as well as a dependence of material strength on current density which is supported by grain size variation. While elastic modulus values of the nickel electrodeposit are near 160 GPa, yield stress values vary by over 60%. A strong orientation in the metal electrodeposits as well as variations in nucleating and growth morphology present a concern for anisotropic and geometry dependent mechanical properties within and between different LIGA components.

Christenson, T.R.; Buchheit, T.E.; Schmale, D.T. [Sandia National Labs., Albuquerque, NM (United States); Bourcier, R.J. [Corning Inc., NY (United States). Photonic Technologies Div.

1998-04-13

226

Comparison of physical and technical performance in European soccer match-play: FA Premier League and La Liga  

Microsoft Academic Search

The aim of this study was to compare match performance in professional soccer players across two major European championships: Spanish La Liga and English FA Premier League (FAPL). Data were collected using a computerized match analysis system. A total of 5938 analyses were recorded during the 2006–2007 season. The players were classified into six positional roles: central defenders, full backs,

Alexandre Dellal; Karim Chamari; Del P. Wong; Said Ahmaidi; Dominique Keller; Ricardo Barros; Gian Nicola Bisciotti; Christopher Carling

2011-01-01

227

Impact of chuck flatness on wafer distortion and stepper overlay  

NASA Astrophysics Data System (ADS)

Overlay accuracy is known as one of the most important subjects for ULSI device production. Significant contributions such as alignment accuracy and mask distortions are well known. By breaking the 100 nm range on overlay accuracy a number of influences have to take into account, which were usually neglected for relaxed design rules. One of these influences to the overlay is directly related to wafer distortions induced by flatness deviations of wafer chucks. This impact was characterized by investigating the elastic behavior of 4' wafers (525 micrometers thick), fixed on a wafer chuck. Induced elastical deformation due to flatness error of the chuck causes strains and elongations in the wafer surface and therefore wafer distortions. The results obtained by exposure experiments and calculations show that even a point size defect has a 30 mm spreading. Therefore the induced distortions arrives about 100 nm in case of a 3 micrometers flatness irregularity. The final result of the investigations induces that the flatness differences between different wafer chucks or steppers should be smaller than 1 micrometers for design rules below quarter micron.

Simon, Klaus; Scheunemann, H.-U.; Huber, Hans L.; Gabeli, F.

1993-06-01

228

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.  

PubMed

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. PMID:24700434

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

229

The uses of Man-Made diamond in wafering applications  

NASA Technical Reports Server (NTRS)

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Fallon, D. B.

1982-01-01

230

On-Wafer Testing of Circuits Through 220 GHz  

NASA Technical Reports Server (NTRS)

We have jointly developed the capability to perform on-wafer s-parameter and noise figure measurements through 220 GHz. S-parameter test sets have been developed covering full waveguide bands of 90-140 GHz (WR-08) and 140-220 GHz (WR-05). The test sets have been integrated with coplanar probes to allow accurate measurements on-wafer. We present the design and performance of the test sets and wafer probes. We also present calibration data as well as measurements of active circuits at frequencies as high as 215 GHz.

Gaier, Todd; Samoska, Lorene; Oleson, Charles; Boll, Greg

1999-01-01

231

ELID supported grinding of thin sapphire wafers  

NASA Astrophysics Data System (ADS)

Sapphire material is, due to its crystal structure, difficult to machine in an economic way. There is a request for thin, i.e. below 0.2 mm thickness, sub surface damage free wafers to produce sensor elements. ELID -- electrolytic in process dressing -- is an innovative high end grinding technology, using small grain sizes, which enable to manufacture surfaces in a quality that is close to polished. ELID grinding requires exactly aligned machining parameters of the grinding process. To grind sapphire the material's behavior is additionally to be considered. Studies on the necessary oxide layer on the grinding wheel and influences on its build-up process will be presented. The presentation shows the results of comparing grinding experiments on different -- c-plane and r-plane -- sapphire materials. Different tool specifications are used. Infeed and grinding velocity are varied and the results on wear, removal rate and surface quality are shown. The process parameters the stiffness of the machine, the grinding forces and pressure are evaluated. The ELID grinding is compared in its results to conventional grinding steps. The material removal rate on sapphire is relatively small due to the extreme hardness of sapphire. The achieved excellent surface roughness will be discussed.

Makarenko, Igor; Vogt, Christian; Rascher, Rolf; Sperber, Peter; Stirner, Thomas

2010-10-01

232

Arthroscopic Wafer Procedure for Ulnar Impaction Syndrome  

PubMed Central

Ulnar impaction syndrome is abutment of the ulna on the lunate and triquetrum that increases stress and load, causing ulnar-sided wrist pain. Typically, ulnar-positive or -neutral variance is seen on a posteroanterior radiograph of the wrist. The management of ulnar impaction syndrome varies from conservative, symptomatic treatment to open procedures to shorten the ulna. Arthroscopic management has become increasingly popular for management of ulnar impaction with ulnar-positive variance of less than 3 mm and concomitant central triangular fibrocartilage complex tears. This method avoids complications associated with open procedures, such as nonunion and symptomatic hardware. The arthroscopic wafer procedure involves debridement of the central triangular fibrocartilage complex tear, along with debridement of the distal pole of the ulna causing the impaction. Debridement of the ulna arthroscopically is taken down to a level at which the patient is ulnar neutral or slightly ulnar negative. Previous studies have shown good results with relief of patient symptoms while avoiding complications seen with open procedures. PMID:24749031

Colantoni, Julie; Chadderdon, Christopher; Gaston, R. Glenn

2014-01-01

233

9nm node wafer defect inspection using visible light  

NASA Astrophysics Data System (ADS)

Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

Zhou, Renjie; Edwards, Chris; Popescu, Gabriel; Goddard, Lynford L.

2014-04-01

234

Laser induced stress wave thermometry applied to silicon wafer processing  

E-print Network

-mechanical properties of single crystal silicon wafers, specifically with respect to ultrasound propagation in the waveguide. The objective is to identify and quantify characteristics of interrogating ultrasonic waves which can be used as a temperature diagnostic...

Rabroker, George Andrew

2012-06-07

235

Wafer bonding : mechanics-based models and experiments  

E-print Network

Direct wafer bonding has emerged as an important technology in the manufacture of silicon-on-insulator substrates (SOI), microelectromechanical systems (MEMS), and three-dimensional integrated circuits (3D IC's). While the ...

Turner, Kevin Thomas, 1977-

2004-01-01

236

Wafer cooling for a high current serial ion implantation system  

Microsoft Academic Search

This paper investigates performance of a gas-cooled, low temperature electrostatic chuck and the effects of gas injection radius change on the wafer cooling efficiency. Wafer temperature measurements were taken for two new electro-static chuck designs at different gas cooling pressures during high current ion implantation. Typical input beam power density was 1.3 W\\/cm2. An improvement in cooling performance was achieved

Svetlana B. Radovanov; Steven R. Walther; Edward Evans; Jon Ballou; Nicholas R. White; William Frutiger

1999-01-01

237

ESFI-SOS transistors on as-grown sapphire wafers  

Microsoft Academic Search

The possibility to grow the silicon film on an as-grown substrate rather than on a mechanically processed substrate is considered. The concept is implemented with the aid of sapphire wafers obtained by the edge-defined film-fed growth (EFG) technique. The wafers are ground on one side only, the other side remaining as an as-grown substrate. The principal advantage of the use

H. Splittgerber; D. Takacs; H. Schloetterer

1977-01-01

238

Thermal stresses in 3D IC inter-wafer interconnects  

Microsoft Academic Search

We present a finite element based analysis to determine if thermally induced stresses in inter-wafer Cu via structures in 3D ICs using BCB-bonded wafers is a potential reliability problem. Experimental information on thermal stresses or stress-induced failures of 3D ICs is not available in the literature. Therefore we first partially validate our approach by comparing computed results against experimental data

Jing Zhang; Max O. Bloomfield; Jian-Qiang Lu; Ronald J. Gutmann; Timothy S. Cale

2005-01-01

239

Characterization of acoustomigration with on-wafer measurement system  

Microsoft Academic Search

Developed an automated on-wafer measurement system and a suitable test device for the design-independent characterization of different metallization layers on piezoelectric substrates with respect to acoustomigration. With the measurement system we are able to measure the devices on the wafer without any additional manual handling. The test devices were fabricated on LiTaO3 with Al and AlCu electrodes. The temperature and

G. Raml; W. Ruile; A. Springer; R. Weigel

2001-01-01

240

Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications  

NASA Astrophysics Data System (ADS)

Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

2012-11-01

241

Nanoscale friction and wear properties of silicon wafer under different lubrication conditions  

NASA Astrophysics Data System (ADS)

The nanoscale friction and wear properties of single crystal silicon wafer under different lubrication conditions are studied in this paper. The experiments were performed with Si3N4 ball sliding on the surface of silicon wafer under four different lubrication conditions: dry friction, water lubrication, hydrogen peroxide lubrication and the static hydrogen peroxide dry friction. The results from the experiments have been analyzed showing the different friction and wear properties of the silicon wafer in different lubrication conditions. It is concluded that the wear rates under the water lubrication and under the hydrogen peroxide lubrication are both small, the chemical reactions are facilitated by the mechanical processes when the load and the sliding speed reach certain levels. This is mainly resulted by the enhanced lubricant performance with the formed silicon hydroxide Si(OH)4 film. Under the water lubrication, the wear is found in a way of material removed in molecule scale. Under the hydrogen peroxide lubrication, the wear is mainly caused by the spalling of micro-cracks. Under the dry friction condition, the wear is found being adhesive wear. And under the static peroxide dry friction, the wear is prevailing adhesive wear. These results are essential and valuable to the development of the efficient and environmental-friendly slurry for the chemical mechanical polishing (CMP) process.

Chen, Xiaochun; Zhao, Yongwu; Wang, Yongguang; Zhou, Hailan; Ni, Zhifeng; An, Wei

2013-10-01

242

Porous silicon optical microcavity biosensor on silicon-on-insulator wafer for sensitive DNA detection.  

PubMed

Silicon-on-insulator (SOI) wafer is one of the most appealing platforms for optical integrated circuit with the potential to realize high performance Ultra Large Scale Integration (ULSI) and device miniaturization. In this work, based on simulations to obtain appropriate optical properties of a porous silicon microcavity (PSM), we successfully fabricated a highly efficient PSM on SOI wafer by electrochemical etching for DNA detection at optical wavelength 1555.0 nm. The narrow resonance peak with a full width at half maximum about 26.0 nm in the reflectance spectrum gives a high Q factor which causes high sensitivity for sensing performance. The sensitivity of this sensor is investigated through 19-base pair DNA hybridization in the PSM by surface modification using a standard cross link chemistry method. The red shift of the reflectance spectra shows a good linear relationship with complementary DNA concentration, ranging from 0.625 to 12.500 ?M, and the detection limit is 43.9 nM. This optical PSM on SOI is highly sensitive, fast responsive, easy to fabricate and low-costly, that will broadly benefit to develop a new optical label-free biosensor on SOI wafer and has a great potential for biochips based on integrated optical devices. PMID:23395728

Zhang, Hongyan; Jia, Zhenhong; Lv, Xiaoyi; Zhou, Jun; Chen, Liangliang; Liu, Rongxia; Ma, Ji

2013-06-15

243

An air-flow based wafer bake system for improved temperature uniformity  

Microsoft Academic Search

This paper presents an innovative apparatus for wafer baking\\/chilling using a stream of temperature controlled air-flow. This apparatus takes the form of a baking chamber on which the wafer is placed. A stream of hot air is passed through the chamber below the wafer. Heat is transferred from the hot air to the wafer from the bottom surface of the

Lan Wang; Ai Poh Loh; Zhi Ming Gong; Siew Loong Chow

2008-01-01

244

Electrochemical method for defect delineation in silicon-on-insulator wafers  

SciTech Connect

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, T.R.; Jones, D.T.H.; Kelly, M.J.; Medernach, J.W.; Stevenson, J.O.; Tsao, S.S.

1990-01-01

245

Electrochemical method for defect delineation in silicon-on-insulator wafers  

SciTech Connect

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, T.R.; Jones, D.T.H.; Kelly, M.J.; Medernach, J.W.; Stevenson, J.O.; Tsao, S.S.

1990-12-31

246

High temperature materials for thin-film thermocouples on silicon wafers  

Microsoft Academic Search

We have developed an instrumented calibration wafer for radiometric temperature measurements in rapid thermal processing (RTP) tools for semiconductor processing. The instrumented wafers have sputter deposited thin-film thermocouples to minimize the thermal disturbance of the wafer by the sensors. The National Institute of Standards and Technology (NIST) calibration wafer also employs platinum–palladium wire thermocouples to achieve a combined standard uncertainty

Kenneth G Kreider; Greg Gillen

2000-01-01

247

Strategy and metrics for wafer handling automation in legacy semiconductor fab  

Microsoft Academic Search

We present a systematic approach for converting a legacy wafer fab from manual wafer handling to fully automatic wafer handling. Our strategy began by quantifying the need for automation in terms of impact on die yield, identifying a seven percent die loss associated with scratches from wafer handling. We then addressed the fundamental changes in production equipment and processes as

R. L. Guldi; D. E. Paradis; M. T. Whitfield; F. D. Poag; D. P. Jensen

1999-01-01

248

Oral Immunization with Escherichia coli Expressing a Lipidated Form of LigA Protects Hamsters against Challenge with Leptospira interrogans Serovar Copenhageni  

PubMed Central

Leptospirosis is a potentially fatal zoonosis transmitted by reservoir host animals that harbor leptospires in their renal tubules and shed the bacteria in their urine. Leptospira interrogans serovar Copenhageni transmitted from Rattus norvegicus to humans is the most prevalent cause of urban leptospirosis. We examined L. interrogans LigA, domains 7 to 13 (LigA7-13), as an oral vaccine delivered by Escherichia coli as a lipidated, membrane-associated protein. The efficacy of the vaccine was evaluated in a susceptible hamster model in terms of the humoral immune response and survival from leptospiral challenge. Four weeks of oral administration of live E. coli expressing LigA7-13 improved survival from intraperitoneal (i.p.) and intradermal (i.d.) challenge by L. interrogans serovar Copenhageni strain Fiocruz L1-130 in Golden Syrian hamsters. Immunization with E. coli expressing LigA7-13 resulted in a systemic antibody response, and a significant LigA7-13 IgG level after the first 2 weeks of immunization was completely predictive of survival 28 days after challenge. As in previous LigA vaccine studies, all immunized hamsters that survived infection had renal leptospiral colonization and histopathological changes. In summary, an oral LigA-based vaccine improved survival from leptospiral challenge by either the i.p. or i.d. route. PMID:24478102

Lourdault, Kristel; Wang, Long-Chieh; Vieira, Ana; Matsunaga, James; Melo, Rita; Lewis, Michael S.; Gomes-Solecki, Maria

2014-01-01

249

Oral immunization with Escherichia coli expressing a lipidated form of LigA protects hamsters against challenge with Leptospira interrogans serovar Copenhageni.  

PubMed

Leptospirosis is a potentially fatal zoonosis transmitted by reservoir host animals that harbor leptospires in their renal tubules and shed the bacteria in their urine. Leptospira interrogans serovar Copenhageni transmitted from Rattus norvegicus to humans is the most prevalent cause of urban leptospirosis. We examined L. interrogans LigA, domains 7 to 13 (LigA7-13), as an oral vaccine delivered by Escherichia coli as a lipidated, membrane-associated protein. The efficacy of the vaccine was evaluated in a susceptible hamster model in terms of the humoral immune response and survival from leptospiral challenge. Four weeks of oral administration of live E. coli expressing LigA7-13 improved survival from intraperitoneal (i.p.) and intradermal (i.d.) challenge by L. interrogans serovar Copenhageni strain Fiocruz L1-130 in Golden Syrian hamsters. Immunization with E. coli expressing LigA7-13 resulted in a systemic antibody response, and a significant LigA7-13 IgG level after the first 2 weeks of immunization was completely predictive of survival 28 days after challenge. As in previous LigA vaccine studies, all immunized hamsters that survived infection had renal leptospiral colonization and histopathological changes. In summary, an oral LigA-based vaccine improved survival from leptospiral challenge by either the i.p. or i.d. route. PMID:24478102

Lourdault, Kristel; Wang, Long-Chieh; Vieira, Ana; Matsunaga, James; Melo, Rita; Lewis, Michael S; Haake, David A; Gomes-Solecki, Maria

2014-02-01

250

Scales  

ScienceCinema

Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain ? a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

Murray Gibson

2010-01-08

251

Performance Evaluation for Electrical Plate Lead-free Solder Bumping on Sapphire Wafers  

Microsoft Academic Search

Electrical plating lead-free solder bumping process is quite common for silicon wafers in semiconductor industry, while for sapphire wafers there are still some technical issues to be encountered. Bumped wafer of unreasonable bumping structure has always been found bumps knocked-off after wafer singulation process which is a three-point breaking. Triple higher residual stress may be accumulated on sapphire wafer surface

Y. J. Zhiyuan

2007-01-01

252

Evaluating the 300 mm wafer-handling task in semiconductor industry  

Microsoft Academic Search

The semiconductor industry is moving from the production of 200mm wafers to 300mm wafers. With the increase in wafer size, the workload of wafer handling tasks is also increasing. This study evaluated the operator's handling capability, and the risk of having musculoskeletal disorders (MSDs) for handling 300mm wafers. Twenty-four female operators from a semiconductor manufacturing company participated in the experiment.

Mao-Jiun J. Wang; Hsiu-Chen Chung; Hsin-Chieh Wu

2004-01-01

253

Gate-Oxide-Integrity Characteristics of Vacancy-rich Wafer Compared with Crystal-Originated-Pits-free Wafer as a Function of Oxide Thickness  

Microsoft Academic Search

The dielectric breakdown of oxides with various thickness between 5-70 nm on Czochralski (CZ)-grown silicon wafer had been investigated. To observe the effects of crystal-originated-particle (COP), vacancy-rich wafers and COP-free wafers were compared. In breakdown voltage (BV) measurement, breakdown fractions of vacancy-rich wafers were increased with the increase of oxide thickness (tOX) and showed a maximum value at the tOX

Ki-Sang Lee; Won-Ju Cho; Bo-Young Lee; Hak-Do Yoo

2000-01-01

254

Effect of post-growth annealing on the optical properties of LiGaS2 nonlinear crystals  

NASA Astrophysics Data System (ADS)

High chalcogen volatility and Li interaction with the container walls result in variation of crystal composition and presence of both extended and point defects in as-grown LiGaS2 nonlinear crystals. Annealing in appropriate conditions is used to correct the composition and improve the optical quality. We annealed LiGaS2 in vacuum, in the presence of Li2S, Ga2S3, and S, and studied changes in transmission, photoluminescence and photo-induced absorption. OH groups, S-H and S-S complexes, sulfur vacancies and cation antisite defects (GaLi) are most important. Photo-induced absorption is reversible: It appears after illumination with UV/blue light and disappears after illumination with IR light or by heating the sample.

Yelisseyev, Alexander; Starikova, Marina; Isaenko, Ludmila; Lobanov, Sergei; Petrov, Valentin

2011-03-01

255

40 Gbit/s silicon modulators fabricated on 200-mm and 300-mm SOI wafers  

NASA Astrophysics Data System (ADS)

We present 40 Gbit/s optical modulators based on different types of phase shifters (lateral pn, pipin, and interleaved pn junction phase). Those structures were processed both on 200 and 300mm SOI wafers, available in large-scale microelectronic foundries. Both Ring Resonators (RR) and Mach Zehnder (MZ) modulators were fabricated. As an example, MZ modulator based on 0.95 mm long interleaved pn junction phase shifter delivered a high ER of 7.8 dB at 40 Gbit/s with low optical loss of only 4 dB. Ring modulator was also fabricated and characterized at high-speed, exhibiting 40 Gbit/s.

Marris-Morini, Delphine; Baudot, Charles; Fédéli, Jean-Marc; Rasigade, Gilles; Vuillet, Nathalie; Souhaité, Aurélie; Ziebell, Melissa; Rivalin, Pierette; Olivier, Ségolène; Crozat, Paul; Bouville, David; Menezo, Sylvie; Boeuf, Frédéric; Vivien, Laurent

2014-03-01

256

100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices  

SciTech Connect

A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

OLIVER,ANDREW D.; MATZKE,CAROLYN M.

2000-04-06

257

Surface quality of silicon wafer improved by hydrodynamic effect polishing  

NASA Astrophysics Data System (ADS)

Differing from the traditional pad polishing, hydrodynamic effect polishing (HEP) is non-contact polishing with the wheel floated on the workpiece. A hydrodynamic lubricated film is established between the wheel and the workpiece when the wheel rotates at a certain speed in HEP. Nanoparticles mixed with deionized water are employed as the polishing slurry, and with action of the dynamic pressure, nanoparticles with high chemisorption due to the high specific surface area can easily reacted with the surface atoms forming a linkage with workpiece surface. The surface atoms are dragged away when nanoparticles are transported to separate by the flow shear stress. The development of grand scale integration put extremely high requirements on the surface quality on the silicon wafer with surface roughness at subnanometer and extremely low surface damage. In our experiment a silicon sample was processed by HEP, and the surface topography before and after polishing was observed by the atomic force microscopy. Experiment results show that plastic pits and bumpy structures on the initial surface have been removed away clearly with the removal depth of 140nm by HEP process. The processed surface roughness has been improved from 0.737nm RMS to 0.175nm RMS(10?m×10?m) and the section profile shows peaks of the process surface are almost at the same height. However, the machining ripples on the wheel surface will duplicate on the silicon surface under the action of the hydrodynamic effect. Fluid dynamic simulation demonstrated that the coarse surface on the wheel has greatly influence on the distribution of shear stress and dynamic pressure on the workpiece surface.

Peng, Wenqiang; Guan, Chaoliang; Li, Shengyi

2014-08-01

258

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?  

NASA Astrophysics Data System (ADS)

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Green, Martin A.

2014-03-01

259

Chip-Scale Quadrupole Mass Filters for Portable Mass Spectrometry  

E-print Network

We report the design, fabrication, and characterization of a new class of chip-scale quadrupole mass filter (QMF). The devices are completely batch fabricated using a wafer-scale process that integrates the quadrupole ...

Cheung, Kerry

260

Characterizing SOI Wafers By Use Of AOTF-PHI  

NASA Technical Reports Server (NTRS)

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

261

Wafer Fusion for Integration of Semiconductor Materials and Devices  

SciTech Connect

We have developed a wafer fusion technology to achieve integration of semiconductor materials and heterostructures with widely disparate lattice parameters, electronic properties, and/or optical properties for novel devices not now possible on any one substrate. Using our simple fusion process which uses low temperature (400-600 C) anneals in inert N{sub 2} gas, we have extended the scope of this technology to examine hybrid integration of dissimilar device technologies. As a specific example, we demonstrate wafer bonding vertical cavity surface emitting lasers (VCSELs) to transparent AlGaAs and GaP substrates to fabricate bottom-emitting short wavelength VCSELs. As a baseline fabrication technology applicable to many semiconductor systems, wafer fusion will revolutionize the way we think about possible semiconductor devices, and enable novel device configurations not possible by epitaxial growth.

Choquette, K.D.; Geib, K.M.; Hou, H.Q.; Allerman, A.A.; Kravitz, S.; Follstaedt, D.M.; Hindi, J.J.

1999-05-01

262

Meta-analysis of stapled hemorrhoidopexy vs LigaSure hemorrhoidectomy  

PubMed Central

AIM: To compare outcome of stapled hemorrhoidopexy (SH) vs LigaSure hemorrhoidectomy (LH) by a meta-analysis of available randomized controlled trials (RCTs). METHODS: Databases, including PubMed, EMBASE, the Cochrane Library, and the Science Citation Index updated to December 2012, were searched. The main outcomes measured were operating time, early postoperative pain, postoperative urinary retention and bleeding, wound problems, gas or fecal incontinence, anal stenosis, length of hospital stay, residual skin tags, prolapse, and recurrence. The meta-analysis was performed using the free software Review Manager. Differences observed between the two groups were expressed as the odds ratio (OR) with 95%CI. A fixed-effects model was used to pool data when statistical heterogeneity was not present. If statistical heterogeneity was present (P < 0.05), a random-effects model was used. RESULTS: The initial search identified 10 publications. After screening, five RCTs published as full articles were included in this meta-analysis. Among the five studies, all described a comparison of the patient baseline characteristics and showed that there was no statistically significant difference between the two groups. Although most of the analyzed outcomes were similar between the two operative techniques, the operating time for SH was significantly longer than for LH (P < 0.00001; OR= -6.39, 95%CI: -7.68 - -5.10). The incidence of residual skin tags and prolapse was significantly lower in the LH group than in the SH group [2/111 (1.8%) vs 16/105 (15.2%); P = 0.0004; OR= 0.17, 95%CI: 0.06-0.45). The incidence of recurrence after the procedures was significantly lower in the LH group than in the SH group [2/173 (1.2%) vs 13/174 (7.5%); P = 0.003; OR= 0.21, 95%CI: 0.07-0.59]. CONCLUSION: Both SH and LH are probably equally valuable techniques in modern hemorrhoid surgery. However, LigaSure might have slightly favorable immediate postoperative results and technical advantages. PMID:23922480

Yang, Jun; Cui, Pei-Jing; Han, Hua-Zhong; Tong, Da-Nian

2013-01-01

263

Wafer heating mechanisms in a molecular gas, inductively coupled plasma: in situ, real time wafer surface measurements and three-dimensional thermal modeling  

SciTech Connect

The authors report measurements and modeling of wafer heating mechanisms in an Ar/O{sub 2} inductively coupled plasma (ICP). The authors employed a commercially available on-wafer sensor system (PlasmaTemp developed by KLA-Tencor) consisting of an on-board electronics module housing battery power and data storage with 30 temperature sensors embedded onto the wafer at different radial positions. This system allows for real time, in situ wafer temperature measurements. Wafer heating mechanisms were investigated by combining temperature measurements from the PlasmaTemp sensor wafer with a three-dimensional heat transfer model of the wafer and a model of the ICP. Comparisons between pure Ar and Ar/O{sub 2} discharges demonstrated that two additional wafer heating mechanisms can be important in molecular gas plasmas compared to atomic gas discharges. The two mechanisms are heating from the gas phase and O-atom surface recombination. These mechanisms were shown to contribute as much as 60% to wafer heating under conditions of low bias power. This study demonstrated how the 'on-wafer' temperature sensor not only yields a temperature profile distribution across the wafer, but can be used to help determine plasma characteristics, such as ion flux profiles or plasma processing temperatures.

Titus, M. J.; Graves, D. B. [Department of Chemical Engineering, University of California, Berkeley, California 94720 (United States)

2008-09-15

264

Optical transitions due to native defects in nonlinear optical crystals LiGaS2  

NASA Astrophysics Data System (ADS)

LiGaS2 (LGS) is a recently developed nonlinear optical crystal widely used for nonlinear conversion in the mid-infrared spectral region, but its applications are significantly influenced by the native defects present in the lattice. In this work, absorption and photoluminescence (PL) spectra are studied after annealing the as-grown LGS crystal in different chemical environments in order to reveal features related to anion vacancy (VS) and cation antisite defect (GaLi). In addition, irradiation with fast electrons produces VS centers and their complexes in LGS. The VS migration and mutual transformations in these defects take place at room temperature whereas their complete annealing occurs at 670 K. Meanwhile, the first-principles calculations are adopted to identify the relevant optical transitions. A good agreement with the experimental results was obtained. It is established that the dominant defects VS result in the optical absorption at 3.43 eV and violet PL emission, while GaLi is responsible for absorption at 2.95 eV. The intense PL peak at 1.92 eV is associated with the self-trapped excitons in LGS. The other weak PL bands are also related to the recombination of electrons or holes with the VS and GaLi defect states.

Yelisseyev, A.; Lin, Z. S.; Starikova, M.; Isaenko, L.; Lobanov, S.

2012-06-01

265

Optical transitions due to native defects in nonlinear optical crystals LiGaS2  

NASA Astrophysics Data System (ADS)

LiGaS2 (LGS) is a recently developed nonlinear optical crystal widely used for nonlinear conversion in the mid-infrared spectral region, but its applications are significantly influenced by the native defects present in the lattice. In this work, absorption and photoluminescence (PL) spectra are studied after annealing the as-grown LGS crystal in different chemical environments in order to reveal features related to anion vacancy (VS) and cation antisite defect (GaLi). In addition, irradiation with fast electrons produces VS centers and their complexes in LGS. The VS migration and mutual transformations in these defects take place at room temperature whereas their complete annealing occurs at 670 K. Meanwhile, the first-principles calculations are adopted to identify the relevant optical transitions. A good agreement with the experimental results was obtained. It is established that the dominant defects VS result in the optical absorption at 3.43 eV and violet PL emission, while GaLi is responsible for absorption at 2.95 eV. The intense PL peak at 1.92 eV is associated with the self-trapped excitons in LGS. The other weak PL bands are also related to the recombination of electrons or holes with the VS and GaLi defect states.

Yelisseyev, A.; Lin, Z. S.; Starikova, M.; Isaenko, L.; Lobanov, S.

2012-05-01

266

Electronic properties of orthorhombic LiGaS2 and LiGaSe2  

NASA Astrophysics Data System (ADS)

We report theoretical calculations of the band structure and density of states for orthorhombic LiGaS2 (LGS) and LiGaSe2 (LGSe). These calculations are based on the full potential linear augmented plane wave (FP-LAPW) method within a framework of density functional theory. Our calculations show that these crystals have similar band structures. The valence band maximum (VBM) and the conduction band minimum (CBM) are located at ?, resulting in a direct energy band gap. The VBM is dominated by S/Se-p and Li-p states, while the CBM is dominated by Ga-s, S/Se-p and small contributions of Li-p and Ga-p. From the partial density of states we find that Li-p hybridizes with Li-s below the Fermi energy ( E F), while Li-s/p hybridizes with Ga-p below and above E F. Also, we note that S/Se-p hybridizes with Ga-s below and above E F.

Reshak, Ali H.; Auluck, S.; Kityk, I. V.; Al-Douri, Y.; Khenata, R.; Bouhemadou, A.

2009-02-01

267

Toward 300 mm Wafer-Scalable High-Performance Polycrystalline Chemical Vapor Deposited Graphene Transistors.  

PubMed

The largest applications of high-performance graphene will likely be realized when combined with ubiquitous Si very large scale integrated (VLSI) technology, affording a new portfolio of "back end of the line" devices including graphene radio frequency transistors, heat and transparent conductors, interconnects, mechanical actuators, sensors, and optical devices. To this end, we investigate the scalable growth of polycrystalline graphene through chemical vapor deposition (CVD) and its integration with Si VLSI technology. The large-area Raman mapping on CVD polycrystalline graphene on 150 and 300 mm wafers reveals >95% monolayer uniformity with negligible defects. About 26?000 graphene field-effect transistors were realized, and statistical evaluation indicates a device yield of ?74% is achieved, 20% higher than previous reports. About 18% of devices show mobility of >3000 cm(2)/(V s), more than 3 times higher than prior results obtained over the same range from CVD polycrystalline graphene. The peak mobility observed here is ?40% higher than the peak mobility values reported for single-crystalline graphene, a major advancement for polycrystalline graphene that can be readily manufactured. Intrinsic graphene features such as soft current saturation and three-region output characteristics at high field have also been observed on wafer-scale CVD graphene on which frequency doubler and amplifiers are demonstrated as well. Our growth and transport results on scalable CVD graphene have enabled 300 mm synthesis instrumentation that is now commercially available. PMID:25198884

Rahimi, Somayyeh; Tao, Li; Chowdhury, Sk Fahad; Park, Saungeun; Jouvray, Alex; Buttress, Simon; Rupesinghe, Nalin; Teo, Ken; Akinwande, Deji

2014-10-28

268

A through-wafer interconnect in silicon for RFICs  

Microsoft Academic Search

In order to minimize ground inductance in RFICs, we have developed a high-aspect ratio, through-wafer interconnect (or substrate via) in silicon that features a silicon nitride barrier liner and completely filled Cu core. We have fabricated vias with a nominal aspect ratio of 30 and verified the integrity of the insulating liner in vias with an aspect ratio of eight.

Joyce H. Wu; Jörg Scholvin; Jesús A. del Alamo

2004-01-01

269

Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence  

E-print Network

Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence H. C. Sio, Z-mediated nonclassical crystal growth of sodium fluorosilicate nanowires and nanoplates AIP Advances 1, 042165 (2011) Crystal phase and growth orientation dependence of GaAs nanowires on NixGay seeds via vapor

270

Thermomechanical global response of the EUVL wafer during exposure  

Microsoft Academic Search

Extreme ultraviolet lithography (EUVL) is one of the leading technologies for Next-Generation Lithography. Continued progress in its development will be facilitated by characterizing all sources of distortion in the chip fabrication process. These include the thermal distortions of the wafer caused by deposited EUVL energy during scanning exposure. Absorbed energy from the beam produces temperature increases and structural displacements in

Jaehyuk Chang; Carl J. Martin; Roxann L. Engelstad; Edward G. Lovell

2002-01-01

271

Comparison of EUV and optical device wafer heating  

Microsoft Academic Search

The International Technology Roadmap for Semiconductors requires improvements in resolution for each lithographic node. In essence, all sources of distortion in the chip fabrication process must be minimized to meet the stringent error budgets for the sub-90-nm nodes. These include the thermal distortions of the device wafer caused by energy deposition during exposure. Absorbed energy from the beam produces temperature

Jaehyuk Chang; Roxann L. Engelstad; Edward G. Lovell

2003-01-01

272

The effect of various wafer thicknesses on hot spot temperature  

Microsoft Academic Search

Hot spots on thin wafers of IC packages are becoming an important issue in thermal and electrical engineering. To investigate these hot spots, we developed a diode temperature sensor array (DTSA) that consists of an array of 32 times 32 diodes (1,024 diodes) in an 8 mm x 8 mm surface area. We used chemical-mechanical planarization to make DTSA chips

Kyo Sung Choo; Il Young Han; Sung Jin Kim

2008-01-01

273

Wafer yield prediction by the Mahalanobis-Taguchi system  

Microsoft Academic Search

The distribution of yield from the production lines is concentrated at a high-yield area and tapers down to the lower-yield area. Production management would find it useful if the yield of individual wafers could be forecast. The yield is determined by the variability of electrical characteristics and dust. In this study, only the variability of electrical characteristics was discussed. One

M. Asada

2001-01-01

274

Fabricating a Microcomputer on a Single Silicon Wafer  

NASA Technical Reports Server (NTRS)

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

Evanchuk, V. L.

1983-01-01

275

Ultra-Gradient Test Cavity for Testing SRF Wafer Samples  

SciTech Connect

A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

2010-11-01

276

Multi-wafer slicing with a fixed abrasive  

NASA Technical Reports Server (NTRS)

A wafering machine having a multiplicity of wire cutting blades supported by a bladehead reciprocally moving past a workpiece supported by a holder that rocks about an axis perpendicular to the wires at a frequency less than the reciprocation of the bladehead.

Schmid, Frederick (Inventor); Khattak, Chandra P. (Inventor); Smith, Maynard B. (Inventor)

1988-01-01

277

Crack propagation and fracture in silicon wafers under thermal stress  

PubMed Central

The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing. PMID:24046487

Danilewsky, Andreas; Wittge, Jochen; Kiefl, Konstantin; Allen, David; McNally, Patrick; Garagorri, Jorge; Elizalde, M. Reyes; Baumbach, Tilo; Tanner, Brian K.

2013-01-01

278

Steel Bridge Fatigue Crack Detection with Piezoelectric Wafer Active Sensors  

E-print Network

Steel Bridge Fatigue Crack Detection with Piezoelectric Wafer Active Sensors Lingyu Yu1 , Victor acoustic emission to detect the presence of fatigue cracks in steel bridges in their early stage since of the fatigue life for these details is consumed while the fatigue crack is too small to be detected. Hence

Giurgiutiu, Victor

279

A robust production control policy for VLSI wafer fabrication  

Microsoft Academic Search

The authors present control policy for shop-level scheduling in a semiconductor wafer fabrication facility. The policy is designed to reduce the work in process in the shop floor and to follow the production plan as closely as possible. It is also robust against random interference such as machine breakdowns. The flow rate control policy is compared with two other approaches

SHELDON X. C. LOU; PATRICK W. KAGER

1989-01-01

280

InP based photonic crystal microlasers on silicon wafer  

Microsoft Academic Search

We report on 2D photonic crystal InP membrane micro-lasers transferred onto a silicon wafer. Two types of lasers are investigated: microcavities and defect-free structures, exploiting either conventional defect modes, or DFB-like modes. Room temperature low threshold laser operation has been performed for low sized devices.

C. Monat; C. Seassal; X. Letartre; P. Regreny; P. Rojo-Romeo; P. Viktorovitch; M. Le Vassor d'Yerville; D. Cassagne; J. P. Albert; E. Jalaguier; S. Pocas; B. Aspar

2003-01-01

281

Vibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements  

E-print Network

the yield per crystal and to reduce the cost. In this paper, the vibration model of wiresaw system crystalline ingots as well as ceramic materials such as alumina. In the study and modeling of wiresaw. Introduction: Wiresaw is an emerging technology for wafer production in both photovoltaic and semiconductor

Kao, Imin

282

Detection and classification of defect patterns on semiconductor wafers  

Microsoft Academic Search

The detection of process problems and parameter drift at an early stage is crucial to successful semiconductor manufacture. The defect patterns on the wafer can act as an important source of information for quality engineers allowing them to isolate production problems. Traditionally, defect recognition is performed by quality engineers using a scanning electron microscope. This manual approach is not only

Chih-Hsuan Wang; Halima Bensmail

2006-01-01

283

Localized induction heating solder bonding for wafer level MEMS packaging  

Microsoft Academic Search

This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was heated using induction heating causing the solder to reflow. The experiment results show that it took less than 1 min to complete the bonding process. In addition, the MEMS devices experienced a temperature of only 110 °C during bonding, thus

Hsueh-An Yang; Mingching Wu; Weileun Fang

2005-01-01

284

A study of defects on EUV masks using blank inspection, patterned mask inspection, and wafer inspection  

E-print Network

-701 5 ASML, 25 Corporate Circle, Albany, NY 12203 ABSTRACT The availability of defect-free masks remains) in Albany. After exposure, the wafers were inspected with a wafer inspection tool (KLA 28XX) at CNSE

285

Wafer temperature measurement in PVD systems using the Co–Si reaction  

Microsoft Academic Search

It is becoming increasingly important to control the wafer temperature during IC processing, e.g. PVD. To measure the wafer temperature in PVD systems it is possible to use the Co–Si reaction. The difference in sheet resistance of the Co–Si phases, which form at different temperatures, is used to measure maximum wafer temperature in a PVD chamber. The maximum wafer temperature

A. M. van Graven; R. A. M. Wolters

2000-01-01

286

Characterization, modeling, and design of an electrostatic chuck with improved wafer temperature uniformity  

NASA Astrophysics Data System (ADS)

The resulting temperature distribution of a silicon wafer held by an electrostatic chuck (ESC) in an electron-cyclotron-resonance chemical vapor deposition (ECR-CVD) reactor is characterized and modeled. The effects of the clamping voltage VESC, pressure between the ESC and wafer PHe, and the surface finish and pattern on the ESC are investigated. Heat transfer coefficients between the wafer and various ESCs are determined experimentally. A model is developed to predict the temperature distribution at the surface of the wafer, and used to explain the experimentally observed temperature variations both within wafer and between different chucks. The model is then used to aid in the design of an ESC which provides improved temperature uniformity at the wafer surface. The results of this study indicate: (a) the thermal resistances across the interface between the wafer and ESC control both the absolute wafer temperature and the wafer temperature uniformity; (b) the surface roughness of the ESC and the size of the ``contact'' regions are major design factors controlling the absolute temperature of the wafer—the temperature can be adjusted by varying the value of VESC and fine tuned by adjusting the value of PHe; (c) the nonuniform temperature distribution across the wafer surface is dictated by the surface pattern on the ESC, the variation in surface roughness, and the size of the ESC relative to the wafer; (d) wafer temperature variations from chuck to chuck are reduced by controlling the surface finish of the ESC and by ensuring that PHe is a dominant heat transfer mechanism; and (e) maximum uniformity in the temperature of the wafer is obtained when the radius of the ESC is matched as closely as possible to that of the wafer. We have shown that numerical heat transfer models can be used to optimize the geometry of the ESC to provide a uniform distribution of temperature across the surface of the wafer.

Olson, Kurt A.; Kotecki, David E.; Ricci, Anthony J.; Lassig, Stephan E.; Husain, Anwar

1995-02-01

287

Electrochemical method for defect delineation in silicon-on-insulator wafers  

SciTech Connect

This patent describes an electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, T.R.; Jones, H.D.T.; Kelly, M.J.; Medernach, J.W.; Stevenson, J.O.; Tsao, S.S.

1991-05-14

288

Influence of a lift hole-equipped pin chuck on wafer flatness  

Microsoft Academic Search

A site flatness of less than 32nm will be required when fabricating next-generation devices. A pin chuck is used to flatten a warped wafer. This chuck has three lift holes that are utilized when loading and unloading wafers. These holes deteriorate local flatness. This paper describes the influence of wafer thickness and the diameters of lift holes and chuck pins

Atsunobu Une; Nagahisa Ogasawara; Tetsuo Fukuda; Masanori Yoshise; Ping Xin

2009-01-01

289

Effects of wafer impedance on the monitoring and control of ion energy in plasma reactors  

Microsoft Academic Search

Ion kinetic energy in plasma reactors is controlled by applying radio-frequency (rf) substrate bias, but the efficiency and reproducibility of such control will be affected if the wafer being processed has a significant electrical impedance. Here, the effects of wafer impedance were studied by modeling and electrical measurements. Models of wafer impedance were proposed and tested by comparing model predictions

Mark A. Sobolewski

2006-01-01

290

Enhanced Growth of Thermal Oxide Due to Impurity Absorption from Adjoining Contaminated Silicon Wafers  

Microsoft Academic Search

Enhanced growth of thermal oxide at high temperature is investigated when a silicon wafer is situated behind an adjoining contaminated one. Impurities reside on the back surface of the wafer due to chucking with a stainless steel plate, depending on the surface roughness. During oxidation, the impurities spread to the adjoining wafers, causing enhanced oxide growth with the convex side

Hirofumi Shimizu; Masashi Yamamoto

1992-01-01

291

Dynamic deformation of a wafer above a lift hole and influence on flatness due to chucking  

Microsoft Academic Search

A site flatness of less than 26nm will be required when fabricating next-generation devices. A pin chuck is used to flatten warped wafers. This chuck has lift holes for loading and unloading wafers and a ring seal around its periphery. The lift holes and seal deteriorate the local flatness. This paper describes the influence of local dynamic deformation on wafer

Atsunobu Une; Kenichiro Yoshitomi; Masaaki Mochida

2011-01-01

292

Transfer of metal MEMS packages using a wafer-level solder sacrificial layer  

Microsoft Academic Search

This paper presents a modular, low profile, wafer-level encapsulation technology for 0-level MEMS packaging. Electroplated caps are formed on a carrier wafer then simultaneously transferred and bonded to a device wafer by a novel solder transfer method and transient liquid phase (TLP) bonding technology. The solder transfer method is enabled by the dewetting of the solder transfer layer from the

Warren C Welch; Khalil Najafi

2005-01-01

293

Transfer of metal MEMS packages using a wafer-level solder transfer technique  

Microsoft Academic Search

This paper presents a modular, low profile, wafer-level encapsulation technology for microelectromechanical systems (MEMS) packaging. Electroplated caps are formed on top of a solder transfer layer previously deposited on a carrier wafer, then simultaneously transferred and bonded to a device wafer by a novel solder transfer method and transient liquid phase (TLP) bonding technology. The solder transfer method is enabled

Warren C. Welch; Junseok Chae; Khalil Najafi

2005-01-01

294

Sapphire Wafer Bumping by Lead-free Solder Paste Printing Process  

Microsoft Academic Search

Peregrine's silicon on sapphire technology provides high performance RF IC devices to wireless market, while for bumping on this type of sapphire wafer new challenges will be encountered. High residual stress accumulated on sapphire wafer surface may cause bumping reliability performance issue. Sapphire wafer's singulation process, which uses three-point breaking method, requires bumping must be of a reasonable structure to

Y. J. Zhiyuan

2007-01-01

295

Beam test results of ion-implanted silicon strip detectors on a 100 mm wafer  

Microsoft Academic Search

The use of planar silicons trip detectors in both position sensitive and energy dispersive applications has rapidly increased. Detector systems of large angular coverage unavoidably consist of a large number of individual detector plates traditionally processed on 3 inch silicon wafers. The effective wafer processing area is almost doubled by the use of 100 mm wafers, enabling detector designs with

Iiro Hietanen; Jukka Lindgren; Risto Orava; Tuure Tuuva; R. Brenner; Mikael Andersson; Kari Leinonen; Hannu Ronkainen; L. Hubbeling; Michal Turala; W. Dulinski; D. Husson; A. Lounis; M. Schaeffer; R. Turchetta; J. Chauveau

1991-01-01

296

Evaluating different sampling techniques for process control using automated patterned wafer inspection systems  

Microsoft Academic Search

To evaluate sampling for automated defect inspections, a series of four inspection areas ranging from <1 cm2 to >4 cm2 were performed. Using an automated patterned wafer inspection system, 20 wafers were inspected for each of the sample sizes. Inspected die were selected in a random pattern across the wafer and remained the same for each inspection. The inspected area

Dennis Lazaroff; David Bakker; Derek R. Granath

1991-01-01

297

Optimized wafer-probe and assembled package test design for analog circuits  

Microsoft Academic Search

It is well known that wafer-probe test costs of analog ICs are an order of magnitude less than the corresponding test costs of assembled packages. It is therefore natural to push as much of the testing process into wafer-probe testing as possible to reduce the scope of assembled package testing. However, the signal drive and response observation capabilities during wafer

Soumendu Bhattacharya; Abhijit Chatterjee

2005-01-01

298

Automation of wafer handling in legacy semiconductor faba true cultural change  

Microsoft Academic Search

When yield analysis revealed extensive die losses associated with wafer scratches, our fab management commissioned a comprehensive program to completely eliminate manual handling of wafers during manufacturing. This experience constituted a true cultural change for our legacy fab, which throughout a 15-year history had excelled at low cost, low cycle time manufacturing but had neglected fundamental improvements in wafer handling

R. L. Guldi; M. T. Whitfield; D. E. Paradis; F. D. Poag; D. P. Jensen

1997-01-01

299

SUEX process optimization for ultra-thick high-aspect ratio LIGA imaging  

NASA Astrophysics Data System (ADS)

The focus of this paper is on the use of SUEX Thick Dry Film Sheet (TDFS) laminates which DJ DevCorp is developing as a thick resist material in optical and X-ray lithography. Preliminary thick dry film sheets up to 1mm thickness were successfully prepared and patterned at the CAMD X-ray beamlines and presented at HARMST 2007. Recently, new results have been published using SUEX resist sheets in UV lithography showing great market potential including plating molds for metal microparts, polymer MEMS, multilayer microfluidics structures, BioMEMS, medical devices, wafer level packaging processes, and displays. The SUEX TDFS are available in a range of thicknesses from 100?m to 1mm or more and are pre-cut into a number of standard wafer sizes. This new material is a modified epoxy formulation containing an antimony-free photo acid generator (PAG) prepared under a highly controlled solvent-less process which provides uniform coatings between two throw-away layers of protective polyester film. As part of our initial studies resist layers of 250, 500 and 1000?m were laminated onto regular silicon wafers using a hot roll laminator at a speed of 1ft/min at 75°C. The entire substrate preparation takes about 1 hour and with practice users can prepare up to 10 substrates in this time which are typically ready to use within 2 hours. In our efforts to develop a commercially viable product we have conducted experiments using standard equipment available at CAMD (Quintel UV aligner and CAMD XRLM 1 and 4 beamline). Initial X-ray exposure tests were done with a bottom dose ranging between 100 and 400 J/cm3 and a top/bottom dose ratio of less than 3 for sheets up to 2mm in thickness. Exposure time for typical conditions of the CAMD storage ring (ring current ranging between 100 and 160mA, beam lifetime of about 10hrs at 100mA ring current) is about 10-15min for a 4' wafer. After exposure the samples were immediately post exposure baked between 70°C and 110°C using a convection oven, taken out and cooled to RT then relaxed up to 3 days before development to reduce stress. Development was done in PGMEA for up to 3 hours for the 1000?m thick samples followed by a short IPA rinse and drying in air. Very high aspect ratios of 100 or more have been routinely patterned with nearly perfectly straight sidewalls (~1-1.5?m deviation for a 1mm tall structure) and excellent image fidelity.

Johnson, Donald W.; Goettert, Jost; Singh, Varshni; Yemane, Dawit

2011-04-01

300

The Study of Deep Lithography and Moulding Process of LIGA Technique  

NASA Astrophysics Data System (ADS)

The knowledge of the development behavior, especially the development rate, is of primary importance for the study of deep x-ray lithography in LIGA technique. In the first part of this paper, we have measured the development rates of crosslinked PMMA foils irradiated in NSRL covering a wide dose range (bottom dose in the range:2.5-8.0 kJ/cm3). After the exposure, we use a so-called period-development method (to dip development in GG-developer for 20 minutes and clean in rinse solution for 40 minutes as a development period). For processing the experiment data, we get the KD? model to describe our PMMA/GG-developer system. The aim of this work is to find out a stable experiment condition for deep X-ray lithography and development. The result shows that in small amount of dose (bottom dose range: 2.5-4 kJ/cm3), this model is very stable. While in large amount of dose (bottom dose range: 5-8kJ/cm3), the model becomes very sensitive and even unavailable. To verify the conclusion validity, the fixed dose range (bottom dose range: 3.5-4 kJ/cm3) is applied on PMMA microstructures. And the result shows an effective development process. In the following procedure, mold inserts can be produced by micro-electroforming and plastic replicas can be mass produced by hot embossing. To emboss high-aspect-ratio microstructures, the deformation of microstructures usually occurs due to the demolding forces between the sidewall of mold inserts and the thermoplastic (PMMA). To minimize the friction force the optimized experiment has been performed using Ni-PTFE compound material mold inserts. Typical defects like pull-up and damaged edges can be greatly reduced.

Guo, Yuhua; Liu, Gang; Kan, Ya; Tian, Yangchao

2007-01-01

301

Performance of Ultra Hard Carbon Wear Coatings on Microgears Fabricated by Liga  

SciTech Connect

Stiction and friction are of concern for the reliable, long-term application of Ni-alloy micromachines. We have found that the application of a 30-70 nm hard carbon coating produces a significant reduction in the friction coefficient and wear rate of electroformed Ni substrates in reciprocating sliding contact under simulated MEMS operating conditions. To evaluate the performance of coated components, a series of 70-pm-thick microgears ranging in diameter from 0.2 to 2.2 mm were fabricated from electroformed Ni via standard LIGA processes and fixtured on posts in preparation for the coating procedure. A pulsed vacuum- arc deposition process was used to deposit a carbon coating on the gears with the plasma incident at a shallow angle to the gears' top surface. A sample bias of -2 keV was used in order to produce a coating with relatively low stress and good adhesion while maintaining high hardness. This coating process is known to be somewhat comformal to the component surfaces. The coating uniformity, particularly in the high-aspect-ratio areas between the gear teeth, was evaluated with micro-Raman spectroscopy. It is shown that the coating can be applied uniformly on the top gear surface. Between the gear teeth the coating was the same thickness as on top of the gear down to a point 50 ~m below the top surface. Below that point (i.e. between 50 and 70 Lm), the coating thickness is somewhat thinner, but is still present. These results demonstrate that it is possible to a deposit hard carbon coating on microgears to reduce friction and wear in micromachines.

Ager III, J.W.; Brown, I.G.; Christenson, T.R.; Dugger, M.T.; Follstaedt, D.M.; Knapp, J.A.; Monteiro, O.R.

1998-12-18

302

Light scatter from defects on chemically-mechanically polished wafers  

NASA Astrophysics Data System (ADS)

Detection and reduction of defects on chemically-mechanically polished (CMP) wafers are important concerns in semiconductor manufacturing. The physical and light scattering characteristics of typical CMP wafer surface defects including roughness, dishing, particles, and scratches are investigated in this dissertation. A new scatterometer is developed for the light scattering study. The system measured "true" bidirectional reflectance distribution functions (BRDF) and differential scattering cross sections (DSC) in plane of incidence. Through comparing experimental results with modeling and with expected values from standard samples, the system is proven to be able to deliver accurate scattering measurements on small features and wafer surfaces. The physical characteristics of metal roughness, metal dishing, contaminants, and scratches on tungsten (W) and copper (Cu) CMP wafers are studied. The power spectral density of W and Cu, the metal dishing's dependency on linewidth and pattern density, the different compositions of various contaminants, and the appearances of scratches are investigated. The scattering characteristics of the patterned W and Cu CMP wafer substrates are studied. A light scattering scheme which measures metal roughness on a patterned wafer is developed based on the Rayleigh-Rice vector perturbation theory. The dishing's dependency on pattern density is characterized using light scattering, and the scatter from Cu line-edges is measured and compared to the scatter from a step simulated using the Kirchhoff approximation method. The angle-resolved scatter from individual 0.305 mum and 0.482 mum polystyrene latex spheres on blanket silicon (Si), silicon dioxide (SiO 2) film, and W film surfaces is measured and the effects of roughness and a dielectric film on particle scatter are investigated. The scattering characteristics of diamond-tip scribed scratches on a filmed surface, which are long linear scratches and are about 0.8 mum wide and 90 nm deep, are studied as a function of incident angle and polarization. Finally, a light scattering scheme that classifies particles and scratches is developed using their different dependency of differential scattering cross sections on beam diameter.

Ding, Ping

2000-10-01

303

Liquid crystal lens auto-focus extended to optical image stabilization for wafer level camera  

NASA Astrophysics Data System (ADS)

Miniaturization and reduction of production cost of optical components in consumer electronics leads to wafer level optics. This miniaturization, associated with the increase of CMOS sensors resolution, generates new needs such as auto-focus (AF) and optical image stabilization (OIS) in order to reduce the blurring caused by hand jitter. In this paper, we propose a wafer scale technology to perform AF and introduce OIS functionality. We managed to create a tunable focal lens by filling with nematic liquid crystal (LC) an assembly of two glass substrates coated with circular hole patterned chromium electrodes and resistive transparent layers of Poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT-PSS). When a voltage with tunable magnitude and frequency is applied to the electrodes, the resistive layer creates a non-uniform voltage distribution from the edge to the center of the aperture which depends on electrical parameters of PEDOT-PSS and LC. The resultant electric field generates a gradient orientation of the nematic director which allows to focus light polarized along the director. It is also possible to shift the optical axis of the lens by dividing the hole patterned electrodes in several sectors and to apply different voltages on each sectors. The principle of the shifting effect has been demonstrated but its magnitude has to be increased by using more adapted electrode structure to ensure the OIS function. Finally, we characterised the dynamical behaviour of the lens in both focus and shifting modes.

Fraval, Nicolas; Berier, Frédéric

2011-03-01

304

A hermetic and room-temperature wafer bonding technique based on integrated reactive multilayer systems  

NASA Astrophysics Data System (ADS)

This paper focuses on direct deposition and patterning of reactive and nano-scale multilayer films at wafer level. These multilayer structures are called integrated reactive material systems (iRMS). In contrast to the typically used nickel (Ni)/ aluminum (Al) systems, in this work we needed to have our total multilayer film thicknesses smaller than 2.5?µm to reduce stress within the multilayer as well as deposition costs. Thus, we introduced new high energetic iRMS. These films were deposited by using alternating magnetron sputtering from high purity Al- and palladium (Pd)-targets to obtain films with a defined Al:Pd atomic ratio. In this paper, we present the result for reaction characteristics and reaction velocities which were up to 72.5?m?s?1 for bond frames with lateral dimensions as low as 20?µm. Furthermore, the feasibility of silicon (Si)–Si, Si–glass as well as Si–ceramic hermetic and metallic wafer bonding at room temperature is presented. We show that by using this bond technology, strong (maximum shear strengths of 235?MPa) and hermetically sealed bond interfaces can be achieved without any additional solder material.

Braeuer, J.; Gessner, T.

2014-11-01

305

Cartilage-retaining Wafer Resection Osteotomy of the Distal Ulna  

PubMed Central

Ulnar-sided wrist pain resulting from ulnar impaction is common. We describe a new cartilage-retaining wafer resection osteotomy designed to keep the cartilage intact and decompress the ulnocarpal articulation without requiring internal fixation. We retrospectively reviewed seven patients with ulnar impaction who had the procedure. The minimum followup was 14 months (mean, 30 months; range, 14–38 months). The mean change in ulnar variance was ?1.29 mm. Patients showed radiographic healing by a mean of 11 weeks. Our preliminary results suggest the cartilage-retaining wafer resection osteotomy may be an effective way to unload the ulnocarpal joint without requiring internal fixation or destruction of the distal ulna cartilage. Level of Evidence: Level IV, therapeutic study. See the Guidelines for Authors for a complete description of levels of evidence. PMID:18196423

Macksoud, Wadih S.

2008-01-01

306

JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES  

SciTech Connect

There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

Montoya, Angela C.; Maji, Arup K. [University of New Mexico, Department of Civil Engineering, Albuquerque, New Mexico, 87131 (United States)

2010-02-22

307

A gas chromatographic air analyzer fabricated on a silicon wafer  

NASA Technical Reports Server (NTRS)

A miniature gas analysis system has been built based on the principles of gas chromatography (GC). The major components are fabricated in silicon using photolithography and chemical etching techniques, which allows size reductions of nearly three orders of magnitude compared to conventional laboratory instruments. The chromatography system consists of a sample injection valve and a 1.5-m-long separating capillary column, which are fabricated on a substrate silicon wafer. The output thermal conductivity detector is separately batch fabricated and integrably mounted on the substrate wafer. The theory of gas chromatography has been used to optimize the performance of the sensor so that separations of gaseous hydrocarbon mixtures are performed in less than 10 s. The system is expected to find application in the areas of portable ambient air quality monitors, implanted biological experiments, and planetary probes.

Terry, S. C.; Jerman, J. H.; Angell, J. B.

1979-01-01

308

Wafer-fused VECSELs emitting in the 1310nm waveband  

NASA Astrophysics Data System (ADS)

Optically pumped wafer fused 1310 nm VECSELs have the advantage of high output power and wavelength agility. Gain mirrors in these lasers are formed by direct bonding of InAlGaAs/InP active cavities to Al(Ga)As/GaAs DBRs. We present for the first time Watt-level 1310 nm wafer-fused VCSELs based on gain mirrors with heat dissipation in the "flip-chip" configuration. Even though output power levels in this approach is lower than with intra-cavity diamond heat-spreaders, the "flip-chip configuration demonstrates higher quality optical emission and is preferable for industrial applications in optical amplifiers, intra-cavity doubled lasers, etc.

Sirbu, A.; Pierscinski, K.; Mereuta, A.; Iakovlev, V.; Caliman, A.; Micovic, Z.; Volet, N.; Rautiainen, J.; Heikkinen, J.; Lyytikainen, J.; Rantamäki, A.; Okhotnikov, O.; Kapon, E.

2014-03-01

309

Chemical method for producing smooth surfaces on silicon wafers  

DOEpatents

An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

Yu, Conrad (Antioch, CA)

2003-01-01

310

Virtual instrument realization of non-contact silicon wafer test  

Microsoft Academic Search

Based on virtual instrument technology, the paper conducts organic integration of capacitive displacement sensor ranging technology, eddy current sensor resistance testing technology and semiconductor P\\/N polarity of infrared pulse sensor testing technology, and develops dynamic non-contact silicon wafer testing instrument, which not only simulates the testing instruments like signal generator, digital oscilloscope, programmable power supply and digital multi-meter, but also

Yan Youjun; Li Yunfei

2009-01-01

311

Towards reduced impact of EUV mask defectivity on wafer  

NASA Astrophysics Data System (ADS)

The defectivity challenges of extreme ultraviolet (EUV) masks, that need to be addressed before production readiness of EUV lithography is assured from the mask perspective, are twofold. First, the EUV-specific defect type relating to the multi-layer (ML) mirror, the so-called ML-defects, require to become more detectable than they are printable. This not only requires proven capability of blank inspection, but also the existence of satisfactory printability mitigation strategies (comprising avoidance, pattern shift methodology, compensation repair). Both these assets need to become available within the mask supply chain, as there is little that can still be done about such residual defects at the wafer fab. In a production phase, finding unexpected printing ML-defects is unacceptable. It is shown how the specific way-of-working in use at imec, starting from the printed wafer, contributes to related learning and identification of remaining gaps, in getting this issue fully dealt with. The second challenge relates to particle contamination during use of the reticle at the wafer fab. Avoiding overlaycritical particles on the backside of NXE3100 reticles is facilitated by the established way-of-working. Minimizing the occurrence of particles "hopping" between reticles via the electrostatic clamp of the scanner (so-called clamp-traveling particles) is a major driver for appropriate mask cleaning. The latter may not have negative impact by frequent use, in view of the highly vulnerable EUV mask stack, and especially for the present "black-border" solution in which the ML is etched away at the image border on the reticle. A lot of effort is spent into monitoring of NXE3100 reticles for particle adders on the pattern side. This is realized by comparing past and present mask defect maps obtained by inspection of printed wafers with subsequent repeater analysis.

Jonckheere, R.; Van den Heuvel, D.; Pacco, A.; Pollentier, I.; Baudemprez, B.; Jehoul, C.; Hermans, J.; Hendrickx, E.

2014-07-01

312

Electrooptic wafer beam deflector in LiTaO3  

Microsoft Academic Search

A novel electrooptic beam deflector is reported based on ferroelectric domain inversion extending through the thickness of a Z-cut LiTaO3 wafer. The selective domain inversion is achieved by electric-field poling assisted by proton exchange, rather than proton exchange followed by rapid thermal annealing. The deflection sensitivity of the device was measured to be 5.0 mrad\\/KV. This is 93% of the

Jun Li; Hsing C. Cheng; Matthew J. Kawas; David N. Lambeth; T. E. Schlesinger; Daniel D. Stancil

1996-01-01

313

Wafer-level radiometric performance testing of uncooled microbolometer arrays  

NASA Astrophysics Data System (ADS)

A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 ?m AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 ?m pixel size and 160x120, 52 ?m pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

2014-03-01

314

Modeling and simulation of material handling for semiconductor wafer fabrication  

Microsoft Academic Search

This paper presents the results of a design study to analyze interbay material-handling systems for semiconductor wafer manufacturing. We developed discrete-event simulation models to model the performance of conventional cleanroom material handling including manual and automated systems. The components of a conventional cleanroom material-handling system include an overhead monorail system for interbay (bay-to-bay) transport, work-in-process stockers for lot storage, and

Neal G. Pierce; Richard Stafford

1994-01-01

315

Robust linear regression for modeling systematic spatial wafer variation  

NASA Astrophysics Data System (ADS)

We describe a new method of estimating the systematic spatial variation across wafers. Current methods for this task share some common deficiencies. For example, few of these techniques are able to decompose the systematic variation into components that can be assigned to different types of tools. Most of these methods are also sensitive to outliers and require that the outliers be manually removed before the model can be estimated. Almost none of the previous methods can account for high-frequency effects caused by reticle non-uniformity. Our method is based on a linear regression model with various components to account for the systematic variation that occurs in practice. Polynomial components model the smooth variation caused by tools that cannot process the wafer uniformly. Reticle components model the variation that occurs due to non-uniformities in the microlithography and etch tools. To generate distinct patterns, we apply QR orthogonalization to the systematic patterns prior to regression. To limit the effects of outliers, we employ robust regression. We demonstrate the performance of our technique with an example on data collected from production wafers.

McNames, James; Moon, Byungsool; Whitefield, Bruce; Abercrombie, David

2005-05-01

316

Method for making circular tubular channels with two silicon wafers  

DOEpatents

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

Yu, C.M.; Hui, W.C.

1996-11-19

317

Towards large size substrates for III-V co-integration made by direct wafer bonding on Si  

NASA Astrophysics Data System (ADS)

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

2014-08-01

318

Wafer-level colinearity monitoring for TFH applications  

NASA Astrophysics Data System (ADS)

Advances in thin film head (TFH) designs continue to outpace those in the IC industry. The transition to giant magneto resistive (GMR) designs is underway along with the push toward areal densities in the 20 Gbit/inch2 regime and beyond. This comes at a time when the popularity of the low-cost personal computer (PC) is extremely high, and PC prices are continuing to fall. Consequently, TFH manufacturers are forced to deal with pricing pressure in addition to technological demands. New methods of monitoring and improving yield are required along with advanced head designs. TFH manufacturing is a two-step process. The first is a wafer-level process consisting of manufacturing devices on substrates using processes similar to those in the IC industry. The second half is a slider-level process where wafers are diced into 'rowbars' containing many heads. Each rowbar is then lapped to obtain the desired performance from each head. Variation in the placement of specific layers of each device on the bar, known as a colinearity error, causes a change in device performance and directly impacts yield. The photolithography tool and process contribute to colinearity errors. These components include stepper lens distortion errors, stepper stage errors, reticle fabrication errors, and CD uniformity errors. Currently, colinearity is only very roughly estimated during wafer-level TFH production. An absolute metrology tool, such as a Nikon XY, could be used to quantify colinearity with improved accuracy, but this technique is impractical since TFH manufacturers typically do not have this type of equipment at the production site. More importantly, this measurement technique does not provide the rapid feedback needed in a high-volume production facility. Consequently, the wafer-fab must rely on resistivity-based measurements from slider-fab to quantify colinearity errors. The feedback of this data may require several weeks, making it useless as a process diagnostic. This study examines a method of quickly estimating colinearity at the wafer-level with a test reticle and metrology equipment routinely found in TFH facilities. Colinearity results are correlated to slider-fab measurements on production devices. Stepper contributions to colinearity are estimated, and compared across multiple steppers and stepper generations. Multiple techniques of integrating this diagnostic into production are investigated and discussed.

Moore, Patrick; Newman, Gary; Abreau, Kelly J.

2000-06-01

319

Transparent masks for aligned deep x-ray lithography/LIGA: low-cost high-performance alternative using glass membranes  

NASA Astrophysics Data System (ADS)

Deep x-ray lithography/LIGA has proven to be a well established framework of x-ray based technologies for the fabrication of microstructures and pseudo three-dimensional objects. Inherently, x-ray lithography/LIGA is not fully three-dimensional because of the principle of simple shadow printing onto resists of constant thickness. Thus, it would be impossible to obtain 3D spheres, but series of stacked monolithic 2D cylinders. Hence, until recently, LIGA was mainly concerned with simple uni-level (1D) monolithic structures, using optically opaque mask-membranes like Be, Si or Ti with grown-on Au absorbers. In the course for mastering pseudo three-dimensional microstructures like micro-coils or electromagnetic applications, an alignment in between the lithographic steps becomes necessary which requires optically transparent membrane materials, if optical alignment is chosen. Diamond or SiC membranes are the actual suitable materials for such purposes, but their pricing and/or process robustness inhibit their frequent use in simple projects. We would like to report on a new promising material: a glued-on thin glass membrane. The advantages are incomparably lower costs compared to Diamond or SiC technologies, a considerable ease of fabrication, handling, quite favorable mechanical/optical properties, sufficient for lithographic purposes and multi-level deep x-ray lithography/LIGA activities.

Kupka, Roland K.; Megtert, Stephan; Roulliay, Marc; Bouamrane, Faycal

1998-09-01

320

Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers  

E-print Network

Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive advantage of copper-to-copper (Cu-to-Cu) bonding with the increased adhesion strength and robustness of dielectric adhesive bonding using benzocyclobutene (BCB) is discussed. Critical processing challenges

Salama, Khaled

321

Wafer-level manufacturing technology of glass microlenses  

NASA Astrophysics Data System (ADS)

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

322

Advanced Ceramic Wafer Seals Demonstrated at 2000 deg. F  

NASA Technical Reports Server (NTRS)

Durable, high-temperature sliding seals are required in advanced hypersonic engines and around movable control surfaces on future vehicles. These seals must operate at temperatures of 2000 to 2500 F, limit hot gas flow, remain resilient for multiple cycles, and resist scrubbing damage against rough surfaces. Current seal designs do not meet these demanding requirements, so the NASA Glenn Research Center is developing advanced seals and preload devices to overcome these shortfalls. An advanced ceramic wafer seal design and two silicon nitride compression spring designs were evaluated in a series of compression, scrub, and flow tests.

Dunlap, Patrick H.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2005-01-01

323

Automotive SOI-BCD Technology Using Bonded Wafers  

SciTech Connect

The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N{sup +} layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

Himi, H.; Fujino, S. [DENSO CORPORATION, Ashinoya, Kota-cho, Nukata-gun, Aichi Pref., 444-0193 (Japan)

2008-11-03

324

Addressable Inverter Matrix Tests Integrated-Circuit Wafer  

NASA Technical Reports Server (NTRS)

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Buehler, Martin G.

1988-01-01

325

Influences of interface oxidation on transmission laser bonding of wafers for microsystem packaging  

Microsoft Academic Search

In the fabrication of micro-devices and systems, wafer bonding offers a unique opportunity for constructing complicated three-dimensional structures. In this paper, a wafer bonding technique, called transmission laser bonding (TLB), is studied with focus on the effects of interface oxidation and contact pressure on the bonding strength. The TLB is implemented for bonding Pyrex glass-to-silicon wafers, with and without interface

Ampere A. Tseng; Jong-Seung Park; George P. Vakanas; Hongtao Wu; Miroslav Raudensky; T. P. Chen

2007-01-01

326

Flattening ability of a vacuum pin chuck around the periphery of a processed wafer  

Microsoft Academic Search

To resolve ultra-fine patterns of 0.13 ?m or less, chucking accuracy must be within ±0.05 ?m except 1 mm from the wafer edge. This paper describes the contact distribution between the back surface of a wafer and a chuck surface measured after clamping and vacuum-pin-chuck flattening ability around the periphery of a processed wafer calculated with the finite element method.

A. Une; Y. Kai; M. Mochida; S. Matsui

2001-01-01

327

Characterization, modeling, and design of an electrostatic chuck with improved wafer temperature uniformity  

Microsoft Academic Search

The resulting temperature distribution of a silicon wafer held by an electrostatic chuck (ESC) in an electron-cyclotron-resonance chemical vapor deposition (ECR-CVD) reactor is characterized and modeled. The effects of the clamping voltage VESC, pressure between the ESC and wafer PHe, and the surface finish and pattern on the ESC are investigated. Heat transfer coefficients between the wafer and various ESCs

Kurt A. Olson; David E. Kotecki; Anthony J. Riccib; Stephan E. Lassig; Anwar Husain

1995-01-01

328

Application of advanced contamination analysis for qualification of wafer handling systems and chucks  

NASA Astrophysics Data System (ADS)

Wafer chucks and handlers were investigated for their release of particulate and metallic contamination onto the backside of the wafers. The wafers were analyzed for metallic impurities using TXRF and VPD-AAS measurement. Particulate contamination was investigated with a laser surface inspection system. Mapping of diffusion lengths of minority carriers was applied in order to make contamination patterns visible. Different chucks were investigated and evaluated. It was demonstrated that the contamination release depends strongly on surface coating and type of the chuck.

Kroninger, F.; Streckfuss, N.; Frey, L.; Falter, T.; Ryzlewicz, C.; Pfitzner, L.; Ryssel, H.

1993-01-01

329

Kerf-free wafering: Technology overview and challenges for thin PV manufacturing  

Microsoft Academic Search

Eliminating high absorber material loss while allowing thin and ultra-thin crystalline silicon PV has been a “Holy Grail” of the crystalline silicon PV industry for decades. Generally called “kerf-free wafering”, the fundamental approach is to substitute slurry saws with an alternative waste-free wafering technology. Ideally, the technology would also eliminate the difficulty to process thin to ultra-thin wafers inherent to

Francois J. Henley

2010-01-01

330

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing  

NASA Technical Reports Server (NTRS)

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

331

Scribing and cutting a blue LED wafer using a Q-switched. Nd:YAG laser  

Microsoft Academic Search

Sapphire wafer is found to be scribed and cut freely by plasma from a metal surface on which a Q-switched Nd:YAG laser beam is focused through the wafer. The wafer is scribed enough to be cut using a Q-switched Nd:YAG laser with the average power of 5 W at atmospheric environment without a vacuum chamber. This method is successfully applied

J.-M. Lee; J.-H. Jang; T.-K. Yoo

2000-01-01

332

Scribing and cutting a blue LED wafer using a Q-switched. Nd:YAG laser  

Microsoft Academic Search

.   Sapphire wafer is found to be scribed and cut freely by plasma from a metal surface on which a Q-switched Nd:YAG laser beam\\u000a is focused through the wafer. The wafer is scribed enough to be cut using a Q-switched Nd:YAG laser with the average power\\u000a of 5 W at atmospheric environment without a vacuum chamber. This method is successfully applied

J.-M. Lee; J.-H. Jang; T.-K. Yoo

2000-01-01

333

Measurements and Control of Particle Deposition Velocity on a Horizontal Wafer with Thermophoretic Effect  

Microsoft Academic Search

To investigate positive and negative thermophoretic effects for polystyrene latex (PSL) spheres of diameter between 0.3 and 0.8 ?m, the average deposition velocity toward a horizontal wafer surface in vertical airflow is measured keeping the wafer surface temperature different from the surrounding air temperature. The temperature difference ranges from -10° to 4°C. The number of particles deposited on a wafer

Gwi-Nam Bae; Chun Sik Lee; Seung O. Park

1995-01-01

334

Advances in cross-contamination control using single-wafer, high-current implantation  

Microsoft Academic Search

The Varian VIISta 80 is a single-wafer high-current implanter, which uses a ribbon beam and a single-direction mechanical scan for implantation. The placement of the wafers on an electrostatic platen, and the absence of end station parts in the vicinity of the wafer during implant, translate into an expected advantage in implanter memory over batch tools. This paper focuses on

S. S. Todorov; A. Bertuch; W. Piscitello; R. Eddy; T. Robertson

2000-01-01

335

Plasma-assisted InP-to-Si low temperature wafer bonding  

Microsoft Academic Search

The applicability of wafer bonding as a tool to integrate the dissimilar material system InP-to-Si is presented and discussed with recent examples of InP-based optoelectronic devices on Si. From there, the lowering of annealing temperature in wafer bonding by plasma-assisted bonding is the essence of this review paper. Lower annealing temperatures would further launch wafer bonding as a competitive technology

Donato Pasquariello; Klas Hjort

2002-01-01

336

Resonating microbridge mass flow sensor with low-temperature glass-bonded cap wafer  

Microsoft Academic Search

A resonating microbridge mass flow sensor has been realized suspended inside a micro flow channel. Thin-film technologies and micromachining are used for the fabrication of the sensor wafer and a cap wafer with opposing V-grooves. A low-temperature glass-bonding technique is used to assemble the wafers allowing for feedthrough of the electrical connections. Measurements show sensitivities of the resonance frequency of

Rob Legtenberg; Siebe Bouwstra; Jan H. J. Fluitman

1991-01-01

337

Correlation of wafer backside defects to photolithography hot spots using advanced macro inspection  

NASA Astrophysics Data System (ADS)

Defects on the backside of a wafer during processing can come from many sources. Particles and scratches on the backsides of wafers can be caused by wafer handling equipment such as robots and chucks, as well as by CMP processes. In addition, cross-contamination of wafers and handling equipment can occur when wafers move from tool to tool, through the production line. When wafers are exposed, backside defects can cause localized areas of poor lithography pattern resolution on the frontsides of wafers, resulting in increased rework rates, decreased throughput, and yield loss. As minimum feature sizes continue to shrink with each new technology node, devices become denser and exposure tool depth of focus decreases - making the elimination of lithography hot spots an even more critical issue. At a major worldwide IDM, automated macro defect inspection tools for integrated front, edge, and backside inspection have been implemented to inspect wafers at several After Develop Inspection (ADI) and post-etch inspection steps. These tools have been used to detect foreign material and scratches on the backsides of several lots that were caused by another process tool, causing photolithography hot spots. This paper describes advanced macro inspection of wafer front and back surfaces and how the inspection data was used to correlate backside defects to photolithography hot spots, and take corrective action.

Carlson, Alan; Le, Tuan

2006-03-01

338

Improved quality control of silicon wafers using novel off-line air pocket image analysis  

NASA Astrophysics Data System (ADS)

Air pockets (APK) occur randomly in Czochralski (Cz) grown silicon (Si) crystals and may become included in wafers after slicing and polishing. Previously the only APK of interest were those that intersected the front surface of the wafer and therefore directly impacted device yield. However mobile and other electronics have placed new demands on wafers to be internally APK-free for reasons of thermal management and packaging yield. We present a novel, recently patented, APK image processing technique and demonstrate the use of that technique, off-line, to improve quality control during wafer manufacturing.

Valley, John F.; Sanna, M. Cristina

2014-08-01

339

The optimization of CD uniformity and measurement on mask and wafer  

NASA Astrophysics Data System (ADS)

As pattern size is shrinking, required mask CD specification is tighter and its effect on wafer patterning is more severe. To enhance the device performance, wafer CD uniformity should be enhanced and controlled by mask global CD uniformity. Mask global CD uniformity usually can be enhanced by mask process and optimal fogging effect correction. To enhance the mask global CD uniformity on mask, resist process and FEC (Fogging Effect Correction), reliable CD measurement tool and methods are necessary. Recently, group CD using OCD(Spectroscopic Ellipsometer) or AIMS(Aerial Image Measurement and Simulation) is used to represent global CD variation on mask. These methods are removing local CD variation on mask. Because local CD variation on wafer is large compared with the effect of local CD variation of mask, global CD uniformity can be measured with suppressed local CD variation [1]. In this paper, local CD variation of mask and wafer is evaluated, and area CD and smoothing methods are used to measure CD on mask and wafer, and the correlation of global CD of mask and field CD of wafer are evaluated. By these methods, CD measurement repeatability can be enhanced to get closer correlation of mask and wafer. Close correlation makes fine CD correction on mask to get better field CD uniformity on wafer. And the repeatability of field to field CD uniformity of wafer is evaluated according to measurement tool of CD-SEM and scatterometry.

Choi, Yongkyoo; Kim, Munsik; Han, Oscar

2007-05-01

340

Determination of wafer center position during the transfer process by using the beam-breaking method  

NASA Astrophysics Data System (ADS)

A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human-machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions.

Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

2014-09-01

341

A practical approach to LWIR wafer-level optics for thermal imaging systems  

NASA Astrophysics Data System (ADS)

The development and implementation of wafer level packaging for commercial microbolometers has opened the pathway towards full wafer-based thermal imaging systems. The next challenge in development is moving from discrete element LWIR imaging systems to a wafer based optical system, similar to lens assemblies found in cell phone cameras. This paper will compare a typical high volume thermal imaging design manufactured from discrete lens elements to a similar design optimized for manufacture through a wafer based approach. We will explore both performance and cost tradeoffs as well as review the manufacturability of all designs.

Symmons, Alan; Pini, Ray

2013-06-01

342

How accurate are rapid prototyped (RP) final orthognathic surgical wafers? A pilot study.  

PubMed

Computer packages have been introduced to simulate the movements of the jaw in three dimensions to facilitate planning of treatment. After final 3-dimensional virtual planning, a rapid prototype wafer can be manufactured and used in theatre. Our aim was to assess the accuracy of rapid prototyping of virtual wafers derived from laser scanned dental models using CAD/CAM software. Upper and lower plaster models from 10 orthognathic patients, the articulated models, and the conventional wafers were scanned. The virtual wafers were made from CAD/CAM software, and printed on a stereolithographic printer. We also scanned the articulated models with rapid prototype wafers in place. The validity of the final rapid prototype wafer was measured by the accuracy with which upper and lower models related to one another. The absolute mean error of the rapid prototype wafer when aligned with the dental models was 0.94 (0.09) mm. The absolute distance of the 2 models articulated by conventional and rapid prototype wafers ranged from 0.04 - 1.73mm. The rapid prototype wafers were able to orientate the upper and lower dental models with an absolute mean error of 0.94 (0.09) mm, but it ranged from 0.04-1.73mm. PMID:24933576

Shqaidef, Abedalrahman; Ayoub, Ashraf F; Khambay, Balvinder S

2014-09-01

343

B-Cell-Specific Peptides of Leptospira interrogans LigA for Diagnosis of Patients with Acute Leptospirosis  

PubMed Central

Leptospirosis is a reemerging infectious disease that is underdiagnosed and under-recognized due to low-sensitivity and cumbersome serological tests. Rapid reliable alternative tests are needed for early diagnosis of the disease. Considering the importance of the pathogenesis-associated leptospiral LigA protein expressed in vivo, we have evaluated its application in the diagnosis of the acute form of leptospirosis. The C-terminal coding sequence of ligA (ligA-C) was cloned into pET15b and expressed in Escherichia coli. Furthermore, the B-cell-specific epitopes were predicted and were synthesized as peptides for evaluation along with recombinant LigA-C. Epitope 1 (VVIENTPGK), with a VaxiJen score of 1.3782, and epitope 2 (TALSVGSSK), with a score of 1.2767, were utilized. A total of 140 serum samples collected from leptospirosis cases during the acute stage of the disease and 138 serum samples collected from normal healthy controls were utilized for evaluation. The sensitivity, specificity, positive predictive value, and negative predictive value were calculated for the recombinant LigA-C-specific IgM enzyme-linked immunosorbent assay (ELISA) and were found to be 92.1%, 97.7%, 92.8%, and 97.5%, respectively. Epitopes 1 and 2 used in the study showed 5.1 to 5.8% increased sensitivity over recombinant LigA-C in single and combination assays for IgM antibody detection. These findings suggest that these peptides may be potential candidates for the early diagnosis of leptospirosis. PMID:24403522

Kanagavel, Murugesan; Shanmughapriya, Santhanam; Anbarasu, Kumarasamy

2014-01-01

344

Verifying high NA polarization OPC treatment on wafer  

NASA Astrophysics Data System (ADS)

High NA scanners with adjustable polarization are becoming commercially available. Linear polarization has been shown to significantly improve imaging performance of preferentially oriented lines. Azimuthal and tangential polarization are now becoming commercially available. The latter has less asymmetry in its imaging and can resolve critical features oriented in multiple directions at the same time. Linear y-oriented or vertical polarization was used, since at the time of this work, azimuthal and tangential polarization were not available. Such x- and y-oriented linear polarization could be used in double exposure imaging, for example. Just as for unpolarized imaging, OPC models are required for polarized imaging that are accurate in (a) fitting and predicting experimental CD values, (b) fragmenting layout, and (c) correcting the fragmented layout to target. This paper describes the results of such a first OPC verification loop. Experimental proximity data in X- and Y-orientation were measured. Source polarization and wafer stack thin film effects were included in the empirically fit OPC simulation model. A parallel investigation was undertaken using an unpolarized source. It served as the reference case. Simple test patterns as well product-like 2D layout was treated with the vertically polarized and unpolarized OPC models. A test mask was written and wafer printing results obtained. They demonstrated the validity of the approach and pointed to further OPC model improvements.

Schlief, Ralph E.; Hennig, Mario; Pforr, Rainer; Thiele, Jörg; Hoepfl, Max

2006-03-01

345

Wafer-fused orientation-patterned GaAs  

NASA Astrophysics Data System (ADS)

The fabrication of thick orientation-patterned GaAs (OP-GaAs) films is reported using a two-step process where an OP-GaAs template with the desired crystal domain pattern was prepared by wafer fusion bonding and then a thick film was grown over the template by low pressure hydride vapor phase epitaxy (HVPE). The OP template was fabricated using molecular beam epitaxy (MBE) followed by thermocompression wafer fusion, substrate removal, and lithographic patterning. On-axis (100) GaAs substrates were utilized for fabricating the template. An approximately 350 ?m thick OP-GaAs film was grown on the template at an average rate of ~70 ?m/hr by HVPE. The antiphase domain boundaries were observed to propagate vertically and with no defects visible by Nomarski microscopy in stain-etched cross sections. The optical loss at ~2 ?m wavelength over an 8 mm long OP-GaAs grating was measured to be no more than that of the semi-insulating GaAs substrate. This template fabrication process can provide more flexibility in arranging the orientation of the crystal domains compared to the Ge growth process and is scalable to quasi-phase-matching (QPM) devices operating from the IR to terahertz frequencies utilizing existing industrial foundries.

Li, Jin; Fenner, David B.; Termkoa, Krongtip; Allen, Mark G.; Moulton, Peter F.; Lynch, Candace; Bliss, David F.; Goodhue, William D.

2008-02-01

346

Development of GaN wafers via the ammonothermal method  

NASA Astrophysics Data System (ADS)

This paper reviews the current progress of ammonothermal growth at SixPoint Materials and discusses some of the remaining challenges to commercialize the technology. The mass production of the ammonothermal grown wafers of GaN for high power devices has substantial commercial potential but is currently limited by two problems: impurities which lead to semitransparent coloration and stress in the crystals which leads to cracking. To improve the coloration, it is important to understand and reduce the impurities in the crystal. Oxygen impurities were found to be the primary source of coloration. By reducing the oxygen impurities the absorption coefficient at 450 nm was improved to 3.9 cm-1 yielding semitransparent crystals. The second and more serious issue is a cracking that occurs when thick boules are produced. Currently we routinely produce ammonothermal growth over a millimeter in thickness without any cracking. However, as the thickness increases cracks develop. From a production viewpoint, the production of thick crystals is beneficial since it allows a single wafer to be processed into many. By improving a variety of parameters, the crack density was reduced and the maximum crack-free growth increased from 1 mm to 2.6 mm.

Letts, Edward; Hashimoto, Tadao; Hoff, Sierra; Key, Daryl; Male, Keith; Michaels, Mathew

2014-10-01

347

Process Performance of Optima XEx Single Wafer High Energy Implanter  

NASA Astrophysics Data System (ADS)

To meet the process requirements for well formation in future CMOS memory production, high energy implanters require more robust angle, dose, and energy control while maintaining high productivity. The Optima XEx high energy implanter meets these requirements by integrating a traditional LINAC beamline with a robust single wafer handling system. To achieve beam angle control, Optima XEx can control both the horizontal and vertical beam angles to within 0.1 degrees using advanced beam angle measurement and correction. Accurate energy calibration and energy trim functions accelerate process matching by eliminating energy calibration errors. The large volume process chamber and UDC (upstream dose control) using faraday cups outside of the process chamber precisely control implant dose regardless of any chamber pressure increase due to PR (photoresist) outgassing. An optimized RF LINAC accelerator improves reliability and enables singly charged phosphorus and boron energies up to 1200 keV and 1500 keV respectively with higher beam currents. A new single wafer endstation combined with increased beam performance leads to overall increased productivity. We report on the advanced performance of Optima XEx observed during tool installation and volume production at an advanced memory fab.

Kim, J. H.; Yoon, Jongyoon; Kondratenko, S.; David, J.; Rubin, L. M.; Jang, I. S.; Cha, J. C.; Joo, Y. H.; Lee, A. B.; Jin, S. W.

2011-01-01

348

Dual-Side Wafer Processing and Resonant Tunneling Transistor Applications  

SciTech Connect

We describe dual-side wafer processing and its application to resonant tunneling transistors in a planar configuration. The fabrication technique utilizes a novel flip-chip, wafer thinning process called epoxy-bond and stop-etch (EBASE) process, where the substrate material is removed by selective wet etching and stopped at an etch-stop layer. This EBASE method results in a semiconductor epitaxial layer that is typically less than a micron thick and has a mirror-finish, allowing backside gates to be placed in close proximity to frontside gates. Utilizing this technique, a resonant tunneling transistor--the double electron layer tunneling transistor (DELTT)--can be fabricated in a fully planar configuration, where the tunneling between two selectively-contacted 2DEGs in GaAs or InGaAs quantum wells is modulated by surface Schottky gate. Low temperature electrical characterization yields source-drain I-V curves with a gate-tunable negative differential resistance.

Moon, J.S.; Simmons, J.A.; Wendt, J.R.; Hietala, V.M.; Reno, J.L.; Baca, W.E.; Blount, M.A.

1999-07-20

349

A new concept of p-(n-)\\/p-(n) thin-film epitaxial silicon wafers for MOS ULSI's that ensures excellent gate oxide integrity  

Microsoft Academic Search

A new concept of epitaxial silicon (Si) wafers (NC epi) in which p -(n-) thin-film layers are grown on p-(n-) Czochralski (CZ)-Si substrates (substrate resistivity: approximately 10 ? cm) is proposed for metal oxide semiconductor (MOS) ultra large-scale integrated circuits (ULSI's) as a starting material. A thickness of 0.3-1 ?m for the epitaxial layer (p -\\/p- structure) is shown to

Hirofumi Shimizu; Yuji Sugino; Norio Suzuki; Yasushi Matsuda; Shogo Kiyota; Koichi Nagasawa; Masato Fujita

1998-01-01

350

148 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 1, FEBRUARY 2005 Wafer-Grown Heat Flux Sensor Arrays for Plasma  

E-print Network

the surface of the wafer and also by heat transfer from the backside of the wafer by the chuck and wafer148 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 1, FEBRUARY 2005 Wafer--This paper treats the design, fabrication, and testing of a wafer-grown thermal flux sensor for use in plasma

California at Berkeley, University of

351

New fabrication method of glass packages with inclined optical windows for micromirrors on wafer level  

NASA Astrophysics Data System (ADS)

For many applications it is inevitable to protect MEMS devices against environmental impacts like humidity which can affect their performance. Moreover recent publications demonstrates that micro mirrors can achieve very large optical scan angles at moderate driving voltages even exceeding 100 degrees when hermetically sealed under vacuum. While discrete chips may be evacuated and sealed on single die level using small can packages like TO housings, it is obvious that for high volume production a much more economical solution for the realisation of transparent optical packages already on wafer level must be developed. However, since any laser beam crossing a transparent glass surface is partly reflected even when anti-reflective coatings are applied, the construction of a wafer level optical housing suitable for laser projection purpose requires more than the integration of simple plane glass cap. The use of inclined optical windows avoids the occurrence of intense reflections of the incident laser beam in the projected images. This paper describes a unique technology to fabricate glass packages with inclined optical windows for micro mirrors on 8 inch wafers. The new process uses a high temperature glass forming process based on subsequent wafer bonding. A borosilicate glass wafer is bonded together with two structured silicon wafers. By grinding both sides of the wafer stack, a pattern of isolated silicon structures is defined. This preprocessed glass wafer is bonded thereon on a third structured silicon wafer, wherein the silicon islands are inserted into the cavities. By setting a defined pressure level inside the cavities during the final wafer bonding, the silicon glass stack extruded and it is out of plane during a subsequent annealing process at temperatures above the softening point of the glass. Finally the silicon is selectively removed in a wet etching process. This technique allows the fabrication of 8 inch glass wafers with oblique optical surfaces with surface roughness <1 nm and an evenness of < 300 nm.

Stenchly, Vanessa; Quenzer, Hans-Joachim; Hofmann, Ulrich; Janes, Joachim; Jensen, Björn; Benecke, Wolfgang

2013-03-01

352

Characterization of wafer-level bonded hermetic packages using optical leak detection  

NASA Astrophysics Data System (ADS)

For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2009-07-01

353

Bonding silicon-on-insulator to glass wafers for integrated bio-electronic Hyun S. Kima)  

E-print Network

is a standard glass wafer for anodic bonding.4 While borosilicate glass will work, the expansion coefficients do borosilicate glass is a typical material that con- tains sodium oxide Na2O . The presence of mobile metal ionsBonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits Hyun S. Kima

Eom, Chang Beom

354

Modeling of Power and Energy Transduction of Embedded Piezoelectric Wafer Active Sensors for Structural Health Monitoring  

E-print Network

1 Modeling of Power and Energy Transduction of Embedded Piezoelectric Wafer Active Sensors a systematic investigation of power and energy transduction in piezoelectric wafer active sensors (PWAS a simplified pitch-catch model of power and energy transduction of PWAS attached to structure. The model

Giurgiutiu, Victor

355

Effect of wafer bow on electrostatic chucking and back side gas cooling  

Microsoft Academic Search

Electrostatic chucks (ESCs) are used in the semiconductor industry to clamp wafers to a pedestal and combined with back side gas (BSG) cooling to control temperature during processing. The effect of wafer bow in an ESC\\/BSG system is studied theoretically and experimentally. An equilibrium model is developed that predicts the maximum allowed bow for initial chucking and the maximum BSG

Daniel L. Goodman

2008-01-01

356

Measurement and modeling of time- and spatial-resolved wafer surface temperature in inductively coupled plasmas  

Microsoft Academic Search

The transient temperature profile across a commercial wafer temperature sensor device in an inductively coupled Ar plasma is reported. The measured temperatures are compared to model predictions, based on a coupled plasma-wafer model. The radial temperature profile is the result of the radial profile in the ion energy flux. The ion energy flux profile is obtained by combining the Langmuir

C. C. Hsu; M. J. Titus; D. B. Graves

2007-01-01

357

Influence of pin chuck ring seals and polishing steps on wafer flatness  

Microsoft Academic Search

A site flatness of less than 32nm will be required when fabricating next-generation devices. To flatten warped wafers, a pin chuck is used. This chuck has lift holes for loading and unloading wafers and a ring seal around its periphery. It is known that the lift holes and seal deteriorate local flatness. This paper describes the theoretical local deformation of

Atsunobu Une; Kenichiro Yoshitomi; Masaaki Mochida; Nagahisa Ogasawara

2010-01-01

358

Fine grinding of silicon wafers: a mathematical model for the chuck shape  

Microsoft Academic Search

Fine grinding of silicon wafers is a patented technology to manufacture super flat semiconductor wafers cost-effectively. Two papers on fine grinding were previously published in this journal, one discussed its uniqueness and special requirements, and the other presented the results of a designed experimental investigation. As a follow up, this paper presents a study aiming at overcoming one of the

S. Chidambaram; Z. J. Pei; S. Kassir

2003-01-01

359

www.suss.com LithographyWaferBondingDeviceBondingTesting  

E-print Network

www.suss.com LithographyWaferBondingDeviceBondingTesting MANUAL PROBE SYSTEM PM5 PM5 Solutions manipulators > Large number of accessories available, such as laser cutters and platens & chucks for HF testing > Quick and ergonomic change of DUT through pull-out stage Cost-Effective, Manual Wafer Probing The SUSS

360

Real-time, noninvasive monitoring of ion energy at a wafer surface during plasma etching  

Microsoft Academic Search

Summary form only given. Energetic ion bombardment plays a crucial role in plasma etching. A better understanding and better control of etch processes could be obtained if the energy distributions of ions striking the wafer surface were known. Although it is difficult or impossible to directly measure ion energy distributions at the wafer surface, they can be determined indirectly using

M. A. Sobolewski

2006-01-01

361

FEA thermal investigation on plasma etching induced heating during wafer thinning process  

Microsoft Academic Search

In this work, finite element analysis (FEA) was used to predict transient heating and temperature distribution on the wafer surface during plasma etching process as backgrind (BG) tape degradation after plasma stress relief was observed. The wafer surface temperature during plasma process was measured using temperature indicator strips and used as input temperature for FEA analysis. A series of parametric

Foo Lam Wong; Radimin; M. Teo; C. Lee

2006-01-01

362

Low target power wafer sputtering regime identified during magnetron tantalum barrier physical vapor deposition  

SciTech Connect

A wafer sputtering regime has been identified during tantalum barrier deposition using a magnetron physical vapor deposition (MPVD) tool. The MPVD tools are designed to operate at high target powers (tens of kW) where the highly directed energetic metal (athermal metal) is the dominant metal species incident on the wafer. Although athermal metal gives better coverage than neutral metal (thermal) due to the narrower range of incident strike angles to the wafer, shadowing by the feature geometries is still a concern. Having available a wafer sputter regime or 'resputter' regime in a PVD tool allows for redistribution of metal from horizontal surfaces in the feature exposed to the plasma to vertical surfaces in the feature. The key in obtaining a wafer sputter regime is the operation of the plasma source in a range that the wafer bias power is effective at generating a sufficient self-bias for sputtering to occur. Discussed are modeling results which predict the wafer sputtering regime and the experimental confirmation that the low target power wafer sputter regime exists. The identified sputter regime in MPVD is such that there is a net deposition of metal at the field. Metal thickness reduction does occur at the trench and via bottoms where much of the unionized metal is being shadowed yielding a lower deposition to sputtering ratio compared to the field.

Stout, Phillip J.; Denning, Dean J.; Michaelson, Lynne M.; Bagchi, Sandeep; Zhang Da; Ventzek, Peter L. G. [Freescale Semiconductor, Inc., 3501 Ed Bluestein Boulevard, Austin Texas 78721 (United States)

2005-07-15

363

Compact infrared cryogenic wafer-level camera: design and experimental validation  

E-print Network

Compact infrared cryogenic wafer-level camera: design and experimental validation Florence de la; posted 12 January 2012 (Doc. ID 158765); published 5 March 2012 We present a compact infrared cryogenic, the concept is compatible with both cryogenic constraints and wafer- level fabrication. The design strategy

Boyer, Edmond

364

Wafer fab construction cost analysis and cost reduction strategies: applications of SEMATECH's future factory analysis methodology  

Microsoft Academic Search

This paper discusses semiconductor wafer fabrication (fab) factory construction costs as they relate to emerging technologies. The generation of factories studied represents facilities supporting 200 mm wafers, and products utilizing 0.25 micron line-width geometries. An analytical approach to categorizing and evaluating fab costs is presented. A pareto analysis of four recent factories' costs is presented. The organization of fab construction

David Art; Michael O'Halloran; Brian Butler

1994-01-01

365

YBCO wafer qualification by surface resistance measurements combined with performance studies of microstrip resonators  

Microsoft Academic Search

High quality double-sided YBCO wafers with ceria buffered sapphire substrates are analysed for the lateral homogeneity and field dependence of the surface resistance (RS) using an open resonator at 145 GHz and a dielectric resonator at 8.5 GHz. In a following step, a set of linear microstrip resonators are patterned on these wafers and are analysed for their high frequency

R. Schwab; E. Gaganidze; J. Halbritter; R. Heidinger; R. Aidam; R. Schneider

2001-01-01

366

High rate etching of sapphire wafer using Cl 2\\/BCl 3\\/Ar inductively coupled plasmas  

Microsoft Academic Search

Sapphire wafers which are generally used for the fabrication of GaN-based optoelectronic devices are found to be very difficult in lapping, polishing, and cutting for packaging due to the chemical stability and hardness of sapphire. To study possibilities of replacing some of these processes by dry etching, (0001) sapphire wafers were etched using inductively coupled plasmas as a function of

Y. J. Sung; H. S. Kim; Y. H. Lee; J. W Lee; S. H. Chae; Y. J. Park; G. Y. Yeom

2001-01-01

367

SILICON PROCESSING 1. THE TRUE SURFACE TEMPERATURE OF A SILICON WAFER  

E-print Network

701 SILICON PROCESSING 1. THE TRUE SURFACE TEMPERATURE OF A SILICON WAFER AND THE RELATED ETCH RATE structure diffused into the surface of a silicon wafer the temperature has been found to increase within. The dependence of the etch rate on the surface temperature has been measured. In the interval from R.T. and 100

Boyer, Edmond

368

Wafer based aberration metrology for lithographic systems using overlay measurements on targets  

E-print Network

Wafer based aberration metrology for lithographic systems using overlay measurements on targets projection system from wafer metrology data. For this, new types of phase-shift gratings (PSG) are introduced metrology tool. In this way, the overlay error can be used as a measurand based on which the phase

369

3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces.  

E-print Network

3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces. Journal: 2008 Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces Jian-Qiang Lu1 , J. Jay Mc approaches to 3D integration using adhesive, metal, and metal/adhesive as the bonding interfaces

Salama, Khaled

370

Shock wave assisted removal of micron size dust particles from silicon wafer surfaces  

Microsoft Academic Search

A new high speed rotor device has been designed, fabricated and tested for cleaning (removal of sub-micron size dust particles) silicon wafer surfaces. The 140 mm diameter aluminium rotor with grooves spins at a maximum speed of 50,000 rpm over silicon wafer surfaces placed at a distance of 1 mm from the rotor surface. A sonic argon jet coming out

G. Jagadeesh; M. Mizunaga; K. Shibasaki; S. Shibasaki; T. Saito; K. Takayama

2005-01-01

371

The evaluation of manual FOUP handling in 300-mm wafer fab  

Microsoft Academic Search

Semiconductor manufacturing industry is moving into the production of 300-mm wafers. To solve the increased workload problem in manual wafer handling, some personal guided vehicles (PGVs) have been developed to help in the transfer of front opening unified pods (FOUP). This study compares two kinds of PGVs with a traditional cart and evaluates the feasibility of using them for manual

Mao-Jiun J. Wang; Hsiu-Chen Chung; Hsin-Chieh Wu

2003-01-01

372

High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging  

Microsoft Academic Search

In this paper, we propose an equivalent circuit model of through wafer via which has height of 90 mum and diameter of 75 mum. The equivalent circuit model composed of RLCG components is developed based on the physical configuration of through wafer via. Then, the parameter values of the equivalent circuit model are fitted to the measured s-parameters up to

Chunghyun Ryu; Jiwang Lee; Hyein Lee; Kwangyong Lee; Taesung Oh; Joungho Kim

2006-01-01

373

New formation technology for a plasma display panel barrier-rib structure using a precise metal mold fabricated by the UV-LIGA process  

NASA Astrophysics Data System (ADS)

We present a new formation technology for a plasma display panel (PDP) barrier-rib structure by which we can obtain a barrier-rib with a high aspect ratio and reduce the manufacturing cost. Firstly, a precise metal mould is manufactured for massively replicating the PDP barrier-rib construction using the UV-LIGA process with a thick negative photoresist (SU-8 50: Microchem Corp). The proposed sequence includes several processes: amorphous silicon as an adhesion layer; dipping into xylene and n-butyl acetate after the development of SU-8; two step removal of the SU-8 layer; rip-off process, etc. The proposed processes produce a copper mould with a high aspect ratio, good surface roughness and a uniform thickness. Secondly, a PDP barrier-rib structure is formed using the roll-pressing method with a reusable metal mould fabricated by the proposed UV-LIGA process. This is a very simple and inexpensive method consisting of printing the barrier-rib paste, drying, roll-pressing and firing. Consequently, by combining the UV-LIGA and roll-pressing processes, the desired barrier-rib shapes can be made with a high aspect ratio and various dimensions. The combination of the UV-LIGA and roll-pressing processes also demonstrates the possibility of achieving two major goals in the barrier-rib processes; i.e., developing a barrier-rib structure with a high aspect ratio that can be applied to high-definition televisions, and reducing the manufacturing cost.

Son, Seung-Hyun; Park, Yong-Suk; Choi, Sie-Young

2002-01-01

374

Second harmonic generation and optical parametric amplification in the mid-IR with orthorhombic biaxial crystals LiGaS2 and LiGaSe2  

NASA Astrophysics Data System (ADS)

By second harmonic generation in and out of the principal planes we estimated the three nonlinear coefficients of the Li-containing mid-IR crystals LiGaS2 and LiGaSe2 which are isostructural to LiInS2 and LiInSe2 and possess even larger bandgaps. First results on optical parametric amplification reveal their advantages for direct down conversion to the mid-IR.

Petrov, V.; Yelisseyev, A.; Isaenko, L.; Lobanov, S.; Titov, A.; Zondy, J.-J.

375

Ultrathick SU8 mold formation and removal, and its application to the fabrication of LIGA-like micromotors with embedded roots  

Microsoft Academic Search

In this study, a novel method to completely remove crosslinked SU-8 without remnants of the resist or destroying the electroplated microstructures was utilized. The LIGA-like fabrication of a side-driven electrostatic micromotor was employed as an example to describe polymerized SU-8 resist removal. Using near-UV light, nickel components of the micromotor were electroplated 160?m in a 300?m-thick SU-8 mold. A comparison

Chien-Hung Ho; Kan-Ping Chin; Chii-Rong Yang; Hsien-Ming Wu; Soon-Lin Chen

2002-01-01

376

Chemical strategies for die/wafer submicron alignment and bonding.  

SciTech Connect

This late-start LDRD explores chemical strategies that will enable sub-micron alignment accuracy of dies and wafers by exploiting the interfacial energies of chemical ligands. We have micropatterned commensurate features, such as 2-d arrays of micron-sized gold lines on the die to be bonded. Each gold line is functionalized with alkanethiol ligands before the die are brought into contact. The ligand interfacial energy is minimized when the lines on the die are brought into registration, due to favorable interactions between the complementary ligand tails. After registration is achieved, standard bonding techniques are used to create precision permanent bonds. We have computed the alignment forces and torque between two surfaces patterned with arrays of lines or square pads to illustrate how best to maximize the tendency to align. We also discuss complex, aperiodic patterns such as rectilinear pad assemblies, concentric circles, and spirals that point the way towards extremely precise alignment.

Martin, James Ellis; Baca, Alicia I.; Chu, Dahwey; Rohwer, Lauren Elizabeth Shea

2010-09-01

377

Precise Fabrication of Silicon Wafers Using Gas Cluster Ion Beams  

SciTech Connect

Precise surface processing of a silicon wafer was studied by using a gas cluster ion beam (GCIB). The damage caused to the silicon surface was strongly dependent on irradiation parameters. The extent of damage varied with the species of source gas and the acceleration voltage (Va) of cluster ions. It also varied with the cluster size and residual gas pressure. The influence of electron acceleration voltage (Ve) used for ionization of a neutral cluster was also investigated. The irradiation damage, such as an amorphous silicon (a-Si) layer, a mixed layer of a-Si and c-Si (transition layer), and surface roughness, was increased with Ve. It is suggested that the increase in the amount of energy per atom was induced by high Ve, because of variation of the cluster size and/or cluster charge. An undamaged smooth surface can be produced by Ar-GCIB irradiation at low Ve and Va.

Isogai, Hiromichi [Processing Technology, Silicon Business Group, Covalent Materials Corporation, 6-861-5 Higashikou Seirou-machi, Kitakanbaragun, Niigata 957-0197 (Japan); Graduate School of Engineering, University of Hyogo, 2167 Syosya, Himeji City, Hyogo 671-2280 (Japan); Toyoda, Eiji; Izunome, Koji [Processing Technology, Silicon Business Group, Covalent Materials Corporation, 6-861-5 Higashikou Seirou-machi, Kitakanbaragun, Niigata 957-0197 (Japan); Kashima, Kazuhiko [New Business Creation, Covalent Material Corporation, 30 Soya, Hadano City, Kanagawa 257-0031 (Japan); Mashita, Takafumi; Toyoda, Noriaki; Yamada, Isao [Graduate School of Engineering, University of Hyogo, 2167 Syosya, Himeji City, Hyogo 671-2280 (Japan)

2009-03-10

378

A Wafer Transfer Technology for MEMS Adaptive Optics  

NASA Technical Reports Server (NTRS)

Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

Yang, Eui-Hyeok; Wiberg, Dean V.

2001-01-01

379

Visible luminescence from silicon wafers subjected to stain etches  

NASA Technical Reports Server (NTRS)

Etching of Si in a variety of solutions is known to cause staining. These stain layers consist of porous material similar to that produced by anodic etching of Si in HF solutions. In this work, photoluminescence peaked in the red from stain-etched Si wafers of different dopant types, concentrations, and orientations produced in solutions of HF:HNO3:H2O was observed. Luminescence is also observed in stain films produced in solutions of NaNO2 in HF, but not in stain films produced in solutions of CrO3 in HF. The luminescence spectra are similar to those reported recently for porous Si films produced by anodic etching in HF solutions. However, stain films are much easier to produce, requiring no special equipment.

Fathauer, R. W.; George, T.; Ksendzov, A.; Vasquez, R. P.

1992-01-01

380

Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint  

SciTech Connect

Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

Johnston, S.; Yan, F.; Zaunbracher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

2011-07-01

381

Shock wave assisted removal of micron size dust particles from silicon wafer surfaces  

NASA Astrophysics Data System (ADS)

A new high speed rotor device has been designed, fabricated and tested for cleaning (removal of sub-micron size dust particles) silicon wafer surfaces. The 140 mm diameter aluminium rotor with grooves spins at a maximum speed of 50,000 rpm over silicon wafer surfaces placed at a distance of 1 mm from the rotor surface. A sonic argon jet coming out of the rotor surface is also used to enhance the wafer cleaning process. The tungsten particles (0.7 ?) are removed successfully from both plain and patterned silicon wafer surfaces. However it was not possible to remove 0.1 ? aluminium dioxide particles from the wafer surfaces. Details of the study are presented in this paper.

Jagadeesh, G.; Mizunaga, M.; Shibasaki, K.; Shibasaki, S.; Saito, T.; Takayama, K.

382

Photostimulated near-infrared persistent luminescence as a new optical read-out from Cr3+-doped LiGa5O8  

PubMed Central

In conventional photostimulable storage phosphors, the optical information written by x-ray or ultraviolet irradiation is usually read out as a visible photostimulated luminescence (PSL) signal under the stimulation of a low-energy light with appropriate wavelength. Unlike the transient PSL, here we report a new optical read-out form, photostimulated persistent luminescence (PSPL) in the near-infrared (NIR), from a Cr3+-doped LiGa5O8 NIR persistent phosphor exhibiting a super-long NIR persistent luminescence of more than 1,000?h. An intense PSPL signal peaking at 716?nm can be repeatedly obtained in a period of more than 1,000?h when an ultraviolet-light (250–360?nm) pre-irradiated LiGa5O8:Cr3+ phosphor is repeatedly stimulated with a visible light or a NIR light. The LiGa5O8:Cr3+ phosphor has promising applications in optical information storage, night-vision surveillance, and in vivo bio-imaging. PMID:23532003

Liu, Feng; Yan, Wuzhao; Chuang, Yen-Jun; Zhen, Zipeng; Xie, Jin; Pan, Zhengwei

2013-01-01

383

Defect characterization and light scattering by PSL spheres on tungsten CMP wafers  

NASA Astrophysics Data System (ADS)

Chemical mechanical polishing (CMP) generates unique difficulties for defect metrology using wafer scanners. Polishing residue, scratches, pits, normal contaminant particles and the pattern covered by the planarized material provide scattering signatures that differ from normal patterned or unpatterned wafers. This relatively young application area for wafer inspection instruments needs a rapid infusion of experience and knowledge infrastructure in order to bring it along to the level of more conventional applications. To that end, a series of relevant experiments have been completed on three types of tungsten (W) CMP test wafers including (1) partially-polished blanket W, (2) fully-polished blanket wafers (polished to oxide), and (3) fully-polished patterned W wafers. Various contamination particles and defects on these wafers were characterized and identified by means of optical microscopy, surface scanning inspection, scanning electron microscopy, energy-dispersive x-ray spectrometry, and atomic force microscopy. A number of defect types including: particles of polished material, substrate, abrasive, oxidizer, and chemical products of polished material and oxidizer; scratches; and pits were expected based on an analysis of the CMP process, and were thereafter confirmed by experiment. Surface roughness was measured on the two types of blanket wafers. W line roughness and dishing depth were measured as a function of line width and pattern density on the patterned W wafers. For light scattering experiments, 0.482 micrometers polystyrene latex spheres were deposited on a patterned W CMP test wafer. Differential light scattering cross sections of particles located in the 0.5 micrometers line/1.0 micrometers pitch region at various locations relative to the W lines were then measured at 488 nm wavelength using the Arizona State University scatterometer.

Ding, Ping; Starr, Greg W.; Chowdhury, Rina; Hirleman, E. Dan

1997-09-01

384

Minority carrier lifetime and iron concentration measurements on p-Si wafers by infrared photothermal radiometry and microwave  

E-print Network

of semiconductor wafers directly affect the performance of various devices fabricated on these wafers. In recent sur- face, an intensity-modulated laser beam simultaneously pro- duces direct lattice heating due

Mandelis, Andreas

385

Infrared differential interference contrast microscopy for overlay metrology on 3D-interconnect bonded wafers  

NASA Astrophysics Data System (ADS)

Overlay metrology for stacked layers will be playing a key role in bringing 3D IC devices into manufacturing. However, such bonded wafer pairs present a metrology challenge for optical microscopy tools by the opaque nature of silicon. Using infrared microscopy, silicon wafers become transparent to the near-infrared (NIR) wavelengths of the electromagnetic spectrum, enabling metrology at the interface of bonded wafer pairs. Wafers can be bonded face to face (F2F) or face to back (F2B) which the stacking direction is dictated by how the stacks are carried in the process and functionality required. For example, Memory stacks tend to use F2B stacking enables a better managed design. Current commercial tools use single image technique for F2F bonding overlay measurement because depth of focus is sufficient to include both surfaces; and use multiple image techniques for F2B overlay measurement application for the depth of focus is no longer sufficient to include both stacked wafer surfaces. There is a need to specify the Z coordinate or stacking wafer number through the silicon when visiting measurement wafer sites. Two shown images are of the same (X, Y) but separate Z location acquired at focus position of each wafer surface containing overlay marks. Usually the top surface image is bright and clear; however, the bottom surface image is somewhat darker and noisier as an adhesive layer is used in between to bond the silicon wafers. Thus the top and bottom surface images are further processed to achieve similar brightness and noise level before merged for overlay measurement. This paper presents a special overlay measurement technique, using the infrared differential interference contrast (DIC) microscopy technique to measure the F2B wafer bonding overlay by a single shot image. A pair of thinned wafers at 50 and 150 ?m thickness is bonded on top of a carrier wafer to evaluate the bonding overlay. It works on the principle of interferometry to gain information about the optical path length of the stacked wafers, to enhance the image contrast of overlay marks features even though they are locating in different Z plane. A two dimensional mirror-symmetric overlay marks for both top and bottom processing wafers is designed and printed in each die in order to know and realize the best achievable wafer to wafer bonding processing. A self-developed analysis algorithms is used to identify the overlay error between the stacking wafers and the interconnect structures. The experimental overlay results after wafer bonding including inter-die and intra-die analysis results will be report in the full paper. Correlation of overlay alignment offset data to electrical yield, provides an early indication of bonded wafer yield.

Ku, Yi-sha; Shyu, Deh-Ming; Lin, Yeou-Sung; Cho, Chia-Hung

2013-04-01

386

Fabrication of an ultrathin silicon wafer with a honeycomb structure by the thermal-stress-induced pattern transfer (TIPT) method  

NASA Astrophysics Data System (ADS)

A 3 µm thick silicon thin film with a textured surface was fabricated successfully by three major steps. First, the silicon thin film was deposited on a sapphire substrate by a plasma-enhanced chemical vapor deposition system. Second, metal paste was printed on the silicon thin film. Third, a thermal treatment was applied on the sapphire substrate. After cooling, the silicon layer, combined with the metal paste, was peeled from the sapphire substrate because of the large differences in the thermal expansion coefficient between the silicon-metal composite layer and the sapphire substrate. An ultrathin silicon wafer of 3 µm thickness was obtained in this study. Furthermore, a silicon layer with a micro-scale and a nano-scale honeycomb structures can be obtained easily by transferring patterns from the well-designed patterned sapphire substrate.

Wang, Teng-Yu; Chen, Chien-Hsun; Du, Chen-Hsun; Kung, Chung-Yuan

2012-05-01

387

SILICON-EMBEDDED 3D TOROIDAL AIR-CORE INDUCTOR WITH THROUGH-WAFER INTERCONNECT FOR ON-CHIP INTEGRATION  

E-print Network

3D toroidal inductor is fabricated in a deep silicon trench, and is coupled to the wafer surfaceSILICON-EMBEDDED 3D TOROIDAL AIR-CORE INDUCTOR WITH THROUGH-WAFER INTERCONNECT FOR ON with high-power, electroplated through-wafer interconnect. Inductors fabricated in these trenches achieved

388

Novel variable-temperature chuck for use in the detection of deep levels in processed semiconductor wafers  

Microsoft Academic Search

This paper describes the design, construction, and characterization of a variable-temperature wafer apparatus for use in the detection of electrically active defects which produce deep levels in the band gap of silicon. In its present form, the wafer chuck can heat and cool wafers as large as 51 mm in diameter over the temperature range from -196 to 350 C.

R. Y. Koyama; M. G. Buehler

1979-01-01

389

Novel variable-temperature chuck for use in the detection of deep levels in processed semiconductor wafers  

Microsoft Academic Search

This paper describes the design, construction, and characterization of a variable-temperature wafer apparatus for use in the detection of electrically active defects which produce deep levels in the band gap of silicon. In its present form, the wafer chuck can heat and cool wafers as large as 51 mm in diameter over the temperature range from ?196° to 350°C. Heating

R. Y. Koyama; M. G. Buehler

1979-01-01

390

Second-order sound field during megasonic cleaning of patterned silicon wafers: Application to ridges and trenches  

E-print Network

Second-order sound field during megasonic cleaning of patterned silicon wafers: Application MHz. The direction of propagation differs whether one cleans a single wafer or multiple wafers are processed simul- taneously. Despite the success of this technology, the actual clean- ing mechanism is still

Deymier, Pierre

391

Mapping of Defects in Large-Area Silicon Carbide Wafers via Photoluminescence and its Correlation with Synchrotron White Beam X-ray Topography  

SciTech Connect

Comparative studies of defect microstructure in 4H-SiC wafers have been carried out using photoluminescence (PL) imaging and grazing-incidence Synchrotron White Beam X-ray Topography. Images of low angle grain boundaries on the PL images correlate well with SWBXT observations, and similar correlation can be established for some micropipe images although the latter is complicated by the overall level of distortion and misorientation associated with the low angle grain boundaries and the fact that many of the micropipes are located in or close to the boundaries. This validation indicates that PL imaging may provide a rapid way of imaging such defect structures in large-scale SiC wafers.

Chen, Y.; Balaji, R; Dudley, M; Murthy, M; Freitas Jr., J; Maximenko, S

2009-01-01

392

Mapping of Defects in Large-Area Silicon Carbide Wafers via Photoluminescence and its Correlation with Synchrotron White Beam X-Ray Topography  

SciTech Connect

Comparative studies of defect microstructure in 4H-SiC wafers have been carried out using photoluminescence (PL) imaging and grazing-incidence Synchrotron White Beam X-ray Topography. Images of low angle grain boundaries on the PL images correlate well with SWBXT observations, and similar correlation can be established for some micropipe images although the latter is complicated by the overall level of distortion and misorientation associated with the low angle grain boundaries and the fact that many of the micropipes are located in or close to the boundaries. This validation indicates that PL imaging may provide a rapid way of imaging such defect structures in large-scale SiC wafers.

Chen, Yi; Balaji, R.; Dudley, Michael; Murthy, Madhu; Maximenko, Serguei I.; Freitas, Jamie A.; (SBU); (George Mason); (NRL)

2008-12-12

393

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss  

NASA Astrophysics Data System (ADS)

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 ?m) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-05-01

394

Edge printability: techniques used to evaluate and improve extreme wafer edge printability  

NASA Astrophysics Data System (ADS)

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

2004-05-01

395

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.  

PubMed

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180??m) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping. PMID:24820403

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-01-01

396

Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers  

NASA Technical Reports Server (NTRS)

A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

Okojie, Robert S. (Inventor)

2002-01-01

397

AWV: high-throughput cross-array cross-wafer variation mapping  

NASA Astrophysics Data System (ADS)

Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision (TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

Yeo, Jeong-Ho; Lee, Byoung-Ho; Lee, Tae-Yong; Greenberg, Gadi; Meshulach, Doron; Ravid, Erez; Levi, Shimon; Kan, Kobi; Shabtay, Saar; Cohen, Yehuda; Rotlevi, Ofer

2008-03-01

398

Low temperature solder process to join a copper tube to a silicon wafer  

NASA Astrophysics Data System (ADS)

With the application for wafer level packages, which could be Complementary Metal-Oxide-Semiconductor (CMOS) based, and which requires a reduced atmosphere, a copper tube connection to a vacuum pump and the package is proposed. The method evaluated uses laser assisted brazing of a solder, to join the copper tube to a silicon wafer. The method was applied to a silicon wafer coated with a metallic interface to bond to the solder. The hermeticity of the joint was tested with a helium leak rate tester and the bonding energy thermal extent was verified with a thin layer of indium that melted wherever the substrate temperature rose above its melting temperature.

Versteeg, Christo; Scarpim de Souza, Marcio

2014-06-01

399

W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas  

NASA Technical Reports Server (NTRS)

Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

1997-01-01

400

Correlation of 150-mm silicon wafer site flatness with stepper performance for deep submicron applications  

NASA Astrophysics Data System (ADS)

An experimental study was conducted to correlate wafer site flatness SFQD with stepper performance for half-micron lines and spaces. CD measurements were taken on wafers patterned on both GCA pre-production XLS i-line and SVGL Micrascan-90 DUV steppers as well as focus measurements on the Micrascan-90. Wafer site flatness SFQD less than 0.3 micrometers was observed to be a sufficiently small variable in CD non-uniformities for these initial half-micron stepper applications.

Huff, Howard R.; Vigil, Joseph C.; Kuyel, Birol; Chan, David Y.; Nguyen, Long P.

1992-06-01

401

Development of a fixed abrasive slicing technique (FAST) for reducing the cost of photovoltaic wafers  

SciTech Connect

This report examines a wafer slicing technique developed by Crystal Systems, Inc. that reduces the cost of photovoltaic wafers. This fixed, abrasive slicing technique (FAST) uses a multiwire bladepack and a diamond-plated wirepack; water is the coolant. FAST is in the prototype production stage and reduces expendable material costs while retaining the advantages of a multiwire slurry technique. The cost analysis revealed that costs can be decreased by making more cuts per bladepack and slicing more wafers per linear inch. Researchers studied the degradation of bladepacks and increased wirepack life. 21 refs.

Schmid, F. (Crystal Systems, Inc., Salem, MA (United States))

1991-12-01

402

Development of thin edgeless silicon pixel sensors on epitaxial wafers  

NASA Astrophysics Data System (ADS)

The paper reports on the development of novel p-on-n thin edgeless planar pixel sensors, compatible with ALICE front-end electronics, fabricated by FBK on epitaxial material. The focus of the activity is the minimization of the material budget required for hybrid pixel detectors. This goal has been addressed in two different stages. In the first one, planar pixel detectors fabricated on epitaxial wafers have been thinned and bonded to the readout chips. The second stage is described by the present paper: the `active edge' concept has been studied for the reduction of the dead area at the periphery of the devices. An overview of the key technological steps and of the electrical characterization of the fabricated sensors is given. In addition, the preliminary results on the static behavior of test sensors after neutron irradiation at different fluences (up to 2.5 × 1015 1 MeV-neq/cm2) are reported. The results demonstrate that these kinds of devices are a viable solution for the reduction of the material budget while maintaining the typical electrical characteristics expected from radiation silicon sensors.

Boscardin, M.; Bosisio, L.; Contin, G.; Giacomini, G.; Manzari, V.; Orzan, G.; Rashevskaya, I.; Ronchin, S.; Zorzi, N.

2014-09-01

403

OPC hotspot identification challenges: ORC vs. PWQ on wafer  

NASA Astrophysics Data System (ADS)

The identification of OPC induced litho hotspots within the product design is essential and a must to make sure that a new OPC model is working correctly and does no harm to the design and future product. Several techniques and methods for OPC verification and identification of hotspots are known and long adopted within the field. An optical rule check done by the simulation software after OPC is one way of identifying hotspots within the design of the whole chip. This is typically done by using a DRC-type width or space check on simulation contours (nominal exposure contour or process window contours). However, the pass/fail nature of this check at a single CD value requires good calibration of the simulation model to avoid false positives and ease of disposition at tapeout. Another method is the process window qualification method which uses the defect inspection of a focus exposure matrix wafer for OPC hotspot identification. However, this can not be done prior to ordering a mask. Based on a 45nm line space layer OPC qualification, we will demonstrate how optical rule check and process window qualification is performed, what the individual results will be, and how they can be used for OPC quality evaluation. The general goal of this work is to show the capabilities of optical rule check and process window qualification, compare both methods, and detect limitations.

Poock, Andre; McGowan, Sarah; Weisbuch, Francois; Schnasse, Guido; Ghaskadvi, Rajesh

2008-10-01

404

High-efficiency microdrilling of silicon wafer using excimer laser  

NASA Astrophysics Data System (ADS)

Drilling rate of thin silicon wafer of 50(mu) thickness was determined as a function of beam diameter and laser fluence of KrF excimer laser with a pulse width of approximately 30ns FMHW. Analysis of drilling process indicated that decreasing beam diameter and laser fluence enhanced the drilling rate with improved quality of the drilled hole. The extent of debris and molten particles ejected from the hole was also reduced as the laser fluence was decreased. The drilling rate, approximately 0.6(mu) per pulse at beam diameters larger than 100(mu) , increased significantly as the beam diameter decreased especially below 20(mu) , reaching approximately as large as 4(mu) per pulse at 10(mu) in diameter under constant laser fluence. On the other hand, only very small increase in drilling rate was observed as the laser fluence was increased. A simple formula was derived where the drilling rate is proportional to the fourth root of the laser fluence and inversely proportional to the square root of the beam diameter, assuming that the silicon is removed in a liquid state out of the hole.

Asada, Shinsuke; Sano, Tomokazu; Miyamoto, Isamu

2000-11-01

405

An electromagnetic actuated microvalve fabricated on a single wafer  

NASA Astrophysics Data System (ADS)

Microvalves are essential components of the miniaturization of the fluidic systems to control of fluid flow in a variety of applications as diverse as chemical analysis systems, micro-fuel cells, and integrated fluidic channel arrangements for electronic cooling. Using microvalves, these systems offer important advantages: they can operate using small sample volumes and provide rapid response time. This PhD dissertation presents the world first electromagnetically actuated microvalve fabricated on a single wafer with CMOS compatibility. In this dissertation, the design, fabrication, and testing results of two different types of electromagnetic microvalves are presented: the on/off microvalve and the bistable microvalve with latching mechanism. The microvalves operate with power consumption of less than 1.5 W and can control the volume flow rate of DI water, or a 50% diluted methanol solution in the range 1--50 muL/min. The leaking rate of the on/off microvalve is the order of 30 nL/min. The microvalve demonstrated a response time for latching of 10 ms in water and 0.2 ms in air. This work has resulted in a US patent, application no. 10/699,210. Other inventions that have been developed as a result of this research are bidirectional, and bistable-bidirectional microactuators with latching mechanism, that can be utilized for optical switch, RF relay, micro mirror, nano indenter, or nano printings.

Sutanto Bintoro, Jemmy

406

Role of oxide thickening in fatigue crack initiation in LIGA nickel MEMS thin films  

E-print Network

measurements of plasticity length scales. The initial work on stress-life behavior showed that the fatigue of South Africa, Private Bag X34, Lynnwood Ridge, 0040, South Africa g Department of Materials Science potential applications in accelerometers for the development of air bags [4] and micro- motors [5]. Since

Shan, Wanliang

407

Room-temperature GaAs/InP wafer bonding with extremely low resistance  

NASA Astrophysics Data System (ADS)

Low-temperature direct wafer bonding is a promising technique for fabricating multijunction solar cells with more than four junctions in order to obtain high conversion efficiencies. However, it has been difficult to reduce the bond interface resistance between a GaAs-based subcell wafer and an InP-based subcell wafer. We found that a novel bonding structure comprising heavily Zn-doped (1 × 1019 cm?3) p+-GaAs and S-doped (3 × 1018 cm?3) n-InP had an interface resistance of 2.5 × 10?5 ?·cm2, which is the lowest value ever reported. This result suggests that the newly developed room-temperature wafer bonding technique has high potential to realize high-efficiency multijunction solar cells.

Uchida, Shiro; Watanabe, Tomomasa; Yoshida, Hiroshi; Tange, Takashi; Arimochi, Masayuki; Ikeda, Masao; Dai, Pan; He, Wei; Ji, Lian; Lu, Shulong; Yang, Hui

2014-11-01

408

Effect of wafer bow on electrostatic chucking and back side gas cooling  

NASA Astrophysics Data System (ADS)

Electrostatic chucks (ESCs) are used in the semiconductor industry to clamp wafers to a pedestal and combined with back side gas (BSG) cooling to control temperature during processing. The effect of wafer bow in an ESC/BSG system is studied theoretically and experimentally. An equilibrium model is developed that predicts the maximum allowed bow for initial chucking and the maximum BSG pressure once the wafer is chucked. Experimental chucking and BSG pressure data show the maximum initial bow that can be chucked agree with model predictions. Hysteresis in pressure versus flow data is also consistent with the model. The model does not predict some features of thin wafers with highly stressed films. However, deviations between the model and data in this nonlinear regime are expected. By combining the theory with the experimental data, a method to determine a safe BSG/ESC operating range is given.

Goodman, Daniel L.

2008-12-01

409

Variable isotropy Deep RIE process for through wafer via holes manufacturing  

NASA Astrophysics Data System (ADS)

This paper reports a method on the manufacturing of through wafer via holes in silicon with tapered walls by Deep Reactive Ion Etching (DRIE) using the opportunity to change the isotropy in the DRIE equipments during processing. By using consecutively anisotropic and isotropic etching steps it is possible to enlarge the dimension of via holes on one side of the wafer, while on the other side dimension is set by the initial etching window. The method was used for two etching windows sizes (100?m and 20?m respectively) on 200?m and 300?m thick wafers. The aim was to manufacture tapered walls via having a good control over the walls angle. Different Bosch process recipes providing different walls roughness were used. Via holes with tapered walls (2° to 22°) were manufactured using this method. An angle deviation smaller than 10% of the manufactured via holes along the wafers was observed.

Vasilache, Dan; Colpo, Sabrina; Giacomozzi, Flavio; Ronchin, Sabina; Qureshi, Abdul Qader Ahsan; Margesin, Benno

2011-06-01

410

Understanding the effects of larger wafers on the global semiconductor equipment supply chain  

E-print Network

This thesis examines how an investment in 450mm wafers might affect capital equipment suppliers in the semiconductor industry and assesses if the 450mm transition is in the industry's best interest. The 450mm transition ...

George, Daniel (Daniel Geer)

2009-01-01

411

Scanning Photovoltage Technique for High Resolution Non-Destructive Characterization of Semiconductor Wafers.  

National Technical Information Service (NTIS)

Near-surface defects in semiconductor wafers have a primary influence upon device properties, both, the yield and radiation hardness. In phase I of this program, a scanning photovoltage (SPV) technique was experimentally evaluated for the high-resolution,...

L. J. Palkuti, A. A. Milgram

1985-01-01

412

Planarization machining of sapphire wafers with boron carbide and colloidal silica as abrasives  

NASA Astrophysics Data System (ADS)

The as-cutted sapphire wafers are planarized by the grinding and polishing two-step machining processes with micrometer B 4C and nanometer silica as abrasives, respectively. The material removal rates (MRRs) of two processes are measured. During the polishing process, the MRR increases with the down-pressure increased, whereas the rotational speeds have less effect on the MRR. The alkaline colloidal silica is more favorable than the acidic to polish sapphire wafer. The ground and polished surfaces of the substrate are compared by scanning electron microscopy, atomic force microscopy, and X-ray rocking curves. Our results show that B 4C abrasives are effective in elimination of the ununiformity in thickness within a wafer. The colloidal silica can achieve a nanoscale flatness of wafer, but the lasting polishing time seems unfavorable. The polishing process is also analyzed in terms of chemical mechanical polishing mechanism.

Hu, XiaoKai; Song, Zhitang; Pan, Zhongcai; Liu, Weili; Wu, LiangCai

2009-07-01

413

Standardizing and improving test wafer processes : inventory optimization and a days of inventory pull system  

E-print Network

Over the past few years, the Intel Fab-17 facility has aggressively pursued lean methodology to reduce the manufacturing costs associated with its aging 200mm diameter wafer process. One area ripe with improvement opportunities ...

Johnson, David W. (David William), S.M. Massachusetts Institute of Technology

2009-01-01

414

Characterization and control of wafer charging effects during high-current ion implantation  

SciTech Connect

EEPROM-based sense and memory devices provide direct measures of the charge flow and potentials occurring on the surface of wafers during ion beam processing. Sensor design and applications for high current ion implantation are discussed.

Current, M.I. [Applied Materials, Santa Clara, CA (United States); Lukaszek, W.; Dixon, W. [Stanford Univ., CA (United States); Vella, M.C. [Lawrence Berkeley Lab., CA (United States); Messick, C.; Shideler, J.; Reno, S. [National Semiconductor, West Jordan, UT (United States)

1994-02-01

415

Fab cycle time improvement through inventory control : a wafer starts approach  

E-print Network

Intel's Colorado Springs wafer fabrication facility, known internally as F23, has undertaken several initiatives to reduce cycle time including High Precision Maintenance (HPM), content reduction through the application ...

Ward, Matthew John

2007-01-01

416

Robust wafer identification recognition based on asterisk-shape filter and high-low score comparison method.  

PubMed

Wafer identifications (wafer ID) can be used to identify wafers from each other so that wafer processing can be traced easily. Wafer ID recognition is one of the problems of optical character recognition. The process to recognize wafer IDs is similar to that used in recognizing car license-plate characters. However, due to some unique characteristics, such as the irregular space between two characters and the unsuccessive strokes of wafer ID, it will not get a good result to recognize wafer ID by directly utilizing the approaches used in car license-plate character recognition. Wafer ID scratches are engraved by a laser scribe almost along the following four fixed directions: horizontal, vertical, plus 45 degrees , and minus 45 degrees orientations. The closer to the center line of a wafer ID scratch, the higher the gray level will be. These and other characteristics increase the difficulty to recognize the wafer ID. In this paper a wafer ID recognition scheme based on an asterisk-shape filter and a high-low score comparison method is proposed to cope with the serious influence of uneven luminance and make recognition more efficiently. Our proposed approach consists of some processing stages. Especially in the final recognition stage, a template-matching method combined with stroke analysis is used as a recognizing scheme. This is because wafer IDs are composed of Semiconductor Equipment and Materials International (SEMI) standard Arabic numbers and English alphabets, and thus the template ID images are easy to obtain. Furthermore, compared with the approach that requires prior training, such as a support vector machine, which often needs a large amount of training image samples, no prior training is required for our approach. The testing results show that our proposed scheme can efficiently and correctly segment out and recognize the wafer ID with high performance. PMID:20011000

Hsu, Wei-Chih; Yu, Tsan-Ying; Chen, Kuan-Liang

2009-12-10

417

Meso-scale machining capabilities and issues  

SciTech Connect

Meso-scale manufacturing processes are bridging the gap between silicon-based MEMS processes and conventional miniature machining. These processes can fabricate two and three-dimensional parts having micron size features in traditional materials such as stainless steels, rare earth magnets, ceramics, and glass. Meso-scale processes that are currently available include, focused ion beam sputtering, micro-milling, micro-turning, excimer laser ablation, femto-second laser ablation, and micro electro discharge machining. These meso-scale processes employ subtractive machining technologies (i.e., material removal), unlike LIGA, which is an additive meso-scale process. Meso-scale processes have different material capabilities and machining performance specifications. Machining performance specifications of interest include minimum feature size, feature tolerance, feature location accuracy, surface finish, and material removal rate. Sandia National Laboratories is developing meso-scale electro-mechanical components, which require meso-scale parts that move relative to one another. The meso-scale parts fabricated by subtractive meso-scale manufacturing processes have unique tribology issues because of the variety of materials and the surface conditions produced by the different meso-scale manufacturing processes.

BENAVIDES,GILBERT L.; ADAMS,DAVID P.; YANG,PIN

2000-05-15

418

Simulation analysis of the connecting transport AMHS in a wafer fab  

Microsoft Academic Search

This paper analyzes the performance of the connecting transport automated material handling system (AMHS) in a wafer fab. Discrete-event simulation models are developed in e-M Plant to study connecting transport in a simplified 300 mm wafer fab. A two-phase experimental approach evaluates the connecting transport. In phase I, the simulation results show that the connecting transport method has a significant

James T. Lin; Fu-Kwun Wang; Chun-Kuan Wu

2003-01-01

419

Investigation of EUV mask defectivity via full-field printing and inspection on wafer  

Microsoft Academic Search

Full-field printing on the ASML Alpha Demo Tool, followed by wafer inspection on a KLA-T 2800, is used to qualify typical defectivity levels of EUV reticles. Mask defects are found as repeaters among multiple dies on wafer. The uniform pattern consists of dense lines and spaces. In a first reticle with 40nm linewidth, high levels of natural defects have been

Rik Jonckheere; Dieter van den Heuvel; Fumio Iwamoto; Nickolay Stepanenko; Alan Myers; Matt Lamantia; Anne-Marie Goethals; Eric Hendrickx; Kurt Ronse

2009-01-01

420

A Study on Wafer-Handling Robot with Coaxial Twin-Shaft Magnetic Fluid Seals  

Microsoft Academic Search

Wafer-handling robot is an important IC equipment in wafer manufacturing system. As such robot works in vacuum environment,\\u000a there is a high requirement for the sealing device of it. Magnetic fluid rotary seal shows the effectiveness in machinery\\u000a operating in a vacuum chamber, and the advantages of simple design, low friction and zero leakage at almost any rotation speed.\\u000a This

Ming Cong; Penglei Dai; Huili Shi

2009-01-01

421

Cleaved GaN facets by wafer fusion of GaN to InP  

Microsoft Academic Search

Basal plane sapphire is a common substrate for the heteroepitaxy of GaN. This presents a challenge for fabrication of cleaved-facet GaN lasers because the natural cleavage planes in (0001) ?-Al2O3 are not perpendicular to the wafer surface. This letter describes a method for achieving perpendicular cleaved facets through wafer fusion that can potentially be used to fabricate GaN based in-plane

R. K. Sink; S. Keller; B. P. Keller; D. I. Babic; A. L. Holmes; D. Kapolnek; S. P. Denbaars; J. E. Bowers; X. H. Wu; J. S. Speck

1996-01-01

422

Platinum\\/palladium thin-film thermocouples for temperature measurements on silicon wafers  

Microsoft Academic Search

A platinum versus palladium thin-film thermocouple system has been established for measuring temperatures on silicon wafers in a rapid thermal processing (RTP) tool. The application includes a silicon wafer with an array of thin-film thermocouples welded to wire thermocouples, used to calibrate radiometric temperature measurements of the RTP tool. The thin-film thermocouples have advantages over present technology using wire thermocouples

Kenneth G. Kreider; Frank DiMeo

1998-01-01

423

Glass wafers bonding via Diels–Alder reaction at mild temperature  

Microsoft Academic Search

In this paper, we introduced a novel bonding method of glass wafers by Diels–Alder reaction at mild temperature. After standard hydroxylization and aminosilylation, two wafers were modified by 2-furaldehyde and maleic anhydride, respectively. Then they were brought into close contact and tightly held with a clamping fixture. A strong bonding could be achieved by annealing for 5h at 200°C. Bonding

Minjie Zhang; Jianying Zhao; Lianxun Gao

2008-01-01

424

A micro-contact and wear model for chemical–mechanical polishing of silicon wafers  

Microsoft Academic Search

A micro-contact and wear model for chemical–mechanical polishing (CMP) of silicon wafers is presented in this paper. The model is developed on the basis of elastic–plastic micro-contact mechanics and abrasive wear theory. The synergetic effects of mechanical and chemical actions are formulated into the model. A close-form equation of material removal rate from the wafer surface is derived relating to

Yongwu Zhao; L Chang

2002-01-01

425

Fabrication and optimization of wafer level SAW filter package using laser via drilling  

Microsoft Academic Search

Wafer level surface acoustic wave (SAW) filter package, 0.8times0.6 mm2, is drilled by laser via process. Via formation for interconnection is based on smaller package manufacture. LT (LiTaO3) which is base material of SAW filter is difficult to drill a small via by RIE (Reactive Ion Etching) because the RIE gets a very small etch rate and has wafer broken

Seung Wook Park; Ju Pyo Hong; Tae Hoon Kim; Si Joong Yang; Job Ha; Tae Ho Kim; Sang Wook Park; Young Do Kweon; Sung Yi

2008-01-01

426

2K PL topography of silicon doped VGF GaAs wafers  

Microsoft Academic Search

We report on full wafer and small area photoluminescence topography investigations of VGF GaAs:Si wafers. The wavelength-specific images exhibit various correlations and anti-correlations. Intensity variations due to competitive radiative and non-radiative recombination processes are mainly due to stoichiometric fluctuations and can be distinguished from those generated by the variation of the silicon dopant concentration. X-ray transmission topograms allow to identify

M. Baeumler; M. Maier; N. Herres; Th. Bünger; J. Stenzenberger; W. Jantz

2002-01-01

427

A wafer charge-up-reducing system of a high-current ion implanter  

NASA Astrophysics Data System (ADS)

A cylindrical target electron shower gun and a charge monitor control system have been developed. The gun has a cylinder closely surrounding the ion beam. The cylinder confines electrons in the ion beam and its vicinity. This makes the gun very effective and the positive/negative charge-up stripe on wafers is minimized, so that positive charge-up can be eliminated without a significant increase of negative charge-up. The charge monitor consists of a small charge pickup chip on the wafer side of the disk and a capacitive sensing system that is on the back side of the disk. This provides a differential signal of the voltage on the charge-up chip. On the chip the voltage is built up depending on the beam condition and the surrounding disk surface condition. The voltage of the chip is very sensitive to changes in the type of wafers and the usage of electron shower, proving the system to be a relative monitor of wafer charge. Combining the monitor and shower gun to make a feedback loop, wafer charge-up becomes controllable. The efficiency of the system is proven by many customer evaluations with their own wafers.

Higuchi, T.; Sato, M.; Tamai, T.

1989-02-01

428

Effect of the doping level on temperature bistability in a silicon wafer  

NASA Astrophysics Data System (ADS)

The influence of the doping level on the effect of the temperature bistability in a silicon wafer upon radiative heat transfer between the wafer and the elements of the heating system is studied. Theoretical transfer characteristics are constructed for a silicon wafer doped with donor and acceptor impurities. These characteristics are compared with the transfer characteristics obtained during heating and cooling of wafers with the hole conduction (with dopant concentrations of 1015, 2 × 1016, and 3 × 1017 cm-3) and electron conduction (with impurity concentrations of 1015 and 8 × 1018 cm-3) in a thermal reactor of the rapid thermal annealing setup. It is found that the width and height of the hysteresis loop decrease with increasing dopant concentration and are almost independent of the type of conduction of the silicon wafer. The critical value of the impurity concentration of both types is 1.4 × 1017 cm-3. For this concentration, the loop width vanishes, and the height corresponds to the minimal value of the temperature jump (˜200 K). The mechanism of temperature bistability in the silicon wafer upon radiative heat transfer is discussed.

Ovcharov, V. V.; Rudakov, V. I.; Prigara, V. P.; Kurenya, A. L.

2014-08-01

429

Investigation of machine compliance uniformity for nanoindentation screening of wafer-supported libraries  

NASA Astrophysics Data System (ADS)

The reliability of nanoindentation results can depend critically on an accurate assessment of the machine compliance term. The common practice is to determine the machine compliance from a small reference specimen, then apply its value to a much larger wafer-supported library. The present study investigates the validity of this approach by thoroughly testing bare 76.2 mm diameter, 410?m thick Si(100) wafers mounted on two vacuum chucks of different design. We find that the small-sample value of the machine compliance is adequate for the majority of the wafer, including areas directly over vacuum rings and a circular center port of ordinary dimensions. However, vacuum chucks with a tweezer slot should be avoided in combinatorial materials science applications. But even in the absence of a tweezer slot, it may be necessary to generate an accurate machine compliance map for the wafer perimeter if the thin-film library extends beyond the outermost vacuum ring to the wafer edge. The Young's modulus and the hardness of silicon are found to be 169±3GPa and 12.2±0.2GPa, respectively, over well-mounted regions of the wafer; both values are in good agreement with the literature.

Warren, Oden L.; Dwivedi, Arpit; Wyrobek, Thomas J.; Famodu, Olugbenga O.; Takeuchi, Ichiro

2005-06-01

430

Detection of Metal Contamination on Silicon Wafer Backside and Edge by New TXRF Methods  

NASA Astrophysics Data System (ADS)

In conventional 200 mm wafer processing, backside defects are not considered to be of much concern because they are obscured by wafer backside topography. However, in current 300 mm wafer processing where both sides of a wafer are polished, backside defects require more consideration. In the beginning, backside defect inspection examined particle contamination because particle contamination adversely influences the depth of field in lithography. Recently, metal contamination is of concern because backside metal contamination causes cross-contamination in a process line, and backside metals easily transfer to the front surface. As the industry strives to yield more devices from the area around the wafer edge, edge exclusion requirements have also become more important. The current International Technology Roadmap for Semiconductors [1] requires a 2 mm edge exclusion. Therefore, metal contamination must be controlled to less than 2 mm from the edge because metal contamination easily diffuses in silicon wafers. To meet these current semiconductor processing requirements, newly developed zero edge exclusion TXRF (ZEE-TXRF) and backside measurement TXRF (BAC-TXRF) are effective metrology methods.

Kohno, Hiroshi; Yamagami, Motoyuki; Formica, Joseph; Shen, Liyong

2009-09-01

431

Differences between wafer and bake plate temperature uniformity in proximity bake: a theoretical and experimental study  

NASA Astrophysics Data System (ADS)

As the lithography industry moves toward finer features, specifications on temperature uniformity of the bake plates are expected to become more stringent. Consequently, aggressive improvements are needed to conventional bake station designs to make them perform significantly better than current market requirements. To this end, we have conducted a rigorous study that combines state-of-the-art simulation tools and experimental methods to predict the impact of the parameters that influence the uniformity of the wafer in proximity bake. The key observation from this detailed study is that the temperature uniformity of the wafer in proximity mode depends on a number of parameters in addition to the uniformity of the bake plate itself. These parameters include the lid design, the air flow distribution around the bake chamber, bake plate design and flatness of the bake plate and wafer. By performing careful experimental studies that were guided by extensive numerical simulations, we were able to understand the relative importance of each of these parameters. In an orderly fashion, we made appropriate design changes to curtail or eliminate the nonuniformity caused by each of these parameters. After implementing all these changes, we have now been able to match or improve the temperature uniformity of the wafer in proximity with that of a contact measurement on the bake plate. The wafer temperature uniformity is also very close to the theoretically predicted uniformity of the wafer.

Ramanan, Natarajan; Kozman, Austin; Sims, James B.

2000-06-01

432

Numerical and experimental evaluations on new direct growth process of polycrystalline silicon wafer from liquid silicon  

NASA Astrophysics Data System (ADS)

A new polycrystalline silicon (Si) wafering process directly from Si melt is introduced. As Si is known to have high latent heat, maintaining the steady state solidification condition in target area could be a main issue to achieve proposing wafering process. In addition, as the proposed process is based on horizontal growth, another critical issue is to keep grains growth parallel to the wafer growth direction, which results in large grain sizes. At first, simple numerical modeling was used to evaluate the possibility of realizing this new conceptual process, and to determine the main process parameters. From the simulation results, growth velocity and heat transfer rate at the solidification zone was identified as main process parameters for the steadily grown Si wafer within target area. Based on the simulation results, a growth system was set up experimentally, and the feasibility of the process was examined. A Si wafer with dimensions of 156×156×0.3 mm3 was successively obtained and grains growth parallel to wafer growth direction as calculated in the simulation were observed.

Jang, BoYun; Shin, SeungWon; Lee, JinSeok; Kim, JoonSoo

2014-05-01

433

Controllable co-segregation synthesis of wafer-scale hexagonal boron nitride thin films.  

PubMed

A facile and scalable co-segregation method is used to grow hexagonal boron nitride (h-BN) thin films from B- and N-containing metals. By annealing the sandwiched metal substrates in vacuum, sub-monolayer h-BN flakes, monolayer h-BN films, and multilayer h-BN thin films of varying thickness are successfully prepared. This approach follows an underneath-growth mode and exhibits good thickness- and location-control. PMID:24307244

Zhang, Chaohua; Fu, Lei; Zhao, Shuli; Zhou, Yu; Peng, Hailin; Liu, Zhongfan

2014-03-19

434

Wafer-scale metasurface for total power absorption, local field enhancement and  

E-print Network

and evaporation techniques. These consist of silver nanoparticle islands formed over a silver mirror, with an SiO2 by huge local field enhancement that is advantageous for surface-enhanced Raman scattering (SERS)10 as Figure 1a. The starting substrate is silicon, onto which silver and SiO2 layers are deposited

435

High Throughput Ultralong (20 cm) Nanowire Fabrication Using a Wafer-Scale Nanograting Template  

E-print Network

actively explored as promising nanostructured materials for high performance flexible electronics Jeongho Yeon, Young Jae Lee, Dong Eun Yoo,§ Kyoung Jong Yoo, Jin Su Kim, Jun Lee, Jeong Oen Lee, Seon (centimeter- long) nanowires are highly attractive from the perspective of electronic performance, device

436

A wafer scale active pixel CMOS image sensor for generic x-ray radiology  

Microsoft Academic Search

This paper describes a CMOS Active Pixel Image Sensor developed for generic X-ray imaging systems using standard CMOS technology and an active pixel architecture featuring low noise and a high sensitivity. The image sensor has been manufactured in a standard 0.35 mum technology using 8\\

Danny Scheffer

2007-01-01

437

Low-temperature Au/a-Si wafer bonding  

NASA Astrophysics Data System (ADS)

The Si/SiO2/Ti/Au-Au/Ti/a-Si/SiO2/Si bonding structure, which can also be used for the bonding of non-silicon material, was investigated for the first time in this paper. The bond quality test showed that the bond yield, bond repeatability and average shear strength are higher for this bonding structure. The interfacial microstructure analysis indicated that the Au-induced crystallization of the amorphous silicon process leads to big Si grains extending across the bond interface and Au filling the other regions of the bond interface, which result into a strong and void-free bond interface. In addition, the Au-induced crystallization reaction leads to a change in the IR images of the bond interface. Therefore, the IR microscope can be used to evaluate and compare the different bond strengths qualitatively. Furthermore, in order to verify the superiority of the bonding structure, the Si/SiO2/Ti/Au-a-Si/SiO2/Si (i.e. no Ti/Au layer on the a-Si surface) and Si/SiO2/Ti/Au-Au/Ti/SiO2/Si bonding structures (i.e. Au thermocompression bonding) were also investigated. For the Si/SiO2/Ti/Au-a-Si/SiO2/Si bonding structure, the poor bond quality is due to the native oxide layer on the a-Si surface, and for the Si/SiO2/Ti/Au-Au/Ti/SiO2/Si bonding structure, the poor bond quality is caused by the wafer surface roughness which prevents intimate contact and limits the interdiffusion at the bond interface.

Jing, Errong; Xiong, Bin; Wang, Yuelin

2011-01-01

438

Micro-nano photonic biosensors scalable at the wafer level  

NASA Astrophysics Data System (ADS)

We present a potential high sensitive label-free optical bio-sensing system based on biophotonic sensing cells, which can be fabricated and interrogated at wafer or disposable chip level. The key benefits rely on the holistic approach that combines bio-photonic resonant micro-nano cavities and advanced sub-micron spot size optical interrogation technologies. The proposed optical sensing system will be tremendously sensitive to refractive index variations by means of the observation of the reflectivity profile of three complementary enhanced sub-micron spot size optical technologies simultaneously (Reflectometry, Spectrometry and Ellipsometry based techniques), and the magnification due to the biophotonics resonant sensing cells, making possible to determine with more reliability and sensitivity the biomolecular interaction with the receptor biomolecules. This novel sensing system also offers an inexpensive solution for integration and packaging because it overcomes the need for using complex systems for light coupling such as inverted tapers or grating couplers, usually used in planar micro-nano photonic devices, because the sensor evaluation is done measuring vertically collecting the reflected light of the bio-photonic resonant sensing cells. The sensing system may use a tightly focused beam which allows measuring in situ micron/sub-micron size geometries, making the routine screening more cost-effective and suitable to perform hundreds of measurements on a single or several samples for multi-single or multiparameter measurements. The simultaneous used of the three different optical techniques will allow the systems to achieve a high throughput and productivity in comparison with other established analytical techniques. The levels of sensitivity expected are in the order of 10-6/10-7 refractive index units (RIU).

Holgado, M.; Casquel, R.; Lagunas, María-Fe

2009-02-01

439

Microlenticular lens replication by the combination of gas-assisted imprint technology and LIGA-like process  

NASA Astrophysics Data System (ADS)

A mold used in creating diffractive optical elements significantly affects the quality of these devices. In this study, we improved traditional microlens fabrication processes, which have shortcomings, mainly by combining gas-assisted imprint technology and the lithographie galvanoformung abformung (LIGA)-like process. This combination resulted in the production of high-quality optical components with high replication rates, high uniformity, large areas and high flexibility. Given the pixel size of the panel used, the optimal viewing distance, the film thickness and the glass thickness in the formula, we could determine the radius of curvature and the thickness of the lens. By the use of U-groove machining, precise electroforming and embossing to produce polydimethylsiloxane (PDMS) molds, lens film elements can be produced via an ultraviolet (UV)-cured molding process that converts microlenses into flexible polyethylene terephthalate films. In this study, the microlenticular lens mold is fabricated by U-groove machining, Ni electroforming and PDMS casting. Then, the PDMS mold with microlenticular lens structure is used in the gas-assisted UV imprint process and the PET film with microlenticular lens array is obtained. The lenticular lens had a radius of curvature and height of 228 and 18 µm, respectively. A 3D confocal laser microscope was used to measure the radius of curvature and the spacing of the metal molds, nickel (Ni) molds, PDMS molds and the finished thin-film products. The geometry of the final microlenticular lens was very close to the design values. All geometric errors were below 5%, the surface roughness reached the optical level (with all Ra values less than 10 nm) and the replication rate was 95%. The results demonstrate that this process can be used to fabricate gapless, lenticular-shaped, high-precision microlens arrays with a unitary curvature.

Yeh, Chia-Hung; Shih, Ching-Jui; Wang, Hsuan-Cheng; Chang, Fuh-Yu; Young, Hong-Tsu; Chang, Wen-Chuan

2012-09-01

440

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers  

NASA Astrophysics Data System (ADS)

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

2009-03-01

441

Enabling virtual wafer CD (WCD) using inverse pattern rendering (IPR) of mask CD-SEM images  

NASA Astrophysics Data System (ADS)

A wafer's printed CD error can be impacted by unaccounted mask making process variation. Unaccounted mask CD and/or corner rounding alters the intended drawn mask pattern contributing to a wafer's printed CD error. During OPC wafer calibration, average mask bias and corner rounding are accounted for in the OPC model, but random local mask making process variations or mask-to-mask variations can be difficult to account in such model calibration. Thus when a wafer's CD has error, it can be difficult to determine if the general root cause was due to mask or wafer or both. An in-line monitoring application has been developed to extract accurate mask CD and rendered mask polygon from collected mask CD-SEM images. Technical information will be presented on the challenges of accurately extracting information from SEM images. In particular, discussions include SEM image calibration, contour extraction, inverse pattern rendering, and general image processing to account for mask SEM aberrations (translation, rotation, & dilation), tool-to-tool variation, vendor-to-vendor variation, run-to-run variation, and dark/bright field pattern-to-pattern variation. After accurate mask SEM contours are obtained, lithographic simulations are performed on extracted polygon contours to determine the impact of mask variation on wafer CD. This paper will present detail information about the Inverse Pattern Rendering (IPR) capabilities developed for a virtual Wafer CD (WCD) application and its results, which is proven to achieved 0.5 nm accuracy across multiple critical layers from 28 nm to 40 nm nodes on multiple CD-SEM tools over multiple mask shop locations.

Dam, Thuc; Chen, Dongxue; Chang, Hsien-Min; Corcoran, Noel; Yu, Paul; Pang, Linyong; Chang, Chia-Wei; Lai, Rick; Chang, Peter; Tuo, Laurent

2011-11-01

442

A cost model comparing image qualification using test wafer and direct mask inspection  

NASA Astrophysics Data System (ADS)

This paper has been updated on April 30, 2007 with new information in Figure 2 and Section 4. Litho-cluster cycle time will drive the economics for fabs even harder at nodes 65nm and below. Any methods or techniques that can reduce this litho-cluster cycle time need to be looked at seriously. Besides running production, a small part of the litho-cluster time is also used to expose test wafers for mask qualification on a periodic interval. Incoming mask inspections as well as periodic mask inspections (re-qualification) in advanced wafer fabs are a necessity to prevent yield loss from progressive mask defect problems (such as crystal growth or haze), traditional reticle contamination, ESD and migrating defects (from non-critical to critical location on mask). This mask inspection can be achieved via two methods. The first method is indirect, commonly known as image qualification, where a mask is being exposed followed by the inspection of the printed wafer to detect if there is any repeater on the wafer or not. The other method of mask inspection is direct mask inspection (such as STARlight TM). A lot has been written on the technical advantages of direct mask inspection over image qualification. This technical report discusses a cost model developed to compare the financial impact of image qualification to direct mask inspection like STARlight. In this model all the inspection and process tool costs are included as well as turn-around-time (TAT) at the litho-cluster for image qualification and TAT for STARlight. Then, the inspection cost and the opportunity cost (for using litho-cluster to expose test wafers other than production wafers) are combined and the net effect is compared. The goal is to find the most cost effective way to do mask qualification in advanced wafer fabs.

Bhattacharyya, Kaustuve; Hazari, Viral; Sutherland, Doug; Higashiki, Tatsuhiko

2006-10-01

443

Large scale production methods for optoelectronic components  

Microsoft Academic Search

Light parameters were measured at the wafer probe station for light emitting diode (LED) wafers, infrared diode-wafers and photodetector wafers. The dicing of 3-5 wafers by: (1) diamond scribing and breaking; (2) laser scribing and breaking; and (3) sawing of wafers were compared. The encapsulation of optoelectronic components by injection molding with polycarbonates (development of injection molding tools for production),

W. Schoebol

1980-01-01

444

Structural Damage Detection with Piezoelectric Wafer Active Sensors  

NASA Astrophysics Data System (ADS)

Piezoelectric wafer active sensors (PWAS) are lightweight and inexpensive enablers for a large class of damage detection and structural health monitoring (SHM) applications. This paper starts with a brief review of PWAS physical principles and basic modelling and continues by considering the various ways in which PWAS can be used for damage detection: (a) embedded guided-wave ultrasonics, i.e., pitch-catch, pulse-echo, phased arrays, thickness mode; (b) high-frequency modal sensing, i.e., the electro-mechanical (E/M) impedance method; (c) passive detection, i.e., acoustic emission and impact detection. An example of crack-like damage detection and localization with PWAS phased arrays on a small metallic plate is given. The modelling of PWAS detection of disbond damage in adhesive joints is achieved with the analytical transfer matrix method (TMM). The analytical methods offer the advantage of fast computation which enables parameter studies and carpet plots. A parametric study of the effect of crack size and PWAS location on disbond detection is presented. The power and energy transduction between PWAS and structure is studied analytically with a wave propagation method. Special attention is given to the mechatronics modeling of the complete transduction cycle from electrical excitation into ultrasonic acoustic waves by the piezoelectric effect, the transfer through the structure, and finally reverse piezoelectric transduction to generate the received electric signal. It is found that the combination of PWAS size and wave frequency/wavelength play an important role in identifying transduction maxima and minima that could be exploited to achieve an optimum power-efficient design. The multi-physics finite element method (MP-FEM), which permits fine discretization of damaged regions and complicated structural geometries, is used to study the generation of guided waves in a plate from an electrically excited transmitter PWAS and the capture of these waves as electric signals at a receiver PWAS. Wave diffraction from a hole damage is illustrated through time-frame snapshots. The paper ends with conclusions and suggestions for further work.

Giurgiutiu, Victor

2011-07-01

445

Growth of oriented diamond on nickel wafers and thin films  

NASA Astrophysics Data System (ADS)

Growth of highly oriented diamond thin films on nickel was achieved by a multi-step process involving seeding, high temperature carbon dissolution, and growth. This process is very sensitive to the substrate temperature and requires accurate timing of both the nucleation and growth steps. It was observed that the surface morphology changed dramatically during the nucleation process and that in-situ monitoring of the surface morphology could provide valuable feedback for process control. An optical monitoring system developed under this study has significantly improved both the reproducibility and overall quality of the oriented diamond films grown on Ni substrates. However, since a significant fraction of carbon diffused into the bulk, as confirmed by Auger carbon depth profiling, the highest nucleation density on the bulk Ni substrate was 107 cm-2. To prevent carbon diffusion away from the surface and to maintain a supersaturated surface region, epitaxial nickel and iridium thin films were deposited by electron-beam evaporation on MgO which acted as a carbon diffusion barrier. A multi-layer structure with 100 A iridium and 1 mum nickel grown epitaxially on an MgO (100) wafer by electron-beam evaporation was used as a substrate. The 100 A thick Ir interlayer was used to overcome the delamination of Ni from the MgO substrate during processing. Oriented diamond was successfully deposited on these substrates and yielded nucleation densities of 3 x 108 cm-2, that resulted in faster coalescence of diamond particles. Coalesced diamond thin films on Ni/Ir/MgO substrates were grown in about six hours of growth, as compared to about 25 hours for the bulk Ni substrates. However, a much narrower process widow on Ni thin films made reproducible growth of oriented diamond more challenging. Cross-sectional high-resolution transmission electron microscopy (XHRTEM) was used to investigate the interfacial microstructure formed during hot filament chemical vapor deposition (HFCVD) of oriented diamond on Ni thin films. Focused ion beam (FIB) technique was used for the sample preparation. Heteroepitaxial diamond nuclei formed at the early nucleation stage and after longer growth time were studied. A carbide interfacial layer between the diamond nuclei and Ni was observed. Diamond grew epitaxially on this interfacial layer with very few defects. All defects appeared to have propagated into the interfacial layer and consisted primarily of stacking faults and dislocations. The selected area diffraction showed a slight misorientation of the interfacial layer with the Ni film. It is believed, that the interfacial layer, which has the same crystal structure and a very close lattice constant with Ni, stabilized the sp3 carbon and facilitated diamond nucleation. A model describing the nucleation mechanism is proposed.

Liu, Wei

2000-10-01

446

Long persistent near infrared luminescence nanoprobes LiGa5O8:Cr3+-PEG-OCH3 for in vivo imaging  

NASA Astrophysics Data System (ADS)

The Cr3+-doped LiGa5O8 nanoparticles (LGNPs) with long-persistent near-infrared phosphorescence were obtained through a sol-gel approach followed by heat treatment at 800 °C in air. The obtained results reveal that the nanoparticles with an average diameter of 100 nm are well defined and have pure structure of LiGa5O8. After illumination for 3 min using a 254 nm UV lamp, the LGNPs exhibit strong near-infrared peak at ca. 720 nm belonging to tissue transparency window which can last for more than 1 h. Via surface modified with PEG-5000-OCH3, the LGNPs-PEG-OCH3 exhibit excellent biocompatibility and low toxicity. Under in vitro pre-excitation using a 254 nm UV lamp for 3 min, the in vivo distribution of the LGNPs-PEG-OCH3 in the abdomen can be detected in real time for more than 1 h. All the results indicate that the LGNPs-PEG-OCH3 can be used as potential nanoprobes to realize in vivo, real time and long time imaging with high sensitivity.

Fu, Xiaoyan; Liu, Chunlin; Shi, Junpeng; Man, Huizi; Xu, Jia; Zhang, Hongwu

2014-09-01

447

Excess Carrier Lifetime Measurement of Bulk SiC Wafers and Its Relationship with Structural Defect Distribution  

Microsoft Academic Search

Excess carrier lifetime in bulk 2-in. SiC wafers was measured by microwave photoconductivity decay (mu-PCD). The mapping technique was used to obtain the lifetime distribution in the entire wafer. We observed the birefringence image and X-ray topograph of the wafers in order to determine the structural defect distribution, and the net donor concentration distribution was also observed by capacitance--voltage measurements.

Tatsuhiro Mori; Masashi Kato; Hideki Watanabe; Masaya Ichimura; Eisuke Arai; Shingo Sumie; Hidehisa Hashizume

2005-01-01

448

Reliability study of wafer bonding for micro-electro-mechanical systems  

NASA Astrophysics Data System (ADS)

Wafer bonding has attracted significant attention in applications that require integration of Micro-Electro-Mechanical Systems (MEMS) with Integrated Circuits (IC). The integration of monolithic MEMS and electronic devices is difficult because of issues such as material compatibility, process compliance and thermal budget. It is important to establish a wafer bonding process which provides long-term protection for the MEMS devices yet does not affect their performance. The attentions for such integration are at the die level and wafer level. Recently, the trend is toward wafer-level integration as a cost effective solution to combine sensing, logic, actuation and communications on a single platform. This paper describes the development of low temperature bonding techniques for post-CMOS MEMS integration in system-on-chip (SOC) applications. The bonding methods discussed in this paper involve Benzocyclobutene polymer (BCB) as glue layer to joint two 200 mm wafers together. The bonding temperature is lower than 400°C. Four-point bending and stud-pull methods were used to investigate the mechanical properties of the bonding interfaces. These methods can provide critical information such as adhesion energy and bonding strength of the bonded interfaces. Initial test results at room temperature showed that the BCB bond stayed intact up to an average stress of 50 MPa. It was observed that the BCB bond strength decreased with increasing temperatures and the energy release rate decreased with decreasing BCB thickness.

Almasri, Mahmoud; Altemus, Bruce; Gracias, Alison; Clow, Larry; Tokranova, Natalya; Castracane, James; Xu, Bai

2003-12-01

449

Reliability study of wafer bonding for micro-electro-mechanical systems  

NASA Astrophysics Data System (ADS)

Wafer bonding has attracted significant attention in applications that require integration of Micro-Electro-Mechanical Systems (MEMS) with Integrated Circuits (IC). The integration of monolithic MEMS and electronic devices is difficult because of issues such as material compatibility, process compliance and thermal budget. It is important to establish a wafer bonding process which provides long-term protection for the MEMS devices yet does not affect their performance. The attentions for such integration are at the die level and wafer level. Recently, the trend is toward wafer-level integration as a cost effective solution to combine sensing, logic, actuation and communications on a single platform. This paper describes the development of low temperature bonding techniques for post-CMOS MEMS integration in system-on-chip (SOC) applications. The bonding methods discussed in this paper involve Benzocyclobutene polymer (BCB) as glue layer to joint two 200 mm wafers together. The bonding temperature is lower than 400°C. Four-point bending and stud-pull methods were used to investigate the mechanical properties of the bonding interfaces. These methods can provide critical information such as adhesion energy and bonding strength of the bonded interfaces. Initial test results at room temperature showed that the BCB bond stayed intact up to an average stress of 50 MPa. It was observed that the BCB bond strength decreased with increasing temperatures and the energy release rate decreased with decreasing BCB thickness.

Almasri, Mahmoud; Altemus, Bruce; Gracias, Alison; Clow, Larry; Tokranova, Natalya; Castracane, James; Xu, Bai

2004-01-01

450

Automated defect review of the wafer bevel with a defect review scanning electron microscope  

NASA Astrophysics Data System (ADS)

One of the few remaining bastions of non-regulated Integrated Circuit defectivity is the wafer bevel. Recent internal Integrated Circuit Manufacturing studies have suggested that the edge bevel may be responsible for as much as a two to three percent yield loss during a defect excursion on the manufacturing line and a one to two percent yield loss during ongoing wafer manufacturing. A new generation of defect inspection equipment has been introduced to the Research and Development, Integrated Circuit, MEM's and Si wafer manufacturing markets that has imparted the ability for the end equipment user to detect defects located on the bevel of the wafer. The inherent weakness of the current batch of wafer bevel inspection equipment is the lack of automatic discrete defect classification data into multiple, significant classification bins and the lack of discrete elemental analysis data. Root cause analysis is based on minimal discrete defect analysis as a surrogate for a statistically valid sampling of defects from the bevel. This paper provides a study of the methods employed with a Hitachi RS-5500EQEQ Defect Review Scanning Electron Microscope (DRSEM) to automatically capture high resolution/high magnification images and collect elemental analysis on a statistically valid sample of the discrete defects that were located by a bevel inspection system.

McGarvey, Steve; Kanezawa, Masakazu

2009-03-01

451

Dissolving oral clonazepam wafers in the acute treatment of prolonged seizures.  

PubMed

Klonopin (clonazepam; Genentech Inc, South San Francisco, California) oral wafers are benzodiazepines with anticonvulsive and anxiolytic properties. Our institution has been prescribing clonazepam wafers for acute treatment of prolonged seizures for years. Patients' size determined dosing at 0.25, 0.5, 1, or 2 mg wafers. We proceeded to obtain evidence for efficacy. Hospital Institutional Review Board approval was obtained for anonymous patient survey. All children who had been prescribed clonazepam wafers over a 6-year period at our institution were mailed detailed questionnaires. Three hundred eighty-one questionnaires were mailed with 88 replies but only 56 with meaningful data. Average age was 12.1 years. There were 31 males. Efficacy was defined as stopping seizure within 10 minutes, >50% of the time. Thirty-eight of the 56 (68%) patients met this criterion. From these 38 patients, 19 (50%) had seizures stop within 1 minute. Overall results were comparable to Diastat (rectal diazepam; Valeant Pharmaceuticals International, Aliso Viejo, California). Clonazepam wafers are an effective acute therapy for prolonged seizures. PMID:20413800

Troester, Matthew M; Hastriter, Eric V; Ng, Yu-Tze

2010-12-01

452

New sensing wafer technique for artifact-free transient temperature measurements in PEB processes  

NASA Astrophysics Data System (ADS)

A system for monitoring the transient and steady state temperature profiles during the deep UV (DUV) post exposure bake (PEB) is described. The system, called Accura°C, consists of a sensor wafer, a wireless electronics unit and software on a laptop computer. To monitor temperature platinum resistance temperature detectors (RTDs) are embedded into silicon wafers. A flexible high temperature printed circuit (PC) ribbon cable connects the wireless electronics unit to the wafer. The system robot moves both the sensor wafer and electronics unit through the system. Communication between the electronics unit and a laptop computer is accomplished by a Bluetooth RF link. The RF link enables the laptop computer to analyze the temperature measurements in real time. The rechargeable batteries in the electronics unit allow detailed examination of all process chambers. Further the long operating time and real time data stream provide for bake chamber optimization such as tuning. The sensor integration into the wafer provides accurate, artifact free measurements of the rapid temperature changes during PEB ramps.

Sun, Mei H.; Cohen, Barney M.; Quli, Farhat; Renken, Wayne G.

2003-05-01

453

Synthesis and thermionic emission properties of graphitic carbon nanofibres supported on Si wafers or carbon felt  

NASA Astrophysics Data System (ADS)

Preparation procedures and thermionic emission properties of graphitic carbon nanofibres (GCNFs) supported on Si wafer or commercial carbon felt supports are reported. GCNF/native-oxide Si wafer, GCNF/oxidized Si wafer, GCNF/Ni-coated Si wafer and GCNF/carbon felt nanocomposites are obtained by growing GCNFs from growth catalyst nanoparticles supported on these supports. Narrow herringbone GCNF/SiO2/carbon felt mats are prepared from growth catalyst nanoparticles supported on fumed silica flakes. Due to weak GCNF-to-support binding in GCNF/Si wafer mats, GCNF/carbon felt mats and GCNF/SiO2/carbon felt mats, mechanical loss of the GCNF component is facile. However, carbothermal reduction of GCNF/SiO2/carbon felt nanocomposites affords mechanically robust GCNF/SiC/carbon felt mats. Thermionic electron energy distribution profiles recorded for these new nanofibre compositions indicate classic free-electron emission with estimated work functions (4.25-4.91 eV) slightly lower than those observed for un-doped graphite or carbon nanotubes. Electron energy di