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Sample records for wafer scale liga

  1. A Batch Wafer Scale LIGA Assembly and Packaging Technique vai Diffusion Bonding

    SciTech Connect

    Christenson, T.R.; Schmale, D.T.

    1999-01-27

    A technique using diffusion bonding (or solid-state welding) has been used to achieve batch fabrication of two- level nickel LIGA structures. Interlayer alignment accuracy of less than 1 micron is achieved using press-fit gauge pins. A mini-scale torsion tester was built to measure the diffusion bond strength of LIGA formed specimens that has shown successful bonding at temperatures of 450"C at 7 ksi pressure with bond strength greater than 100 Mpa. Extensions to this basic process to allow for additional layers and thereby more complex assemblies as well as commensurate packaging are discussed.

  2. LIGA Scanner Control Software

    Energy Science and Technology Software Center (ESTSC)

    1999-02-01

    The LIGA Scanner Software is a graphical user interface package that facilitates controlling the scanning operation of x-rays from a synchrotron and sample manipulation for making LIGA parts. The process requires scanning of the LIGA mask and the PMMA resist through a stationary x-ray beam to provide an evenly distributed x-ray exposure over the wafer. This software package has been written specifically to interface with Aerotech motor controllers.

  3. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  4. Wafer-scale Mitochondrial Membrane Potential Assays

    PubMed Central

    Lim, Tae-Sun; Davila, Antonio; Zand, Katayoun; Douglas, Wallace C.; Burke, Peter J.

    2012-01-01

    It has been reported that mitochondrial metabolic and biophysical parameters are associated with degenerative diseases and the aging process. To evaluate these biochemical parameters, current technology requires several hundred milligrams of isolated mitochondria for functional assays. Here, we demonstrate manufacturable wafer-scale mitochondrial functional assay lab-on-a-chip devices, which require mitochondrial protein quantities three orders of magnitude less than current assays, integrated onto 4” standard silicon wafer with new fabrication processes and materials. Membrane potential changes of isolated mitochondria from various well-established cell lines such as human HeLa cell line (Heb7A), human osteosarcoma cell line (143b) and mouse skeletal muscle tissue were investigated and compared. This second generation integrated lab-on-a-chip system developed here shows enhanced structural durability and reproducibility while increasing the sensitivity to changes in mitochondrial membrane potential by an order of magnitude as compared to first generation technologies. We envision this system to be a great candidate to substitute current mitochondrial assay systems. PMID:22627274

  5. Eutectic bonds on wafer scale by thin film multilayers

    NASA Astrophysics Data System (ADS)

    Christensen, Carsten; Bouwstra, Siebe

    1996-09-01

    The use of gold based thin film multilayer systems for forming eutectic bonds on wafer scale is investigated and preliminary results will be presented. On polished 4 inch wafers different multilayer systems are developed using thin film techniques and bonded afterwards under reactive atmospheres and different bonding temperatures and forces. Pull tests are performed to extract the bonding strengths.

  6. Parallel Assembly of LIGA Components

    SciTech Connect

    Christenson, T.R.; Feddema, J.T.

    1999-03-04

    In this paper, a prototype robotic workcell for the parallel assembly of LIGA components is described. A Cartesian robot is used to press 386 and 485 micron diameter pins into a LIGA substrate and then place a 3-inch diameter wafer with LIGA gears onto the pins. Upward and downward looking microscopes are used to locate holes in the LIGA substrate, pins to be pressed in the holes, and gears to be placed on the pins. This vision system can locate parts within 3 microns, while the Cartesian manipulator can place the parts within 0.4 microns.

  7. Wafer-scale aluminum nano-plasmonics

    NASA Astrophysics Data System (ADS)

    George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

    2014-09-01

    The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

  8. IGBT scaling principle toward CMOS compatible wafer processes

    NASA Astrophysics Data System (ADS)

    Tanaka, Masahiro; Omura, Ichiro

    2013-02-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

  9. Liga developer apparatus system

    DOEpatents

    Boehme, Dale R.; Bankert, Michelle A.; Christenson, Todd R.

    2003-01-01

    A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

  10. Wafer-scale aluminum plasmonics for fluorescence based biodetection

    NASA Astrophysics Data System (ADS)

    Farhang, Arash; George, Matthew C.; Williamson, Brent; Black, Mike; Wangensteen, Ted; Fraser, James; Petrova, Rumyana; Prestgard, Kent

    2015-08-01

    Moxtek has leveraged existing capabilities in wafer-scale patterning of sub-wavelength wire grid polarizers into the fabrication of 1D and 2D periodic aluminum plasmonic structures. This work will discuss progress in 200 mm diameter wafer-scale fabrication, with detailed emphasis within the realm of microarray based fluorescence detection. Aluminum nanohole arrays in a hexagonal lattice are first numerically investigated. The nanohole array geometry and periodicity are specifically tuned to coincide both with the excitation of the fluorophore Cy3, and to provide a high field enhancement within the nanoholes where labeled biomolecules are captured. This is accomplished through numerical modelling, nanofabrication, SEM imaging, and optical characterization. A 200mm diameter wafer, patterned with the optically optimized nanohole array, is cut into standard 1x3 inch microscope slide pieces and then subsequently printed with various antigens at 9 different concentrations. A sandwich bioassay is then carried out, using the corresponding conjugate antibodies in order to demonstrate specificity. The nanohole array exhibit a 3-4 times total fluorescence enhancement of Cy3, when compared to a leading commercial microarray glass slide.

  11. Wafer-scale plasmonic and photonic crystal sensors

    NASA Astrophysics Data System (ADS)

    George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

    2015-08-01

    200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

  12. Wafer-scale fabrication of nanoapertures using corner lithography

    NASA Astrophysics Data System (ADS)

    Burouni, Narges; Berenschot, Erwin; Elwenspoek, Miko; Sarajlic, Edin; Leussink, Pele; Jansen, Henri; Tas, Niels

    2013-07-01

    Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated—based on a theoretical foundation including a statistical analysis—with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures.

  13. Wrinkled bilayer graphene with wafer scale mechanical strain

    NASA Astrophysics Data System (ADS)

    Mikael, Solomon; Seo, Jung-Hun; Javadi, Alireza; Gong, Shaoqin; Ma, Zhenqiang

    2016-05-01

    Wafer-scale strained bilayer graphene is demonstrated by employing a silicon nitride (Si3N4) stressor layer. Different magnitudes of compressive stress up to 840 MPa were engineered by adjusting the Si3N4 deposition recipes, and different strain conditions were analyzed using Raman spectroscopy. The strained graphene displayed significant G peak shifts and G peak splitting with 16.2 cm-1 and 23.0 cm-1 of the G band and two-dimensional band shift, which corresponds to 0.26% of strain. Raman mapping of large regions of the graphene films found that the largest shifts/splitting occurred near the bilayer regions of the graphene films. The significance of our approach lies in the fact that it can be performed in a conventional microfabrication process, i.e., the plasma enhanced chemical vapor deposition system, and thus easily implemented for large scale production.

  14. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture

  15. Video-rate fuzzy Golay processor for wafer scale integration

    SciTech Connect

    Steinvorth, R.H.

    1987-01-01

    The fuzzy Golay transformation is a novel approach for gray-level image processing. Fuzzy-set theory is used to modify the binary image processing techniques developed by M. J. Golay to permit direct gray-level image processing without thresholding. The comparison between gray-level pixels is accomplished with the Pixel Closeness Value (PCV) while comparison between gray-level neighborhoods uses the Neighborhood Closeness Value (NCV). Feature extraction is done by comparing the gray-level image neighborhood to a subset of the fourteen Golay neighborhoods using the NCV function. The Fuzzy Golay Processor (FGP) is an architecture designed to implement the fuzzy Golay transformation. The design of the FGP has been optimized to permit a successful implementation in Wafer Scale Integration (WSI). A system containing four FGPs is capable of performing thirty fuzzy Golay transformations per second on a 256 by 256 eight-bit pixel image. Such a system could fit on a four-inch wafer with enough redundant dies to allow a 30% die yield. The required dies are four Input-Output Modules (IOM) and 56 Neighborhood Evaluation Modules (NEM).

  16. Wafer-scale micro-optics replication technology

    NASA Astrophysics Data System (ADS)

    Rossi, Markus; Rudmann, Hartmut; Marty, Brigitte; Maciossek, Andreas

    2003-11-01

    For many high-volume applications of micro-optical elements and systems the most cost-effective fabrication technology is replication in polymer materials with techniques such as UV embossing, hot embossing, and injection molding. Replication significantly reduces the cost in volume production in comparison to silicon-based etched components. However, the temperature and humidity stability of most commercial polymers is not suitable for the application of replicated elements in areas such as telecom or datacom. A process based on UV-replication in chemically durable polymers has been developed. Technologies for all fabrication steps from mastering over tooling to replication on wafer-scale, post-processing and characterization are described. We present results of various projects with double-sided micro-optics for telecom/datacom and various sensor applications.

  17. Wafer-Scale Microwire Transistor Array Fabricated via Evaporative Assembly.

    PubMed

    Park, Jae Hoon; Sun, Qijun; Choi, Yongsuk; Lee, Seungwoo; Lee, Dong Yun; Kim, Yong Hoon; Cho, Jeong Ho

    2016-06-22

    One-dimensional (1D) nano/microwires have attracted significant attention as promising building blocks for various electronic and optical device applications. The integration of these elements into functional device networks with controlled alignment and density presents a significant challenge for practical device applications. Here, we demonstrated the fabrication of wafer-scale microwire field-effect transistor (FET) arrays based on well-aligned inorganic semiconductor microwires (indium-gallium-zinc-oxide (IGZO)) and organic polymeric insulator microwires fabricated via a simple and large-area evaporative assembly technique. This microwire fabrication method offers a facile approach to precisely manipulating the channel dimensions of the FETs. The resulting solution-processed monolithic IGZO microwire FETs exhibited a maximum electron mobility of 1.02 cm(2) V(-1) s(-1) and an on/off current ratio of 1 × 10(6). The appropriate choice of the polymeric microwires used to define the channel lengths enabled fine control over the threshold voltages of the devices, which were employed to fabricate high-performance depletion-load inverters. Low-voltage-operated microwire FETs were successfully fabricated on a plastic substrate using a high-capacitance ion gel gate dielectric. The microwire fabrication technique involving evaporative assembly provided a facile, effective, and reliable method for preparing flexible large-area electronics. PMID:27228025

  18. Designing defect spins for wafer-scale quantum technologies

    SciTech Connect

    Koehl, William F.; Seo, Hosung; Galli, Giulia; Awschalom, David D.

    2015-11-27

    The past decade has seen remarkable progress in the development of the nitrogen-vacancy (NV) defect center in diamond, which is one of the leading candidates for quantum information technologies. The success of the NV center as a solid-state qubit has stimulated an active search for similar defect spins in other technologically important and mature semiconductors, such as silicon carbide. If successfully combined with the advanced microfabrication techniques available to such materials, coherent quantum control of defect spins could potentially lead to semiconductor-based, wafer-scale quantum technologies that make use of exotic quantum mechanical phenomena like entanglement. In this article, we describe the robust spin property of the NV center and the current status of NV center research for quantum information technologies. We then outline first-principles computational modeling techniques based on density functional theory to efficiently search for potential spin defects in nondiamond hosts suitable for quantum information applications. The combination of computational modeling and experimentation has proven invaluable in this area, and we describe the successful interplay between theory and experiment achieved with the divacancy spin qubit in silicon carbide.

  19. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  20. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  1. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates.

    PubMed

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-19

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes. PMID:26789103

  2. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates

    NASA Astrophysics Data System (ADS)

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-01

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes.

  3. Transfer-Free, Wafer-Scale Manufacturing of Graphene-Based Electromechanical Resonant Devices

    NASA Astrophysics Data System (ADS)

    Cullinan, Michael; Gorman, Jason

    2013-03-01

    Nanoelectromechanical (NEMS) resonators offer the potential to extend the limits of force and mass detection due to their small size, high natural frequencies and high Q-factors. Graphene-based NEMS resonators are particularly promising due to their high elastic modulus and atomic thickness. However, widespread use of graphene in such systems is limited by the way in which graphene-based devices are typically fabricated. Most graphene-based NEMS devices are fabricated in a ``one-off'' manner using slow, limited scale methods such as mechanical exfoliation, electron beam lithography, or transfer from copper foils which can't be incorporated into standard micro/nanofabrication lines. This talk will present a method that can be used to manufacture graphene-based NEMS devices at the wafer scale using conventional microfabrication techniques. In this method graphene is grown directly on thin film copper using chemical vapor deposition. The copper film is then patterned and etched to produce graphene-based NEMS resonators. This talk will also address some of the challenges in fabricating a large number of graphene devices at the wafer scale including achieving high uniformity across the wafer, increasing device-to-device repeatability, and producing high device yields.

  4. Wafer-scale growth of VO2 thin films using a combinatorial approach

    PubMed Central

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

    2015-01-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that ‘electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

  5. Fabrication of wafer-scale nanopatterned sapphire substrate through phase separation lithography

    NASA Astrophysics Data System (ADS)

    Guo, Xu; Ni, Mengyang; Zhuang, Zhe; Dai, Jiangping; Wu, Feixiang; Cui, Yushuang; Yuan, Changsheng; Ge, Haixiong; Chen, Yanfeng

    2016-04-01

    A phase separation lithography (PSL) based on polymer blend provides an extremely simple, low-cost, and high-throughput way to fabricate wafer-scale disordered nanopatterns. This method was introduced to fabricate nanopatterned sapphire substrates (NPSSs) for GaN-based light-emitting diodes (LEDs). The PSL process only involved in spin-coating of polystyrene (PS)/polyethylene glycol (PEG) polymer blend on sapphire substrate and followed by a development with deionized water to remove PEG moiety. The PS nanoporous network was facilely obtained, and the structural parameters could be effectively tuned by controlling the PS/PEG weight ratio of the spin-coating solution. 2-in. wafer-scale NPSSs were conveniently achieved through the PS nanoporous network in combination with traditional nanofabrication methods, such as O2 reactive ion etching (RIE), e-beam evaporation deposition, liftoff, and chlorine-based RIE. In order to investigate the performance of such NPSSs, typical blue LEDs with emission wavelengths of ~450 nm were grown on the NPSS and a flat sapphire substrate (FSS) by metal-organic chemical vapor deposition, respectively. The integral photoluminescence (PL) intensity of the NPSS LED was enhanced by 32.3 % compared to that of the FSS-LED. The low relative standard deviation of 4.7 % for PL mappings of NPSS LED indicated the high uniformity of PL data across the whole 2-in. wafer. Extremely simple, low cost, and high throughput of the process and the ability to fabricate at the wafer scale make PSL a potential method for production of nanopatterned sapphire substrates.

  6. High-precision micro-optic elements by wafer-scale replication on arbitrary substrates

    NASA Astrophysics Data System (ADS)

    Dannberg, Peter; Bierbaum, Ralf; Erdmann, Lars; Krehl, A.; Braeuer, Andreas H.

    1999-09-01

    A solution is described for replication of polymer microoptical elements on arbitrary substrates. The replication is done on wafer scale level and includes the adjustment step between the optical elements and the substrate. Demonstrators are various microlens arrays, structures for the efficient coupling between monomode waveguides or multimode fibers and photodiodes, and between multimode waveguides and LED's. Out of the many different replication techniques, UV-reaction molding is chosen for this application. This technique has advantages against hot embossing and injection molding. Network polymers which are stable against temperature changes can be used. The replication is made in thin layers on a solid substrate resulting in high mechanical stability and very good flatness of the samples. The process introduces mechanical stress nor thermal load on the substrate which can be a fully processed semiconductor wafer containing elements like diodes or LEDs.

  7. Self-adaptive phosphor coating technology for wafer-level scale chip packaging

    NASA Astrophysics Data System (ADS)

    Linsong, Zhou; Haibo, Rao; Wei, Wang; Xianlong, Wan; Junyuan, Liao; Xuemei, Wang; Da, Zhou; Qiaolin, Lei

    2013-05-01

    A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.

  8. Wafer scale interdigitated nanoelectrode devices functionalized using a MEMS-based deposition system

    NASA Astrophysics Data System (ADS)

    Martinez-Rivas, A.; Carcenac, F.; Saya, D.; Séverac, C.; Nicu, L.; Vieu, C.

    2012-03-01

    This paper reports on a methodology to elaborate interdigitated nanoelectrode devices (INDs) at the wafer scale, relying on a mix-and-match process which combines proximity optical lithography and electron beam lithography. An optimum exposure dose allowed fabricating nanodevices, at the wafer level, with a successful yield of 97%. The final devices are bonded onto conventional TO-8 packages. Electrical characterization in a short-circuited nanoelectrode is performed, revealing a 230 µΩ cm resistivity value at 23 °C. A MEMS-based spotter made of cantilevers (called Bioplume) has been used to obtain precise functionalization of the INDs with sub-picoliter volume solutions. These INDs are the basis of multiple tunnel junction nanodevices, intended to serve as novel highly sensitive nanobiosensors.

  9. 200 mm wafer-scale epitaxial transfer of single crystal Si on glass by anodic bonding of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Teh, W. H.; Trigg, Alastair; Tung, C. H.; Kumar, R.; Balasubramanian, N.; Kwong, D. L.

    2005-08-01

    We report a low-temperature (350 °C) anodic bonding followed by grind/etch-back method for a 200 mm wafer-scale epitaxial transfer of ultrathin (1.9 kÅ) single crystalline Si on Pyrex glass. Standard back-end-of-line 3 kÅ SiN/3 kÅ undoped silicon glass passivating films were used as the buffer layers between the silicon-on-insulator wafer and the glass wafer. The quality and strain-free state of the transferred transparent Si film to glass was characterized by cross-sectional transmission electron microscopy, x-ray diffraction (XRD), and high-resolution XRD. Complete removal of the bulk Si after bonding was ascertained by Auger electron spectroscopy spectra and depth profiling. Strong adhesion between the transferred film and the glass wafer was verified by standard tape adhesion tests. This process will pave the way for future generations of Si-based microelectronics including bioelectronics.

  10. LIGA Micromachining: Infrastructure Establishment

    SciTech Connect

    Alfredo M. Morales; Barry V. Hess; Dale R. Boehme; Jill M. Hruby; John S. Krafcik; Robert H. Nilson; Stewart K. Griffiths; William D. Bonivert

    1999-02-01

    LIGA is a micromachining technology that uses high energy x-rays from a synchrotron to create patterns with small lateral dimensions in a deep, non-conducting polymeric resist. Typical dimensions for LIGA parts are microns to tens of microns in lateral size, and hundreds of microns to millimeters in depth. Once the resist is patterned, metal is electrodeposited in the features to create metal microparts, or to create a metal mold for subsequent replication. The acronym LIGA comes from the German words for lithography, electroforming, and molding, and the technology has been under worldwide development for more than a decade. over the last five years, a full-service capability to produce metal microparts using the LIGA process has been established at Sandia national Laboratories, California. This report describes the accomplishments made during the past two years in infrastructure establishment funded by a Laboratory Directed Research and Development (LDRD) project entitled ''LIGA Micromachining.'' Specific topics include photoresist processing for LIGA mask making, x-ray scanning equipment, plating bath instrumentation, plating uniformity, and software architecture.

  11. Wafer-scale manufacturing and integration of micro-optical systems

    NASA Astrophysics Data System (ADS)

    Kathman, Alan D.; Boomgarden, Mark

    2001-11-01

    Demand for optical components and subsystems has exploded in the last decade. The question directed at component providers by customers is no longer when can you make it? The critical question is now become when can you make it in high volume? Wafer scale manufacturing, developed for the integrated circuit industry, has transitioned into the realm of optical fabrication and assembly. Photonic Chip optical subassemblies are products fabricated using these techniques. To create them, the optical elements are lithographically generated with integrated alignment and bonding features. Wafers of complimentary elements can be aligned and bonded at the wafer level, assembling hundreds of optical systems in parallel with a single operation. Electro-optical components, such as source and detector elements can be assembled into the system at the chip level, using flip-chip die bonding to complete the mechanical and electrical connection. The striking features of this manufacturing method are its parallel assembly techniques, broad use of automation, and very attractive intrinsic cost at high volume.

  12. Wafer-Scale, Homogeneous MoS2 Layers on Plastic Substrates for Flexible Visible-Light Photodetectors.

    PubMed

    Lim, Yi Rang; Song, Wooseok; Han, Jin Kyu; Lee, Young Bum; Kim, Sung Jun; Myung, Sung; Lee, Sun Sook; An, Ki-Seok; Choi, Chel-Jong; Lim, Jongsun

    2016-07-01

    An appropriate solution is suggested for synthesizing wafer-scale, continuous, and stoichiometric MoS2 layers with spatial homogeneity at the low temperature of 450 °C. It is also demonstrated that the MoS2 -based visible-light photodetector arrays are both fabricated on 4 inch SiO2 /Si wafer and polyimide films, revealing 100% active devices with a narrow photocurrent distribution and excellent mechanical durability. PMID:27119775

  13. Wafer-scale high-throughput ordered growth of vertically aligned ZnO nanowire arrays.

    PubMed

    Wei, Yaguang; Wu, Wenzhuo; Guo, Rui; Yuan, Dajun; Das, Suman; Wang, Zhong Lin

    2010-09-01

    This article presents an effective approach for patterned growth of vertically aligned ZnO nanowire (NW) arrays with high throughput and low cost at wafer scale without using cleanroom technology. Periodic hole patterns are generated using laser interference lithography on substrates coated with the photoresist SU-8. ZnO NWs are selectively grown through the holes via a low-temperature hydrothermal method without using a catalyst and with a superior control over orientation, location/density, and as-synthesized morphology. The development of textured ZnO seed layers for replacing single crystalline GaN and ZnO substrates extends the large-scale fabrication of vertically aligned ZnO NW arrays on substrates of other materials, such as polymers, Si, and glass. This combined approach demonstrates a novel method of manufacturing large-scale patterned one-dimensional nanostructures on various substrates for applications in energy harvesting, sensing, optoelectronics, and electronic devices. PMID:20681617

  14. A Method to Pattern Silver Nanowires Directly on Wafer-Scale PDMS Substrate and Its Applications.

    PubMed

    Chou, Namsun; Kim, Youngseok; Kim, Sohee

    2016-03-01

    This study describes a fabrication method of microsized AgNW patterns based on poly dimethylsiloxane (PDMS) substrate using a poly(p-xylylene) (parylene) stencil technique. Various patterns of AgNW conductive sheets were created on the wafer scale area in the forms of straight and serpentine lines, texts, and symbols, which dimensions ranged from a few tens of micrometers to hundreds of micrometers. We demonstrated the electrical performance of straight line and serpentine line patterned AgNW electrodes when subjected to mechanical strains. The gauge factor and stretchability ranged from 0.5 to 55.2 at 2% uniaxial strain and from 4.7 to 55.7%, respectively, depending on the shapes and structures of the AgNW electrodes. Using the developed AgNW patterning technique, we fabricated strain sensors to detect small body signals epidermally such as hand motion, eye blink and heart rate. Also, tactile sensors were fabricated and exhibited the sensitivity of 3.91 MPa(-1) in the pressure range lower than 50 kPa, and 0.28 MPa(-1) in the pressure range greater than 50 kPa up to 1.3 MPa. From these results, we concluded that the proposed technique enables the fabrication of reliable AgNW patterns on wafer-scale PDMS substrate and the potential applications for various flexible electronic devices. PMID:26882099

  15. Wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible biomedical platform.

    PubMed

    Maeng, Jimin; Meng, Chuizhou; Irazoqui, Pedro P

    2015-02-01

    We present wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible parylene platform, as progress toward sustainably powering biomedical microsystems suitable for implantable and wearable applications. All-solid-state, low-profile (<30 μm), and high-density (up to ~500 μF/mm(2)) micro-supercapacitors are formed on an ultrathin (~20 μm) freestanding parylene film by a wafer-scale parylene packaging process in combination with a polyaniline (PANI) nanowire growth technique assisted by surface plasma treatment. These micro-supercapacitors are highly flexible and shown to be resilient toward flexural stress. Further, direct integration of micro-supercapacitors into a radio frequency (RF) rectifying circuit is achieved on a single parylene platform, yielding a complete RF energy harvesting microsystem. The system discharging rate is shown to improve by ~17 times in the presence of the integrated micro-supercapacitors. This result suggests that the integrated micro-supercapacitor technology described herein is a promising strategy for sustainably powering biomedical microsystems dedicated to implantable and wearable applications. PMID:25653069

  16. Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

    PubMed Central

    Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

    2014-01-01

    In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

  17. Face-to-face transfer of wafer-scale graphene films

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying

  18. Wafer-scale process and materials optimization in cross-flow atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Lecordier, Laurent Christophe

    The exceptional thickness control (atomic scale) and conformality (uniformity over nanoscale 3D features) of atomic layer deposition (ALD) has made it the process of choice for numerous applications from microelectronics to nanotechnology, and for a wide variety of ALD processes and resulting materials. While its benefits derive from self-terminated chemisorbed reactions of alternatively supplied gas precursors, identifying a suitable process window in which ALD's benefits are realized can be a challenge, even in favorable cases. In this work, a strategy exploiting in-situ gas phase sensing in conjunction with ex-situ measurements of the film properties at the wafer scale is employed to explore and optimize the prototypical Al2O3 ALD process. Downstream mass-spectrometry is first used to rapidly identify across the [H2O x Al(CH3)3] process space the exposure conditions leading to surface saturation. The impact of precursor doses outside as well as inside the parameter space outlined by mass-spectrometry is then investigated by characterizing film properties across 100 mm wafer using spectroscopic ellipsometry, CV and IV electrical characterization, XPS and SIMS. Under ideal dose conditions, excellent thickness uniformity was achieved (1sigma/mean<1%) in conjunction with a deposition rate and electrical properties in good agreement with best literature data. As expected, under-dosing of precursor results in depletion of film growth in the flow direction across the wafer surface. Since adsorbed species are reactive with respect to subsequent dose of the complementary precursor, such depletion magnifies non-uniformities as seen in the cross-flow reactor, thereby decorating deviations from a suitable ALD process recipe. Degradation of the permittivity and leakage current density across the wafer was observed though the film composition remained unchanged. Upon higher water dose in the over-exposure regime, deposition rates increased by up to 40% while the uniformity

  19. Face-to-face transfer of wafer-scale graphene films.

    PubMed

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying

  20. Assembly of LIGA using Electric Fields

    SciTech Connect

    FEDDEMA, JOHN T.; WARNE, LARRY K.; JOHNSON, WILLIAM A.; OGDEN, ALLISON J.; ARMOUR, DAVID L.

    2002-04-01

    The goal of this project was to develop a device that uses electric fields to grasp and possibly levitate LIGA parts. This non-contact form of grasping would solve many of the problems associated with grasping parts that are only a few microns in dimensions. Scaling laws show that for parts this size, electrostatic and electromagnetic forces are dominant over gravitational forces. This is why micro-parts often stick to mechanical tweezers. If these forces can be controlled under feedback control, the parts could be levitated, possibly even rotated in air. In this project, we designed, fabricated, and tested several grippers that use electrostatic and electromagnetic fields to grasp and release metal LIGA parts. The eventual use of this tool will be to assemble metal and non-metal LIGA parts into small electromechanical systems.

  1. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale.

    PubMed

    Berman, Diana; Deshmukh, Sanket A; Narayanan, Badri; Sankaranarayanan, Subramanian K R S; Yan, Zhong; Balandin, Alexander A; Zinovev, Alexander; Rosenmann, Daniel; Sumant, Anirudha V

    2016-01-01

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the process can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. In addition, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics. PMID:27373740

  2. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

    PubMed Central

    Berman, Diana; Deshmukh, Sanket A.; Narayanan, Badri; Sankaranarayanan, Subramanian K. R. S.; Yan, Zhong; Balandin, Alexander A.; Zinovev, Alexander; Rosenmann, Daniel; Sumant, Anirudha V.

    2016-01-01

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the process can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. In addition, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics. PMID:27373740

  3. Wafer-scale fabrication and growth dynamics of suspended graphene nanoribbon arrays

    NASA Astrophysics Data System (ADS)

    Suzuki, Hiroo; Kaneko, Toshiro; Shibuta, Yasushi; Ohno, Munekazu; Maekawa, Yuki; Kato, Toshiaki

    2016-06-01

    Adding a mechanical degree of freedom to the electrical and optical properties of atomically thin materials can provide an excellent platform to investigate various optoelectrical physics and devices with mechanical motion interaction. The large scale fabrication of such atomically thin materials with suspended structures remains a challenge. Here we demonstrate the wafer-scale bottom-up synthesis of suspended graphene nanoribbon arrays (over 1,000,000 graphene nanoribbons in 2 × 2 cm2 substrate) with a very high yield (over 98%). Polarized Raman measurements reveal graphene nanoribbons in the array can have relatively uniform-edge structures with near zigzag orientation dominant. A promising growth model of suspended graphene nanoribbons is also established through a comprehensive study that combined experiments, molecular dynamics simulations and theoretical calculations with a phase-diagram analysis. We believe that our results can contribute to pushing the study of graphene nanoribbons into a new stage related to the optoelectrical physics and industrial applications.

  4. Wafer-scale growth of MoS2 thin films by atomic layer deposition.

    PubMed

    Pyeon, Jung Joon; Kim, Soo Hyun; Jeong, Doo Seok; Baek, Seung-Hyub; Kang, Chong-Yun; Kim, Jin-Sang; Kim, Seong Keun

    2016-05-19

    The wafer-scale synthesis of MoS2 layers with precise thickness controllability and excellent uniformity is essential for their application in the nanoelectronics industry. Here, we demonstrate the atomic layer deposition (ALD) of MoS2 films with Mo(CO)6 and H2S as the Mo and S precursors, respectively. A self-limiting growth behavior is observed in the narrow ALD window of 155-175 °C. Long H2S feeding times are necessary to reduce the impurity contents in the films. The as-grown MoS2 films are amorphous due to the low growth temperature. Post-annealing at high temperatures under a H2S atmosphere efficiently improves the film properties including the crystallinity and chemical composition. An extremely uniform film growth is achieved even on a 4 inch SiO2/Si wafer. These results demonstrate that the current ALD process is well suited for the synthesis of MoS2 layers for application in industry. PMID:27166838

  5. Wafer-scale growth of MoS2 thin films by atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Pyeon, Jung Joon; Kim, Soo Hyun; Jeong, Doo Seok; Baek, Seung-Hyub; Kang, Chong-Yun; Kim, Jin-Sang; Kim, Seong Keun

    2016-05-01

    The wafer-scale synthesis of MoS2 layers with precise thickness controllability and excellent uniformity is essential for their application in the nanoelectronics industry. Here, we demonstrate the atomic layer deposition (ALD) of MoS2 films with Mo(CO)6 and H2S as the Mo and S precursors, respectively. A self-limiting growth behavior is observed in the narrow ALD window of 155-175 °C. Long H2S feeding times are necessary to reduce the impurity contents in the films. The as-grown MoS2 films are amorphous due to the low growth temperature. Post-annealing at high temperatures under a H2S atmosphere efficiently improves the film properties including the crystallinity and chemical composition. An extremely uniform film growth is achieved even on a 4 inch SiO2/Si wafer. These results demonstrate that the current ALD process is well suited for the synthesis of MoS2 layers for application in industry.

  6. Wafer scale fabrication of submicron chessboard gratings using phase masks in proximity lithography

    NASA Astrophysics Data System (ADS)

    Stuerzebecher, Lorenz; Harzendorf, Torsten; Fuchs, Frank; Zeitner, Uwe D.

    2012-03-01

    One and two dimensional grating structures with submicron period have a huge number of applications in optics and photonics. Such structures are conventionally fabricated using interference or e-beam lithography. However, both technologies have significant drawbacks. Interference lithography is limited to rather simple geometries and the sequential writing scheme of e-beam lithography leads to time consuming exposures for each grating. We present a novel fabrication technique for this class of microstructures which is based on proximity lithography in a mask aligner. The technology is capable to pattern a complete wafer within less than one minute of exposure time and offers thereby high lateral resolution and a reliable process. Our advancements compared to standard mask aligner lithography are twofold: First of all, we are using periodic binary phase masks instead of chromium masks to generate an aerial image of high resolution and exceptional light efficiency at certain distances behind the mask. Second, a special mask aligner illumination set-up is employed which allows to precisely control the incidence angles of the exposure light. This degree of freedom allows both, to shape the aerial image (e. g. transformation of a periodic spot pattern into a chessboard pattern) and to increase its depth of focus considerably. That way, our technology enables the fabrication of high quality gratings with arbitrary geometry in a fast and stable wafer scale process.

  7. Fabrication of CVD graphene-based devices via laser ablation for wafer-scale characterization

    NASA Astrophysics Data System (ADS)

    Mackenzie, David M. A.; Buron, Jonas D.; Whelan, Patrick R.; Jessen, Bjarke S.; Silajdźić, Adnan; Pesquera, Amaia; Centeno, Alba; Zurutuza, Amaia; Bøggild, Peter; Petersen, Dirch H.

    2015-12-01

    Selective laser ablation of a wafer-scale graphene film is shown to provide flexible, high speed (1 wafer/hour) device fabrication while avoiding the degradation of electrical properties associated with traditional lithographic methods. Picosecond laser pulses with single pulse peak fluences of 140 mJ cm-2 for 1064 nm, 40 mJ cm-2 for 532 nm, and 30 mJ cm-2 for 355 nm are sufficient to ablate the graphene film, while the ablation onset for Si/SiO2 (thicknesses 500 μm/302 nm) did not occur until 240 mJ cm-2, 150 mJ cm-2, and 135 mJ cm-2, respectively, allowing all wavelengths to be used for graphene ablation without detectable substrate damage. Optical microscopy and Raman Spectroscopy were used to assess the ablation of graphene, while stylus profilometery indicated that the SiO2 substrate was undamaged. CVD graphene devices were electrically characterized and showed comparable field-effect mobility, doping level, on-off ratio, and conductance minimum before and after laser ablation fabrication.

  8. Wafer-scale epitaxial graphene on SiC for sensing applications

    NASA Astrophysics Data System (ADS)

    Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

    2015-12-01

    The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

  9. Terahertz wafer-scale mobility mapping of graphene on insulating substrates without a gate.

    PubMed

    Buron, Jonas D; Mackenzie, David M A; Petersen, Dirch H; Pesquera, Amaia; Centeno, Alba; Bøggild, Peter; Zurutuza, Amaia; Jepsen, Peter U

    2015-11-30

    We demonstrate wafer-scale, non-contact mapping of essential carrier transport parameters, carrier mobility (µdrift), carrier density (Ns), DC sheet conductance (σdc), and carrier scattering time (τsc) in CVD graphene, using spatially resolved terahertz time-domain conductance spectroscopy. σdc and τsc are directly extracted from Drude model fits to terahertz conductance spectra obtained in each pixel of 10 × 10 cm2 maps with a 400 µm step size. σdc- and τsc-maps are translated into µdrift and Ns maps through Boltzmann transport theory for graphene charge carriers and these parameters are directly compared to van der Pauw device measurements on the same wafer. The technique is compatible with all substrate materials that exhibit a reasonably low absorption coefficient for terahertz radiation. This includes many materials used for transferring CVD graphene in production facilities as well as in envisioned products, such as polymer films, glass substrates, cloth, or paper substrates. PMID:26698704

  10. High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity.

    PubMed

    Kang, Kibum; Xie, Saien; Huang, Lujie; Han, Yimo; Huang, Pinshane Y; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-04-30

    The large-scale growth of semiconducting thin films forms the basis of modern electronics and optoelectronics. A decrease in film thickness to the ultimate limit of the atomic, sub-nanometre length scale, a difficult limit for traditional semiconductors (such as Si and GaAs), would bring wide benefits for applications in ultrathin and flexible electronics, photovoltaics and display technology. For this, transition-metal dichalcogenides (TMDs), which can form stable three-atom-thick monolayers, provide ideal semiconducting materials with high electrical carrier mobility, and their large-scale growth on insulating substrates would enable the batch fabrication of atomically thin high-performance transistors and photodetectors on a technologically relevant scale without film transfer. In addition, their unique electronic band structures provide novel ways of enhancing the functionalities of such devices, including the large excitonic effect, bandgap modulation, indirect-to-direct bandgap transition, piezoelectricity and valleytronics. However, the large-scale growth of monolayer TMD films with spatial homogeneity and high electrical performance remains an unsolved challenge. Here we report the preparation of high-mobility 4-inch wafer-scale films of monolayer molybdenum disulphide (MoS2) and tungsten disulphide, grown directly on insulating SiO2 substrates, with excellent spatial homogeneity over the entire films. They are grown with a newly developed, metal-organic chemical vapour deposition technique, and show high electrical performance, including an electron mobility of 30 cm(2) V(-1) s(-1) at room temperature and 114 cm(2) V(-1) s(-1) at 90 K for MoS2, with little dependence on position or channel length. With the use of these films we successfully demonstrate the wafer-scale batch fabrication of high-performance monolayer MoS2 field-effect transistors with a 99% device yield and the multi-level fabrication of vertically stacked transistor devices for three

  11. Wafer-scale, three-dimensional helical porous thin films deposited at a glancing angle

    NASA Astrophysics Data System (ADS)

    Huang, Zhifeng; Bai, Fan

    2014-07-01

    Minimization of helices opens a door to impose novel functions derived from the dimensional shrinkage of optical, mechanical and electronic devices. Glancing angle deposition (GLAD) enables one to deposit three-dimensional helical porous thin films (HPTFs) composed of separated spiral micro/nano-columns. GLAD integrates a series of advantageous features, including one-step deposition, wafer-scale production with mono-handedness of spirals, flexible engineering of spiral materials and dimensions, and the adaption to various kinds of substrates. Herein, we briefly review the fabrication of HPTFs by GLAD, specific growth mechanisms, physical properties in structures, mechanics and chiral optics, and the emerging applications in green energy. A prospective outlook is presented to illuminate some promising developments in enantioselection, bio-dynamic analyses, wirelessly-controlled drug delivery and mass production.

  12. Near-infrared tailored thermal emission from wafer-scale continuous-film resonators.

    PubMed

    Roberts, Alexander S; Chirumamilla, Manohar; Thilsing-Hansen, Kasper; Pedersen, Kjeld; Bozhevolnyi, Sergey I

    2015-09-21

    We experimentally investigate the near-infrared emission from simple-to-fabricate, continuous-film Fabry-Perot-type resonators, consisting only of unstructured dielectric and metallic films. We show that the proposed configuration is suitable for realization of narrowband emitters, tunable in ranges from mid- to near-infrared, and demonstrate emission centered at the wavelength of 1.7 μm, which corresponds to the band gap energy of GaSb-based photodetectors. The emission is measured at 748 K and follows well the emissivity as predicted from reflection measurements and Kirchhoff's reciprocity. The considered emitter configuration is spectrally highly tunable and, consisting of only few unstructured layers, is amenable to wafer-scale fabrication at low cost by use of standard deposition procedures. PMID:26406741

  13. Wafer-scale MoS2 thin layers prepared by MoO3 sulfurization.

    PubMed

    Lin, Yu-Chuan; Zhang, Wenjing; Huang, Jing-Kai; Liu, Keng-Ku; Lee, Yi-Hsien; Liang, Chi-Te; Chu, Chih-Wei; Li, Lain-Jong

    2012-10-21

    Atomically thin molybdenum disulfide (MoS(2)) layers have attracted great interest due to their direct-gap property and potential applications in optoelectronics and energy harvesting. Meanwhile, they are extremely bendable, promising for applications in flexible electronics. However, the synthetic approach to obtain large-area MoS(2) atomic thin layers is still lacking. Here we report that wafer-scale MoS(2) thin layers can be obtained using MoO(3) thin films as a starting material followed by a two-step thermal process, reduction of MoO(3) at 500 °C in hydrogen and sulfurization at 1000 °C in the presence of sulfur. Spectroscopic, optical and electrical characterizations reveal that these films are polycrystalline and with semiconductor properties. The obtained MoS(2) films are uniform in thickness and easily transferable to arbitrary substrates, which make such films suitable for flexible electronics or optoelectronics. PMID:22983609

  14. High speed wafer scale bulge testing for the determination of thin film mechanical properties

    PubMed Central

    Orthner, M. P.; Rieth, L. W.; Solzbacher, F.

    2010-01-01

    A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50–150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 μm in width comprised of 720±10 nm thick low pressure chemical vapor deposited silicon nitride with ∼20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to ∼8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (∼350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young’s modulus was estimated for the films assuming a Poisson’s ratio of v=0.25. Calculations to determine Young’s modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young’s modulus for the smaller membranes. The deflection measurements of three 1200×1200

  15. High speed wafer scale bulge testing for the determination of thin film mechanical properties

    NASA Astrophysics Data System (ADS)

    Orthner, M. P.; Rieth, L. W.; Solzbacher, F.

    2010-05-01

    A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50-150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 μm in width comprised of 720±10 nm thick low pressure chemical vapor deposited silicon nitride with ˜20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to ˜8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (˜350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young's modulus was estimated for the films assuming a Poisson's ratio of v =0.25. Calculations to determine Young's modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young's modulus for the smaller membranes. The deflection measurements of three 1200×1200 μm2 Si3N4-x

  16. High speed wafer scale bulge testing for the determination of thin film mechanical properties.

    PubMed

    Orthner, M P; Rieth, L W; Solzbacher, F

    2010-05-01

    A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50-150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 microm in width comprised of 720+/-10 nm thick low pressure chemical vapor deposited silicon nitride with approximately 20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to approximately 8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (approximately 350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young's modulus was estimated for the films assuming a Poisson's ratio of v=0.25. Calculations to determine Young's modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young's modulus for the smaller membranes. The deflection

  17. Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale

    PubMed Central

    2013-01-01

    We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production. PMID:24289275

  18. Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale

    NASA Astrophysics Data System (ADS)

    Ho, Jian-Wei; Wee, Qixun; Dumond, Jarrett; Tay, Andrew; Chua, Soo-Jin

    2013-12-01

    We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production.

  19. Resolution enhancement using plasmonic metamask for wafer-scale photolithography in the far field

    PubMed Central

    Baek, Seunghwa; Kang, Gumin; Kang, Min; Lee, Chang-Won; Kim, Kyoungsik

    2016-01-01

    Resolution enhancement in far-field photolithography is demonstrated using a plasmonic metamask in the proximity regime, in which Fresnel diffraction is dominant. The transverse magnetic component of the diffracted wave from the photomask, which reduces the pattern visibility and lowers the resolution, was successfully controlled by coupling with the anti-symmetric mode of the excited surface plasmon. We obtained a consistently finely-patterned photoresist surface at a distance of up to 15 μm from the mask surface for 3-μm-pitch slits because of conserved field visibility when propagating from the near-field to the proximity regime. We confirmed that sharp edge patterning is indeed possible when using a wafer-scale photomask in the proximity photolithography regime. Our plasmonic metamask method produces cost savings for ultra-large-scale high-density display fabrication by maintaining longer photomask lifetimes and by allowing sufficient tolerance for the distance between the photomask and the photoresist. PMID:27457127

  20. Wafer-scale fabrication and growth dynamics of suspended graphene nanoribbon arrays

    PubMed Central

    Suzuki, Hiroo; Kaneko, Toshiro; Shibuta, Yasushi; Ohno, Munekazu; Maekawa, Yuki; Kato, Toshiaki

    2016-01-01

    Adding a mechanical degree of freedom to the electrical and optical properties of atomically thin materials can provide an excellent platform to investigate various optoelectrical physics and devices with mechanical motion interaction. The large scale fabrication of such atomically thin materials with suspended structures remains a challenge. Here we demonstrate the wafer-scale bottom–up synthesis of suspended graphene nanoribbon arrays (over 1,000,000 graphene nanoribbons in 2 × 2 cm2 substrate) with a very high yield (over 98%). Polarized Raman measurements reveal graphene nanoribbons in the array can have relatively uniform-edge structures with near zigzag orientation dominant. A promising growth model of suspended graphene nanoribbons is also established through a comprehensive study that combined experiments, molecular dynamics simulations and theoretical calculations with a phase-diagram analysis. We believe that our results can contribute to pushing the study of graphene nanoribbons into a new stage related to the optoelectrical physics and industrial applications. PMID:27250877

  1. Wafer-Scale Monolayer Films of Semiconducting Metal Dichalcogenides for High-Performance Electronics

    NASA Astrophysics Data System (ADS)

    Xie, Saien; Kang, Kibum; Huang, Lujie; Han, Yimo; Huang, Pinshane; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-03-01

    Two-dimensional semiconducting transition metal dichalcogenides (TMDs) have shown their potential in electronics, optoelectronic and valleytronis. However, large-scale growth methods reported to date have only produced materials with limited structural and electrical uniformity, hindering further technological applications. Here we present a 4-inch scale growth of continuous monolayer molybdenum disulfide (MoS2) and tungsten disulfide (WS2) films that show excellent structural and electrical uniformity over the entire wafer using metal-organic chemical vapor deposition. The resulting monolayer films show high mobility of 30 cm2/Vs at room temperature, as well as the phonon-limited transport for MoS2, regardless of the channel length and device location. They allow for the batch fabrication of monolayer MoS2 field effect transistors with a 99% yield, which display spatially-uniform n-type transistor operation with a high on/off ratio. We further demonstrate the multi-level growth and fabrication of vertically-stacked monolayer MoS2 films and devices, which could enable the development of novel three-dimensional circuitry and device integration.

  2. Resolution enhancement using plasmonic metamask for wafer-scale photolithography in the far field.

    PubMed

    Baek, Seunghwa; Kang, Gumin; Kang, Min; Lee, Chang-Won; Kim, Kyoungsik

    2016-01-01

    Resolution enhancement in far-field photolithography is demonstrated using a plasmonic metamask in the proximity regime, in which Fresnel diffraction is dominant. The transverse magnetic component of the diffracted wave from the photomask, which reduces the pattern visibility and lowers the resolution, was successfully controlled by coupling with the anti-symmetric mode of the excited surface plasmon. We obtained a consistently finely-patterned photoresist surface at a distance of up to 15 μm from the mask surface for 3-μm-pitch slits because of conserved field visibility when propagating from the near-field to the proximity regime. We confirmed that sharp edge patterning is indeed possible when using a wafer-scale photomask in the proximity photolithography regime. Our plasmonic metamask method produces cost savings for ultra-large-scale high-density display fabrication by maintaining longer photomask lifetimes and by allowing sufficient tolerance for the distance between the photomask and the photoresist. PMID:27457127

  3. Wafer-scale MoS2 thin layers prepared by MoO3 sulfurization

    NASA Astrophysics Data System (ADS)

    Lin, Yu-Chuan; Zhang, Wenjing; Huang, Jing-Kai; Liu, Keng-Ku; Lee, Yi-Hsien; Liang, Chi-Te; Chu, Chih-Wei; Li, Lain-Jong

    2012-09-01

    Atomically thin molybdenum disulfide (MoS2) layers have attracted great interest due to their direct-gap property and potential applications in optoelectronics and energy harvesting. Meanwhile, they are extremely bendable, promising for applications in flexible electronics. However, the synthetic approach to obtain large-area MoS2 atomic thin layers is still lacking. Here we report that wafer-scale MoS2 thin layers can be obtained using MoO3 thin films as a starting material followed by a two-step thermal process, reduction of MoO3 at 500 °C in hydrogen and sulfurization at 1000 °C in the presence of sulfur. Spectroscopic, optical and electrical characterizations reveal that these films are polycrystalline and with semiconductor properties. The obtained MoS2 films are uniform in thickness and easily transferable to arbitrary substrates, which make such films suitable for flexible electronics or optoelectronics.Atomically thin molybdenum disulfide (MoS2) layers have attracted great interest due to their direct-gap property and potential applications in optoelectronics and energy harvesting. Meanwhile, they are extremely bendable, promising for applications in flexible electronics. However, the synthetic approach to obtain large-area MoS2 atomic thin layers is still lacking. Here we report that wafer-scale MoS2 thin layers can be obtained using MoO3 thin films as a starting material followed by a two-step thermal process, reduction of MoO3 at 500 °C in hydrogen and sulfurization at 1000 °C in the presence of sulfur. Spectroscopic, optical and electrical characterizations reveal that these films are polycrystalline and with semiconductor properties. The obtained MoS2 films are uniform in thickness and easily transferable to arbitrary substrates, which make such films suitable for flexible electronics or optoelectronics. Electronic supplementary information (ESI) available. See DOI: 10.1039/c2nr31833d

  4. Wafer-scale high-resolution patterning of reduced graphene oxide films for detection of low concentration biomarkers in plasma

    NASA Astrophysics Data System (ADS)

    Kim, Jinsik; Chae, Myung-Sic; Lee, Sung Min; Jeong, Dahye; Lee, Byung Chul; Lee, Jeong Hoon; Kim, Youngsoo; Chang, Suk Tai; Hwang, Kyo Seon

    2016-08-01

    Given that reduced graphene oxide (rGO)-based biosensors allow disposable and repeatable biomarker detection at the point of care, we developed a wafer-scale rGO patterning method with mass productivity, uniformity, and high resolution by conventional micro-electro-mechanical systems (MEMS) techniques. Various rGO patterns were demonstrated with dimensions ranging from 5 μm up to several hundred μm. Manufacture of these patterns was accomplished through the optimization of dry etching conditions. The axis-homogeneity and uniformity were also measured to verify the uniform patternability in 4-inch wafer with dry etching. Over 66.2% of uniform rGO patterns, which have deviation of resistance within range of ±10%, formed the entire wafer. We selected amyloid beta (Aβ) peptides in the plasma of APP/PS1 transgenic mice as a study model and measured the peptide level by resistance changes of highly uniform rGO biosensor arrays. Aβ is a pathological hallmark of Alzheimer’s disease and its plasma concentration is in the pg mL‑1 range. The sensor detected the Aβ peptides with ultra-high sensitivity; the LOD was at levels as low as 100 fg mL‑1. Our results provide biological evidences that this wafer-scale high-resolution patterning method can be used in rGO-based electrical diagnostic devices for detection of low-level protein biomarkers in biofluids.

  5. Wafer-scale high-resolution patterning of reduced graphene oxide films for detection of low concentration biomarkers in plasma.

    PubMed

    Kim, Jinsik; Chae, Myung-Sic; Lee, Sung Min; Jeong, Dahye; Lee, Byung Chul; Lee, Jeong Hoon; Kim, YoungSoo; Chang, Suk Tai; Hwang, Kyo Seon

    2016-01-01

    Given that reduced graphene oxide (rGO)-based biosensors allow disposable and repeatable biomarker detection at the point of care, we developed a wafer-scale rGO patterning method with mass productivity, uniformity, and high resolution by conventional micro-electro-mechanical systems (MEMS) techniques. Various rGO patterns were demonstrated with dimensions ranging from 5 μm up to several hundred μm. Manufacture of these patterns was accomplished through the optimization of dry etching conditions. The axis-homogeneity and uniformity were also measured to verify the uniform patternability in 4-inch wafer with dry etching. Over 66.2% of uniform rGO patterns, which have deviation of resistance within range of ±10%, formed the entire wafer. We selected amyloid beta (Aβ) peptides in the plasma of APP/PS1 transgenic mice as a study model and measured the peptide level by resistance changes of highly uniform rGO biosensor arrays. Aβ is a pathological hallmark of Alzheimer's disease and its plasma concentration is in the pg mL(-1) range. The sensor detected the Aβ peptides with ultra-high sensitivity; the LOD was at levels as low as 100 fg mL(-1). Our results provide biological evidences that this wafer-scale high-resolution patterning method can be used in rGO-based electrical diagnostic devices for detection of low-level protein biomarkers in biofluids. PMID:27506288

  6. Wafer-scale high-resolution patterning of reduced graphene oxide films for detection of low concentration biomarkers in plasma

    PubMed Central

    Kim, Jinsik; Chae, Myung-Sic; Lee, Sung Min; Jeong, Dahye; Lee, Byung Chul; Lee, Jeong Hoon; Kim, YoungSoo; Chang, Suk Tai; Hwang, Kyo Seon

    2016-01-01

    Given that reduced graphene oxide (rGO)-based biosensors allow disposable and repeatable biomarker detection at the point of care, we developed a wafer-scale rGO patterning method with mass productivity, uniformity, and high resolution by conventional micro-electro-mechanical systems (MEMS) techniques. Various rGO patterns were demonstrated with dimensions ranging from 5 μm up to several hundred μm. Manufacture of these patterns was accomplished through the optimization of dry etching conditions. The axis-homogeneity and uniformity were also measured to verify the uniform patternability in 4-inch wafer with dry etching. Over 66.2% of uniform rGO patterns, which have deviation of resistance within range of ±10%, formed the entire wafer. We selected amyloid beta (Aβ) peptides in the plasma of APP/PS1 transgenic mice as a study model and measured the peptide level by resistance changes of highly uniform rGO biosensor arrays. Aβ is a pathological hallmark of Alzheimer’s disease and its plasma concentration is in the pg mL−1 range. The sensor detected the Aβ peptides with ultra-high sensitivity; the LOD was at levels as low as 100 fg mL−1. Our results provide biological evidences that this wafer-scale high-resolution patterning method can be used in rGO-based electrical diagnostic devices for detection of low-level protein biomarkers in biofluids. PMID:27506288

  7. Wafer-scale arrays of nonvolatile polymer memories with microprinted semiconducting small molecule/polymer blends.

    PubMed

    Bae, Insung; Hwang, Sun Kak; Kim, Richard Hahnkee; Kang, Seok Ju; Park, Cheolmin

    2013-11-13

    Nonvolatile ferroelectric-gate field-effect transistors (Fe-FETs) memories with solution-processed ferroelectric polymers are of great interest because of their potential for use in low-cost flexible devices. In particular, the development of a process for patterning high-performance semiconducting channel layers with mechanical flexibility is essential not only for proper cell-to-cell isolation but also for arrays of flexible nonvolatile memories. We demonstrate a robust route for printing large-scale micropatterns of solution-processed semiconducting small molecules/insulating polymer blends for high performance arrays of nonvolatile ferroelectric polymer memory. The nonvolatile memory devices are based on top-gate/bottom-contact Fe-FET with ferroelectric polymer insulator and micropatterned semiconducting blend channels. Printed micropatterns of a thin blended semiconducting film were achieved by our selective contact evaporation printing, with which semiconducting small molecules in contact with a micropatterned elastomeric poly(dimethylsiloxane) (PDMS) mold were preferentially evaporated and absorbed into the PDMS mold while insulating polymer remained intact. Well-defined micrometer-scale patterns with various shapes and dimensions were readily developed over a very large area on a 4 in. wafer, allowing for fabrication of large-scale printed arrays of Fe-FETs with highly uniform device performance. We statistically analyzed the memory properties of Fe-FETs, including ON/OFF ratio, operation voltage, retention, and endurance, as a function of the micropattern dimensions of the semiconducting films. Furthermore, roll-up memory arrays were produced by successfully detaching large-area Fe-FETs printed on a flexible substrate with a transient adhesive layer from a hard substrate and subsequently transferring them to a nonplanar surface. PMID:24070419

  8. Wafer-scale design of lightweight and transparent electronics that wraps around hairs

    NASA Astrophysics Data System (ADS)

    Salvatore, Giovanni A.; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

    2014-01-01

    Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

  9. Wafer-scale self-organized InP nanopillars with controlled orientation for photovoltaic devices.

    PubMed

    Sanatinia, Reza; Berrier, Audrey; Dhaka, Veer; Perros, Alexander P; Huhtio, Teppo; Lipsanen, Harri; Anand, Srinivasan

    2015-10-16

    A unique wafer-scale self-organization process for generation of InP nanopillars is demonstrated, which is based on maskless ion-beam etching (IBE) of InP developed to obtain the nanopillars, where the height, shape, and orientation of the nanopillars can be varied by controlling the processing parameters. The fabricated InP nanopillars exhibit broadband suppression of the reflectance, 'black InP,' a property useful for solar cells. The realization of a conformal p-n junction for carrier collection, in the fabricated solar cells, is achieved by a metalorganic vapor phase epitaxy (MOVPE) overgrowth step on the fabricated pillars. The conformal overgrowth retains the broadband anti-reflection property of the InP nanopillars, indicating the feasibility of this technology for solar cells. Surface passivation of the formed InP nanopillars using sulfur-oleylamine solution resulted in improved solar-cell characteristics. An open-circuit voltage of 0.71 V and an increase of 0.13 V compared to the unpassivated device were achieved. PMID:26403979

  10. Surface plasmon assisted hot electron collection in wafer-scale metallic-semiconductor photonic crystals.

    PubMed

    Chou, Jeffrey B; Li, Xin-Hao; Wang, Yu; Fenning, David P; Elfaer, Asmaa; Viegas, Jaime; Jouiad, Mustapha; Shao-Horn, Yang; Kim, Sang-Gook

    2016-09-01

    Plasmon assisted photoelectric hot electron collection in a metal-semiconductor junction can allow for sub-bandgap optical to electrical energy conversion. Here we report hot electron collection by wafer-scale Au/TiO2 metallic-semiconductor photonic crystals (MSPhC), with a broadband photoresponse below the bandgap of TiO2. Multiple absorption modes supported by the 2D nano-cavity structure of the MSPhC extend the photon-metal interaction time and fulfill a broadband light absorption. The surface plasmon absorption mode provides access to enhanced electric field oscillation and hot electron generation at the interface between Au and TiO2. A broadband sub-bandgap photoresponse centered at 590 nm was achieved due to surface plasmon absorption. Gold nanorods were deposited on the surface of MSPhC to study localized surface plasmon (LSP) mode absorption and subsequent injection to the TiO2 catalyst at different wavelengths. Applications of these results could lead to low-cost and robust photo-electrochemical applications such as more efficient solar water splitting. PMID:27607726

  11. Wafer-scale synthesis of multi-layer graphene by high-temperature carbon ion implantation

    SciTech Connect

    Kim, Janghyuk; Lee, Geonyeop; Kim, Jihyun

    2015-07-20

    We report on the synthesis of wafer-scale (4 in. in diameter) high-quality multi-layer graphene using high-temperature carbon ion implantation on thin Ni films on a substrate of SiO{sub 2}/Si. Carbon ions were bombarded at 20 keV and a dose of 1 × 10{sup 15 }cm{sup −2} onto the surface of the Ni/SiO{sub 2}/Si substrate at a temperature of 500 °C. This was followed by high-temperature activation annealing (600–900 °C) to form a sp{sup 2}-bonded honeycomb structure. The effects of post-implantation activation annealing conditions were systematically investigated by micro-Raman spectroscopy and transmission electron microscopy. Carbon ion implantation at elevated temperatures allowed a lower activation annealing temperature for fabricating large-area graphene. Our results indicate that carbon-ion implantation provides a facile and direct route for integrating graphene with Si microelectronics.

  12. Wafer-scale highly-transparent and superhydrophilic sapphires for high-performance optics.

    PubMed

    Leem, Jung Woo; Yu, Jae Su

    2012-11-19

    We reported the wafer-scale highly-transparent and superhydrophilic sapphires with antireflective subwavelength structures (SWSs) which were fabricated by dry etching using thermally dewetted gold (Au) nanomasks. Their optical transmittance properties were experimentally and theoretically investigated. The density, size, and period of the thermally dewetted Au nanopatterns can be controlled by the Au film thickness. For the sapphire with both-side SWSs at 5 nm of Au film, the average total transmittance (T(avg)) of ~96.5% at 350-800 nm was obtained, indicating a higher value than those of the flat sapphire (T(avg)~85.6%) and the sapphire with one-side SWSs (T(avg)~91%), and the less angle-dependent transmittance property was observed. The calculated transmittance results also showed a similar tendency to the measured data. The SWSs enhanced significantly the surface hydrophilicity of sapphires, exhibiting a water contact angle (θ(c)) of < 5° for Au film of 5 nm compared to θ(c)~37° of the flat sapphire. PMID:23187471

  13. Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy

    PubMed Central

    Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

    2013-01-01

    The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (“metasurfaces”) can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

  14. A wafer-scale backplane-assisted resonating nanoantenna array SERS device created by tunable thermal dewetting nanofabrication

    NASA Astrophysics Data System (ADS)

    Chang, Te-Wei; Ranjan Gartia, Manas; Seo, Sujin; Hsiao, Austin; Logan Liu, Gang

    2014-04-01

    A tunable lithography-less nanofabrication process using a metal thin-film thermal dewetting technique has been developed to fabricate wafer-scale and uniform plasmonic substrates at low cost for optimal performance in surface enhanced Raman scattering (SERS) applications. The relationship between the tunable parameters of this process and the corresponding optical and plasmonic characteristic is investigated both experimentally and theoretically to understand the deterministic design of an optimal SERS device with a three-dimensional plasmonic nanoantenna structure. The enhancement of SERS using various nanoplasmonic particle sizes, structure lengths, lateral hot spot spacings and resonating effects are examined and demonstrated. We achieve a uniform optimal enhancement factor of 1.38 × 108 on a 4 in wafer-scale SERS substrate with a backplane-assisted resonating nanoantenna array design. Sensitive environmental nitrate sensing, vitamin detection and oligonucleotide identification are demonstrated on the high-performance SERS device.

  15. Crack-release transfer method of wafer-scale grown graphene onto large-area substrates.

    PubMed

    Lee, Jooho; Kim, Yongsung; Shin, Hyeon-Jin; Lee, ChangSeung; Lee, Dongwook; Lee, Sunghee; Moon, Chang-Yul; Lee, Su Chan; Kim, Sun Jun; Ji, Jae Hoon; Yoon, Hyong Seo; Jun, Seong Chan

    2014-08-13

    We developed a crack-release graphene transfer technique for opening up possibilities for the fabrication of graphene-based devices. Graphene film grown on metal catalysts/SiO2/Si wafer should be scathelessly peeled for sequent transferring to a target substrate. However, when the graphene is grown on the metal catalyst on a silicon substrate, there is a large tensile stress resulting from the difference of the coefficient of thermal expansion in the catalyst and silicon. The conventional methods of detaching graphene from metal catalysts were found to induce considerable mechanical damage on graphene films during separation processes including metal wet etching. Here we report a new technique wherein bubbles generated by electrolysis reaction separate thin metal catalysts from the SiO2/Si wafer. The dry attachment of graphene to the target wafer was processed utilizing a wafer to wafer bonding technique in a vacuum. We measured the microscopic image, Raman spectra, and electrical properties of the transferred graphene. The optical and electrical properties of the graphene transferred by the bubbles/dry method are better than those of the graphene obtained by mechanical/wet transfer. PMID:24967530

  16. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  17. Field-effect transistors based on wafer-scale, highly uniform few-layer p-type WSe2

    NASA Astrophysics Data System (ADS)

    Campbell, Philip M.; Tarasov, Alexey; Joiner, Corey A.; Tsai, Meng-Yen; Pavlidis, Georges; Graham, Samuel; Ready, W. Jud; Vogel, Eric M.

    2016-01-01

    The synthesis of few-layer tungsten diselenide (WSe2) via chemical vapor deposition typically results in highly non-uniform thickness due to nucleation initiated growth of triangular domains. In this work, few-layer p-type WSe2 with wafer-scale thickness and electrical uniformity is synthesized through direct selenization of thin films of e-beam evaporated W on SiO2 substrates. Raman maps over a large area of the substrate show small variations in the main peak position, indicating excellent thickness uniformity across several square centimeters. Additionally, field-effect transistors fabricated from the wafer-scale WSe2 films demonstrate uniform electrical performance across the substrate. The intrinsic field-effect mobility of the films at a carrier concentration of 3 × 1012 cm-2 is 10 cm2 V-1 s-1. The unprecedented uniformity of the WSe2 on wafer-scale substrates provides a substantial step towards producing manufacturable materials that are compatible with conventional semiconductor fabrication processes.

  18. Field-effect transistors based on wafer-scale, highly uniform few-layer p-type WSe2.

    PubMed

    Campbell, Philip M; Tarasov, Alexey; Joiner, Corey A; Tsai, Meng-Yen; Pavlidis, Georges; Graham, Samuel; Ready, W Jud; Vogel, Eric M

    2016-01-28

    The synthesis of few-layer tungsten diselenide (WSe2) via chemical vapor deposition typically results in highly non-uniform thickness due to nucleation initiated growth of triangular domains. In this work, few-layer p-type WSe2 with wafer-scale thickness and electrical uniformity is synthesized through direct selenization of thin films of e-beam evaporated W on SiO2 substrates. Raman maps over a large area of the substrate show small variations in the main peak position, indicating excellent thickness uniformity across several square centimeters. Additionally, field-effect transistors fabricated from the wafer-scale WSe2 films demonstrate uniform electrical performance across the substrate. The intrinsic field-effect mobility of the films at a carrier concentration of 3 × 10(12) cm(-2) is 10 cm(2) V(-1) s(-1). The unprecedented uniformity of the WSe2 on wafer-scale substrates provides a substantial step towards producing manufacturable materials that are compatible with conventional semiconductor fabrication processes. PMID:26743173

  19. Surface microstructuring of biocompatible bone analogue material HAPEX using LIGA technique and embossing

    NASA Astrophysics Data System (ADS)

    Schneider, Andreas; Rea, Susan; Huq, Ejaz; Bonfield, William

    2003-04-01

    HAPEX is an artificial bone analogue composite based on hydroxyapatite and polyethylene, which can be applied for growth of bone cells. Due to its biocompatibility and favourable mechanical properties, HAPEX is used for orthopaedic implants like tympanic (middle ear) bones. The morphology of HAPEX surfaces is of high interest and it is believed that surface structuring on a micron scale might improve the growth conditions for bone cells. A new and simple approach for the microstructuring of HAPEX surfaces has been investigated using LIGA technique. LIGA is a combination of several processes, in particular lithography, electroplating and forming/moulding. For HAPEX surface structuring, arrays of dots, grids and lines with typical lateral dimension ranging from 5 μm to 50 μm were created on a chromium photomask and the patterns were transferred into thick SU-8 photoresist (structure height > 10 μm) by UV lithography. Subsequently, the SU-8 structures served as moulds for electroplating nickel on Si wafers and nickel substrates. The final nickel microstructures were used as embossing master for the HAPEX material. Embossing was carried out using a conventional press (> 500 hPa) with the facility to heat the master and the HAPEX. The temperature ranged from ambient to a few degrees above glass transition temperature (Tg) of HAPEX. The paper will include details of the fabrication process and process tolerances in lateral and vertical directions. Data obtained are correlated to the temperature used during embossing.

  20. Wafer-scale arrayed p-n junctions based on few-layer epitaxial GaTe

    NASA Astrophysics Data System (ADS)

    Yuan, Xiang; Tang, Lei; Hu, Weida; Xiu, Faxian

    2015-03-01

    Two dimensional (2D) materials have showed appealing applications in electronics and optoelectronics. Gapless graphene presents ultra-broadband and fast photoresponse while the 2D semiconducting MoS2 and GaTe exhibit highly sensitive and tunable responsivity to the visible light. However, the device yield and its repeatability call for a further improvement of 2D materials to render large-scale uniformity. Here we report a layer-by-layer growth of the wafer-scale GaTe by molecular beam epitaxy. To develop the arrayed p-n junctions, the few-layer GaTe was grew on three-inch Si wafers. The resultant diodes reveal good rectifying characteristics and photoresponse with maximum photodetection responsivity of 2.74 A/W and photovoltaic external quantum efficiency up to 62%. The photocurrent reaches saturation very fast within 22 μs and shows no sign of device degradation after 1.37 million cycles of operation. Most strikingly, such high performance has been achieved across the entire wafer, making the volume production of devices accessible. Finally, several photo-images was acquired by using these photodiodes with a reasonable contrast and resolution, demonstrating for the first time the potential for these 2D technology coming into the real life.

  1. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    NASA Astrophysics Data System (ADS)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  2. Wafer-scale fabrication of transistors using CVD-grown graphene and its application to inverter circuit

    NASA Astrophysics Data System (ADS)

    Nakaharai, Shu; Iijima, Tomohiko; Ogawa, Shinichi; Yagi, Katsunori; Harada, Naoki; Hayashi, Kenjiro; Kondo, Daiyu; Takahashi, Makoto; Li, Songlin; Tsukagoshi, Kazuhito; Sato, Shintaro; Yokoyama, Naoki

    2015-04-01

    Graphene transistors were fabricated by a wafer-scale “top-down” process using a graphene sheet formed by the chemical vapor deposition (CVD) method. The devices have a dual-gated structure with an ion-irradiated channel, in which transistor polarity can be electrostatically controlled. We demonstrated, at room temperature, an on/off operation of current and electrostatic control of transistor polarity. By combining two dual-gated transistors, a six-terminal device was fabricated with three top gates and two ion-irradiated channels. In this device, we demonstrated an inverter operation.

  3. Fabrication of a wafer-scale uniform array of single-crystal organic nanowire complementary inverters by nanotransfer printing

    NASA Astrophysics Data System (ADS)

    Park, Kyung Sun; Baek, Jangmi; Koo Lee, Yong-Eun; Sung, Myung Mo

    2015-02-01

    We report the fabrication and electrical characterization of a wafer-scale array of organic complementary inverters using single-crystal 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-PEN) and fullerene (C60) nanowires as p- and n-channels, respectively. Two arrays of single-crystal organic nanowires were generated consecutively on desired locations of a common substrate with a desired mutual alignment by a direct printing method (liquid-bridge-mediated nanotransfer molding). Another direct printing of silver micron scale structures, as source and drain electrodes, on the substrate with the two printed nanowire arrays produced an array of complementary inverters with a bottom gate, top contact configuration. Field-effect mobilities of single-crystal TIPS-PEN and C60 nanowire field-effect transistors (FETs) in the arrays were uniform with 1.01 ± 0.14 and 0.10 ± 0.01 cm2V-1 s-1, respectively. A wafer-scale array of complementary inverters produced all by the direct printing method showed good performance with an average gain of 25 and with low variations among the inverters.

  4. Inspection strategy for LIGA microstructures using a programmable optical microscope.

    SciTech Connect

    Kurfess, Thomas R; Aigeldinger, Georg; Ceremuga, Joseph T.

    2004-07-01

    The LIGA process has the ability to fabricate very precise, high aspect ratio mesoscale structures with microscale features [l]. The process consists of multiple steps before a final part is produced. Materials native to the LIGA process include metals and photoresists. These structures are routinely measured for quality control and process improvement. However, metrology of LIGA structures is challenging because of their high aspect ratio and edge topography. For the scale of LIGA structures, a programmable optical microscope is well suited for lateral (XU) critical dimension measurements. Using grayscale gradient image processing with sub-pixel interpolation, edges are detected and measurements are performed. As with any measurement, understanding measurement uncertainty is necessary so that appropriate conclusions are drawn from the data. Therefore, the abilities of the inspection tool and the obstacles presented by the structures under inspection should be well understood so that precision may be quantified. This report presents an inspection method for LIGA microstructures including a comprehensive assessment of the uncertainty for each inspection scenario.

  5. Fabrication method for chip-scale-vacuum-packages based on a chip-to-wafer-process

    NASA Astrophysics Data System (ADS)

    Bauer, J.; Weiler, D.; Ruß, M.; Heß, J.; Yang, P.; Voß, J.; Arnold, N.,; Vogt, H.

    2010-10-01

    This paper introduces a simple vacuum packaging method which is based on a Chip-to-Wafer process. The MEMS-device is provided with an electroplated solder frame. A Si-lid with the same solder frame is mounted on each die of the wafer using a flip chip process. The same materials for lid and substrate are used in order to reduce the mechanical stress due to the same thermal coefficients of expansion. The resulting cavity between die and lid can be evacuated and hermetically sealed with an eutectic soldering process. The feasibility of the method is demonstrated with an infrared focal plane array (IR-FPA). In this case, the Si-lid acts as an optical window and contains an anti reflective layer for the 8-14 μm wavelength area on both sides. The long-term vacuum stability is supported by a getter film inside the package. This method simplifies the sawing process and has the additional cost benefit that it is possible to package only known good dies.

  6. Stationary Optical Concentrator Designs and Wafer Scale Monolithic Integration of Semiconductor Devices for Next Generation Photovoltaic Panels

    NASA Astrophysics Data System (ADS)

    Kim, Jung Min

    A major barrier in utilizing solar energy for large scale deployment is the cost of the photovoltaic (PV) systems. Several approaches have been used for the cost reduction such as by modifying PV system designs in addition to enhancing the efficiency of solar cells. Due to the high cost of materials, minimizing the use of solar cells such as in concentrator type systems is highly attractive for reducing the cost of the PV modules by focusing the incident light onto the PV cell. However concentrator PV systems (CPV) require constant tracking of the sun and hence are complex in design and expensive to operate, except in limited situations such as large scale PV power plants. It is desirable to design new concentrator type systems that do not require continuous tracking of the sun. These systems could ultimately reduce the PV system cost to a minimum while maximizing the power conversion efficiency. In this thesis we propose a simple design for a stationary concentrator photovoltaic (SCPV) system that could significantly reduce the cost of generating electricity using PV devices. Using optical ray tracing simulations, we have been able to design SCPV systems that could reduce the PV module cost by 2--10 times without compromising on the power conversion efficiency of the system. Another alternative approach for sustainable high efficiency PV system design is to develop low cost PV cells for terrestrial applications. To meet the demands of low cost and large scale production, larger and thinner (or flexible) substrates are required. We demonstrated the feasibility of fabricating monolithic interconnected PV devices at the wafer scale (2 inch wafers). In this study, GaSb PV cells grown on semi-insulating GaAs were used as the model material. Crucial device fabrication steps such as a selective etching process have been developed that is necessary for isolating individual devices on the wafer and interconnecting them with sub-micron scale accuracy. Selective etching of

  7. Wafer-Scale and Wrinkle-Free Epitaxial Growth of Single-Orientated Multilayer Hexagonal Boron Nitride on Sapphire.

    PubMed

    Jang, A-Rang; Hong, Seokmo; Hyun, Chohee; Yoon, Seong In; Kim, Gwangwoo; Jeong, Hu Young; Shin, Tae Joo; Park, Sung O; Wong, Kester; Kwak, Sang Kyu; Park, Noejung; Yu, Kwangnam; Choi, Eunjip; Mishchenko, Artem; Withers, Freddie; Novoselov, Kostya S; Lim, Hyunseob; Shin, Hyeon Suk

    2016-05-11

    Large-scale growth of high-quality hexagonal boron nitride has been a challenge in two-dimensional-material-based electronics. Herein, we present wafer-scale and wrinkle-free epitaxial growth of multilayer hexagonal boron nitride on a sapphire substrate by using high-temperature and low-pressure chemical vapor deposition. Microscopic and spectroscopic investigations and theoretical calculations reveal that synthesized hexagonal boron nitride has a single rotational orientation with AA' stacking order. A facile method for transferring hexagonal boron nitride onto other target substrates was developed, which provides the opportunity for using hexagonal boron nitride as a substrate in practical electronic circuits. A graphene field effect transistor fabricated on our hexagonal boron nitride sheets shows clear quantum oscillation and highly improved carrier mobility because the ultraflatness of the hexagonal boron nitride surface can reduce the substrate-induced degradation of the carrier mobility of two-dimensional materials. PMID:27120101

  8. Wafer scale fabrication of highly dense and uniform array of sub-5 nm nanogaps for surface enhanced Raman scatting substrates.

    PubMed

    Cai, Hongbing; Wu, YuKun; Dai, Yanmeng; Pan, Nan; Tian, Yangchao; Luo, Yi; Wang, Xiaoping

    2016-09-01

    Metallic nanogap is very important for a verity of applications in plasmonics. Although several fabrication techniques have been proposed in the last decades, it is still a challenge to produce uniform nanogaps with a few nanometers gap distance and high throughput. Here we present a simple, yet robust method based on the atomic layer deposition (ALD) and lift-off technique for patterning ultranarrow nanogaps array. The ability to accurately control the thickness of the ALD spacer layer enables us to precisely define the gap size, down to sub-5 nm scale. Moreover, this new method allows to fabricate uniform nanogaps array along different directions densely arranged on the wafer-scale substrate. It is demonstrated that the fabricated array can be used as an excellent substrate for surface enhanced Raman scatting (SERS) measurements of molecules, even on flexible substrates. This uniform nanogaps array would also find its applications for the trace detection and biosensors. PMID:27607684

  9. Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

    NASA Astrophysics Data System (ADS)

    Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

    2014-02-01

    Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

  10. Highly Transparent Wafer-Scale Synthesis of Crystalline WS2 Nanoparticle Thin Film for Photodetector and Humidity-Sensing Applications.

    PubMed

    Pawbake, Amit S; Waykar, Ravindra G; Late, Dattatray J; Jadkar, Sandesh R

    2016-02-10

    In the present investigation, we report a one-step synthesis method of wafer-scale highly crystalline tungsten disulfide (WS2) nanoparticle thin film by using a modified hot wire chemical vapor deposition (HW-CVD) technique. The average size of WS2 nanoparticle is found to be 25-40 nm over an entire 4 in. wafer of quartz substrate. The low-angle XRD data of WS2 nanoparticle shows the highly crystalline nature of sample along with orientation (002) direction. Furthermore, Raman spectroscopy shows two prominent phonon vibration modes of E(1)2g and A1g at ∼356 and ∼420 cm(-1), respectively, indicating high purity of material. The TEM analysis shows good crystalline quality of sample. The synthesized WS2 nanoparticle thin film based device shows good response to humidity and good photosensitivity along with good long-term stability of the device. It was found that the resistance of the films decreases with increasing relative humidity (RH). The maximum humidity sensitivity of 469% along with response time of ∼12 s and recovery time of ∼13 s were observed for the WS2 thin film humidity sensor device. In the case of photodetection, the response time of ∼51 s and recovery time of ∼88 s were observed with sensitivity ∼137% under white light illumination. Our results open up several avenues to grow other transition metal dichalcogenide nanoparticle thin film for large-area nanoelectronics as well as industrial applications. PMID:26771049

  11. Wafer-scale, conformal and direct growth of MoS2 thin films by atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Jang, Yujin; Yeo, Seungmin; Lee, Han-Bo-Ram; Kim, Hyungjun; Kim, Soo-Hyun

    2016-03-01

    Molybdenum disulfide (MoS2) thin films were grown directly on SiO2 covered wafers by atomic layer deposition (ALD) at the deposition temperatures ranging from 175 to 225 °C using molybdenum hexacarbonyl [Mo(CO)6] and H2S plasma as the precursor and reactant, respectively. Self-limited film growth on the thermally-grown SiO2 substrate was observed with both the precursor and reactant pulsing time. The growth rate was ∼0.05 nm/cycle and a short incubation cycle of around 13 was observed at a deposition temperature of 175 °C. The MoS2 films formed nanocrystalline microstructure with a hexagonal crystal system (2H-MoS2), which was confirmed by X-ray diffraction and transmission electron microscopy. Single crystal MoS2 nanosheets, ∼20 nm in size, were fabricated by controlling the number of ALD cycles. The ALD-MoS2 thin films exhibited good stoichiometry with negligible C impurities, approximately 0.1 at.% from Rutherford backscattering spectrometry (RBS). X-ray photoelectron spectroscopy confirmed the formation of chemical bonding from MoS2. The step coverage of ALD-MoS2 was approximately 75% at a 100 nm sized trench. Overall, the ALD-MoS2 process made uniform deposition possible on the wafer-scale (4 in. in diameter).

  12. Wafer-level-scale package of MEMS device by eutectic bonding method

    NASA Astrophysics Data System (ADS)

    Chen, Sihai; Ma, Hong; Chen, Mingxiang; Xiong, Tao; Liu, Sheng; Yi, Xinjian

    2003-12-01

    This paper reports the preliminary results for an on-going program in wafer-level MEMS package. In this particular paper, three closed-loop microheaters of 5μm, 7μm and 9μm width were designed. By reactive ion sputtering technique, two classes of samples were presented. The first one was first co-sputtered with nickel / chromium (Ni/Cr) alloy and then sputtered with gold(Au) metal as heating material; the second one was sputtered with Cr, tin (Sn) and Au respectively as heating material. The bonding of the former sample based on the Ni/Cr and Au heating material failed. The eutectic bonding experiment of the later sample based on the Cr, Sn and Au heating material by global heating method was completed in annealing oven at temperature of about 400 for 20 minutes. The SEM testing result showed the eutectic bonding of Au-Sn by global heating was successful. More results will be reported in future.

  13. Wafer-level scale package of MEMS device by eutectic bonding method

    NASA Astrophysics Data System (ADS)

    Chen, Sihai; Ma, Hong; Chen, Mingxiang; Xiong, Tao; Liu, Sheng; Yi, Xinjian

    2004-01-01

    This paper reports the preliminary results for an on-going program in wafer-level MEMS package. In this particular paper, three closed-loop microheaters of 5μm, 7μm and 9μm width were designed. By reactive ion sputtering technique, two classes of samples were presented. The first one was first co-sputtered with nickel / chromium (Ni/Cr) alloy and then sputtered with gold(Au) metal as heating material; the second one was sputtered with Cr, tin (Sn) and Au respectively as heating material. The bonding of the former sample based on the Ni/Cr and Au heating material failed. The eutectic bonding experiment of the later sample based on the Cr, Sn and Au heating material by global heating method was completed in annealing oven at temperature of about 400 deg. C. for 20 minutes. The SEM testing result showed the eutectic bonding of Au-Sn by global heating was successful. More results will be reported in future.

  14. 12-inch-wafer-scale CMOS active-pixel sensor for digital mammography

    NASA Astrophysics Data System (ADS)

    Heo, Sung Kyn; Kosonen, Jari; Hwang, Sung Ha; Kim, Tae Woo; Yun, Seungman; Kim, Ho Kyung

    2011-03-01

    This paper describes the development of an active-pixel sensor (APS) panel, which has a field-of-view of 23.1×17.1 cm and features 70-μm-sized pixels arranged in a 3300×2442 array format, for digital mammographic applications. The APS panel was realized on 12-inch wafers based on the standard complementary metal-oxide-semiconductor (CMOS) technology without physical tiling processes of several small-area sensor arrays. Electrical performance of the developed panel is described in terms of dark current, full-well capacity and leakage current map. For mammographic imaging, the optimized CsI:Tl scintillator is experimentally determined by being combined with the developed panel and analyzing im aging characteristics, such as modulation-transfer function, noise-power spectrum, detective quantum efficiency, image l ag, and contrast-detail analysis by using the CDMAM 3.4 phantom. With these results, we suggest that the developed CMOS-based detector can be used for conventional and advanced digital mammographic applications.

  15. Wafer-Scale Nanopillars Derived from Block Copolymer Lithography for Surface-Enhanced Raman Spectroscopy.

    PubMed

    Li, Tao; Wu, Kaiyu; Rindzevicius, Tomas; Wang, Zhongli; Schulte, Lars; Schmidt, Michael S; Boisen, Anja; Ndoni, Sokol

    2016-06-22

    We report a novel nanofabrication process via block copolymer lithography using solvent vapor annealing. The nanolithography process is facile and scalable, enabling fabrication of highly ordered periodic patterns over entire wafers as substrates for surface-enhanced Raman spectroscopy (SERS). Direct silicon etching with high aspect ratio templated by the block copolymer mask is realized without any intermediate layer or external precursors. Uniquely, an atomic layer deposition (ALD)-assisted method is introduced to allow reversing of the morphology relative to the initial pattern. As a result, highly ordered silicon nanopillar arrays are fabricated with controlled aspect ratios. After metallization, the resulting nanopillar arrays are suitable for SERS applications. These structures readily exhibit an average SERS enhancement factor of above 10(8), SERS uniformities of 8.5% relative standard deviation across 4 cm, and 6.5% relative standard deviation over 5 × 5 mm(2) surface area, as well as a very low SERS background. The as-prepared SERS substrate, with a good enhancement and large-area uniformity, is promising for practical SERS sensing applications. PMID:27254397

  16. Modeling electrodeposition for LIGA microdevice fabrication

    SciTech Connect

    Griffiths, S.K.; Nilson, R.H.; Bradshaw, R.W.

    1998-02-01

    To better understand and to help optimize the electroforming portion of the LIGA process, we have developed one and two-dimensional numerical models describing electrode-position of metal into high aspect-ratio molds. The one-dimensional model addresses dissociation, diffusion, electromigration, and deposition of multiple ion species. The two-dimensional model is limited to a single species, but includes transport induced by forced flow of electrolyte outside the mold and by buoyancy associated with metal ion depletion within the mold. To guide model development and to validate these models, we have also conducted a series of laboratory experiments using a sulfamate bath to deposit nickel in cylindrical molds having aspect ratios up to twenty-five. The experimental results indicate that current densities well in excess of the diffusion-limited currents may still yield metal deposits of acceptable morphology. However, the numerical models demonstrate that such large ion fluxes cannot be sustained by convection within the mold resulting from flow across the mold top. Instead, calculations suggest that the observed enhancement of transport probably results from natural convection within the molds, and that buoyancy-driven flows may be critical to metal ion transport even in micron-scale features having very large aspect ratios. Taking advantage of this enhanced ion transport may allow order-of-magnitude reductions in electroforming times for LIGA microdevice fabrication. 42 refs., 14 figs., 1 tab.

  17. Wafer-scale single-domain-like graphene by defect-selective atomic layer deposition of hexagonal ZnO

    NASA Astrophysics Data System (ADS)

    Park, Kyung Sun; Kim, Sejoon; Kim, Hongbum; Kwon, Deokhyeon; Koo Lee, Yong-Eun; Min, Sung-Wook; Im, Seongil; Choi, Hyoung Joon; Lim, Seulky; Shin, Hyunjung; Koo, Sang Man; Sung, Myung Mo

    2015-10-01

    Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity.Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also

  18. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

    NASA Astrophysics Data System (ADS)

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-02-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

  19. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

    PubMed Central

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-01-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

  20. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors.

    PubMed

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-01-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8" glass wafer. PMID:26861833

  1. Wafer-scale single-domain-like graphene by defect-selective atomic layer deposition of hexagonal ZnO.

    PubMed

    Park, Kyung Sun; Kim, Sejoon; Kim, Hongbum; Kwon, Deokhyeon; Lee, Yong-Eun Koo; Min, Sung-Wook; Im, Seongil; Choi, Hyoung Joon; Lim, Seulky; Shin, Hyunjung; Koo, Sang Man; Sung, Myung Mo

    2015-11-14

    Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity. PMID:26452020

  2. Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics.

    PubMed

    Heo, Jinseong; Byun, Kyung-Eun; Lee, Jaeho; Chung, Hyun-Jong; Jeon, Sanghun; Park, Seongjun; Hwang, Sungwoo

    2013-01-01

    Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V. PMID:24256403

  3. Fabrication of miniaturized electrostatic deflectors using LIGA

    SciTech Connect

    Jackson, K.H.; Khan-Malek, C.; Muray, L.P.

    1997-04-01

    Miniaturized electron beam columns ({open_quotes}microcolumns{close_quotes}) have been demonstrated to be suitable candidates for scanning electron microscopy (SEM), e-beam lithography and other high resolution, low voltage applications. In the present technology, microcolumns consist of {open_quotes}selectively scaled{close_quotes} micro-sized lenses and apertures, fabricated from silicon membranes with e-beam lithography, reactive ion beam etching and other semiconductor thin-film techniques. These miniaturized electron-optical elements provide significant advantages over conventional optics in performance and ease of fabrication. Since lens aberrations scale roughly with size, it is possible to fabricate simple microcolumns with extremely high brightness sources and electrostatic objective lenses, with resolution and beam current comparable to conventional e-beam columns. Moreover since microcolumns typically operate at low voltages (1 KeV), the proximity effects encountered in e-beam lithography become negligible. For high throughput applications, batch fabrication methods may be used to build large parallel arrays of microcolumns. To date, the best reported performance with a 1 keV cold field emission cathode, is 30 nm resolution at a working distance of 2mm in a 3.5mm column. Fabrication of the microcolumn deflector and stigmator, however, have remained beyond the capabilities of conventional machining operations and semiconductor processing technology. This work examines the LIGA process as a superior alternative to fabrication of the deflectors, especially in terms of degree of miniaturization, dimensional control, placement accuracy, run-out, facet smoothness and choice of suitable materials. LIGA is a combination of deep X-ray lithography, electroplating, and injection molding processes which allow the fabrication of microstructures.

  4. Wafer scale fabrication of carbon nanotube thin film transistors with high yield

    NASA Astrophysics Data System (ADS)

    Tian, Boyuan; Liang, Xuelei; Yan, Qiuping; Zhang, Han; Xia, Jiye; Dong, Guodong; Peng, Lianmao; Xie, Sishen

    2016-07-01

    Carbon nanotube thin film transistors (CNT-TFTs) are promising candidates for future high performance and low cost macro-electronics. However, most of the reported CNT-TFTs are fabricated in small quantities on a relatively small size substrate. The yield of large scale fabrication and the performance uniformity of devices on large size substrates should be improved before the CNT-TFTs reach real products. In this paper, 25 200 devices, with various geometries (channel width and channel length), were fabricated on 4-in. size ridged and flexible substrates. Almost 100% device yield were obtained on a rigid substrate with high out-put current (>8 μA/μm), high on/off current ratio (>105), and high mobility (>30 cm2/V.s). More importantly, uniform performance in 4-in. area was achieved, and the fabrication process can be scaled up. The results give us more confidence for the real application of the CNT-TFT technology in the near future.

  5. Integration of hexagonal boron nitride with quasi-freestanding epitaxial graphene: toward wafer-scale, high-performance devices.

    PubMed

    Bresnehan, Michael S; Hollander, Matthew J; Wetherington, Maxwell; LaBella, Michael; Trumbull, Kathleen A; Cavalero, Randal; Snyder, David W; Robinson, Joshua A

    2012-06-26

    Hexagonal boron nitride (h-BN) is a promising dielectric material for graphene-based electronic devices. Here we investigate the potential of h-BN gate dielectrics, grown by chemical vapor deposition (CVD), for integration with quasi-freestanding epitaxial graphene (QFEG). We discuss the large scale growth of h-BN on copper foil via a catalytic thermal CVD process and the subsequent transfer of h-BN to a 75 mm QFEG wafer. X-ray photoelectron spectroscopy (XPS) measurements confirm the absence of h-BN/graphitic domains and indicate that the film is chemically stable throughout the transfer process, while Raman spectroscopy indicates a 42% relaxation of compressive stress following removal of the copper substrate and subsequent transfer of h-BN to QFEG. Despite stress-induced wrinkling observed in the films, Hall effect measurements show little degradation (<10%) in carrier mobility for h-BN coated QFEG. Temperature dependent Hall measurements indicate little contribution from remote surface optical phonon scattering and suggest that, compared to HfO(2) based dielectrics, h-BN can be an excellent material for preserving electrical transport properties. Graphene transistors utilizing h-BN gates exhibit peak intrinsic cutoff frequencies >30 GHz (2.4× that of HfO(2)-based devices). PMID:22545808

  6. Wafer-scale fabrication of self-actuated piezoelectric nanoelectromechanical resonators based on lead zirconate titanate (PZT)

    NASA Astrophysics Data System (ADS)

    Dezest, D.; Thomas, O.; Mathieu, F.; Mazenq, L.; Soyer, C.; Costecalde, J.; Remiens, D.; Deü, J. F.; Nicu, L.

    2015-03-01

    In this paper we report an unprecedented level of integration of self-actuated nanoelectromechanical system (NEMS) resonators based on a 150 nm thick lead zirconate titanate (PZT) thin film at the wafer-scale. A top-down approach combining ultraviolet (UV) lithography with other standard planar processing technologies allows us to achieve high-throughput manufacturing. Multilayer stack cantilevers with different geometries have been implemented with measured fundamental resonant frequencies in the megahertz range and Q-factor values ranging from ~130 in air up to ~900 in a vacuum at room temperature. A refined finite element model taking into account the exact configuration of the piezoelectric stack is proposed and demonstrates the importance of considering the dependence of the beam’s cross-section upon the axial coordinate. We extensively investigate both experimentally and theoretically the transduction efficiency of the implemented piezoelectric layer and report for the first time at this integration level a piezoelectric constant of {{d}31}=15  fm V-1. Finally, we discuss the current limitations to achieve piezoelectric detection.

  7. Facile fabrication of wafer-scale MoS2 neat films with enhanced third-order nonlinear optical performance.

    PubMed

    Zhang, Xiaoyan; Zhang, Saifeng; Chang, Chunxia; Feng, Yanyan; Li, Yuanxin; Dong, Ningning; Wang, Kangpeng; Zhang, Long; Blau, Werner J; Wang, Jun

    2015-02-21

    Wafer-scale MoS2 neat films with controllable thicknesses were successfully fabricated by vacuum filtering liquid-exfoliated MoS2 dispersions. The obtained MoS2 filtered thin films were systematically characterized by UV-Vis spectroscopy, Fourier transform infrared spectroscopy (FTIR), Raman spectroscopy, atomic force microscopy (AFM) and scanning electron microscopy (SEM). It was found that the fabricated scalable MoS2 films have a smooth surface and high optical homogeneity verified by AFM and a collimated 532 nm beam, respectively. We investigated the ultrafast nonlinear optical (NLO) properties of the filtered films by an open aperture Z-scan method using 515 and 1030 nm femtosecond laser pulses. Saturable absorption was observed at both 515 and 1030 nm with the figure of merit (FOM) values as ∼3.3 × 10(-12) esu cm and ∼3.4 × 10(-14) esu cm, respectively. The observation of ultrafast NLO performance of the MoS2 filtered films indicates that vacuum filtration is a feasible method for the fabrication of optical thin films, which can be expanded to fabricate other two-dimensional films from the corresponding dispersions. This easy film fabrication technology will greatly enlarge the application of graphene analogues including graphene in photonic devices, especially of MoS2 as a saturable absorber. PMID:25597818

  8. Wafer-scale fabrication of nanofluidic arrays and networks using nanoimprint lithography and lithographically patterned nanowire electrodeposition gold nanowire masters.

    PubMed

    Halpern, Aaron R; Donavan, Keith C; Penner, Reginald M; Corn, Robert M

    2012-06-01

    Wafer scale (cm(2)) arrays and networks of nanochannels were created in polydimethylsiloxane (PDMS) from a surface pattern of electrodeposited gold nanowires in a master-replica process and characterized with scanning electron microscopy (SEM), atomic force microscopy (AFM), and fluorescence imaging measurements. Patterns of gold nanowires with cross-sectional dimensions as small as 50 nm in height and 100 nm in width were prepared on silica substrates using the process of lithographically patterned nanowire electrodeposition (LPNE). These nanowire patterns were then employed as masters for the fabrication of inverse replica nanochannels in a special formulation of PDMS. SEM and AFM measurements verified a linear correlation between the widths and heights of the nanowires and nanochannels over a range of 50 to 500 nm. The PDMS replica was then oxygen plasma-bonded to a glass substrate in order to create a linear array of nanofluidic channels (up to 1 mm in length) filled with solutions of either fluorescent dye or 20 nm diameter fluorescent polymer nanoparticles. Nanochannel continuity and a 99% fill success rate was determined from the fluorescence imaging measurements, and the electrophoretic injection of both dye and nanoparticles in the nanochannel arrays was also demonstrated. Employing a double LPNE fabrication method, this master-replica process was also used to create a large two-dimensional network of crossed nanofluidic channels. PMID:22533970

  9. Three-dimensional LIGA structures for use in tagging

    NASA Astrophysics Data System (ADS)

    Cox, Adam G.; Garcia, Ephrahim

    1999-07-01

    Nature provides many examples of organisms capable of attaching themselves to other organisms. Seeds and some parasitic insects, for example, have attachment mechanisms that allow them to remain undetected for long periods of time. Such properties may be useful in military and law enforcement tagging situations, where one desires the discrete placement of an active or passive device on an unwitting host. This paper describes the development of 3D micro-scale burrs, that can readily attach to clothing, and are capable of opening the door to new methods of tracking. With the development of bulk micro-machining techniques such as LIGA and MEMS the ability to develop such a carrier taggent has arisen. 3D micro-scale burrs, made of electrodeposited nickel, have been developed using the LIGA process and have been tested for use as carriers for micro- sensors and emitters both active and passive.

  10. Wafer-scale monodomain films of spontaneously aligned single-walled carbon nanotubes.

    PubMed

    He, Xiaowei; Gao, Weilu; Xie, Lijuan; Li, Bo; Zhang, Qi; Lei, Sidong; Robinson, John M; Hároz, Erik H; Doorn, Stephen K; Wang, Weipeng; Vajtai, Robert; Ajayan, Pulickel M; Adams, W Wade; Hauge, Robert H; Kono, Junichiro

    2016-07-01

    The one-dimensional character of electrons, phonons and excitons in individual single-walled carbon nanotubes leads to extremely anisotropic electronic, thermal and optical properties. However, despite significant efforts to develop ways to produce large-scale architectures of aligned nanotubes, macroscopic manifestations of such properties remain limited. Here, we show that large (>cm(2)) monodomain films of aligned single-walled carbon nanotubes can be prepared using slow vacuum filtration. The produced films are globally aligned within ±1.5° (a nematic order parameter of ∼1) and are highly packed, containing 1 × 10(6) nanotubes in a cross-sectional area of 1 μm(2). The method works for nanotubes synthesized by various methods, and film thickness is controllable from a few nanometres to ∼100 nm. We use the approach to create ideal polarizers in the terahertz frequency range and, by combining the method with recently developed sorting techniques, highly aligned and chirality-enriched nanotube thin-film devices. Semiconductor-enriched devices exhibit polarized light emission and polarization-dependent photocurrent, as well as anisotropic conductivities and transistor action with high on/off ratios. PMID:27043199

  11. Wafer-scale monodomain films of spontaneously aligned single-walled carbon nanotubes

    NASA Astrophysics Data System (ADS)

    He, Xiaowei; Gao, Weilu; Xie, Lijuan; Li, Bo; Zhang, Qi; Lei, Sidong; Robinson, John M.; Hároz, Erik H.; Doorn, Stephen K.; Wang, Weipeng; Vajtai, Robert; Ajayan, Pulickel M.; Adams, W. Wade; Hauge, Robert H.; Kono, Junichiro

    2016-07-01

    The one-dimensional character of electrons, phonons and excitons in individual single-walled carbon nanotubes leads to extremely anisotropic electronic, thermal and optical properties. However, despite significant efforts to develop ways to produce large-scale architectures of aligned nanotubes, macroscopic manifestations of such properties remain limited. Here, we show that large (>cm2) monodomain films of aligned single-walled carbon nanotubes can be prepared using slow vacuum filtration. The produced films are globally aligned within ±1.5° (a nematic order parameter of ∼1) and are highly packed, containing 1 × 106 nanotubes in a cross-sectional area of 1 μm2. The method works for nanotubes synthesized by various methods, and film thickness is controllable from a few nanometres to ∼100 nm. We use the approach to create ideal polarizers in the terahertz frequency range and, by combining the method with recently developed sorting techniques, highly aligned and chirality-enriched nanotube thin-film devices. Semiconductor-enriched devices exhibit polarized light emission and polarization-dependent photocurrent, as well as anisotropic conductivities and transistor action with high on/off ratios.

  12. 200 mm wafer-scale substrate transfer of 0.13 μm Cu/low-k (Black Diamond™) dual-damascene interconnection to glass substrates

    NASA Astrophysics Data System (ADS)

    Teh, W. H.; Kumar, R.; Kwong, D. L.

    2005-07-01

    We report a low-temperature (350 °C) pulsed-voltage anodic bonding followed by grind/etch-back method for 200 mm wafer-scale substrate transfer of 0.13μmCu/low-k (Black Diamond™) dual-damascene interconnection to glass substrates. Standard back-end-of-line (BEOL) 3kÅSiN/3kÅ undoped Si glass passivating films were used as buffer layers between donor wafer and glass wafer to facilitate the bonding. We demonstrate removal of the silicon bulk layer to leave behind a transparent (˜1.25μm thick) 0.13μm BEOL circuit on a 1-mm-thick glass wafer. The quality of the mechanical and electrical integrity of the deep submicron BEOL circuit is confirmed by focused ion beam-scanning electron microscopy microscopy and I-V characterization on via chain test structures. This technique has potential applications for bioelectronics and optoelectronics integration schemes.

  13. Wafer-scale synthesis of thickness-controllable MoS2 films via solution-processing using a dimethylformamide/n-butylamine/2-aminoethanol solvent system

    NASA Astrophysics Data System (ADS)

    Yang, Jaehyun; Gu, Yeahyun; Lee, Eunha; Lee, Hyangsook; Park, Sang Han; Cho, Mann-Ho; Kim, Yong Ho; Kim, Yong-Hoon; Kim, Hyoungsub

    2015-05-01

    The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates.The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the

  14. Slip, Crystal Orientation, and Damage Evolution During Thermal Cycling in High-Strain Wafer-Level Chip-Scale Packages

    NASA Astrophysics Data System (ADS)

    Zhou, Bite; Zhou, Quan; Bieler, Thomas R.; Lee, Tae-kyu

    2015-03-01

    Wafer-level chip-scale package samples with pre-cross-sectioned edge rows were thermally cycled to study microstructure evolution and damage development. Electron backscattered diffraction (EBSD) and high-energy x-ray diffraction were used to obtain Sn grain orientations and the average coefficient of thermal expansion normal to the board in every joint of the package for samples in the as-fabricated and thermally cycled conditions. The results indicated a near-random distribution of joint orientation. Optical, scanning electron microscopy, and EBSD methods were used to characterize microstructure changes in pre-cross-sectioned samples due to thermal cycling. Slip trace analysis and Orientation Imaging Microscopy™ (OIM) show that slip systems with high Schmid factors (estimated global shear stress based on the package neutral point) are responsible for the observed microstructure evolution during thermal cycling, which provides information about slip systems that are more easily activated. Two joints were analyzed in detail to evaluate slip activity at different stages of their thermal history. The first case showed that a solidification twin grain boundary misorientation deviated from the twin relationship due to slip activity during thermal cycling, which can influence damage development and the path of crack propagation. The second case showed a new grain orientation developing due to gradual lattice rotation about the Sn [110] axis by a continuous recrystallization mechanism. This rotation was correlated with the operation of slip system . Small tin whiskers emerged from the initially polished chip interface and grew with increasing thermal cycles until a crack developed in the solder that relieved the stress. As the local stresses are not known experimentally, this analysis provides observations that can be compared with a crystal plasticity model simulation.

  15. Miniature Inchworm Actuators Fabricated by Use of LIGA

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok

    2003-01-01

    Miniature inchworm actuators that would have relatively simple designs have been proposed for applications in which there are requirements for displacements of the order of microns or tens of microns and for the ability to hold their positions when electric power is not applied. The proposed actuators would be members of the class of microelectromechanical systems (MEMS), but would be designed and fabricated following an approach that is somewhat unusual for MEMS. Like other MEMS actuators, the proposed inchworm actuators could utilize thermoplastic, bimetallic, shape-memory-alloy, or piezoelectric actuation principles. The figure depicts a piezoelectric inchworm actuator according to the proposal. As in other inchworm actuators, linear motion of an extensible member would be achieved by lengthening and shortening the extensible member in synchronism with alternately clamping and releasing one and then the other end of the member. In this case, the moving member would be the middle one; the member would be piezoelectric and would be shortened by applying a voltage to it. The two outer members would also be piezoelectric; the release of the clamps on the upper or lower end would be achieved by applying a voltage to the electrodes on the upper or lower ends, respectively, of these members. Usually, MEMS actuators cannot be fabricated directly on the side walls of silicon wafers, yet the geometry of this actuator necessitates such fabrication. The solution, according to the proposal, would be to use the microfabrication technique known by the German acronym LIGA - "lithographie, galvanoformung, abformung," which means lithography, electroforming, molding. LIGA involves x-ray lithography of a polymer film followed by selective removal of material to form a three-dimensional pattern from which a mold is made. Among the advantages of LIGA for this purpose are that it is applicable to a broad range of materials, can be used to implement a variety of designs, including

  16. MUSE - a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer-scale integration. Technical report

    SciTech Connect

    Rader, C.M.; Allen, D.L.; gLASCO , D.B.; Woodward, C.E.

    1990-05-18

    This report describes an architecture for a highly parallel system of computational processors specialized for real-time adaptive antenna nulling computations with many degrees of freedom, which we call MUSE (Matrix Update Systolic Experiment), and a specific realization of MUSE for 64 degrees of freedom. Each processor uses the CORDIC algorithm and has been designed as a single integrated circuit. Ninety-six such processors working together can update the 64-element nulling weights based on 300 new observations in only 6.7 milliseconds. This is equivalent to 2.88 Giga-ops for a conventional processor. The computations are accurate enough to support 50 decibel of signal-to-noise improvement in a sidelobe canceller. The connectivity between processors is quite simple and permits MUSE to be realized on a single large wafer, using restructurable VLSI (Very Large Scale Integration). The complete design of such a wafer is described.

  17. Machining lead wafers

    SciTech Connect

    Schamaun, R.T.

    1987-09-01

    Recently, MEC-6 machined some 4-inch-diameter lead wafers to precision tolerances. The tolerance on the wafer thickness was +-0.000080 inch. A diamond tool was used to machine the wafers on a Moore No. 3 lathe. This report discusses the methods used to machine the wafers, the fixtures used to hold the wafers, and the inspection methods and results.

  18. Imaging ATUM ultrathin section libraries with WaferMapper: a multi-scale approach to EM reconstruction of neural circuits

    PubMed Central

    Hayworth, Kenneth J.; Morgan, Josh L.; Schalek, Richard; Berger, Daniel R.; Hildebrand, David G. C.; Lichtman, Jeff W.

    2014-01-01

    The automated tape-collecting ultramicrotome (ATUM) makes it possible to collect large numbers of ultrathin sections quickly—the equivalent of a petabyte of high resolution images each day. However, even high throughput image acquisition strategies generate images far more slowly (at present ~1 terabyte per day). We therefore developed WaferMapper, a software package that takes a multi-resolution approach to mapping and imaging select regions within a library of ultrathin sections. This automated method selects and directs imaging of corresponding regions within each section of an ultrathin section library (UTSL) that may contain many thousands of sections. Using WaferMapper, it is possible to map thousands of tissue sections at low resolution and target multiple points of interest for high resolution imaging based on anatomical landmarks. The program can also be used to expand previously imaged regions, acquire data under different imaging conditions, or re-image after additional tissue treatments. PMID:25018701

  19. Optimization and scale-down of wafer-based resist strip and rinse processes for photomask production

    NASA Astrophysics Data System (ADS)

    Aggus, Brant L.; Weaver, Gene

    2002-03-01

    Retrofitting of wafer processing equipment is a common scenario in the photomask industry, as most available tools are built to accommodate the high throughput and substrate size of wafers. The acid process tanks in use at most mask shops are built to suit a single rack of 25 8 inch wafers, each coated with roughly two microns of photoresist. Conversely, a typical photomask shop sends one to two masks at a time through the resist strip line, each coated with 4500 angstroms of resist. The amount of unused volume of active chemical within an 8 inch X 8.5 inch X 10 inch acid tank when it is dumped is enough to warrant a hardware change. Experimentation has shown that it is possible to decrease Piranha usage by 43 percent by optimizing tank size for photomasks. The same logic applies to quick dump rinsers (QDRs). Additionally, water is wasted with 'spray down' processes, whereby masks are sprayed via perforated bars or nozzles. Because a < 0.5 μm viscous sublayer can not be practically achieved through spraying the mask, better cleaning performance is obtained with a bottom-filled weiring process. This is demonstrated through experimental results and theoretical mass transfer models.

  20. Laser wafering for silicon solar.

    SciTech Connect

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  1. Wafer-scale pixelated scintillator and specially designed data acquisition system for fiber optic taper array-coupled digital x-ray detector

    NASA Astrophysics Data System (ADS)

    Zhao, Zhigang; Li, Ji; Lei, Yaohu; Wang, Ru; Ren, Jianping; Qiao, Jian; Niu, Hanben

    2015-09-01

    A digital x-ray detector scheme based on a pixelated scintillator coupled with a fiber optic (FOT) array is suitable for many high-resolution x-ray imaging applications. However, certain challenges need to be addressed for fabrication of wafer-scale uniform pixelated x-ray scintillators. In addition, difficulties associated with implementation of the data acquisition system for acquiring output image data from the multiple image sensors used in the detector also need to be addressed. In this paper, a 2×2 FOT array-coupled digital x-ray detector scheme using a 5-in. pixelated scintillator is proposed. A novel fabrication setup along with the corresponding processes for fabricating the wafer-scale pixelated scintillator and implementation of a specially designed embedded data acquisition system based on a single embedded micro-processer (ARM) and four field-programmable gate array (FPGA) chips are discussed in detail. Preliminary experiments demonstrate that this pixelated scintillator-based digital x-ray detector scheme with an active imaging area of about 100 mm×100 mm shows considerable potential for use in high-resolution x-ray imaging.

  2. Large-area, wafer-scale epitaxial growth of germanium on silicon and integration of high-performance transistors

    NASA Astrophysics Data System (ADS)

    Ghosh, Swapnadip

    Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the ˜105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress

  3. Wafer-scale double-layer stacked Au/Al2O3@Au nanosphere structure with tunable nanospacing for surface-enhanced Raman scattering.

    PubMed

    Hu, Zhaosheng; Liu, Zhe; Li, Lin; Quan, Baogang; Li, Yunlong; Li, Junjie; Gu, Changzhi

    2014-10-15

    Fabricating perfect plasmonic nanostructures has been a major challenge in surface enhanced Raman scattering (SERS) research. Here, a double-layer stacked Au/Al2O3@Au nanosphere structures is designed on the silicon wafer to bring high density, high intensity "hot spots" effect. A simply reproducible high-throughput approach is shown to fabricate feasibly this plasmonic nanostructures by rapid thermal annealing (RTA) and atomic layer deposition process (ALD). The double-layer stacked Au nanospheres construct a three-dimensional plasmonic nanostructure with tunable nanospacing and high-density nanojunctions between adjacent Au nanospheres by ultrathin Al2O3 isolation layer, producing highly strong plasmonic coupling so that the electromagnetic near-field is greatly enhanced to obtain a highly uniform increase of SERS with an enhancement factor (EF) of over 10(7). Both heterogeneous nanosphere group (Au/Al2O@Ag) and pyramid-shaped arrays structure substrate can help to increase the SERS signals further, with a EF of nearly 10(9). These wafer-scale, high density homo/hetero-metal-nanosphere arrays with tunable nanojunction between adjacent shell-isolated nanospheres have significant implications for ultrasensitive Raman detection, molecular electronics, and nanophotonics. PMID:24995658

  4. Wafer-scale epitaxial lift-off of optoelectronic grade GaN from a GaN substrate using a sacrificial ZnO interlayer

    NASA Astrophysics Data System (ADS)

    Rajan, Akhil; Rogers, David J.; Ton-That, Cuong; Zhu, Liangchen; Phillips, Matthew R.; Sundaram, Suresh; Gautier, Simon; Moudakir, Tarik; El-Gmili, Youssef; Ougazzaden, Abdallah; Sandana, Vinod E.; Teherani, Ferechteh H.; Bove, Philippe; Prior, Kevin A.; Djebbour, Zakaria; McClintock, Ryan; Razeghi, Manijeh

    2016-08-01

    Full 2 inch GaN epilayers were lifted off GaN and c-sapphire substrates by preferential chemical dissolution of sacrificial ZnO underlayers. Modification of the standard epitaxial lift-off (ELO) process by supporting the wax host with a glass substrate proved key in enabling full wafer scale-up. Scanning electron microscopy and x-ray diffraction confirmed that intact epitaxial GaN had been transferred to the glass host. Depth-resolved cathodoluminescence (CL) analysis of the bottom surface of the lifted-off GaN layer revealed strong near-band-edge (3.33 eV) emission indicating a superior optical quality for the GaN which was lifted off the GaN substrate. This modified ELO approach demonstrates that previous theories proposing that wax host curling was necessary to keep the ELO etch channel open do not apply to the GaN/ZnO system. The unprecedented full wafer transfer of epitaxial GaN to an alternative support by ELO offers the perspective of accelerating industrial adoption of the expensive GaN substrate through cost-reducing recycling.

  5. Understanding and Tailoring the Mechanical Properties of LIGA Fabricated Materials

    SciTech Connect

    Buchheit, T.E.; Christenson, T.R.; Lavan, D.A.; Schmale, D.T.

    1999-01-25

    LIGA fabricated materials and components exhibit several processing issues affecting their metallurgical and mechanical properties, potentially limiting their usefulness for MEMS applications. For example, LIGA processing by metal electrodeposition is very sensitive to deposition conditions which causes significant processing lot variations of mechanical and metallurgical properties. Furthermore, the process produces a material with a highly textured lenticular rnicrostructural morphology suggesting an anisotropic material response. Understanding and controlling out-of-plane anisotropy is desirable for LIGA components designed for out-of-plane flexures. Previous work by the current authors focused on results from a miniature servo-hydraulic mechanical test frame constructed for characterizing LIGA materials. Those results demonstrated microstructural and mechanical properties dependencies with plating bath current density in LIGA fabricated nickel (LIGA Ni). This presentation builds on that work and fosters a methodology for controlling the properties of LIGA fabricated materials through processing. New results include measurement of mechanical properties of LIGA fabricated copper (LIGA Cu), out-of-plane and localized mechanical property measurements using compression testing and nanoindentation of LIGA Ni and LIGA Cu.

  6. Fast and robust hydrogen sensors based on discontinuous palladium films on polyimide, fabricated on a wafer scale.

    PubMed

    Kiefer, T; Villanueva, L G; Fargier, F; Favier, F; Brugger, J

    2010-12-17

    Fast hydrogen sensors based on discontinuous palladium (Pd) films on supporting polyimide layers, fabricated by a cost-efficient and full-wafer compatible process, are presented. The films, deposited by electron-beam evaporation with a nominal thickness of 1.5 nm, consist of isolated Pd islands that are separated by nanoscopic gaps. On hydrogenation, the volume expansion of Pd brings initially separated islands into contact which leads to the creation of new electrical pathways through the film. The supporting polyimide layer provides both sufficient elasticity for the Pd nanoclusters to expand on hydrogenation and a sufficiently high surface energy for good adhesion of both film and contacting electrodes. The novel order of the fabrication processes involves a dicing step prior to the Pd deposition and stencil lithography for the patterning of microelectrodes. This allows us to preserve the as-deposited film properties. The devices work at room temperature, show response times of a few seconds and have a low power consumption of some tens of nW. PMID:21098952

  7. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  8. Cyanoacrylate bonding of thick resists for LIGA

    NASA Astrophysics Data System (ADS)

    Rogers, James G., IV; Marques, Christophe; Kelly, Kevin W.; Sangishetty, Venkat; Khan Malek, Chantal G.

    1996-09-01

    The MicroSystems Engineering Team ((mu) SET) at Louisiana State University, in close collaboration with the Center for Advanced Microstructures and Devices, has successfully completed the lithography and electroplating steps of the LIGA process sequence using cyanoacrylate to bond a PMMA resist layer to a nickel surface. Nickel microstructures 300 micrometers in height have been electroplated. Tests were performed which indicate that the bond between cyanoacrylate and nickel is much stronger than the bond between PMMA and nickel.

  9. LIGA microsystems aging : evaluation and mitigation.

    SciTech Connect

    Cadden, Charles H.; Yang, Nancy Y. C.; San Marchi, Christopher W.

    2003-12-01

    The deployment of LIGA structures in DP applications requires a thorough understanding of potential long term physical and chemical changes that may occur during service. While these components are generally fabricated from simple metallic systems such as copper, nickel and nickel alloys, the electroplating process used to form them creates microstructural features which differ from those found in conventional (e.g. ingot metallurgy) processing of such materials. Physical changes in non-equilibrium microstructures may occur due to long term exposure to temperatures sufficient to permit atomic and vacancy mobility. Chemical changes, particularly at the surfaces of LIGA parts, may occur in the presence of gaseous chemical species (e.g. water vapor, HE off-gassing compounds) and contact with other metallic structures. In this study, we have characterized the baseline microstructure of several nickel-based materials that are used to fabricate LIGA structures. Solute content and distribution was found to have a major effect on the electroplated microstructures. Microstructural features were correlated to measurements of hardness and tensile strength. Dormancy testing was conducted on one of the baseline compositions, nickel-sulfamate. Groups of specimens were exposed to controlled thermal cycles; subsequent examinations compared properties of 'aged' specimens to the baseline conditions. Results of our testing indicate that exposure to ambient temperatures (-54 C to 71 C) do not result in microstructural changes that might be expected to significantly effect mechanical performance. Additionally, no localized changes in surface appearance were found as a result of contact between electroplated parts.

  10. High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth.

    PubMed

    Miao, Xin; Chabak, Kelson; Zhang, Chen; Mohseni, Parsian K; Walker, Dennis; Li, Xiuling

    2015-05-13

    Wafer-scale defect-free planar III-V nanowire (NW) arrays with ∼100% yield and precisely defined positions are realized via a patterned vapor-liquid-solid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 10(4), 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 × 1.5 cm(2) chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics. PMID:25494481

  11. Method to reduce particles and defects on unprocessed wafers caused by clusterization and cross contamination from processed wafers

    NASA Astrophysics Data System (ADS)

    Sant, Sanket

    2012-10-01

    One of the leading problems in the semiconductor industry with device scaling is defects and particles. Of this the most important ones are particles that can clusterize (condensate) with exposure to atmosphere. These clusters can be formed by residual halides or halide structures on the wafer surface reacting with surface moisture which is unavoidable. Such clusters can prove detrimental to the processed wafer, but more interestingly can migrate inside the FOUP onto unetched wafers. This migration of clusters can cause micro masking and other defects when these wafers are processed. This reduces the wafer yield and is challenging to resolve as we move towards smaller nodes. In this work, different methods of eliminating cross condensation defects and avoiding cluster formation on processed wafers are discussed. UV, Ozone and heat are the primary candidates explored and the mechanism behind each method is explored and optimized. Impact of each mechanism on wafer yield, part corrosion in a reactor platform and wafer throughput has been studied.

  12. Wafer-scale monolayer MoS2 grown by chemical vapor deposition using a reaction of MoO3 and H2S.

    PubMed

    Kim, Youngchan; Bark, Hunyoung; Ryu, Gyeong Hee; Lee, Zonghoon; Lee, Changgu

    2016-05-11

    Monolayer MoS2 nanosheets are potentially useful in optoelectronics, photoelectronics, and nanoelectronics due to their flexibility, mechanical strength, and direct band gap of 1.89 eV. Experimentalists have studied the synthesis of MoS2 using chemical vapor deposition (CVD) methods in an effort to fabricate wafer-scale nanofilms with a high uniformity and continuity for practical electronic applications. In this work, we applied the CVD method to a reaction of MoO3 powder and H2S gas to grow high-quality polycrystalline monolayer MoS2 sheets with unprecedented uniformity over an area of several centimeters. The monolayer MoS2 was characterized using Raman spectroscopy, photoluminescence (PL) spectroscopy, atomic force microscopy (AFM), x-ray photoemission spectroscopy (XPS), and transmission electron microscopy (TEM). The top-gate field-effect transistor prepared with a 30 nm HfO2 capping layer displayed an electrical mobility of 1 cm(2) v(-1) s(-1) and an I on/off of ~10(5). This method paves the way for the development of practical devices with MoS2 monolayers and advances fundamental research. PMID:27058779

  13. Wafer-scale monolayer MoS2 grown by chemical vapor deposition using a reaction of MoO3 and H2S

    NASA Astrophysics Data System (ADS)

    Kim, Youngchan; Bark, Hunyoung; Ryu, Gyeong Hee; Lee, Zonghoon; Lee, Changgu

    2016-05-01

    Monolayer MoS2 nanosheets are potentially useful in optoelectronics, photoelectronics, and nanoelectronics due to their flexibility, mechanical strength, and direct band gap of 1.89 eV. Experimentalists have studied the synthesis of MoS2 using chemical vapor deposition (CVD) methods in an effort to fabricate wafer-scale nanofilms with a high uniformity and continuity for practical electronic applications. In this work, we applied the CVD method to a reaction of MoO3 powder and H2S gas to grow high-quality polycrystalline monolayer MoS2 sheets with unprecedented uniformity over an area of several centimeters. The monolayer MoS2 was characterized using Raman spectroscopy, photoluminescence (PL) spectroscopy, atomic force microscopy (AFM), x-ray photoemission spectroscopy (XPS), and transmission electron microscopy (TEM). The top-gate field-effect transistor prepared with a 30 nm HfO2 capping layer displayed an electrical mobility of 1 cm2 v‑1 s‑1 and an I on/off of ~105. This method paves the way for the development of practical devices with MoS2 monolayers and advances fundamental research.

  14. LigaSure Hemorrhoidectomy for Symptomatic Hemorrhoids: First Pediatric Experience.

    PubMed

    Grossmann, Ole; Soccorso, Giampiero; Murthi, Govind

    2015-08-01

    Hemorrhoids are uncommon in children. Third and fourth degree symptomatic hemorrhoids may be surgically excised. We describe the first experience of using LigaSure (Covidien, Mansfield, Massachusetts, United States) to perform hemorrhoidectomies in children. LigaSure hemorrhoidectomy has been well described in adults and is found to be superior in patient tolerance as compared with conventional hemorrhoidectomy. PMID:24918403

  15. Solution structure of leptospiral LigA4 Big domain.

    PubMed

    Mei, Song; Zhang, Jiahai; Zhang, Xuecheng; Tu, Xiaoming

    2015-11-13

    Pathogenic Leptospiraspecies express immunoglobulin-like proteins which serve as adhesins to bind to the extracellular matrices of host cells. Leptospiral immunoglobulin-like protein A (LigA), a surface exposed protein containing tandem repeats of bacterial immunoglobulin-like (Big) domains, has been proved to be involved in the interaction of pathogenic Leptospira with mammalian host. In this study, the solution structure of the fourth Big domain of LigA (LigA4 Big domain) from Leptospira interrogans was solved by nuclear magnetic resonance (NMR). The structure of LigA4 Big domain displays a similar bacterial immunoglobulin-like fold compared with other Big domains, implying some common structural aspects of Big domain family. On the other hand, it displays some structural characteristics significantly different from classic Ig-like domain. Furthermore, Stains-all assay and NMR chemical shift perturbation revealed the Ca(2+) binding property of LigA4 Big domain. PMID:26449456

  16. Final-part metrology for LIGA springs, Build Group 1.

    SciTech Connect

    Aigeldinger, Georg; Skala, Dawn M.; Ceremuga, Joseph T.; Mills, Bernice E.

    2004-03-01

    The LIGA spring is a recently designed part for defense program applications. The Sandia California LIGA team has produced an initial group build of these nickel alloy parts. These are distinctive in having a macroscopic lateral size of about 1 cm, while requiring microscopic dimensional precision on the order of a few micrometers. LIGA technology capabilities at Sandia are able to manufacture such precise structures. While certain aspects of the LIGA process and its production capabilities have been dimensionally characterized in the past, [1-6] the present work is exclusive in defining a set of methods and techniques to inspect and measure final LIGA nickel alloy parts in large prototype quantities. One hundred percent inspection, meaning that every single LIGA part produced needs to be measured, ensures quality control and customer satisfaction in this prototype production run. After a general visual inspection of the parts and an x-ray check for voids, high precision dimensional metrology tools are employed. The acquired data is analyzed using both in house and commercially available software. Examples of measurements illustrating these new metrology capabilities are presented throughout the report. These examples furthermore emphasize that thorough inspection of every final part is not only essential to characterize but also improve the LIGA manufacturing process.

  17. Microstructural Evolution of SAC305 Solder Joints in Wafer Level Chip-Scale Packaging (WLCSP) with Continuous and Interrupted Accelerated Thermal Cycling

    NASA Astrophysics Data System (ADS)

    Zhou, Quan; Zhou, Bite; Lee, Tae-Kyu; Bieler, Thomas

    2016-02-01

    Four high-strain design wafer level chip scale packages were given accelerated thermal cycling with a 10°C/min ramp rate and 10 min hold times between 0°C and 100°C to examine the effects of continuous and interrupted thermal cycling on the number of cycles to failure. The interruptions given two of the samples were the result of periodic examinations using electron backscattered pattern mapping, leading to room temperature aging of 30 days-2.5 years after increments of about 100 cycles at several stages of the cycling history. The continuous thermal cycling resulted in solder joints with a much larger degree of recrystallization, whereas the interrupted thermal cycling tests led to much less recrystallization, which was more localized near the package side, and the crack was more localized near the interface and had less branching. The failure mode for both conditions was still the same, with cracks nucleating along the high angle grain boundaries formed during recrystallization. In conditions where there were few recrystallized grains, recovery led to formation of subgrains that strengthened the solder, and the higher strength led to a larger driving force for crack growth through the solder, leading to failure after less than half of the cycles in the continuous accelerated thermal cycling condition. This work shows that there is a critical point where sufficient strain energy accumulation will trigger recrystallization, but this point depends on the rate of strain accumulation in each cycle and various recovery processes, which further depends on local crystal orientations, stress state evolution, and specific activated slip and twinning systems.

  18. Microstructural Evolution of SAC305 Solder Joints in Wafer Level Chip-Scale Packaging (WLCSP) with Continuous and Interrupted Accelerated Thermal Cycling

    NASA Astrophysics Data System (ADS)

    Zhou, Quan; Zhou, Bite; Lee, Tae-Kyu; Bieler, Thomas

    2016-06-01

    Four high-strain design wafer level chip scale packages were given accelerated thermal cycling with a 10°C/min ramp rate and 10 min hold times between 0°C and 100°C to examine the effects of continuous and interrupted thermal cycling on the number of cycles to failure. The interruptions given two of the samples were the result of periodic examinations using electron backscattered pattern mapping, leading to room temperature aging of 30 days-2.5 years after increments of about 100 cycles at several stages of the cycling history. The continuous thermal cycling resulted in solder joints with a much larger degree of recrystallization, whereas the interrupted thermal cycling tests led to much less recrystallization, which was more localized near the package side, and the crack was more localized near the interface and had less branching. The failure mode for both conditions was still the same, with cracks nucleating along the high angle grain boundaries formed during recrystallization. In conditions where there were few recrystallized grains, recovery led to formation of subgrains that strengthened the solder, and the higher strength led to a larger driving force for crack growth through the solder, leading to failure after less than half of the cycles in the continuous accelerated thermal cycling condition. This work shows that there is a critical point where sufficient strain energy accumulation will trigger recrystallization, but this point depends on the rate of strain accumulation in each cycle and various recovery processes, which further depends on local crystal orientations, stress state evolution, and specific activated slip and twinning systems.

  19. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis

    NASA Astrophysics Data System (ADS)

    Zhao, C.; Konstantinidis, A. C.; Zheng, Y.; Anaxagoras, T.; Speller, R. D.; Kanicki, J.

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm-1 and a DQE of around 0.5 at spatial frequencies  <1 mm-1. In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered.

  20. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    PubMed

    Zhao, C; Konstantinidis, A C; Zheng, Y; Anaxagoras, T; Speller, R D; Kanicki, J

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm(-1) and a DQE of around 0.5 at spatial frequencies  <1 mm(-1). In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered. PMID:26540090

  1. Wafer scale micromachine assembly method

    DOEpatents

    Christenson, Todd R.

    2001-01-01

    A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.

  2. Micro-grippers for assembly of LIGA parts

    SciTech Connect

    Feddema, J.; Polosky, M.; Christenson, T.; Spletzer, B.; Simon, R.

    1997-12-31

    This paper describes ongoing testing of two microgrippers for assembly of LIGA (Lithographie Galvanoformung Abformung) parts. The goal is to place 100 micron outside diameter (OD) LIGA gears with a 50 micron inner diameter hole onto pins ranging from 35 to 49 microns. The first micro gripper is a vacuum gripper made of a 100 micron OD stainless steel tube. The second micro gripper is a set of tweezers fabricated using the LIGA process. Nickel, Permalloy, and copper materials are tested. The tweezers are actuated by a collet mechanism which is closed by a DC linear motor.

  3. Scriber for silicon wafers

    NASA Technical Reports Server (NTRS)

    Yamakawa, K. A.; Fortier, E. P. (Inventor)

    1981-01-01

    A device for dividing silicon wafers into rectangular chips is characterized by a base including a horizontally oriented bed with a planar support surface, a vacuum chuck adapted to capture a silicon wafer seated on the support for translation in mutually perpendicular directions. A stylus support mounted on the bed includes a shaft disposed above and extended across the bed and a truck mounted on the shaft and supported thereby for linear translation along a path extended across the bed a vertically oriented scribe has a diamond tip supported by the truck also adapted as to engage a silicon wafer captured by the chuck and positioned beneath it in order to form score lines in the surface of the wafer as linear translation is imparted to the truck. A chuck positioning means is mounted on the base and is connected to the chuck for positioning the chuck relative to the stylus.

  4. Wafer characteristics via reflectometry

    DOEpatents

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  5. Reciprocating Saw for Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.; Collins, E. R., Jr.

    1985-01-01

    Concept increases productivity and wafer quality. Cutting wafers from silicon ingots produces smooth wafers at high rates with reduced blade wear. Involves straight reciprocating saw blade and slight rotation of ingot between cutting strokes. Many parallel blades combined to cut many wafers simultaneously from ingot.

  6. Cantilevered multilevel LIGA devices and methods

    DOEpatents

    Morales, Alfredo Martin; Domeier, Linda A.

    2002-01-01

    In the formation of multilevel LIGA microstructures, a preformed sheet of photoresist material, such as polymethylmethacrylate (PMMA) is patterned by exposure through a mask to radiation, such as X-rays, and developed using a developer to remove the exposed photoresist material. A first microstructure is then formed by electroplating metal into the areas from which the photoresist has been removed. Additional levels of microstructure are added to the initial microstructure by covering the first microstructure with a conductive polymer, machining the conductive polymer layer to reveal the surface of the first microstructure, sealing the conductive polymer and surface of the first microstructure with a metal layer, and then forming the second level of structure on top of the first level structure. In such a manner, multiple layers of microstructure can be built up to allow complex cantilevered microstructures to be formed.

  7. Miniature Scroll Pumps Fabricated by LIGA

    NASA Technical Reports Server (NTRS)

    Wiberg, Dean; Shcheglov, Kirill; White, Victor; Bae, Sam

    2009-01-01

    Miniature scroll pumps have been proposed as roughing pumps (low - vacuum pumps) for miniature scientific instruments (e.g., portable mass spectrometers and gas analyzers) that depend on vacuum. The larger scroll pumps used as roughing pumps in some older vacuum systems are fabricated by conventional machining. Typically, such an older scroll pump includes (1) an electric motor with an eccentric shaft to generate orbital motion of a scroll and (2) conventional bearings to restrict the orbital motion to a circle. The proposed miniature scroll pumps would differ from the prior, larger ones in both design and fabrication. A miniature scroll pump would include two scrolls: one mounted on a stationary baseplate and one on a flexure stage (see figure). An electromagnetic actuator in the form of two pairs of voice coils in a push-pull configuration would make the flexure stage move in the desired circular orbit. The capacitance between the scrolls would be monitored to provide position (gap) feedback to a control system that would adjust the drive signals applied to the voice coils to maintain the circular orbit as needed for precise sealing of the scrolls. To minimize power consumption and maximize precision of control, the flexure stage would be driven at the frequency of its mechanical resonance. The miniaturization of these pumps would entail both operational and manufacturing tolerances of <1 m. Such tight tolerances cannot be achieved easily by conventional machining of high-aspect-ratio structures like those of scroll-pump components. In addition, the vibrations of conventional motors and ball bearings exceed these tight tolerances by an order of magnitude. Therefore, the proposed pumps would be fabricated by the microfabrication method known by the German acronym LIGA ( lithographie, galvanoformung, abformung, which means lithography, electroforming, molding) because LIGA has been shown to be capable of providing the required tolerances at large aspect ratios.

  8. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  9. Wafer level reliability testing: An idea whose time has come

    NASA Technical Reports Server (NTRS)

    Trapp, O. D.

    1987-01-01

    Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

  10. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  11. Thinning of PLZT ceramic wafers for sensor integration

    NASA Astrophysics Data System (ADS)

    Jin, Na; Liu, Weiguo

    2010-08-01

    Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

  12. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  13. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  14. Within-wafer CD variation induced by wafer shape

    NASA Astrophysics Data System (ADS)

    Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

    2016-03-01

    In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer

  15. Laser-LIGA for Ni microcantilevers

    NASA Astrophysics Data System (ADS)

    Jin, Hengyi; Harvey, Erol C.; Hayes, Jason P.; Ghantasala, Muralidhar K.; Fu, Yao; Jolic, Karlo; Solomon, Matthew; Graves, Kynan

    2002-11-01

    This paper presents our design and experimental results of nickel microcantilevers, which were fabricated using a laser-LIGA process, based on KrF (248 nm) excimer laser micromachining. A chrome-on-quartz mask, containing the desired mask patterns was prepared for this work. The substrate of copper (30 μm thick) clad printed circuit board (PCB) was laminated with Laminar 5038 photopolymer to be laser patterned. Following laser patterning and laser cleaning, all the samples were electroformed with nickel on top of the copper layer. To release the Ni microcantilevers, the excimer laser was employed again to remove the polymer in the localised area to facilitate Cu selective etching. Here, copper acted as the sacrificial layer as well. The Cu selective etching was carried out with ~ 20 % (wt) aqueous solution of ammonium persulfate. Because the Cu selective etching is isotropic, some undercuts happened next to the anchor area. The samples were characterised using optical microscope, confocal laser scanning microscope and SEM, and some of Ni cantilevers were tested electro-thermally. Their performance was analyzed with respect to the simulation results.

  16. Etching Of Semiconductor Wafer Edges

    DOEpatents

    Kardauskas, Michael J.; Piwczyk, Bernhard P.

    2003-12-09

    A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

  17. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  18. Osmolarity, a Key Environmental Signal Controlling Expression of Leptospiral Proteins LigA and LigB and the Extracellular Release of LigA

    PubMed Central

    Matsunaga, James; Sanchez, Yolanda; Xu, Xiaoyi; Haake, David A.

    2005-01-01

    The high-molecular-weight leptospiral immunoglobulin-like repeat (Lig) proteins are expressed only by virulent low-passage forms of pathogenic Leptospira species. We examined the effects of growth phase and environmental signals on the expression, surface exposure, and extracellular release of LigA and LigB. LigA was lost from stationary-phase cells, while LigB expression was maintained. The loss of cell-associated LigA correlated with selective release of a lower-molecular-weight form of LigA into the culture supernatant, while LigB and the outer membrane lipoprotein LipL41 remained associated with cells. Addition of tissue culture medium to leptospiral culture medium induced LigA and LigB expression and caused a substantial increase in released LigA. The sodium chloride component of tissue culture medium was primarily responsible for the enhanced release of LigA. Addition of sodium chloride, potassium chloride, or sodium sulfate to leptospiral medium to physiological osmolarity caused the induction of both cell-associated LigA and LigB, indicating that osmolarity regulates the expression of Lig proteins. Osmotic induction of Lig expression also resulted in enhanced release of LigA and increased surface exposure of LigB, as determined by surface immunofluorescence. Osmolarity appears to be a key environmental signal that controls the expression of LigA and LigB. PMID:15618142

  19. Recent Developments in Microsystems Fabricated by the Liga-Technique

    NASA Technical Reports Server (NTRS)

    Schulz, J.; Bade, K.; El-Kholi, A.; Hein, H.; Mohr, J.

    1995-01-01

    As an example of microsystems fabricated by the LIGA-technique (x-ray lithography, electroplating and molding), three systems are described and characterized: a triaxial acceleration sensor system, a micro-optical switch, and a microsystem for the analysis of pollutants. The fabrication technologies are reviewed with respect to the key components of the three systems: an acceleration sensor, and electrostatic actuator, and a spectrometer made by the LIGA-technique. Aa micro-pump and micro-valve made by using micromachined tools for molding and optical fiber imaging are made possible by combining LIGA and anisotropic etching of silicon in a batch process. These examples show that the combination of technologies and components is the key to complex microsystems. The design of such microsystems will be facilitated is standardized interfaces are available.

  20. Wafer-scale crack-free AlGaN on GaN through two-step selective-area growth for optically pumped stimulated emission

    NASA Astrophysics Data System (ADS)

    Ko, Young-Ho; Bae, Sung-Bum; Kim, Sung-Bock; Kim, Dong Churl; Leem, Young Ahn; Cho, Yong-Hoon; Nam, Eun-Soo

    2016-07-01

    Crack-free AlGaN template has been successfully grown over entire 2-in. wafer by using 2-step selective-area growth (SAG). The GaN truncated structure was obtained by vertical growth mode with low growth temperature. AlGaN of second step was grown under lateral growth mode. Low pressure enhanced the relative ratio of lateral to vertical growth rate as well as absolute overall growth rate. High V/III ratio was favorable for lateral growth mode. Crack-free planar AlGaN was obtained under low pressure of 30 Torr and high V/III ratio of 4400. The AlGaN was crack-free over entire 2-in. wafer and had quite uniform Al-mole fraction. The dislocation density of the AlGaN with 20% Al-composition was as low as ~7.6×108 /cm2, measured by cathodoluminescence. GaN/AlGaN multi-quantum well (MQW) with cladding and waveguide layers were grown on the crack-free AlGaN template with low dislocation density. It was confirmed that the MQW on the AlGaN template emitted the stimulated emission at 355.5 nm through optical pumping experiment. The AlGaN obtained by 2-step SAG would provide high crystal quality for highly-efficient optoelectronic devices as well as the ultraviolet laser diode.

  1. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the

  2. Wafer level warpage characterization of 3D interconnect processing wafers

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2012-03-01

    We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 μm after thinning down to the nominal thickness of 75 μm and 50 μm. The measurement precision is better than 2 um.

  3. Development of a LIGA-based elastodynamic flying mechanism

    NASA Astrophysics Data System (ADS)

    Cox, Adam G.; Garcia, Ephrahim

    1998-07-01

    With the emergence of MEMS and LIGA technology piezoceramics can be integrated to create tiny solid state devices. The precision motion that piezoelectric materials can provide is complimented by the tolerances that can be achieved through MEMS and LIGA micromachining. The integration of these two technologies is ideal for microactuation. A LIGA based devices has been developed that is capable of amplifying small motions from a piezoelectric element into an output stroke angle large enough to produce flight. Micro flight is a difficult aerodynamic problem. With small wing areas conventional lift requires velocities that are difficult to achieve. However it is possible to induce lift using drag in the same manner as some birds and insects. Flapping is a highly efficient way to produce flight. For sustained low energy flight both insects and birds use a complex elastodynamic system that only requires them to excite it at its natural frequency. The actuation device presented is based on the same flight principle of insects and birds, a resonating elastodynamic system excited at its natural frequency or at a lower harmonic. This allows for long distance flights that require little energy. Piezoceramics posses a high energy level and force output that can excite the device and induce a flapping motion. The dynamics of the system rely on the LIGA flexure mechanism, the piezoelectric element, as well as the aerodynamic interaction of the wing and the air which is a complex nonlinear problem.

  4. Wafer-scale controlled exfoliation of metal organic vapor phase epitaxy grown InGaN/GaN multi quantum well structures using low-tack two-dimensional layered h-BN

    NASA Astrophysics Data System (ADS)

    Ayari, Taha; Sundaram, Suresh; Li, Xin; El Gmili, Youssef; Voss, Paul L.; Salvestrini, Jean Paul; Ougazzaden, Abdallah

    2016-04-01

    Recent advances in epitaxial growth have led to the growth of III-nitride devices on 2D layered h-BN. This advance has the potential for wafer-scale transfer to arbitrary substrates, which could improve the thermal management and would allow III-N devices to be used more flexibly in a broader range of applications. We report wafer scale exfoliation of a metal organic vapor phase epitaxy grown InGaN/GaN Multi Quantum Well (MQW) structure from a 5 nm thick h-BN layer that was grown on a 2-inch sapphire substrate. The weak van der Waals bonds between h-BN atomic layers break easily, allowing the MQW structure to be mechanically lifted off from the sapphire substrate using a commercial adhesive tape. This results in the surface roughness of only 1.14 nm on the separated surface. Structural characterizations performed before and after the lift-off confirm the conservation of structural properties after lift-off. Cathodoluminescence at 454 nm was present before lift-off and 458 nm was present after. Electroluminescence near 450 nm from the lifted-off structure has also been observed. These results show that the high crystalline quality ultrathin h-BN serves as an effective sacrificial layer—it maintains performance, while also reducing the GaN buffer thickness and temperature ramps as compared to a conventional two-step growth method. These results support the use of h-BN as a low-tack sacrificial underlying layer for GaN-based device structures and demonstrate the feasibility of large area lift-off and transfer to any template, which is important for industrial scale production.

  5. Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

    PubMed Central

    Thomson, Stephen R. D.; Perron, Justin K.; Kimball, Mark O.; Mehta, Sarabjit; Gasparini, Francis M.

    2014-01-01

    Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale. PMID:24457563

  6. Augmented reality for wafer prober

    NASA Astrophysics Data System (ADS)

    Gilgenkrantz, Pascal

    2011-03-01

    The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

  7. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  8. Ulnar Impaction Syndrome: Ulnar Shortening vs. Arthroscopic Wafer Procedure

    PubMed Central

    Smet, Luc De; Vandenberghe, Lore; Degreef, Ilse

    2014-01-01

    The outcome of ulnar shortenings was compared with that of arthroscopic wafer resections for ulnar impaction (or abutment) syndrome in patients with a positive ulnar variance. The outcome was measured by DASH score, visual analog scale for pain, and working incapacity. The mean DASH score in the ulnar shortening group was 26; in the wafer group it was 36. The VAS scores were respectively 4.4 and 4.6. The working incapacity was 7?months in the ulnar shortening group and 6.1 months in the wafer group. The differences between the two groups were not statistically significant. PMID:25032075

  9. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  10. W-band LiGA fabricated klystron

    NASA Astrophysics Data System (ADS)

    Song, Liqun

    2002-01-01

    Klystrino-W-band klystron was proposed by scientists at SLAC to satisfy recent applications in advanced accelerators, medical treatment, radars and communications. LiGA (a German acronym for lithographe, galvanoformung, and abformung) is introduced in the fabrication of klystrino for the first time in the history of microwave tube fabrication. The cold test experiments show that LiGA fabrication yields best surface smoothness compared with an alternative way EDM (Electrical Discharge Machining). Resultantly LiGA fabricated klystrino has the smallest wall loss which maximizes the circuit efficiency of the output structure. A multiple-gap coupled cavity is motivated to be employed as the klystrino output cavity for maximizing the efficiency. Klytrino is simulated by 1-D, 2-D and 3-D simulation codes. Particularly a complete klystrino is simulated intensively using 2-D MAGIC Particle-in-Cell (PIC) code either for beam absence or beam presence. Many simulation techniques are developed such as model transformation from 3-D to 2-D, circuit parameter simulation, dispersion characteristic analysis, pre bunched electron beam mode and so on. Klystrino, as a 3-D structure, is modeled by 3-D MAFIA for analyzing the cold circuit properties. 3-D MAGIC is explored to simulate klystrino for the actual structure analysis and actual beam interaction process observation.

  11. In-situ detection method for wafer movement and micro-arc discharge around a wafer in plasma etching process using electrostatic chuck wafer stage with built-in acoustic emission sensor

    NASA Astrophysics Data System (ADS)

    Kasashima, Yuji; Tabaru, Tatsuo; Yasaka, Mitsuo; Kobayashi, Yoshikazu; Akiyama, Morito; Nabeoka, Natsuko; Motomura, Taisei; Sakamoto, Shingo; Uesugi, Fumihiko

    2014-01-01

    We report an electrostatic chuck (ESC) wafer stage with a built-in acoustic emission (AE) sensor for detecting anomalies occurring around a wafer during plasma etching. The built-in AE sensor detects acoustic waves caused by wafer movement and micro-arc discharge with high sensitivity, and identifies these anomalies based on the frequency characteristics of the waves. The results demonstrate the effectiveness of using an ESC wafer stage with a built-in AE sensor for in-situ anomaly detection, which can improve the production yield and overall equipment efficiency in large scale integrated circuit (LSI) manufacturing.

  12. [Thyroidectomy with LigaSure versus traditional thyroidectomy: our experience].

    PubMed

    Marrazzo, Antonio; Casà, Luigi; David, Massimo; Lo Gerfo, Domenico; Noto, Antonio; Riili, Ignazio; Taormina, Pietra

    2007-01-01

    Over the past few decades the surgical strategy for both benign and malignant thyroid diseases has undergone several changes. In particular, total thyroidectomy today has become the routine operation for most thyroid diseases. The complications of this surgical procedure, though of multifactorial aetiopathogenesis, are often related to the efficacy of the haemostasis. Our aim in this study was to verify whether the use of the new LigaSure haemostatic system is capable of reducing the incidence of these complications as well as operative times and length of hospital stay as compared to the conventional haemostatic procedures. Twenty-five patients were randomly assigned to thyroidectomy with LigaSureTM (group A), and 25 to total thyroidectomy using the conventional haemostasis procedures (group B). Of these, 39 were women and 11 men, with a mean age +/- standard deviation of 52.26 +/- 13.57 years. In both groups the thyroidectomy was performed according to the standard total thyroidectomy surgical technique entailing the placement of two aspiration drainages at the end of the operation. As regards the assessment of operative times, these were significantly lower in thyroidectomy with LigaSureTM compared to traditional thyroidectomy (duration: 60 +/- 14.8 min [range: 60-105) in group A versus 92.4 +/- 27.5 min [range: 70-150] in group B, p = 0.02). The total amount of fluid drained postoperatively was substantially similar in the two groups (145 +/- 80 cc in group A versus 140 +/- 64.1 cc in group B). The incidence of postoperative complications was also similar in the two groups. We had only one case of haemorrhage in a patient submitted to thyroidectomy with LigaSureTM, 8 cases of transitory hypocalcaemia, 3 of which in patients with LigaSure thyroidectomy and 5 in patients treated with traditional thyroidectomy (p = 0.42), 2 cases of stupor of the recurrent nerve (1 in group A and 1 in group B) and a single definitive recurrent lesion in a group B patient with

  13. Wafer handling and placement tool

    DOEpatents

    Witherspoon, Linda L.

    1988-01-05

    A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

  14. Wafer Replacement Cluster Tool (Presentation);

    SciTech Connect

    Branz, H. M.

    2008-04-01

    This presentation on wafer replacement cluster tool discusses: (1) Platform for advanced R and D toward SAI 2015 cost goal--crystal silicon PV at area costs closer to amorphous Si PV, it's 15% efficiency, inexpensive substrate, and moderate temperature processing (<800 C); (2) Why silicon?--industrial and knowledge base, abundant and environmentally benign, market acceptance, and good efficiency; and (3) Why replace wafers?--expensive, high embedded energy content, and uses 50-100 times more silicon than needed.

  15. Note: Near infrared interferometric silicon wafer metrology

    NASA Astrophysics Data System (ADS)

    Choi, M. S.; Park, H. M.; Joo, K. N.

    2016-04-01

    In this investigation, two near infrared (NIR) interferometric techniques for silicon wafer metrology are described and verified with experimental results. Based on the transparent characteristic of NIR light to a silicon wafer, the fiber based spectrally resolved interferometry can measure the optical thickness of the wafer and stitching low coherence scanning interferometry can reconstruct entire surfaces of the wafer.

  16. Wafer dicing utilizing unique beam shapes

    NASA Astrophysics Data System (ADS)

    Lizotte, Todd; Ohar, Orest

    2007-09-01

    Laser dicing of wafers is of keen interest to the semiconductor and LED industry. Devices such as ASICs, Ultra-thin Wafer Scale Packages and LEDS are unique in that they typically are formed from various materials in a multilayered structure. Many of these layers include active device materials, passivation coatings, conductors and dielectric films all deposited on top of a bulk wafer substrate and all potentially having differing ablation thresholds. These composite multi-layered structures require high finesse laser processes to ensure yields, cut quality and low process cost. Such processes have become very complex over the years as new devices have become miniaturized, requiring smaller kerf sizes. Of critical concern is the need to minimize substrate micro-cracking or lift off of upper layers along the dicing streets which directly corresponds to bulk device strength and device operational integrity over its projected lifetime. Laser processes involving the sequential use of single or multiple diode pumped solid state (DPSS) lasers, such as UV DPSS (355nn, 266nm, 532 nm), VIS DPSS (~532 nm) and IR DPSS (1064nm, 1070nm) as well as (UV, VIS, NIR, FIR and Eye Safe Wavelengths) DPFL (Diode Pumped Fiber Lasers) lasers to penetrate various and differing material layers and substrates including Silicon Carbide (SiC), Silicon, GaAs and Sapphire. Development of beam shaping optics with the purpose of permitting two or more differing energy densities within a single focused or imaged beam spot would provide opportunities for pre-processing or pre-scribing of thinner cover layers, while following through with a higher energy density segment to cut through the bulk base substrates. This paper will describe the development of beam shaping optical elements with unique beam shapes that could benefit dicing and patterning of delicate thin film coatings. Various designs will be described, with processing examples using LED wafer materials.

  17. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    NASA Astrophysics Data System (ADS)

    Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

    2014-08-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

  18. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    PubMed

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

  19. Development of Megasonic cleaning for silicon wafers. Final report

    SciTech Connect

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  20. Wafer sampling by regression for systematic wafer variation detection

    NASA Astrophysics Data System (ADS)

    Moon, Byungsool; McNames, James; Whitefield, Bruce; Rudolph, Paul; Zola, Jeff

    2005-05-01

    In-line measurements are used to monitor semiconductor manufacturing processes for excessive variation using statistical process control (SPC) chart techniques. Systematic spatial wafer variation often occurs in a recognizable pattern across the wafer that is characteristic of a particular manufacturing step. Visualization tools are used to associate these patterns with specific manufacturing steps preceding the measurement. Acquiring the measurements is an expensive and slow process. The number of sites measured on a wafer must be minimized while still providing sufficient data to monitor the process. We address two key challenges to effective wafer-level monitoring. The first challenge is to select a small sample of inspection sites that maximize detection sensitivity to the patterns of interest, while minimizing the confounding effects of other types of wafer variation. The second challenge is to develop a detection algorithm that maximizes sensitivity to the patterns of interest without exceeding a user-specified false positive rate. We propose new sampling and detection methods. Both methods are based on a linear regression model with distinct and orthogonal components. The model is flexible enough to include many types of systematic spatial variation across the wafer. Because the components are orthogonal, the degree of each type of variation can be estimated and detected independently with very few samples. A formal hypothesis test can then be used to determine whether specific patterns are present. This approach enables one to determine the sensitivity of a sample plan to patterns of interest and the minimum number of measurements necessary to adequately monitor the process.

  1. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    DOEpatents

    Bajikar, Sateesh S.; De Carlo, Francesco; Song, Joshua J.

    2001-01-01

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  2. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    SciTech Connect

    Bajikar, Sateesh S.; De Carlo, Francesco; Song, Joshua J.

    2004-01-27

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  3. Selective area growth of InP in shallow trench isolation on large scale Si(001) wafer using defect confinement technique

    NASA Astrophysics Data System (ADS)

    Merckling, C.; Waldron, N.; Jiang, S.; Guo, W.; Richard, O.; Douhard, B.; Moussa, A.; Vanhaeren, D.; Bender, H.; Collaert, N.; Heyns, M.; Thean, A.; Caymax, M.; Vandervorst, W.

    2013-07-01

    Heterogeneous integration of III-V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III-V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III-V virtual substrates on large-scale Si substrates.

  4. Fabrication of Compound Refractive X-ray Lenses Using LIGA Process and Performance Tests

    SciTech Connect

    Lee, Jin Pyoung; Kim, Guk Bae; Kim, Jong Hyun; Chang, Suk Sang; Lee, Sang Joon

    2007-01-19

    Recent advances of X-ray microscopy technology enable the visualization of some micro/nano-scale objects which optical microscopy and electron microscopy cannot be used to observe. The X-ray microscopy can be applied to observe the internal structure of a thicker sample than the electron microscopy can, and its spatial resolution is higher than that of the optical microscopy. Moreover, it has a powerful element specific imaging ability. For further improving the X-ray microscope, it is indispensable to make X-ray optics for focusing X-rays more effectively. Recently, various X-ray lenses such as diffraction lenses of FZP(Fresnel zone plate) and spatter-sliced FZT, total reflection lenses of K-B(Kirkpatrick-Baez) mirror and Wolter mirror, and refractive lens of CRL(compound refractive lens) were introduced. Compared with the other types of lenses, CRL is easy to fabricate and handle. In this study, we designed and fabricated various types of CRLs using LIGA(LIthographie, Galvanoformung, Abformtechnik) process, and used PMMA(Poly(methyl methacrylate)) material as the material of CRL. Their performances are tested with varying parameters such as parabolic/kinoform shape, radius of curvature, wall thickness between adjacent lenses, and width of lenses. The performance tests were carried out by using a simple synchrotron X-ray imaging method. The tests results revealed that hard x-rays could be condensed well by the CRL of PMMA material at the focal point we expect We captured sample images one-dimensionally magnified by CRLs. Furthermore, we found which parameter is more effective for enhancing focus efficiency and which parameter should be considered more carefully in the fabrication process of LIGA.

  5. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R.

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  6. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  7. Nano-particle laser removal from silicon wafers

    NASA Astrophysics Data System (ADS)

    Lee, J. M.; Cho, S. H.; Kim, T. H.; Park, Jin-Goo; Busnaina, Ahmed A.

    2003-11-01

    A laser shock cleaning (LSC) technique as a new dry cleaning methodology has been applied to remove micro and nano-scale inorganic particulate contaminants. Shock wave is generated in the air just above the wafer surface by focusing intensive laser beam. The velocity of shock wave can be controlled to 10,000 m/sec. The sub-micron sized silica and alumina particles are attempted to remove from bare silicon wafer surfaces. More than 95% of removal efficiency of the both particles are carried out by the laser-induced airborne shock waves. In the final, a removal of nano-scale slurry particles from real patterned wafers are successfully demonstrated by LSC after chemical-mechanical polishing (CMP) process.

  8. Manufacturing microcomponents for optical information technology using the LIGA technique

    NASA Astrophysics Data System (ADS)

    Bauer, Hans-Dieter; Ehrfeld, Wolfgang; Hossfeld, Jens; Paatzsch, Thomas

    1999-09-01

    Recently, splices and connectors for fibers ribbons, optical cross connects and especially planar waveguide devices have been fabricated via LIGA in combination with precision engineering techniques. LIGA combines high precision and mass production capability, necessary for products designed for applications in the telecom and datacom market. In this presentation the fabrication of three-level molding and embossing tools is presented, which have been used for the manufacturing of waveguide prestructures consisting of waveguide channels and bier-to-waveguide coupling grooves. The precision of the tools is better than 1 micrometers in all directions, which allows for simple passive pigtailing. A first product, a precision of the tool is better than 1 micrometers in all directions, which allows for simple passive pigtailing. A first product, sixfold array of 4 X 4 multimode star couplers has been realized. The molding behavior of PMMA and COC material has been tested and compared. Production and assembly was tested by fabricating a series of 300 star couplers. The average insertion los has been found better than 9dB, the uniformity better than 3dB, both measured at 830nm. THe device is designed for application in optical backplanes for high-speed computers.

  9. GEM-type detectors using LIGA and etchable glass technologies

    SciTech Connect

    Ahn, S.K.; Kim, J.G.; Perez-Mendez, V.; Chang, S.; Jackson, K.H.; Kadyk, J.A.; Wenzel, W.A.; Cho, G.

    2001-11-02

    Gas electron multipliers (GEMS) have been made by a deep X-ray lithography technique (LIGA process) using synchrotron radiation on polymethylmethacrylate (PMMA) and by UV processes using a UV etchable glass. Gain, stability and rate capability for these detectors are described.The LIGA detectors described consist of PMMA sheets of various thicknesses, 125mm to 350mm, and have 150mm x 150mm square holes spaced with a pitch of 300mm. Thin copper electrodes are plated on the top and bottom surfaces using a Damascene method, followed by electroless plating of the copper onto a palladium-tin base layer. For various thicknesses of PMMA measurements have been made of absolute gain vs. voltage, time stability of gain, and rate capability. The operating gas mixture was usually Ar/CO2 (70/30) gas, but some tests were also done using P10 gas. We also made GEM-like detectors using the UV etchable glass called Foturan, patterned by exposure to UV light and subsequent etching. A few measurements using these detectors will be reported, including avalanche gain and time stability.

  10. Allowable silicon wafer thickness versus diameter for ingot rotation ID wafering

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1982-01-01

    Inner diameter (ID) wafering of ingot rotation reduce the ID saw blade diameter was investigated. The blade thickness can be reduced, resulting in minimal kerf loss. However, significant breakage of wafers occurs during the rotation wafering as the wafer thickness decreases. Fracture mechanics was used to develop an equation relating wafer thickness, diameter and fracture behavior at the point of fracture by using a model of a wafer, supported by a center column and subjected to a cantilever force. It is indicated that the minimum allowable wafer thickness does not increase appreciably with increasing wafer diameter and that fracture through the thickness rather than through the center supporting column limits the minimum allowable wafer thickness. It is suggested that the minimum allowable wafer thickness can be reduced by using a vacuum chuck on the wafer surface to enhance cleavage fracture of the center core and by using 111 ingots.

  11. LIGA-based microsystem manufacturing:the electrochemistry of through-mold depostion and material properties.

    SciTech Connect

    Kelly, James J. (Sandia National Laboratories, Livermore, CA); Goods, Steven Howard (Sandia National Laboratories, Livermore, CA)

    2005-06-01

    The report presented below is to appear in ''Electrochemistry at the Nanoscale'', Patrik Schmuki, Ed. Springer-Verlag, (ca. 2005). The history of the LIGA process, used for fabricating dimensional precise structures for microsystem applications, is briefly reviewed, as are the basic elements of the technology. The principal focus however, is on the unique aspects of the electrochemistry of LIGA through-mask metal deposition and the generation of the fine and uniform microstructures necessary to ensure proper functionality of LIGA components. We draw from both previously published work by external researchers in the field as well as from published and unpublished studies from within Sandia.

  12. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Astrophysics Data System (ADS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-02-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  13. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  14. Fabrication of Spiral Micro-Coil Utilizing LIGA Process

    NASA Astrophysics Data System (ADS)

    Shimada, Osamu; Kusumi, Shinji; Mekaru, Harutaka; Sato, Noriaki; Shimizu, Masami; Yamashita, Michiru; Hattori, Tadashi

    We developed a method for fabricating a three-dimensional spiral micro-inductor with high inductance using the LIGA process. The spiral inductor created had a diameter of 0.5mm, and a length of 1mm. The width of the spiral line was 10µm, the pitch was 20µm, and the number of turns was 15. It was made of plated copper. The master was a brass round bar coated with PMMA resist. Deep X-ray lithography was employed to fabricate a master for a metallic mold at the NewSUBARU synchrotron radiation facility, University of Hyogo. The inductor core was made of resin by injection molding. It has a spiral micro flute on the surface. We chose the worm injection molding technique in order to avoid the parting line across the spiral line. The worm injection molding was the method─for demolding the work such as that used in loosening a screw.

  15. Temperature Dependent Electrical Properties of PZT Wafer

    NASA Astrophysics Data System (ADS)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  16. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  17. Low-loss LIGA-micromachined conductor-backed coplanar waveguide.

    SciTech Connect

    Forman, Michael A.

    2004-12-01

    A mesoscale low-loss LIGA-micromachined conductor-backed coplanar waveguide is presented. The 517 {micro}m lines are the tallest uniplanar LIGA-fabricated microwave transmission lines to date, as well as the first to be constructed of copper rather than nickel. The conductor-backed micromachined CPW on quartz achieves a measured attenuation of 0.064 dB/cm at 15.5 GHz.

  18. Wafer-bonded surface plasmon waveguides

    NASA Astrophysics Data System (ADS)

    Berini, Pierre; Mattiussi, Greg; Lahoud, Nancy; Charbonneau, Robert

    2007-02-01

    Direct wafer bonding and thinning were explored as an approach for constructing long-range surface plasmon waveguides. The structures consist of a thin metal stripe deposited into a shallow trench etched into one of the claddings, to which another cladding of the same material is directly bonded. The approach was developed first using Pyrex wafers in order to assess feasibility and then using lithium niobate wafers. Optical and electro-optical measurements validate the approach.

  19. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  20. Micro cycloid-gear system fabricated by multiexposure LIGA technique

    NASA Astrophysics Data System (ADS)

    Hirata, Toru; Chung, Song-Jo; Hein, Herbert; Akashi, Tomoyuki; Mohr, Juergen

    1999-09-01

    In this paper, a prototype of 2 mm-diameter micro-cycloid gear system fabricated by the multi-exposure LIGA technique is presented. The entire gear system consists of a casing and three vertically stacked disks and gears. Each part is composed of three different levels. The first level, 40 micrometers high, was fabricated by UV-lithography, and the second as well as the third level, 195 micrometers and 250 micrometers high respectively, were processed by aligned deep X-ray lithography (DXL). The alignment error between two DXL- processed layers was measured, and the results have turned out to be within +/- 5 micrometers range. As a result of the height control process by the mechanical surface machining, the deviation of structural height has been maintained within +/- 3 micrometers range for the UV-lithography-processed structures, and +/- 10 micrometers for the DXL-processed structures. Further the tests of gear assembly were implemented with 125 micrometers -diameter glass fiber, by using a die-bonding machine with vacuum gripper under stereo- microscope. Finally the dynamic tests of the gear system were successfully conducted with the mechanical torque input by an electrical motor. A proper rotational speed reduction was observed in the operational input range of 3 to 1500 rpm with the designed gear ratio of 18.

  1. An aluminum resist substrate for microfabrication by LIGA.

    SciTech Connect

    Kelly, James J.; Boehme, Dale R.; Hauck, Cheryl A.; Yang, Chu-Yeu Peter; Hunter, Luke L.; Griffiths, Stewart K.; McLean, Dorrance E.; Aigeldinger, Georg; Hekmaty, Michelle A.; Hachman, John T.; Losey, Matthew W.; Skala, Dawn M.; Korellis, John S.; Friedmann, Thomas Aquinas; Yang, Nancy Y. C.; Lu, Wei-Yang

    2005-04-01

    Resist substrates used in the LIGA process must provide high initial bond strength between the substrate and resist, little degradation of the bond strength during x-ray exposure, acceptable undercut rates during development, and a surface enabling good electrodeposition of metals. Additionally, they should produce little fluorescence radiation and give small secondary doses in bright regions of the resist at the substrate interface. To develop a new substrate satisfying all these requirements, we have investigated secondary resist doses due to electrons and fluorescence, resist adhesion before exposure, loss of fine features during extended development, and the nucleation and adhesion of electrodeposits for various substrate materials. The result of these studies is a new anodized aluminum substrate and accompanying methods for resist bonding and electrodeposition. We demonstrate successful use of this substrate through all process steps and establish its capabilities via the fabrication of isolated resist features down to 6 {micro}m, feature aspect ratios up to 280 and electroformed nickel structures at heights of 190 to 1400 {micro}m. The minimum mask absorber thickness required for this new substrate ranges from 7 to 15 {micro}m depending on the resist thickness.

  2. Stress Voiding During Wafer Processing

    SciTech Connect

    Yost, F.G.

    1999-03-01

    Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

  3. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    SciTech Connect

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  4. Wafer level reliability for high-performance VLSI design

    NASA Technical Reports Server (NTRS)

    Root, Bryan J.; Seefeldt, James D.

    1987-01-01

    As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

  5. Methane production using resin-wafer electrodeionization

    DOEpatents

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  6. Formation and combustion characteristics of elephantgrass and energycane wafers

    NASA Astrophysics Data System (ADS)

    Mofleh, Mohamad I.

    Elephantgrass (Pennisetum purpureum Schum.) and energycane (Saccharum Spp.) are two cane type grasses. These are tall-growing perennial bunchgrasses that produce long hardened stems and grow in the tropics and subtropics. Traditionally, they have been used for forage and, in some regions, have been randomly burned on fields or disposed of uselessly. However, these plants have high dry matter yield and, thus, are excellent candidates as energy crops. Elephantgrass and energycane have been used for direct combustion in their loose form in large-scale applications. Several problems, many of which were attributed to their low bulk density, were encountered with using the materials. Consequently, this project was initiated to investigate the formation and combustion characteristics of the two materials in the form of small compact units called wafers. A hydraulic press that applied axial stresses on the material in four different dies was used. A load cell and a displacement transducer were utilized to measure the stresses and material detection. Wafer quality was evaluated using a tumbler built according to the American Society of Agricultural Engineers standards. In addition, a small stove was built to test wafer combustion. Thermocouples were used to measure temperatures during combustion. All the data gathered was transferred to a computer using a data acquisition system. It was found that the stress-deformation and stress-density relationships of elephantgrass and energycane were of exponential nature. Compaction energy required, which was calculated from the area under the force-deformation curves, ranged from 0.1 to 0.3% of their energy content. It was also found that wafer quality (durability) was mainly a function of wafer size and its final (relaxed) density in addition to material stem-to-leaf ratio and its crude protein content. Wafers possessed poor ignition quality but once ignited, they burned satisfactorily. The results indicated that sufficient and

  7. A model for reaction-assisted polymer dissolution in LIGA.

    SciTech Connect

    Larson, Richard S.

    2004-05-01

    A new chemically-oriented mathematical model for the development step of the LIGA process is presented. The key assumption is that the developer can react with the polymeric resist material in order to increase the solubility of the latter, thereby partially overcoming the need to reduce the polymer size. The ease with which this reaction takes place is assumed to be determined by the number of side chain scissions that occur during the x-ray exposure phase of the process. The dynamics of the dissolution process are simulated by solving the reaction-diffusion equations for this three-component, two-phase system, the three species being the unreacted and reacted polymers and the solvent. The mass fluxes are described by the multicomponent diffusion (Stefan-Maxwell) equations, and the chemical potentials are assumed to be given by the Flory-Huggins theory. Sample calculations are used to determine the dependence of the dissolution rate on key system parameters such as the reaction rate constant, polymer size, solid-phase diffusivity, and Flory-Huggins interaction parameters. A simple photochemistry model is used to relate the reaction rate constant and the polymer size to the absorbed x-ray dose. The resulting formula for the dissolution rate as a function of dose and temperature is ?t to an extensive experimental data base in order to evaluate a set of unknown global parameters. The results suggest that reaction-assisted dissolution is very important at low doses and low temperatures, the solubility of the unreacted polymer being too small for it to be dissolved at an appreciable rate. However, at high doses or at higher temperatures, the solubility is such that the reaction is no longer needed, and dissolution can take place via the conventional route. These results provide an explanation for the observed dependences of both the dissolution rate and its activation energy on the absorbed dose.

  8. A MEMS-Based Micro Biopsy Actuator for the Capsular Endoscope Using LiGA Process

    NASA Astrophysics Data System (ADS)

    Park, Sunkil; Koo, Kyo-In; Kim, Gil-Sub; Bang, Seoung Min; Song, Si Young; Chu, Chong Nam; Jeon, Doyoung; Cho, Dongil ``Dan''

    2007-01-01

    This paper presents a LiGA (German acronym for LIthografie, Galvanoformung, Abformung) based micro biopsy actuator for the capsular endoscope. The proposed fabricated actuator aims to extract sample tissues inside small gastric intestines, that cannot be reached by conventional biopsy. The actuator size is 10 mm in diameter and 1.8 mm in length. The mechanism is of a slider-crank type. The actuator consists of trigger, rotational module, and micro biopsy tool. The core components are fabricated using the LiGA process, for overcoming the limitations in accuracy of conventional precision machining.

  9. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  10. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  11. Local indicators of geocoding accuracy (LIGA): theory and application

    PubMed Central

    Jacquez, Geoffrey M; Rommel, Robert

    2009-01-01

    Background Although sources of positional error in geographic locations (e.g. geocoding error) used for describing and modeling spatial patterns are widely acknowledged, research on how such error impacts the statistical results has been limited. In this paper we explore techniques for quantifying the perturbability of spatial weights to different specifications of positional error. Results We find that a family of curves describes the relationship between perturbability and positional error, and use these curves to evaluate sensitivity of alternative spatial weight specifications to positional error both globally (when all locations are considered simultaneously) and locally (to identify those locations that would benefit most from increased geocoding accuracy). We evaluate the approach in simulation studies, and demonstrate it using a case-control study of bladder cancer in south-eastern Michigan. Conclusion Three results are significant. First, the shape of the probability distributions of positional error (e.g. circular, elliptical, cross) has little impact on the perturbability of spatial weights, which instead depends on the mean positional error. Second, our methodology allows researchers to evaluate the sensitivity of spatial statistics to positional accuracy for specific geographies. This has substantial practical implications since it makes possible routine sensitivity analysis of spatial statistics to positional error arising in geocoded street addresses, global positioning systems, LIDAR and other geographic data. Third, those locations with high perturbability (most sensitive to positional error) and high leverage (that contribute the most to the spatial weight being considered) will benefit the most from increased positional accuracy. These are rapidly identified using a new visualization tool we call the LIGA scatterplot. Herein lies a paradox for spatial analysis: For a given level of positional error increasing sample density to more accurately

  12. Yield-driven multi-project reticle design and wafer dicing

    NASA Astrophysics Data System (ADS)

    Kahng, Andrew B.; Mandoiu, Ion; Xu, Xu; Zelikovsky, Alex

    2005-11-01

    The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies has lead to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such low volume designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle design and wafer dicing introduce complexities not encountered in typical, single-project wafers. Recent works on wafer dicing adopt some assumptions to reduce the problem complexity. Although using one or more assumptions makes the problem solvable, the feasibility or performance of the solutions may be degraded. Also, the delay cost associated with schedule alignment was ignored in all previous works. In this paper we propose a general MPW flow including four main steps: (1) schedule-aware project partitioning (2) multi-project reticle floorplanning, (3) wafer shot-map definition, and (4) wafer dicing plan definition. Our project partitioner provides the best trade-off between the mask cost and delay cost. Our reticle floorplaner can automatically clone a design to better fit given production volumes. The round wafer shot-map definition step allows extracting functional dies from partially printed reticle images. Finally, our dicing planner allows multiple side-to-side dicing plans for different wafers and image rows/columns within a wafer. Experiments on industry testcases show that our methods outperform significantly not only previous methods in the literature, but also reticle floorplans manually designed by experienced engineers.

  13. Adhesive wafer bonding using a molded thick benzocyclobutene layer for wafer-level integration of MEMS and LSI

    NASA Astrophysics Data System (ADS)

    Makihata, M.; Tanaka, S.; Muroyama, M.; Matsuzaki, S.; Yamada, H.; Nakayama, T.; Yamaguchi, U.; Mima, K.; Nonomura, Y.; Fujiyoshi, M.; Esashi, M.

    2011-08-01

    This paper describes a wafer bonding process using a 50 µm thick benzocyclobutene (BCB) layer which has vias and metal electrodes. The vias were fabricated by molding BCB using a glass mold. During the molding, worm-like voids grew between BCB and the mold due to the shrinkage of polymerizing BCB. They were completely removed by subsequent reflowing in N2. After patterning Al on the reflowed BCB for the electrodes and via connections, bonding with a glass substrate was performed. Voidless bonding without damage in the vias and electrodes was achieved. Through the process, the control of the polymerization degree of BCB is important, and thus the polymerization degree was evaluated by Fourier transform infrared spectroscopy. The developed process is useful for the wafer-bonding-based integration of different devices, e.g. micro electro mechanical systems and large-scale integrated circuits.

  14. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Rhee, S. S.

    1979-01-01

    Several aspects of silicon wafer surface texturizing were studied. A low cost cleaning method that utilizes recycled Freon in an ultrasonic vapor degreaser to remove organic and inorganic contaminants from the surface of silicon wafers as received from silicon suppliers was investigated. The use of clean dry air and high throughout wafer batch drying techniques was shown to lower the cost of wafer drying. A two stage texturizing process was examined for suitability in large scale production. Also, an in-depth gettering study with the two stage texturizing process was performed for the enhancement of solar cell efficiency, minimization of current versus voltage curve dispersion, and improvement in process reproducibility. The 10% efficiency improvement goal was exceeded for the near term implementation of flat plate photovoltaic cost reduction.

  15. Harmonic versus LigaSure hemostasis technique in thyroid surgery: A meta-analysis

    PubMed Central

    Upadhyaya, Arun; Hu, Tianpeng; Meng, Zhaowei; Li, Xue; He, Xianghui; Tian, Weijun; Jia, Qiang; Tan, Jian

    2016-01-01

    Harmonic scalpel and LigaSure vessel sealing systems have been suggested as options for saving surgical time and reducing postoperative complications. The aim of the present meta-analysis was to compare surgical time, postoperative complications and other parameters between them in for the open thyroidectomy procedure. Studies were retrieved from MEDLINE, Cochrane Library, EMBASE and ISI Web of Science until December 2015. All the randomized controlled trials (RCTs) comparing Harmonic scalpel and LigaSure during open thyroidectomy were selected. Following data extraction, statistical analyses were performed. Among the 24 studies that were evaluated for eligibility, 7 RCTs with 981 patients were included. The Harmonic scalpel significantly reduced surgical time compared with LigaSure techniques (8.79 min; 95% confidence interval, −15.91 to −1.67; P=0.02). However, no significant difference was observed for the intraoperative blood loss, postoperative blood loss, duration of hospital stay, thyroid weight and serum calcium level postoperatively in either group. The present meta-analysis indicated superiority of Harmonic Scalpel only in terms of surgical time compared with LigaSure hemostasis techniques in open thyroid surgery. PMID:27446546

  16. Adhesive wafer bonding for MEMS applications

    NASA Astrophysics Data System (ADS)

    Dragoi, Viorel; Glinsner, Thomas; Mittendorfer, Gerald; Wieder, Bernhard; Lindner, Paul

    2003-04-01

    Low temperature wafer bonding is a powerful technique for MEMS/MOEMS devices fabrication and packaging. Among the low temperature processes adhesive bonding focuses a high technological interest. Adhesive wafer bonding is a bonding approach using an intermediate layer for bonding (e.g. glass, polymers, resists, polyimides). The main advantages of this method are: surface planarization, encapsulation of structures on the wafer surface, particle compensation and decrease of annealing temperature after bonding. This paper presents results on adhesive bonding using spin-on glass and Benzocyclobutene (BCB) from Dow Chemicals. The advantages of using adhesive bonding for MEMS applications will be illustrated be presenting a technology of fabricating GaAs-on-Si substrates (up to 150 mm diameter) and results on BCB bonding of Si wafers (200 mm diameter).

  17. Modelling deformation and fracture in confectionery wafers

    SciTech Connect

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  18. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  19. Total x-ray power measurements in the Sandia LIGA program.

    SciTech Connect

    Malinowski, Michael E. (Sandia National Laboratories, Livermore, CA); Ting, Aili (Sandia National Laboratories, Livermore, CA)

    2005-08-01

    Total X-ray power measurements using aluminum block calorimetry and other techniques were made at LIGA X-ray scanner synchrotron beamlines located at both the Advanced Light Source (ALS) and the Advanced Photon Source (APS). This block calorimetry work was initially performed on the LIGA beamline 3.3.1 of the ALS to provide experimental checks of predictions of the LEX-D (LIGA Exposure- Development) code for LIGA X-ray exposures, version 7.56, the version of the code in use at the time calorimetry was done. These experiments showed that it was necessary to use bend magnet field strengths and electron storage ring energies different from the default values originally in the code in order to obtain good agreement between experiment and theory. The results indicated that agreement between LEX-D predictions and experiment could be as good as 5% only if (1) more accurate values of the ring energies, (2) local values of the magnet field at the beamline source point, and (3) the NIST database for X-ray/materials interactions were used as code inputs. These local magnetic field value and accurate ring energies, together with NIST database, are now defaults in the newest release of LEX-D, version 7.61. Three dimensional simulations of the temperature distributions in the aluminum calorimeter block for a typical ALS power measurement were made with the ABAQUS code and found to be in good agreement with the experimental temperature data. As an application of the block calorimetry technique, the X-ray power exiting the mirror in place at a LIGA scanner located at the APS beamline 10 BM was measured with a calorimeter similar to the one used at the ALS. The overall results at the APS demonstrated the utility of calorimetry in helping to characterize the total X-ray power in LIGA beamlines. In addition to the block calorimetry work at the ALS and APS, a preliminary comparison of the use of heat flux sensors, photodiodes and modified beam calorimeters as total X-ray power

  20. Temperature Sensitivity Conferred by ligA Alleles from Psychrophilic Bacteria upon Substitution in Mesophilic Bacteria and a Yeast Species

    PubMed Central

    Pankowski, Jarosław A.; Puckett, Stephanie M.

    2016-01-01

    We have assembled a collection of 13 psychrophilic ligA alleles that can serve as genetic elements for engineering mesophiles to a temperature-sensitive (TS) phenotype. When these ligA alleles were substituted into Francisella novicida, they conferred a TS phenotype with restrictive temperatures between 33 and 39°C. When the F. novicida ligA hybrid strains were plated above their restrictive temperatures, eight of them generated temperature-resistant variants. For two alleles, the mutations that led to temperature resistance clustered near the 5′ end of the gene, and the mutations increased the predicted strength of the ribosome binding site at least 3-fold. Four F. novicida ligA hybrid strains generated no temperature-resistant variants at a detectable level. These results suggest that multiple mutations are needed to create temperature-resistant variants of these ligA gene products. One ligA allele was isolated from a Colwellia species that has a maximal growth temperature of 12°C, and this allele supported growth of F. novicida only as a hybrid between the psychrophilic and the F. novicida ligA genes. However, the full psychrophilic gene alone supported the growth of Salmonella enterica, imparting a restrictive temperature of 27°C. We also tested two ligA alleles from two Pseudoalteromonas strains for their ability to support the viability of a Saccharomyces cerevisiae strain that lacked its essential gene, CDC9, encoding an ATP-dependent DNA ligase. In both cases, the psychrophilic bacterial alleles supported yeast viability and their expression generated TS phenotypes. This collection of ligA alleles should be useful in engineering bacteria, and possibly eukaryotic microbes, to predictable TS phenotypes. PMID:26773080

  1. Temperature Sensitivity Conferred by ligA Alleles from Psychrophilic Bacteria upon Substitution in Mesophilic Bacteria and a Yeast Species.

    PubMed

    Pankowski, Jarosław A; Puckett, Stephanie M; Nano, Francis E

    2016-01-01

    We have assembled a collection of 13 psychrophilic ligA alleles that can serve as genetic elements for engineering mesophiles to a temperature-sensitive (TS) phenotype. When these ligA alleles were substituted into Francisella novicida, they conferred a TS phenotype with restrictive temperatures between 33 and 39°C. When the F. novicida ligA hybrid strains were plated above their restrictive temperatures, eight of them generated temperature-resistant variants. For two alleles, the mutations that led to temperature resistance clustered near the 5' end of the gene, and the mutations increased the predicted strength of the ribosome binding site at least 3-fold. Four F. novicida ligA hybrid strains generated no temperature-resistant variants at a detectable level. These results suggest that multiple mutations are needed to create temperature-resistant variants of these ligA gene products. One ligA allele was isolated from a Colwellia species that has a maximal growth temperature of 12°C, and this allele supported growth of F. novicida only as a hybrid between the psychrophilic and the F. novicida ligA genes. However, the full psychrophilic gene alone supported the growth of Salmonella enterica, imparting a restrictive temperature of 27°C. We also tested two ligA alleles from two Pseudoalteromonas strains for their ability to support the viability of a Saccharomyces cerevisiae strain that lacked its essential gene, CDC9, encoding an ATP-dependent DNA ligase. In both cases, the psychrophilic bacterial alleles supported yeast viability and their expression generated TS phenotypes. This collection of ligA alleles should be useful in engineering bacteria, and possibly eukaryotic microbes, to predictable TS phenotypes. PMID:26773080

  2. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  3. Analyzes Data from Semiconductor Wafers

    Energy Science and Technology Software Center (ESTSC)

    2002-07-23

    This program analyzes reflectance data from semiconductor wafers taken during the deposition or evolution of a thin film, typically via chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). It is used to determine the growth rate and optical constants of the deposited thin films using a virtual interface concept. Growth rates and optical constants of multiple-layer structures is possible by selecting appropriate sections in the reflectance vs time waveform. No prior information or estimatesmore » of growth rates and materials properties is required if an absolute reflectance waveform is used. If the optical constants of a thin film are known, then the growth rate may be extracted from a relative reflectance data set. The analysis is valid for either s or p polarized light at any incidence angle and wavelength. The analysis package is contained within an easy-to-use graphical user interface. The program is based on the algorighm described in the following two publications: W.G. Breiland and K.P. Killen, J. Appl. Phys. 78 (1995) 6726, and W. G. Breiland, H.Q. Hou, B.E. Hammons, and J.F. Klem, Proc. XXVIII SOTAPOCS Symp. Electrochem. Soc. San Diego, May 3-8, 1998. It relies on the fact that any multiple-layer system has a reflectance spectrum that is mathematically equivalent to a single-layer thin film on a virtual substrate. The program fits the thin film reflectance with five adjustable parameters: 1) growth rate, 2) real part of complex refractive index, 3) imaginary part of refractive index, 4) amplitude of virtual interface reflectance, 5) phase of virtual interface reflectance.« less

  4. Process Control By Automated In-Process Wafer Inspection

    NASA Astrophysics Data System (ADS)

    Harris, K. L.; Sandland, P.; Singleton, R. M.

    1984-06-01

    This is the introduction of new technology developed specifically for the inprocess pattern inspection and measurement of very large scale integrated (VLSI) wafers. There is a current need for significant improvements in pattern inspection instrumentation in order to tighten process control and achieve more competitive yields and therefore die costs. For the tedious and detailed task of pattern inspection and measurement, automation is the indicated solution. The future of computerized manufacturing requires, most fundamentally, the automation of the instrumentation and control function. In this paper, a system, designated the KLA 2020 Wafer Inspector, is described which incorporates the basic functions required to measure variations in the patterning process: linear and area dimensional measurements, registration error measurement, comparison for defects down to submicron in size. It is capable of inspecting in-process wafers in order to gain the most immediate process feedback. The speed with which it does each of these tests, less than a second, allows significant increases in sample size and therefore statistical control. It is this technology which will make computer-controlled photo processing possible.

  5. The Imaging Properties of a Silicon Wafer X-Ray Telescope

    NASA Technical Reports Server (NTRS)

    Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

    1994-01-01

    Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

  6. Porous solid ion exchange wafer for immobilizing biomolecules

    DOEpatents

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  7. Improvement of focus accuracy on processed wafer

    NASA Astrophysics Data System (ADS)

    Higashibata, Satomi; Komine, Nobuhiro; Fukuhara, Kazuya; Koike, Takashi; Kato, Yoshimitsu; Hashimoto, Kohji

    2013-04-01

    As feature size shrinkage in semiconductor device progress, process fluctuation, especially focus strongly affects device performance. Because focus control is an ongoing challenge in optical lithography, various studies have sought for improving focus monitoring and control. Focus errors are due to wafers, exposure tools, reticles, QCs, and so on. Few studies are performed to minimize the measurement errors of auto focus (AF) sensors of exposure tool, especially when processed wafers are exposed. With current focus measurement techniques, the phase shift grating (PSG) focus monitor 1) has been already proposed and its basic principle is that the intensity of the diffraction light of the mask pattern is made asymmetric by arranging a π/2 phase shift area on a reticle. The resist pattern exposed at the defocus position is shifted on the wafer and shifted pattern can be easily measured using an overlay inspection tool. However, it is difficult to measure shifted pattern for the pattern on the processed wafer because of interruptions caused by other patterns in the underlayer. In this paper, we therefore propose "SEM-PSG" technique, where the shift of the PSG resist mark is measured by employing critical dimension-scanning electron microscope (CD-SEM) to measure the focus error on the processed wafer. First, we evaluate the accuracy of SEM-PSG technique. Second, by applying the SEM-PSG technique and feeding the results back to the exposure, we evaluate the focus accuracy on processed wafers. By applying SEM-PSG feedback, the focus accuracy on the processed wafer was improved from 40 to 29 nm in 3σ.

  8. Design and simulation of non-resonant 1-DOF drive mode and anchored 2-DOF sense mode gyroscope for implementation using UV-LIGA process

    NASA Astrophysics Data System (ADS)

    Verma, Payal; Gopal, Ram; Butt, M. A.; Khonina, Svetlana N.; Skidanov, Roman V.

    2016-03-01

    This paper presents the design and simulation of a 3-DOF (degree-of-freedom) MEMS gyroscope structure with 1-DOF drive mode and anchored 2-DOF sense mode, based on UV-LIGA technology. The 3-DOF system has the drive resonance located in the flat zone between the two sense resonances. It is an inherently robust structure and offers a high sense frequency band width and high gain without much scaling down the mass on which the sensing comb fingers are attached and it is also immune to process imperfections and environmental conditions. The design is optimized to be compatible with the UV-LIGA process, having 9 μm thick nickel as structural layer. The electrostatic gap between the drive comb fingers is 4 μm and sense comb fingers gap are 4 μm/12 μm. The damping effect is considered by assuming the flexures and the proof mass suspended about 6 μm over the substrate. Accordingly, mask is designed in L-Edit software.

  9. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

  10. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y.; James, Ralph B.

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  11. Wafer plane inspection evaluated for photomask production

    NASA Astrophysics Data System (ADS)

    Gallagher, Emily; Badger, Karen; Lawliss, Mark; Kodera, Yutaka; Azpiroz, Jaione Tirapu; Pang, Song; Zhang, Hongqin; Eugenieva, Eugenia; Clifford, Chris; Goonesekera, Arosha; Tian, Yibin

    2008-10-01

    Wafer Plane Inspection (WPI) is a novel approach to inspection, developed to enable high inspectability on fragmented mask features at the optimal defect sensitivity. It builds on well-established high resolution inspection capabilities to complement existing manufacturing methods. The production of defect-free photomasks is practical today only because of informed decisions on the impact of defects identified. The defect size, location and its measured printing impact can dictate that a mask is perfectly good for lithographic purposes. This inspection - verification - repair loop is timeconsuming and is predicated on the fact that detectable photomask defects do not always resolve or matter on wafer. This paper will introduce and evaluate an alternative approach that moves the mask inspection to the wafer plane. WPI uses a high NA inspection of the mask to construct a physical mask model. This mask model is used to create the mask image in the wafer plane. Finally, a threshold model is applied to enhance sensitivity to printing defects. WPI essentially eliminates the non-printing inspection stops and relaxes some of the pattern restrictions currently placed on incoming photomask designs. This paper outlines the WPI technology and explores its application to patterns and substrates representative of 32nm designs. The implications of deploying Wafer Plane Inspection will be discussed.

  12. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  13. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  14. Laser furnace and method for zone refining of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

    1988-01-01

    A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

  15. Diamond-like nanocomposite coatings for LIGA-fabricated nickel alloy parts.

    SciTech Connect

    Prasad, Somuri V.; Scharf, Thomas W.

    2005-03-01

    A commercial plasma enhanced chemical vapor deposition (PECVD) technique with planetary substrate rotation was used to apply a thin (200-400 nm thick) conformal diamond-like carbon (DLC) coating (known as a diamond-like nanocomposite (DLN)) on LIGA fabricated Ni-Mn alloy parts. The PECVD technique is known to overcome the drawbacks associated with the line-of-sight nature of physical vapor deposition (PVD) and substrate heating inherent with traditional chemical vapor deposition (CVD). The purpose of the present study is to characterize the coverage, adhesion, and tribological (friction and wear) behavior of DLN coatings applied to planar and sidewall surfaces of small featured LIGA Ni-Mn fabricated parts, e.g. 280 {micro}m thick sidewalls. Friction and wear tests were performed in dry nitrogen, dry air, and air with 50% RH at Hertzian contact pressures ranging from 0.3 to 0.6 GPa. The friction coefficient of bare Ni-Mn alloy was determined to be 0.9. In contrast, low friction coefficients ({approx}0.02 in dry nitrogen and {approx}0.2 in 50% RH air) and minimal amount of wear were exhibited for the DLN coated LIGA Ni-Mn alloy parts and test coupons. This behavior was due to the ability of the coating to transfer to the rubbing counterface providing low interfacial shear at the sliding contact; resultantly, coating one surface was adequate for low friction and wear. In addition, a 30 nm thick titanium bond layer was determined to be necessary for good adhesion of DLN coating to Ni-Mn alloy substrates. Raman spectroscopy and cross-sectional SEM with energy dispersive x-ray analysis revealed that the DLN coatings deposited by the PECVD with planetary substrate rotation covered both the planar and sidewall surfaces of LIGA fabricated parts, as well as narrow holes of 300 {micro}m (0.012 inch) diameter.

  16. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu

  17. Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

    NASA Astrophysics Data System (ADS)

    Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

    2001-11-01

    The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

  18. Effect of wafer geometry on lithography chucking processes

    NASA Astrophysics Data System (ADS)

    Turner, Kevin T.; Sinha, Jaydeep K.

    2015-03-01

    Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

  19. Apparatus for edge etching of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Casajus, A.

    1986-01-01

    A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

  20. Methanol Steam Reformer on a Silicon Wafer

    SciTech Connect

    Park, H; Malen, J; Piggott, T; Morse, J; Sopchak, D; Greif, R; Grigoropoulos, C; Havstad, M; Upadhye, R

    2004-04-15

    A study of the reforming rates, heat transfer and flow through a methanol reforming catalytic microreactor fabricated on a silicon wafer are presented. Comparison of computed and measured conversion efficiencies are shown to be favorable. Concepts for insulating the reactor while maintaining small overall size and starting operation from ambient temperature are analyzed.

  1. Wafer capping of MEMS with fab-friendly metals

    NASA Astrophysics Data System (ADS)

    Martin, Jack

    2007-01-01

    Inertial MEMS (Micro Electro Mechanical System) sensors are normally sealed in hermetic enclosures. Some are assembled in hermetic packages but wafer level packaging has become much more important in recent years. Anodic bonding can be used to achieve wafer level seals between silicon and glass but most suppliers of inertial sensors screen print glass frit onto silicon cap wafers. After removing the organic vehicle, these patterned cap wafers are sealed to device wafer prior to wafer singulation and plastic packaging. Anodic and glass frit bonding are both cost-effective. However, they impose size, quality and performance limitations. Wafer level sealing with a metal removes some of these limitations but introduces other concerns. This paper will review the current wafer level hermetic processes followed by a description of a thermocompression metal seal technology that is compatible with IC fabrication.

  2. Wafer plane inspection for advanced reticle defects

    NASA Astrophysics Data System (ADS)

    Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

    2008-05-01

    Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

  3. Innovative optical alignment technique for CMP wafers

    NASA Astrophysics Data System (ADS)

    Sugaya, Ayako; Kanaya, Yuho; Nakajima, Shinichi; Nagayama, Tadashi; Shiraishi, Naomasa

    2002-07-01

    Detecting position of the wafers such as after CMP process is critical theme of current and forthcoming IC manufacturing. The alignment system must be with high accuracy for any process. To satisfy such requirements, we have studied and analyzed factors that have made alignment difficult. From the result of the studies, we have developed new optical alignment techniques which improve the accuracy of FIA (alignment sensor of Nikon's NSR series) and examined them. The approaches are optimizing the focus position, developing an advanced algorithm for position detection, and selecting a suitable mark design. For experiment, we have developed the special wafers that make it possible to evaluate the influence of CMP processes. The experimental results show that the overlay errors decrease dramatically with the new alignment techniques. FIA with these new techniques will be much accurate and suitable alignment sensor for CMP and other processes of future generation ULSI production.

  4. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  5. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.; St. Martin, Edward; Arora, Michelle; de la Garza, Linda

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  6. TOPICAL REVIEW: Wafer level packaging of MEMS

    NASA Astrophysics Data System (ADS)

    Esashi, Masayoshi

    2008-07-01

    Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass-Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review.

  7. Precipitating Chromium Impurities in Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Salama, A. M.

    1982-01-01

    Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

  8. Wafer plane inspection with soft resist thresholding

    NASA Astrophysics Data System (ADS)

    Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

    2008-10-01

    Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

  9. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  10. Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Shi, Fang Frank

    Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances. Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported. Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure

  11. Mask-to-wafer alignment system

    DOEpatents

    Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

    2003-11-04

    A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

  12. Wafer level test solutions for IR sensors

    NASA Astrophysics Data System (ADS)

    Giessmann, Sebastian; Werner, Frank-Michael

    2014-05-01

    Wafer probers provide an established platform for performing electrical measurements at wafer level for CMOS and similar process technologies. For testing IR sensors, the requirements are beyond the standard prober capabilities. This presentation will give an overview about state of the art IR sensor probing systems reaching from flexible engineering solutions to automated production needs. Cooled sensors typically need to be tested at a target temperature below 80 K. Not only is the device temperature important but also the surrounding environment is required to prevent background radiation from reaching the device under test. To achieve that, a cryogenic shield is protecting the movable chuck. By operating that shield to attract residual gases inside the chamber, a completely contamination-free test environment can be guaranteed. The use of special black coatings are furthermore supporting the removal of stray light. Typically, probe card needles are operating at ambient (room) temperature when connecting to the wafer. To avoid the entrance of heat, which can result in distorted measurements, the probe card is fully embedded into the cryogenic shield. A shutter system, located above the probe field, is designed to switch between the microscope view to align the sensor under the needles and the test relevant setup. This includes a completely closed position to take dark current measurements. Another position holds a possible filter glass with the required aperture opening. The necessary infrared sources to stimulate the device are located above.

  13. Wafer weak point detection based on aerial images or WLCD

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Philipp, Peter; Litt, Lloyd C.; Ackmann, Paul; Crell, Christian; Chen, Norman

    2015-10-01

    Aerial image measurement is a key technique for model based optical proximity correction (OPC) verification. Actual aerial images obtained by AIMS (aerial image measurement system) or WLCD (wafer level critical dimension) can detect printed wafer weak point structures in advance of wafer exposure and defect inspection. Normally, the potential wafer weak points are determined based on optical rule check (ORC) simulation in advance. However, the correlation to real wafer weak points is often not perfect due to the contribution of mask three dimension (M3D) effects, actual mask errors, and scanner lens effects. If the design weak points can accurately be detected in advance, it will reduce the wafer fab cost and improve cycle time. WLCD or AIMS tools are able to measure the aerial images CD and bossung curve through focus window. However, it is difficult to detect the wafer weak point in advance without defining selection criteria. In this study, wafer weak points sensitive to mask mean-to-nominal values are characterized for a process with very high MEEF (normally more than 4). Aerial image CD uses fixed threshold to detect the wafer weak points. By using WLCD through threshold and focus window, the efficiency of wafer weak point detection is also demonstrated. A novel method using contrast range evaluation is shown in the paper. Use of the slope of aerial images for more accurate detection of the wafer weak points using WLCD is also discussed. The contrast range can also be used to detect the wafer weak points in advance. Further, since the mean to nominal of the reticle contributes to the effective contrast range in a high MEEF area this work shows that control of the mask error is critical for high MEEF layers such as poly, active and metal layers. Wafer process based weak points that cannot be detected by wafer lithography CD or WLCD will be discussed.

  14. Multi-dimensional multi-species modeling of transient electrodeposition in LIGA microfabrication.

    SciTech Connect

    Evans, Gregory Herbert; Chen, Ken Shuang

    2004-06-01

    This report documents the efforts and accomplishments of the LIGA electrodeposition modeling project which was headed by the ASCI Materials and Physics Modeling Program. A multi-dimensional framework based on GOMA was developed for modeling time-dependent diffusion and migration of multiple charged species in a dilute electrolyte solution with reduction electro-chemical reactions on moving deposition surfaces. By combining the species mass conservation equations with the electroneutrality constraint, a Poisson equation that explicitly describes the electrolyte potential was derived. The set of coupled, nonlinear equations governing species transport, electric potential, velocity, hydrodynamic pressure, and mesh motion were solved in GOMA, using the finite-element method and a fully-coupled implicit solution scheme via Newton's method. By treating the finite-element mesh as a pseudo solid with an arbitrary Lagrangian-Eulerian formulation and by repeatedly performing re-meshing with CUBIT and re-mapping with MAPVAR, the moving deposition surfaces were tracked explicitly from start of deposition until the trenches were filled with metal, thus enabling the computation of local current densities that potentially influence the microstructure and frictional/mechanical properties of the deposit. The multi-dimensional, multi-species, transient computational framework was demonstrated in case studies of two-dimensional nickel electrodeposition in single and multiple trenches, without and with bath stirring or forced flow. Effects of buoyancy-induced convection on deposition were also investigated. To further illustrate its utility, the framework was employed to simulate deposition in microscreen-based LIGA molds. Lastly, future needs for modeling LIGA electrodeposition are discussed.

  15. Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size

    NASA Astrophysics Data System (ADS)

    Kim, Hee Yeoun; Yang, Chungmo; Park, Jae Hong; Jung, Ho; Kim, Taehyun; Kim, Kyung Tae; Lim, Sung Kyu; Lee, Sang Woo; Mitchell, Jay; Hwang, Wook Joong; Lee, Kwyro

    2013-06-01

    For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.

  16. Equipment for On-Wafer Testing From 220 to 325 GHz

    NASA Technical Reports Server (NTRS)

    Samoska, Lorene; Peralta, Alejandro; Dawson, Douglas; Lee, Karen; Boll, Greg; Oleson, Chuck

    2006-01-01

    A system of electronic instrumentation, constituting the equivalent of a two-port vector network analyzer, has been developed for use in on-wafer measurement of key electrical characteristics of semiconductor devices at frequencies from 220 to 325 GHz. A prior system designed according to similar principles was reported in Equipment for On-Wafer Testing at Frequencies Up to 220 GHz (NPO-20760), NASA Tech Briefs, Vol. 25, No. 11 (November 2001), page 42. As one would expect, a major source of difficulty in progressing to the present higher-frequency-range system was the need for greater mechanical precision as wavelengths shorten into the millimeter range, approaching the scale of mechanical tolerances of prior systems. The system (see figure) includes both commercial off-the-shelf and custom equipment. As in the system of the cited prior article, the equipment includes test sets that are extended versions of commercial network analyzers that function in a lower frequency range. The extension to the higher frequency range is accomplished by use of custom frequency-extension modules that contain frequency multipliers and harmonic mixers. On-wafer measurement is made possible by waveguide wafer probes that were custom designed and built for this wavelength range, plus an on-wafer calibration substrate designed for use with these probes. In this case, the calibration substrate was specially fabricated by laser milling. The system was used to make the first on-wafer measurements of a semiconductor device in the frequency range from 220 to 320 GHz. Some of the measurement results showed that the device had gain.

  17. Compliant membranes improve resolution in full-wafer micro/nanostencil lithography.

    PubMed

    Sidler, Katrin; Villanueva, Luis G; Vazquez-Mena, Oscar; Savu, Veronica; Brugger, Juergen

    2012-02-01

    This work reports on a considerable resolution improvement of micro/nanostencil lithography when applied on full-wafer scale by using compliant membranes to reduce gap-induced pattern blurring. Silicon nitride (SiN) membranes are mechanically decoupled from a rigid silicon (Si) frame by means of four compliant, protruding cantilevers. When pressing the stencil into contact with a surface to be patterned, the membranes thus adapt to the surface independently and reduce the gap between the membrane and the substrate even over large, uneven surfaces. Finite element modeling (FEM) simulations show that compliant membranes can deflect vertically 40 μm which is a typical maximal non-planarity observed in standard Si wafers, due to polishing. Microapertures in the stencil membrane are defined by UV lithography and nanoapertures, down to 200 nm in diameter, using focused ion beam (FIB). A thin aluminium (Al) layer is deposited through both compliant and non-compliant membranes on a Si wafer, for comparison. The blurring in the case of compliant membranes is up to 95% reduced on full-wafer scale compared to standard (non-compliant) membranes. PMID:22170588

  18. Compliant membranes improve resolution in full-wafer micro/nanostencil lithography

    NASA Astrophysics Data System (ADS)

    Sidler, Katrin; Villanueva, Luis G.; Vazquez-Mena, Oscar; Savu, Veronica; Brugger, Juergen

    2012-01-01

    This work reports on a considerable resolution improvement of micro/nanostencil lithography when applied on full-wafer scale by using compliant membranes to reduce gap-induced pattern blurring. Silicon nitride (SiN) membranes are mechanically decoupled from a rigid silicon (Si) frame by means of four compliant, protruding cantilevers. When pressing the stencil into contact with a surface to be patterned, the membranes thus adapt to the surface independently and reduce the gap between the membrane and the substrate even over large, uneven surfaces. Finite element modeling (FEM) simulations show that compliant membranes can deflect vertically 40 μm which is a typical maximal non-planarity observed in standard Si wafers, due to polishing. Microapertures in the stencil membrane are defined by UV lithography and nanoapertures, down to 200 nm in diameter, using focused ion beam (FIB). A thin aluminium (Al) layer is deposited through both compliant and non-compliant membranes on a Si wafer, for comparison. The blurring in the case of compliant membranes is up to 95% reduced on full-wafer scale compared to standard (non-compliant) membranes.

  19. Design of electrostatically levitated micromachined rotational gyroscope based on UV-LIGA technology

    NASA Astrophysics Data System (ADS)

    Cui, Feng; Chen, Wenyuan; Su, Yufeng; Zhang, Weiping; Zhao, Xiaolin

    2004-12-01

    The prevailing micromachined vibratory gyroscope typically has a proof mass connected to the substrate by a mechanical suspension system, which makes it face a tough challenge to achieve tactical or inertial grade performance levels. With a levitated rotor as the proof mass, a micromachined rotational gyroscope will potentially have higher performance than vibratory gyroscope. Besides working as a moment rebalance dual-axis gyroscope, the micromachined rotational gyroscope based on a levitated rotor can simultaneously work as a force balance tri-axis accelerometer. Micromachined rotational gyroscope based on an electrostatically levitated silicon micromachined rotor has been notably developed. In this paper, factors in designing a rotational gyro/accelerometer based on an electrostatically levitated disc-like rotor, including gyroscopic action of micro rotor, methods of stable levitation, micro displacement detection and control, rotation drive and speed control, vacuum packaging and microfabrication, are comprehensively considered. Hence a design of rotational gyro/accelerometer with an electroforming nickel rotor employing low cost UV-LIGA technology is presented. In this design, a wheel-like flat rotor is proposed and its basic dimensions, diameter and thickness, are estimated according to the required loading capability. Finally, its micromachining methods based on UV-LIGA technology and assembly technology are discussed.

  20. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu

  1. Electrooptic shutter devices utilizing PLZT ceramic wafers

    SciTech Connect

    Thornton, A.L.

    1981-01-01

    Optical transparency was achieved in lead zirconate-titanate ferroelectric ceramics by substituting moderate amounts of the element lanthanum (8 to 12%) for lead. These compositions exhibit the quadratic (Kerr) electrooptic effect. The excellent optical qualities of these materials (designated PLZT) has permitted the practical utilization of their electrooptic properties in a number of devices. All of these devices utilize the classic Kerr cell arrangement. A PLZT wafer with optical axis oriented at 45/sup 0/ with respect to the axes of polarization is sandwiched between crossed polarizers. Application of an electric field via an interdigital array of electrodes on opposing wafer surfaces forces the PLZT material into a tetragonal state with the resulting induced birefringence proportional to the square of the applied electric field. Hence, the electrooptic wafer provides a retardation of light so that a component is passed by the second crossed polarizer to achieve an ON or open state. Maximum transmission is achieved when the retardation is half-wave. Shutter devices developed by Sandia and those in continuing development are described with respect to operational characteristics and physical configuration. The devices range in size from very small apertures of 50 ..mu..m x 2 mm with center-to-center repeat dimensions of 125 ..mu..m - to very large - apertures of 15.2 cm in single pieces and mosaics with apertures of 15.2 cm x 20.3 cm. Major efforts have centered on shutter development for the protection of aircrew from eye-damaging weapon effects. Other devices are also described which: provide eye protection for welders, protect vidicon tubes, function as page composers for holographic memories serve as large aperture photographic shutters, provide stereoscopic three-dimensional TV displays, and serve as data links in a fiber-optic transmission path.

  2. Super-flat wafer chucks: from simulation and testing to a complete 300mm wafer chuck with low wafer deformation between pins

    NASA Astrophysics Data System (ADS)

    Müller, Renate; Afanasiev, Kanstantin; Ziemann, Marcel; Schmidt, Volker

    2014-04-01

    Berliner Glas is a privately owned, mid-sized manufacturer of precision opto-mechanics in Germany. One specialty of Berliner Glas is the design and production of high performance vacuum and electrostatic wafer chucks. Driven by the need of lithography and inspection for smaller overlay values, we pursue the production of an ideally flat wafer chuck. An ideally flat wafer chuck holds a wafer with a completely flat backside and without lateral distortion within the wafer surface. Key parameters in influencing the wafer chucks effective flatness are thermal performance and thermal management, roughness of the surface, choice of materials and the contact area between wafer and wafer chuck. In this presentation we would like to focus on the contact area. Usually this is decreased as much as possible to avoid sticking effects and the chance of trapped particles between the chuck surface and the backside of the wafer. This can be realized with a pin structure on the chuck surface. Making the pins smaller and moving pins further apart from each other makes the contact area ever smaller but also adds new challenges to achieve a flat and undistorted wafer on the chuck. We would like to address methods of designing and evaluating such a pin structure. This involves not only the capability to simulate the ideal pattern of pins on the chuck's surface, for which we will present 2D and 3D simulation results. As well, we would like to share first results of our functional models. Finally, measurement capability has to be ensured, which means improving and further development of Fizeau flatness test interferometers.

  3. Photoluminescence method of testing double heterostructure wafers

    SciTech Connect

    Besomi, P.R.; Wilt, D.P.

    1984-04-10

    Under photoluminescence (PL) excitation, the lateral spreading of photo-excited carriers can suppress the photoluminescence signal from double heterostructure (DH) wafers containing a p-n junction. In any DH with a p-n junction in the active layer, PL is suppressed if the power of the excitation source does not exceed a threshold value. This effect can be advantageously used for a nondestructive optical determination of the top cladding layer sheet conductance as well as p-n junction misplacement, important parameters for injection lasers and LEDs.

  4. Investigation of intrinsic gettering for germanium doped Czochralski silicon wafer

    NASA Astrophysics Data System (ADS)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Wang, Weiyan; Zeng, Yuheng; Que, Duanlin

    2007-06-01

    The intrinsic gettering (IG) effects in a germanium-doped Czochralski (GCz) silicon wafer have been investigated through a processing simulation of dynamic random access memory making and an evaluation on IG capability for copper contamination. It has been suggested that both the good quality defect-free denuded zones (DZs) and the high-density bulk microdefect (BMD) regions could be generated in GCz silicon wafer during device fabrication. Meanwhile, it was also indicated that the tiny oxygen precipitates were hardly presented in DZs of silicon wafer with the germanium doping. Furthermore, it was found in GCz silicon wafer that the BMDs were higher in density but smaller in size in contrast to that in conventional Cz silicon wafer. Promoted IG capability for metallic contamination was therefore induced in the germanium-doped Cz silicon wafer. A mechanism of the germanium doping on oxygen precipitation in Cz silicon was discussed, which was based on the hypothesis of germanium-related complexes.

  5. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  6. Dominant factors of the laser gettering of silicon wafers

    SciTech Connect

    Bokhan, Yu. I. E-mail: yuibokhan@gmail.com; Kamenkov, V. S.; Tolochko, N. K.

    2015-02-15

    The laser gettering of silicon wafers is experimentally investigated. The typical gettering parameters are considered. The surfaces of laser-treated silicon wafers are investigated by microscopy. When studying the effect of laser radiation on silicon wafers during gettering, a group of factors determining the conditions of interaction between the laser beam and silicon-wafer surface and affecting the final result of treatment are selected. The main factors determining the gettering efficiency are revealed. Limitations on the desired value of the getter-layer capacity on surfaces with insufficiently high cleanness (for example, ground or matte) are established.

  7. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  8. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M.

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  9. The impact of wafering on organic and inorganic surface contaminations

    NASA Astrophysics Data System (ADS)

    Meyer, S.; Wahl, S.; Timmel, S.; Köpge, R.; Jang, B.-Y.

    2016-08-01

    Beside the silicon feedstock material, the crystallization process and the cell processing itself, the wafer sawing process can strongly determine the final solar cell quality. Especially surface contamination is introduced in this process step because impurities from sawing meet with a virgin silicon surface which is highly reactive until the oxide layer is formed. In this paper we quantitatively analysed both, the organic and inorganic contamination on wafer surfaces and show that changes of process parameters during wafering may cause dramatic changes in surface purity. We present powerful techniques for the monitoring of wafer surface quality which is essential for the production of high efficiency and high quality solar cells.

  10. LIGA20, a lyso derivative of ganglioside GM1, given orally after cortical thrombosis reduces infarct size and associated cognition deficit.

    PubMed Central

    Kharlamov, A; Zivkovic, I; Polo, A; Armstrong, D M; Costa, E; Guidotti, A

    1994-01-01

    A bilateral photochemically induced thrombotic lesion of rat sensorimotor cortex (approximately 3 mm in diameter and 25 mm3 in volume) is associated with a persistent cognition (learning and memory) deficit, which was evaluated with water maze tasks. The N-dichloroacetylsphingosine derivative of lysoGM1 (LIGA20) administered after the lesion either i.v. or per or reduces the infarct size by 30-40% and attenuates the associated cognition deficits, presumably by limiting the extent of damage of neurons at risk located in the surroundings of the infarcted core (i.e., area penumbra). The LIGA20 protection is dose and time dependent. Maximal protection is afforded by a single dose of LIGA20 of 34 mumol/kg i.v. 1 hr after lesion or by a dose of 270 mumol/kg per os when administered 1 hr and 24 hr after the lesion. The protective effect of LIGA20 can be observed when the drug is administered i.v. up to 6 hr after the lesion. The protective efficacy of the oral administration of LIGA20 is related to its physiochemical properties, which, unlike those of GM1, allow absorption from the gastrointestinal tract. LIGA20 given orally reaches the brain promptly and rapidly inserts into the neuronal membranes. Here, by an unknown molecular mechanism, LIGA20 selectively reduces the pathological amplification of Ca2+ signaling elicited by persistent stimulation of ionotropic glutamate receptors in the area penumbra. PMID:8022776

  11. Strategy For Yield Control And Enhancement In VLSI Wafer Manufacturing

    NASA Astrophysics Data System (ADS)

    Neilson, B.; Rickey, D.; Bane, R. P.

    1988-01-01

    In most fully utilized integrated circuit (IC) production facilities, profit is very closely linked with yield. In even the most controlled manufacturing environments, defects due to foreign material are a still major contributor to yield loss. Ideally, an IC manufacturer will have ample engineering resources to address any problem that arises. In the real world, staffing limitations require that some tasks must be left undone and potential benefits left unrealized. Therefore, it is important to prioritize problems in a manner that will give the maximum benefit to the manufacturer. When offered a smorgasbord of problems to solve, most people (engineers included) will start with what is most interesting or the most comfortable to work on. By providing a system that accurately predicts the impact of a wide variety of defect types, a rational method of prioritizing engineering effort can be made. To that effect, a program was developed to determine and rank the major yield detractors in a mixed analog/digital FET manufacturing line. The two classical methods of determining yield detractors are chip failure analysis and defect monitoring on drop in test die. Both of these methods have short comings: 1) Chip failure analysis is painstaking and very time consuming. As a result, the sample size is very small. 2) Drop in test die are usually designed for device parametric analysis rather than defect analysis. To provide enough wafer real estate to do meaningful defect analysis would render the wafer worthless for production. To avoid these problems, a defect monitor was designed that provided enough area to detect defects at the same rate or better than the NMOS product die whose yield was to be optimized. The defect monitor was comprehensive and electrically testable using such equipment as the Prometrix LM25 and other digital testers. This enabled the quick accumulation of data which could be handled statistically and mapped individually. By scaling the defect densities

  12. Mask qualification strategies in a wafer fab

    NASA Astrophysics Data System (ADS)

    Jaehnert, Carmen; Kunowski, Angela

    2007-02-01

    Having consistent high quality photo masks is one of the key factors in lithography in the wafer fab. Combined with stable exposure- and resist processes, it ensures yield increases in production and fast learning cycles for technology development and design evaluation. Preventive controlling of incoming masks and quality monitoring while using the mask in production is essential for the fab to avoid yield loss or technical problems caused by mask issues, which eventually result in delivery problems to the customer. In this paper an overview of the procedures used for mask qualification and production release, for both logic and DRAM, at Infineon Dresden is presented. Incoming qualification procedures, such as specification checks, incoming inspection, and inline litho process window evaluation, are described here. Pinching and electrical tests, including compatibility tests for mask copies for high volume products on optimized litho processes, are also explained. To avoid mask degradation over lifetime, re-inspection checks are done for re-qualification while using the mask in production. The necessity of mask incoming inspection and re-qualification, due to the repeater printing from either the processing defects of the original mask or degrading defects of being used in the fab (i.e. haze, ESD, and moving particles, etc.), is demonstrated. The need and impact of tight mask specifications, such as CD uniformity signatures and corresponding electrical results, are shown with examples of mask-wafer CD correlation.

  13. Diamond MEMS: wafer scale processing, devices, and technology insertion

    NASA Astrophysics Data System (ADS)

    Carlisle, J. A.

    2009-05-01

    Diamond has long held the promise of revolutionary new devices: impervious chemical barriers, smooth and reliable microscopic machines, and tough mechanical tools. Yet it's been an outsider. Laboratories have been effectively growing diamond crystals for at least 25 years, but the jump to market viability has always been blocked by the expense of diamond production and inability to integrate with other materials. Advances in chemical vapor deposition (CVD) processes have given rise to a hierarchy of carbon films ranging from diamond-like carbon (DLC) to vapor-deposited diamond coatings, however. All have pros and cons based on structure and cost, but they all share some of diamond's heralded attributes. The best performer, in theory, is the purest form of diamond film possible, one absent of graphitic phases. Such a material would capture the extreme hardness, high Young's modulus and chemical inertness of natural diamond. Advanced Diamond Technologies Inc., Romeoville, Ill., is the first company to develop a distinct chemical process to create a marketable phase-pure diamond film. The material, called UNCD® (for ultrananocrystalline diamond), features grain sizes from 3 to 300 nm in size, and layers just 1 to 2 microns thick. With significant advantages over other thin films, UNCD is designed to be inexpensive enough for use in atomic force microscopy (AFM) probes, microelectromechanical machines (MEMS), cell phone circuitry, radio frequency devices, and even biosensors.

  14. Physiological Osmotic Induction of Leptospira interrogans Adhesion: LigA and LigB Bind Extracellular Matrix Proteins and Fibrinogen▿

    PubMed Central

    Choy, Henry A.; Kelley, Melissa M.; Chen, Tammy L.; Møller, Annette K.; Matsunaga, James; Haake, David A.

    2007-01-01

    Transmission of leptospirosis occurs through contact of mucous membranes and abraded skin with freshwater contaminated by pathogenic Leptospira spp. Exposure to physiological osmolarity induces leptospires to express high levels of the Lig surface proteins containing imperfect immunoglobulin-like repeats that are shared or differ between LigA and LigB. We report that osmotic induction of Lig is accompanied by 1.6- to 2.5-fold increases in leptospiral adhesion to immobilized extracellular matrix and plasma proteins, including collagens I and IV, laminin, and especially fibronectin and fibrinogen. Recombinant LigA-unique and LigB-unique repeat proteins bind to these same host ligands. We found that the avidity of LigB in binding fibronectin is comparable to that of the Staphylococcus aureus FnBPA D repeats. Both LigA- and LigB-unique repeats interact with the amino-terminal fibrin- and gelatin-binding domains of fibronectin, which are also recognized by fibronectin-binding proteins mediating the adhesion of other microbial pathogens. In contrast, repeats common to both LigA and LigB do not bind these host proteins, and nonrepeat sequences in the carboxy-terminal domain of LigB show only weak interaction with fibronectin and fibrinogen. A functional role for the binding activity of LigA and LigB is suggested by the ability of the recombinants to inhibit leptospiral adhesion to fibronectin by 28% and 21%, respectively. The binding of LigA and LigB to multiple ligands present in different tissues suggests that these adhesins may be involved in the initial colonization and dissemination stages of leptospirosis. The characterization of the Lig adhesin function should aid the design of Lig-based vaccines and serodiagnostic tests. PMID:17296754

  15. Temperature rise of the mask-resist assembly during LIGA exposure.

    SciTech Connect

    Ting, Aili

    2004-11-01

    Deep X-ray lithography on PMMA resist is used in the LIGA process. The resist is exposed to synchrotron X-rays through a patterned mask and then is developed in a liquid developer to make high aspect ratio microstructures. The limitations in dimensional accuracies of the LIGA generated microstructure originate from many sources, including synchrotron and X-ray physics, thermal and mechanical properties of mask and resist, and from the kinetics of the developer. This work addresses the thermal analysis and temperature rise of the mask-resist assembly during exposure in air at the Advanced Light Source (ALS) synchrotron. The concern is that dimensional errors generated at the mask and the resist due to thermal expansion will lower the accuracy of the lithography. We have developed a three-dimensional finite-element model of the mask and resist assembly that includes a mask with absorber, a resist with substrate, three metal holders, and a water-cooling block. We employed the LIGA exposure-development software LEX-D to calculate volumetric heat sources generated in the assembly by X-ray absorption and the commercial software ABAQUS to calculate heat transfer including thermal conduction inside the assembly, natural and forced convection, and thermal radiation. at assembly outer and/or inner surfaces. The calculations of assembly maximum temperature. have been compared with temperature measurements conducted at ALS. In some of these experiments, additional cooling of the assembly was produced by forced nitrogen flow ('nitrogen jets') directed at the mask surface. The temperature rise in the silicon mask and the mask holder comes directly from the X-ray absorption, but nitrogen jets carry away a significant portion of heat energy from the mask surface, while natural convection carries away negligibly small amounts energy from the holder. The temperature rise in PMMA resist is mainly from heat conducted from the silicon substrate backward to the resist and from the inner

  16. High-throughput automatic defect review for 300mm blank wafers with atomic force microscope

    NASA Astrophysics Data System (ADS)

    Zandiatashbar, Ardavan; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

    2015-03-01

    While feature size in lithography process continuously becomes smaller, defect sizes on blank wafers become more comparable to device sizes. Defects with nm-scale characteristic size could be misclassified by automated optical inspection (AOI) and require post-processing for proper classification. Atomic force microscope (AFM) is known to provide high lateral and the highest vertical resolution by mechanical probing among all techniques. However, its low throughput and tip life in addition to the laborious efforts for finding the defects have been the major limitations of this technique. In this paper we introduce automatic defect review (ADR) AFM as a post-inspection metrology tool for defect study and classification for 300 mm blank wafers and to overcome the limitations stated above. The ADR AFM provides high throughput, high resolution, and non-destructive means for obtaining 3D information for nm-scale defect review and classification.

  17. Analysis of wafer heating in 14nm DUV layers

    NASA Astrophysics Data System (ADS)

    Subramany, Lokesh; Chung, Woong Jae; Samudrala, Pavan; Gao, Haiyong; Aung, Nyan; Gomez, Juan Manuel; Minghetti, Blandine; Lee, Shawn

    2016-03-01

    To further shrink the contact and trench dimensions, Negative Tone Development (NTD) has become the de facto process at these layers. The NTD process uses a positive tone resist and an organic solvent-based negative tone developer which leads to improved image contrast, larger process window and smaller Mask Error Enhancement Factor (MEEF)[1]. The NTD masks have high transmission values leading to lens heating and as observed here wafer heating as well. Both lens and wafer heating will contribute to overlay error, however the effects of lens heating can be mitigated by applying lens heating corrections while no such corrections exist for wafer heating yet. Although the magnitude of overlay error due to wafer heating is low relative to lens heating; ever tightening overlay requirements imply that the distortions due to wafer heating will quickly become a significant part of the overlay budget. In this work the effects, analysis and observations of wafer heating on contact and metal layers of the 14nm node are presented. On product wafers it manifests as a difference in the scan up and scan down signatures between layers. An experiment to further understand wafer heating is performed with a test reticle that is used to monitor scanner performance.

  18. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, Gary S.

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  19. Fundamental limitations of LIGA x-ray lithography : sidewall offset, slope and minimum feature size.

    SciTech Connect

    Griffiths, Stewart K.

    2004-01-01

    Analytical and numerical methods are used to examine photoelectron doses and their effect on the dimensions of features produced by deep x-ray lithography. New analytical models describing electron doses are presented and used to compute dose distributions for several feature geometries. The history of development and final feature dimensions are also computed, taking into account the dose field, dissolution kinetics based on measured development rates, and the transport of PMMA fragments away from the dissolution front. We find that sidewall offsets, sidewall slope and producible feature sizes all exhibit at least practical minima and that these minima represent fundamental limitations of the LIGA process. The minimum values under optimum conditions are insensitive to the synchrotron spectrum, but depend strongly on resist thickness. This dependence on thickness is well approximated by simple analytical expressions describing the minimum offset, minimum sidewall slope, minimum producible size of positive and negative features, maximum aspect ratio and minimum radius of inside and outside corners.

  20. Piezoresistive stress sensors on (110) silicon wafers

    NASA Technical Reports Server (NTRS)

    Kang, Y. L.; Suhling, J. C.; Jaeger, R. C.

    1992-01-01

    Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

  1. Wafer Mapping Using Deuterium Enhanced Defect Characterization

    NASA Astrophysics Data System (ADS)

    Hossain, K.; Holland, O. W.; Hellmer, R.; Vanmil, B.; Bubulac, L. O.; Golding, T. D.

    2010-07-01

    Deuterium (as well as other hydrogen isotopes) binds with a wide range of morphological defects in semiconductors and, as such, becomes distributed similarly to those defects. Thus, the deuterium profile within the sample serves as the basis of a technique for defect mapping known as amethyst wafer mapping (AWM). The efficiency of this technique has been demonstrated by evaluation of ion-induced damage in implanted Si, as well as as-grown defects in HgCdTe (MCT) epilayers. The defect tagging or decoration capability of deuterium is largely material independent and applicable to a wide range of defect morphologies. A number of analytical techniques including ion channeling and etch pit density measurements were used to evaluate the AWM results.

  2. Overlay Tolerances For VLSI Using Wafer Steppers

    NASA Astrophysics Data System (ADS)

    Levinson, Harry J.; Rice, Rory

    1988-01-01

    In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his

  3. Electromechanically driven microchopper for integration in microspectrometers based on LIGA technology

    NASA Astrophysics Data System (ADS)

    Krippner, Peter; Mohr, Juergen; Saile, Volker

    1999-09-01

    In recent years, microspectrometers made by the LIGA technology for the visible wavelength range have found their way into the market. Opening the wide field of spectral analysis in the infrared range, the concept of a highly transmissive hollow waveguide has been demonstrated successfully. In combination with linear detector arrays, hollow waveguide microspectrometers can be combined into handheld infrared spectrometer systems. The only obstacle to a miniaturized system is the lack of miniaturized light modulators. To solve this problem, a miniaturized light modulator has been developed. It consists of an oscillating stop driven by an electromagnetic actuator. It is made out of permalloy by means of LIGA micromechanics. Its outer dimensions of approx. 3.0 X 3.2 mm2 and a structure height of 280 micrometer allow it to be integrated into the plane of the entrance slit of the microspectrometer of about 20 mm to 30 mm size. The spectrometer has alignment structures to ensure positioning of the oscillating stop close to the entrance slit. This simplifies assembly. The actuator is excited by an hybrid integrated coil fixed by springs snapping into place during assembly. The maximum supply voltage of 5V allows the chopper to be used in low-voltage spectrometer systems, especially in handheld systems. The highest modulation frequency is more than 1 kHz, which is sufficient to work with the lead salt detectors commonly used. In this frequency range, detector noise is greatly attenuated compared to continuous-light operation. The paper contains an outline of the concept of the whole microspectrometer system. Experimental results are discussed to demonstrate the performance of the system.

  4. UV-LIGA microfabrication process for sub-terahertz waveguides utilizing multiple layered SU-8 photoresist

    NASA Astrophysics Data System (ADS)

    Malekabadi, Ali; Paoloni, Claudio

    2016-09-01

    A microfabrication process based on UV LIGA (German acronym of lithography, electroplating and molding) is proposed for the fabrication of relatively high aspect ratio sub-terahertz (100–1000 GHz) metal waveguides, to be used as a slow wave structure in sub-THz vacuum electron devices. The high accuracy and tight tolerances required to properly support frequencies in the sub-THz range can be only achieved by a stable process with full parameter control. The proposed process, based on SU-8 photoresist, has been developed to satisfy high planar surface requirements for metal sub-THz waveguides. It will be demonstrated that, for a given thickness, it is more effective to stack a number of layers of SU-8 with lower thickness rather than using a single thick layer obtained at lower spin rate. The multiple layer approach provides the planarity and the surface quality required for electroforming of ground planes or assembly surfaces and for assuring low ohmic losses of waveguides. A systematic procedure is provided to calculate soft and post-bake times to produce high homogeneity SU-8 multiple layer coating as a mold for very high quality metal waveguides. A double corrugated waveguide designed for 0.3 THz operating frequency, to be used in vacuum electronic devices, was fabricated as test structure. The proposed process based on UV LIGA will enable low cost production of high accuracy sub-THz 3D waveguides. This is fundamental for producing a new generation of affordable sub-THz vacuum electron devices, to fill the technological gap that still prevents a wide diffusion of numerous applications based on THz radiation.

  5. Reduction of Thermal Conductivity in Wafer-Bonded Silicon

    SciTech Connect

    ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

    2006-11-27

    Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

  6. Backside EBR process performance with various wafer properties

    NASA Astrophysics Data System (ADS)

    Goto, Tomohiro; Shigemori, Kazuhito; Vangheluwe, Rik; Erich, Daub; Sanada, Masakazu

    2009-03-01

    In immersion lithography process, film stacking architecture will be necessary to avoid top coat film peeling. To achieve suitable stacking architecture for immersion lithography process, an EBR process that delivers tightly controlled film edge position and good uniformity around the wafer circumference is needed. We demonstrated a new bevel rinse system on a SOKUDO RF3 coat-and-develop track for immersion lithography. The performance of the new bevel rinse system for various wafer properties was evaluated. It was found that the bevel rinse system has a good controllability of film edge position and good uniformity around the wafer circumference. The results indicate that the bevel rinse system has a large margin for wafer centering accuracy, back side particles, wafer shape and substrates with good film edge position controllability, uniformity and clean apex. The system has been demonstrated to provide a suitable film stacking architecture for immersion lithography mass production process.

  7. Interferometric metrology of wafer nanotopography for advanced CMOS process integration

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Koliopoulos, Chris L.; Tang, Shouhong

    2001-12-01

    According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

  8. Rapid defect detections of bonded wafer using near infrared polariscope

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand K.

    2011-10-01

    In modern field of microelectronics and MEMS, wafer bonding has emerged as an important processing step in wide range of manufacturing applications. During the manufacturing process, even in the modern clean room, small defects result from trapped particles and gas bubbles exist at bonded interface. Defects and trapped particles may exist on the top and bottom of the wafers, or at the interface of bonded wafer pair. These inclusions will generate high stress around debond region at the wafers bonded interface. In this paper, inspection at the bonded interface will be the interest of investigation. Since silicon wafer is opaque to visible light, defect detection at the bonded interface of silicon wafer is not possible. Due to the fact that silicon wafer is transparent to wavelength greater than 1150nm, an Near Infrared Polariscope which has showed some promises on residual stress measurement on silicon devices has been adapted and developed. This method is based on the well known photoelastic principles, where the stress variations are measured based on the changes of light propagation velocity in birefringence material. The results are compared and contrast with conventional Infrared Transmission Imaging tool (IRT) which is widely used to inspect the bonded silicon wafer. In this research, the trapped particles that are not visible via conventional infrared transmission method are identified via the generated residual stress pattern. The magnitude of the residual stress fields associated with each defect is examined qualitatively and quantitatively. The stress field generated at the wafers bonded interface will looks like a 'butterfly' pattern. Wafer pairs Pyrex-Si and Si-Si bonded interface will be examined.

  9. Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage

    PubMed Central

    Rack, Alexander; Scheel, Mario; Danilewsky, Andreas N.

    2016-01-01

    Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1–2 ms followed by jumps faster than 2–6 m s−1, leading to a macroscopically observed average velocity of 0.028–0.055 m s−1. The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound. PMID:27006774

  10. Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage.

    PubMed

    Rack, Alexander; Scheel, Mario; Danilewsky, Andreas N

    2016-03-01

    Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1-2 ms followed by jumps faster than 2-6 m s(-1), leading to a macroscopically observed average velocity of 0.028-0.055 m s(-1). The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound. PMID:27006774

  11. Wafer-level filling of microfabricated atomic vapor cells based on thin-film deposition and photolysis of cesium azide

    SciTech Connect

    Liew, Li-Anne; Moreland, John; Gerginov, Vladislav

    2007-03-12

    The thin-film deposition and photodecomposition of cesium azide are demonstrated and used to fill arrays of miniaturized atomic resonance cells with cesium and nitrogen buffer gas for chip-scale atomic-based instruments. Arrays of silicon cells are batch fabricated on wafers into which cesium azide is deposited by vacuum thermal evaporation. After vacuum sealing, the cells are irradiated with ultraviolet radiation, causing the azide to photodissociate into pure cesium and nitrogen in situ. This technology integrates the vapor-cell fabrication and filling procedures into one continuous and wafer-level parallel process, and results in cells that are optically transparent and chemically pure.

  12. Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

    2014-01-01

    This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

  13. Development of optical automatic positioning and wafer defect detection system

    NASA Astrophysics Data System (ADS)

    Tien, Chuen-Lin; Lai, Qun-Huang; Lin, Chern-Sheng

    2016-02-01

    The data of a wafer with defects can provide engineers with very important information and clues to improve the yield rate and quality in manufacturing. This paper presents a microscope automatic positioning and wafer detection system with human-machine interface based on image processing and fuzzy inference algorithms. In the proposed system, a XY table is used to move the position of each die on 6 inch or 8 inch wafers. Then, a high-resolution CCD and one set of two-axis optical linear encoder are used to accurately measure the position on the wafer. Finally, the developed human-machine interface is used to display the current position of an actual wafer in order to complete automatic positioning, and a wafer map database can be created. In the process of defect detection, CCD is used for image processing, and during preprocessing, it is required to filter noise, acquire the defect characteristics, define the defective template, and then take the characteristic points of the defective template as the reference input for fuzzy inference. A high-accuracy optical automatic positioning and wafer defect detection system is thus constructed. This study focused on automatic detection of spots, scratches, and bruises, and attempted to reduce the time to detect defective die and improve the accuracy of determining the defects of semiconductor devices.

  14. Wafer-level vacuum/hermetic packaging technologies for MEMS

    NASA Astrophysics Data System (ADS)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  15. Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

    PubMed

    Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

    2014-06-01

    Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. PMID:24700434

  16. Techniques for the evaluation of outgassing from polymeric wafer pods

    SciTech Connect

    McIntyre, D.C.; Liang, A.; Thornberg, S.M.; Bender, S.F.; Lujan, R.D.; Blewer, R.S.; Bowers, W.D.

    1994-03-01

    In recent years there has been increasing interest in using wafer-level isolation environments or pods (microenvironments) to provide a more controllable, cleaner wafer environment during wafer processing. It has been shown that pods can be effective in reducing the amount of particulate contamination on wafers during manufacturing. However, there have also been studies that indicate that pods and wafer boxes can be the source of condensible, molecular organic contamination. This paper summarizes the work that has been performed during the past year at Sandia National Laboratories` Contamination Free Manufacturing Research Center (CFMRC) on (1) devising standard, low-temperature, high sensitivity techniques to detect outgassing of volatile organic compounds (VOCs) from polymers used to construct wafer pods and (2) development of a technique that can be used to continuously measure the condensible contamination within pods so that the pod environment can be monitored during manufacturing. Although these techniques have been developed specifically for assessing contamination threats from wafer pods, they can be used to evaluate other potential contamination sources. The high sensitivity outgassing techniques can be used to evaluate outgassing of volatiles from other clean-room materials and the real-time outgassing sensor can be used to monitor contamination condensation in non-pod environments such as ballroom-type cleanrooms and minienvironments.

  17. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    NASA Astrophysics Data System (ADS)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

    2016-08-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

  18. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    NASA Astrophysics Data System (ADS)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

    2016-03-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

  19. Thermal spray and cold spray analysis of density, porosity, and tensile Specimens for use with LIGA applications

    SciTech Connect

    DECKER,MERLIN K.; SMITH,MARK F.

    2000-02-01

    This analysis provides a preliminary investigation into using Twin-Wire Arc Thermal Spray and Cold Spray as material deposition processes for LIGA applications. These spray material processes were studied to make an initial determination of their potential as alternatives to producing mechanical parts via the electroplating process. Three materials, UltraMachinable{reg_sign} Stainless Steel, BondArc{reg_sign}, and aluminum, were sprayed using Thermal Spray. Only aluminum was sprayed using the Cold Spray process. Following the spray procedure, the test specimens were released from a copper mold and then tested. Three tests, density, tensile strength, and porosity, were performed on the specimens to determine the spray effect on material properties. Twin-Wire Arc Thermal Spray did not demonstrate adequate deposition properties and does not appear to be a good process candidate for LIGA. However, Cold Spray yielded better density results and warrants further investigation to analyze the minimum feature size produced by the process.

  20. Microfabrication of fine electron beam tunnels using UV-LIGA and embedded polymer monofilaments for vacuum electron devices

    NASA Astrophysics Data System (ADS)

    Joye, Colin D.; Calame, Jeffrey P.; Nguyen, Khanh T.; Garven, Morag

    2012-01-01

    Vacuum electron devices require electron beams to be transported through hollow channels that pass through an electromagnetic slow-wave circuit. These electron 'beam tunnels' are shrinking toward sizes smaller than traditional techniques can manage as the operating frequencies push toward the THz. A novel technique is described and experimentally demonstrated that uses polymer monofilaments of arbitrary cross-sectional shape combined with ultraviolet photolithography (UV-LIGA) of SU-8 photoresists. This combination of monofilaments and SU-8 structures comprises a 3D mold around which copper is electroformed to produce high-quality beam tunnels of arbitrary length and size along with the electromagnetic circuits. True round beam tunnels needed for upper-millimeter wave and THz vacuum electron devices can now be fabricated in a single UV-LIGA step. These techniques are also relevant to microfluidic devices and other applications requiring very small, straight channels with aspect ratios of several hundred or more.

  1. The uses of Man-Made diamond in wafering applications

    NASA Technical Reports Server (NTRS)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  2. Wafer warpage characterization measurement with modified fringe reflection method

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2015-05-01

    We have demonstrated a modified fringe reflection method to compensate the warpage measurement errors caused by the height difference between optical reference mirror and wafer sample surface. We have used a linearity analysis approach to obtain the parabolic height errors for a 4-inch sapphire wafer warpage measurement, which is around 1.48 μm of 100 μm height difference. The experimental results shows the warp discrepancy of 6-inch sapphire wafer is less than 1 μm compared with the reference Tropel instrument.

  3. Analysis of the interdigitated back contact solar cells: The n-type substrate lifetime and wafer thickness

    NASA Astrophysics Data System (ADS)

    Zhang, Wei; Chen, Chen; Jia, Rui; Sun, Yun; Xing, Zhao; Jin, Zhi; Liu, Xin-Yu; Liu, Xiao-Wen

    2015-10-01

    The n-type silicon integrated-back contact (IBC) solar cell has attracted much attention due to its high efficiency, whereas its performance is very sensitive to the wafer of low quality or the contamination during high temperature fabrication processing, which leads to low bulk lifetime τbulk. In order to clarify the influence of bulk lifetime on cell characteristics, two-dimensional (2D) TCAD simulation, combined with our experimental data, is used to simulate the cell performances, with the wafer thickness scaled down under various τbulk conditions. The modeling results show that for the IBC solar cell with high τbulk, (such as 1 ms-2 ms), its open-circuit voltage Voc almost remains unchanged, and the short-circuit current density Jsc monotonically decreases as the wafer thickness scales down. In comparison, for the solar cell with low τbulk (for instance, < 500 μs) wafer or the wafer contaminated during device processing, the Voc increases monotonically but the Jsc first increases to a maximum value and then drops off as the wafer’s thickness decreases. A model combing the light absorption and the minority carrier diffusion is used to explain this phenomenon. The research results show that for the wafer with thinner thickness and high bulk lifetime, the good light trapping technology must be developed to offset the decrease in Jsc. Project supported by the Chinese Ministry of Science and Technology Projects (Grant Nos. 2012AA050304 and Y0GZ124S01), the National Natural Science Foundation of China (Grant Nos. 11104319, 11274346, 51202285, 51402347, and 51172268), and the Fund of the Solar Energy Action Plan from the Chinese Academy of Sciences (Grant Nos. Y3ZR044001 and Y2YF014001).

  4. Low-temperature full wafer adhesive bonding

    NASA Astrophysics Data System (ADS)

    Niklaus, Frank; Enoksson, Peter; Kälvesten, Edvard; Stemme, Göran

    2001-03-01

    We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 µm and 18 µm. The tested polymer materials were benzocyclobutene (BCB) from Dow Chemical, a negative photoresist (ULTRA-i 300) and a positive photoresist (S1818) from Shipley, a polyimide (HTR3) from Arch Chemical and two different polyimides (PI2555 and PI2610) from DuPont. The polymer material, the bonding pressure and the pre-curing time and temperature for the polymer significantly influence void formation at the bond interface. High bonding pressure and optimum pre-curing times/temperatures counteract void formation. We present the process parameters to achieve void-free bonding with the BCB coating and with the ULTRA-i 300 photoresist coating as adhesive materials. Excellent void-free and strong bonds have been achieved by using BCB as the bonding material which requires a minimum bonding temperature of 180 °C.

  5. Phoradendron liga (Gill. ex H. et A.) Eichl. (Viscaceae) used in folk medicine: anatomical, phytochemical, and immunochemical studies.

    PubMed

    Varela, Beatriz G; Fernández, Teresa; Ricco, Rafael A; Zolezzi, Paula Cerdá; Hajos, Silvia E; Gurni, Alberto A; Alvarez, Elida; Wagner, Marcelo L

    2004-09-01

    Phoradendron liga (Gill. ex H. et A.) Eichl. is a Viscaceae widely distributed in Argentina. It has been commonly used in folk medicine as a substitute of the European mistletoe (Viscum album L.) to decrease high blood pressure due to their external similarity. In this study, the anatomical features as well as micromolecular and macromolecular analysis of this species are reported. Anatomical study has shown that Phoradendron liga presents as anatomic features: papillous cuticle, clusters in leaves and stems, and isodiametric stone cells only in stems. The analysis of flavonoids showed that this species produces C-glycosylflavones and 3-desoxyproanthocyanidins. Protein study showed a protein pattern with components ranging from 14 to 90 kDa and the presence of related epitopes between the species was demonstrated by cross recognition using anti-Phoradendron and anti-Viscum antisera of both species by Western blot assay. In addition, a galactose specific lectin (L-Phl) was isolated form Phoradendron liga extracts. These results are part of a comprehensive project on Argentine hemiparasite species destinated to be applied to quality control of commercial samples and disclosed their potential use as a potential source for immunomodulatory compounds. PMID:15261970

  6. Extraction and Analysis of Noise Parameters of On Wafer HEMTs up to 26.5 GHz

    SciTech Connect

    Caddemi, Alina; Crupi, Giovanni; Macchiarella, Alessio

    2009-04-23

    This paper presents a procedure for extracting the four noise parameters of on wafer scaled HEMTs based on AlGaAs/GaAs heterostructure. This procedure relies on 50-{omega} noise figure measurements up to 26.5 GHz by determining the equivalent temperatures associated to the intrinsic resistances of the small signal equivalent circuit. The non-quasi-static effect associated to the gate-drain resistance R{sub gd} is accounted for by the noise model. A good agreement between measured and simulated noise figure is obtained and scaling of the noise parameters is reported.

  7. Efficient data transmission from silicon wafer strip detectors

    SciTech Connect

    Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

    1991-12-31

    An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

  8. Proceedings of the Low-Cost Solar Array Wafering Workshop

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1982-01-01

    The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

  9. Surface defects in GaAs wafer processes

    NASA Astrophysics Data System (ADS)

    Matsushita, H.; Ishida, M.; Kikawa, J.

    1990-06-01

    The causes of micro- and macro-irregularities observed on GaAs(100) polished wafers were investigated. From the results, the wafer processes were improved so that a high-quality surface was obtained without orange peel, haze, or pits. For 3-inch wafers the flatness was improved to less than 2 μm in TTV and the warp to less than 5 μm. Improvements in the wafer processes were: development of a better polishing solution, filtering of this solution with maintenance of the pad conditions, thereby eliminating scratches, annealing at high temperature to eliminate pits, advances in slicing and lapping to reduce warp, and three-stage double-sided polishing to eliminate dimples and to improve TTV.

  10. Particle-wafer interactions in semiaqueous silicon cleaning systems

    NASA Astrophysics Data System (ADS)

    Hupka, Lukasz

    During the semiconductor chip manufacturing process, a silicon wafer goes through a number of cycles in both hydrophilic and hydrophobic environments. As silicon chips become more sophisticated, the manufacturing process becomes more involved and new challenges are imposed by size reduction, increase in the aspect ratio and the formation of multilayer structures. Wafer cleaning processes emerge several times in one manufacturing cycle. By rule of thumb, it is necessary to remove wafer contamination by particles which are half of a feature size. This is an enormous challenge, keeping in mind that currently wafer structures are of nanometer size. The cleaning procedures which worked for the last 40 years are becoming ineffective and obsolete. The industry calls for more efficient cleaning procedures in terms of particle contamination removal, and at the same time less aggressive procedures to prevent damage/dissolution of the fragile and narrow wafer structures. Atomic Force Microscopy (AFM), besides being an imaging tool with nano resolution, proves to be an indispensable instrument to characterize interaction forces, lateral forces, and adhesion between micron and submicron contaminant particles and the wafer surfaces both in air and liquid. Using the AFM colloidal probe technique interaction forces were measured between a contaminant particle and a wafer surface. These measurements were done for the silica---silica hydrophilic system and for the silanated silica---silanated silica hydrophobic system. The influence of the nonaqueous component in semiconductor wafer cleaning solution on interaction forces was also investigated under both hydrophilic and hydrophobic conditions. In addition the effect of particle size on the interaction forces as well as particle removal rate under both conditions is addressed. While force/radius normalization of measured interaction forces works great for hydrophilic systems, it was found to significantly underestimate the influence

  11. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  12. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2008-10-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  13. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-03-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  14. Thermomechanical global response of the EUVL wafer during exposure

    NASA Astrophysics Data System (ADS)

    Chang, Jaehyuk; Martin, Carl J.; Engelstad, Roxann L.; Lovell, Edward G.

    2002-07-01

    Extreme ultraviolet lithography (EUVL) is one of the leading technologies for Next-Generation Lithography. Continued progress in its development will be facilitated by characterizing all sources of distortion in the chip fabrication process. These include the thermal distortions of the wafer caused by deposited EUVL energy during scanning exposure. Absorbed energy from the beam produces temperature increases and structural displacements in the wafer, which directly contribute to pattern placement errors and image blur. Because of the vacuum conditions of EUVL systems, wafer chucking will be electrostatic, which has a number of advantages over mechanical clamping systems. The goals of this research are to predict the transient temperature increases and corresponding displacements (locally and globally) consistent with the thermomechanical boundary conditions of the wafer. Both thermal and structural finite element models were constructed to numerically simulate wafer exposure. The response of the wafer is relatively sensitive to the interface conditions between the substrate and electrostatic chuck. Thus, parametric studies of the response to changes in the contact conductance and the friction coefficient were performed and are presented in this paper.

  15. Strategy optimization for mask rule check in wafer fab

    NASA Astrophysics Data System (ADS)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  16. Further investigation of EUV process sensitivities for wafer track processing

    NASA Astrophysics Data System (ADS)

    Bradon, Neil; Nafus, K.; Shite, H.; Kitano, J.; Kosugi, H.; Goethals, M.; Cheng, S.; Hermans, J.; Hendrickx, E.; Baudemprez, B.; Van Den Heuvel, D.

    2010-04-01

    As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.

  17. Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis

    SciTech Connect

    Tobin, K.W.

    2003-05-22

    This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

  18. Scales

    MedlinePlus

    Scales are a visible peeling or flaking of outer skin layers. These layers are called the stratum ... Scales may be caused by dry skin, certain inflammatory skin conditions, or infections. Eczema , ringworm , and psoriasis ...

  19. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  20. A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

    PubMed

    Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

    2012-07-01

    We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging. PMID:22966554

  1. Power-scalable 1.57 microm mode-locked semiconductor disk laser using wafer fusion.

    PubMed

    Saarinen, Esa J; Puustinen, Janne; Sirbu, Alexei; Mereuta, Alexandru; Caliman, Andrei; Kapon, Eli; Okhotnikov, Oleg G

    2009-10-15

    We report the first (to our knowledge) wafer-fused high-power passively mode-locked semiconductor disk laser operating at 1.57 microm wavelength. An InP-based active medium was fused with GaAs/AlGaAs distributed Bragg reflector on a 2 inch wafer level, resulting in an integrated monolithic gain mirror. An intracavity wedged diamond heat-spreader capillary bonded to the gain chip provides efficient heat removal from the gain structure without disturbing the spectrum of the mode-locked laser. The laser produces over 0.6 W of average output power at 15 degrees C with 16 ps pulse width. The total output power accounting for all output beams emerging from the cavity was 0.86 W. The results reveal an essential advantage of wafer fusion processing of disparate materials over monolithically grown InP-based gain structures and demonstrate the high potential of this technique for power scaling of long-wavelength semiconductor disk lasers. PMID:19838252

  2. Nanoscale friction and wear properties of silicon wafer under different lubrication conditions

    NASA Astrophysics Data System (ADS)

    Chen, Xiaochun; Zhao, Yongwu; Wang, Yongguang; Zhou, Hailan; Ni, Zhifeng; An, Wei

    2013-10-01

    The nanoscale friction and wear properties of single crystal silicon wafer under different lubrication conditions are studied in this paper. The experiments were performed with Si3N4 ball sliding on the surface of silicon wafer under four different lubrication conditions: dry friction, water lubrication, hydrogen peroxide lubrication and the static hydrogen peroxide dry friction. The results from the experiments have been analyzed showing the different friction and wear properties of the silicon wafer in different lubrication conditions. It is concluded that the wear rates under the water lubrication and under the hydrogen peroxide lubrication are both small, the chemical reactions are facilitated by the mechanical processes when the load and the sliding speed reach certain levels. This is mainly resulted by the enhanced lubricant performance with the formed silicon hydroxide Si(OH)4 film. Under the water lubrication, the wear is found in a way of material removed in molecule scale. Under the hydrogen peroxide lubrication, the wear is mainly caused by the spalling of micro-cracks. Under the dry friction condition, the wear is found being adhesive wear. And under the static peroxide dry friction, the wear is prevailing adhesive wear. These results are essential and valuable to the development of the efficient and environmental-friendly slurry for the chemical mechanical polishing (CMP) process.

  3. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  4. The influence of feature sidewall tolerance on minimum absorber thickness for LIGA x-ray masks

    SciTech Connect

    S. K. Griffiths; J. M. Hruby; A. Ting

    1999-02-01

    Minimizing mask absorber thickness is an important practical concern in producing very small features by the LIGA process. To assist in this minimization, the authors have developed coupled numerical models describing both the exposure and development of a thick PMMA resist. The exposure model addresses multi-wavelength, one-dimensional x-ray transmission through multiple beam filters, through the mask substrate and absorber, and the subsequent attenuation and photon absorption in the PMMA resist. The development model describes one-dimensional dissolution of a feature and its sidewalls, taking into account the variation in absorbed dose through the PMMA thickness. These exposure and development models are coupled in a single interactive code, permitting the automated adjustment of mask absorber thickness to yield a prescribed sidewall taper or dissolution distance. They have used this tool to compute the minimum required absorber thickness yielding a prescribed sidewall tolerance for exposures performed at the ALS, SSRL and NSLS synchrotron sources. Results are presented as a function of the absorbed dose for a range of the prescribed sidewall tolerance, feature size, PMMA thickness, mask substrate thickness and the development temperature.

  5. Dimensional errors in LIGA-produced metal structures due to thermal expansion and swelling of PMMA.

    SciTech Connect

    Kistler, Bruce L.; Dryden, Andrew S.; Crowell, Jeffrey A.W.; Griffiths, Stewart K.

    2004-04-01

    Numerical methods are used to examine dimensional errors in metal structures microfabricated by the LIGA process. These errors result from elastic displacements of the PMMA mold during electrodeposition and arise from thermal expansion of the PMMA when electroforming is performed at elevated temperatures and from PMMA swelling due to absorption of water from aqueous electrolytes. Both numerical solutions and simple analytical approximations describing PMMA displacements for idealized linear and axisymmetric geometries are presented and discussed. We find that such displacements result in tapered metal structures having sidewall slopes up to 14 {micro}m per millimeter of height for linear structures bounded by large areas of PMMA. Tapers for curved structures are of similar magnitude, but these structures are additionally skewed from the vertical. Potential remedies for reducing dimensional errors are also discussed. Here we find that auxiliary moat-like features patterned into the PMMA surrounding mold cavities can reduce taper by an order of magnitude or more. Such moats dramatically reduce tapers for all structures, but increase skew for curved structures when the radius of curvature is comparable to the structure height.

  6. Improving on-wafer CD correlation analysis using advanced diagnostics and across-wafer light-source monitoring

    NASA Astrophysics Data System (ADS)

    Alagna, Paolo; Zurita, Omar; Rechtsteiner, Gregory; Lalovic, Ivan; Bekaert, Joost

    2014-04-01

    With the implementation of multi-patterning ArF-immersion for sub 20nm integrated circuits (IC), advances in equipment monitoring and control are needed to support on-wafer yield performance. These in-situ equipment monitoring improvements, along with advanced litho-cell corrections based on on-wafer measurements, enable meeting stringent overlay and CD control requirements for advanced lithography patterning. The importance of light-source performance on lithography pattering (CD and overlay) has been discussed in previous publications.[1-3] Recent developments of Cymer ArF light-source metrology and on-board monitoring enable end-users to detect, for each exposed wafer, changes in the near-field and far-field spatial profiles and polarization performance, [4-6] in addition to the key `optical' scalar parameters, such as bandwidth, wavelength and energy. The major advantage of this capability is that the key performance metrics are sampled at rates matched to wafer performance, e.g. every exposure field across the wafer, which is critical for direct correlation with on-wafer performance for process control and excursion detection.

  7. Fine Mapping of the Interaction between C4b-Binding Protein and Outer Membrane Proteins LigA and LigB of Pathogenic Leptospira interrogans

    PubMed Central

    Breda, Leandro C. D.; Hsieh, Ching-Lin; Castiblanco Valencia, Mónica M.; da Silva, Ludmila B.; Barbosa, Angela S.; Blom, Anna M.; Yung-Fu, Chang; Isaac, Lourdes

    2015-01-01

    The complement system consists of more than 40 proteins that participate in the inflammatory response and in pathogen killing. Complement inhibitors are necessary to avoid the excessive consumption and activation of this system on host cells. Leptospirosis is a worldwide zoonosis caused by spirochetes from the genus Leptospira. Pathogenic leptospires are able to escape from complement activation by binding to host complement inhibitors Factor H [FH] and C4b-binding protein (C4BP) while non-pathogenic leptospires are rapidly killed in the presence of fresh serum. In this study, we demonstrate that complement control protein domains (CCP) 7 and 8 of C4BP α-chain interact with the outer membrane proteins LcpA, LigA and LigB from the pathogenic leptospire L. interrogans. The interaction between C4BP and LcpA, LigA and LigB is sensitive to ionic strength and inhibited by heparin. We fine mapped the LigA and LigB domains involved in its binding to C4BP and heparin and found that both interactions are mediated through the bacterial immunoglobulin-like (Big) domains 7 and 8 (LigA7-8 and LigB7-8) of both LigA and LigB and also through LigB9-10. Therefore, C4BP and heparin may share the same binding sites on Lig proteins. PMID:26517116

  8. Comparison and Efficacy of LigaSure and Rubber Band Ligature in Closing the Inflamed Cecal Stump in a Rat Model of Acute Appendicitis

    PubMed Central

    Yeh, Chun-Chieh; Jan, Chia-Ing; Yang, Horng-Ren; Jeng, Long-Bin; Su, Wen-Pang

    2015-01-01

    Safety of either LigaSure or rubber band in closing inflamed appendiceal stump in acute appendicitis has been less investigated. In this study, cecal ligation followed by resecting inflamed cecum was performed to mimic appendectomy in a rat model of acute appendicitis. Rats were sacrificed immediately (Group A) and 7 days (Group B) after cecal resection, respectively. The cecal stumps were closed by silk ligature (S), 5 mm LigaSure (L), or rubber band (R). Seven days after cecal resection, the LigaSure (BL) and silk subgroups (BS) had significantly less intra-abdominal adhesion and better laparotomy wound healing than rubber band subgroup (BR). The initial bursting pressure at cecal stump was comparable among the three methods; along with tissue healing process, both BL and BS provided a higher bursting pressure than BR 7 days after appendectomy. BL subgroup had more abundant hydroxyproline deposition than BS and BR subgroup. Furthermore, serum TNF-α in BR group kept persistently increasing along with time after cecal resection. Thus, the finding that LigaSure but not rubber band is safe in sealing off the inflamed cecal stump in rat model of acute appendicitis suggests the possibility of applying LigaSure for appendectomy via single port procedure or natural orifice transluminal endoscopic surgery (NOTES). PMID:25699264

  9. Comparison and efficacy of LigaSure and rubber band ligature in closing the inflamed cecal stump in a rat model of acute appendicitis.

    PubMed

    Yeh, Chun-Chieh; Jan, Chia-Ing; Yang, Horng-Ren; Huang, Po-Han; Jeng, Long-Bin; Su, Wen-Pang; Chen, Hui-Chen

    2015-01-01

    Safety of either LigaSure or rubber band in closing inflamed appendiceal stump in acute appendicitis has been less investigated. In this study, cecal ligation followed by resecting inflamed cecum was performed to mimic appendectomy in a rat model of acute appendicitis. Rats were sacrificed immediately (Group A) and 7 days (Group B) after cecal resection, respectively. The cecal stumps were closed by silk ligature (S), 5 mm LigaSure (L), or rubber band (R). Seven days after cecal resection, the LigaSure (BL) and silk subgroups (BS) had significantly less intra-abdominal adhesion and better laparotomy wound healing than rubber band subgroup (BR). The initial bursting pressure at cecal stump was comparable among the three methods; along with tissue healing process, both BL and BS provided a higher bursting pressure than BR 7 days after appendectomy. BL subgroup had more abundant hydroxyproline deposition than BS and BR subgroup. Furthermore, serum TNF-α in BR group kept persistently increasing along with time after cecal resection. Thus, the finding that LigaSure but not rubber band is safe in sealing off the inflamed cecal stump in rat model of acute appendicitis suggests the possibility of applying LigaSure for appendectomy via single port procedure or natural orifice transluminal endoscopic surgery (NOTES). PMID:25699264

  10. Low-temperature titanium-based wafer bonding

    NASA Astrophysics Data System (ADS)

    Yu, Jian

    This thesis presents novel methods of metal-based wafer bonding at back-end-of-the-line (BEOL) compatible conditions (≤450°C). For the first time to our knowledge, 200 mm diameter oxidized Si wafers are bonded with prime Si wafers using 10-300 nm thick Ti as bonding intermediate at 300-450°C. Nearly void-free bonding with strong mechanical integrity has been confirmed. Moreover, microcavity formation has been demonstrated by bonding of patterned wafers. Both Rutherford backscattering spectroscopy (RBS) and Auger electron spectroscopy (AES) show clear evidence of Si and Ti interdiffusion, whereas high-resolution transmission electron microscopy (HRTEM) reveals an approximately 8 nm thick amorphous layer at the bonding interface. Those results indicate that the strong adhesion at the Ti/Si bonding interface is attributed to a solid-state amorphization (SSA) assisted by interdiffusion. A key effort is devoted to fundamental investigation of low-temperature transition metal(TM)/Si-based wafer bonding. With the extensive work on Ti/Si system, additional experiments are performed with six other TM/Si systems, namely Ni/Si, Co/Si, Pd/Si, Hf/Si, Au/Si and Ta/Si. The results indicate there are two principal requirements for TM/Si-based wafer bonding: (1) intimate contact (able to break through kinetic barriers), and (2) adequate chemical bonding. Three kinetic barriers addressed in this thesis are: (1) enclosed microvoids due to surface roughness, (2) gas molecules at the bonding interface, and (3) interfacial oxides. Presence of these barriers can prevent formation of intimate contact, consequently retarding or even blocking interfacial interactions for chemical bonding. The unique properties of Group IVA metals (e.g., Ti and Hf) to reduce native SiO2 on Si surfaces and their exceptionally large solid solubility for O2 and N2, help overcome those issues. Once kinetic barriers are surmounted, the key for strong metal/Si-based wafer bonding is formation of chemical bonds

  11. Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering

    NASA Astrophysics Data System (ADS)

    Chen, Po-Ying; Tsai, Ming-Hsing; Yeh, Wen-Kuan; Jing, Ming-Haw; Chang, Yukon

    2009-12-01

    Silicon wafer breakage has become a major concern for all semiconductor fabrication lines because it is brittle, and thus high stresses are easily induced in its manufacture. The production cost of devices significantly increases even for a breakage loss of a few percent if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant. In this investigation, we develop a brand new approach to reducing breakage by using a charge-coupled device (CCD) to capture the cross-section image of the wafer at its edge; the data measured at the edge can be used to determine overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength, and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in the wafer bulk before failure. We also describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unidentified causes. Our analysis gives the optimal front size (B1), edge widths (A1,A2), and bevel angle (θ) for the edge profiles of wafers to prevent wafer breakage. Briefly, when a suitable material and suitable process control approaches are utilized, silicon wafer breakage can be prevented. This is the first investigation providing evidence that whole-wafer strength is an important issue. We present a physical model to explain why wafer fracture has become an increasingly serious problem as the diameter of wafers has increased. The control of wafer edge geometry has been demonstrated to be an effective means of protecting wafers with large diameters against breakage. This model reveals that the breakage rate of wafers can be reduced by controlling the uniformity of the differences between the front size and the rear edge widths during the wafer manufacturing process.

  12. Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.

    2004-01-01

    An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

  13. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    NASA Astrophysics Data System (ADS)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  14. Simple and accurate optical height sensor for wafer inspection systems

    NASA Astrophysics Data System (ADS)

    Shimura, Kei; Nakai, Naoya; Taniguchi, Koichi; Itoh, Masahide

    2016-02-01

    An accurate method for measuring the wafer surface height is required for wafer inspection systems to adjust the focus of inspection optics quickly and precisely. A method for projecting a laser spot onto the wafer surface obliquely and for detecting its image displacement using a one-dimensional position-sensitive detector is known, and a variety of methods have been proposed for improving the accuracy by compensating the measurement error due to the surface patterns. We have developed a simple and accurate method in which an image of a reticle with eight slits is projected on the wafer surface and its reflected image is detected using an image sensor. The surface height is calculated by averaging the coordinates of the images of the slits in both the two directions in the captured image. Pattern-related measurement error was reduced by applying the coordinates averaging to the multiple-slit-projection method. Accuracy of better than 0.35 μm was achieved for a patterned wafer at the reference height and ±0.1 mm from the reference height in a simple configuration.

  15. Quantitative phase measurement for wafer-level optics

    NASA Astrophysics Data System (ADS)

    Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

    2015-07-01

    Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

  16. 100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices

    SciTech Connect

    OLIVER,ANDREW D.; MATZKE,CAROLYN M.

    2000-04-06

    A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

  17. Surface quality of silicon wafer improved by hydrodynamic effect polishing

    NASA Astrophysics Data System (ADS)

    Peng, Wenqiang; Guan, Chaoliang; Li, Shengyi

    2014-08-01

    Differing from the traditional pad polishing, hydrodynamic effect polishing (HEP) is non-contact polishing with the wheel floated on the workpiece. A hydrodynamic lubricated film is established between the wheel and the workpiece when the wheel rotates at a certain speed in HEP. Nanoparticles mixed with deionized water are employed as the polishing slurry, and with action of the dynamic pressure, nanoparticles with high chemisorption due to the high specific surface area can easily reacted with the surface atoms forming a linkage with workpiece surface. The surface atoms are dragged away when nanoparticles are transported to separate by the flow shear stress. The development of grand scale integration put extremely high requirements on the surface quality on the silicon wafer with surface roughness at subnanometer and extremely low surface damage. In our experiment a silicon sample was processed by HEP, and the surface topography before and after polishing was observed by the atomic force microscopy. Experiment results show that plastic pits and bumpy structures on the initial surface have been removed away clearly with the removal depth of 140nm by HEP process. The processed surface roughness has been improved from 0.737nm RMS to 0.175nm RMS(10μm×10μm) and the section profile shows peaks of the process surface are almost at the same height. However, the machining ripples on the wheel surface will duplicate on the silicon surface under the action of the hydrodynamic effect. Fluid dynamic simulation demonstrated that the coarse surface on the wheel has greatly influence on the distribution of shear stress and dynamic pressure on the workpiece surface.

  18. Performance of Ultra Hard Carbon Wear Coatings on Microgears Fabricated by Liga

    SciTech Connect

    Ager III, J.W.; Brown, I.G.; Christenson, T.R.; Dugger, M.T.; Follstaedt, D.M.; Knapp, J.A.; Monteiro, O.R.

    1998-12-18

    Stiction and friction are of concern for the reliable, long-term application of Ni-alloy micromachines. We have found that the application of a 30-70 nm hard carbon coating produces a significant reduction in the friction coefficient and wear rate of electroformed Ni substrates in reciprocating sliding contact under simulated MEMS operating conditions. To evaluate the performance of coated components, a series of 70-pm-thick microgears ranging in diameter from 0.2 to 2.2 mm were fabricated from electroformed Ni via standard LIGA processes and fixtured on posts in preparation for the coating procedure. A pulsed vacuum- arc deposition process was used to deposit a carbon coating on the gears with the plasma incident at a shallow angle to the gears' top surface. A sample bias of -2 keV was used in order to produce a coating with relatively low stress and good adhesion while maintaining high hardness. This coating process is known to be somewhat comformal to the component surfaces. The coating uniformity, particularly in the high-aspect-ratio areas between the gear teeth, was evaluated with micro-Raman spectroscopy. It is shown that the coating can be applied uniformly on the top gear surface. Between the gear teeth the coating was the same thickness as on top of the gear down to a point 50 ~m below the top surface. Below that point (i.e. between 50 and 70 Lm), the coating thickness is somewhat thinner, but is still present. These results demonstrate that it is possible to a deposit hard carbon coating on microgears to reduce friction and wear in micromachines.

  19. The Study of Deep Lithography and Moulding Process of LIGA Technique

    NASA Astrophysics Data System (ADS)

    Guo, Yuhua; Liu, Gang; Kan, Ya; Tian, Yangchao

    2007-01-01

    The knowledge of the development behavior, especially the development rate, is of primary importance for the study of deep x-ray lithography in LIGA technique. In the first part of this paper, we have measured the development rates of crosslinked PMMA foils irradiated in NSRL covering a wide dose range (bottom dose in the range:2.5-8.0 kJ/cm3). After the exposure, we use a so-called period-development method (to dip development in GG-developer for 20 minutes and clean in rinse solution for 40 minutes as a development period). For processing the experiment data, we get the KDβ model to describe our PMMA/GG-developer system. The aim of this work is to find out a stable experiment condition for deep X-ray lithography and development. The result shows that in small amount of dose (bottom dose range: 2.5-4 kJ/cm3), this model is very stable. While in large amount of dose (bottom dose range: 5-8kJ/cm3), the model becomes very sensitive and even unavailable. To verify the conclusion validity, the fixed dose range (bottom dose range: 3.5-4 kJ/cm3) is applied on PMMA microstructures. And the result shows an effective development process. In the following procedure, mold inserts can be produced by micro-electroforming and plastic replicas can be mass produced by hot embossing. To emboss high-aspect-ratio microstructures, the deformation of microstructures usually occurs due to the demolding forces between the sidewall of mold inserts and the thermoplastic (PMMA). To minimize the friction force the optimized experiment has been performed using Ni-PTFE compound material mold inserts. Typical defects like pull-up and damaged edges can be greatly reduced.

  20. Comparison of hemorrhoidectomy by LigaSure with conventional Milligan Morgan’s hemorrhoidectomy

    PubMed Central

    Bakhtiar, Nighat; Moosa, Foad Ali; Jaleel, Farhat; Qureshi, Naeem Akhtar; Jawaid, Masood

    2016-01-01

    Objective: To compare the efficacy of haemorrhoidectomy done by using LigaSure with conventional Milligan Morgan haemorrhoidectomy. Methods: This randomized controlled trial was done at Department of Surgery Dow University Hospital Karachi during January 2013 to September 2015. A total of 55 patients were included in the study. Patients were randomly allocated to group A (Haemorrhoidectomy by Ligasure) and group B (Milligan Morgan Haemorrhoiectomy). Efficacies of both procedures were compared by operative time, Blood loss, wound healing, and pain score on immediate, 1st and 7th post operative day. Results: Out of total 55 patients 23 were male and 32 were females. The most common group of age involved was between 40 – 60 years. Third degree Heamorrhoids were present in 37 (67.3%) of patients while remaining 18 (32.7%) had fourth degree Heamorrhoids. Group A included 29 cases while Group B included 26 cases. The mean operating time of Group A was 52.5 with standard deviation of 11.9 while it was 36.6± 9.8 in the other group. The mean blood loss in group A was 51.92 with standard deviation of 15.68 while it was 70.34±25.59 in group B. Overall pain score was less in those patients who underwent Heamorrhoidectomy by Ligasure method. Conclusion: The efficacy of Heamorrhoidectomy by Ligasure is better than the traditional Milligan Morgan Heamorrhoidectomy but we need more clinical trials with large sample size and long term follow ups. PMID:27375709

  1. Blood loss associated with radical cystectomy: A prospective, randomized study comparing impact LigaSure vs. stapling device☆

    PubMed Central

    Thompson, Ian M.; Kappa, Stephen F.; Morgan, Todd M.; Barocas, Daniel A.; Bischoff, Carl J.; Keegan, Kirk A.; Stratton, Kelly L.; Clark, Peter E.; Resnick, Matthew J.; Smith, Joseph A.; Cookson, Michael S.; Chang, Sam S.

    2014-01-01

    Objectives Radical cystectomy (RC) is associated with significant blood loss and transfusion requirement. We performed a prospective, randomized trial to compare blood loss, operative time, and cost using 2 different and commonly employed approaches to tissue ligation and division during RC: mechanical (stapler device) and electrosurgical (heat-sealing device). Methods and materials Eighty patients undergoing RC for urothelial bladder carcinoma were randomized to use of either an Endo GIA Stapler or Impact LigaSure device for tissue ligation and division. Primary outcomes were blood loss, operative time, and device costs. Data were analyzed with Wilcoxon rank sum test and Welch 2-sample t test. Results There were no significant demographic or preoperative differences between the cohorts. Mean estimated blood loss was similar between the electrosurgical (687 ml) and stapler (708 ml) arms (P = 0.850). There were no significant differences between cohorts when comparing operative times or transfusion requirement. There was a significant increase in the mean number of adjunctive suture ligatures used in the stapling device arm (3.0 vs. 1.5, P = 0.047). Total device costs were significantly lower with the LigaSure compared with the GIA Stapler ($625.00 vs. $1490.10, P < 0.001). There were no complications attributable to either device. Conclusions This prospective, randomized study demonstrates no significant difference in blood loss, transfusion requirement, or safety between mechanical vs. electrosurgical control of the vascular pedicles. The LigaSure device, however, is significantly less costly than the GIA Stapler and required fewer additional measures for hemostasis. PMID:24054870

  2. Optical wafer metrology sensors for process-robust CD and overlay control in semiconductor device manufacturing

    NASA Astrophysics Data System (ADS)

    den Boef, Arie J.

    2016-06-01

    This paper presents three optical wafer metrology sensors that are used in lithography for robustly measuring the shape and position of wafers and device patterns on these wafers. The first two sensors are a level sensor and an alignment sensor that measure, respectively, a wafer height map and a wafer position before a new pattern is printed on the wafer. The third sensor is an optical scatterometer that measures critical dimension-variations and overlay after the resist has been exposed and developed. These sensors have different optical concepts but they share the same challenge that sub-nm precision is required at high throughput on a large variety of processed wafers and in the presence of unknown wafer processing variations. It is the purpose of this paper to explain these challenges in more detail and give an overview of the various solutions that have been introduced over the years to come to process-robust optical wafer metrology.

  3. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  4. On-wafer magnetic resonance of magnetite nanoparticles

    NASA Astrophysics Data System (ADS)

    Little, Charles A. E.; Russek, Stephen E.; Booth, James C.; Kabos, Pavel; Usselman, Robert J.

    2015-11-01

    Magnetic resonance measurements of ferumoxytol and TEMPO were made using an on-wafer transmission line technique with a vector network analyzer, allowing for broadband measurements of small sample volumes (4 nL) and small numbers of spins (1 nmol). On-wafer resonance measurements were compared with standard single-frequency cavity-based electron paramagnetic resonance (EPR) measurements using a new power conservation approach and the results show similar line shape. On-wafer magnetic resonance measurements using integrated microfluidics and microwave technology can significantly reduce the cost and sample volumes required for EPR spectral analysis and allow for integration of EPR with existing lab-on-a-chip processing and characterization techniques for point-of-care medical diagnostic applications.

  5. Silicon-wafer-surface damage revealed by surface photovoltage measurements

    NASA Astrophysics Data System (ADS)

    Goodman, Alvin M.

    1982-11-01

    Anomalous results of surface photovoltage (SPV) measurements on Si wafers are shown to be associated with a damaged region beneath the illuminated surface of the wafer being measured. The anomaly is a concave-upward curvature of the I0(α-1) plot with an r2 value, derived from linear regression analysis, less than the normally observed minimum value (˜0.98). Removal of the damaged region by an appropriate etching procedure allows subsequent SPV measurements whose results are substantially free of the previously observed anomaly. The qualitative character of the anomaly can be reproduced by a simple theoretical model in which only one effect of the damage is considered; this effect is a diminished quantum efficiency for hole-electron pair generation by photon absorption in the damaged region. The results suggest the use of SPV measurements as a test procedure for revealing the presence of surface damage in Si wafers.

  6. Silicon carbide wafer bonding by modified surface activated bonding method

    NASA Astrophysics Data System (ADS)

    Suga, Tadatomo; Mu, Fengwen; Fujino, Masahisa; Takahashi, Yoshikazu; Nakazawa, Haruo; Iguchi, Kenichi

    2015-03-01

    4H-SiC wafer bonding has been achieved by the modified surface activated bonding (SAB) method without any chemical-clean treatment and high temperature annealing. Strong bonding between the SiC wafers with tensile strength greater than 32 MPa was demonstrated at room temperature under 5 kN force for 300 s. Almost the entire wafer has been bonded very well except a small peripheral region and few voids. The interface structure was analyzed to verify the bonding mechanism. It was found an amorphous layer existed as an intermediate layer at the interface. After annealing at 1273 K in vacuum for 1 h, the bonding tensile strength was still higher than 32 MPa. The interface changes after annealing were also studied. The results show that the thickness of the amorphous layer was reduced to half after annealing.

  7. 450mm wafer patterning with jet and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  8. Wafer CD variation for random units of track and polarization

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

    2012-03-01

    After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle

  9. An application of selective electrochemical wafer thinning for silicon characterization

    SciTech Connect

    Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

    1990-01-01

    A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

  10. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    SciTech Connect

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  11. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  12. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  13. Scale

    ERIC Educational Resources Information Center

    Schaffhauser, Dian

    2009-01-01

    The common approach to scaling, according to Christopher Dede, a professor of learning technologies at the Harvard Graduate School of Education, is to jump in and say, "Let's go out and find more money, recruit more participants, hire more people. Let's just keep doing the same thing, bigger and bigger." That, he observes, "tends to fail, and fail…

  14. Metrology study of high precision mm parts made by the deep x-ray lithography (LIGA) technique

    NASA Astrophysics Data System (ADS)

    Mäder, Olaf; Meyer, Pascal; Saile, Volker; Schulz, Joachim

    2009-02-01

    Microcomponents are increasingly applied in industrial products, e.g. smallest gears, springs or the watch industry. Apart from their small dimensions, such components are characterized by a high contour accuracy. Industry requires the tolerances to be in the µm range. Measurement of lateral dimensions in the mm range with submicrometer accuracy and precision, however, results in high requirements on measurement technology. The relevance of this problem is illustrated by the fact that the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) has launched the Collaborative Research Center 1159 on 'New Strategies of Measurement and Inspection for the Production of Microsystems and Nanostructures'. The Institut für Mikrostrukturtechnik, Karlsruhe (Institute of Microstructure Technology, Karlsruhe), produces microstructures by means of the LIG(A) technique (German acronym for lithography, electrodeposition, molding). Presently, a coordinate measurement machine equipped with an optical fiber probe to measure these microstructures is being tested. This paper will particularly focus on the precision and accuracy of the machine. The rules of measurement system analysis will be applied for this purpose. Following the elimination of the systematic error, reproducibility of deep-etch x-ray lithography will be highlighted using the LIGA production of gold gears as an example.

  15. Correlation of the structural properties of a Pt seed layer with the perpendicular magnetic anisotropy features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 junctions via a 12-inch scale Si wafer process

    NASA Astrophysics Data System (ADS)

    Chae, Kyo-Suk; Lee, Du-Yeong; Shim, Tae-Hun; Hong, Jin-Pyo; Park, Jea-Gun

    2013-10-01

    We elucidated the interfacial-perpendicular magnetic anisotropy (i-PMA) features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 magnetic-tunnel-junctions as functions of the structural properties of the Pt seed layer including its thickness and ex situ annealing temperature. All of the samples were prepared in a 12-inch silicon wafer process for real industry applications. The observations of the M-H loops emphasize that a thinner Pt seed layer and a high ex situ annealing temperature enhance the surface roughness of the seed layer, providing better i-PMA characteristics. HR-TEM images of the samples were evaluated to understand the structural effects of thin and thick Pt seed layers.

  16. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    NASA Astrophysics Data System (ADS)

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, Sanghyeon; Choi, Won Jun

    2016-02-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

  17. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    PubMed Central

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  18. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications.

    PubMed

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called "Si photonics"). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  19. Interaction of an argon plasma jet with a silicon wafer

    NASA Astrophysics Data System (ADS)

    Engelhardt, Max; Pothiraja, Ramasamy; Kartaschew, Konstantin; Bibinov, Nikita; Havenith, Martina; Awakowicz, Peter

    2016-04-01

    A filamentary discharge is ignited in an argon plasma jet under atmospheric pressure conditions. The gas discharge is characterized with voltage-current measurements, optical emission spectroscopy and an ICCD-camera with a high temporal resolution down to 10 ns. In the effluent of the plasma jet, filaments come into contact with the surface of a silicon wafer and modify it, namely etching traces are produced and microcrystals are deposited. These traces are studied with optical and electron microscopes. The material of the deposited microcrystals and the surface modifications of the silicon wafer are analyzed with Raman microspectroscopy. Amorphous silicon is found within the etching traces. The largest part of the deposited microcrystals are composed of nitratine (NaNO3) and some of them are calcite (CaCO3). Analyzing the possible reasons for the silicon wafer modifications we come to the conclusion that plasmoids, which are produced near the substrate surface by interaction with ionization waves, are a plausible explanation for the observed surface modifications of the silicon wafer.

  20. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    SciTech Connect

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

  1. A reclaiming process for solar cell silicon wafer surfaces.

    PubMed

    Pa, P S

    2011-01-01

    The low yield of epoxy film and Si3N4 thin-film deposition is an important factor in semiconductor production. A new design system using a set of three lamination-shaped electrodes as a machining tool and micro electro-removal as a precision reclaiming process of the Si3N4 layer and epoxy film removal from silicon wafers of solar cells surface is presented. In the current experiment, the combination of the small thickness of the anode and cathodes corresponds to a higher removal rate for the thin films. The combination of the short length of the anode and cathodes combined with enough electric power produces fast electroremoval. A combination of the small edge radius of the anode and cathodes corresponds to a higher removal rate. A higher feed rate of silicon wafers of solar cells combined with enough electric power produces fast removal. A precise engineering technology constructed a clean production approach for the removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers from solar cells that can reduce pollution and lower cost. PMID:21446525

  2. Multi-wafer slicing with a fixed abrasive

    NASA Technical Reports Server (NTRS)

    Schmid, Frederick (Inventor); Khattak, Chandra P. (Inventor); Smith, Maynard B. (Inventor)

    1988-01-01

    A wafering machine having a multiplicity of wire cutting blades supported by a bladehead reciprocally moving past a workpiece supported by a holder that rocks about an axis perpendicular to the wires at a frequency less than the reciprocation of the bladehead.

  3. Crack propagation and fracture in silicon wafers under thermal stress

    PubMed Central

    Danilewsky, Andreas; Wittge, Jochen; Kiefl, Konstantin; Allen, David; McNally, Patrick; Garagorri, Jorge; Elizalde, M. Reyes; Baumbach, Tilo; Tanner, Brian K.

    2013-01-01

    The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing. PMID:24046487

  4. National solar technology roadmap: Wafer-silicon PV

    SciTech Connect

    Sopori, Bhushan

    2007-06-01

    This report applies to all bulk-silicon-based PV technologies, including those based on Czochralski, multicrystalline, float-zone wafers, and melt-grown crystals that are 100 μm or thicker, such as ribbons, sheet, or spheral silicon.

  5. SUEX process optimization for ultra-thick high-aspect ratio LIGA imaging

    NASA Astrophysics Data System (ADS)

    Johnson, Donald W.; Goettert, Jost; Singh, Varshni; Yemane, Dawit

    2011-04-01

    The focus of this paper is on the use of SUEX Thick Dry Film Sheet (TDFS) laminates which DJ DevCorp is developing as a thick resist material in optical and X-ray lithography. Preliminary thick dry film sheets up to 1mm thickness were successfully prepared and patterned at the CAMD X-ray beamlines and presented at HARMST 2007. Recently, new results have been published using SUEX resist sheets in UV lithography showing great market potential including plating molds for metal microparts, polymer MEMS, multilayer microfluidics structures, BioMEMS, medical devices, wafer level packaging processes, and displays. The SUEX TDFS are available in a range of thicknesses from 100μm to 1mm or more and are pre-cut into a number of standard wafer sizes. This new material is a modified epoxy formulation containing an antimony-free photo acid generator (PAG) prepared under a highly controlled solvent-less process which provides uniform coatings between two throw-away layers of protective polyester film. As part of our initial studies resist layers of 250, 500 and 1000μm were laminated onto regular silicon wafers using a hot roll laminator at a speed of 1ft/min at 75°C. The entire substrate preparation takes about 1 hour and with practice users can prepare up to 10 substrates in this time which are typically ready to use within 2 hours. In our efforts to develop a commercially viable product we have conducted experiments using standard equipment available at CAMD (Quintel UV aligner and CAMD XRLM 1 and 4 beamline). Initial X-ray exposure tests were done with a bottom dose ranging between 100 and 400 J/cm3 and a top/bottom dose ratio of less than 3 for sheets up to 2mm in thickness. Exposure time for typical conditions of the CAMD storage ring (ring current ranging between 100 and 160mA, beam lifetime of about 10hrs at 100mA ring current) is about 10-15min for a 4' wafer. After exposure the samples were immediately post exposure baked between 70°C and 110°C using a convection

  6. Virtual fab flow for wafer topography aware OPC

    NASA Astrophysics Data System (ADS)

    Stock, Hans-Jürgen; Bomholt, Lars; Krüger, Dietmar; Shiely, James; Song, Hua; Voznesenskiy, Nikolay

    2010-04-01

    Small feature sizes down to the current 45 nm node and precision requirements of patterning in 193 nm lithography as well as layers where the wafer stack does not allow any BARC require - not only correction of optical proximity (OPC) effects originating from mask topography and imaging system, but also correction of wafer topography proximity (WTPC) effects as well. In spite of wafer planarization process steps, wafer topography (proximity) effects induced by different optical properties of the patterned materials start playing a significant role, and correction techniques need to be applied in order to minimize the impact. In this paper, we study a methodology to create fast models intended for effective use in OPC and WTPC procedures. In order to be short we use the terms "OPCWTPC modeling" and "OPCWTPC models" through the paper although it would be more correctly to take the terms "mask synthesis modeling" and "mask synthesis models". A comprehensive data set is required to build a reliable OPC model. We present a "virtual fab" concept using extensive test pattern sets with both 1D and 2D structures to capture optical proximity effects as well as wafer topography effects. A rigorous lithography simulator taking into account exposure tool source maps, topographic mask effects as well as wafer topography is used to generate virtual measurement data, which are used for model calibration as well as for model validation. For model building, we use a two step approach: in a first step, an OPC model is built using test patterns on a planar, homogenous substrate; in a second step a WTPC model is calibrated, using results from simulated test patterns on shallow trench isolation (STI) layer. This approach allows building models from experimental data, including hybrid approaches where only experimental data from planar substrates is available and a corresponding OPC model for the planar case can be retrofitted with capabilities for correcting wafer topography effects. We

  7. Bonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits

    NASA Astrophysics Data System (ADS)

    Kim, Hyun S.; Blick, Robert H.; Kim, D. M.; Eom, C. B.

    2004-09-01

    We report a method for bonding silicon-on-insulator wafers onto glass wafers. After pre-cleaning the wafers by an ozone and ultraviolet exposure, followed by mega-sonic water rinse, the SOI wafers are bonded to glass wafers in a vacuum chamber. This is performed at a temperature of 400 °C under an applied voltage of 700 V. The interface between the glass and SOI wafer is tested mechanically and inspected by electron beam microscopy. Furthermore, we demonstrate removal of the silicon bulk layer after wafer bonding. The quality of the single crystalline Si thin film on the glass wafers has been verified by four-circle x-ray diffraction and scanning electron microscopy. This process will allow us the integration of thin-film electronics in biological sensor applications.

  8. Transparent masks for aligned deep x-ray lithography/LIGA: low-cost high-performance alternative using glass membranes

    NASA Astrophysics Data System (ADS)

    Kupka, Roland K.; Megtert, Stephan; Roulliay, Marc; Bouamrane, Faycal

    1998-09-01

    Deep x-ray lithography/LIGA has proven to be a well established framework of x-ray based technologies for the fabrication of microstructures and pseudo three-dimensional objects. Inherently, x-ray lithography/LIGA is not fully three-dimensional because of the principle of simple shadow printing onto resists of constant thickness. Thus, it would be impossible to obtain 3D spheres, but series of stacked monolithic 2D cylinders. Hence, until recently, LIGA was mainly concerned with simple uni-level (1D) monolithic structures, using optically opaque mask-membranes like Be, Si or Ti with grown-on Au absorbers. In the course for mastering pseudo three-dimensional microstructures like micro-coils or electromagnetic applications, an alignment in between the lithographic steps becomes necessary which requires optically transparent membrane materials, if optical alignment is chosen. Diamond or SiC membranes are the actual suitable materials for such purposes, but their pricing and/or process robustness inhibit their frequent use in simple projects. We would like to report on a new promising material: a glued-on thin glass membrane. The advantages are incomparably lower costs compared to Diamond or SiC technologies, a considerable ease of fabrication, handling, quite favorable mechanical/optical properties, sufficient for lithographic purposes and multi-level deep x-ray lithography/LIGA activities.

  9. Acquisition of negative complement regulators by the saprophyte Leptospira biflexa expressing LigA or LigB confers enhanced survival in human serum.

    PubMed

    Castiblanco-Valencia, Mónica M; Fraga, Tatiana R; Breda, Leandro C D; Vasconcellos, Sílvio A; Figueira, Cláudio P; Picardeau, Mathieu; Wunder, Elsio; Ko, Albert I; Barbosa, Angela S; Isaac, Lourdes

    2016-05-01

    Leptospiral immunoglobulin-like (Lig) proteins are surface exposed molecules present in pathogenic but not in saprophytic Leptospira species. We have previously shown that Lig proteins interact with the soluble complement regulators Factor H (FH), FH like-1 (FHL-1), FH related-1 (FHR-1) and C4b Binding Protein (C4BP). In this study, we used the saprophyte L. biflexa serovar Patoc as a surrogate host to address the specific role of LigA and LigB proteins in leptospiral complement evasion. L. biflexa expressing LigA or LigB was able to acquire FH and C4BP. Bound complement regulators retained their cofactor activities of FI in the proteolytic cleavage of C3b and C4b. Moreover, heterologous expression of ligA and ligB genes in the saprophyte L. biflexa enhanced bacterial survival in human serum. Complement deposition on lig-transformed L. biflexa was assessed by flow cytometry analysis. With regard to MAC deposition, L. biflexa expressing LigA or LigB presented an intermediate profile: MAC deposition levels were greater than those found in the pathogenic L. interrogans, but lower than those observed for L. biflexa wildtype. In conclusion, Lig proteins contribute to in vitro control of complement activation on the leptospiral surface, promoting an increased bacterial survival in human serum. PMID:26976804

  10. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    SciTech Connect

    Qiusheng, Y. Senkai, C. Jisheng, P.

    2015-03-30

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  11. Scales

    ScienceCinema

    Murray Gibson

    2010-01-08

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain ? a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  12. Scales

    SciTech Connect

    Murray Gibson

    2007-04-27

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain — a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  13. Enhanced capture rate for haze defects in production wafer inspection

    NASA Astrophysics Data System (ADS)

    Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

    2010-03-01

    Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure

  14. Mask blank defect printability comparison using optical and SEM mask and wafer inspection and bright field actinic mask imaging

    NASA Astrophysics Data System (ADS)

    Mangat, Pawitter; Verduijn, Erik; Wood, Obert R.; Benk, Markus P.; Wojdyla, Antoine; Goldberg, Kenneth A.

    2015-07-01

    Despite significant enhancements in defect detection using optical and e-beam methodology, the smaller length scales and increasing challenges of future technology nodes motivate ongoing research into the need and associated cost of actinic inspection for EUV masks. This paper reports an extensive study of two EUV patterned masks, wherein the mask blank defectivity was characterized using optical (mask and wafer) methods and bright-field mask imaging (using the SHARP actinic microscope) of previously identified blank defects. We find that the bright field actinic imaging tool microscope captures and images many defects that are not seen by the automated optical inspection of patterned masks and printed wafers. In addition, actinic review reveals the impact of multilayer damage and depicts the printability profile which can be used as an added metric to define the patterned mask repair and defect compensation strategies.

  15. Height inspection of wafer bumps without explicit 3D reconstruction

    NASA Astrophysics Data System (ADS)

    Dong, Mei; Chung, Ronald; Zhao, Yang; Lam, Edmund Y.

    2006-02-01

    The shrunk dimension of electronic devices leads to more stringent requirement on process control and quality assurance of their fabrication. For instance, direct die-to-die bonding requires placement of solder bumps not on PCB but on the wafer itself. Such wafer solder bumps, which are much miniaturized from the counterparts on PCB, still need to have their heights meet the specification, or else the electrical connection could be compromised, or the dies be crushed, or even the manufacturing equipments be damaged. Yet the tiny size, typically tens of microns in diameter, and the textureless and mirror nature of the bumps pose great challenge to the 3D inspection process. This paper addresses how a large number of such wafer bumps could have their heights massively checked against the specification. We assume ball bumps in this work. We propose a novel inspection measure about the collection of bump heights that possesses these advantages: (1) it is sensitive to global and local disturbances to the bump heights, thus serving the bump height inspection purpose; (2) it is invariant to how individual bumps are locally displaced against one another on the substrate surface, thus enduring 2D displacement error in soldering the bumps onto the wafer substrate; and (3) it is largely invariant to how the wafer itself is globally positioned relative to the imaging system, thus having tolerance to repeatability error in wafer placement. This measure makes use of the mirror nature of the bumps, which used to cause difficulty in traditional inspection methods, to capture images of two planes. One contains the bump peaks and the other corresponds to the substrate. With the homography matrices of these two planes and fundamental matrix of the camera, we synthesize a matrix called Biplanar Disparity Matrix. This matrix can summarize the bumps' heights in a fast and direct way without going through explicit 3D reconstruction. We also present a design of the imaging and

  16. Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

    NASA Astrophysics Data System (ADS)

    Altan, Hakan

    All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on

  17. Single incision cholecystectomy using a clipless technique with LigaSure in a resource limited environment: The Bahamas experience

    PubMed Central

    Downes, Ross O.; McFarlane, Michael; Diggiss, Charles; Iferenta, James

    2015-01-01

    Background Scarless/single-incision laparoscopic cholecystectomy (SILC) is a new procedure. It affords a superior cosmetic outcome when compared to conventional laparoscopic cholecystectomy. We examine the application of this technique using LigaSure via a clipless method. The present study looks at the experience of a single surgeon using this method with initial evaluation of the safety, feasibility, affordability, and benefits of this procedure. Methods Twenty-eight patients underwent transumbilical SILC at Doctors Hospital from January to December, 2014. The cohort included both emergency and elective patients. There was no difference in the preoperative work-up as indicated. To perform the operation, a 2–2.5-cm linear incision was made through the umbilicus and the single port platform utilized. A 10 mm 30-degree laparoscope, a 5 mm LigaSure and straight instruments were used to perform the laparoscopic cholecystectomy procedure. Results All patients except two were operated on successfully. Conversion was considered the placement of an additional epigastric/Right upper quadrant (RUQ) port. The conversion rate to standard LC was 7%. No patient was converted to open cholecystectomy. In the 28 successfully completed patients, the median duration of the operation was 38.5 min and estimated operative blood loss was 24 ml. Patients were commenced on liquid diet immediately on being fully conscious and after return to the ward with an estimated time of 6 h. The mean postoperative hospital stay was 1.4 days. Follow-up visits were conducted for all patients at 2-weeks intervals and continued for 6 weeks after surgery where possible. Two patients developed wound infections. All patients were satisfied with the good cosmetic effect of the surgery. The total satisfaction rate was 100%. Conclusions SILC is a safe and feasible technique for operating with scarless outcomes and reducing perioperative discomfort at the same time. The GelPOINTTM is a safe and feasible

  18. Characterization, modeling, and design of an electrostatic chuck with improved wafer temperature uniformity

    NASA Astrophysics Data System (ADS)

    Olson, Kurt A.; Kotecki, David E.; Ricci, Anthony J.; Lassig, Stephan E.; Husain, Anwar

    1995-02-01

    The resulting temperature distribution of a silicon wafer held by an electrostatic chuck (ESC) in an electron-cyclotron-resonance chemical vapor deposition (ECR-CVD) reactor is characterized and modeled. The effects of the clamping voltage VESC, pressure between the ESC and wafer PHe, and the surface finish and pattern on the ESC are investigated. Heat transfer coefficients between the wafer and various ESCs are determined experimentally. A model is developed to predict the temperature distribution at the surface of the wafer, and used to explain the experimentally observed temperature variations both within wafer and between different chucks. The model is then used to aid in the design of an ESC which provides improved temperature uniformity at the wafer surface. The results of this study indicate: (a) the thermal resistances across the interface between the wafer and ESC control both the absolute wafer temperature and the wafer temperature uniformity; (b) the surface roughness of the ESC and the size of the ``contact'' regions are major design factors controlling the absolute temperature of the wafer—the temperature can be adjusted by varying the value of VESC and fine tuned by adjusting the value of PHe; (c) the nonuniform temperature distribution across the wafer surface is dictated by the surface pattern on the ESC, the variation in surface roughness, and the size of the ESC relative to the wafer; (d) wafer temperature variations from chuck to chuck are reduced by controlling the surface finish of the ESC and by ensuring that PHe is a dominant heat transfer mechanism; and (e) maximum uniformity in the temperature of the wafer is obtained when the radius of the ESC is matched as closely as possible to that of the wafer. We have shown that numerical heat transfer models can be used to optimize the geometry of the ESC to provide a uniform distribution of temperature across the surface of the wafer.

  19. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Luo, Xianshu; Cao, Yulian; Song, Junfeng; Hu, Xiaonan; Cheng, Yungbing; Li, Chengming; Liu, Chongyang; Liow, Tsung-Yang; Yu, Mingbin; Wang, Hong; Wang, Qijie; Lo, Patrick Guo-Qiang

    2015-04-01

    Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS) fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W) bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP) laser, lateral-coupled distributed feedback (LC-DFB) laser with side wall grating, and mode-locked laser (MLL). From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC).

  20. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    NASA Astrophysics Data System (ADS)

    Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

    2016-02-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

  1. A hermetic and room-temperature wafer bonding technique based on integrated reactive multilayer systems

    NASA Astrophysics Data System (ADS)

    Braeuer, J.; Gessner, T.

    2014-11-01

    This paper focuses on direct deposition and patterning of reactive and nano-scale multilayer films at wafer level. These multilayer structures are called integrated reactive material systems (iRMS). In contrast to the typically used nickel (Ni)/ aluminum (Al) systems, in this work we needed to have our total multilayer film thicknesses smaller than 2.5 µm to reduce stress within the multilayer as well as deposition costs. Thus, we introduced new high energetic iRMS. These films were deposited by using alternating magnetron sputtering from high purity Al- and palladium (Pd)-targets to obtain films with a defined Al:Pd atomic ratio. In this paper, we present the result for reaction characteristics and reaction velocities which were up to 72.5 m s-1 for bond frames with lateral dimensions as low as 20 µm. Furthermore, the feasibility of silicon (Si)-Si, Si-glass as well as Si-ceramic hermetic and metallic wafer bonding at room temperature is presented. We show that by using this bond technology, strong (maximum shear strengths of 235 MPa) and hermetically sealed bond interfaces can be achieved without any additional solder material.

  2. Wafer-level packaging with compression-controlled seal ring bonding

    SciTech Connect

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  3. A gas chromatographic air analyzer fabricated on a silicon wafer

    NASA Technical Reports Server (NTRS)

    Terry, S. C.; Jerman, J. H.; Angell, J. B.

    1979-01-01

    A miniature gas analysis system has been built based on the principles of gas chromatography (GC). The major components are fabricated in silicon using photolithography and chemical etching techniques, which allows size reductions of nearly three orders of magnitude compared to conventional laboratory instruments. The chromatography system consists of a sample injection valve and a 1.5-m-long separating capillary column, which are fabricated on a substrate silicon wafer. The output thermal conductivity detector is separately batch fabricated and integrably mounted on the substrate wafer. The theory of gas chromatography has been used to optimize the performance of the sensor so that separations of gaseous hydrocarbon mixtures are performed in less than 10 s. The system is expected to find application in the areas of portable ambient air quality monitors, implanted biological experiments, and planetary probes.

  4. A silicon wafer packaging solution for HB-LEDs

    NASA Astrophysics Data System (ADS)

    Murphy, Tom; Weichel, Steen; Isaacs, Steven; Kuhmann, Jochen

    2007-09-01

    In this paper we present HyLED, a silicon wafer packaging solution for high-brightness LEDs. The associated technology is batch micro-machining/metallisation processing of silicon wafers allowing significant reduction of the final device size. The presented package is multi-functional where the micro-machined cavity acts as reflector, thermal conductor and reservoir for the silicone/colour conversion substance. The base material, silicon, has excellent mechanical and thermal properties and enables direct integration of intelligence. We present customer specific solutions, open tool samples and performance data for optical and thermal parameters and reliability testing. Thermal resistance values of R<5 K/W, junction-to-board are demonstrated.

  5. Chemical method for producing smooth surfaces on silicon wafers

    SciTech Connect

    Yu, Conrad

    2003-01-01

    An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

  6. Sputter deposition of SiC coating on silicon wafers

    NASA Technical Reports Server (NTRS)

    Robson, M. T.; Blue, C. A.; Warrier, S. G.; Lin, R. Y.

    1992-01-01

    A study is conducted of the effect of substrate temperature during coating on the properties of coated SiC films on Si wafers, using a scratch test technique. While specimen temperature during coating has little effect on deposition rate, it significantly affects the durability of the coating. Scratch test damage to both film coating and substrate decreased with increasing deposition temperature, perhaps due to the rapid diffusion of the deposited atoms.

  7. High resolution inspection with wafer plane die: database defect detection

    NASA Astrophysics Data System (ADS)

    Hess, Carl; Wihl, Mark; Shi, Rui-fang; Xiong, Yalin; Pang, Song

    2008-10-01

    High Resolution reticle inspection is well-established as a proven, effective, and efficient means of detecting yieldlimiting mask defects as well as defects which are not immediately yield-limiting yet can enable manufacturing process improvements. Historically, RAPID products have enabled detection of both classes of these defects. The newlydeveloped Wafer Plane Inspection (WPI) detector technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. Wafer Plane Inspection accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. This has the effect of reducing sensitivity to non-printing defects while enabling higher sensitivity focused in high MEEF areas where small reticle defects still yield significant printing defects on wafers. This approach has several important features. The ability to ignore non-printing defects and to apply additional effective sensitivity in high MEEF areas enables advanced node development. In addition, the modeling allows the inclusion of important polarization effects that occur in the resist for high NA operation. This allows for the results to better match wafer print results compared to alternate approaches. Finally, the simulation easily allows for the application of arbitrary illumination profiles. With this approach, users of WPI can make use of unique or custom scanner illumination profiles. This allows the more precise modeling of profiles without inspection system hardware modification or loss of company intellectual property. A previous paper [1] introduced WPI in D:D mode. This paper examines the operation and results for WPI in Die:Database mode.

  8. Cost of Czochralski wafers as a function of diameter

    SciTech Connect

    Leipold, M.H.; Radics, C.; Kachare, A.

    1980-02-15

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots is analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size are estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/m/sup 2/ (1980 $) depending upon technique used.

  9. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    NASA Astrophysics Data System (ADS)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  10. Influence of the bonding front propagation on the wafer stack curvature

    SciTech Connect

    Navarro, E.; Bréchet, Y.; Barthelemy, A.; Radu, I.; Pardoen, T.; Raskin, J.-P.

    2014-08-11

    The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

  11. A photo-sensor on thin polysilicon membrane embedded in wafer level package LED

    NASA Astrophysics Data System (ADS)

    Kim, Jin Kwan; Lee, Hee Chul

    2012-06-01

    A wafer level packaging LED with photo-sensor which is fabricated on thin poly-silicon membrane located on the corner of silicon cavity is presented in this paper. The wafer substrate was fabricated with (100) orientation silicon wafer and a cavity was etched on the top of the wafer with wet chemical anisotropic etching process for mounting a LED chip. A thin polysilicon membrane was fabricated on the corner of the cavity and a MSM (Metal Semiconductor Metal) type photo-sensor was fabricated on the thin polysilicon membrane. The photo-sensor fabrication and LED packaging were completed on wafer level. The embedded photo-sensor in a wafer level packaging LED is designed to measure light intensity of a LED. The membrane structure photo-sensor can sense the light of the mounted LED directly, so it can measure accurate light intensity of the wafer level packing LED.

  12. Physical mechanisms of copper-copper wafer bonding

    SciTech Connect

    Rebhan, B.; Hingerl, K.

    2015-10-07

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing.

  13. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, C.M.; Hui, W.C.

    1996-11-19

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

  14. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, Conrad M.; Hui, Wing C.

    1996-01-01

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

  15. Wettability investigating on the wet etching textured multicrystalline silicon wafer

    NASA Astrophysics Data System (ADS)

    Liu, Xiangju; Niu, Yuchao; Zhai, Tongguang; Ma, Yuying; Zhen, Yongtai; Ma, Xiaoyu; Gao, Ying

    2016-02-01

    In order to investigate the wettability properties of multicrystalline silicon (mc-Si), the different surface structures were fabricated on the as-cut p-type multi-wire slurry sawn mc-Si wafers, such as as-cut, polished and etched in various acid solutions. The contact angles and the XRD spectra of these samples were measured. It was noted that both the surface structures and the use of surfactant, such as Tween 80, made a stronger effect on wettability of the Si wafer. Due to the lipophilic groups of Tween 80 combined with the Si atoms while the hydrophilic groups of it were outward, a lipophilic surface of Si changed into a hydrophilic one and the rougher the surface, the stronger the hydrophily. Thus, it is feasible to add an appropriate surfactant into the etching solution during black-Si wafer fabrication for solar cells. In addition, different crystal plains of Si had different dangling bond density, so that their surface energies were different. A surface with higher surface energy could attract more water atoms and its wettability was better. However, the effect of crystal plain on the surface wettability was much weaker than surface morphology.

  16. Miniaturized fiber optical switches with nonmoving polymeric mirrors for tele- and data-communication networks fabricated using the LIGA technology

    NASA Astrophysics Data System (ADS)

    Neumeier, Michel; Ehrfeld, Wolfgang; Jaeger, Jutta; Picard, Antoni; Schulze, Jens

    1998-03-01

    Fiber optical switches for telecom and datacom purposes become more and more important with the growth of fiber- based networks. This paper proposes a new principle for manipulating optical light paths through switchable, but non-moving polymeric mirrors in free-space optical interconnects. To achieve this a polymeric body and a thin liquid film are moved within a cavity. By moving the body up and down perpendicular to the light path the cavity wall can be switched from total reflective to transmissive state while the liquid film remains between body and wall due to capillary forces. The body can be moved with integrated electro-magnetic actuators and so the whole concept allows the realization of very compact switching elements. The coupling of single mode optical fibers requires a lateral and angular alignment precision in the micron and millirad range for both direct coupling and expanded beam coupling concepts. To meet these requirements, the LIGA technology provides a promising approach with respect to the high precision and also low-cost fabrication by mass replication processes. The combination of LIGA technology with other precision machining technologies allows the fabrication of miniaturized systems with both micro-optic and micromechanic components which fulfill the required tolerances for optical coupling. First demonstrators of 1 X 2 and 2 X 2 switches with bistable electro-magnetic actuators have been fabricated to show the feasibility of the proposed principle. The measured insertion loss is less than 2 dB at 1300 nm with -40 dB crosstalk. The switching time was measured 100 ms. The capabilities of the proposed non-moving mirror principle can be applied to 1 X 2 repair switches for the access area as well as to FDDI-switching-nodes up to compact N X M cross-connect switches for reconfiguration purposes or parallel interconnects to optical backplanes for the office area.

  17. Investigation of optimized wafer sampling with multiple integrated metrology modules within photolithography equipment

    NASA Astrophysics Data System (ADS)

    Taylor, Ted L.; Makimura, Eri

    2007-03-01

    Micron Technology, Inc., explores the challenges of defining specific wafer sampling scenarios for users of multiple integrated metrology modules within a Tokyo Electron Limited (TEL) CLEAN TRACK TM LITHIUS TM. With the introduction of integrated metrology (IM) into the photolithography coater/developer, users are faced with the challenge of determining what type of data is required to collect to adequately monitor the photolithography tools and the manufacturing process. Photolithography coaters/developers have a metrology block that is capable of integrating three metrology modules into the standard wafer flow. Taking into account the complexity of multiple metrology modules and varying across-wafer sampling plans per metrology module, users must optimize the module wafer sampling to obtain their desired goals. Users must also understand the complexity of the coater/developer handling systems to deliver wafers to each module. Coater/developer systems typically process wafers sequentially through each module to ensure consistent processing. In these systems, the first wafer must process through a module before the next wafer can process through a module, and the first wafer must return to the cassette before the second wafer can return to the cassette. IM modules within this type of system can reduce throughput and limit flexible wafer selections. Finally, users must have the ability to select specific wafer samplings for each IM module. This case study explores how to optimize wafer sampling plans and how to identify limitations with the complexity of multiple integrated modules to ensure maximum metrology throughput without impact to the productivity of processing wafers through the photolithography cell (litho cell).

  18. Bulk Laser Material Modification: Towards a Kerfless Laser Wafering Process

    NASA Astrophysics Data System (ADS)

    LeBeau, James

    Due to the ever increasing relevance of finer machining control as well as necessary reduction in material waste by large area semiconductor device manufacturers, a novel bulk laser machining method was investigated. Because the cost of silicon and sapphire substrates are limiting to the reduction in cost of devices in both the light emitting diode (LED) and solar industries, and the present substrate wafering process results in >50% waste, the need for an improved ingot wafering technique exists. The focus of this work is the design and understanding of a novel semiconductor wafering technique that utilizes the nonlinear absorption properties of band-gapped materials to achieve bulk (subsurface) morphological changes in matter using highly focused laser light. A method and tool was designed and developed to form controlled damage regions in the bulk of a crystalline sapphire wafer leaving the surfaces unaltered. The controllability of the subsurface damage geometry was investigated, and the effect of numerical aperture of the focusing optic, energy per pulse, wavelength, and number of pulses was characterized for a nanosecond pulse length variable wavelength Nd:YAG OPO laser. A novel model was developed to describe the geometry of laser induced morphological changes in the bulk of semiconducting materials for nanosecond pulse lengths. The beam propagation aspect of the model was based on ray-optics, and the full Keldysh multiphoton photoionization theory in conjuncture with Thornber's and Drude's models for impact ionization were used to describe high fluence laser light absorption and carrier generation ultimately resulting in permanent material modification though strong electron-plasma absorption and plasma melting. Although the electron-plasma description of laser damage formation is usually reserved for extremely short laser pulses (<20 ps), this work shows that it can be adapted for longer pulses of up to tens of nanoseconds. In addition to a model

  19. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    SciTech Connect

    Daix, N. Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup −2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  20. The optimization of FA/O barrier slurry with respect to removal rate selectivity on patterned Cu wafers

    NASA Astrophysics Data System (ADS)

    Yi, Hu; Yan, Li; Yuling, Liu; Yangang, He

    2016-02-01

    Because the polishing of different materials is required in barrier chemical mechanical planarization (CMP) processes, the development of a kind of barrier slurry with improved removal rate selectivity for Cu/barrier/TEOS would reduce erosion and dishing defects on patterned Cu wafers. In this study, we developed a new benzotriazole-free barrier slurry named FA/O barrier slurry, containing 20 mL/L of the chelating agent FA/O, 5 mL/L surfactant, and a 1:5 concentration of abrasive particles. By controlling the polishing slurry ingredients, the removal rate of different materials could be controlled. For process integration considerations, the effect of the FA/O barrier slurry on the dielectric layer of the patterned Cu wafer was investigated. After CMP processing by the FA/O barrier slurry, the characteristics of the dielectric material were tested. The results showed that the dielectric characteristics met demands for industrial production. The current leakage was of pA scale. The resistance and capacitance were 2.4 kω and 2.3 pF, respectively. The dishing and erosion defects were both below 30 nm in size. CMP-processed wafers using this barrier slurry could meet industrial production demands. Project supported by the Special Project Items No. 2 in National Long-Term Technology Development Plan (No. 2009ZX02308), the Natural Science Foundation of Hebei Province (No. F2012202094), and the Doctoral Program Foundation of Xinjiang Normal University Plan (No. XJNUBS1226).

  1. Wafer level hermetic package and device testing of a SOI-MEMS switch for biomedical applications

    NASA Astrophysics Data System (ADS)

    Receveur, Rogier A. M.; Zickar, Michael; Marxer, Cornel; Larik, Vincent; de Rooij, Nicolaas F.

    2006-04-01

    We have designed a wafer level chip scale package for a bi-stable SOI-MEMS dc switch using a silicon-glass hermetic seal with through the lid feedthroughs. Bonded at 365 °C, 230 V and 250 kg, they pass the fine/gross leak test after thermal cycling and mechanical shock/vibration according to MIL-STD-833, fulfilling the requirements for biomedical applications. The measured shear strength is 114 ± 26 N in correspondence with the theoretically expected 100 N. Ruthenium microcontacts are a factor of 100 more robust than gold microcontacts, being stable over 106 cycles measured in a N2 atmosphere inside the package presented here. Future work will include a more extensive bond quality assessment and continued microcontact reliability measurements.

  2. Non-Contact, No Wafer Preparation Deep Level Transient Spectroscopy Based on Surface Photovoltage

    NASA Astrophysics Data System (ADS)

    Lagowski, Jacek; Morawski, Andrzej; Edelman, Piotr

    1992-08-01

    We discuss a novel approach to Deep Level Transient Spectroscopy (DLTS) in which the emission of trapped minority carriers is analyzed employing the surface photovoltage (SPV) transient as measured in a non-contact manner on the native depletion barrier on semiconductor surfaces. Optical excitation is used as the trap-filling pulse. Experiments done on n-type GaAs demonstrate that the SPV-DLTS is suitable for wafer-scale, non-contact determination of deep level defects on semiconductor surfaces. The SPV approach can monitor emission rates up to 106 s-1 which is 102 to 103 above the limit of standard capacitance DLTS. The sensitivity of the method is comparable to that of the oplical capacitance DLTS.

  3. Homogeneous transparent conductive ZnO:Ga by ALD for large LED wafers

    NASA Astrophysics Data System (ADS)

    Szabó, Zoltán; Baji, Zsófia; Basa, Péter; Czigány, Zsolt; Bársony, István; Wang, Hsin-Ying; Volk, János

    2016-08-01

    Highly conductive and uniform Ga doped ZnO (GZO) films were prepared by atomic layer deposition (ALD) as transparent conductive layers for InGaN/GaN LEDs. The optimal Ga doping concentration was found to be 3 at%. Even for 4" wafers, the TCO layer shows excellent homogeneity of film resistivity (0.8 %) according to Eddy current and spectroscopic ellipsometry mapping. This makes ALD a favourable technique over concurrent methods like MBE and PLD where the up-scaling is problematic. In agreement with previous studies, it was found that by an annealing treatment the quality of the GZO/p-GaN interface can be improved, although it causes the degradation of TCO conductivity. Therefore, a two-step ALD deposition technique was proposed and demonstrated: a "buffer layer" deposited and annealed first was followed by a second deposition step to maintain the high conductivity of the top layer.

  4. Thermomechanical Reliability Study of Benzocyclobutene Film in Wafer-Level Chip-Size Package

    NASA Astrophysics Data System (ADS)

    Lee, K.-O.

    2012-04-01

    A new wafer-level chip-scale package process for high-performance, low-cost packaging has been developed based on passivation with low dielectric constant. This process is simpler and shorter when using permanent photosensitive benzocyclobutene (BCB) compared with the conventional process. However, cracks nucleating on the BCB cause serious reliability problems. The major reasons for cracking of the BCB layer seem to be both thermal stress and a shortage of BCB cross-linking agent (cyclobutene). The stress was reduced by optimizing the thickness of the BCB layer and the underlying stress buffer layer. The BCB cracking resistance was improved by creating more cross-linking agent at the final curing process through modification of the photolithography processes.

  5. Wafer shape compensation at the track PEB for improved CD uniformity

    NASA Astrophysics Data System (ADS)

    Michaelson, Timothy; Dai, Junyan; Chen, Lu; Cervera, Hiram; Lue, Brian; Herchen, Harald; Vellore, Kim; Bekiaris, Nikolaos

    2008-03-01

    This paper investigates the feasibility of using an electrostatic chuck (ESC) on a post exposure bake (PEB) plate in the track to improve the critical dimension uniformity (CDU) for bowed wafers. Although it is more conventional to consider vacuum chucking during PEB, electrostatic chucking offers some potential advantages, chief among which is the fact that electrostatic chucking does not require any type of a seal between the wafer and the PEB plate whereas vacuum chucking does. Such a seal requires contact and therefore has the potential to generate backside particles on the wafer. Electrostatic chucking therefore has the potential for a cleaner overall process. Three different PEB plates were tested in the course of this investigation, a non-chucking PEB plate (SRHP), a PEB plate equipped with a vacuum chuck (VRHP), and a PEB plate equipped with an ESC (eBHP). It was found that CD uniformities were up to 84 percent lower for bowed wafers that were chucked during PEB relative to wafers that were not chucked. In every case tested, wafers processed through chucking PEB plates showed lower CDUs than wafers processed through the non-chucking plate. CDU results were similar between vacuum chucked wafers and electrostatic chucked wafers. Based on the results presented in this paper, it can be concluded that electrostatic chucking during PEB is a feasible method for controlling CD uniformities on bowed wafers.

  6. Transfer of InP epilayers by wafer bonding

    NASA Astrophysics Data System (ADS)

    Hjort, Klas

    2004-08-01

    Wafer bonding increases the freedom of design in the integration of dissimilar materials. For example, it is interesting to combine III-V compounds that have direct band gap and high mobility with silicon (Si) that is extensively used in microelectronic applications. The interest to integrate III-V-based materials with Si arises primarily from two types of applications: smart pixels for optical intra- and inter-chip interconnects in the so-called optoelectronic integrated circuits, and optoelectronic devices using some material advantages of combining III-V with Si. Also, in the III-V industry larger substrates are crucial for higher efficiency in high-volume production, and especially so for monolithic microwave integrated circuits (MMIC). For indium phosphide (InP) the development of large-area substrates has not been able to keep up with market demands. One way to circumvent this problem is to use silicon substrates that are large-area, low-cost, and mechanically strong with high thermal conductivity. In addition, silicon is transparent at the emission wavelengths most often used in InP-based optoelectronics. Unfortunately, the large lattice-mismatch, 8.1%, between silicon and InP, has limited the success of heteroepitaxial growth. Hence, one alternative to be reviewed is InP-to-Si wafer bonding. When a direct semiconductor interface is not needed there are several other means of wafer bonding, e.g. adhesive, eutectic, and solid-state. These processes can be used for direct integration of small islets of epitaxially thin InP microelectronics onto other substrates, e.g. by transferring of InP-based epilayers to a Si-based microwave circuit by pick-and-place, BCB resist adhesive bonding and sacrificing of the InP substrate.

  7. High transmittance silicon terahertz polarizer using wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Yu, Ting-Yang; Tsai, Hsin-Cheng; Wang, Shiang-Yu; Luo, Chih-Wei; Chen, Kuan-Neng

    2015-08-01

    Due to the difficulties faced in fabricating robust Terahertz (THz) optical components with low Fresnel reflection loss, the need to increase the efficiency of THz system with reduced cost is still considered as one of the most essential tasks. In this report, a new low cost THz polarizer with robust structure is proposed and demonstrated. This new THz wire grid polarizer was based on an anti-reflection (AR) layer fabricated with low temperature metal bonding and deep reactive ion etching (DRIE). After patterning Cu wire gratings and the corresponding In/Sn solder ring on the individual silicon wafers, the inner gratings were sealed by wafer-level Cu to In/Sn guard ring bonding, providing the protection against humidity oxidation and corrosion. With the low eutectic melting point of In/Sn solder, wafers could be bonded face to face below 150°C. Two anti-reflection layers on both outward surfaces were fabricated by DRIE. With the mixing of empty holes and silicon, the effective refractive index was designed to be the square root of the silicon refractive index. The central frequency of the anti-reflection layers was designed between 0.5THz to 2THz with an approximate bandwidth of 0.5THz. The samples were measured with a commercial free-standing wire grid polarizer by a THz time domain spectroscopy (THz-TDS) from 0.2THz to 2.2THz. The power transmittance is close to 100% at central frequency. Extinction ratio of the polarizer is between 20dB to 40dB depending on the frequency. The advantages of this new polarizer include high transmittance, robust structure and low cost with no precision optical alignment required.

  8. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  9. Self-assembly of Epitaxial Monolayers for Vacuum Wafer Bonding.

    NASA Astrophysics Data System (ADS)

    Altfeder, Igor; Huang, Biqin; Appelbaum, Ian; Walker, Barry

    2007-03-01

    Self-assembled epitaxial metal monolayers can be used for hetero-integration of mismatched semiconductors, leading to simultaneously low interfacial resistance and high optical transparency. Lattice-mismatched wafers of Si(100) and Si(111) were bonded at room temperature in situ after vacuum deposition of a single atomic layer of Ag on them. The interfacial resistance was measured to be 3.9x 10-4 ohm. cm^ 2 and the optical transmission of the interface at 2500 nm is approximately 98%. We discuss the important role of electron confinement in ultrathin Ag layers as a possible contributor to the bonding energy.

  10. Self-assembly of epitaxial monolayers for vacuum wafer bonding

    NASA Astrophysics Data System (ADS)

    Altfeder, Igor; Huang, Biqin; Appelbaum, Ian; Walker, B. C.

    2006-11-01

    Self-assembled epitaxial metal monolayers can be used for heterointegration of mismatched semiconductors, leading to simultaneously low interfacial resistance and high optical transparency. Lattice-mismatched wafers of Si(100) and Si(111) were bonded at room temperature in situ after vacuum deposition of a single atomic layer of Ag. The interfacial resistance was measured to be 3.9×10-4Ωcm2 and the optical transmission of the interface at 2500nm is approximately 98%. Electron confinement in ultrathin Ag layers as a possible contributor to the bonding energy.

  11. Wafer-level assembly of carbon nanotube networks using dielectrophoresis

    NASA Astrophysics Data System (ADS)

    Monica, A. H.; Papadakis, S. J.; Osiander, R.; Paranjape, M.

    2008-02-01

    We use dielectrophoresis (DEP) to controllably and simultaneously assemble multiple carbon nanotube (CNT) networks at the wafer level. By an appropriate choice of electrode dimensions and geometry, an electric field is generated that captures CNTs from a sizable volume of suspension, resulting in good CNT network uniformity and alignment. During the DEP process, the electrical characteristics of the CNT network are measured and correlated with the network morphology. These experiments give novel insight into the physics of DEP assembly of CNT networks, and demonstrate the scalability of DEP for future device applications.

  12. A sliding wafer-OMVPE scheme for fabricating subnanometer superlattices

    NASA Astrophysics Data System (ADS)

    Minagawa, S.; Satoh, S.; Nakatsuka, S.; Kakibayashi, H.

    1988-03-01

    A sliding wafer-OMVPE (Organometallic Vapor Phase Epitaxy) reactor suitable for growing superlattices is developed. The reactor is a two-channel horizontal reactor with a susceptor placed across the two channels. A slider is used to transport the substrate by sliding it along the susceptor surface from one channel to the other. This scheme makes it possible to set the temperature of the susceptor in each channel independently by utilizing the skin effect of radio wave in graphite. The performance of this scheme is demonstrated by growing a superlattice of ten periods of GaAs(3.5 Å)/AlAs(7 Å).

  13. Network analyzer calibration for cryogenic on-wafer measurements

    SciTech Connect

    Hietala, V.M.; Housel, M.S.; Caldwell, R.B.

    1994-04-01

    A cryogenic probe station for on-wafer microwave measurements has been developed at Sandia National Laboratories to explore the basic device physics and characterize advanced components for low-temperature applications. The station was designed to operate over a temperature range of 20 to 300 K with a frequency range of DC to 50 GHz. Due to the vacuum and the low temperature environment, the use of microwave probes and the calibration of network analyzer measurements are somewhat elaborate. This paper presents guidelines for probe use and calibration in this environment.

  14. Sub-micron texturing of silicon wafer with fiber laser

    NASA Astrophysics Data System (ADS)

    Farrokhi, Hamid; Zhou, Wei; Zheng, Hong Yu; Li, Zhongli

    2011-03-01

    Laser texturing is extensively investigated for modifying surface properties. A continuous wave (CW) fiber laser (λ= 1090nm) was used to pattern a silicon wafer surface in ambient and O2 atmosphere respectively. The O2 gas stream was delivered through a coaxial nozzle to the laser spot. Characterization of the patterned features was carried out by surface profiling, scanning electron microscope (SEM), energy dispersive X-ray spectroscopy (EDS or EDX), Raman spectroscopy, and X-ray photoelectron spectroscopy (XPS). Formation of laser-induced silicon oxide sub-micron bumps was observed, which were analyzed and shown to cause changes in surface wetability and reflectivity.

  15. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  16. The terminal portion of leptospiral immunoglobulin-like protein LigA confers protective immunity against lethal infection in the hamster model of leptospirosis.

    PubMed

    Silva, Everton F; Medeiros, Marco A; McBride, Alan J A; Matsunaga, Jim; Esteves, Gabriela S; Ramos, João G R; Santos, Cleiton S; Croda, Júlio; Homma, Akira; Dellagostin, Odir A; Haake, David A; Reis, Mitermayer G; Ko, Albert I

    2007-08-14

    Subunit vaccines are a potential intervention strategy against leptospirosis, which is a major public health problem in developing countries and a veterinary disease in livestock and companion animals worldwide. Leptospiral immunoglobulin-like (Lig) proteins are a family of surface-exposed determinants that have Ig-like repeat domains found in virulence factors such as intimin and invasin. We expressed fragments of the repeat domain regions of LigA and LigB from Leptospira interrogans serovar Copenhageni. Immunization of Golden Syrian hamsters with Lig fragments in Freund's adjuvant induced robust antibody responses against recombinant protein and native protein, as detected by ELISA and immunoblot, respectively. A single fragment, LigANI, which corresponds to the six carboxy-terminal Ig-like repeat domains of the LigA molecule, conferred immunoprotection against mortality (67-100%, P<0.05) in hamsters which received a lethal inoculum of L. interrogans serovar Copenhageni. However, immunization with this fragment did not confer sterilizing immunity. These findings indicate that the carboxy-terminal portion of LigA is an immunoprotective domain and may serve as a vaccine candidate for human and veterinary leptospirosis. PMID:17629368

  17. Photostimulated near-infrared persistent luminescence as a new optical read-out from Cr3+-doped LiGa5O8

    PubMed Central

    Liu, Feng; Yan, Wuzhao; Chuang, Yen-Jun; Zhen, Zipeng; Xie, Jin; Pan, Zhengwei

    2013-01-01

    In conventional photostimulable storage phosphors, the optical information written by x-ray or ultraviolet irradiation is usually read out as a visible photostimulated luminescence (PSL) signal under the stimulation of a low-energy light with appropriate wavelength. Unlike the transient PSL, here we report a new optical read-out form, photostimulated persistent luminescence (PSPL) in the near-infrared (NIR), from a Cr3+-doped LiGa5O8 NIR persistent phosphor exhibiting a super-long NIR persistent luminescence of more than 1,000 h. An intense PSPL signal peaking at 716 nm can be repeatedly obtained in a period of more than 1,000 h when an ultraviolet-light (250–360 nm) pre-irradiated LiGa5O8:Cr3+ phosphor is repeatedly stimulated with a visible light or a NIR light. The LiGa5O8:Cr3+ phosphor has promising applications in optical information storage, night-vision surveillance, and in vivo bio-imaging. PMID:23532003

  18. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

    1979-01-01

    A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

  19. Effect of internal stresses on the mechanical parameters of silicon wafers

    SciTech Connect

    Oksanich, A.P.; Cherner, V.M.; Tuzovskii, K.A.

    1988-12-01

    The authors examined how the mechanical parameters of silicon wafers vary with the stress area. The polished (100) wafers were cut from a billet grown by Czochralski's method. The internal stresses were produced by moving the wafers in and out of an oven having a working zone at 1420 K. Then the oxide film was removed. The area of the stressed parts was determined by photoelasticity. The mechanical parameters were measured with contactless pneumatic loading and continuous central deflection measurement. The internal stresses affect the properties; at a given load the central deflection in an unstressed wafer is larger than in a stressed one.

  20. Determination of wafer center position during the transfer process by using the beam-breaking method

    NASA Astrophysics Data System (ADS)

    Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

    2014-09-01

    A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human-machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions.

  1. A practical approach to LWIR wafer-level optics for thermal imaging systems

    NASA Astrophysics Data System (ADS)

    Symmons, Alan; Pini, Ray

    2013-06-01

    The development and implementation of wafer level packaging for commercial microbolometers has opened the pathway towards full wafer-based thermal imaging systems. The next challenge in development is moving from discrete element LWIR imaging systems to a wafer based optical system, similar to lens assemblies found in cell phone cameras. This paper will compare a typical high volume thermal imaging design manufactured from discrete lens elements to a similar design optimized for manufacture through a wafer based approach. We will explore both performance and cost tradeoffs as well as review the manufacturability of all designs.

  2. Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

    NASA Astrophysics Data System (ADS)

    Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

    2015-07-01

    Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

  3. Growth of Catalyst-Free Epitaxial InAs Nanowires on Si Wafers Using Metallic Masks.

    PubMed

    Soo, M Teng; Zheng, Kun; Gao, Qiang; Tan, H Hoe; Jagadish, Chennupati; Zou, Jin

    2016-07-13

    Development of heteroepitaxy growth of catalyst-free vertical III-V nanowires on Si wafers is highly desirable for future nanoscale Si-based electronic and optoelectronic devices. In this study, a proof-of-concept approach is developed for catalyst-free heteroepitaxy growth of InAs nanowires on Si wafers. Before the growth of InAs nanowires, a Si-compatible metallic film with a thickness of several tens of nanometers was predeposited on a Si wafer and then annealed to form nanosize openings so as to obtain a metallic mask. These nano-openings exposed the surface of the Si wafer, which allowed subsequent nucleation and growth of epitaxial InAs nanowires directly on the surface of the Si wafer. The small size of the nano-openings limits the lateral growth of the nanostructures but promotes their axial growth. Through this approach, catalyst-free InAs nanowires were grown on both Si (111) and (001) wafers successfully at different growth temperatures. In particular, ultralong defect-free InAs nanowires with the wurtzite structure were grown the Si (111) wafers at 550 °C using the Ni mask. This study offers a simple, cost-effective, and scalable method to grow catalyst-free III-V nanowires on Si wafers. The simplicity of the approach opens a new avenue for the growth and integration of catalyst-free high-quality heteroepitaxial III-V nanowires on Si wafers. PMID:27248817

  4. The optimization of CD uniformity and measurement on mask and wafer

    NASA Astrophysics Data System (ADS)

    Choi, Yongkyoo; Kim, Munsik; Han, Oscar

    2007-05-01

    As pattern size is shrinking, required mask CD specification is tighter and its effect on wafer patterning is more severe. To enhance the device performance, wafer CD uniformity should be enhanced and controlled by mask global CD uniformity. Mask global CD uniformity usually can be enhanced by mask process and optimal fogging effect correction. To enhance the mask global CD uniformity on mask, resist process and FEC (Fogging Effect Correction), reliable CD measurement tool and methods are necessary. Recently, group CD using OCD(Spectroscopic Ellipsometer) or AIMS(Aerial Image Measurement and Simulation) is used to represent global CD variation on mask. These methods are removing local CD variation on mask. Because local CD variation on wafer is large compared with the effect of local CD variation of mask, global CD uniformity can be measured with suppressed local CD variation [1]. In this paper, local CD variation of mask and wafer is evaluated, and area CD and smoothing methods are used to measure CD on mask and wafer, and the correlation of global CD of mask and field CD of wafer are evaluated. By these methods, CD measurement repeatability can be enhanced to get closer correlation of mask and wafer. Close correlation makes fine CD correction on mask to get better field CD uniformity on wafer. And the repeatability of field to field CD uniformity of wafer is evaluated according to measurement tool of CD-SEM and scatterometry.

  5. UV/Ozone Cleaning For Organics Removal On Silicon Wafers

    NASA Astrophysics Data System (ADS)

    Zafonte, Leo; Chiu, Rafael

    1984-06-01

    The feasibility for using a combination of ultraviolet light and ozone - UV/Ozone Cleaning - for organics removal and photoresist residue cleaning from silicon semiconductor wafers was investigated. The process generates a highly oxidative atmosphere that is specific for removing trace organic residues. Product of the reactions are carbon dioxide and water. In most cases, stable inorganic materials such as oxide coatings remain unaffected. UV/Ozone exposure of silicon causes formation of a thin layer of silicon oxide that tends to retard further oxidation of the silicon. Based on the expected photochemistry o," this process, specific enhancements to accelerate the cleaning rates were tested. The enhancements involved the use of both gas phase and liquio phase additives, and comparative rates of removal were determined. The technique was tested on several photoresists, potential organic residues, and common solvent systems. The photoresists studies were primarily positive resists and were tested at several levels of ion implantation. The results of the testing suggests that the highest potential applications of UV/Ozone Cleaning in the processing of semiconductor wafers include: a) Removal of solvent residues and process contaminants. b) A pre-process step to insure cleanliness by removal of residual organic or airborne organic contaminants. c) As a post-process step to insure cleanliness or to remove trace organics.

  6. Cryogenic wafer-level MWIR camera: laboratory demonstration

    NASA Astrophysics Data System (ADS)

    Druart, G.; De La Barrière, F.; Chambon, M.; Guérineau, N.; Lasfargues, G.; Fendler, M.

    2013-06-01

    We present a compact infrared cryogenic multichannel camera with a wide field of view equal to 120°. By merging the optics with the detector, the concept has to be compatible with both cryogenic constraints and wafer-level fabrication. For this, we take advantage of the progress in micro-optics to design a multichannel optical architecture directly integrated on the detector. This wafer-level camera uses state of art microlenses with a high sag height. The additional mass of the optics is sufficiently small to be compatible with the cryogenic environment of the Dewar. The performance of this camera will be discussed. Its characterization has been carried out in terms of modulation transfer function and noise equivalent temperature difference (NETD). The optical system is limited by the diffraction. By cooling the optics, we achieve a very low NETD equal to 15 mK compared with traditional infrared cameras. A postprocessing algorithm that aims at reconstructing a well-sampled image from the set of undersampled raw subimages produced by the camera is proposed and validated on experimental images.

  7. Micropeak array in the scribe line on a wafer

    NASA Astrophysics Data System (ADS)

    Chiba, Teiichirou; Komura, Ryuusuke; Mori, Akira

    2000-11-01

    Small dot matrix marking on a silicon wafer has been performed using an second-harmonic generation (SHG) laser of yttrium aluminum garnet (YAG), liquid-crystal-display (LCD) mask, and projection optics. A marked image was obtained after laser irradiation through the pattern on the LCD mask. The each dot is a square with sides of 3.6micrometers , the pitch of each dot is 4.5micrometers and the height (not the depth) of each dot is approximately 0.5micrometers . The topography of each dot is unique, and features a central peak and peripheral depression. We have named this topography micropeak and have proposed a hypothesis for the micropeak formation mechanism, based on the density of liquid silicon and the congelation of molten silicon. In this report, micropeaks were formed in the scribe line on a wafer covered with oxide layers. Without being torn, these oxide layers were pushed up by micropeak generation and rose. Silicon particle scattering around the laser irradiation area was prevented completely. Clear dot images were observed through the transparent oxide layers. The conditions forc lean marking by laser irradiation greatly depend on the thickness of the oxide layers.

  8. Deposition and removal of sodium contamination on silicon wafers

    NASA Astrophysics Data System (ADS)

    Constant, I.; Tardif, F.; Derrien, J.

    2000-01-01

    In this paper investigations are performed in order to understand the source of sodium contamination in clean-room environments and to find different cleaning processes able to limit or suppress sodium deposition. In a clean-room environment, the human being has been identified as one of the major sources of sodium. The airborne sodium contamination is essentially transmitted in particle form. In order to limit sodium deposition from the air, the wafers awaiting subsequent processing need to be stored in a protective box or placed far from the human environment and should not be left for much more than 1 week in a class 1 clean room. Also, wet chemistries could cause sodium contamination on wafers particularly during the deionized water rinse. In order to limit the possible contamination, the sodium deposition mechanisms have been studied: they show the typical characteristics of Langmuir adsorption. Temperature and ionic concentration are both parameters which influence the deposition. In water, sodium deposition can be avoided by introducing acid or alkaline solutions or increasing the temperature: it can be drastically reduced by adding traces of HCl (0.01%). Finally, other cleaning chemistries such as SC1 (NH4 OH-H2 O2 -H2 O) in 0.25:1:5 proportion, SC2 (HCl-H2 O2 -H2 O) in 1:1:5 proportion, 0.1% HF and SPM (H2 SO4 -H2 O2 ) in 3:1 proportion reduce the contamination as well.

  9. Wafer-fused orientation-patterned GaAs

    NASA Astrophysics Data System (ADS)

    Li, Jin; Fenner, David B.; Termkoa, Krongtip; Allen, Mark G.; Moulton, Peter F.; Lynch, Candace; Bliss, David F.; Goodhue, William D.

    2008-02-01

    The fabrication of thick orientation-patterned GaAs (OP-GaAs) films is reported using a two-step process where an OP-GaAs template with the desired crystal domain pattern was prepared by wafer fusion bonding and then a thick film was grown over the template by low pressure hydride vapor phase epitaxy (HVPE). The OP template was fabricated using molecular beam epitaxy (MBE) followed by thermocompression wafer fusion, substrate removal, and lithographic patterning. On-axis (100) GaAs substrates were utilized for fabricating the template. An approximately 350 μm thick OP-GaAs film was grown on the template at an average rate of ~70 μm/hr by HVPE. The antiphase domain boundaries were observed to propagate vertically and with no defects visible by Nomarski microscopy in stain-etched cross sections. The optical loss at ~2 μm wavelength over an 8 mm long OP-GaAs grating was measured to be no more than that of the semi-insulating GaAs substrate. This template fabrication process can provide more flexibility in arranging the orientation of the crystal domains compared to the Ge growth process and is scalable to quasi-phase-matching (QPM) devices operating from the IR to terahertz frequencies utilizing existing industrial foundries.

  10. Equipment and wafer modeling of batch furnaces by neural networks

    NASA Astrophysics Data System (ADS)

    Benesch, N.; Schneider, Claus; Lehnert, Wolfgang; Pfitzner, Lothar; Ryssel, Heiner

    1999-04-01

    In semiconductor manufacturing there is a great demand for innovations towards higher cost-effectiveness. The increasing employment of advanced control systems for process and equipment control is one means to improve manufacturing processes effectively and, hence, to lower costs. A precondition for an accurate and fast control is the availability of process models. In this paper neural networks are applied to non-linear system identification as an alternative or addition to physical models. Neural empirical models are developed with the help of measured input and output data of a system or process. After a brief summary of the theory of neural networks their application to system identification is described in detail. The capabilities of the neural network models are demonstrated by several examples. The temperature dynamics of a vertical furnace for the oxidation of 300 mm wafers as well as the zone temperatures of a 150 mm LPCVD furnace are simulated and the results are verified by measurements. Moreover, in order to control wafer temperatures in batch furnaces, an appropriate model was developed and implemented in a model- based controller.

  11. Dual-Side Wafer Processing and Resonant Tunneling Transistor Applications

    SciTech Connect

    Moon, J.S.; Simmons, J.A.; Wendt, J.R.; Hietala, V.M.; Reno, J.L.; Baca, W.E.; Blount, M.A.

    1999-07-20

    We describe dual-side wafer processing and its application to resonant tunneling transistors in a planar configuration. The fabrication technique utilizes a novel flip-chip, wafer thinning process called epoxy-bond and stop-etch (EBASE) process, where the substrate material is removed by selective wet etching and stopped at an etch-stop layer. This EBASE method results in a semiconductor epitaxial layer that is typically less than a micron thick and has a mirror-finish, allowing backside gates to be placed in close proximity to frontside gates. Utilizing this technique, a resonant tunneling transistor--the double electron layer tunneling transistor (DELTT)--can be fabricated in a fully planar configuration, where the tunneling between two selectively-contacted 2DEGs in GaAs or InGaAs quantum wells is modulated by surface Schottky gate. Low temperature electrical characterization yields source-drain I-V curves with a gate-tunable negative differential resistance.

  12. Molded, wafer level optics for long wave infra-red applications

    NASA Astrophysics Data System (ADS)

    Franks, John

    2016-05-01

    For many years, the Thermal Imaging market has been driven by the high volume consumer market. The first signs of this came with the launch of night vision systems for cars, first by Cadillac and Honda and then, more successfully by BMW, Daimler and Audi. For the first time, simple thermal imaging systems were being manufactured at the rate of more than 10,000 units a year. This step change in volumes enabled a step change in system costs, with thermal imaging moving into the consumer's price range. Today we see that the consumer awareness and the consumer market continues to increase with the launch of a number of consumer focused smart phone add-ons. This has brought a further step change in system costs, with the possibility to turn your mobile phone into a thermal imager for under $250. As the detector technology has matured, the pixel pitches have dropped from 50μm in 2002 to 12 μm or even 10μm in today's detectors. This dramatic shrinkage in size has had an equally dramatic effect on the optics required to produce the image on the detector. A moderate field of view that would have required a focal length of 40mm in 2002 now requires a focal length of 8mm. For wide field of view applications and small detector formats, focal lengths in the range 1mm to 5mm are becoming common. For lenses, the quantity manufactured, quality and costs will require a new approach to high volume Infra-Red (IR) manufacturing to meet customer expectations. This, taken with the SwaP-C requirements and the emerging requirement for very small lenses driven by the new detectors, suggests that wafer scale optics are part of the solution. Umicore can now present initial results from an intensive research and development program to mold and coat wafer level optics, using its chalcogenide glass, GASIR®.

  13. Fabrication of micro nickel/diamond abrasive pellet array lapping tools using a LIGA-like technology

    NASA Astrophysics Data System (ADS)

    Luo, Sheng-Yih; Yu, Tsung-Han; Hu, Yuh-Chung

    2007-06-01

    A manufacturing process of micro nickel/diamond abrasive pellet array lapping tools using a LIGA-like technology is reported here. The thickness of JSR THB-151N resist coated on an aluminum alloy substrate for micro lithography can reach up to 110 µm. During the lithography, different geometrical photomasks were used to create specific design patterns of the resist mold on the substrate. Micro roots, made by electrolytic machining on the substrate with guidance of the resist mold, can improve the adhesion of micro nickel abrasive pellets electroplated on the substrate. During the composite electroforming, the desired hardness of the nickel matrix inside the micro diamond abrasive pellets can be obtained by the addition of leveling and stress reducing agents. At moderate blade agitation and ultrasonic oscillation, higher concentration and more uniform dispersion of diamond powders deposited in the nickel matrix can be achieved. With these optimal experiment conditions of this fabrication process, the production of micro nickel/diamond abrasive pellet array lapping tools is demonstrated.

  14. New fabrication method of glass packages with inclined optical windows for micromirrors on wafer level

    NASA Astrophysics Data System (ADS)

    Stenchly, Vanessa; Quenzer, Hans-Joachim; Hofmann, Ulrich; Janes, Joachim; Jensen, Björn; Benecke, Wolfgang

    2013-03-01

    For many applications it is inevitable to protect MEMS devices against environmental impacts like humidity which can affect their performance. Moreover recent publications demonstrates that micro mirrors can achieve very large optical scan angles at moderate driving voltages even exceeding 100 degrees when hermetically sealed under vacuum. While discrete chips may be evacuated and sealed on single die level using small can packages like TO housings, it is obvious that for high volume production a much more economical solution for the realisation of transparent optical packages already on wafer level must be developed. However, since any laser beam crossing a transparent glass surface is partly reflected even when anti-reflective coatings are applied, the construction of a wafer level optical housing suitable for laser projection purpose requires more than the integration of simple plane glass cap. The use of inclined optical windows avoids the occurrence of intense reflections of the incident laser beam in the projected images. This paper describes a unique technology to fabricate glass packages with inclined optical windows for micro mirrors on 8 inch wafers. The new process uses a high temperature glass forming process based on subsequent wafer bonding. A borosilicate glass wafer is bonded together with two structured silicon wafers. By grinding both sides of the wafer stack, a pattern of isolated silicon structures is defined. This preprocessed glass wafer is bonded thereon on a third structured silicon wafer, wherein the silicon islands are inserted into the cavities. By setting a defined pressure level inside the cavities during the final wafer bonding, the silicon glass stack extruded and it is out of plane during a subsequent annealing process at temperatures above the softening point of the glass. Finally the silicon is selectively removed in a wet etching process. This technique allows the fabrication of 8 inch glass wafers with oblique optical surfaces

  15. Alternative fabrication process for edgeless detectors on 6 in. wafers

    NASA Astrophysics Data System (ADS)

    Kalliopuska, Juha; Eränen, Simo; Virolainen, Tuula

    2011-05-01

    VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150 μm thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 5×5 and 1×1 cm2 edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.4×1.4 cm2 Medipix2 edgeless pixel detectors were also fabricated.This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100 μm from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50-70 nA/cm2 and 580-660 pF/cm2 at, respectively, 40 V reverse bias for the p-on-n. For the n-on-n design these parameters were 116-118 nA/cm2 and 930-960 pF/cm2. The breakdown voltages were above 150 V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13-28 V.

  16. Low target power wafer sputtering regime identified during magnetron tantalum barrier physical vapor deposition

    SciTech Connect

    Stout, Phillip J.; Denning, Dean J.; Michaelson, Lynne M.; Bagchi, Sandeep; Zhang Da; Ventzek, Peter L. G.

    2005-07-15

    A wafer sputtering regime has been identified during tantalum barrier deposition using a magnetron physical vapor deposition (MPVD) tool. The MPVD tools are designed to operate at high target powers (tens of kW) where the highly directed energetic metal (athermal metal) is the dominant metal species incident on the wafer. Although athermal metal gives better coverage than neutral metal (thermal) due to the narrower range of incident strike angles to the wafer, shadowing by the feature geometries is still a concern. Having available a wafer sputter regime or 'resputter' regime in a PVD tool allows for redistribution of metal from horizontal surfaces in the feature exposed to the plasma to vertical surfaces in the feature. The key in obtaining a wafer sputter regime is the operation of the plasma source in a range that the wafer bias power is effective at generating a sufficient self-bias for sputtering to occur. Discussed are modeling results which predict the wafer sputtering regime and the experimental confirmation that the low target power wafer sputter regime exists. The identified sputter regime in MPVD is such that there is a net deposition of metal at the field. Metal thickness reduction does occur at the trench and via bottoms where much of the unionized metal is being shadowed yielding a lower deposition to sputtering ratio compared to the field.

  17. The influence of carmustine wafer implantation on tumor bed cysts and peritumoral brain edema.

    PubMed

    Hasegawa, Yuzo; Iuchi, Toshihiko; Sakaida, Tsukasa; Yokoi, Sana; Kawasaki, Koichiro

    2016-09-01

    The development of perifocal edema and tumor bed cyst has been reported after implantation of biodegradable carmustine wafers for the treatment of malignant gliomas. We retrospectively evaluated these changes in a series of patients; 19 consecutive patients with malignant glioma who received carmustine wafer implantation at our hospital from January 2013 through July 2013, and 28 patients who underwent surgery prior to our institution's initiation of carmustine wafer implantation, as historical controls. The volume of the tumor bed cyst and perifocal edema was calculated on MRI acquired at four time points: ⩽72hours after surgery for baseline, and at 1-4, 5-8, and 9-12weeks after surgery. The volume of the tumor bed cyst in the wafer group increased significantly relative to the control group at all time points (p=0.04). Opening of the ventricle was inversely correlated with enlargement of the tumor bed cyst in the wafer group (p=0.04). The change in the volume of perifocal edema in the wafer group was not significantly different (p=0.48), but exhibited a considerable increase in patients with anaplastic oligodendroglioma relative to glioblastoma patients in the wafer group (p=0.01). We demonstrated significant enlargement of the tumor bed cyst volume after carmustine wafer implantation, as well as the development of marked perifocal edema in patients with anaplastic oligodendroglioma. PMID:27430412

  18. High-accuracy inspection of defects and profile of wafers by phase measuring deflectometry

    NASA Astrophysics Data System (ADS)

    Yue, Huimin; Wu, Yuxiang; Zhao, Biyu; Ou, Zhonghua; Liu, Yong

    2014-09-01

    The demands of the less-defective and high-flatness wafers are urgent in many wafer based technologies ranging from micro-electronics to the current photovoltaic industry. As the wafer becomes thinner and larger to cope with the advances in those industries, there is an increasing possibility of the emerging of crack and warp on the wafer surface. High-accuracy inspection of defects and profile are thus necessary to ensure the reliability of device. Phase measuring deflectometry(PMD) is a fast, cost-effective and high accuracy measurement technology which has been developed in recent years. As a slope measurement technology, PMD possesses a high sensitivity. Very small slope variation will lead to a large variation of the phase. PMD is very possible to have a good performance in the wafer inspection. In this paper, the requirements of the wafer inspection in the industries are discussed, and compatibility of PMD and those requirements is analyzed. In the experimental work, PMD gets the slope information of the wafer surface directly. The curvature or height information can be acquired simply by the derivation or integral of the slope. PMD is proved to make a superior result in high-precision defect detecting and shape measurement of wafer by the analysis of experiment results.

  19. The application of a crosslinked pectin-based wafer matrix for gradual buccal drug delivery.

    PubMed

    Shaikh, Rubina P; Pillay, Viness; Choonara, Yahya E; Du Toit, Lisa C; Ndesendo, Valence M K; Kumar, Pradeep; Khan, Riaz A

    2012-05-01

    The purpose of this study was to develop crosslinked wafer matrices and establish the influence of the crosslinker type and processing sequence on achieving gradual buccal drug delivery. Three sets of drug-loaded crosslinked pectin wafers were produced employing the model water-soluble antihistamine, diphenhydramine and were compared with noncrosslinked wafers. The formulations were crosslinked with CaCl(2), BaCl(2), or ZnSO(4) pre- or postlyophilization (sets 1 and 2) as well as pre- and postlyophilization (set 3), respectively. The surface morphology, porositometry, molecular vibrational transitions, textural attributes, thermal and in vitro drug release were characterized and supported by in silico molecular mechanics simulations. Results revealed that crosslinked wafers produced smaller pore sizes (107.63 Å) compared with noncrosslinked matrices (180.53 Å) due to molecular crosslinks formed between pectin chains. Drug release performance was dependent on the wafer crosslinking production sequence. Noncrosslinked wafers displayed burst-release with 82% drug released at t(30min) compared with first-order kinetic profiles obtained for prelyophilized crosslinked matrices (50% released at t(30min) followed by steady release). Wafers crosslinked postlyophilization displayed superior control of drug release (40% at t(30min)). Molecular mechanics simulations corroborated with the experimental data and established that Ba(++), having the largest atomic radii (1.35 Å) formed a number of ionic bridges producing wafers of higher porosity (0.048 cm(2)/g) and had more influence on drug release. PMID:22323418

  20. Nanotribology of nanooxide materials in ionic liquids on silicon wafers

    NASA Astrophysics Data System (ADS)

    Hamidunsani, Ahmad Termizi; Radiman, Shahidan; Hassan, Masjuki Haji; Rahman, Irman Abdul

    2015-09-01

    Nanotribological properties have a significant impact on daily life. Ionic liquids (ILs) are becoming new favourable lubricants currently in researches. Addition of nanooxide materials in lubricants provide improvements to new technology. In this study, we determine nanotribological properties of BMIM+BF4- IL addition of different amount of ZnO nanomaterial on single crystals silicon wafer (Si110). The viscosity changes of IL samples against temperature increase were determined by rheological method. Nanotribological properties were determined by changes in friction coefficient and wear rate on silicon substrate surfaces using a reciprocating friction and wear monitor in 1 hour duration time. Aluminium cylinders acted as pins used to rub Si (110) substrate sample surfaces. Thus, on range between 0 mg to 3.5 mg of ZnO nanooxide material dispersed in 10ml BMIM+BF4- showed a good friction coefficient, wear and surface roughness reduction.

  1. Chemical strategies for die/wafer submicron alignment and bonding.

    SciTech Connect

    Martin, James Ellis; Baca, Alicia I.; Chu, Dahwey; Rohwer, Lauren Elizabeth Shea

    2010-09-01

    This late-start LDRD explores chemical strategies that will enable sub-micron alignment accuracy of dies and wafers by exploiting the interfacial energies of chemical ligands. We have micropatterned commensurate features, such as 2-d arrays of micron-sized gold lines on the die to be bonded. Each gold line is functionalized with alkanethiol ligands before the die are brought into contact. The ligand interfacial energy is minimized when the lines on the die are brought into registration, due to favorable interactions between the complementary ligand tails. After registration is achieved, standard bonding techniques are used to create precision permanent bonds. We have computed the alignment forces and torque between two surfaces patterned with arrays of lines or square pads to illustrate how best to maximize the tendency to align. We also discuss complex, aperiodic patterns such as rectilinear pad assemblies, concentric circles, and spirals that point the way towards extremely precise alignment.

  2. Coherent Spin Transport through a 350Micron Thick Silicon Wafer

    NASA Astrophysics Data System (ADS)

    Huang, Biqin; Monsma, Douwe J.; Appelbaum, Ian

    2007-10-01

    We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13π precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

  3. Visible luminescence from silicon wafers subjected to stain etches

    NASA Technical Reports Server (NTRS)

    Fathauer, R. W.; George, T.; Ksendzov, A.; Vasquez, R. P.

    1992-01-01

    Etching of Si in a variety of solutions is known to cause staining. These stain layers consist of porous material similar to that produced by anodic etching of Si in HF solutions. In this work, photoluminescence peaked in the red from stain-etched Si wafers of different dopant types, concentrations, and orientations produced in solutions of HF:HNO3:H2O was observed. Luminescence is also observed in stain films produced in solutions of NaNO2 in HF, but not in stain films produced in solutions of CrO3 in HF. The luminescence spectra are similar to those reported recently for porous Si films produced by anodic etching in HF solutions. However, stain films are much easier to produce, requiring no special equipment.

  4. Effect of lubricant environment on saw damage in silicon wafers

    NASA Technical Reports Server (NTRS)

    Kuan, T. S.; Shih, K. K.; Vanvechten, J. A.; Westdorp, W. A.

    1982-01-01

    The chemomechanical effect of lubricant environments on the inner diameter (ID) sawing induced surface damage in Si wafers was tested for four different lubricants: water, dielectric oil, and two commercial cutting solutions. The effects of applying different potential on Si crystals during the sawing were also tested. It is indicated that the number and depth of surface damage are sensitive to the chemical nature of the saw lubricant. It is determined that the lubricants that are good catalysts for breaking Si bonds can dampen the out of plane blade vibration more effectively and produce less surface damage. Correlations between the applied potential and the depth of damage in the dielectric oil and one of the commercial cutting solutions and possible mechanisms involved are discussed.

  5. Wafer-level hysteresis-free resonant carbon nanotube transistors.

    PubMed

    Cao, Ji; Bartsch, Sebastian T; Ionescu, Adrian M

    2015-03-24

    We report wafer-level fabrication of resonant-body carbon nanotube (CNT) field-effect transistors (FETs) in a dual-gate configuration. An integration density of >10(6) CNTFETs/cm(2), an assembly yield of >80%, and nanoprecision have been simultaneously obtained. Through combined chemical and thermal treatments, hysteresis-free (in vacuum) suspended-body CNTFETs have been demonstrated. Electrostatic actuation by lateral gate and FET-based readout of mechanical resonance have been achieved at room temperature. Both upward and downward in situ frequency tuning has been experimentally demonstrated in the dual-gate architecture. The minuscule mass, high resonance frequency, and in situ tunability of the resonant CNTFETs offer promising features for applications in radio frequency signal processing and ultrasensitive sensing. PMID:25752991

  6. Patterned wafer inspection using spatial filtering for the cluster environment.

    PubMed

    Taubenblatt, M A; Batchelder, J S

    1992-06-10

    Automated-process tool clusters are becoming increasingly prevalent in advanced semiconductor manufacturing plants, necessitating integrated inspection of patterned semiconductor wafers for defects and particulates. Integrated inspection tools must be small, sensitive, inexpensive, and fast in order to be compatible with the cluster environment. We show that intensity spatial filtering, with some refinements, can provide the required sensitivity and speed in a small, inexpensive package. By using dark-field illumination and a nonrectangular azimuthal orientation (e.g., 45 degrees ) to the primarily rectangular pattern, we show that the strongest diffraction from the pattern can be made to bypass the optical system entirely. This technique alleviates stringent scatter and antireflection requirements on the optics, and it permits the use of off-the-shelf components. PMID:20725290

  7. Arthroscopic wafer resection for ulnar impaction syndrome: prediction of outcomes.

    PubMed

    Meftah, Morteza; Keefer, Eric P; Panagopoulos, Georgia; Yang, S Steven

    2010-01-01

    Twenty-six patients with mean age of 38.5 (range 18-59), from 1998 to 2005, with ulnar impaction syndrome who failed nonoperative treatments were included in our study. Patients' age, history of previous wrist fracture, presence of MRI signs and ulnar variance were recorded as variables. Also, patients' postoperative strength (compared to the contralateral wrist) and pain relief were collected as outcome measurements. Twenty-two patients (84.6%) had either good or excellent pain relief (median 4, range 1-4). Significant correlation was found between MRI findings and postop pain relief (r = 0.53, p < or = 0.01). History of previous distal radius fractures was negatively correlated with pain relief (r = -0.50, p < or = 0.01). No correlation was found between postop strength and any of the variables. Presence of MRI signs of UIS is a predictor of good outcome in arthroscopic wafer resection. PMID:20672395

  8. A Wafer Transfer Technology for MEMS Adaptive Optics

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean V.

    2001-01-01

    Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

  9. Characterization of semiconductor surface-emitting laser wafers

    SciTech Connect

    Gourley, P.L.; Vawter, G.A.; Brennan, T.M.; Hammons, B.E.

    1990-01-01

    The development of epitaxial semiconductor surface-emitting lasers has begun in recent years. These lasers are ultra-short (few {mu}m) Fabry-Perot resonators comprising epitaxial multilayer semiconductor mirrors and quantum well active regions. The resonators are single crystals grown along the lasing axis by molecular beam epitaxy (MBE) or chemical vapor deposition (CVD). They offer significant advances over conventional cleaved, edge-emitting lasers for creating lasers with single elements of 2 dimensional arrays, low beam divergence, engineered active regions, single longitudinal modes, and improved temperature characteristics. To realize the high potential of these new laser structures, techniques for characterizing the laser wafer after growth and between fabrication steps must be developed. In this paper we discuss several optical techniques that we have developed for this emerging surface-emitting laser technology.

  10. Magnetometory of AlGaN/GaN heterostructure wafers

    NASA Astrophysics Data System (ADS)

    Tsubaki, K.; Maeda, N.; Saitoh, T.; Kobayashi, N.

    2005-06-01

    AlGaN/GaN heterostructure wafers are becoming a key technology for next generation cellar-phone telecommunication system because of their potential for high-performance microwave applications. Therefore, the electronic properties of a 2DEG in AlGaN/GaN heterostructures have recently been discussed. In this paper, we performed the extraordinary Hall effect measurement and the SQUID magnetometory of AlGaN/GaN heterostructure wafer at low temperature. The AlGaN/GaN heterostructures were grown by low-pressure metal-organic chemical vapour phase epitaxy on (0001) SiC substrate using AlN buffers. The electron mobility and electron concentration at 4.2 K are 9,540cm2/V s and 6.6 × 1012cm-2, respectively. In the extraordinary Hall effect measurement of AlGaN/GaN heterostructures, the hysteresis of Hall resistance appeared below 4.5 K and disappeared above 4.5 K. On the other hand, the hysteresis of magnetometric data obtained by SQUID magnetometory appears near zero magnetic field when the temperature is lower than 4.5 K. At the temperature larger than 4.5 K, the hysteresis of magnetometric data disappears. And the slopes of magnetometric data with respect to magnetic field become lower as obeying Currie-Weiss law and the Curie temperature TC is 4.5 K. Agreement of TC measured by the extraordinary Hall effect and the SQUID magnetometory implies the ferromagnetism at the AlGaN/GaN heterojunction. However, the conformation of the ferromagnetism of AlGaN/GaN heterostructure is still difficult and the detailed physical mechanism is still unclear.

  11. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbracher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-07-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  12. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbrecher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-01-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  13. High performance LWIR microbolometer with Si/SiGe quantum well thermistor and wafer level packaging

    NASA Astrophysics Data System (ADS)

    Roer, Audun; Lapadatu, Adriana; Bring, Martin; Wolla, Erik; Hohler, Erling; Kittilsland, Gjermund

    2011-11-01

    An uncooled microbolometer with peak responsivity in the long wave infrared region of the electromagnetic radiation is developed at Sensonor Technologies. It is a 384 x 288 focal plane array with a pixel pitch of 25μm, based on monocrystalline Si/SiGe quantum wells as IR sensitive material. The high sensitivity (TCR) and low 1/f noise are the main performance characteristics of the product. The frame rate is maximum 60Hz and the output interface is digital (LVDS). The quantum well thermistor material is transferred to the read-out integrated circuit (ROIC) by direct wafer bonding. The ROIC wafer containing the released pixels is bonded in vacuum with a silicon cap wafer, providing hermetic encapsulation at low cost. The resulting wafer stack is mounted in a standard ceramic package. In this paper the architecture of the pixels and the ROIC, the wafer packaging and the electro-optical measurement results are presented.

  14. A universal process development methodology for complete removal of residues from 300mm wafer edge bevel

    NASA Astrophysics Data System (ADS)

    Randall, Mai; Linnane, Michael; Longstaff, Chris; Ueda, Kenichi; Winter, Tom

    2006-03-01

    Many yield limiting, etch blocking defects are attributed to "flake" type contamination from the lithography process. The wafer edge bevel is a prime location for generation of this type of defect. Wafer bevel quality is not readily observed with top down or even most off axis inspection equipment. Not all chemistries are removed with one "universal" cleaning process. IC manufacturers must maximize usable silicon area as well. These requirements have made traditional chemical treatments to clean the wafer edge inadequate for many chemistry types used in 193nm processing. IBM has evaluated a method to create a robust wafer bevel and backside cleaning process. An August Technology AXi TM Series advanced macro inspection tool with E20 TM edge inspection module has been used to check wafer bevel cleanliness. Process impact on the removal of post apply residues has been investigated. The new process used backside solvent rinse nozzles only and cleaned the wafer bevel completely. The use of the topside edge solvent clean nozzles was eliminated. Thickness, wet film defect measurements (wet FM), and pattern wafer defect monitors showed no difference between the new backside rinse edge bead removal process and the process of record. Solvent topside edge bead removal of both bottom anti-reflective coatings and resist materials showed better cut width control and uniformity. We conclude that the topside solvent edge bead removal nozzle can be removed from the process. Backside solvent rinse nozzles can clean the backside of the wafer, the wafer bevel, and can wrap to the front edge of the wafer to provide a uniform edge bead removal cut width that is not sensitive to coater module tolerances. Recommendations are made for changes to the typical preventive maintenance procedures.

  15. Creating a single twin boundary between two CdTe (111) wafers with controlled rotation angle by wafer bonding

    SciTech Connect

    Sun, Ce; Lu, Ning; Wang, Jinguo; Lee, Jihyung; Peng, Xin; Kim, Moon J.; Klie, Robert F.

    2013-12-16

    The single twin boundary with crystallographic orientation relationship (1{sup ¯}1{sup ¯}1{sup ¯})//(111) [01{sup ¯}1]//[011{sup ¯}] was created by wafer bonding. Electron diffraction patterns and high-resolution transmission electron microscopy images demonstrated the well control of the rotation angle between the bonded pair. At the twin boundary, one unit of wurtzite structure was found between two zinc-blende matrices. High-angle annular dark-field scanning transmission electron microscopy images showed Cd- and Te-terminated for the two bonded portions, respectively. The I-V curve across the twin boundary showed increasingly nonlinear behavior, indicating a potential barrier at the bonded twin boundary.

  16. Infrared differential interference contrast microscopy for overlay metrology on 3D-interconnect bonded wafers

    NASA Astrophysics Data System (ADS)

    Ku, Yi-sha; Shyu, Deh-Ming; Lin, Yeou-Sung; Cho, Chia-Hung

    2013-04-01

    Overlay metrology for stacked layers will be playing a key role in bringing 3D IC devices into manufacturing. However, such bonded wafer pairs present a metrology challenge for optical microscopy tools by the opaque nature of silicon. Using infrared microscopy, silicon wafers become transparent to the near-infrared (NIR) wavelengths of the electromagnetic spectrum, enabling metrology at the interface of bonded wafer pairs. Wafers can be bonded face to face (F2F) or face to back (F2B) which the stacking direction is dictated by how the stacks are carried in the process and functionality required. For example, Memory stacks tend to use F2B stacking enables a better managed design. Current commercial tools use single image technique for F2F bonding overlay measurement because depth of focus is sufficient to include both surfaces; and use multiple image techniques for F2B overlay measurement application for the depth of focus is no longer sufficient to include both stacked wafer surfaces. There is a need to specify the Z coordinate or stacking wafer number through the silicon when visiting measurement wafer sites. Two shown images are of the same (X, Y) but separate Z location acquired at focus position of each wafer surface containing overlay marks. Usually the top surface image is bright and clear; however, the bottom surface image is somewhat darker and noisier as an adhesive layer is used in between to bond the silicon wafers. Thus the top and bottom surface images are further processed to achieve similar brightness and noise level before merged for overlay measurement. This paper presents a special overlay measurement technique, using the infrared differential interference contrast (DIC) microscopy technique to measure the F2B wafer bonding overlay by a single shot image. A pair of thinned wafers at 50 and 150 μm thickness is bonded on top of a carrier wafer to evaluate the bonding overlay. It works on the principle of interferometry to gain information about the

  17. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates.

    PubMed

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-01-01

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the "melt-back" effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 μm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude. PMID:26487465

  18. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates

    PubMed Central

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-01-01

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the “melt-back” effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 μm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude. PMID:26487465

  19. Kinetic mechanism and fidelity of nick sealing by Escherichia coli NAD+-dependent DNA ligase (LigA)

    PubMed Central

    Chauleau, Mathieu; Shuman, Stewart

    2016-01-01

    Escherichia coli DNA ligase (EcoLigA) repairs 3′-OH/5′-PO4 nicks in duplex DNA via reaction of LigA with NAD+ to form a covalent LigA-(lysyl-Nζ)–AMP intermediate (step 1); transfer of AMP to the nick 5′-PO4 to form an AppDNA intermediate (step 2); and attack of the nick 3′-OH on AppDNA to form a 3′-5′ phosphodiester (step 3). A distinctive feature of EcoLigA is its stimulation by ammonium ion. Here we used rapid mix-quench methods to analyze the kinetic mechanism of single-turnover nick sealing by EcoLigA–AMP. For substrates with correctly base-paired 3′-OH/5′-PO4 nicks, kstep2 was fast (6.8–27 s−1) and similar to kstep3 (8.3–42 s−1). Absent ammonium, kstep2 and kstep3 were 48-fold and 16-fold slower, respectively. EcoLigA was exquisitely sensitive to 3′-OH base mispairs and 3′ N:abasic lesions, which elicited 1000- to >20000-fold decrements in kstep2. The exception was the non-canonical 3′ A:oxoG configuration, which EcoLigA accepted as correctly paired for rapid sealing. These results underscore: (i) how EcoLigA requires proper positioning of the nick 3′ nucleoside for catalysis of 5′ adenylylation; and (ii) EcoLigA's potential to embed mutations during the repair of oxidative damage. EcoLigA was relatively tolerant of 5′-phosphate base mispairs and 5′ N:abasic lesions. PMID:26857547

  20. Microlenticular lens replication by the combination of gas-assisted imprint technology and LIGA-like process

    NASA Astrophysics Data System (ADS)

    Yeh, Chia-Hung; Shih, Ching-Jui; Wang, Hsuan-Cheng; Chang, Fuh-Yu; Young, Hong-Tsu; Chang, Wen-Chuan

    2012-09-01

    A mold used in creating diffractive optical elements significantly affects the quality of these devices. In this study, we improved traditional microlens fabrication processes, which have shortcomings, mainly by combining gas-assisted imprint technology and the lithographie galvanoformung abformung (LIGA)-like process. This combination resulted in the production of high-quality optical components with high replication rates, high uniformity, large areas and high flexibility. Given the pixel size of the panel used, the optimal viewing distance, the film thickness and the glass thickness in the formula, we could determine the radius of curvature and the thickness of the lens. By the use of U-groove machining, precise electroforming and embossing to produce polydimethylsiloxane (PDMS) molds, lens film elements can be produced via an ultraviolet (UV)-cured molding process that converts microlenses into flexible polyethylene terephthalate films. In this study, the microlenticular lens mold is fabricated by U-groove machining, Ni electroforming and PDMS casting. Then, the PDMS mold with microlenticular lens structure is used in the gas-assisted UV imprint process and the PET film with microlenticular lens array is obtained. The lenticular lens had a radius of curvature and height of 228 and 18 µm, respectively. A 3D confocal laser microscope was used to measure the radius of curvature and the spacing of the metal molds, nickel (Ni) molds, PDMS molds and the finished thin-film products. The geometry of the final microlenticular lens was very close to the design values. All geometric errors were below 5%, the surface roughness reached the optical level (with all Ra values less than 10 nm) and the replication rate was 95%. The results demonstrate that this process can be used to fabricate gapless, lenticular-shaped, high-precision microlens arrays with a unitary curvature.

  1. Kinetic mechanism and fidelity of nick sealing by Escherichia coli NAD+-dependent DNA ligase (LigA).

    PubMed

    Chauleau, Mathieu; Shuman, Stewart

    2016-03-18

    Escherichia coli DNA ligase (EcoLigA) repairs 3'-OH/5'-PO4 nicks in duplex DNA via reaction of LigA with NAD(+) to form a covalent LigA-(lysyl-Nζ)-AMP intermediate (step 1); transfer of AMP to the nick 5'-PO4 to form an AppDNA intermediate (step 2); and attack of the nick 3'-OH on AppDNA to form a 3'-5' phosphodiester (step 3). A distinctive feature of EcoLigA is its stimulation by ammonium ion. Here we used rapid mix-quench methods to analyze the kinetic mechanism of single-turnover nick sealing by EcoLigA-AMP. For substrates with correctly base-paired 3'-OH/5'-PO4 nicks, kstep2 was fast (6.8-27 s(-1)) and similar to kstep3 (8.3-42 s(-1)). Absent ammonium, kstep2 and kstep3 were 48-fold and 16-fold slower, respectively. EcoLigA was exquisitely sensitive to 3'-OH base mispairs and 3' N:abasic lesions, which elicited 1000- to >20000-fold decrements in kstep2. The exception was the non-canonical 3' A:oxoG configuration, which EcoLigA accepted as correctly paired for rapid sealing. These results underscore: (i) how EcoLigA requires proper positioning of the nick 3' nucleoside for catalysis of 5' adenylylation; and (ii) EcoLigA's potential to embed mutations during the repair of oxidative damage. EcoLigA was relatively tolerant of 5'-phosphate base mispairs and 5' N:abasic lesions. PMID:26857547

  2. Retrospective comparison of Traditional vs. LigaSure impact dissection during pancreatoduodenectomy: how to save money by using an expensive device.

    PubMed

    Piccinni, Giuseppe; Pasculli, Alessandro; D'Ambrosio, Erasmina; Gurrado, Angela; Lissidini, Germana; Testini, Mario

    2013-09-01

    Pancreatoduodenectomy is an exceptional procedure that requires an extensive dissection of the supramesocolic region extended to the first jejunal limb. Lymphadenectomy, required for cancer, increases the dissection surface. The extensive preparation of the area is traditionally conducted with bipolar ormonopolar instruments, while clips, ligatures, and sutures are used for haemostasis. LigaSure™ vessel sealing(LSVS; Valleylab, Boulder, CO) is a technology that obtains vessel closure by using the body's own collagen and elastin to create a permanent fusion zone. This is obtained by a combination of forceps pressure and radio frequency. This effect has been improved by the introduction of the Force Triad™ (Valleylab, Boulder,CO) energy platform, controlled by TissueFect™ (Valleylab, Boulder, CO) sensing technology. With this device, the surgeon is able to fuse vessels up to 7 mm, lymphatics, tissue bundles, and pulmonary vasculature in a fast-seal cycle of almost 4 seconds. In our daily practice of open surgery we observe a rapid improvement of abdominal drainage output with a drastic reduction of protein loss. Its practical significance is, in our opinion, that we obtain a rapid recovery of normal serum protein levels with a low number of blood/plasmasac transfusions and a real improvement of anastomosis healing. Moreover, the efficacy and the speed of work of the device allow us to reduce the operating time significantly but safely. We performed a retrospective analysis of the data of 20 pancreatic resections conducted both with traditional dissection and with the Liga-Sure Impact device with Force Triad platform in order to verify whether observed data were real. Our clinical results show that the use of the LigaSure Impact device with Force Triad energy platform is really useful in open surgery to save operating time, number of postoperative days, and hemoderivate administration. PMID:24081851

  3. A new LigaSure technique for the formation of segmental plane by intravenous indocyanine green fluorescence during thoracoscopic anatomical segmentectomy

    PubMed Central

    Dejima, Hitoshi; Mizumo, Tetsuya; Sakakura, Noriaki; Sakao, Yukinori

    2016-01-01

    Background The purpose of this study was to present a new approach to the formation of a segmental plane by LigaSure (Covidien, Mansfield, MA, USA) with indocyanine green (ICG) fluorescence system during thoracoscopic segmentectomy. Methods This was a consecutive study that compared 12 patients who underwent a new LigaSure technique (LT) for segmental plane formation during thoracoscopic anatomical segmentectomy with 38 patients who underwent conventional methods using the staple technique (ST). Eleven patients were followed up more than 3 months after discharge. Results The mean age of the patients was 66 years in the LT group and 67 years in ST. The mean duration for the formation of segmental plane and the mean number of staples was 22.8 min and 1.8 per surgery, respectively, in the LT group; and 16.2 min and 3.4 per surgery, respectively, in ST. No patient had a prolonged air leak (PAL) of more than 7 days. Minor air leak was identified early in two and was delayed in one. Two-thirds of patients with early minor air leak had low index of prolonged air leak (IPAL) score. There was no air leak in the patients with high IPAL score. Eventually, we deduced that the cause of the minor air leak was a technical problem. Conclusions In the formation of segmental plane during thoracoscopic segmentectomy, a combination of ICG fluorescence and LigaSure may be beneficial for patients. As a new operative instrument, LT constitutes, in our opinion, a feasible and easy alternative to other thoracoscopic techniques. PMID:27293839

  4. Contact doping of silicon wafers and nanostructures with phosphine oxide monolayers.

    PubMed

    Hazut, Ori; Agarwala, Arunava; Amit, Iddo; Subramani, Thangavel; Zaidiner, Seva; Rosenwaks, Yossi; Yerushalmi, Roie

    2012-11-27

    Contact doping method for the controlled surface doping of silicon wafers and nanometer scale structures is presented. The method, monolayer contact doping (MLCD), utilizes the formation of a dopant-containing monolayer on a donor substrate that is brought to contact and annealed with the interface or structure intended for doping. A unique feature of the MLCD method is that the monolayer used for doping is formed on a separate substrate (termed donor substrate), which is distinct from the interface intended for doping (termed acceptor substrate). The doping process is controlled by anneal conditions, details of the interface, and molecular precursor used for the formation of the dopant-containing monolayer. The MLCD process does not involve formation and removal of SiO(2) capping layer, allowing utilization of surface chemistry details for tuning and simplifying the doping process. Surface contact doping of intrinsic Si wafers (i-Si) and intrinsic silicon nanowires (i-SiNWs) is demonstrated and characterized. Nanowire devices were formed using the i-SiNW channel and contact doped using the MLCD process, yielding highly doped SiNWs. Kelvin probe force microscopy (KPFM) was used to measure the longitudinal dopant distribution of the SiNWs and demonstrated highly uniform distribution in comparison with in situ doped wires. The MLCD process was studied for i-Si substrates with native oxide and H-terminated surface for three types of phosphorus-containing molecules. Sheet resistance measurements reveal the dependency of the doping process on the details of the surface chemistry used and relation to the different chemical environments of the P═O group. Characterization of the thermal decomposition of several monolayer types formed on SiO(2) nanoparticles (NPs) using TGA and XPS provides insight regarding the role of phosphorus surface chemistry at the SiO(2) interface in the overall MLCD process. The new MLCD process presented here for controlled surface doping

  5. Evaluation of the Technical Feasibility and Effective Cost of Various Wafer Thicknesses for the Manufacture of Solar Cells

    NASA Technical Reports Server (NTRS)

    1979-01-01

    Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.

  6. Evaluation of the technical feasibility and effective cost of various wafer thicknesses for the manufacture of solar cells

    NASA Technical Reports Server (NTRS)

    1978-01-01

    Three wafering demonstration runs were completed on the Yasunaga wire saw. Wafer thickness/taper uniformity is excellent. Many small problems were encountered with Yasunaga accessories, slowing the effort. A wafer characterization cycle was defined and will be initiated during the next period.

  7. Brush Scrub Cleaning after Spraying Ozonized Water on Si Wafer Treated by Chemical Mechanical Polishing

    NASA Astrophysics Data System (ADS)

    Kurokawa, Yoshiaki; Hayashi, Kounosuke; Nishimura, Eriko; Saito, Reiko; Maki, Kunisuke

    2008-09-01

    To clean the surface of 300-mm-diameter silicon wafers treated by chemical mechanical polishing (CMP), the following steps were performed: (1) the wafer surfaces were first terminated with hydrogen using an etching solution of hydrofluoric acid, and (2) the wafers were then spun while ozonized water was sprayed before brush scrub cleaning was performed. The number of particles more than 100 nm in diameter remaining on the wafer decreased linearly with increasing time after spraying ozonized water for approximately 5 s before brush scrub cleaning. The wafers had fewer than 10 particles after spraying ozonized water for approximately 15 s followed by brush scrub cleaning. Such a cleaning effect was not accomplished when the ozonized water was not sprayed. A model of the brush scrub cleaning process is discussed from the view point that an oxide film is first formed on the wafer surface where no particles are adhered, and then grows laterally beneath the particles. The force then applied by the brush scrubber overcomes the adhesion force between the particles and the wafer, which results in their removal when the oxide layer reaches a sufficient thickness. The growth of the oxide film was confirmed by observing the spectra obtained by attenuated total reflectance spectroscopy (ATR) using a Fourier transform infrared spectroscope (FTIR) and by X-ray photoelectron spectroscopy (XPS).

  8. Therml & Gravitational Stress in Si Wafers; Lim. on Process Htg & Cool. Rates

    Energy Science and Technology Software Center (ESTSC)

    1997-01-14

    The MacWafer code determines maximum allowable processing temperatures and maximum heating and cooling rates for thermal processing of silicon semiconductor wafers in single and multiple wafer furnaces. The program runs interactively on Macintosh, PC, and workstation computers. Execution time is typically 20 seconds on a Macintosh 68040 processor operating at 33 MHz. Gravitational stresses and displacements are first calculated based on the user''s input of a support system consisting of a ring beneath the wafermore » and/or arbitrarily placed point supports. The maximum operating temperature is then deduced by comparing the calculated gravitational stresses with the temperature-dependent wafer strength. At lower temperatures, the difference between wafer strength and gravitational stress is used to determine the allowable thermal stress, and hence the allowable radial temperature difference across the wafer. Finally, an analytical model of radial heat transfer in a batch furnace yields the maximum heating or cooling rate as a function of the allowable temperature difference based on the user''s inputs of wafer spacing and furnace power. Outputs to the screen include plots of stress components and vertical displacement, as well as tables of maximum stresses and maximum heating and cooling rates as a function of temperature. All inputs and outputs may be directed to user-named files for further processing or graphical display.« less

  9. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss

    PubMed Central

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-01-01

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping. PMID:24820403

  10. AWV: high-throughput cross-array cross-wafer variation mapping

    NASA Astrophysics Data System (ADS)

    Yeo, Jeong-Ho; Lee, Byoung-Ho; Lee, Tae-Yong; Greenberg, Gadi; Meshulach, Doron; Ravid, Erez; Levi, Shimon; Kan, Kobi; Shabtay, Saar; Cohen, Yehuda; Rotlevi, Ofer

    2008-03-01

    Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision (TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

  11. Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010

    SciTech Connect

    Lorenz, A.

    2011-06-01

    1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

  12. Improvement of surface roughness in silicon-on-insulator wafer fabrication using a neutral beam etching

    NASA Astrophysics Data System (ADS)

    Min, T. H.; Park, B. J.; Kang, S. K.; Gweon, G. H.; Kim, Y. Y.; Yeom, G. Y.

    2009-08-01

    Silicon-on-insulator (SOI) wafers were etched by an energetic chlorine neutral beam obtained by the low-angle forward reflection of an ion beam, and the surface roughness of the etched wafers was compared with that of the SOI wafers etched by an energetic chlorine ion beam. When the ion beam was used to etch the silicon layer of the SOI wafers, the surface roughness was not significantly changed even though the use of higher ion bombardment energy slightly decreased the surface roughness of the SOI wafer. However, when the chlorine neutral beam was used instead of the chlorine ion beam having a similar beam energy, the surface roughness of the SOI wafer was significantly improved compared with that etched by the chlorine ion beam. By etching about 150 nm silicon from the SOI wafer having a 300 nm-thick top silicon layer with the chlorine neutral beam at the energy of 500 eV, the rms surface roughness of 1.5 Å could be obtained with the etch rate of about 750 Å min-1.

  13. Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

    NASA Technical Reports Server (NTRS)

    Okojie, Robert S. (Inventor)

    2002-01-01

    A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

  14. Carboxymethyl cellulose wafers containing antimicrobials: a modern drug delivery system for wound infections.

    PubMed

    Ng, Shiow-Fern; Jumaat, Nafisah

    2014-01-23

    Lyophilised wafers have been shown to have potential as a modern dressing for mucosal wound healing. The wafer absorbs wound exudates and transforms into a gel, thus providing a moist environment which is essential for wound healing. The objective of this study was to develop a carboxymethyl cellulose wafer containing antimicrobials to promote wound healing and treat wound infection. The pre-formulation studies began with four polymers, sodium carboxymethyl cellulose (NaCMC), methylcellulose (MC), sodium alginate and xanthan gum, but only NaCMC and MC were chosen for further investigation. The wafers were characterised by physical assessments, solvent loss, microscopic examination, swelling and hydration properties, drug content uniformity, drug release and efficacy of antimicrobials. Three of the antimicrobials, neomycin trisulphate salt hydrate, sulphacetamide sodium and silver nitrate, were selected as model drugs. Among the formulations, NaCMC wafer containing neomycin trisulphate exhibited the most desirable wound dressing characteristics (i.e., flexibility, sponginess, uniform wafer texture, high content drug uniformity) with the highest in vitro drug release and the greatest inhibition against both Gram positive and Gram negative bacteria. In conclusion, we successfully developed a NaCMC lyophilised wafer containing antimicrobials, and this formulation has potential for use in mucosal wounds infected with bacteria. PMID:24076463

  15. A self-priming, high performance, check valve diaphragm micropump made from SOI wafers

    NASA Astrophysics Data System (ADS)

    Kang, Jianke; Mantese, Joseph V.; Auner, Gregory W.

    2008-12-01

    In this paper, we describe a self-priming high performance piezoelectrically actuated check valve diaphragm micropump. The micropump was fabricated from three wafers: two silicon-on-insulator (SOI) wafers and one silicon wafer. A process named 'SOI/SOI wafer bonding and etching back followed by a second wafer bonding' was developed in order to make the core components of this device which included an inlet check valve, an outlet check valve, a diaphragm and a chamber. The movable structures of this device, i.e. the check valves and the diaphragm, were fabricated from the device layers of the two bonded SOI wafers. Taking advantages of SOI wafer technology and etch-stop layers, the vertical parameters of the movable structures were precisely controlled in fabrication. The micropump was self-priming without any pre-filling process. The pumping rate of the micropump was linearly adjustable from 0 to 650l µm min-1 by adjusting frequency. The maximum pumping rate was 860 µl min-1 and the maximum pumping pressure was approximately 10.5 psi. The power consumption of the device was less than 1.2 mW.

  16. Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

    NASA Astrophysics Data System (ADS)

    Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

    2015-02-01

    The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

  17. Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers Used for PV Cells: Preprint

    SciTech Connect

    Guthrey, H.; Gorman, B.; Al-Jassim, M.

    2011-07-01

    As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay (uPCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

  18. Ultrasound-assisted handling force reduction during the solar silicon wafers production.

    PubMed

    Saffar, S; Abdullah, A; Gouttebroze, S; Zhang, Z L

    2014-04-01

    Surface adhesion between wet wafers poses great challenges for silicon wafer handling. It has been shown that both the shear and normal handling forces of the solar silicon wafers can be dramatically reduced by using the ultrasound energy. Approximately 20 and 5 times reduction in horizontal and vertical forces were achieved by as low power as 10W, and a good agreement was found between the measured values and the predictions of a simple model for the effect of longitudinal vibration we developed. PMID:24434116

  19. W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

    NASA Technical Reports Server (NTRS)

    Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

    1997-01-01

    Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

  20. Wafer chamber having a gas curtain for extreme-UV lithography

    DOEpatents

    Kanouff, Michael P.; Ray-Chaudhuri, Avijit K.

    2001-01-01

    An EUVL device includes a wafer chamber that is separated from the upstream optics by a barrier having an aperture that is permeable to the inert gas. Maintaining an inert gas curtain in the proximity of a wafer positioned in a chamber of an extreme ultraviolet lithography device can effectively prevent contaminants from reaching the optics in an extreme ultraviolet photolithography device even though solid window filters are not employed between the source of reflected radiation, e.g., the camera, and the wafer. The inert gas removes the contaminants by entrainment.

  1. Development of a fixed abrasive slicing technique (FAST) for reducing the cost of photovoltaic wafers

    SciTech Connect

    Schmid, F. )

    1991-12-01

    This report examines a wafer slicing technique developed by Crystal Systems, Inc. that reduces the cost of photovoltaic wafers. This fixed, abrasive slicing technique (FAST) uses a multiwire bladepack and a diamond-plated wirepack; water is the coolant. FAST is in the prototype production stage and reduces expendable material costs while retaining the advantages of a multiwire slurry technique. The cost analysis revealed that costs can be decreased by making more cuts per bladepack and slicing more wafers per linear inch. Researchers studied the degradation of bladepacks and increased wirepack life. 21 refs.

  2. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sang Min; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Vukkadala, Pradeep; Awasthi, Amartya; Kim, J. H.; Veeraraghavan, Sathish; Choi, DongSub; Huang, Kevin; Dighe, Prasanna; Lee, Cheouljung; Byeon, Jungho; Dey, Soham; Sinha, Jaydeep

    2015-03-01

    Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes - which is directly related to

  3. The removal of deformed submicron particles from silicon wafers by spin rinse and megasonics

    NASA Astrophysics Data System (ADS)

    Zhang, Fan; Busnaina, Ahmed A.; Fury, Michael A.; Wang, Shi-Qing

    2000-02-01

    In order to successfully clean particulate contamination from wafer surfaces, it is necessary to understand the adhesion and deformation between the particles and the substrate in contact. The adhesion and removal mechanisms of deformed submicron particles have not been addressed in many previous studies. Submicron polystyrene latex particles (0.1-0.5 µm) were deposited on silicon wafers and removed by spin rinse and megasonic cleanings. Particle rolling is identified as the major removal mechanism for the deformed submicron particles from silicon wafers. Megasonics provides larger streaming velocity because of the extremely thin boundary layer resulting in a larger removal force that is capable of achieving complete removal of contamination particles.

  4. Low temperature solder process to join a copper tube to a silicon wafer

    NASA Astrophysics Data System (ADS)

    Versteeg, Christo; Scarpim de Souza, Marcio

    2014-06-01

    With the application for wafer level packages, which could be Complementary Metal-Oxide-Semiconductor (CMOS) based, and which requires a reduced atmosphere, a copper tube connection to a vacuum pump and the package is proposed. The method evaluated uses laser assisted brazing of a solder, to join the copper tube to a silicon wafer. The method was applied to a silicon wafer coated with a metallic interface to bond to the solder. The hermeticity of the joint was tested with a helium leak rate tester and the bonding energy thermal extent was verified with a thin layer of indium that melted wherever the substrate temperature rose above its melting temperature.

  5. Fast wafer-level detection and control of interconnect reliability

    NASA Astrophysics Data System (ADS)

    Foley, Sean; Molyneaux, James; Mathewson, Alan

    2000-08-01

    Many of the technological advances in the semiconductor industry have led to dramatic increases in device density and performance in conjunction with enhanced circuit reliability. As reliability is improved, the time taken to characterize particular failure modes with traditional test methods is getting substantially longer. Furthermore, semiconductor customers expect low product cost and fast time-to-market. The limits of traditional reliability testing philosophies are being reached and new approaches need to be investigated to enable the next generation of highly reliable products to be tested. This is especially true in the area of IC interconnect, where significant challenges are predicted for the next decade. A number of fast, wafer level test methods exist for interconnect reliability evaluation. The relative abilities of four such methods to detect the quality and reliability of IC interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are bench-marked against conventional package level Median Time to Failure results. The Isothermal test method combine with SWEAT-type test structures is shown to be the most suitable combination for defect detection and interconnect reliability control over very short test times.

  6. Adhesive disbond detection using piezoelectric wafer active sensors

    NASA Astrophysics Data System (ADS)

    Roth, William; Giurgiutiu, Victor

    2015-04-01

    The aerospace industry continues to increase the use of adhesives for structural bonding due to the increased joint efficiency (reduced weight), even distribution of the load path and decreases in stress concentrations. However, the limited techniques for verifying the strength of adhesive bonds has reduced its use on primary structures and requires an intensive inspection schedule. This paper discusses a potential structural health monitoring (SHM) technique for the detection of disbonds through the in situ inspection of adhesive joints. This is achieved through the use of piezoelectric wafer active sensors (PWAS), thin unobtrusive sensors which are permanently bonded to the aircraft structure. The detection method discussed in this study is electromechanical impedance spectroscopy (EMIS), a local vibration method. This method detects disbonds from the change in the mechanical impedance of the structure surrounding the disbond. This paper will discuss how predictive modeling can provide valuable insight into the inspection method, and provide better results than empirical methods alone. The inspection scheme was evaluated using the finite element method, and the results were verified experimentally using a large aluminum test article, and included both pristine and disbond coupons.

  7. Evolution of grain structures during directional solidification of silicon wafers

    NASA Astrophysics Data System (ADS)

    Lin, H. K.; Wu, M. C.; Chen, C. C.; Lan, C. W.

    2016-04-01

    The evolution of grain structures, especially the types of grain boundaries (GBs), during directional solidification is crucial to the electrical properties of multicrystalline silicon used for solar cells. To study this, the electric molten zone crystallization (EMZC) of silicon wafers at different drift speeds from 2 to 6 mm/min was considered. It was found that <111> orientation was dominant at the lower drift velocity, while <112> orientation at the higher drift velocity. Most of the non-∑GBs tended to align with the thermal gradient, but some tilted toward the unfavorable grains having higher interfacial energies. On the other hand, the tilted ∑3GBs tended to decrease during grain competition, except at the higher speed, where the twin nucleation became frequent. The competition of grains separated by ∑GBs could be viewed as the interactions of GBs that two coherent ∑3n GBs turned into one ∑3nGB following certain relations as reported before. On the other hand, when ∑ GBs met non-∑ GBs, the non-∑ GBs remained which explained the decrease of ∑ GBs at the lower speed.

  8. A study on wafer level vacuum packaging for MEMS devices

    NASA Astrophysics Data System (ADS)

    Lee, Byeungleul; Seok, Seonho; Chun, Kukjin

    2003-09-01

    A new vacuum packaging process at the wafer level is developed for the surface micromachining devices using glass-silicon anodic bonding technology. The rim for the glass-silicon bonding process which is needed to prevent vacuum leakage is built up simultaneously as the structure is being etched. The mechanical resonator is used as a tool for evaluating the vacuum level of the packaging. The inside pressure of the packaged device was measured indirectly by measuring the quality factor of the mechanical resonator. The measured Q factor was about 5 × 104 and the estimated inner pressure was about 1 mTorr. It is also possible to change the inside pressure of the packaged devices from 2 Torr to 1 mTorr by varying the amount of Ti getter material. The yield of the vacuum packaging process is about 80% and vacuum degradation was not observed after 1000 h had passed. The developed vacuum packaging process is also applied to resonant accelerometers which need a high vacuum environment to implement higher performance.

  9. Wafer-level self-packaged infrared microsensors

    NASA Astrophysics Data System (ADS)

    Mahmoud, Aamer; Dave, Aasutosh; Celik-Butler, Zeynep; Butler, Donald P.

    2004-08-01

    One common requirement of microbolometers fabricated on both rigid and flexible substrates is the need for vacuum packaging to eliminate the thermal conductivity of air and achieve high performance. However, vacuum packaging of microbolometers is expensive and is a limiting factor in achieving truly low-cost uncooled infrared detection. Vacuum packing of microbolometers on flexible substrates requires a novel approach unless flexibility is to be sacrificed. This paper explores the vacuum packaging of microbolometers through self-packaging. In this case, the micromachined encapsulation in a vacuum cavity is investigated through computer simulation of microbolometers in flexible polyimide films and through the encapsulation of microbolometers on rigid Si substrates with a Si3N4 shell. In this manner, self packaged uncooled microbolometers were fabricated on a Si wafer with semiconducting yttrium barium copper oxide (YBCO) as the infrared sensing material. The self-packaged structure is designed such that it can be covered with a superstrate, yielding low stress in the flexible skin sensors and better detection figures of merit. The devices have demonstrated voltage responsivities over 103 V/W, detectivities above 106 cm Hz1/2/W and temperature coefficient of resistance around -3.3% K-1. Computer simulations using CoventorWare and MEMulator have been used to determine suitable materials for the process, the optimum design of a vacuum element and a streamlined process flow.

  10. High uniform growth of 4-inch GaN wafer via flow field optimization by HVPE

    NASA Astrophysics Data System (ADS)

    Cheng, Yutian; Liu, Peng; Wu, Jiejun; Xiang, Yong; Chen, Xinjuan; Ji, Cheng; Yu, Tongjun; Zhang, Guoyi

    2016-07-01

    The uniformity of flow field inner the reactor plays a crucial role for hydride vapor phase epitaxy (HVPE) crystal growth and its more important for large scale substrate. A new nozzle structure was designed by adding a push and dilution (PD) gas pipe in the center of gas channels for a 4-inch HVPE (PD-HVPE) system. Experimental results showed that the thickness inhomogeneity of 46 μm 4-inch GaN layer could reach ±1.8% by optimizing PD gas, greatly improved from ±14% grown with conventional nozzle. The simulations of the internal flow field were consistent with our experiment, and the enhancement in uniformity should be attributed to the redistribution of GaCl and NH3 upon the wafer induced by PD pipe. The full width at half maximum (FWHM) of X-ray diffraction rocking curves for the 4-inch GaN film were about 224 and 200 arcsec for (002) and (102) reflection. The dislocation density of as-grown GaN was about 6.4×107 cm-2.

  11. Disbond detection with piezoelectric wafer active sensors in RC structures strengthened with FRP composite overlays

    NASA Astrophysics Data System (ADS)

    Giurgiutiu, Victor; Harries, Kent; Petrou, Michael; Bost, Joel; Quattlebaum, Josh B.

    2003-12-01

    The capability of embedded piezoelectric wafer active sensors (PWAS) to perform in-situ nondestructive evaluation (NDE) for structural health monitoring (SHM) of reinforced concrete (RC) structures strengthened with fiber reinforced polymer (FRP) composite overlays is explored. First, the disbond detection method were developed on coupon specimens consisting of concrete blocks covered with an FRP composite layer. It was found that the presence of a disbond crack drastically changes the electromechanical (E/M) impedance spectrum measured at the PWAS terminals. The spectral changes depend on the distance between the PWAS and the crack tip. Second, large scale experiments were conducted on a RC beam strengthened with carbon fiber reinforced polymer (CFRP) composite overlay. The beam was subject to an accelerated fatigue load regime in a three-point bending configuration up to a total of 807,415 cycles. During these fatigue tests, the CFRP overlay experienced disbonding beginning at about 500,000 cycles. The PWAS were able to detect the disbonding before it could be reliably seen by visual inspection. Good correlation between the PWAS readings and the position and extent of disbond damage was observed. These preliminary results demonstrate the potential of PWAS technology for SHM of RC structures strengthened with FRP composite overlays.

  12. Long persistent near infrared luminescence nanoprobes LiGa5O8:Cr3+-PEG-OCH3 for in vivo imaging

    NASA Astrophysics Data System (ADS)

    Fu, Xiaoyan; Liu, Chunlin; Shi, Junpeng; Man, Huizi; Xu, Jia; Zhang, Hongwu

    2014-09-01

    The Cr3+-doped LiGa5O8 nanoparticles (LGNPs) with long-persistent near-infrared phosphorescence were obtained through a sol-gel approach followed by heat treatment at 800 °C in air. The obtained results reveal that the nanoparticles with an average diameter of 100 nm are well defined and have pure structure of LiGa5O8. After illumination for 3 min using a 254 nm UV lamp, the LGNPs exhibit strong near-infrared peak at ca. 720 nm belonging to tissue transparency window which can last for more than 1 h. Via surface modified with PEG-5000-OCH3, the LGNPs-PEG-OCH3 exhibit excellent biocompatibility and low toxicity. Under in vitro pre-excitation using a 254 nm UV lamp for 3 min, the in vivo distribution of the LGNPs-PEG-OCH3 in the abdomen can be detected in real time for more than 1 h. All the results indicate that the LGNPs-PEG-OCH3 can be used as potential nanoprobes to realize in vivo, real time and long time imaging with high sensitivity.

  13. Fabrication of capacitive absolute pressure sensor using Si-Au eutectic bonding in SOI wafer

    NASA Astrophysics Data System (ADS)

    Ryeol Lee, Kang; Kim, Kunnyun; Park, Hyo-Derk; Kim, Yong Kook; Choi, Seung-Woo; Choi, Woo-Beom

    2006-04-01

    A capacitive absolute pressure sensor was fabricated using a large deflected diaphragm with a sealed vacuum cavity formed by removing handling silicon wafer and oxide layers from a SOI wafer after eutectic bonding of a silicon wafer to the SOI wafer. The deflected displacements of the diaphragm formed by the vacuum cavity in the fabricated sensor were similar to simulation results. Initial capacitance values were about 2.18pF and 3.65pF under normal atmosphere, where the thicknesses of the diaphragm used to fabricate the vacuum cavity were 20 µm and 30 µm, respectively. Also, it was confirmed that the differences of capacitance value from 1000hPa to 5hPa were about 2.57pF and 5.35pF, respectively.

  14. On-wafer vector network analyzer measurements in the 220-325 Ghz frequency band

    NASA Technical Reports Server (NTRS)

    Fung, King Man Andy; Dawson, D.; Samoska, L.; Lee, K.; Oleson, C.; Boll, G.

    2006-01-01

    We report on a full two-port on-wafer vector network analyzer test set for the 220-325 GHz (WR3) frequency band. The test set utilizes Oleson Microwave Labs frequency extenders with the Agilent 8510C network analyzer. Two port on-wafer measurements are made with GGB Industries coplanar waveguide (CPW) probes. With this test set we have measured the WR3 band S-parameters of amplifiers on-wafer, and the characteristics of the CPW wafer probes. Results for a three stage InP HEMT amplifier show 10 dB gain at 235 GHz [1], and that of a single stage amplifier, 2.9 dB gain at 231 GHz. The approximate upper limit of loss per CPW probe range from 3.0 to 4.8 dB across the WR3 frequency band.

  15. {ital In} {ital situ} wafer temperature monitoring of silicon etching using diffuse reflectance spectroscopy

    SciTech Connect

    Booth, J.L.; Beard, B.T.; Stevens, J.E.; Blain, M.G.; Meisenheimer, T.L.

    1996-07-01

    Real time, {ital in} {ital situ} temperature measurements during chemical downstream etching of silicon wafers have been performed using a diffuse reflectance spectroscopy based sensor [Weilmeier {ital et} {ital al}., Can. J. Phys. {bold 69}, 422 (1991)]. The spectrometer has a spatial resolution of 1 cm{sup 2}, updates the temperature every 2 s, and has a temperature resolution of better than 1{degree}C. The thermal time constant the wafers and the thermally regulated electrostatic chuck (10{degree}C{lt}{ital T}{lt}90{degree}C) varied between 7 and 30 s depending on clamping and backside gas pressure. The exothermic etch process is accompanied by increases in the silicon wafer temperature consistent with the thermal conductivity conditions and with the etch chemistry. The temperature uniformity across the wafers was better than 2{degree}C during the entire etch process. {copyright} {ital 1996 American Vacuum Society}

  16. Photocatalytic water disinfection by simple and low-cost monolithic and heterojunction ceramic wafers.

    PubMed

    Makwana, Neel M; Hazael, Rachael; McMillan, Paul F; Darr, Jawwad A

    2015-06-01

    In this work, the photocatalytic disinfection of Escherichia coli (E. coli) using dual layer ceramic wafers, prepared by a simple and low-cost technique, was investigated. Heterojunction wafers were prepared by pressing TiO2 and WO3 powders together into 2 layers within a single, self-supported monolith. Data modelling showed that the heterojunction wafers were able to sustain the formation of charged species (after an initial "charging" period). In comparison, a wafer made from pure TiO2 showed a less desirable bacterial inactivation profile in that the rate decreased with time (after being faster initially). The more favourable kinetics of the dual layer system was due to superior electron-hole vectorial charge separation and an accumulation of charges beyond the initial illumination period. The results demonstrate the potential for developing simplified photocatalytic devices for rapid water disinfection. PMID:25976167

  17. Surface self-assembly of N-fluorenyl-9-methoxycarbonyl diphenylalanine on silica wafer.

    PubMed

    Liu, Yun; Xu, Xiao-Ding; Chen, Jing-Xiao; Cheng, Han; Zhang, Xian-Zheng; Zhuo, Ren-Xi

    2011-10-01

    N-Fluorenyl-9-methoxycarbonyl diphenylalanine (Fmoc-FF-OH) was chemically immobilized to the surface of silica wafer as the "seed". When immersing this peptide attached silica wafer into the dipeptide aqueous solution, the occurrence of a pH triggered surface self-assembly resulted in the formation of peptide nanorods on the surface of silica wafer. This surface self-assembly exhibited a dependence on the concentration of the dipeptide aqueous solution. It was proposed that the self-assembly of this dipeptide on the surface of silica wafer was similar to that in aqueous solution. In comparison with the conventional physical adsorption on the substrates, the chemically attached self-assembled nanorods exhibited much improved adsorption capacity on the substrate surface. PMID:21612897

  18. Influence of thermal load on 450 mm Si-wafer IPD during lithographic patterning

    NASA Astrophysics Data System (ADS)

    Peschel, Thomas; Kalkowski, Gerhard; Eberhardt, Ramona

    2012-03-01

    We report on Finite Element Modeling (FEM) of the influence of heat load due to the lithographic exposure on the inplane distortion (IPD) of 450 mm Si-wafers and hence on the effect of the heat load on the achievable image placement accuracy. Based on a scenario of electron beam writing at an exposure power of 20 mW, the thermo-mechanical behavior of the chuck and the attached Si wafer is modeled and used to derive corresponding IPD values. To account for the pin structured chuck surface, an effective layer model is derived. Different materials for the wafer chuck are compared with respect to their influence on wafer IPD and thermal characteristics of the exposure process. Guidelines for the selection of the chuck material und suggestions for its cooling and corrective strategies on e-beam steering during exposure are derived.

  19. Analysis of organic contaminants from silicon wafer and disk surfaces by thermal desorption-GC-MS

    NASA Astrophysics Data System (ADS)

    Camenzind, Mark J.; Ahmed, Latif; Kumar, Anurag

    1999-03-01

    Organic contaminants can affect semiconductor wafer processing including gate oxide integrity, polysilicon growth, deep ultraviolet photoresist line-width, and cleaning & etching steps. Organophosphates are known to counter dope silicon wafers. Organic contaminants in disk drives can cause failures due to stiction or buildup on the heads. Therefore, it is important to identify organic contaminants adsorbed on wafer or disk surfaces and find their sources so they can be either completely eliminated or at least controlled. Dynamic headspace TD-GC-MS (Thermal Desorption-Gas Chromatography-Mass Spectrometry) methods are very sensitive and can be used to identify organic contaminants on disks and wafers, in air, or outgassing from running drives or their individual components.

  20. A study of defects on EUV mask using blank inspection, patterned mask inspection, and wafer inspection

    SciTech Connect

    Huh, S.; Ren, L.; Chan, D.; Wurm, S.; Goldberg, K. A.; Mochi, I.; Nakajima, T.; Kishimoto, M.; Ahn, B.; Kang, I.; Park, J.-O.; Cho, K.; Han, S.-I.; Laursen, T.

    2010-03-12

    The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing. yet link data is available for understanding native defects on real masks. In this paper, a full-field EUV mask is fabricated to investigate the printability of various defects on the mask. The printability of defects and identification of their source from mask fabrication to handling were studied using wafer inspection. The printable blank defect density excluding particles and patterns is 0.63 cm{sup 2}. Mask inspection is shown to have better sensitivity than wafer inspection. The sensitivity of wafer inspection must be improved using through-focus analysis and a different wafer stack.