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Sample records for wafer scale liga

  1. A Batch Wafer Scale LIGA Assembly and Packaging Technique vai Diffusion Bonding

    SciTech Connect

    Christenson, T.R.; Schmale, D.T.

    1999-01-27

    A technique using diffusion bonding (or solid-state welding) has been used to achieve batch fabrication of two- level nickel LIGA structures. Interlayer alignment accuracy of less than 1 micron is achieved using press-fit gauge pins. A mini-scale torsion tester was built to measure the diffusion bond strength of LIGA formed specimens that has shown successful bonding at temperatures of 450"C at 7 ksi pressure with bond strength greater than 100 Mpa. Extensions to this basic process to allow for additional layers and thereby more complex assemblies as well as commensurate packaging are discussed.

  2. The influence of wafer elasticity on acoustic waves during LIGA development.

    SciTech Connect

    Ting, Aili

    2003-12-01

    During acoustically stimulated LIGA development, a wafer receives sound waves from both sides at a wide variety of incidence angles that vary in time depending on the orientation of the wafer relative to the multiple transducers that are typically actuated in a periodic sequence. It is important to understand the influence of these variables on the transmission of energy through the wafer as well as the induced motion of the wafer itself because these processes impact the induced acoustic streaming of the fluid within features, the mechanism presently thought responsible for enhanced development of LIGA features. In the present work, the impact of wafer elasticity on LIGA development is investigated. Transmission waves, wafer bending waves, and the related concepts such as critical bending frequency, mechanical impedance, coincidence, and resonance, are discussed. Supercritical-frequency incident waves induce supersonic bending waves in the wafer. Incident wave energy is channeled into three components, transmitted, reflected and energy deposited to the wafer, depending on the wafer material, thickness and wave incidence angle. Results show at normal incidence for a 1-mm PMMA wafer, about 47% of the wave energy is deposited in the wafer. The wafer gains almost half of the incident energy, a result that agrees well with the Bankert et a1 measurements. In LIGA development, transmitted waves may sometimes produce strong acoustic motion of the developer on the wafer backside, especially for the so-called coincidence case in which almost all incident wave energy transfers to the backside. Wafer bending waves cause wafer oscillation at high frequency, promoting the development process, but features shaking may weaken their attachments to the substrate. Resonance is not likely for the entire wafer, but may occur in short and wide wafer feature columns, which are least likely to break away from the substrate, perhaps resulting in good agitation of the fluid in adjacent feature cavities.

  3. LIGA Scanner Control Software

    Energy Science and Technology Software Center (ESTSC)

    1999-02-01

    The LIGA Scanner Software is a graphical user interface package that facilitates controlling the scanning operation of x-rays from a synchrotron and sample manipulation for making LIGA parts. The process requires scanning of the LIGA mask and the PMMA resist through a stationary x-ray beam to provide an evenly distributed x-ray exposure over the wafer. This software package has been written specifically to interface with Aerotech motor controllers.

  4. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  5. Parallel Assembly of LIGA Components

    SciTech Connect

    Christenson, T.R.; Feddema, J.T.

    1999-03-04

    In this paper, a prototype robotic workcell for the parallel assembly of LIGA components is described. A Cartesian robot is used to press 386 and 485 micron diameter pins into a LIGA substrate and then place a 3-inch diameter wafer with LIGA gears onto the pins. Upward and downward looking microscopes are used to locate holes in the LIGA substrate, pins to be pressed in the holes, and gears to be placed on the pins. This vision system can locate parts within 3 microns, while the Cartesian manipulator can place the parts within 0.4 microns.

  6. Wafer-scale aluminum nano-plasmonics

    NASA Astrophysics Data System (ADS)

    George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

    2014-09-01

    The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

  7. IGBT scaling principle toward CMOS compatible wafer processes

    NASA Astrophysics Data System (ADS)

    Tanaka, Masahiro; Omura, Ichiro

    2013-02-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

  8. Wafer-scale fabrication of penetrating neural microelectrode arrays.

    PubMed

    Bhandari, Rajmohan; Negi, Sandeep; Solzbacher, Florian

    2010-10-01

    The success achieved with implantable neural interfaces has motivated the development of novel architectures of electrode arrays and the improvement of device performance. The Utah electrode array (UEA) is one example of such a device. The unique architecture of the UEA enables single-unit recording with high spatial and temporal resolution. Although the UEA has been commercialized and been used extensively in neuroscience and clinical research, the current processes used to fabricate UEA's impose limitations in the tolerances of the electrode array geometry. Further, existing fabrication costs have led to the need to develop less costly but higher precision batch fabrication processes. This paper presents a wafer-scale fabrication method for the UEA that enables both lower costs and faster production. More importantly, the wafer-scale fabrication significantly improves the quality and tolerances of the electrode array and allow better controllability in the electrode geometry. A comparison between the geometrical and electrical characteristics of the wafer-scale and conventional array-scale processed UEA's is presented. PMID:20480240

  9. Wafer-scale aluminum plasmonics for fluorescence based biodetection

    NASA Astrophysics Data System (ADS)

    Farhang, Arash; George, Matthew C.; Williamson, Brent; Black, Mike; Wangensteen, Ted; Fraser, James; Petrova, Rumyana; Prestgard, Kent

    2015-08-01

    Moxtek has leveraged existing capabilities in wafer-scale patterning of sub-wavelength wire grid polarizers into the fabrication of 1D and 2D periodic aluminum plasmonic structures. This work will discuss progress in 200 mm diameter wafer-scale fabrication, with detailed emphasis within the realm of microarray based fluorescence detection. Aluminum nanohole arrays in a hexagonal lattice are first numerically investigated. The nanohole array geometry and periodicity are specifically tuned to coincide both with the excitation of the fluorophore Cy3, and to provide a high field enhancement within the nanoholes where labeled biomolecules are captured. This is accomplished through numerical modelling, nanofabrication, SEM imaging, and optical characterization. A 200mm diameter wafer, patterned with the optically optimized nanohole array, is cut into standard 1x3 inch microscope slide pieces and then subsequently printed with various antigens at 9 different concentrations. A sandwich bioassay is then carried out, using the corresponding conjugate antibodies in order to demonstrate specificity. The nanohole array exhibit a 3-4 times total fluorescence enhancement of Cy3, when compared to a leading commercial microarray glass slide.

  10. Wafer-scale nanowell array patterning based electrochemical impedimetric immunosensor.

    PubMed

    Lee, JuKyung; Cho, SiHyeong; Lee, JungHwan; Ryu, HeonYul; Park, JinGoo; Lim, SunHee; Oh, ByungDo; Lee, ChangWoo; Huang, Wilber; Busnaina, Ahmed; Lee, HeaYeon

    2013-12-01

    We have reported that nanowell array (NWA) can enhance electrochemical detection of molecular binding events by controlling the binding sites of the captured molecules. Using NWA biosensor based amperometric analysis, we have detected biological macromolecules such as DNA, protein or aptamers at low concentrations. In this research, we developed an impedimetric immunosensor based on wafer-scale NWA for electrochemical detection of stress-induced-phosphoprotein-1 (STIP-1). In order to develop NWA sensor through the cost-effective combination of high-throughput nanopattern, the NWA electrode was fabricated on Si wafer by krypton-fluoride (KrF) stepper semiconductor process. Finally, 12,500,000 ea nanowell with a 500 nm diameter was fabricated on 4 mm × 2 mm substrate. Next, by using these electrodes, we measured impedance to quantify antigen binding to the immunoaffinity layer. The limit of detection (LOD) of the NWA was improved about 100-fold compared to milli-sized electrodes (4 mm × 2 mm) without an NWA. These results suggest that wafer-scale NWA immunosensor will be useful for biosensing applications because their interface response is appropriate for detecting molecular binding events. PMID:24013070

  11. Liga developer apparatus system

    DOEpatents

    Boehme, Dale R. (Pleasanton, CA); Bankert, Michelle A. (San Francisco, CA); Christenson, Todd R. (Albuquerque, NM)

    2003-01-01

    A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

  12. Wafer-scale plasmonic and photonic crystal sensors

    NASA Astrophysics Data System (ADS)

    George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

    2015-08-01

    200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

  13. Towards Wafer-Scale Monocrystalline Graphene Growth and Characterization.

    PubMed

    Nguyen, Van Luan; Lee, Young Hee

    2015-08-01

    Since its discovery in 2004, graphene has boosted numerous fundamental sciences and technological applications due to its massless Dirac particle-like linear band dispersion, that causes unprecedented physical properties. Among the various methods for synthesizing graphene, chemical vapor deposition is the most suitable approach for scalable production on a wafer scale, which is a critical step for practical applications. Graphene grain boundaries (GGBs), consisting of nonhexagonal carbon rings and therefore modulating the properties of graphene films, are inevitably formed via the merging of adjacent graphene domains with different orientations. Large-area monocrystalline graphene synthesis without forming GGBs has been challenging, let alone observing such boundaries. Here, an up-to-date review is presented of how to grow wafer-scale monocrystalline graphene without GGBs. One approach is to make single domain sizes as large as possible by reducing or passivating the number of nucleation sites. Another approach is to align graphene domains in identical orientations, and then merge them atomically. The recently developed methods for observing graphene orientation and GGBs both at the atomic and macro-scales are also presented. Finally, perspectives for future research in graphene growth are discussed. PMID:25903119

  14. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

  15. Nickel Micro-spike for Micro-scale Biopsy using LiGA Process

    NASA Astrophysics Data System (ADS)

    Kim, Gilsub; Park, Sunkil; Koo, Kyo-In; Choi, Hyun-Min; Jung, Myeong-Jun; Song, Si-Young; Bang, Seoung-Min; Cho, Dongil ``Dan''

    2007-01-01

    In this paper, biopsy tools are developed for minimally invasive tissue sampling using the LiGA (Lithographie Galvanoformung Abformung) process. The micro-spike is composed of two barbed-shanks and a body. The shank of the micro-spike is between 2 mm 3 mm and the opening gap is approximately 350 ?m between the shanks. The micro-spike is integrated with the conventional catheter, for medical diagnostics. Tissue samples were extracted from the anesthetized pigs using biopsy catheters in vivo, and observed with hematoxylin and eosin (H&E) staining. The amount of extracted sample is sufficient to diagnose abnormal cells.

  16. Fabrication of phone-camera module using wafer-scale UV embossing process

    NASA Astrophysics Data System (ADS)

    Shin, Dong-Ik; Kim, Sung-Kwa; Jeong, Ho-Seop; Lee, Seok Cheon; Jin, YoungSu; Noh, JungEun; Oh, HyeRan; Lee, KiUn; Shin, Dong Ho; Song, Seok Ho

    2006-02-01

    We have developed a compact and cost-effective camera module on the basis of wafer-scale-replica processing. A multiple-layered structure of several aspheric lenses in a mobile-phone camera module is first assembled by bonding multiple glass-wafers on which 2-dimensional replica arrays of identical aspheric lenses are UV-embossed, followed by dicing the stacked wafers and packaging them with image sensor chips. This wafer-scale processing leads to at least 95% yield in mass-production, and potentially to a very slim phone with camera-module less than 2 mm in thickness. We have demonstrated a VGA camera module fabricated by the wafer-scale-replica processing with various UV-curable polymers having refractive indices between 1.4 and 1.6, and with three different glass-wafers of which both surfaces are embossed as aspheric lenses having 230 ?m sag-height and aspheric-coefficients of lens polynomials up to tenth-order. We have found that precise compensation in material shrinkage of the polymer materials is one of the most technical challenges, in order to achieve a higher resolution in wafer-scaled lenses for mobile-phone camera modules.

  17. Wafer-scale fabrication of plasmonic crystals from patterned silicon templates prepared by nanosphere lithography.

    PubMed

    Hall, Anthony Shoji; Friesen, Stuart A; Mallouk, Thomas E

    2013-06-12

    By combining nanosphere lithography with template stripping, silicon wafers were patterned with hexagonal arrays of nanowells or pillars. These silicon masters were then replicated in gold by metal evaporation, resulting in wafer-scale hexagonal gratings for plasmonic applications. In the nanosphere lithography step, two-dimensional colloidal crystals of 510 nm diameter polystyrene spheres were assembled at the air-water interface and transferred to silicon wafers. The spheres were etched in oxygen plasma in order to define their size for masking of the silicon wafer. For fabrication of metallic nanopillar arrays, an alumina film was grown over the nanosphere layer and the spheres were then removed by bath sonication. The well pattern was defined in the silicon wafer by reactive ion etching in a chlorine plasma. For fabrication of metal nanowell arrays, the nanosphere monolayer was used directly as a mask and exposed areas of the silicon wafer were plasma-etched anisotropically in SF6/Ar. Both techniques could be used to produce subwavelength metal replica structures with controlled pillar or well diameter, depth, and profile, on the wafer scale, without the use of direct writing techniques to fabricate masks or masters. PMID:23614608

  18. Pressure Waves Induced by Megasonic Agitation in a LIGA Development Tank

    SciTech Connect

    Aili Ting

    2002-08-01

    Megasonic agitation is used to improve the uniformity of the LIGA{sup 1} development process. To investigate the acoustic wave fields induced by megasonic agitation, we compute wave fields for a development tank containing a submerged wafer and for a typical trench-like feature on the wafer face. This separate treatment of these two problems is advantageous, because the length scales of the tank and the feature differ by three to four orders of magnitude. A spectral method based on Green's functions is used to construct the acoustic wave field, avoiding the alternative of solving partial differential equations over the entire domain. The total acoustic wave field is obtained by superposing of the primary wave field and the first reflected wave field, which are computed in sequence without any need for iterations. The wafer interference to the wave field is treated directly by a priori recognition of shadow regions in the primary field and a concept of boundary of dependence in the reflected field. Unlike a divergent wave field produced by ultrasonic agitation, results show that the wave field in the tank becomes narrowly focused at megasonic frequencies such that the most effective agitation is confined in a region directly above the acoustic source; this numerical expectation has been verified analytically and further confirmed experimentally by Sandia's LIGA Group.{sup [13]} The amplitude of the focused wave pressure is proportional to square root of the wave frequency. The wave pattern in a feature cavity also depends strongly on the orientation of the wafer and the aspect ratio of the cavity. It is concluded that the LIGA development process will be greatly accelerated, if the orientation and the location of the immersed wafer is arranged so that the wafer spends more time in the focused wave field of high frequency agitation.

  19. Wafer-scale growth of VO2 thin films using a combinatorial approach.

    PubMed

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C; Alem, Nasim; Engel-Herbert, Roman

    2015-01-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that 'electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

  20. Wafer-scale growth of VO2 thin films using a combinatorial approach

    NASA Astrophysics Data System (ADS)

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

    2015-10-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that `electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems.

  1. Wafer-scale metamaterials for polarization-insensitive and dual-band perfect absorption

    NASA Astrophysics Data System (ADS)

    Liu, Jia; Zhu, Maoxia; Zhang, Nan; Zhang, Haitao; Zhou, Yu; Sun, Shang; Yi, Ningbo; Gao, Shang; Song, Qinghai; Xiao, Shumin

    2015-11-01

    Mid-infrared (IR) perfect absorbers have great potential in practical applications such as biomedical sensing and thermal energy and have been successfully demonstrated in a number of plasmonic metallic nanostructures. However, all the experimental realizations of perfect absorbers are strongly dependent on nanofabrication techniques, which usually require high costs and a long time to fabricate a wafer scale device. Here we propose and experimentally demonstrate a wafer scale, polarization independent, wide angle, and dual-band IR perfect absorber. By fabricating double ``E''-shaped metallic structures on a ZnSe coated gold film, a dual-band metamaterial absorber has been uniformly realized on a 2'' silicon wafer. Two absorption peaks have been realized at 18 and 27 THz, which are well consistent with the designs. We believe that our research will boost the applications of metamaterial perfect absorbers.

  2. Wafer-scale metamaterials for polarization-insensitive and dual-band perfect absorption.

    PubMed

    Liu, Jia; Zhu, Maoxia; Zhang, Nan; Zhang, Haitao; Zhou, Yu; Sun, Shang; Yi, Ningbo; Gao, Shang; Song, Qinghai; Xiao, Shumin

    2015-12-01

    Mid-infrared (IR) perfect absorbers have great potential in practical applications such as biomedical sensing and thermal energy and have been successfully demonstrated in a number of plasmonic metallic nanostructures. However, all the experimental realizations of perfect absorbers are strongly dependent on nanofabrication techniques, which usually require high costs and a long time to fabricate a wafer scale device. Here we propose and experimentally demonstrate a wafer scale, polarization independent, wide angle, and dual-band IR perfect absorber. By fabricating double "E"-shaped metallic structures on a ZnSe coated gold film, a dual-band metamaterial absorber has been uniformly realized on a 2'' silicon wafer. Two absorption peaks have been realized at 18 and 27 THz, which are well consistent with the designs. We believe that our research will boost the applications of metamaterial perfect absorbers. PMID:26525777

  3. Wafer-scale growth of single-crystal monolayer graphene on reusable hydrogen-terminated germanium.

    PubMed

    Lee, Jae-Hyun; Lee, Eun Kyung; Joo, Won-Jae; Jang, Yamujin; Kim, Byung-Sung; Lim, Jae Young; Choi, Soon-Hyung; Ahn, Sung Joon; Ahn, Joung Real; Park, Min-Ho; Yang, Cheol-Woong; Choi, Byoung Lyong; Hwang, Sung-Woo; Whang, Dongmok

    2014-04-18

    The uniform growth of single-crystal graphene over wafer-scale areas remains a challenge in the commercial-level manufacturability of various electronic, photonic, mechanical, and other devices based on graphene. Here, we describe wafer-scale growth of wrinkle-free single-crystal monolayer graphene on silicon wafer using a hydrogen-terminated germanium buffer layer. The anisotropic twofold symmetry of the germanium (110) surface allowed unidirectional alignment of multiple seeds, which were merged to uniform single-crystal graphene with predefined orientation. Furthermore, the weak interaction between graphene and underlying hydrogen-terminated germanium surface enabled the facile etch-free dry transfer of graphene and the recycling of the germanium substrate for continual graphene growth. PMID:24700471

  4. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

  5. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

  6. Wafer-scale transfer of vertically aligned carbon nanotube arrays.

    PubMed

    Wang, Miao; Li, Taotao; Yao, Yagang; Lu, Huifen; Li, Qiang; Chen, Minghai; Li, Qingwen

    2014-12-31

    The first critical step in making vertically aligned carbon nanotube (VACNT)-based thermal interface materials is to transfer the VACNTs on a large scale. Although VACNTs have been transferred by several methods, they were only transferred inadvertently in most cases. Here we report well-controlled weak-oxidation-assisted transfer of VACNTs. Specifically, after a short time of weak oxidation, we found that VACNTs could be easily detached from the native growth substrates, and thus, a freestanding VACNT film was obtained. Then the VACNTs could be assembled onto specific substrates for its real applications. More importantly, the repeated growth-transfer synthesis of VACNT arrays can be realized in one batch by introducing an additional process of weak oxidation in chemical vapor deposition, which makes the strategy more effective. Surprisingly, no degradation in the quality was observed before and after the weak oxidation according to thermogravimetric analysis and Raman spectra of VACNTs. Enhanced thermal and mechanical properties were achieved after reactive ion etching (RIE) and subsequent metallization of the surfaces of the VACNTs, and this might be due to the removal of impurities such as amorphous carbon and entangled CNTs by RIE. These findings provide an efficient approach for transferring VACNTs, which is important for the application of VACNTs in thermal management. PMID:25490088

  7. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates.

    PubMed

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-19

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes. PMID:26789103

  8. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates

    NASA Astrophysics Data System (ADS)

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-01

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes.

  9. Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments.

    PubMed

    Bomer, Johan G; Prokofyev, Alexander V; van den Berg, Albert; Le Gac, Séverine

    2014-12-01

    We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the microchannels, and alignment precision. Experiments on lipid bilayers with electrophysiological recordings using a model pore-forming polypeptide are demonstrated. PMID:25284632

  10. Wafer-scale growth of VO2 thin films using a combinatorial approach

    PubMed Central

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

    2015-01-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that ‘electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

  11. Terahertz wafer-scale mobility mapping of graphene on insulating substrates without a gate.

    PubMed

    Buron, Jonas D; Mackenzie, David M A; Petersen, Dirch H; Pesquera, Amaia; Centeno, Alba; Bggild, Peter; Zurutuza, Amaia; Jepsen, Peter U

    2015-11-30

    We demonstrate wafer-scale, non-contact mapping of essential carrier transport parameters, carrier mobility (drift), carrier density (Ns), DC sheet conductance (?dc), and carrier scattering time (?sc) in CVD graphene, using spatially resolved terahertz time-domain conductance spectroscopy. ?dc and ?sc are directly extracted from Drude model fits to terahertz conductance spectra obtained in each pixel of 10 10 cm2 maps with a 400 m step size. ?dc- and ?sc-maps are translated into drift and Ns maps through Boltzmann transport theory for graphene charge carriers and these parameters are directly compared to van der Pauw device measurements on the same wafer. The technique is compatible with all substrate materials that exhibit a reasonably low absorption coefficient for terahertz radiation. This includes many materials used for transferring CVD graphene in production facilities as well as in envisioned products, such as polymer films, glass substrates, cloth, or paper substrates. PMID:26698704

  12. Microfluidic design and fabrication of wafer-scale varifocal liquid lens

    NASA Astrophysics Data System (ADS)

    Lee, Jeong-Yub; Choi, Seung-Tae; Lee, Seung-Wan; Kim, Woonbae

    2009-08-01

    Microfluidic design and fabrication was developed for wafer-scale varifocal liquid lens which is slim less than 0.9mm. The liquid-filled varifocal lens has advanced functions such as auto macro and focusing to obtain a high quality of image. This varifocal lens is similar to human eye and it consists of main Si frame which has penetrated inner hole, upside-bonded PDMS (polydimethylsiloxane) elastomer membrane, downside-bonded glass plate and optical fluid confined by these structures. Si frame, which has a circular hole for tunable lens chamber, several holes for actuator chamber and micro-fluidic channels between chambers, is fabricated using thin Si wafer and microelectromechanical system (MEMS) processes. When optical fluid is filled the internal cavity by conventional injection, void trapping which degrades optical performance or filling impossibility happens because of high aspect ratio between lens diameter and thickness for slim liquid lens. To prevent these problems, we developed wafer-based microfabrications of seal line dispensing, accurate dropping of optical fluid, pressing & bonding process in vacuum and UV sealant curing. Afterward, electro-active polymer actuators, which push the optical fluid to change the lens shape, was attached on the PDMS membrane of liquid lens wafer and sawing process of 9.4mm*9.0mm chip size followed. Finally, the varifocal liquid lens which is slim less than 0.6mm thickness (0.9mm included actuators), tunable more than 20diopter changes of refractive power, guaranteed reliability of 300,000 repetitions and suitable for mass production, was realized.

  13. LIGA Micromachining: Infrastructure Establishment

    SciTech Connect

    Alfredo M. Morales; Barry V. Hess; Dale R. Boehme; Jill M. Hruby; John S. Krafcik; Robert H. Nilson; Stewart K. Griffiths; William D. Bonivert

    1999-02-01

    LIGA is a micromachining technology that uses high energy x-rays from a synchrotron to create patterns with small lateral dimensions in a deep, non-conducting polymeric resist. Typical dimensions for LIGA parts are microns to tens of microns in lateral size, and hundreds of microns to millimeters in depth. Once the resist is patterned, metal is electrodeposited in the features to create metal microparts, or to create a metal mold for subsequent replication. The acronym LIGA comes from the German words for lithography, electroforming, and molding, and the technology has been under worldwide development for more than a decade. over the last five years, a full-service capability to produce metal microparts using the LIGA process has been established at Sandia national Laboratories, California. This report describes the accomplishments made during the past two years in infrastructure establishment funded by a Laboratory Directed Research and Development (LDRD) project entitled ''LIGA Micromachining.'' Specific topics include photoresist processing for LIGA mask making, x-ray scanning equipment, plating bath instrumentation, plating uniformity, and software architecture.

  14. A Wafer-Scale Etching Technique for High Aspect Ratio Implantable MEMS Structures

    PubMed Central

    Bhandari, R; Negi, S; Rieth, L.; Solzbacher, F

    2010-01-01

    Microsystem technology is well suited to batch fabricate microelectrode arrays, such as the Utah electrode array (UEA), intended for recording and stimulating neural tissue. Fabrication of the UEA is primarily based on the use of dicing and wet etching to achieve high aspect ratio (15:1) penetrating electrodes. An important step in the array fabrication is the etching of electrodes to produce needle-shape electrodes with sharp tips. Traditional etching processes are performed on a single array, and the etching conditions are not optimized. As a result, the process leads to variable geometries of electrodes within an array. Furthermore, the process is not only time consuming but also labor-intensive. This report presents a wafer-scale etching method for the UEA. The method offers several advantages, such as substantial reduction in the processing time, higher throughput and lower cost. More importantly, the method increases the geometrical uniformity from electrode to electrode within an array (1.5 0.5 % non-uniformity), and from array to array within a wafer (2 0.3 % non-uniformity). Also, the etching rate of silicon columns, produced by dicing, are studied as a function of temperature, etching time and stirring rate in a nitric acid rich HF-HNO3 solution. These parameters were found to be related to the etching rates over the ranges studied and more-importantly affect the uniformity of the etched silicon columns. An optimum etching condition was established to achieve uniform shape electrode arrays on wafer-scale. PMID:20706618

  15. Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

    PubMed Central

    Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

    2014-01-01

    In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32?A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50?kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

  16. A Method to Pattern Silver Nanowires Directly on Wafer-Scale PDMS Substrate and Its Applications.

    PubMed

    Chou, Namsun; Kim, Youngseok; Kim, Sohee

    2016-03-01

    This study describes a fabrication method of microsized AgNW patterns based on poly dimethylsiloxane (PDMS) substrate using a poly(p-xylylene) (parylene) stencil technique. Various patterns of AgNW conductive sheets were created on the wafer scale area in the forms of straight and serpentine lines, texts, and symbols, which dimensions ranged from a few tens of micrometers to hundreds of micrometers. We demonstrated the electrical performance of straight line and serpentine line patterned AgNW electrodes when subjected to mechanical strains. The gauge factor and stretchability ranged from 0.5 to 55.2 at 2% uniaxial strain and from 4.7 to 55.7%, respectively, depending on the shapes and structures of the AgNW electrodes. Using the developed AgNW patterning technique, we fabricated strain sensors to detect small body signals epidermally such as hand motion, eye blink and heart rate. Also, tactile sensors were fabricated and exhibited the sensitivity of 3.91 MPa(-1) in the pressure range lower than 50 kPa, and 0.28 MPa(-1) in the pressure range greater than 50 kPa up to 1.3 MPa. From these results, we concluded that the proposed technique enables the fabrication of reliable AgNW patterns on wafer-scale PDMS substrate and the potential applications for various flexible electronic devices. PMID:26882099

  17. Face-to-face transfer of wafer-scale graphene films

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene.

  18. Face-to-face transfer of wafer-scale graphene films.

    PubMed

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene. PMID:24336218

  19. Assembly of LIGA using Electric Fields

    SciTech Connect

    FEDDEMA, JOHN T.; WARNE, LARRY K.; JOHNSON, WILLIAM A.; OGDEN, ALLISON J.; ARMOUR, DAVID L.

    2002-04-01

    The goal of this project was to develop a device that uses electric fields to grasp and possibly levitate LIGA parts. This non-contact form of grasping would solve many of the problems associated with grasping parts that are only a few microns in dimensions. Scaling laws show that for parts this size, electrostatic and electromagnetic forces are dominant over gravitational forces. This is why micro-parts often stick to mechanical tweezers. If these forces can be controlled under feedback control, the parts could be levitated, possibly even rotated in air. In this project, we designed, fabricated, and tested several grippers that use electrostatic and electromagnetic fields to grasp and release metal LIGA parts. The eventual use of this tool will be to assemble metal and non-metal LIGA parts into small electromechanical systems.

  20. Fabrication of CVD graphene-based devices via laser ablation for wafer-scale characterization

    NASA Astrophysics Data System (ADS)

    Mackenzie, David M. A.; Buron, Jonas D.; Whelan, Patrick R.; Jessen, Bjarke S.; Silajd?i?, Adnan; Pesquera, Amaia; Centeno, Alba; Zurutuza, Amaia; Bggild, Peter; Petersen, Dirch H.

    2015-12-01

    Selective laser ablation of a wafer-scale graphene film is shown to provide flexible, high speed (1 wafer/hour) device fabrication while avoiding the degradation of electrical properties associated with traditional lithographic methods. Picosecond laser pulses with single pulse peak fluences of 140 mJ cm?2 for 1064 nm, 40 mJ cm?2 for 532 nm, and 30 mJ cm?2 for 355 nm are sufficient to ablate the graphene film, while the ablation onset for Si/SiO2 (thicknesses 500 ?m/302 nm) did not occur until 240 mJ cm?2, 150 mJ cm?2, and 135 mJ cm?2, respectively, allowing all wavelengths to be used for graphene ablation without detectable substrate damage. Optical microscopy and Raman Spectroscopy were used to assess the ablation of graphene, while stylus profilometery indicated that the SiO2 substrate was undamaged. CVD graphene devices were electrically characterized and showed comparable field-effect mobility, doping level, onoff ratio, and conductance minimum before and after laser ablation fabrication.

  1. High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity.

    PubMed

    Kang, Kibum; Xie, Saien; Huang, Lujie; Han, Yimo; Huang, Pinshane Y; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-04-30

    The large-scale growth of semiconducting thin films forms the basis of modern electronics and optoelectronics. A decrease in film thickness to the ultimate limit of the atomic, sub-nanometre length scale, a difficult limit for traditional semiconductors (such as Si and GaAs), would bring wide benefits for applications in ultrathin and flexible electronics, photovoltaics and display technology. For this, transition-metal dichalcogenides (TMDs), which can form stable three-atom-thick monolayers, provide ideal semiconducting materials with high electrical carrier mobility, and their large-scale growth on insulating substrates would enable the batch fabrication of atomically thin high-performance transistors and photodetectors on a technologically relevant scale without film transfer. In addition, their unique electronic band structures provide novel ways of enhancing the functionalities of such devices, including the large excitonic effect, bandgap modulation, indirect-to-direct bandgap transition, piezoelectricity and valleytronics. However, the large-scale growth of monolayer TMD films with spatial homogeneity and high electrical performance remains an unsolved challenge. Here we report the preparation of high-mobility 4-inch wafer-scale films of monolayer molybdenum disulphide (MoS2) and tungsten disulphide, grown directly on insulating SiO2 substrates, with excellent spatial homogeneity over the entire films. They are grown with a newly developed, metal-organic chemical vapour deposition technique, and show high electrical performance, including an electron mobility of 30 cm(2) V(-1) s(-1) at room temperature and 114 cm(2) V(-1) s(-1) at 90 K for MoS2, with little dependence on position or channel length. With the use of these films we successfully demonstrate the wafer-scale batch fabrication of high-performance monolayer MoS2 field-effect transistors with a 99% device yield and the multi-level fabrication of vertically stacked transistor devices for three-dimensional circuitry. Our work is a step towards the realization of atomically thin integrated circuitry. PMID:25925478

  2. Near-infrared tailored thermal emission from wafer-scale continuous-film resonators.

    PubMed

    Roberts, Alexander S; Chirumamilla, Manohar; Thilsing-Hansen, Kasper; Pedersen, Kjeld; Bozhevolnyi, Sergey I

    2015-09-21

    We experimentally investigate the near-infrared emission from simple-to-fabricate, continuous-film Fabry-Perot-type resonators, consisting only of unstructured dielectric and metallic films. We show that the proposed configuration is suitable for realization of narrowband emitters, tunable in ranges from mid- to near-infrared, and demonstrate emission centered at the wavelength of 1.7 μm, which corresponds to the band gap energy of GaSb-based photodetectors. The emission is measured at 748 K and follows well the emissivity as predicted from reflection measurements and Kirchhoff's reciprocity. The considered emitter configuration is spectrally highly tunable and, consisting of only few unstructured layers, is amenable to wafer-scale fabrication at low cost by use of standard deposition procedures. PMID:26406741

  3. High speed wafer scale bulge testing for the determination of thin film mechanical properties.

    PubMed

    Orthner, M P; Rieth, L W; Solzbacher, F

    2010-05-01

    A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50-150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 microm in width comprised of 720+/-10 nm thick low pressure chemical vapor deposited silicon nitride with approximately 20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to approximately 8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (approximately 350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young's modulus was estimated for the films assuming a Poisson's ratio of v=0.25. Calculations to determine Young's modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young's modulus for the smaller membranes. The deflection measurements of three 1200 x 1200 microm(2) Si(3)N(4-x) membranes were taken at increased pressures (>25 kPa) to increase nonlinearity and better determine Young's modulus. This pressure-deflection data were fit to an analytical solution and Young's modulus estimated to be 257+/-3 GPa, close to those previously reported in literature. PMID:20515176

  4. High speed wafer scale bulge testing for the determination of thin film mechanical properties

    PubMed Central

    Orthner, M. P.; Rieth, L. W.; Solzbacher, F.

    2010-01-01

    A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 ?m in width comprised of 72010 nm thick low pressure chemical vapor deposited silicon nitride with ?20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to ?8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (?350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Youngs modulus was estimated for the films assuming a Poissons ratio of v=0.25. Calculations to determine Youngs modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Youngs modulus for the smaller membranes. The deflection measurements of three 12001200 ?m2 Si3N4?x membranes were taken at increased pressures (>25 kPa) to increase nonlinearity and better determine Youngs modulus. This pressure-deflection data were fit to an analytical solution and Youngs modulus estimated to be 2573 GPa, close to those previously reported in literature. PMID:20515176

  5. Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale

    PubMed Central

    2013-01-01

    We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production. PMID:24289275

  6. Wafer-Scale Monolayer Films of Semiconducting Metal Dichalcogenides for High-Performance Electronics

    NASA Astrophysics Data System (ADS)

    Xie, Saien; Kang, Kibum; Huang, Lujie; Han, Yimo; Huang, Pinshane; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-03-01

    Two-dimensional semiconducting transition metal dichalcogenides (TMDs) have shown their potential in electronics, optoelectronic and valleytronis. However, large-scale growth methods reported to date have only produced materials with limited structural and electrical uniformity, hindering further technological applications. Here we present a 4-inch scale growth of continuous monolayer molybdenum disulfide (MoS2) and tungsten disulfide (WS2) films that show excellent structural and electrical uniformity over the entire wafer using metal-organic chemical vapor deposition. The resulting monolayer films show high mobility of 30 cm2/Vs at room temperature, as well as the phonon-limited transport for MoS2, regardless of the channel length and device location. They allow for the batch fabrication of monolayer MoS2 field effect transistors with a 99% yield, which display spatially-uniform n-type transistor operation with a high on/off ratio. We further demonstrate the multi-level growth and fabrication of vertically-stacked monolayer MoS2 films and devices, which could enable the development of novel three-dimensional circuitry and device integration.

  7. A wafer-scale graphene and ferroelectric multilayer for flexible and fast-switched modulation applications

    NASA Astrophysics Data System (ADS)

    Zhu, Minmin; Wu, Jing; Du, Zehui; Tay, Roland Yingjie; Li, Hongling; Özyilmaz, Barbarous; Teo, Edwin Hang Tong

    2015-08-01

    Here we report a wafer-scale graphene/P(VDF-TrFE)/graphene multilayer for light-weight, flexible and fast-switched broadband modulation applications. The P(VDF-TrFE) film not only significantly reduces the sheet resistance of graphene throughout heavy doping of ~0.8 × 1013 cm-2 by nonvolatile ferroelectric dipoles, but also acts as an efficient electro-optic (EO) layer. Such multilayered structural integration with remarkable ferroelectric polarization, high transparency (>90%), low sheet resistance (~302 Ω □-1), and excellent mechanic flexibility shows the potential of a flexible modulation application over a broad range of wavelengths. Moreover, the derived device also exhibits strong field-induced EO modulation even under bending and one large Pockels coefficient (~54.3 pm V-1) is obtained. Finally, the graphene and ferroelectric hybrid demonstrates a fast switching time (~2 μs) and works well below low sheet resistance level over a long time. This work gives insights into the potential of graphene and ferroelectric hybrid structures, enabling future exploration on next-generation high-performance, flexible transparent electronics and photonics.Here we report a wafer-scale graphene/P(VDF-TrFE)/graphene multilayer for light-weight, flexible and fast-switched broadband modulation applications. The P(VDF-TrFE) film not only significantly reduces the sheet resistance of graphene throughout heavy doping of ~0.8 × 1013 cm-2 by nonvolatile ferroelectric dipoles, but also acts as an efficient electro-optic (EO) layer. Such multilayered structural integration with remarkable ferroelectric polarization, high transparency (>90%), low sheet resistance (~302 Ω □-1), and excellent mechanic flexibility shows the potential of a flexible modulation application over a broad range of wavelengths. Moreover, the derived device also exhibits strong field-induced EO modulation even under bending and one large Pockels coefficient (~54.3 pm V-1) is obtained. Finally, the graphene and ferroelectric hybrid demonstrates a fast switching time (~2 μs) and works well below low sheet resistance level over a long time. This work gives insights into the potential of graphene and ferroelectric hybrid structures, enabling future exploration on next-generation high-performance, flexible transparent electronics and photonics. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr03020j

  8. Efficient fabrication of wafer scale thin film of individualized single-walled carbon nanotubes by dual-nozzle spin casting

    NASA Astrophysics Data System (ADS)

    Kim, Yong Shin; Kwon, Soongeun; Shin, Dong Hun; Shim, Hyung Cheoul; Woo, Ju Yeon; Lim, Donghyun; Kwak, Yoon Keun; Kim, Soohyun; Han, Chang-Soo

    2010-06-01

    In this paper, a dual-nozzle spin casting method was proposed to form a thin film of individualized single-walled carbon nanotubes (SWNTs) at the wafer scale. Each nozzle simultaneously ejected the SWNT solution and methanol, respectively. During the ejection process, two solutions were mixed at the contacting end of the nozzles and then dropped onto the substrate. Functionalization of the wafer substrate with the amine group improved the uniformity of the SWNT thin film as well as the adhesion between the individualized SWNTs and the substrate. The best condition of the spin casting involved the substrate functionalization using 3-aminopropyltriethosilane aqueous solution with a concentration of ˜10 mM and a deposition velocity of ˜5000 rpm. The root-mean-square roughness of the fabricated SWNT layer over the wafer substrate was found to be 1.4-1.8 nm, which indicated that the resultant thin film was one or two layers of SWNTs. The wafer scale SWNT thin film formed by dual-nozzle spin casting can be further used for the mass production and high integration of the SWNT nanoelectronic devices.

  9. Wafer-scale highly-transparent and superhydrophilic sapphires for high-performance optics.

    PubMed

    Leem, Jung Woo; Yu, Jae Su

    2012-11-19

    We reported the wafer-scale highly-transparent and superhydrophilic sapphires with antireflective subwavelength structures (SWSs) which were fabricated by dry etching using thermally dewetted gold (Au) nanomasks. Their optical transmittance properties were experimentally and theoretically investigated. The density, size, and period of the thermally dewetted Au nanopatterns can be controlled by the Au film thickness. For the sapphire with both-side SWSs at 5 nm of Au film, the average total transmittance (T(avg)) of ~96.5% at 350-800 nm was obtained, indicating a higher value than those of the flat sapphire (T(avg)~85.6%) and the sapphire with one-side SWSs (T(avg)~91%), and the less angle-dependent transmittance property was observed. The calculated transmittance results also showed a similar tendency to the measured data. The SWSs enhanced significantly the surface hydrophilicity of sapphires, exhibiting a water contact angle (?(c)) of < 5 for Au film of 5 nm compared to ?(c)~37 of the flat sapphire. PMID:23187471

  10. Performance of 4-in. wafer-scale thermoset working stamps in hot-embossing lithography

    NASA Astrophysics Data System (ADS)

    Roos, Nils; Schulz, Hubert; Fink, Marion; Pfeiffer, Karl; Osenberg, Frank; Scheer, Hella-Christin

    2002-07-01

    In order to reduce the cost for stamps featuring nanometer structures in a hot embossing lithography (HEL) process the production and performance of working stamps made of thermoset polymer are of interest. Fabrication of stamps made of thermosetting material no silicon substrates by hot embossing with 2 X 2 cm2 templates and their replication by HEL has already been demonstrate. In this paper the enlargement of this principle to 4 inch wafer- scale is presented. Two procedures to obtain working stamps by hot embossing are compared, one solely based on hot embossing, the other enhanced by additional UV-exposure. The produced working stamps are tested for performance under standard embossing conditions are the topic of anti-sticking layers, a key issue in all large area imprint applications is addressed. Two methods of tailoring adhesion properties of thermosets are proposed, plasma-depositing a fluorinated film and coating with a self-assembled monolayer of fluoroalkyltrichlorosilane, only the former of which was employed successfully. The achieved fidelity of pattern replication with working stamps and imprints thereof is assessed by cross-sectional SEM investigation, showing only the UV-enhanced method to be well suited for the task of obtaining low-cost replications of silicon stamps.

  11. A wafer-scale graphene and ferroelectric multilayer for flexible and fast-switched modulation applications.

    PubMed

    Zhu, Minmin; Wu, Jing; Du, Zehui; Tay, Roland Yingjie; Li, Hongling; zyilmaz, Barbarous; Teo, Edwin Hang Tong

    2015-09-21

    Here we report a wafer-scale graphene/P(VDF-TrFE)/graphene multilayer for light-weight, flexible and fast-switched broadband modulation applications. The P(VDF-TrFE) film not only significantly reduces the sheet resistance of graphene throughout heavy doping of ?0.8 10(13) cm(-2) by nonvolatile ferroelectric dipoles, but also acts as an efficient electro-optic (EO) layer. Such multilayered structural integration with remarkable ferroelectric polarization, high transparency (>90%), low sheet resistance (?302 ??(-1)), and excellent mechanic flexibility shows the potential of a flexible modulation application over a broad range of wavelengths. Moreover, the derived device also exhibits strong field-induced EO modulation even under bending and one large Pockels coefficient (?54.3 pm V(-1)) is obtained. Finally, the graphene and ferroelectric hybrid demonstrates a fast switching time (?2 ?s) and works well below low sheet resistance level over a long time. This work gives insights into the potential of graphene and ferroelectric hybrid structures, enabling future exploration on next-generation high-performance, flexible transparent electronics and photonics. PMID:26284783

  12. Wafer-scale design of lightweight and transparent electronics that wraps around hairs

    NASA Astrophysics Data System (ADS)

    Salvatore, Giovanni A.; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

    2014-01-01

    Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

  13. Wafer-scale self-organized InP nanopillars with controlled orientation for photovoltaic devices

    NASA Astrophysics Data System (ADS)

    Sanatinia, Reza; Berrier, Audrey; Dhaka, Veer; Perros, Alexander P.; Huhtio, Teppo; Lipsanen, Harri; Anand, Srinivasan

    2015-10-01

    A unique wafer-scale self-organization process for generation of InP nanopillars is demonstrated, which is based on maskless ion-beam etching (IBE) of InP developed to obtain the nanopillars, where the height, shape, and orientation of the nanopillars can be varied by controlling the processing parameters. The fabricated InP nanopillars exhibit broadband suppression of the reflectance, black InP, a property useful for solar cells. The realization of a conformal p-n junction for carrier collection, in the fabricated solar cells, is achieved by a metalorganic vapor phase epitaxy (MOVPE) overgrowth step on the fabricated pillars. The conformal overgrowth retains the broadband anti-reflection property of the InP nanopillars, indicating the feasibility of this technology for solar cells. Surface passivation of the formed InP nanopillars using sulfur-oleylamine solution resulted in improved solar-cell characteristics. An open-circuit voltage of 0.71 V and an increase of 0.13 V compared to the unpassivated device were achieved.

  14. 14C autoradiography with a novel wafer scale CMOS Active Pixel Sensor

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Larner, J.; Allinson, N. M.; Wells, K.

    2013-01-01

    14C autoradiography is a well established technique for structural and metabolic analysis of cells and tissues. The most common detection medium for this application is film emulsion, which offers unbeatable spatial resolution due to its fine granularity but at the same time has some limiting drawbacks such as poor linearity and rapid saturation. In recent years several digital detectors have been developed, following the technological transition from analog to digital-based detection systems in the medical and biological field. Even so such digital systems have been greatly limited by the size of their active area (a few square centimeters), which have made them unsuitable for routine use in many biological applications where sample areas are typically ~ 10-100 cm2. The Multidimensional Integrated Intelligent Imaging (MI3-Plus) consortium has recently developed a new large area CMOS Active Pixel Sensor (12.8 cm 13.1 cm). This detector, based on the use of two different pixel resolutions, is capable of providing simultaneously low noise and high dynamic range on a wafer scale. In this paper we will demonstrate the suitability of this detector for routine beta autoradiography in a comparative approach with widely used film emulsion.

  15. Wafer-scale self-organized InP nanopillars with controlled orientation for photovoltaic devices.

    PubMed

    Sanatinia, Reza; Berrier, Audrey; Dhaka, Veer; Perros, Alexander P; Huhtio, Teppo; Lipsanen, Harri; Anand, Srinivasan

    2015-10-16

    A unique wafer-scale self-organization process for generation of InP nanopillars is demonstrated, which is based on maskless ion-beam etching (IBE) of InP developed to obtain the nanopillars, where the height, shape, and orientation of the nanopillars can be varied by controlling the processing parameters. The fabricated InP nanopillars exhibit broadband suppression of the reflectance, 'black InP,' a property useful for solar cells. The realization of a conformal p-n junction for carrier collection, in the fabricated solar cells, is achieved by a metalorganic vapor phase epitaxy (MOVPE) overgrowth step on the fabricated pillars. The conformal overgrowth retains the broadband anti-reflection property of the InP nanopillars, indicating the feasibility of this technology for solar cells. Surface passivation of the formed InP nanopillars using sulfur-oleylamine solution resulted in improved solar-cell characteristics. An open-circuit voltage of 0.71 V and an increase of 0.13 V compared to the unpassivated device were achieved. PMID:26403979

  16. Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy

    PubMed Central

    Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

    2013-01-01

    The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (metasurfaces) can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

  17. Wafer-scale synthesis of single-crystal zigzag silicon nanowire arrays with controlled turning angles.

    PubMed

    Chen, Huan; Wang, Hui; Zhang, Xiao-Hong; Lee, Chun-Sing; Lee, Shuit-Tong

    2010-03-10

    Silicon nanowires (SiNWs) having curved structures may have unique advantages in device fabrication. However, no methods are available to prepare curved SiNWs controllably. In this work, we report the preparation of three types of single-crystal SiNWs with various turning angles via metal-assisted chemical etching using (111)-oriented silicon wafers near room temperature. The zigzag SiNWs are single crystals and can be p- or n-doped using corresponding Si wafer as substrate. The controlled growth direction is attributed to the preferred movement of Ag nanoparticles along 001 and other directions in Si wafer. Our results demonstrate that metal-assisted chemical etching may be a viable approach to fabricate SiNWs with desired turning angles by utilizing the various crystalline directions in a Si wafer. PMID:20104856

  18. A wafer-scale backplane-assisted resonating nanoantenna array SERS device created by tunable thermal dewetting nanofabrication

    NASA Astrophysics Data System (ADS)

    Chang, Te-Wei; Ranjan Gartia, Manas; Seo, Sujin; Hsiao, Austin; Logan Liu, Gang

    2014-04-01

    A tunable lithography-less nanofabrication process using a metal thin-film thermal dewetting technique has been developed to fabricate wafer-scale and uniform plasmonic substrates at low cost for optimal performance in surface enhanced Raman scattering (SERS) applications. The relationship between the tunable parameters of this process and the corresponding optical and plasmonic characteristic is investigated both experimentally and theoretically to understand the deterministic design of an optimal SERS device with a three-dimensional plasmonic nanoantenna structure. The enhancement of SERS using various nanoplasmonic particle sizes, structure lengths, lateral hot spot spacings and resonating effects are examined and demonstrated. We achieve a uniform optimal enhancement factor of 1.38 × 108 on a 4 in wafer-scale SERS substrate with a backplane-assisted resonating nanoantenna array design. Sensitive environmental nitrate sensing, vitamin detection and oligonucleotide identification are demonstrated on the high-performance SERS device.

  19. Bottom-Up Nano-heteroepitaxy of Wafer-Scale Semipolar GaN on (001) Si.

    PubMed

    Hus, Jui-Wei; Chen, Chien-Chia; Lee, Ming-Jui; Liu, Hsueh-Hsing; Chyi, Jen-Inn; Huang, Michael R S; Liu, Chuan-Pu; Wei, Tzu-Chiao; He, Jr-Hau; Lai, Kun-Yu

    2015-09-01

    Semipolar {1011} InGaN quantum wells are grown on (001) Si substrates with an Al-free buffer and wafer-scale uniformity. The novel structure is achieved by a bottom-up nano-heteroepitaxy employing self-organized ZnO nanorods as the strain-relieving layer. This ZnO nanostructure unlocks the problems encountered by the conventional AlN-based buffer, which grows slowly and contaminates the growth chamber. PMID:26178685

  20. Field-effect transistors based on wafer-scale, highly uniform few-layer p-type WSe2.

    PubMed

    Campbell, Philip M; Tarasov, Alexey; Joiner, Corey A; Tsai, Meng-Yen; Pavlidis, Georges; Graham, Samuel; Ready, W Jud; Vogel, Eric M

    2016-01-21

    The synthesis of few-layer tungsten diselenide (WSe2) via chemical vapor deposition typically results in highly non-uniform thickness due to nucleation initiated growth of triangular domains. In this work, few-layer p-type WSe2 with wafer-scale thickness and electrical uniformity is synthesized through direct selenization of thin films of e-beam evaporated W on SiO2 substrates. Raman maps over a large area of the substrate show small variations in the main peak position, indicating excellent thickness uniformity across several square centimeters. Additionally, field-effect transistors fabricated from the wafer-scale WSe2 films demonstrate uniform electrical performance across the substrate. The intrinsic field-effect mobility of the films at a carrier concentration of 3 10(12) cm(-2) is 10 cm(2) V(-1) s(-1). The unprecedented uniformity of the WSe2 on wafer-scale substrates provides a substantial step towards producing manufacturable materials that are compatible with conventional semiconductor fabrication processes. PMID:26743173

  1. Field-effect transistors based on wafer-scale, highly uniform few-layer p-type WSe2

    NASA Astrophysics Data System (ADS)

    Campbell, Philip M.; Tarasov, Alexey; Joiner, Corey A.; Tsai, Meng-Yen; Pavlidis, Georges; Graham, Samuel; Ready, W. Jud; Vogel, Eric M.

    2016-01-01

    The synthesis of few-layer tungsten diselenide (WSe2) via chemical vapor deposition typically results in highly non-uniform thickness due to nucleation initiated growth of triangular domains. In this work, few-layer p-type WSe2 with wafer-scale thickness and electrical uniformity is synthesized through direct selenization of thin films of e-beam evaporated W on SiO2 substrates. Raman maps over a large area of the substrate show small variations in the main peak position, indicating excellent thickness uniformity across several square centimeters. Additionally, field-effect transistors fabricated from the wafer-scale WSe2 films demonstrate uniform electrical performance across the substrate. The intrinsic field-effect mobility of the films at a carrier concentration of 3 × 1012 cm-2 is 10 cm2 V-1 s-1. The unprecedented uniformity of the WSe2 on wafer-scale substrates provides a substantial step towards producing manufacturable materials that are compatible with conventional semiconductor fabrication processes.

  2. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  3. Wafer-scale arrayed p-n junctions based on few-layer epitaxial GaTe

    NASA Astrophysics Data System (ADS)

    Yuan, Xiang; Tang, Lei; Hu, Weida; Xiu, Faxian

    2015-03-01

    Two dimensional (2D) materials have showed appealing applications in electronics and optoelectronics. Gapless graphene presents ultra-broadband and fast photoresponse while the 2D semiconducting MoS2 and GaTe exhibit highly sensitive and tunable responsivity to the visible light. However, the device yield and its repeatability call for a further improvement of 2D materials to render large-scale uniformity. Here we report a layer-by-layer growth of the wafer-scale GaTe by molecular beam epitaxy. To develop the arrayed p-n junctions, the few-layer GaTe was grew on three-inch Si wafers. The resultant diodes reveal good rectifying characteristics and photoresponse with maximum photodetection responsivity of 2.74 A/W and photovoltaic external quantum efficiency up to 62%. The photocurrent reaches saturation very fast within 22 ?s and shows no sign of device degradation after 1.37 million cycles of operation. Most strikingly, such high performance has been achieved across the entire wafer, making the volume production of devices accessible. Finally, several photo-images was acquired by using these photodiodes with a reasonable contrast and resolution, demonstrating for the first time the potential for these 2D technology coming into the real life.

  4. Study of wafer thickness scaling in n-type rear-emitter solar cells with different bulk lifetimes

    NASA Astrophysics Data System (ADS)

    Chen, Chen; Zhang, Wei; Xing, Zhao; Sun, Yun; Jia, Rui; Jin, Zhi; Liu, Xinyu; Redwing, Joan M.

    2014-08-01

    In case of the n-type rear-emitter solar cell (n-RESC), wafer thickness scaling down has been studied and simulated under different bulk lifetimes (?bulk). The effect of minority-carrier lifetime of bulk ?bulk on photovoltaic properties has been studied by using a symmetrical front-and-rear electrode structure, followed by a discussion of the physical mechanism. Simulation results show that by decreasing the wafer thickness, high energy-conversion efficiency can be achieved, even though a low bulk lifetime substrate is used, suggesting a cost-effective way to manufacture the high efficiency n-RESC. In addition, emitter saturation current density (Joe) of the n-RESC has also been extracted.

  5. Full-wafer technology - A new approach to large-scale laser fabrication and integration

    NASA Astrophysics Data System (ADS)

    Vettiger, Peter; Bona, Gian-Luca; Buchmann, Peter; Daetwyler, Kurt; Dietrich, Hans-Peter; Moser, Andreas; Seitz, Hugo K.; Benedict, Melvin K.; Cahoon, Edward C.; Voegeli, Otto

    1991-06-01

    A concept for full-wafer processing (FWP) and full-wafer testing (FWT) for semiconductor laser fabrication in the AlGaAs-GaAs material system is presented. The approach is based on chemically assisted ion beam etching for the laser-mirror formation. Record values for mirror scattering, optimum mirror reflectivity, and equivalence to cleaved mirrors in terms of laser threshold and efficiency have been achieved. Promising results for uniformity and reproducibility for major laser diode characteristics on processed 2-inch wafers have been found. The FWP technology has been extensively used for designing test sites to determine various materials, process, and laser parameters, such as sheet resistance, ridge dimensions, lithographic alignment errors, mirror surface leakage, etc. FWP improves process yield and throughput by reducing bar and chip handling to an absolute minimum. In addition to FWP, an FWT concept has been developed which allows a complete on-wafer characterization of laser diodes, including their beam characteristics, without any cleaving.

  6. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    NASA Astrophysics Data System (ADS)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Bjrn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Gran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 ?m is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 ?m 25 ?m that are arranged on read-out-wafers in arrays with 320 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  7. Fabrication of a wafer-scale uniform array of single-crystal organic nanowire complementary inverters by nanotransfer printing

    NASA Astrophysics Data System (ADS)

    Park, Kyung Sun; Baek, Jangmi; Koo Lee, Yong-Eun; Sung, Myung Mo

    2015-02-01

    We report the fabrication and electrical characterization of a wafer-scale array of organic complementary inverters using single-crystal 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-PEN) and fullerene (C60) nanowires as p- and n-channels, respectively. Two arrays of single-crystal organic nanowires were generated consecutively on desired locations of a common substrate with a desired mutual alignment by a direct printing method (liquid-bridge-mediated nanotransfer molding). Another direct printing of silver micron scale structures, as source and drain electrodes, on the substrate with the two printed nanowire arrays produced an array of complementary inverters with a bottom gate, top contact configuration. Field-effect mobilities of single-crystal TIPS-PEN and C60 nanowire field-effect transistors (FETs) in the arrays were uniform with 1.01 0.14 and 0.10 0.01 cm2V-1 s-1, respectively. A wafer-scale array of complementary inverters produced all by the direct printing method showed good performance with an average gain of 25 and with low variations among the inverters.

  8. Stationary Optical Concentrator Designs and Wafer Scale Monolithic Integration of Semiconductor Devices for Next Generation Photovoltaic Panels

    NASA Astrophysics Data System (ADS)

    Kim, Jung Min

    A major barrier in utilizing solar energy for large scale deployment is the cost of the photovoltaic (PV) systems. Several approaches have been used for the cost reduction such as by modifying PV system designs in addition to enhancing the efficiency of solar cells. Due to the high cost of materials, minimizing the use of solar cells such as in concentrator type systems is highly attractive for reducing the cost of the PV modules by focusing the incident light onto the PV cell. However concentrator PV systems (CPV) require constant tracking of the sun and hence are complex in design and expensive to operate, except in limited situations such as large scale PV power plants. It is desirable to design new concentrator type systems that do not require continuous tracking of the sun. These systems could ultimately reduce the PV system cost to a minimum while maximizing the power conversion efficiency. In this thesis we propose a simple design for a stationary concentrator photovoltaic (SCPV) system that could significantly reduce the cost of generating electricity using PV devices. Using optical ray tracing simulations, we have been able to design SCPV systems that could reduce the PV module cost by 2--10 times without compromising on the power conversion efficiency of the system. Another alternative approach for sustainable high efficiency PV system design is to develop low cost PV cells for terrestrial applications. To meet the demands of low cost and large scale production, larger and thinner (or flexible) substrates are required. We demonstrated the feasibility of fabricating monolithic interconnected PV devices at the wafer scale (2 inch wafers). In this study, GaSb PV cells grown on semi-insulating GaAs were used as the model material. Crucial device fabrication steps such as a selective etching process have been developed that is necessary for isolating individual devices on the wafer and interconnecting them with sub-micron scale accuracy. Selective etching of GaSb and GaAs has been developed for isolation of GaSb devices on semi-insulating GaAs substrates. Smooth side wall morphology and desirable depth profile of the etched structures have been accomplished using optimized etching conditions presented in this thesis. Device fabrication of series interconnected GaSb PV cells on a GaAs substrate with single-sided metal contacts has been successfully demonstrated.

  9. Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

    SciTech Connect

    Sangwan, Vinod K.; Jariwala, Deep; McMorrow, Julian J.; He, Jianting; Lauhon, Lincoln J.; Everaerts, Ken; Grayson, Matthew; Marks, Tobin J. E-mail: m-hersam@northwestern.edu; Hersam, Mark C. E-mail: m-hersam@northwestern.edu

    2014-02-24

    Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2?V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure?wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

  10. Highly Transparent Wafer-Scale Synthesis of Crystalline WS2 Nanoparticle Thin Film for Photodetector and Humidity-Sensing Applications.

    PubMed

    Pawbake, Amit S; Waykar, Ravindra G; Late, Dattatray J; Jadkar, Sandesh R

    2016-02-10

    In the present investigation, we report a one-step synthesis method of wafer-scale highly crystalline tungsten disulfide (WS2) nanoparticle thin film by using a modified hot wire chemical vapor deposition (HW-CVD) technique. The average size of WS2 nanoparticle is found to be 25-40 nm over an entire 4 in. wafer of quartz substrate. The low-angle XRD data of WS2 nanoparticle shows the highly crystalline nature of sample along with orientation (002) direction. Furthermore, Raman spectroscopy shows two prominent phonon vibration modes of E(1)2g and A1g at ∼356 and ∼420 cm(-1), respectively, indicating high purity of material. The TEM analysis shows good crystalline quality of sample. The synthesized WS2 nanoparticle thin film based device shows good response to humidity and good photosensitivity along with good long-term stability of the device. It was found that the resistance of the films decreases with increasing relative humidity (RH). The maximum humidity sensitivity of 469% along with response time of ∼12 s and recovery time of ∼13 s were observed for the WS2 thin film humidity sensor device. In the case of photodetection, the response time of ∼51 s and recovery time of ∼88 s were observed with sensitivity ∼137% under white light illumination. Our results open up several avenues to grow other transition metal dichalcogenide nanoparticle thin film for large-area nanoelectronics as well as industrial applications. PMID:26771049

  11. Wafer-scale, conformal and direct growth of MoS2 thin films by atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Jang, Yujin; Yeo, Seungmin; Lee, Han-Bo-Ram; Kim, Hyungjun; Kim, Soo-Hyun

    2016-03-01

    Molybdenum disulfide (MoS2) thin films were grown directly on SiO2 covered wafers by atomic layer deposition (ALD) at the deposition temperatures ranging from 175 to 225 °C using molybdenum hexacarbonyl [Mo(CO)6] and H2S plasma as the precursor and reactant, respectively. Self-limited film growth on the thermally-grown SiO2 substrate was observed with both the precursor and reactant pulsing time. The growth rate was ∼0.05 nm/cycle and a short incubation cycle of around 13 was observed at a deposition temperature of 175 °C. The MoS2 films formed nanocrystalline microstructure with a hexagonal crystal system (2H-MoS2), which was confirmed by X-ray diffraction and transmission electron microscopy. Single crystal MoS2 nanosheets, ∼20 nm in size, were fabricated by controlling the number of ALD cycles. The ALD-MoS2 thin films exhibited good stoichiometry with negligible C impurities, approximately 0.1 at.% from Rutherford backscattering spectrometry (RBS). X-ray photoelectron spectroscopy confirmed the formation of chemical bonding from MoS2. The step coverage of ALD-MoS2 was approximately 75% at a 100 nm sized trench. Overall, the ALD-MoS2 process made uniform deposition possible on the wafer-scale (4 in. in diameter).

  12. Wafer-scale single-domain-like graphene by defect-selective atomic layer deposition of hexagonal ZnO

    NASA Astrophysics Data System (ADS)

    Park, Kyung Sun; Kim, Sejoon; Kim, Hongbum; Kwon, Deokhyeon; Koo Lee, Yong-Eun; Min, Sung-Wook; Im, Seongil; Choi, Hyoung Joon; Lim, Seulky; Shin, Hyunjung; Koo, Sang Man; Sung, Myung Mo

    2015-10-01

    Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity.Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr05392g

  13. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

    PubMed Central

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-01-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

  14. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

    NASA Astrophysics Data System (ADS)

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-02-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

  15. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors.

    PubMed

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-01-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

  16. Modeling electrodeposition for LIGA microdevice fabrication

    SciTech Connect

    Griffiths, S.K.; Nilson, R.H.; Bradshaw, R.W.

    1998-02-01

    To better understand and to help optimize the electroforming portion of the LIGA process, we have developed one and two-dimensional numerical models describing electrode-position of metal into high aspect-ratio molds. The one-dimensional model addresses dissociation, diffusion, electromigration, and deposition of multiple ion species. The two-dimensional model is limited to a single species, but includes transport induced by forced flow of electrolyte outside the mold and by buoyancy associated with metal ion depletion within the mold. To guide model development and to validate these models, we have also conducted a series of laboratory experiments using a sulfamate bath to deposit nickel in cylindrical molds having aspect ratios up to twenty-five. The experimental results indicate that current densities well in excess of the diffusion-limited currents may still yield metal deposits of acceptable morphology. However, the numerical models demonstrate that such large ion fluxes cannot be sustained by convection within the mold resulting from flow across the mold top. Instead, calculations suggest that the observed enhancement of transport probably results from natural convection within the molds, and that buoyancy-driven flows may be critical to metal ion transport even in micron-scale features having very large aspect ratios. Taking advantage of this enhanced ion transport may allow order-of-magnitude reductions in electroforming times for LIGA microdevice fabrication. 42 refs., 14 figs., 1 tab.

  17. Wafer-scale single-domain-like graphene by defect-selective atomic layer deposition of hexagonal ZnO.

    PubMed

    Park, Kyung Sun; Kim, Sejoon; Kim, Hongbum; Kwon, Deokhyeon; Koo Lee, Yong-Eun; Min, Sung-Wook; Im, Seongil; Choi, Hyoung Joon; Lim, Seulky; Shin, Hyunjung; Koo, Sang Man; Sung, Myung Mo

    2015-10-22

    Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity. PMID:26452020

  18. Nanogap-enhanced infrared spectroscopy with template-stripped wafer-scale arrays of buried plasmonic cavities.

    PubMed

    Chen, Xiaoshu; Cirac, Cristian; Smith, David R; Oh, Sang-Hyun

    2015-01-14

    We have combined atomic layer lithography and template stripping to produce a new class of substrates for surface-enhanced infrared absorption (SEIRA) spectroscopy. Our structure consists of a buried and U-shaped metal-insulator-metal waveguide whose folded vertical arms efficiently couple normally incident light. The insulator is formed by atomic layer deposition (ALD) of Al2O3 and precisely defines the gap size. The buried nanocavities are protected from contamination by a silicon template until ready for use and exposed by template stripping on demand. The exposed nanocavity generates strong infrared resonances, tightly confines infrared radiation into a gap that is as small as 3 nm (?/3300), and creates a dense array of millimeter-long hotspots. After partial removal of the insulators, the gaps are backfilled with benzenethiol molecules, generating distinct Fano resonances due to strong coupling with gap plasmons, and a SEIRA enhancement factor of 10(5) is observed for a 3 nm gap. Because of the wafer-scale manufacturability, single-digit-nanometer control of the gap size via ALD, and long-term storage enabled by template stripping, our buried plasmonic nanocavity substrates will benefit broad applications in sensing and spectroscopy. PMID:25423481

  19. Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

    PubMed

    Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sbastien; Berbezier, Isabelle; Bonod, Nicolas

    2014-11-25

    Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers. PMID:25365786

  20. Wafer-scale synthesis of thickness-controllable MoS2 films via solution-processing using a dimethylformamide/n-butylamine/2-aminoethanol solvent system

    NASA Astrophysics Data System (ADS)

    Yang, Jaehyun; Gu, Yeahyun; Lee, Eunha; Lee, Hyangsook; Park, Sang Han; Cho, Mann-Ho; Kim, Yong Ho; Kim, Yong-Hoon; Kim, Hyoungsub

    2015-05-01

    The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates.The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates. Electronic supplementary information (ESI) available: Optical microscopy image of the spin-coated film, thermogravimetric data of the spin-coating solution, Raman spectra after first- and second-annealing, and AFM images of selected MoS2 films. See DOI: 10.1039/c5nr01486g

  1. Slip, Crystal Orientation, and Damage Evolution During Thermal Cycling in High-Strain Wafer-Level Chip-Scale Packages

    NASA Astrophysics Data System (ADS)

    Zhou, Bite; Zhou, Quan; Bieler, Thomas R.; Lee, Tae-kyu

    2015-03-01

    Wafer-level chip-scale package samples with pre-cross-sectioned edge rows were thermally cycled to study microstructure evolution and damage development. Electron backscattered diffraction (EBSD) and high-energy x-ray diffraction were used to obtain Sn grain orientations and the average coefficient of thermal expansion normal to the board in every joint of the package for samples in the as-fabricated and thermally cycled conditions. The results indicated a near-random distribution of joint orientation. Optical, scanning electron microscopy, and EBSD methods were used to characterize microstructure changes in pre-cross-sectioned samples due to thermal cycling. Slip trace analysis and Orientation Imaging Microscopy (OIM) show that slip systems with high Schmid factors (estimated global shear stress based on the package neutral point) are responsible for the observed microstructure evolution during thermal cycling, which provides information about slip systems that are more easily activated. Two joints were analyzed in detail to evaluate slip activity at different stages of their thermal history. The first case showed that a solidification twin grain boundary misorientation deviated from the twin relationship due to slip activity during thermal cycling, which can influence damage development and the path of crack propagation. The second case showed a new grain orientation developing due to gradual lattice rotation about the Sn [110] axis by a continuous recrystallization mechanism. This rotation was correlated with the operation of slip system . Small tin whiskers emerged from the initially polished chip interface and grew with increasing thermal cycles until a crack developed in the solder that relieved the stress. As the local stresses are not known experimentally, this analysis provides observations that can be compared with a crystal plasticity model simulation.

  2. MUSE - a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer-scale integration. Technical report

    SciTech Connect

    Rader, C.M.; Allen, D.L.; gLASCO , D.B.; Woodward, C.E.

    1990-05-18

    This report describes an architecture for a highly parallel system of computational processors specialized for real-time adaptive antenna nulling computations with many degrees of freedom, which we call MUSE (Matrix Update Systolic Experiment), and a specific realization of MUSE for 64 degrees of freedom. Each processor uses the CORDIC algorithm and has been designed as a single integrated circuit. Ninety-six such processors working together can update the 64-element nulling weights based on 300 new observations in only 6.7 milliseconds. This is equivalent to 2.88 Giga-ops for a conventional processor. The computations are accurate enough to support 50 decibel of signal-to-noise improvement in a sidelobe canceller. The connectivity between processors is quite simple and permits MUSE to be realized on a single large wafer, using restructurable VLSI (Very Large Scale Integration). The complete design of such a wafer is described.

  3. Miniature Inchworm Actuators Fabricated by Use of LIGA

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok

    2003-01-01

    Miniature inchworm actuators that would have relatively simple designs have been proposed for applications in which there are requirements for displacements of the order of microns or tens of microns and for the ability to hold their positions when electric power is not applied. The proposed actuators would be members of the class of microelectromechanical systems (MEMS), but would be designed and fabricated following an approach that is somewhat unusual for MEMS. Like other MEMS actuators, the proposed inchworm actuators could utilize thermoplastic, bimetallic, shape-memory-alloy, or piezoelectric actuation principles. The figure depicts a piezoelectric inchworm actuator according to the proposal. As in other inchworm actuators, linear motion of an extensible member would be achieved by lengthening and shortening the extensible member in synchronism with alternately clamping and releasing one and then the other end of the member. In this case, the moving member would be the middle one; the member would be piezoelectric and would be shortened by applying a voltage to it. The two outer members would also be piezoelectric; the release of the clamps on the upper or lower end would be achieved by applying a voltage to the electrodes on the upper or lower ends, respectively, of these members. Usually, MEMS actuators cannot be fabricated directly on the side walls of silicon wafers, yet the geometry of this actuator necessitates such fabrication. The solution, according to the proposal, would be to use the microfabrication technique known by the German acronym LIGA - "lithographie, galvanoformung, abformung," which means lithography, electroforming, molding. LIGA involves x-ray lithography of a polymer film followed by selective removal of material to form a three-dimensional pattern from which a mold is made. Among the advantages of LIGA for this purpose are that it is applicable to a broad range of materials, can be used to implement a variety of designs, including those of structures >1 mm high, affords submicron precision, and is amenable to mass production at relatively low unit cost. Fabrication of the proposed actuators would involve some technological risks - in particular, in the integration of electrode connection lines and placement of actuator elements. It will also be necessary to perform an intensive study of the feasibility of growing piezoelectric crystals onto LIGA molds.

  4. Minimum silicon wafer thickness for ID wafering

    NASA Technical Reports Server (NTRS)

    Chen, C. P.

    1982-01-01

    An analytical model, based on fracture mechanics analysis, is proposed for estimating the minimum wafer thickness as a function of the diameter requirement for solar cells. The conditions under which the model can be applied are discussed with reference to the critical flaw size, the applied force, and the width of the side support. It is shown that the equivalent cantilever force applied during ID slicing can be estimated from the wafering mechanical yield data. The width of the wafer side support was found to be a significant factor in controlling the minimum allowable wafer thickness during slicing. Wafer side support width requirements were found to increase with decreasing wafer thickness.

  5. Imaging ATUM ultrathin section libraries with WaferMapper: a multi-scale approach to EM reconstruction of neural circuits

    PubMed Central

    Hayworth, Kenneth J.; Morgan, Josh L.; Schalek, Richard; Berger, Daniel R.; Hildebrand, David G. C.; Lichtman, Jeff W.

    2014-01-01

    The automated tape-collecting ultramicrotome (ATUM) makes it possible to collect large numbers of ultrathin sections quickly—the equivalent of a petabyte of high resolution images each day. However, even high throughput image acquisition strategies generate images far more slowly (at present ~1 terabyte per day). We therefore developed WaferMapper, a software package that takes a multi-resolution approach to mapping and imaging select regions within a library of ultrathin sections. This automated method selects and directs imaging of corresponding regions within each section of an ultrathin section library (UTSL) that may contain many thousands of sections. Using WaferMapper, it is possible to map thousands of tissue sections at low resolution and target multiple points of interest for high resolution imaging based on anatomical landmarks. The program can also be used to expand previously imaged regions, acquire data under different imaging conditions, or re-image after additional tissue treatments. PMID:25018701

  6. Optimization and scale-down of wafer-based resist strip and rinse processes for photomask production

    NASA Astrophysics Data System (ADS)

    Aggus, Brant L.; Weaver, Gene

    2002-03-01

    Retrofitting of wafer processing equipment is a common scenario in the photomask industry, as most available tools are built to accommodate the high throughput and substrate size of wafers. The acid process tanks in use at most mask shops are built to suit a single rack of 25 8 inch wafers, each coated with roughly two microns of photoresist. Conversely, a typical photomask shop sends one to two masks at a time through the resist strip line, each coated with 4500 angstroms of resist. The amount of unused volume of active chemical within an 8 inch X 8.5 inch X 10 inch acid tank when it is dumped is enough to warrant a hardware change. Experimentation has shown that it is possible to decrease Piranha usage by 43 percent by optimizing tank size for photomasks. The same logic applies to quick dump rinsers (QDRs). Additionally, water is wasted with 'spray down' processes, whereby masks are sprayed via perforated bars or nozzles. Because a < 0.5 μm viscous sublayer can not be practically achieved through spraying the mask, better cleaning performance is obtained with a bottom-filled weiring process. This is demonstrated through experimental results and theoretical mass transfer models.

  7. Laparoscopic Splenectomy Using LigaSure

    PubMed Central

    Kindy, Nayil Al; Chopra, Pradeep J.

    2010-01-01

    Background: Laparoscopic splenectomy (LS) has become the standard approach for most splenectomy cases. Bleeding is the main complication and cause for conversion. We present our experience with the LigaSure and discuss its advantage as a vessel sealing system in achieving safe vascular control. Method: Over a 3-year period, we performed 12 consecutive LS using LigaSure at a single center. A literature review of all the patients who had undergone laparoscopic splenectomy with of the LigaSure to achieve vascular control at the hilum was carried out, assessing its advantages and outcome. Results: Twelve LS were performed. Eleven of these patients had ITP, and one patient had sickle cell disease. The mean blood loss was 70mL (range, 50 to 460), and operating time was 126 minutes (range, 110 to 240). Two postoperative complications occurred: portal vein thrombosis in one case and subphrenic collection in the other. The literature review revealed 8 studies with 231 cases in which the LigaSure was used to perform laparoscopic splenectomy. A significant reduction in operating time (average 102 minutes) and intraabdominal blood loss (66mL) was observed with the LigaSure compared with endostaplers. Conclusion: The use of LigaSure and the semilateral position results in a gain of time and safety in addition to low intraoperative bleeding, need for transfusion, minimal complications and a low conversion rate. PMID:21605520

  8. Wafer-scale surface roughening for enhanced light extraction of high power AlGaInP-based light-emitting diodes.

    PubMed

    Park, Hyeong-Ho; Zhang, Xin; Cho, Yunae; Kim, Dong-Wook; Kim, Joondong; Lee, Keun Woo; Choi, Jehyuk; Lee, Hee Kwan; Jung, Sang Hyun; Her, Eun Jin; Kim, Chang Hwan; Moon, A-Young; Shin, Chan-Soo; Shin, Hyun-Beom; Sung, Ho Kun; Park, Kyung Ho; Park, Hyung-Ho; Kim, Hi-Jung; Kang, Ho Kwan

    2014-05-01

    A new approach to surface roughening was established and optimized in this paper for enhancing the light extraction of high power AlGaInP-based LEDs, by combining ultraviolet (UV) assisted imprinting with dry etching techniques. In this approach, hexagonal arrays of cone-shaped etch pits are fabricated on the surface of LEDs, forming gradient effective-refractive-index that can mitigate the emission loss due to total internal reflection and therefore increase the light extraction efficiency. For comparison, wafer-scale FLAT-LEDs without any surface roughening, WET-LEDs with surface roughened by wet etching, and DRY-LEDs with surface roughened by varying the dry etching time of the AlGaInP layer, were fabricated and characterized. The average output power for wafer-scale FLAT-LEDs, WET-LEDs, and DRY3-LEDs (optimal) at 350 mA was found to be 102, 140, and 172 mW, respectively, and there was no noticeable electrical degradation with the WET-LEDs and DRY-LEDs. The light output was increased by 37.3% with wet etching, and 68.6% with dry etching surface roughening, respectively, without compromising the electrical performance of LEDs. A total number of 1600 LED chips were tested for each type of LEDs. The yield of chips with an optical output power of 120 mW and above was 0.3% (4 chips), 42.8% (684 chips), and 90.1% (1441 chips) for FLAT-LEDs, WET-LEDs, and DRY3-LEDs, respectively. The dry etching surface roughening approach developed here is potentially useful for the industrial mass production of wafer-scale high power LEDs. PMID:24922380

  9. Versatile Wafer-Scale Technique for the Formation of Ultrasmooth and Thickness-Controlled Graphene Oxide Films Based on Very Large Flakes.

    PubMed

    Azevedo, Jol; Campidelli, Stphane; He, Delong; Cornut, Renaud; Bertucchi, Michael; Sorgues, Sbastien; Benattar, Jean-Jacques; Colbeau-Justin, Christophe; Derycke, Vincent

    2015-09-30

    We present a new strategy to form thickness-adjusted and ultrasmooth films of very large and unwrinkled graphene oxide (GO) flakes through the transfer of both hemispherical and vertical water films stabilized by surfactants. With its versatility in terms of substrate type (including flexible organic substrates) and in terms of flake density (from isolated flakes to continuous and multilayer films), this wafer-scale assembly technique is adapted to a broad range of experiments involving GO and rGO (reduced graphene oxide). We illustrate its use through the evaluation of transparent rGO electrodes. PMID:26348321

  10. Laser wafering for silicon solar.

    SciTech Connect

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  11. Nano-scale origins of recombination activity and optical properties of extended defects in mc-Si wafers and PV cells

    NASA Astrophysics Data System (ADS)

    Guthrey, Harvey L., IV

    Multicrystalline silicon (mc-Si) is the most used absorber in photovoltaic (PV) cells at present. If efficiencies are to improve in this established technology a better understanding of how minority carrier lifetimes are reduced is necessary. The capture of minority carriers by states associated with extended defects is known to play a major role in reducing minority carrier lifetimes. Energy levels introduced into the silicon bandgap often have electrical activity or optical signatures that can provide clues as to the structural or chemical origin of a particular level. This work utilizes electron beam induced current (EBIC), cathodoluminescence (CL) imaging and spectroscopy, photoluminescence (PL) imaging, and nano-scale chemical analysis to provide new insight into the origin of the electrical and optical properties of extended defects in mc-Si wafers and PV cells. A new interpretation of the temperature dependence of EBIC contrast is formulated based on observations of an anomalous form of the contrast vs. temperature curves as well as evidence of high impurity content. In addition an attempt is made to determine the origin of specific types of defect related emission as well as how this emission is influenced by processing steps applied to mc-Si wafers. Nano-scale chemical analysis is used to reveal the origin of the observed luminescence.

  12. Wafer-scale pixelated scintillator and specially designed data acquisition system for fiber optic taper array-coupled digital x-ray detector

    NASA Astrophysics Data System (ADS)

    Zhao, Zhigang; Li, Ji; Lei, Yaohu; Wang, Ru; Ren, Jianping; Qiao, Jian; Niu, Hanben

    2015-09-01

    A digital x-ray detector scheme based on a pixelated scintillator coupled with a fiber optic (FOT) array is suitable for many high-resolution x-ray imaging applications. However, certain challenges need to be addressed for fabrication of wafer-scale uniform pixelated x-ray scintillators. In addition, difficulties associated with implementation of the data acquisition system for acquiring output image data from the multiple image sensors used in the detector also need to be addressed. In this paper, a 22 FOT array-coupled digital x-ray detector scheme using a 5-in. pixelated scintillator is proposed. A novel fabrication setup along with the corresponding processes for fabricating the wafer-scale pixelated scintillator and implementation of a specially designed embedded data acquisition system based on a single embedded micro-processer (ARM) and four field-programmable gate array (FPGA) chips are discussed in detail. Preliminary experiments demonstrate that this pixelated scintillator-based digital x-ray detector scheme with an active imaging area of about 100 mm100 mm shows considerable potential for use in high-resolution x-ray imaging.

  13. Large-area, wafer-scale epitaxial growth of germanium on silicon and integration of high-performance transistors

    NASA Astrophysics Data System (ADS)

    Ghosh, Swapnadip

    Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the 105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress simulation shows that the oval air gaps around the SiO2 template can reduce the thermal stress by 50% and help reduce the DD. We have then compared the structural and electrical characteristics of n-type Ge films with its p-type counter parts. In n-type Ge, the DD decreases from 109cm-2 near the Ge-Si interface to 105 cm-2 at the film surface. In contrast, we observe 5x107 cm-2 TDD at the film surface in p-type Ge. The full width at half-maximum for our n-type Ge(004) XRD peak is ~70% narrower than that of p-type Ge. As a stringent test of the dislocation reduction, we have also fabricated and characterized high-carrier-mobility MOSFETs on GoS substrates. We also report p- and n-MOSFETs with microeff of 401 and 940 cm2/V-s and a subthreshold slope of 100 and 200 mV/decade, respectively. These effective mobilities show an exceptional 82 and 30% improvement over that of conventional Si channel MOSFETs. We also investigate the optical quality of ultra-low DD GoS film by measuring photoluminescence (PL). The n-type Ge PL main peak shows pronounced tensile-strain (x0.8%) than that of p-type which is an indicator of direct BG shrinking at the \\Gcy band-edge. Going beyond epitaxial engineering and device fabrication, we have also recently demonstrated a scalable path to create a 2D array of Ge quantum dots (QDs) on responsive SiGe substrates based on elastic mechanical deformation and subsequent SiGe compositional redistribution, coupled with MBE growth. For large-scale manufacturing of single-electron transistors, we have also demonstrated that a spatially structured elastic compressive stress to the SiGe substrate with thermally annealing leads to a compositional redistribution of Si and Ge in the near-surface region of SiGe substrates, forming a 2D array of Ge-depleted nanoscale regions. Based on these latest findings, we have also begun to chart a future direction for my research group, where one can explore new advanced device architectures, such as Si-compatible, optically actuated, Ge-quantum dot-based field effect transistors.

  14. Ultrathin silicon wafer bonding: Physics and applications

    NASA Astrophysics Data System (ADS)

    Beggans, Michael Howard

    Ultrathin silicon wafer bonding is an emerging process that simplifies device fabrication, reduces manufacturing costs, increases yield, and allows the realization of novel devices. Ultrathin silicon wafers are between 3 and 200 microns thick with all the same properties of the thicker silicon wafers (greater than 300 microns) normally used by the semiconductor electronics industry. Wafer bonding is one technique by which multiple layers are formed. In this thesis, the history and practice of wafer bonding is described and applied to the manufacture of microelectomechanical systems (MEMS) devices with layer thickness on the scale of microns. Handling and processing problems specific to ultrathin silicon wafers and their bonding are addressed and solved. A model that predicts the conformal nature of these flexible silicon wafers and its impact on bonding is developed in terms of a relatively new description of surface quality, the Power Spectral Density (PSD). A process for reducing surface roughness of silicon is elucidated and a model of this process is described. A method of detecting particle contamination in chemical baths and other processes using wafer bonding is detailed. A final section highlights some recent work that has used ultrathin silicon wafer bonding to fabricate MEMS devices that have reduced existing design complexity and made possible novel, and otherwise difficult to produce, sensors. A new fabrication process that can reduce the required time for "proof-of-principle" devices using ultrathin silicon wafers is also described.

  15. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  16. High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth.

    PubMed

    Miao, Xin; Chabak, Kelson; Zhang, Chen; Mohseni, Parsian K; Walker, Dennis; Li, Xiuling

    2015-05-13

    Wafer-scale defect-free planar III-V nanowire (NW) arrays with ?100% yield and precisely defined positions are realized via a patterned vapor-liquid-solid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 10(4), 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 1.5 cm(2) chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics. PMID:25494481

  17. Mechanical properties of wear tested LIGA nickel.

    SciTech Connect

    Jungk, John Michael; Prasad, Somuri V.; Gerberich, William W.; Moody, Neville Reid; Kennedy, Marian S.; Bahr, David F.

    2005-03-01

    Strength, friction, and wear are dominant factors in the performance and reliability of materials and devices fabricated using nickel based LIGA and silicon based MEMS technologies. However, the effects of frictional contacts and wear on long-term performance of microdevices are not well-defined. To address these effects on performance of LIGA nickel, we have begun a program employing nanoscratch and nanoindentation. Nanoscratch techniques were used to generate wear patterns using loads of 100, 200, 500, and 990 {micro}N with each load applied for 1, 2, 5, and 10 passes. Nanoindentation was then used to measure properties in each wear pattern correcting for surface roughness. The results showed a systematic increase in hardness with applied load and number of nanoscratch passes. The results also showed that the work hardening coefficient determined from indentation tests within the wear patterns follows the results established from tensile tests, supporting use of a nanomechanics-based approach for studying wear.

  18. Optical measurement of LIGA milliengine performance

    SciTech Connect

    Dickey, F.M.; Holswade, S.C.; Christenson, T.R.; Garcia, E.J.; Polosky, M.A.

    1997-12-31

    Understanding the parameters that affect the performance of milliscale and microscale actuators is essential to the development of optimized designs and fabrication processes, as well as the qualification of devices for commercial applications. This paper discusses the development of optical techniques for motion measurements of LIGA fabricated milliengines. LIGA processing permits the fabrication of precision millimeter-sized machine elements that cannot be fabricated by conventional miniature machining techniques because of their small feature sizes. In addition, tolerances of 1 part in 10{sup 3} to 10{sup 4} may be maintained in millimeter sized components with this processing technique. Optical techniques offer a convenient means for measuring long term statistical performance data and transient responses needed to optimize designs and manufacturing techniques. Optical techniques can also be used to provide feedback signals needed for control and sensing of the state of the machine. Optical probe concepts and experimental data obtained using a milliengine developed at Sandia National Laboratories are presented.

  19. Cyanoacrylate bonding of thick resists for LIGA

    NASA Astrophysics Data System (ADS)

    Rogers, James G., IV; Marques, Christophe; Kelly, Kevin W.; Sangishetty, Venkat; Khan Malek, Chantal G.

    1996-09-01

    The MicroSystems Engineering Team ((mu) SET) at Louisiana State University, in close collaboration with the Center for Advanced Microstructures and Devices, has successfully completed the lithography and electroplating steps of the LIGA process sequence using cyanoacrylate to bond a PMMA resist layer to a nickel surface. Nickel microstructures 300 micrometers in height have been electroplated. Tests were performed which indicate that the bond between cyanoacrylate and nickel is much stronger than the bond between PMMA and nickel.

  20. Solution structure of leptospiral LigA4 Big domain.

    PubMed

    Mei, Song; Zhang, Jiahai; Zhang, Xuecheng; Tu, Xiaoming

    2015-11-13

    Pathogenic Leptospiraspecies express immunoglobulin-like proteins which serve as adhesins to bind to the extracellular matrices of host cells. Leptospiral immunoglobulin-like protein A (LigA), a surface exposed protein containing tandem repeats of bacterial immunoglobulin-like (Big) domains, has been proved to be involved in the interaction of pathogenic Leptospira with mammalian host. In this study, the solution structure of the fourth Big domain of LigA (LigA4 Big domain) from Leptospira interrogans was solved by nuclear magnetic resonance (NMR). The structure of LigA4 Big domain displays a similar bacterial immunoglobulin-like fold compared with other Big domains, implying some common structural aspects of Big domain family. On the other hand, it displays some structural characteristics significantly different from classic Ig-like domain. Furthermore, Stains-all assay and NMR chemical shift perturbation revealed the Ca(2+) binding property of LigA4 Big domain. PMID:26449456

  1. Injection molding of LIGA and LIGA-similar microstructures using filled and unfilled thermoplastics

    NASA Astrophysics Data System (ADS)

    Ruprecht, Robert; Bacher, Walter; Hausselt, Juergen H.; Piotter, Volker

    1995-09-01

    Micromolding is a key technology for the economic production of micro-components for microsystems. It is applied in several microstructuring techniques including the LIGA process which was invented and developed at Forschungszentrum Karlsruhe. Injection molding of multiple-use LIGA tool inserts produced by deep-etch x-ray lithography and electroforming allows the economic production of components for most applications using microsystems technology. Such microstructures are produced in small and large series and commercialized by Forschungszentrum Karlsruhe and the microParts Company, Dormund, Germany, cooperating within the framework of a license agreement. Special molding machines are applied for the production of single- or multi-stepped microstructures of a few micrometers in lateral dimension and structural details in the submicrometer range. Maximum aspect ratios of several ten up to 600 are achieved. In contrast to compact disc production, the machines are equipped with a special control unit, by means of which tool temperature is often kept above the melting temperatures of the plastics processed during injection. Evacuation of the tool cavity is required for the complete filling of the microstructurized nest area of the mold. Cycle time is mainly determined by the heating and cooling of the whole molding tool. Recently, novel techniques were developed for the production of ceramic LIGA or LIGA-similar microstructures at Forschungszentrum Karlsruhe, where further development of the LIGA technique has been performed for more than a decade. Using lost plastic microstructures and sometimes even metal tools, microstructures are made of structural (e.g., aluminum oxide, zirconium oxide) and functional ceramics (e.g., PZT). Current development activities are aimed at producing lost plastic molds for metal microstructures by injection molding. Molding tests with conductively filled thermoplastics have been carried out to manufacture lost molds for e.g. spin nozzles.

  2. Microstructural Evolution of SAC305 Solder Joints in Wafer Level Chip-Scale Packaging (WLCSP) with Continuous and Interrupted Accelerated Thermal Cycling

    NASA Astrophysics Data System (ADS)

    Zhou, Quan; Zhou, Bite; Lee, Tae-Kyu; Bieler, Thomas

    2016-02-01

    Four high-strain design wafer level chip scale packages were given accelerated thermal cycling with a 10°C/min ramp rate and 10 min hold times between 0°C and 100°C to examine the effects of continuous and interrupted thermal cycling on the number of cycles to failure. The interruptions given two of the samples were the result of periodic examinations using electron backscattered pattern mapping, leading to room temperature aging of 30 days-2.5 years after increments of about 100 cycles at several stages of the cycling history. The continuous thermal cycling resulted in solder joints with a much larger degree of recrystallization, whereas the interrupted thermal cycling tests led to much less recrystallization, which was more localized near the package side, and the crack was more localized near the interface and had less branching. The failure mode for both conditions was still the same, with cracks nucleating along the high angle grain boundaries formed during recrystallization. In conditions where there were few recrystallized grains, recovery led to formation of subgrains that strengthened the solder, and the higher strength led to a larger driving force for crack growth through the solder, leading to failure after less than half of the cycles in the continuous accelerated thermal cycling condition. This work shows that there is a critical point where sufficient strain energy accumulation will trigger recrystallization, but this point depends on the rate of strain accumulation in each cycle and various recovery processes, which further depends on local crystal orientations, stress state evolution, and specific activated slip and twinning systems.

  3. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis

    NASA Astrophysics Data System (ADS)

    Zhao, C.; Konstantinidis, A. C.; Zheng, Y.; Anaxagoras, T.; Speller, R. D.; Kanicki, J.

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm‑1 and a DQE of around 0.5 at spatial frequencies  <1 mm‑1. In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered.

  4. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    PubMed

    Zhao, C; Konstantinidis, A C; Zheng, Y; Anaxagoras, T; Speller, R D; Kanicki, J

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm(-1) and a DQE of around 0.5 at spatial frequencies  <1 mm(-1). In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered. PMID:26540090

  5. Wafer scale micromachine assembly method

    DOEpatents

    Christenson, Todd R. (Albuquerque, NM)

    2001-01-01

    A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.

  6. Scriber for silicon wafers

    NASA Technical Reports Server (NTRS)

    Yamakawa, K. A.; Fortier, E. P. (inventors)

    1981-01-01

    A device for dividing silicon wafers into rectangular chips is characterized by a base including a horizontally oriented bed with a planar support surface, a vacuum chuck adapted to capture a silicon wafer seated on the support for translation in mutually perpendicular directions. A stylus support mounted on the bed includes a shaft disposed above and extended across the bed and a truck mounted on the shaft and supported thereby for linear translation along a path extended across the bed a vertically oriented scribe has a diamond tip supported by the truck also adapted as to engage a silicon wafer captured by the chuck and positioned beneath it in order to form score lines in the surface of the wafer as linear translation is imparted to the truck. A chuck positioning means is mounted on the base and is connected to the chuck for positioning the chuck relative to the stylus.

  7. Wafer characteristics via reflectometry

    DOEpatents

    Sopori, Bhushan L. (Denver, CO)

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  8. Micro-grippers for assembly of LIGA parts

    SciTech Connect

    Feddema, J.; Polosky, M.; Christenson, T.; Spletzer, B.; Simon, R.

    1997-12-31

    This paper describes ongoing testing of two microgrippers for assembly of LIGA (Lithographie Galvanoformung Abformung) parts. The goal is to place 100 micron outside diameter (OD) LIGA gears with a 50 micron inner diameter hole onto pins ranging from 35 to 49 microns. The first micro gripper is a vacuum gripper made of a 100 micron OD stainless steel tube. The second micro gripper is a set of tweezers fabricated using the LIGA process. Nickel, Permalloy, and copper materials are tested. The tweezers are actuated by a collet mechanism which is closed by a DC linear motor.

  9. Reciprocating Saw for Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.; Collins, E. R., Jr.

    1985-01-01

    Concept increases productivity and wafer quality. Cutting wafers from silicon ingots produces smooth wafers at high rates with reduced blade wear. Involves straight reciprocating saw blade and slight rotation of ingot between cutting strokes. Many parallel blades combined to cut many wafers simultaneously from ingot.

  10. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  11. Wafer level reliability testing: An idea whose time has come

    NASA Technical Reports Server (NTRS)

    Trapp, O. D.

    1987-01-01

    Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

  12. Cantilevered multilevel LIGA devices and methods

    DOEpatents

    Morales, Alfredo Martin; Domeier, Linda A.

    2002-01-01

    In the formation of multilevel LIGA microstructures, a preformed sheet of photoresist material, such as polymethylmethacrylate (PMMA) is patterned by exposure through a mask to radiation, such as X-rays, and developed using a developer to remove the exposed photoresist material. A first microstructure is then formed by electroplating metal into the areas from which the photoresist has been removed. Additional levels of microstructure are added to the initial microstructure by covering the first microstructure with a conductive polymer, machining the conductive polymer layer to reveal the surface of the first microstructure, sealing the conductive polymer and surface of the first microstructure with a metal layer, and then forming the second level of structure on top of the first level structure. In such a manner, multiple layers of microstructure can be built up to allow complex cantilevered microstructures to be formed.

  13. Miniature Scroll Pumps Fabricated by LIGA

    NASA Technical Reports Server (NTRS)

    Wiberg, Dean; Shcheglov, Kirill; White, Victor; Bae, Sam

    2009-01-01

    Miniature scroll pumps have been proposed as roughing pumps (low - vacuum pumps) for miniature scientific instruments (e.g., portable mass spectrometers and gas analyzers) that depend on vacuum. The larger scroll pumps used as roughing pumps in some older vacuum systems are fabricated by conventional machining. Typically, such an older scroll pump includes (1) an electric motor with an eccentric shaft to generate orbital motion of a scroll and (2) conventional bearings to restrict the orbital motion to a circle. The proposed miniature scroll pumps would differ from the prior, larger ones in both design and fabrication. A miniature scroll pump would include two scrolls: one mounted on a stationary baseplate and one on a flexure stage (see figure). An electromagnetic actuator in the form of two pairs of voice coils in a push-pull configuration would make the flexure stage move in the desired circular orbit. The capacitance between the scrolls would be monitored to provide position (gap) feedback to a control system that would adjust the drive signals applied to the voice coils to maintain the circular orbit as needed for precise sealing of the scrolls. To minimize power consumption and maximize precision of control, the flexure stage would be driven at the frequency of its mechanical resonance. The miniaturization of these pumps would entail both operational and manufacturing tolerances of <1 m. Such tight tolerances cannot be achieved easily by conventional machining of high-aspect-ratio structures like those of scroll-pump components. In addition, the vibrations of conventional motors and ball bearings exceed these tight tolerances by an order of magnitude. Therefore, the proposed pumps would be fabricated by the microfabrication method known by the German acronym LIGA ( lithographie, galvanoformung, abformung, which means lithography, electroforming, molding) because LIGA has been shown to be capable of providing the required tolerances at large aspect ratios.

  14. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  15. Modeling electrodeposition in LIGA microfabrication using an arbitrary-Lagrangian-Eulerian formulation for moving-boundary tracking with repeated re-meshing.

    SciTech Connect

    Chen, Ken Shuang

    2003-06-01

    Electrodeposition is a key process in LIGA (Lithographie, Galvanoformung, Abformung - German words for lithography, electroplating and molding) - microfabrication, which is increasingly demonstrated to be a viable technology for fabricating micro-devices or parts. LIGA Electrodeposition involves complex multi-physics phenomena: (1) diffusion, migration, and convection of charged species in a centimeter-scale electrolyte-bath region and in micron-scale featurecavity or trench regions; (2) homogeneous and heterogeneous electrochemical reactions; and (3) moving deposition surface or surfaces on which metal ions (e.g., {approx} i) are electrochemically reduced to form a pure metal or an alloy.

  16. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  17. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  18. Etching Of Semiconductor Wafer Edges

    DOEpatents

    Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

    2003-12-09

    A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

  19. Metallic nanowires by full wafer stencil lithography.

    PubMed

    Vazquez-Mena, O; Villanueva, G; Savu, V; Sidler, K; van den Boogaart, M A F; Brugger, J

    2008-11-01

    Aluminum and gold nanowires were fabricated using 100 mm stencil wafers containing nanoslits fabricated with a focused ion beam. The stencils were aligned and the nanowires deposited on a substrate with predefined electrical pads. The morphology and resistivity of the wires were studied. Nanowires down to 70 nm wide and 5 mum long have been achieved showing a resistivity of 10 microOmegacm for Al and 5 microOmegacm for Au and maximum current density of approximately 10(8) A/cm(2). This proves the capability of stencil lithography for the fabrication of metallic nanowires on a full wafer scale. PMID:18817451

  20. Laser-LIGA for Ni microcantilevers

    NASA Astrophysics Data System (ADS)

    Jin, Hengyi; Harvey, Erol C.; Hayes, Jason P.; Ghantasala, Muralidhar K.; Fu, Yao; Jolic, Karlo; Solomon, Matthew; Graves, Kynan

    2002-11-01

    This paper presents our design and experimental results of nickel microcantilevers, which were fabricated using a laser-LIGA process, based on KrF (248 nm) excimer laser micromachining. A chrome-on-quartz mask, containing the desired mask patterns was prepared for this work. The substrate of copper (30 ?m thick) clad printed circuit board (PCB) was laminated with Laminar 5038 photopolymer to be laser patterned. Following laser patterning and laser cleaning, all the samples were electroformed with nickel on top of the copper layer. To release the Ni microcantilevers, the excimer laser was employed again to remove the polymer in the localised area to facilitate Cu selective etching. Here, copper acted as the sacrificial layer as well. The Cu selective etching was carried out with ~ 20 % (wt) aqueous solution of ammonium persulfate. Because the Cu selective etching is isotropic, some undercuts happened next to the anchor area. The samples were characterised using optical microscope, confocal laser scanning microscope and SEM, and some of Ni cantilevers were tested electro-thermally. Their performance was analyzed with respect to the simulation results.

  1. Atomic scale fabrication of dangling bond structures on hydrogen passivated Si(0 0 1) wafers processed and nanopackaged in a clean room environment

    NASA Astrophysics Data System (ADS)

    Kolmer, Marek; Godlewski, Szymon; Zuzak, Rafal; Wojtaszek, Mateusz; Rauer, Caroline; Thuaire, Aurlie; Hartmann, Jean-Michel; Moriceau, Hubert; Joachim, Christian; Szymonski, Marek

    2014-01-01

    Specific surfaces allowing the ultra-high vacuum (UHV) creation of electronic interconnects and atomic nanostructures are required for the successful development of novel nanoscale electronic devices. Atomically flat and reconstructed Si(0 0 1):H surfaces are serious candidates for that role. In this work such Si:H surfaces were prepared in a cleanroom environment on 200 mm silicon wafers with a hydrogen bake and were subsequently bonded together to ensure the surface protection, and allow their transportation and storage for several months in air. Given the nature of the bonding, which was hydrophobic with weak van der Waals forces, we were then able to de-bond them in UHV. We show that the quality of the de-bonded Si:H surface enables the "at will" construction of sophisticated and complex dangling bond (DB) nanostructures by atomically precise scanning tunneling microscope (STM) tip induced desorption of hydrogen atoms. The DB structures created on slightly doped Si:H samples were characterized by scanning tunneling microscopy and spectroscopy (STM/STS) performed at 4 K. Our results demonstrate that DB nanostructures fabricated on UHV de-bonded Si(0 0 1):H wafers could be directly incorporated in future electronics as interconnects and parts of nanoscale logic circuits.

  2. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  3. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the developments made under this program have increased 1366 confidence that Direct Wafers can be produced for ~$0.10/W, still nearly 50% lower than current industry best practice. Wafer quality also steadily improved throughout the program, both in electrical performance and geometry. The improvements to electrical performance were achieved through a combination of optimized heat transfer during growth, reduction of metallic impurities to below 10 ppbw total metals, and lowering oxygen content to below 2e17 atoms/cc. Wafer average thickness has been reduced below 200µm with standard deviation less than 20µm. Measurement of spatially varying thickness shortly after wafer growth is being used to continually improve uniformity by adjusting thermal conditions. At the conclusion of the program, 1366 has developed strong relationships with four leading Tier1 cell manufactures and several have demonstrated 17% cell efficiency on Direct Wafer. Sample volumes were limited, with the largest trial consisting of 300 Direct Wafers, and there remains strong pull for larger quantities necessary for qualification before sales contracts can be signed. This will be the focus of our pilot manufacturing scale up in 2014.

  4. Recent Developments in Microsystems Fabricated by the Liga-Technique

    NASA Technical Reports Server (NTRS)

    Schulz, J.; Bade, K.; El-Kholi, A.; Hein, H.; Mohr, J.

    1995-01-01

    As an example of microsystems fabricated by the LIGA-technique (x-ray lithography, electroplating and molding), three systems are described and characterized: a triaxial acceleration sensor system, a micro-optical switch, and a microsystem for the analysis of pollutants. The fabrication technologies are reviewed with respect to the key components of the three systems: an acceleration sensor, and electrostatic actuator, and a spectrometer made by the LIGA-technique. Aa micro-pump and micro-valve made by using micromachined tools for molding and optical fiber imaging are made possible by combining LIGA and anisotropic etching of silicon in a batch process. These examples show that the combination of technologies and components is the key to complex microsystems. The design of such microsystems will be facilitated is standardized interfaces are available.

  5. Great enhancement in the excitonic recombination and light extraction of highly ordered InGaN/GaN elliptic nanorod arrays on a wafer scale.

    PubMed

    Zhuang, Zhe; Guo, Xu; Liu, Bin; Hu, Fengrui; Dai, Jiangping; Zhang, Yun; Li, Yi; Tao, Tao; Zhi, Ting; Xie, Zili; Ge, Haixiong; Wang, Xiaoyong; Xiao, Min; Wang, Tao; Shi, Yi; Zheng, Youdou; Zhang, Rong

    2016-01-01

    A series of highly ordered c-plane InGaN/GaN elliptic nanorod (NR) arrays were fabricated by our developed soft UV-curing nanoimprint lithography on a wafer. The photoluminescence (PL) integral intensities of NR samples show a remarkable enhancement by a factor of up to two orders of magnitude compared with their corresponding as-grown samples at room temperature. The radiative recombination in NR samples is found to be greatly enhanced due to not only the suppressed non-radiative recombination but also the strain relaxation and optical waveguide effects. It is demonstrated that elliptic NR arrays improve the light extraction greatly and have polarized emission, both of which possibly result from the broken structure symmetry. Green NR light-emitting diodes have been finally realized, with good current-voltage performance and uniform luminescence. PMID:26595508

  6. Great enhancement in the excitonic recombination and light extraction of highly ordered InGaN/GaN elliptic nanorod arrays on a wafer scale

    NASA Astrophysics Data System (ADS)

    Zhuang, Zhe; Guo, Xu; Liu, Bin; Hu, Fengrui; Dai, Jiangping; Zhang, Yun; Li, Yi; Tao, Tao; Zhi, Ting; Xie, Zili; Ge, Haixiong; Wang, Xiaoyong; Xiao, Min; Wang, Tao; Shi, Yi; Zheng, Youdou; Zhang, Rong

    2016-01-01

    A series of highly ordered c-plane InGaN/GaN elliptic nanorod (NR) arrays were fabricated by our developed soft UV-curing nanoimprint lithography on a wafer. The photoluminescence (PL) integral intensities of NR samples show a remarkable enhancement by a factor of up to two orders of magnitude compared with their corresponding as-grown samples at room temperature. The radiative recombination in NR samples is found to be greatly enhanced due to not only the suppressed non-radiative recombination but also the strain relaxation and optical waveguide effects. It is demonstrated that elliptic NR arrays improve the light extraction greatly and have polarized emission, both of which possibly result from the broken structure symmetry. Green NR light-emitting diodes have been finally realized, with good currentvoltage performance and uniform luminescence.

  7. Fracture of silicon wafers

    NASA Astrophysics Data System (ADS)

    McLaughlin, J. C.; Willoughby, A. F. W.

    1987-11-01

    In spite of the increasing use of silicon in applications where mechanical stresses are deliberately applied to the material, such as in transducers, and the fatal nature of cracking in silicon devices, there is very limited characterisation and understanding of the fracture behaviour of silicon wafers at room temperature. This understanding is of increasing importance with the use of larger diameter wafers in modern technology. This paper examines the fracture strength of a wide range of silicon material both as-grown and after processing. The wafers tested were from crystals grwon by float-zone and Czochralski techniques and the effects of oxidation, ion-implantation and annealing in various environments have been studied. The technique used to measure the fracture stress involved simply supporting the wafer on an aluminium ring concentric to the load axis. The load was gradually increased until the wafer fractured. This method was chosen to avoid edge effects, and has proved to have adequate reproducibility. Typical values of the fracture stress obtained by this method, for different crystals, vary between 2 and 3.5 GPa. In the first part of the study, the role of the surface on the fracture behaviour has been investigated in detail. While the surface perfection of the tensile surface has a major effect on the fracture stress (as shown in previous studies), some of the results were found to be sensitive to the compressive surface as well. In the case where the results are sensitive to the compressive surface finish the fracture stress rose from 3.7 to 8.8 GPa as the surface finish was improved while in the cases where they were not sensitive the fracture stress remained at about 3.5-4.6 GPa. Only in the float-zone material were fracture stresses approaching 8.8 GPa observed. At this level of fracture stress, the behaviour is believed to be sensitive to surface defects less than 0.01 ?m in size. These results can be analyzed in terms of surface controlled defects under conditions where surface defects are dominant and bulk controlled defects where these defects are dominant. In this manner bulk effects can be isolated from surface ones. This gives the opportunity to study the effects of specific defects on the fracture stress and the results in this paper are discussed in terms of the role of surface and internal defects on the fracture stress.

  8. Torsion Testing of Diffusion Bonded LIGA Formed Nickel

    SciTech Connect

    Buchheit, T.E.; Christenson, T.R.; Schmale, D.T.

    1999-01-27

    A test technique has been devised which is suitable for the testing of the bond strength of batch diffusion bonded LIGA or DXRL defined structures. The method uses a torsion tester constructed with the aid of LIGA fabrication and distributed torsion specimens which also make use of the high aspect ratio nature of DXRL based processing. Measurements reveal achieved bond strengths of 130MPa between electroplated nickel with a bond temperature of 450 C at 7 ksi pressure which is a sufficiently low temperature to avoid mechanical strength degradation.

  9. Wafer level warpage characterization of 3D interconnect processing wafers

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2012-03-01

    We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 ?m after thinning down to the nominal thickness of 75 ?m and 50 ?m. The measurement precision is better than 2 um.

  10. Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

    PubMed Central

    Thomson, Stephen R. D.; Perron, Justin K.; Kimball, Mark O.; Mehta, Sarabjit; Gasparini, Francis M.

    2014-01-01

    Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 m thick Si wafers with about 1 m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale. PMID:24457563

  11. Augmented reality for wafer prober

    NASA Astrophysics Data System (ADS)

    Gilgenkrantz, Pascal

    2011-03-01

    The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

  12. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  13. Automatic inspection of silicon wafers

    NASA Technical Reports Server (NTRS)

    Martin, M.

    1980-01-01

    Laser machine scans wafers for contaminating particles which cause open circuits, short circuits, and other defects in integrated circuits and transfers good wafers to integrated circuit processing equipment. Machine is faster and more accurate than human operator using lightfield/dark field microscope.

  14. High-Speed Wafer Slicer

    NASA Technical Reports Server (NTRS)

    Schmid, F.; Khattak, C. P.; Smith, M. B.

    1982-01-01

    Multiblade cutter slices silicon ingots into solar-cell wafers quickly and with little waste. Speed and blade pressure ensure high wafer-production rate. Lightweight, balanced construction minimizes blade vibration and reduces sideways motion that would otherwise widen kerf and waste silicon.

  15. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  16. W-band LiGA fabricated klystron

    NASA Astrophysics Data System (ADS)

    Song, Liqun

    2002-01-01

    Klystrino-W-band klystron was proposed by scientists at SLAC to satisfy recent applications in advanced accelerators, medical treatment, radars and communications. LiGA (a German acronym for lithographe, galvanoformung, and abformung) is introduced in the fabrication of klystrino for the first time in the history of microwave tube fabrication. The cold test experiments show that LiGA fabrication yields best surface smoothness compared with an alternative way EDM (Electrical Discharge Machining). Resultantly LiGA fabricated klystrino has the smallest wall loss which maximizes the circuit efficiency of the output structure. A multiple-gap coupled cavity is motivated to be employed as the klystrino output cavity for maximizing the efficiency. Klytrino is simulated by 1-D, 2-D and 3-D simulation codes. Particularly a complete klystrino is simulated intensively using 2-D MAGIC Particle-in-Cell (PIC) code either for beam absence or beam presence. Many simulation techniques are developed such as model transformation from 3-D to 2-D, circuit parameter simulation, dispersion characteristic analysis, pre bunched electron beam mode and so on. Klystrino, as a 3-D structure, is modeled by 3-D MAFIA for analyzing the cold circuit properties. 3-D MAGIC is explored to simulate klystrino for the actual structure analysis and actual beam interaction process observation.

  17. System for slicing wafers

    NASA Technical Reports Server (NTRS)

    1982-01-01

    A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

  18. Wafer-Scale Precise Patterning of Organic Single-Crystal Nanowire Arrays via a Photolithography-Assisted Spin-Coating Method.

    PubMed

    Deng, Wei; Zhang, Xiujuan; Wang, Liang; Wang, Jincheng; Shang, Qixun; Zhang, Xiaohong; Huang, Liming; Jie, Jiansheng

    2015-12-01

    A photolithography-assisted spin-coating approach is developed to produce single-crystal organic nanowire (NW) arrays at designated locations with high precision and high efficiency. This strategy enables the large-scale fabrication of organic NW arrays with nearly the same accuracy, reliability, and flexibility as photolithography. The high mobilities of the organic NWs enable the control of the switch of multicolored light-emitting devices with good stability. PMID:26460612

  19. Wafer Replacement Cluster Tool (Presentation);

    SciTech Connect

    Branz, H. M.

    2008-04-01

    This presentation on wafer replacement cluster tool discusses: (1) Platform for advanced R and D toward SAI 2015 cost goal--crystal silicon PV at area costs closer to amorphous Si PV, it's 15% efficiency, inexpensive substrate, and moderate temperature processing (<800 C); (2) Why silicon?--industrial and knowledge base, abundant and environmentally benign, market acceptance, and good efficiency; and (3) Why replace wafers?--expensive, high embedded energy content, and uses 50-100 times more silicon than needed.

  20. Wafer handling and placement tool

    DOEpatents

    Witherspoon, Linda L. (22 Cottonwood La., Los Lunas, NM 87031)

    1988-01-05

    A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

  1. Spinner For Etching Of Semiconductor Wafers

    NASA Technical Reports Server (NTRS)

    Lombardi, Frank

    1989-01-01

    Simple, inexpensive apparatus coats semiconductor wafers uniformly with hydrofluoric acid for etching. Apparatus made in part from small commercial electric-fan motor. Features bowl that collects acid. Silicon wafer placed on platform and centered on axis; motor switched on. As wafer spins, drops of hydrofluoric acid applied from syringe. Centrifugal force spreads acid across wafer in fairly uniform sheet.

  2. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    PubMed

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

  3. Development of Megasonic cleaning for silicon wafers. Final report

    SciTech Connect

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  4. Computational Modeling in Plasma Processing for 300 mm Wafers

    NASA Technical Reports Server (NTRS)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  5. Wafer sampling by regression for systematic wafer variation detection

    NASA Astrophysics Data System (ADS)

    Moon, Byungsool; McNames, James; Whitefield, Bruce; Rudolph, Paul; Zola, Jeff

    2005-05-01

    In-line measurements are used to monitor semiconductor manufacturing processes for excessive variation using statistical process control (SPC) chart techniques. Systematic spatial wafer variation often occurs in a recognizable pattern across the wafer that is characteristic of a particular manufacturing step. Visualization tools are used to associate these patterns with specific manufacturing steps preceding the measurement. Acquiring the measurements is an expensive and slow process. The number of sites measured on a wafer must be minimized while still providing sufficient data to monitor the process. We address two key challenges to effective wafer-level monitoring. The first challenge is to select a small sample of inspection sites that maximize detection sensitivity to the patterns of interest, while minimizing the confounding effects of other types of wafer variation. The second challenge is to develop a detection algorithm that maximizes sensitivity to the patterns of interest without exceeding a user-specified false positive rate. We propose new sampling and detection methods. Both methods are based on a linear regression model with distinct and orthogonal components. The model is flexible enough to include many types of systematic spatial variation across the wafer. Because the components are orthogonal, the degree of each type of variation can be estimated and detected independently with very few samples. A formal hypothesis test can then be used to determine whether specific patterns are present. This approach enables one to determine the sensitivity of a sample plan to patterns of interest and the minimum number of measurements necessary to adequately monitor the process.

  6. Wafer characteristics via reflectometry and wafer processing apparatus and method

    DOEpatents

    Sopori, Bhushan L. (Denver, CO)

    2007-07-03

    An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

  7. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    SciTech Connect

    Bajikar, Sateesh S.; DeCarlo, Francesco; Song, Joshua J.

    1998-05-22

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized from pyromellitic anhydride and oxydianiline (PMDA-ODA).

  8. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    SciTech Connect

    Bajikar, Sateesh S.; De Carlo, Francesco; Song, Joshua J.

    2004-01-27

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  9. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    DOEpatents

    Bajikar, Sateesh S. (San Jose, CA); De Carlo, Francesco (Darien, IL); Song, Joshua J. (Naperville, IL)

    2001-01-01

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  10. BCB wafer bonding for microfluidics

    NASA Astrophysics Data System (ADS)

    Hwang, Taejoo; Popa, Dan; Sin, Jeongsik; Stephanou, Harry E.; Leonard, Eric M.

    2004-01-01

    In this paper we show that BCB wafer bonding, combined with deep-reactive-ion-etching (DRIE) for silicon, and HF etching for FOTURAN glass are viable methods to fabricate three-dimensional microfluidics. The BCB film is patterned by dry-etching technique with a photoresist mask and the target wafer is then bulk-micromachined together with the BCB mask. The two micromachined wafers are then bonded together under vacuum or nitrogen gas environment, at low temperature. Silicon-glass, silicon-silicon and glass-glass are all possible bonding pairs using thermocompressive bonding with BCB. It was found that hard-cured BCB bonding is more suitable for microfluidic channel fabrications than soft-cured BCB bonding, due to adhesive overflows in microfluidic channels and delamination during wet etching.

  11. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  12. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R. (Berkeley, CA)

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  13. Wafer-level optics enables low cost camera phones

    NASA Astrophysics Data System (ADS)

    Dagan, Yehudit

    2009-02-01

    To meet market demand and enable the proliferation of camera phones for developing countries, manufacturers must be able to meet requirements for camera modules that are reduced in size and cost. Conventional camera-module technology is heading towards an asymptote, where the optics no longer scale with the required size, performance, and cost. Using wafer-level techniques and reflow compatible materials to manufacture the optics together with wafer-level chip scale packaging (WLCSP) of image sensors enables manufacturing of smaller-size, lower-cost, reflow-compatible camera modules. Focusing on VGA resolution, this paper will present a comparison between optical modules that were built using conventional technology and wafer-level technology.

  14. Allowable silicon wafer thickness versus diameter for ingot rotation ID wafering

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1982-01-01

    Inner diameter (ID) wafering of ingot rotation reduce the ID saw blade diameter was investigated. The blade thickness can be reduced, resulting in minimal kerf loss. However, significant breakage of wafers occurs during the rotation wafering as the wafer thickness decreases. Fracture mechanics was used to develop an equation relating wafer thickness, diameter and fracture behavior at the point of fracture by using a model of a wafer, supported by a center column and subjected to a cantilever force. It is indicated that the minimum allowable wafer thickness does not increase appreciably with increasing wafer diameter and that fracture through the thickness rather than through the center supporting column limits the minimum allowable wafer thickness. It is suggested that the minimum allowable wafer thickness can be reduced by using a vacuum chuck on the wafer surface to enhance cleavage fracture of the center core and by using 111 ingots.

  15. Investigation of sidewall cracking in PMMA LIGA structures

    NASA Astrophysics Data System (ADS)

    Hunter, L. L.; Skala, D. M.; Levey, B. S.

    2006-07-01

    During x-ray exposure in the LIGA process, the polymethylmethacrylate (PMMA) photoresist undergoes chain scission, which reduces the molecular weight of the exposed materials. Under some exposure and development conditions, sidewall cracking is observed on the PMMA sidewall, creating surface texture that is undesirable. In this research, exposed and developed PMMA sidewalls were examined for evidence of crack formation using optical profilometry. PMMA thickness, exposure dose and delay time between the end of exposure and beginning of development were varied. Our analysis of samples, with three different radiation doses and four different delay times from the end of exposure to the beginning of development, indicate that the first occurrence of cracking and the extent of cracking are affected by both the dose and the development delay time. This work includes the examination of the depth of cracks into the PMMA, distance between cracks, the width of cracks and the relationship between crack occurrence and dose profile. An empirical predictive model to correlate the delay time to the observance of sidewall cracking based on the deposited dose is presented. This information has direct implication for predicting processing conditions and logistics for LIGA fabricated parts.

  16. Characterization of Sidewall and Planar Surfaces of Electroformed LIGA Parts

    SciTech Connect

    PRASAD,SOMURI V.; HALL,AARON C.; DUGGER,MICHAEL T.

    2000-10-01

    The nature of surfaces and the way they interact with each other during sliding contact can have a direct bearing on the performance of a microelectromechanical (MEMS) device. Therefore, a study was undertaken to characterize the surfaces of LIGA fabricated Ni and Cu components. Sidewall and planar surfaces were examined by scanning electron microscopy (SEM) and atomic force microscopy (AFM). Surface roughness was quantified using the AFM. Post-processing (e.g. lapping, removal of polymer film) can profoundly influence the morphology of LIGA components. Edge rounding and smearing of ductile materials during lapping can result in undesirable sidewall morphologies. By judicious selection of AFM scan sizes, the native roughness ({approximately}10 nm RMS) can be distinguished from that arising due to post processing, e.g. scratches, debris, polymer films. While certain processing effects on morphology such as those due to lapping or release etch can be controlled, the true side wall morphology appears to be governed by the morphology of the polymer mold or by the electroforming process itself, and may be much less amenable to modification.

  17. NMR Study on Defect Structure in ?-LiGa

    NASA Astrophysics Data System (ADS)

    Nishioka, Daisuke; Nakamura, Koichi; Michihiro, Yoshitaka; Ohno, Takashi; Kanashiro, Tatsuo; Kuriyama, Kazuo; Hamanaka, Hiromi; Yahagi, Masahito

    2008-03-01

    The mechanism of superionic conductivity in ?-LiGa has been investigated by 7Li and 71Ga NMR spin-lattice relaxation rates 1/T1 in Li excess 50.0 at. %, Li deficient 44.0 and 47.0 at. % samples. The activation energies of Li+ ionic diffusions through free Li vacancy VLi and through bound Li vacancy trapped by antisite LiGa have been estimated to be 0.13 and 0.064 eV by applying Bloembergen-Purcell-Pound (BPP) type equation to 1/T1 in 50.0 at. % Li sample. In Li deficient samples, the same activation energy, 0.11-0.13 eV, for Li+ ionic diffusion through free VLi has been obtained at high temperatures, and evidence for the ordering of VLi has been also detected by anomalies at 200-240 K in the temperature dependence of 1/T1 for 7Li. However, the motional narrowing observed in 7Li NMR line width above 110-130 K indicates that disorder in VLi can still remain even below its ordering temperature in 44.0 and 47.0 at. % Li samples.

  18. GEM-type detectors using LIGA and etchable glass technologies

    SciTech Connect

    Ahn, S.K.; Kim, J.G.; Perez-Mendez, V.; Chang, S.; Jackson, K.H.; Kadyk, J.A.; Wenzel, W.A.; Cho, G.

    2001-11-02

    Gas electron multipliers (GEMS) have been made by a deep X-ray lithography technique (LIGA process) using synchrotron radiation on polymethylmethacrylate (PMMA) and by UV processes using a UV etchable glass. Gain, stability and rate capability for these detectors are described.The LIGA detectors described consist of PMMA sheets of various thicknesses, 125mm to 350mm, and have 150mm x 150mm square holes spaced with a pitch of 300mm. Thin copper electrodes are plated on the top and bottom surfaces using a Damascene method, followed by electroless plating of the copper onto a palladium-tin base layer. For various thicknesses of PMMA measurements have been made of absolute gain vs. voltage, time stability of gain, and rate capability. The operating gas mixture was usually Ar/CO2 (70/30) gas, but some tests were also done using P10 gas. We also made GEM-like detectors using the UV etchable glass called Foturan, patterned by exposure to UV light and subsequent etching. A few measurements using these detectors will be reported, including avalanche gain and time stability.

  19. Manufacturing microcomponents for optical information technology using the LIGA technique

    NASA Astrophysics Data System (ADS)

    Bauer, Hans-Dieter; Ehrfeld, Wolfgang; Hossfeld, Jens; Paatzsch, Thomas

    1999-09-01

    Recently, splices and connectors for fibers ribbons, optical cross connects and especially planar waveguide devices have been fabricated via LIGA in combination with precision engineering techniques. LIGA combines high precision and mass production capability, necessary for products designed for applications in the telecom and datacom market. In this presentation the fabrication of three-level molding and embossing tools is presented, which have been used for the manufacturing of waveguide prestructures consisting of waveguide channels and bier-to-waveguide coupling grooves. The precision of the tools is better than 1 micrometers in all directions, which allows for simple passive pigtailing. A first product, a precision of the tool is better than 1 micrometers in all directions, which allows for simple passive pigtailing. A first product, sixfold array of 4 X 4 multimode star couplers has been realized. The molding behavior of PMMA and COC material has been tested and compared. Production and assembly was tested by fabricating a series of 300 star couplers. The average insertion los has been found better than 9dB, the uniformity better than 3dB, both measured at 830nm. THe device is designed for application in optical backplanes for high-speed computers.

  20. Smoother Scribing of Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Danyluk, S.

    1986-01-01

    Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

  1. Characterization of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  2. LIGA-based microsystem manufacturing:the electrochemistry of through-mold depostion and material properties.

    SciTech Connect

    Kelly, James J.; Goods, Steven Howard

    2005-06-01

    The report presented below is to appear in ''Electrochemistry at the Nanoscale'', Patrik Schmuki, Ed. Springer-Verlag, (ca. 2005). The history of the LIGA process, used for fabricating dimensional precise structures for microsystem applications, is briefly reviewed, as are the basic elements of the technology. The principal focus however, is on the unique aspects of the electrochemistry of LIGA through-mask metal deposition and the generation of the fine and uniform microstructures necessary to ensure proper functionality of LIGA components. We draw from both previously published work by external researchers in the field as well as from published and unpublished studies from within Sandia.

  3. NREL Core Program; Session: Wafer Silicon (Presentation)

    SciTech Connect

    Wang, Q.

    2008-04-01

    This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

  4. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  5. Temperature Dependent Electrical Properties of PZT Wafer

    NASA Astrophysics Data System (ADS)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-01-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  6. Deposition uniformity inspection in IC wafer surface

    NASA Astrophysics Data System (ADS)

    Li, W. C.; Lin, Y. T.; Jeng, J. J.; Chang, C. L.

    2014-03-01

    This paper focuses on the task of automatic visual inspection of color uniformity on the surface of integrated circuits (IC) wafers arising from the layering process. The oxide thickness uniformity within a given wafer with a desired target thickness is of great importance for modern semiconductor circuits with small oxide thickness. The non-uniform chemical vapor deposition (CVD) on a wafer surface will proceed to fail testing in Wafer Acceptance Test (WAT). Early detection of non-uniform deposition in a wafer surface can reduce material waste and improve production yields. The fastest and most low-priced inspection method is a machine vision-based inspection system. In this paper, the proposed visual inspection system is based on the color representations which were reflected from wafer surface. The regions of non-uniform deposition present different colors from the uniform background in a wafer surface. The proposed inspection technique first learns the color data via color space transformation from uniform deposition of normal wafer surfaces. The individual small region statistical comparison scheme then proceeds to the testing wafers. Experimental results show that the proposed method can effectively detect the non-uniform deposition regions on the wafer surface. The inspection time of the deposited wafers is quite compatible with the atmospheric pressure CVD time.

  7. Fabrication of Spiral Micro-Coil Utilizing LIGA Process

    NASA Astrophysics Data System (ADS)

    Shimada, Osamu; Kusumi, Shinji; Mekaru, Harutaka; Sato, Noriaki; Shimizu, Masami; Yamashita, Michiru; Hattori, Tadashi

    We developed a method for fabricating a three-dimensional spiral micro-inductor with high inductance using the LIGA process. The spiral inductor created had a diameter of 0.5mm, and a length of 1mm. The width of the spiral line was 10m, the pitch was 20m, and the number of turns was 15. It was made of plated copper. The master was a brass round bar coated with PMMA resist. Deep X-ray lithography was employed to fabricate a master for a metallic mold at the NewSUBARU synchrotron radiation facility, University of Hyogo. The inductor core was made of resin by injection molding. It has a spiral micro flute on the surface. We chose the worm injection molding technique in order to avoid the parting line across the spiral line. The worm injection molding was the method─for demolding the work such as that used in loosening a screw.

  8. Two-dimensional modeling of nickel electrodeposition in LIGA microfabrication.

    SciTech Connect

    Evans, Gregory Herbert; Chen, Ken Shuang

    2003-07-01

    Two-dimensional processes of nickel electrodeposition in LIGA microfabrication were modeled using the finite-element method and a fully coupled implicit solution scheme via Newtons technique. Species concentrations, electrolyte potential, flow field, and positions of the moving deposition surfaces were computed by solving the species-mass, charge, and momentum conservation equations as well as pseudo-solid mesh-motion equations that employ an arbitrary Lagrangian-Eulerian (ALE) formulation. Coupling this ALE approach with repeated re-meshing and re-mapping makes it possible to track the entire transient deposition processes from start of deposition until the trenches are filled, thus enabling the computation of local current densities that influence the microstructure and functional/mechanical properties of the deposit.

  9. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  10. Technology for integrated circuit micropackages for neural interfaces, based on gold-silicon wafer bonding

    NASA Astrophysics Data System (ADS)

    Saeidi, N.; Schuettler, M.; Demosthenous, A.; Donaldson, N.

    2013-07-01

    Progress in the development of active neural interface devices requires a very compact method for protecting integrated circuits (ICs). In this paper, a method of forming micropackages is described in detail. The active areas of the chips are sealed in gas-filled cavities of the cap wafer in a wafer-bonding process using Au-Si eutectic. We describe the simple additions to the design of the IC, the post-processing of the active wafer and the required features of the cap wafer. The bonds, which were made at pressure and temperature levels within the range of the tolerance of complementary metal-oxide-semiconductor ICs, are strong enough to meet MIL STD 883G, Method 2019.8 (shear force test). We show results that suggest a method for wafer-scale gross leak testing using FTIR. This micropackaging method requires no special fabrication process and is based on using IC compatible or conventional fabrication steps.

  11. Accurate surface profilometry of ultrathin wafers

    NASA Astrophysics Data System (ADS)

    Weeks, A. E.; Litwin, D.; Galas, J.; Surma, B.; Piatkowski, B.; MacLaren, D. A.; Allison, W.

    2007-09-01

    Geometric characterization of 50 mm diameter, 50 m thick single-crystal Si(1 1 1) wafers has been performed using complementary methods: industry-standard capacitance measurements of warp and total thickness variation (TTV), and a technique we term scanned chromatic confocal profilometry (SCCP). We compare the measurements made by the two techniques and demonstrate the limitations of capacitance measurements when applied to ultrathin wafers. The two-dimensional SCCP measurements are shown to enhance the description of wafer thickness variations beyond that generated by the standard test method. We discuss a Fourier transform-based analysis and show it to be useful in wafer quality assessment. Adding a summary of spatial frequencies in a wafer's thickness map to the conventional measures of warp and TTV provides a more complete summary of the salient features of a wafer's geometry.

  12. Wafer Resection of the Distal Ulna.

    PubMed

    Griska, Adam; Feldon, Paul

    2015-11-01

    The wafer procedure is an effective treatment for ulnar impaction syndrome, which decompresses the ulnocarpal junction through a limited open or arthroscopic approach. In comparison with other common decompressive procedures, the wafer procedure does not require bone healing or internal fixation and also provides excellent exposure of the proximal surface of the triangular fibrocartilage complex. Results of the wafer procedure have been good and few complications have been reported. PMID:26518323

  13. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  14. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    DOEpatents

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  15. Stress Voiding During Wafer Processing

    SciTech Connect

    Yost, F.G.

    1999-03-01

    Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

  16. Wafer level reliability for high-performance VLSI design

    NASA Technical Reports Server (NTRS)

    Root, Bryan J.; Seefeldt, James D.

    1987-01-01

    As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

  17. LIGA-fabricated compact mm-wave linear accelerator cavities.

    SciTech Connect

    Song, J.J.; Bajikar, S.S.; DeCarlo, F.; Kang, Y.W.; Kustom, R.L.; Mancini, D.C.; Nassiri, A.; Lai, B.; Feinerman, A.D.; White, V.

    1998-03-23

    Millimeter-wave rf cavities for use in linear accelerators, free-electron lasers, and mm-wave undulatory are under development at Argonne National Laboratory. Typical cavity dimensions are in the 1000 mm range, and the overall length of the accelerator structure, which consists of 30-100 cavities, is about 50-100 mm. An accuracy of 0.2% in the cavity dimensions is necessary in order to achieve a high Q-factor of the cavity. To achieve this these structures are being fabricated using deep X-ray lithography, electroforming, and assembly (LIGA). The first prototype cavity structures are designed for 108 GHz and 2p/3-mode operation. Input and output couplers are integrated with the cavity structures. The cavities are fabricated on copper substrates by electroforming copper into 1-mm-thick PMMA resists patterned by deep x-ray lithography and polishing the copper down to the desired thickness. These are fabricated separately and subsequently assembled with precision spacing and alignment using microspheres, optical fibers, or microfabricated spacers/alignment pieces. Details of the fabrication process, alignment, and assembly work are presented in here.

  18. An aluminum resist substrate for microfabrication by LIGA.

    SciTech Connect

    Kelly, James J.; Boehme, Dale R.; Hauck, Cheryl A.; Yang, Chu-Yeu Peter; Hunter, Luke L.; Griffiths, Stewart K.; McLean, Dorrance E.; Aigeldinger, Georg; Hekmaty, Michelle A.; Hachman, John T.; Losey, Matthew W.; Skala, Dawn M.; Korellis, John S.; Friedmann, Thomas Aquinas; Yang, Nancy Y. C.; Lu, Wei-Yang

    2005-04-01

    Resist substrates used in the LIGA process must provide high initial bond strength between the substrate and resist, little degradation of the bond strength during x-ray exposure, acceptable undercut rates during development, and a surface enabling good electrodeposition of metals. Additionally, they should produce little fluorescence radiation and give small secondary doses in bright regions of the resist at the substrate interface. To develop a new substrate satisfying all these requirements, we have investigated secondary resist doses due to electrons and fluorescence, resist adhesion before exposure, loss of fine features during extended development, and the nucleation and adhesion of electrodeposits for various substrate materials. The result of these studies is a new anodized aluminum substrate and accompanying methods for resist bonding and electrodeposition. We demonstrate successful use of this substrate through all process steps and establish its capabilities via the fabrication of isolated resist features down to 6 {micro}m, feature aspect ratios up to 280 and electroformed nickel structures at heights of 190 to 1400 {micro}m. The minimum mask absorber thickness required for this new substrate ranges from 7 to 15 {micro}m depending on the resist thickness.

  19. Structural and compositional characterization of MOVPE GaN thin films transferred from sapphire to glass substrates using chemical lift-off and room temperature direct wafer bonding and GaN wafer scale MOVPE growth on ZnO-buffered sapphire

    NASA Astrophysics Data System (ADS)

    Gautier, S.; Moudakir, T.; Patriarche, G.; Rogers, D. J.; Sandana, V. E.; Hosseini Téherani, F.; Bove, P.; El Gmili, Y.; Pantzas, K.; Sundaram, Suresh; Troadec, D.; Voss, P. L.; Razeghi, M.; Ougazzaden, A.

    2013-05-01

    GaN thin films were grown on ZnO/c-Al2O3 with excellent uniformity over 2 in. diameter wafers using a low temperature/pressure MOVPE process with N2 as a carrier and dimethylhydrazine as an N source. 5 mm×5 mm sections of similar GaN layers were direct-fusion-bonded onto soda lime glass substrates after chemical lift-off from the sapphire substrates. X-Ray Diffraction, Scanning Electron Microscopy and Transmission Electron Microscopy confirmed the bonding of crack-free wurtzite GaN films onto a glass substrate with a very good quality of interface, i.e. continuous/uniform adherence and absence of voids or particle inclusions. Using this approach, (In) GaN based devices can be lifted-off expensive single crystal substrates and bonded onto supports with a better cost-performance profile. Moreover, the approach offers the possibility of reclaiming the expensive sapphire substrate so it can be utilized again for growth.

  20. Mechanics of the pad-abrasive-wafer contact in chemical mechanical polishing

    NASA Astrophysics Data System (ADS)

    Bozkaya, Dincer

    2009-12-01

    In chemical mechanical polishing (CMP), a rigid wafer is forced on a rough, elastomeric polishing pad, while a slurry containing abrasive particles flows through the interface. The applied pressure on the wafer is carried partially by the 2-body pad-wafer contact (direct contact) and partially by the 3-body contact of pad, wafer and abrasive particles ( particle contact). The fraction of the applied pressure carried by particle contacts is an important factor affecting the material removal rate (MRR) as the majority of the material is removed by the abrasive particles trapped between the pad asperities and the wafer. In this thesis, the contact of a rough, deformable pad and a smooth, rigid wafer in the presence of rigid abrasive particles at the contact interface is investigated by using contact mechanics and finite element (FE) modeling. The interactions between the pad, the wafer and the abrasive particles are modeled at different scales of contact, starting from particle level interactions, and gradually expanding the contact scale to the multi-asperity contact of pad and wafer. The effect of surface forces consisting of van der Waals and electrical double layer forces acting between the wafer and the abrasive particles are also investigated in this work. The wear rate due to each abrasive particle is calculated based on the wafer-abrasive particle contact force, and by considering adhesive and abrasive wear mechanisms. A passivated layer on the wafer surface with a hardness and thickness determined by the chemical effects is modeled, in order to characterize the effect of chemical reactions between slurry and wafer on the MRR. The model provides accurate predictions for the MRR as a function of pad related parameters; pad elastic modulus, pad porosity and pad topography, particle related parameters; particle size and concentration, and slurry related parameters; slurry pH, thickness and hardness of the passivated surface layer of wafer. A good qualitative agreement between the model and the experiments is found for the variation of the MRR with respect to these parameters. Furthermore, closed form equations are derived in order to optimize the CMP parameters for maximizing the material removal efficiency, which is a measure of the ability of pad to transmit the applied pressure on the abrasive particles. The optimization of the CMP parameters described in this thesis may be particularly important for the low-pressure CMP of ultra-low-k (ULK) dielectric materials, where it is difficult to achieve acceptable MRR without compromising the porous structure of ULK materials.

  1. Preparation and Characterization of PZT Wafers

    NASA Astrophysics Data System (ADS)

    Seal, A.; Rao, B. S. S. Chandra; Kamath, S. V.; Sen, A.; Maiti, H. S.

    2008-07-01

    Piezoelectric materials have recently attracted a lot of attention for ultrasonic structural health monitoring (shm) in aerospace, defence and civilian sectors, where they can act as both actuators and sensors. Incidentally, piezoelectric materials in the form of wafers (pwas-piezoelectric wafer active sensor, approx. 5-10 mm square and 0.2-0.3 mm thickness) are inexpensive, non intrusive and non-resonant wide band devices that can be surface-mounted on existing structures, inserted between the layers of lap joints or embedded inside composite materials. The material of choice for piezoelectric wafers is lead zirconate titanate (PZT) of composition close to morphotropic phase boundary [pb(zr0.52 ti0.48)o3]. However, an excess pbo is normally added to pzt as a densification aid and also to make up for the lead loss during high temperature sintering. Hence, it is of paramount importance to know how the shift of the lead content from the morphotropic composition affects the piezoelectric and mechanical properties of the sintered wafers, keeping in view the importance of mechanical properties of wafers in shm. In the present study, we observed that with the increase in the lead content of the sintered wafers, the dielectric and piezoelectric constants decreased. However, the elastic modulus, hardness and fracture toughness of the wafers increased with increasing lead content in the composition. Hence, the lead content in the sintered wafers should be optimized to get acceptable piezoelectric and mechanical

  2. Formation and combustion characteristics of elephantgrass and energycane wafers

    NASA Astrophysics Data System (ADS)

    Mofleh, Mohamad I.

    Elephantgrass (Pennisetum purpureum Schum.) and energycane (Saccharum Spp.) are two cane type grasses. These are tall-growing perennial bunchgrasses that produce long hardened stems and grow in the tropics and subtropics. Traditionally, they have been used for forage and, in some regions, have been randomly burned on fields or disposed of uselessly. However, these plants have high dry matter yield and, thus, are excellent candidates as energy crops. Elephantgrass and energycane have been used for direct combustion in their loose form in large-scale applications. Several problems, many of which were attributed to their low bulk density, were encountered with using the materials. Consequently, this project was initiated to investigate the formation and combustion characteristics of the two materials in the form of small compact units called wafers. A hydraulic press that applied axial stresses on the material in four different dies was used. A load cell and a displacement transducer were utilized to measure the stresses and material detection. Wafer quality was evaluated using a tumbler built according to the American Society of Agricultural Engineers standards. In addition, a small stove was built to test wafer combustion. Thermocouples were used to measure temperatures during combustion. All the data gathered was transferred to a computer using a data acquisition system. It was found that the stress-deformation and stress-density relationships of elephantgrass and energycane were of exponential nature. Compaction energy required, which was calculated from the area under the force-deformation curves, ranged from 0.1 to 0.3% of their energy content. It was also found that wafer quality (durability) was mainly a function of wafer size and its final (relaxed) density in addition to material stem-to-leaf ratio and its crude protein content. Wafers possessed poor ignition quality but once ignited, they burned satisfactorily. The results indicated that sufficient and uniform combustion air distribution and a stove lining were critical factors in burning these materials. Further, the findings revealed that it may not be recommended to use elephantgrass or energycane in large-scale applications due to their high slagging index. Nonetheless, using them in small-scale applications may be possible. Elephantgrass was generally a better candidate for such an application.

  3. Methane production using resin-wafer electrodeionization

    SciTech Connect

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  4. A comparison of wafer resistivity probing tools

    NASA Astrophysics Data System (ADS)

    Larson, L. A.

    1989-02-01

    A comparative study of four-point probing systems has been carried out by measuring a large group of wafers. The wafers were produced by multiple donors for a Greater Silicon Valley Implant Users' Group round-robin experiment on dosing accuracy. Three implant conditions were represented in 139 wafers. These wafers were all measured by five vendors in this study. This data has been analyzed as scatterplots by paired vendors which has produced several interesting results. The general spread between the database means runs about 1% for systems using configuration switching. Single configuration measurements were somewhat worse. It is noted that each particular system had trouble probing different wafers. This implies that the method of probing is important even for the routine measurement of "easy" layers.

  5. A MEMS-Based Micro Biopsy Actuator for the Capsular Endoscope Using LiGA Process

    NASA Astrophysics Data System (ADS)

    Park, Sunkil; Koo, Kyo-In; Kim, Gil-Sub; Bang, Seoung Min; Song, Si Young; Chu, Chong Nam; Jeon, Doyoung; Cho, Dongil ``Dan''

    2007-01-01

    This paper presents a LiGA (German acronym for LIthografie, Galvanoformung, Abformung) based micro biopsy actuator for the capsular endoscope. The proposed fabricated actuator aims to extract sample tissues inside small gastric intestines, that cannot be reached by conventional biopsy. The actuator size is 10 mm in diameter and 1.8 mm in length. The mechanism is of a slider-crank type. The actuator consists of trigger, rotational module, and micro biopsy tool. The core components are fabricated using the LiGA process, for overcoming the limitations in accuracy of conventional precision machining.

  6. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  7. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  8. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Rhee, S. S.

    1979-01-01

    Several aspects of silicon wafer surface texturizing were studied. A low cost cleaning method that utilizes recycled Freon in an ultrasonic vapor degreaser to remove organic and inorganic contaminants from the surface of silicon wafers as received from silicon suppliers was investigated. The use of clean dry air and high throughout wafer batch drying techniques was shown to lower the cost of wafer drying. A two stage texturizing process was examined for suitability in large scale production. Also, an in-depth gettering study with the two stage texturizing process was performed for the enhancement of solar cell efficiency, minimization of current versus voltage curve dispersion, and improvement in process reproducibility. The 10% efficiency improvement goal was exceeded for the near term implementation of flat plate photovoltaic cost reduction.

  9. Forming electrical interconnections through semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Anthony, T. R.

    1981-01-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  10. Subsea template leveling wafer and leveling method

    SciTech Connect

    Bunnell, R.L.; Miller, H.W.; Padilla, J.R

    1989-05-16

    This patent describes a monopile supported subsea hydrocarbon production platform having a monopile driven into the sea bottom with a non-level ring girder secured thereto and a machinery supporting template supported by the ring girder. The improvement consists of a leveling wafer between the ring girder and the template, the wafer comprising upper and lower wedge portions, each portion having two non-parallel principal surfaces, the lower principal surface of the upper wedge portion being in face-to-face contact with the upper principal surface of the lower wedge portion so as to form a composite wafer having a taper suitable to level the non-level ring girder, the taper being adjustable by rotating one wedge portion in relation to the other; means between the bottom surface of the template and the upper surface of the upper wedge portion for securing rotational alignment thereof when the template is placed on the leveling wafer.

  11. Modelling deformation and fracture in confectionery wafers

    SciTech Connect

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  12. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  13. Image quality and wafer level optics

    NASA Astrophysics Data System (ADS)

    Dagan, Y.; Humpston, G.

    2010-05-01

    Increasing demand from consumers to integrate camera modules into electronic devices, such as cell phones, has driven the cost of camera modules down very rapidly. Now that most cell phones include at least one camera, consumers are starting to ask for better image quality - without compromising on the cost. Wafer level optics has emerged over the past few years as an innovative technology enabling simultaneous manufacturing of thousands of lenses, at the wafer level. Using reflow-compatible materials to manufacture these lenses permits a reduction in the cost and size of camera module, thus answering the market demand for lowering the cost. But what about image quality? The author will present image quality analysis that was conducted for both VGA and megapixel camera resolutions. Comparison between conventional camera modules and wafer level camera modules shows wafer level technology brings equivalent, if not better, image quality performance compared to conventional camera modules.

  14. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  15. Total x-ray power measurements in the Sandia LIGA program.

    SciTech Connect

    Malinowski, Michael E. (Sandia National Laboratories, Livermore, CA); Ting, Aili (Sandia National Laboratories, Livermore, CA)

    2005-08-01

    Total X-ray power measurements using aluminum block calorimetry and other techniques were made at LIGA X-ray scanner synchrotron beamlines located at both the Advanced Light Source (ALS) and the Advanced Photon Source (APS). This block calorimetry work was initially performed on the LIGA beamline 3.3.1 of the ALS to provide experimental checks of predictions of the LEX-D (LIGA Exposure- Development) code for LIGA X-ray exposures, version 7.56, the version of the code in use at the time calorimetry was done. These experiments showed that it was necessary to use bend magnet field strengths and electron storage ring energies different from the default values originally in the code in order to obtain good agreement between experiment and theory. The results indicated that agreement between LEX-D predictions and experiment could be as good as 5% only if (1) more accurate values of the ring energies, (2) local values of the magnet field at the beamline source point, and (3) the NIST database for X-ray/materials interactions were used as code inputs. These local magnetic field value and accurate ring energies, together with NIST database, are now defaults in the newest release of LEX-D, version 7.61. Three dimensional simulations of the temperature distributions in the aluminum calorimeter block for a typical ALS power measurement were made with the ABAQUS code and found to be in good agreement with the experimental temperature data. As an application of the block calorimetry technique, the X-ray power exiting the mirror in place at a LIGA scanner located at the APS beamline 10 BM was measured with a calorimeter similar to the one used at the ALS. The overall results at the APS demonstrated the utility of calorimetry in helping to characterize the total X-ray power in LIGA beamlines. In addition to the block calorimetry work at the ALS and APS, a preliminary comparison of the use of heat flux sensors, photodiodes and modified beam calorimeters as total X-ray power monitors was made at the ALS, beamline 3.3.1. This work showed that a modification of a commercially available, heat flux sensor could result in a simple, direct reading beam power meter that could be a useful for monitoring total X-ray power in Sandia's LIGA exposure stations at the ALS, APS and Stanford Synchrotron Radiation Laboratory (SSRL).

  16. Analyzes Data from Semiconductor Wafers

    Energy Science and Technology Software Center (ESTSC)

    2002-07-23

    This program analyzes reflectance data from semiconductor wafers taken during the deposition or evolution of a thin film, typically via chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). It is used to determine the growth rate and optical constants of the deposited thin films using a virtual interface concept. Growth rates and optical constants of multiple-layer structures is possible by selecting appropriate sections in the reflectance vs time waveform. No prior information or estimatesmore » of growth rates and materials properties is required if an absolute reflectance waveform is used. If the optical constants of a thin film are known, then the growth rate may be extracted from a relative reflectance data set. The analysis is valid for either s or p polarized light at any incidence angle and wavelength. The analysis package is contained within an easy-to-use graphical user interface. The program is based on the algorighm described in the following two publications: W.G. Breiland and K.P. Killen, J. Appl. Phys. 78 (1995) 6726, and W. G. Breiland, H.Q. Hou, B.E. Hammons, and J.F. Klem, Proc. XXVIII SOTAPOCS Symp. Electrochem. Soc. San Diego, May 3-8, 1998. It relies on the fact that any multiple-layer system has a reflectance spectrum that is mathematically equivalent to a single-layer thin film on a virtual substrate. The program fits the thin film reflectance with five adjustable parameters: 1) growth rate, 2) real part of complex refractive index, 3) imaginary part of refractive index, 4) amplitude of virtual interface reflectance, 5) phase of virtual interface reflectance.« less

  17. The Imaging Properties of a Silicon Wafer X-Ray Telescope

    NASA Technical Reports Server (NTRS)

    Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

    1994-01-01

    Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

  18. Metal-assisted homogeneous etching of single crystal silicon: A novel approach to obtain an ultra-thin silicon wafer

    NASA Astrophysics Data System (ADS)

    Bai, Fan; Li, Meicheng; Song, Dandan; Yu, Hang; Jiang, Bing; Li, Yingfeng

    2013-05-01

    Homogeneous etching of silicon is achieved through one-step metal-assisted chemical etching (MACE), which offers a simple route to obtain the ultra-thin silicon wafer with thickness below 50 ?m. The surface of the ultra-thin silicon wafer obtained by this method is smooth at the nanometer scale, and its surface roughness is around 10 nm. The homogenous etching mechanism is discussed in terms of the hole injection principle. It's found that the introduction of a high concentration of H2O2 facilitates the uniform distribution of the holes injected on the silicon surface, causing the homogeneous etching of the silicon. Meanwhile, the thinning is uniform across a large wafer area, and ultra thin silicon wafers up to 4 in. in diameter were obtained. Furthermore, any thickness of silicon wafer within 30-180 ?m can be obtained by modulating the etching process accurately.

  19. Porous solid ion exchange wafer for immobilizing biomolecules

    DOEpatents

    Arora, Michelle B. (Woodridge, IL); Hestekin, Jamie A. (Morton Grove, IL); Lin, YuPo J. (Naperville, IL); St. Martin, Edward J. (Libertyville, IL); Snyder, Seth W. (Lincolnwood, IL)

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  20. Wafer and wafer-lug check valves, fourth edition, May 1991

    SciTech Connect

    Not Available

    1991-01-01

    This book covers cast iron, ductile iron, carbon steel alloy steel, and nickel-alloy wafer and wafer-lug, single and dual plate check valves with dimensions that permit installation between flanges complying with ASME B16.1, B16.5, or B16.42; MSS SP-44, or API Standard 605. Such values may be used in petroleum refineries.

  1. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020from $0.15 per kilowatt hour to less than $0.07. 1366s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with todays state-of-the-art technologies. 1366s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366s technology, the cost of silicon wafers could be reduced by 80%.

  2. Integrating III-V compound semiconductors with silicon using wafer bonding

    NASA Astrophysics Data System (ADS)

    Zhou, Yucai

    2000-12-01

    From Main Street to Wall Street, everyone has felt the effects caused by the Internet revolution. The Internet has created a new economy in the New Information Age and has brought significant changes in both business and personal life. This revolution has placed strong demands for higher bandwidth and higher computing speed due to high data traffic on today's information highway. In order to alleviate this problem, growing interconnection bottlenecks in digital designs have to be solved. The most feasible and practical way is to replace the conventional electrical interconnect with an optical interconnect. Since silicon does not have the optical properties necessary to accommodate these optical interconnect requirements, III-V based devices, most of which are GaAs-based or InP-based, must be intimately interconnected with the Si circuit at chip level. This monolithic integration technology enables the development of both intrachip and interchip optical connectors to take advantage of the enormous bandwidth provided by both high-performance very-large-scale integrated (VLSI) circuits and allied fiber and free-space optical technologies. However, lattice mismatch and thermal expansion mismatches between III-V materials and Si create enormous challenges for developing a feasible technology to tackle this problem. Among all the available approaches today, wafer bonding distinguishes itself as the most promising technology for integration due to its ability to overcome the constraints of both lattice constant mismatch and thermal expansion coefficient differences and even strain due to the crystal orientation. We present our development of wafer bonding technology for integrating III-V with Si in my dissertation. First, the pick-and-place multiple-wafer bonding technology was introduced. Then we systematically studied the wafer bonding of GaAs and InP with Si. Both high temperature wafer fusion and low/room temperature (LT/RT) wafer bonding have been investigated for different applications. We also systematically studied the electrical properties of bonding interfaces for high temperature wafer fusion of GaAs/Si and InP/Si. Room temperature and low temperature wafer bonding technology has been invented primarily for bonding GaAs with Si due to larger thermal expansion coefficient mismatches. Finally, we showed the feasibility and practicality of our wafer bonding technologies by fabricating high performance devices. A high performance InP-based avalanche photodetector on Si was fabricated utilizing the high temperature wafer fusion of InP and Si. And a 0.85 μm GaAs-based vertical cavity surface emitting lasers (VCSELs) were fabricated by utilizing the low temperature wafer bonding of GaAs and Si.

  3. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  4. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  5. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  6. Laser furnace and method for zone refining of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

    1988-01-01

    A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

  7. Seasoning of Plasma Reactors: Feedback Control Strategies to Counter Wafer-to-Wafer Drifts

    NASA Astrophysics Data System (ADS)

    Agarwal, Ankur; Kushner, Mark J.

    2007-10-01

    Seasoning of plasma etching reactors is the deposition of materials on wafers and surfaces of the chamber resulting in process or wafer-to-wafer drift in etch rates or uniformity. Feedback control with in situ diagnostics is being investigated to combat this drift. The Virtual Plasma Equipment Model, an implementation of sensors, actuators and control algorithms in the HPEM, was used to investigate real-time and wafer-to-wafer control strategies. The model system is Ar/Cl2 etching of Si in an inductively coupled plasma reactor. The passivation of surfaces in contact with the plasma, including the deposition of etch products, change reactive sticking coefficients and produce etch blocks which in turn affect etch rate. Sputtering of dielectrics may introduce additional etch-block capable species. A PID controller was used to vary the bias voltage in response to an etch rate monitor to enable control of etch rate. We found that control is problematic at high bias voltages where the flux of etch products from the wafer is sufficiently large that plasma properties are affected and redeposition increases etch blocks on the wafer. Multiple sensors-and-actuators may be necessary when sputtering of dielectrics produce additional etch-block species.

  8. Fundamental aspects of particulate contamination of tungsten and thermal oxide wafers during chemical-mechanical polishing

    NASA Astrophysics Data System (ADS)

    Chilkunda, Raghunath R.

    Chemical-mechanical polishing (CMP) has emerged as a new processing technique for achieving a high degree of planarity (<10 mum) for submicron devices in very large scale integrated (VLSI) process technology. Metal as well dielectic films can be planarized using CMP. Polishing of tungsten (W) and interlayer dielectric (SiOsb2) films is carried out using alumina (Alsb2Osb3) based slurries which typically contain acids, complexing and oxidizing agents. One of the challenges of CMP is the effective removal of slurry particles (e.g., Alsb2Osb3) that are deposited on the wafer (e.g., W) surface during polishing. Control of particulate deposition during CMP as well as the development of post CMP cleaning techniques to remove deposited particles require an understanding of the surface and solution chemistry of the wafers and particles under polishing conditions. In this research, an attempt is made to develop an understanding of the importance of the electrostatic interactions in particle deposition using electrokinetic potential data, particle deposition results from small scale polishing experiments and calculated interaction energies between a particle and wafer surface. The electrokinetic potential of tungsten, thermal oxide (SiOsb2) wafers and alumina particles were measured as a function of solution chemistry. The measured electrokinetic potential data was used to calculate the interaction energy between an alumina particle and a wafer (e.g., W) surface using the well known DLVO (Derjaguin-Landau-Verwey-Overbeek) theory.

  9. Thermal Behavior of Large-Diameter Silicon Wafers during High-Temperature Rapid Thermal Processing in Single Wafer Furnace

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Yokoyama, Ichiro; Kang, Kitaek; Takahashi, Nobuaki

    2002-07-01

    Thermal behavior of 200-mm- and 300-mm-diameter Si (100) wafers during high-temperature rapid thermal processing (RTP) in a single wafer furnace (SWF) is investigated as a function of temperature, pressure, process time, wafer handling method and speed. Significant elastic wafer shape deformation was observed during wafer temperature ramp-up. Slip generation was frequently observed in wafers processed above 1050°C. Size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in reducing defect generation during RTP at the given process conditions. Highly reproducible, slip-free RTP results were achieved in 200-mm- and 300-mm-diameter Si (100) wafers processed at 1100°C by optimizing the wafer handling method and speed.

  10. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ?50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (? 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu-precipitates (upto 50 nm) compresses Si-lattice to facilitate Si-XII/III

  11. LigaSure meets endobronchial valve in a case of lung cancer with pneumoconiosis.

    PubMed

    Fiorelli, Alfonso; Accardo, Marina; Vicidomini, Giovanni; Santini, Mario

    2013-08-01

    Resection of lung cancer associated with pneumoconiosis may be difficult since fibrosis limits the exposure of hilum, and the use of stapler; yet, surgery may be complicated by persistent air leaks due to the underlying disease. In this setting, LigaSure was used to perform the tumor resection, and the postoperative treatment of air leaks in the same patient was treated with placement of endobronchial valves. PMID:25806247

  12. A Transdermal Drug Delivery System Based on LIGA Technology and Soft Lithography

    NASA Astrophysics Data System (ADS)

    Matteucci, Marco; Perennes, Frederic; Marmiroli, Benedetta; Di Fabrizio, Enzo

    2007-01-01

    This report presents a transdermal drug delivery system based on LIGA fabricated microparts. It is a portable device combining a magnetically actuated micro gear pump with a microneedle array. The fluidic behaviour of the system is analyzed in order to predict its performance according to the dimension of the microparts and then compared to experimental data. The manufacturing process of both micropump and microneedle array are described.

  13. Diamond-like nanocomposite coatings for LIGA-fabricated nickel alloy parts.

    SciTech Connect

    Prasad, Somuri V.; Scharf, Thomas W.

    2005-03-01

    A commercial plasma enhanced chemical vapor deposition (PECVD) technique with planetary substrate rotation was used to apply a thin (200-400 nm thick) conformal diamond-like carbon (DLC) coating (known as a diamond-like nanocomposite (DLN)) on LIGA fabricated Ni-Mn alloy parts. The PECVD technique is known to overcome the drawbacks associated with the line-of-sight nature of physical vapor deposition (PVD) and substrate heating inherent with traditional chemical vapor deposition (CVD). The purpose of the present study is to characterize the coverage, adhesion, and tribological (friction and wear) behavior of DLN coatings applied to planar and sidewall surfaces of small featured LIGA Ni-Mn fabricated parts, e.g. 280 {micro}m thick sidewalls. Friction and wear tests were performed in dry nitrogen, dry air, and air with 50% RH at Hertzian contact pressures ranging from 0.3 to 0.6 GPa. The friction coefficient of bare Ni-Mn alloy was determined to be 0.9. In contrast, low friction coefficients ({approx}0.02 in dry nitrogen and {approx}0.2 in 50% RH air) and minimal amount of wear were exhibited for the DLN coated LIGA Ni-Mn alloy parts and test coupons. This behavior was due to the ability of the coating to transfer to the rubbing counterface providing low interfacial shear at the sliding contact; resultantly, coating one surface was adequate for low friction and wear. In addition, a 30 nm thick titanium bond layer was determined to be necessary for good adhesion of DLN coating to Ni-Mn alloy substrates. Raman spectroscopy and cross-sectional SEM with energy dispersive x-ray analysis revealed that the DLN coatings deposited by the PECVD with planetary substrate rotation covered both the planar and sidewall surfaces of LIGA fabricated parts, as well as narrow holes of 300 {micro}m (0.012 inch) diameter.

  14. A LigA Three-Domain Region Protects Hamsters from Lethal Infection by Leptospira interrogans

    PubMed Central

    Coutinho, Mariana L.; Choy, Henry A.; Kelley, Melissa M.; Matsunaga, James; Babbitt, Jane T.; Lewis, Michael S.; Aleixo, Jose Antonio G.; Haake, David A.

    2011-01-01

    The leptospiral LigA protein consists of 13 bacterial immunoglobulin-like (Big) domains and is the only purified recombinant subunit vaccine that has been demonstrated to protect against lethal challenge by a clinical isolate of Leptospira interrogans in the hamster model of leptospirosis. We determined the minimum number and location of LigA domains required for immunoprotection. Immunization with domains 11 and 12 was found to be required but insufficient for protection. Inclusion of a third domain, either 10 or 13, was required for 100% survival after intraperitoneal challenge with Leptospira interrogans serovar Copenhageni strain Fiocruz L1-130. As in previous studies, survivors had renal colonization; here, we quantitated the leptospiral burden by qPCR to be 1.2103 to 8105 copies of leptospiral DNA per microgram of kidney DNA. Although renal histopathology in survivors revealed tubulointerstitial changes indicating an inflammatory response to the infection, blood chemistry analysis indicated that renal function was normal. These studies define the Big domains of LigA that account for its vaccine efficacy and highlight the need for additional strategies to achieve sterilizing immunity to protect the mammalian host from leptospiral infection and its consequences. PMID:22180800

  15. Effectiveness of the LigaSure Small Jaw Vessel-Sealing System in Hepatic Resection

    PubMed Central

    Yoshimoto, Miwa; Endo, Kanenori; Hanaki, Takehiko; Watanabe, Joji; Tokuyasu, Naruo; Sakamoto, Teruhisa; Honjo, Soichiro; Hirooka, Yasuaki; Ikeguchi, Masahide

    2014-01-01

    Background In hepatic resection for liver tumors, reducing operation time and blood loss are important for postsurgical complication prevention. This study aimed to compare the safety and efficacy of the LigaSure Small Jaw (Covidien, Boulder, CO) with those of the Cavitation Ultrasonic Surgical Aspirator (CUSA) system (Integra Life Sciences, Plainsboro, NJ) in hepatic surgery. Methods We enrolled 102 patients with liver tumors, of whom 51 underwent liver resection with the CUSA (CUSA group) between March 2004 and April 2011. Another 51 underwent resection with the LigaSure Small Jaw (LS group) between June 2011 and July 2012. We stratified patients by time period depending on the instrument used, and compared operative duration; intraoperative bleeding; and postoperative liver function and complication rate. Results Total operation time (mean ± SD) was significantly shorter in the LS group than in the CUSA group (358.8 ± 91.7 versus 460.6 ± 146.1 min, P < 0.001). Blood loss was not significantly different between the 2 groups. Frequency of postoperative complications was lower, but not significantly, in the LS group. Conclusion The LigaSure Small Jaw may allow a shorter total operative duration than the CUSA device. PMID:25324590

  16. High resolution interferometric metrology for patterned wafers

    NASA Astrophysics Data System (ADS)

    Tang, Shouhong; Freischlad, Klaus; Yam, Petrie

    2007-09-01

    The precision metrology of patterned wafer is increasingly demanded by the semiconductor device manufacturers. The most common methods include scanning probe microscopy (SPM) techniques such as stylus profilometry and Atomic Force Microscopy (AFM). These methods acquire data by contacting the surface over a sequence of one-dimensional scans. While high lateral resolution can be achieved in this way, such processes are time-consuming and can have the potential to deform the surface under test. An alternative non-contact interferometric method is presented here. The method uses the white-light interferometry (WLI) to provide wafer topography quickly in a direct three-dimensional format. The improved measurement throughput suggests that it is feasible to use this method for production monitoring. Most commercial interferometers with WLI are capable of measuring opaque surfaces with sub-nanometer precision. The described method extends this capability to determine the top surface topography of structured surfaces in the presence of varying phase shifts on reflection. The phase shift on reflection may be due to the material properties of bulk surfaces, single or multi-layer film stacks on a substrate, or other micro-structures on the wafer. Furthermore, this method simultaneously or separately provides additional parameters of the test piece e.g. layer thickness and/or material refractive index for film stacks, or line width and structure depth of micro-structures. The measurement results on various types of the wafer surfaces will be presented in this paper.

  17. Apparatus for edge etching of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Casajus, A.

    1986-01-01

    A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

  18. Wafer capping of MEMS with fab-friendly metals

    NASA Astrophysics Data System (ADS)

    Martin, Jack

    2007-01-01

    Inertial MEMS (Micro Electro Mechanical System) sensors are normally sealed in hermetic enclosures. Some are assembled in hermetic packages but wafer level packaging has become much more important in recent years. Anodic bonding can be used to achieve wafer level seals between silicon and glass but most suppliers of inertial sensors screen print glass frit onto silicon cap wafers. After removing the organic vehicle, these patterned cap wafers are sealed to device wafer prior to wafer singulation and plastic packaging. Anodic and glass frit bonding are both cost-effective. However, they impose size, quality and performance limitations. Wafer level sealing with a metal removes some of these limitations but introduces other concerns. This paper will review the current wafer level hermetic processes followed by a description of a thermocompression metal seal technology that is compatible with IC fabrication.

  19. Wafer LMC accuracy improvement by adding mask model

    NASA Astrophysics Data System (ADS)

    Lo, Wei Cyuan; Cheng, Yung Feng; Chen, Ming Jui; Haung, Peter; Chang, Stephen; Tsujimoto, Eiji

    2010-04-01

    Mask effect will be more sensitive for wafer printing in high-end technology. For advance only using current wafer model can not predict real wafer behavior accurately because it do not concern real mask performance (CD error, corner rounding..). Generally, we use wafer model to check whether our OPC results can satisfy our requirements (CD target). Through simulation on post-OPC patterns by using wafer model, we can check whether these post-OPC patterns can meet our target. Hence, accuracy model can help us to predict real wafer printing results and avoid OPC verification error. To Improve simulation verification accuracy at wafer level and decrease false alarm. We must consider mask effect like corner rounding and line-end shortening...etc in high-end mask. UMC (United Microelectronics Corporation) has cooperated with Brion and DNP to evaluate whether the wafer LMC (Lithography Manufacturability Check) (Brion hot spots prediction by simulation contour) accuracy can be improved by adding mask model into LMC verification procedure. We combine mask model (DNP provide 45nm node Poly mask model) and wafer model (UMC provide 45nm node Poly wafer model) then build up a new model that called M-FEM (Mask Focus Energy Matrix model) (Brion fitting M-FEM model). We compare the hotspots prediction between M-FEM model and baseline wafer model by LMC verification. Some different hotspots between two models were found. We evaluate whether the hotspots of M-FEM is more close to wafer printing results.

  20. Whole wafer imprint patterning using step and flash imprint lithography: a manufacturing solution for sub-100-nm patterning

    NASA Astrophysics Data System (ADS)

    Lentz, David; Doyle, Gary; Miller, Mike; Schmidt, Gerald; Ganapathisuramanian, Maha; Lu, Xiaoming; Resnick, Doug; LaBrake, Dwayne L.

    2007-03-01

    Imprint lithography has been shown to be an effective technique for the replication of nano-scale features1. When the imprint material is a UV cross linkable liquid, it is possible to perform the patterning process at room temperature and ambient pressure, which enables good pattern fidelity, short processing times, and reduced process defectivity2. Imprinting whole wafers using drop on demand dispense techniques offers improved throughput and nanopatterning over wafer topography which can exceed 10 ?m. Template fabrication of arbitrary whole wafer patterns offers unique challenges for 1x feature fabrication. The resolution and pattern area of the imprint approach is strictly dependent on the ability to create a 1X master template. This paper provides a detailed description of whole wafer templates, imprint patterning processes, and etch processes that have been employed to create a whole wafer archetype process through hard mask patterning. Particular attention is given to high volume manufacturing focused on whole wafer template fabrication, throughput and pattern fidelity. Step and Flash Imprint Lithography (S-FIL TM) makes use of templates that can be fabricated with the same patterning and etch transfer processes that are used for manufacturing phase-shifting photo masks. In the case of whole wafer templates the master die pattern is fabricated using conventional techniques. The replicate template carries the full wafer die pattern imprinted by step and repeat using the master. The S-FIL/R process can be used for patterning the replicate template 3. The structure, pattern fidelity and critical dimension uniformity of the master and replicate templates and patterned wafer is shown to be within measurement errors.

  1. A Wafer based W-band Phased Antenna Array

    NASA Astrophysics Data System (ADS)

    Kuo, Jerry Weiming

    A phased antenna array is a set of antennas that focuses radiating electromagnetic field with electronic steering of its main beam. Phased array has traditionally come with high development costs and hence is not widely used for more applications. The operation of phased array at W-band (94GHz) is also challenging since high frequency signal generation and reception is highly inefficient. The research goal of this work is to provide an integrated on-wafer solution to tackle these challenges. Novel techniques are integrated into a systematic solution in the following manner: First, a sub-harmonic mixing concept is introduced to ease W-band signal generation. Second, the phased array design is divided into different functional layers, and hence individual work could be collaboratively integrated. Finally, the direct implementation of phased array MMIC circuits through the wafer design limits the phase errors of the MMIC circuits and their connection circuits in a sub-micron scale, which is unprecedented in the traditional manufacturing style.

  2. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL); St. Martin, Edward (Libertyville, IL); Arora, Michelle (Woodridge, IL); de la Garza, Linda (Woodridge, IL)

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  3. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  4. Elimination of wafer edge die yield loss for accelerometers

    NASA Astrophysics Data System (ADS)

    Zhang, Zhenjun; Eskes, Kim A.

    2000-08-01

    Residual stresses from deposition of several micron thick polysilicon film on accelerometer wafers caused wafer to warp towards edge of wafer. The average peak to valley difference for wafer flat across wafer is 16 +/- 1 micrometers . The photo layer following the thick polysilicon deposition process is a CD critical layer with 1 micrometers spacing to be resolved. With standard stepper configuration, wafer non- flatness from residual stresses reduced overall depth of focus and made the 1 (mu) spacing in edge dies not resolved, resulting in stiction and yield loss for edge dies. To minimize the effect of wafer non-flatness on across wafer CD control and edge die CD definition at photo, three different focus algorithms as well as two different wafer chuck styles were evaluated on 1X steppers. Results showed that both oblong wafer chuck and two step focus option significantly improved CD definition and resolution of the 1 micrometers spacing in edge dies. Two step focus combined with oblong chuck offered the best CD control edge dies. Edge die yield loss was eliminated for accelerometer wafers ran with oblong chuck and two step focus. Oblong chuck, and two step focus combination have been released to full production at Poly2 layer of accelerometers.

  5. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  6. Warpage Measurement of Thin Wafers by Reflectometry

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moir Methods and Novel Techniques in Reflection Moir, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

  7. Precipitating Chromium Impurities in Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Salama, A. M.

    1982-01-01

    Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

  8. Mask-to-wafer alignment system

    DOEpatents

    Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

    2003-11-04

    A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

  9. Wafer level test solutions for IR sensors

    NASA Astrophysics Data System (ADS)

    Giessmann, Sebastian; Werner, Frank-Michael

    2014-05-01

    Wafer probers provide an established platform for performing electrical measurements at wafer level for CMOS and similar process technologies. For testing IR sensors, the requirements are beyond the standard prober capabilities. This presentation will give an overview about state of the art IR sensor probing systems reaching from flexible engineering solutions to automated production needs. Cooled sensors typically need to be tested at a target temperature below 80 K. Not only is the device temperature important but also the surrounding environment is required to prevent background radiation from reaching the device under test. To achieve that, a cryogenic shield is protecting the movable chuck. By operating that shield to attract residual gases inside the chamber, a completely contamination-free test environment can be guaranteed. The use of special black coatings are furthermore supporting the removal of stray light. Typically, probe card needles are operating at ambient (room) temperature when connecting to the wafer. To avoid the entrance of heat, which can result in distorted measurements, the probe card is fully embedded into the cryogenic shield. A shutter system, located above the probe field, is designed to switch between the microscope view to align the sensor under the needles and the test relevant setup. This includes a completely closed position to take dark current measurements. Another position holds a possible filter glass with the required aperture opening. The necessary infrared sources to stimulate the device are located above.

  10. Wafer weak point detection based on aerial images or WLCD

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Philipp, Peter; Litt, Lloyd C.; Ackmann, Paul; Crell, Christian; Chen, Norman

    2015-10-01

    Aerial image measurement is a key technique for model based optical proximity correction (OPC) verification. Actual aerial images obtained by AIMS (aerial image measurement system) or WLCD (wafer level critical dimension) can detect printed wafer weak point structures in advance of wafer exposure and defect inspection. Normally, the potential wafer weak points are determined based on optical rule check (ORC) simulation in advance. However, the correlation to real wafer weak points is often not perfect due to the contribution of mask three dimension (M3D) effects, actual mask errors, and scanner lens effects. If the design weak points can accurately be detected in advance, it will reduce the wafer fab cost and improve cycle time. WLCD or AIMS tools are able to measure the aerial images CD and bossung curve through focus window. However, it is difficult to detect the wafer weak point in advance without defining selection criteria. In this study, wafer weak points sensitive to mask mean-to-nominal values are characterized for a process with very high MEEF (normally more than 4). Aerial image CD uses fixed threshold to detect the wafer weak points. By using WLCD through threshold and focus window, the efficiency of wafer weak point detection is also demonstrated. A novel method using contrast range evaluation is shown in the paper. Use of the slope of aerial images for more accurate detection of the wafer weak points using WLCD is also discussed. The contrast range can also be used to detect the wafer weak points in advance. Further, since the mean to nominal of the reticle contributes to the effective contrast range in a high MEEF area this work shows that control of the mask error is critical for high MEEF layers such as poly, active and metal layers. Wafer process based weak points that cannot be detected by wafer lithography CD or WLCD will be discussed.

  11. LIGA-fabricated two-dimensional quadrupole array and scroll pump for miniature gas chromatograph/mass spectrometer

    NASA Astrophysics Data System (ADS)

    Wiberg, Dean V.; Myung, Nosang V.; Eyre, Beverley; Shcheglov, Kirill; Orient, Otto J.; Moore, Eric; Munz, Philip

    2003-07-01

    A 3X3 array of hyperboloid quadrupole mass filters with a 3 mm pole length was fabricated using the LIGA (LIthographic Galvanoformung and Abformung) process. Electrical connectivity and spatial orientation are established by bonding the pole array to a low temperature co-fired ceramic (LTCC) substrate. A miniature scroll pump for vacuum pumping with a scroll height of 3 mm was also fabricated using the LIGA process. New LIGA fabrication steps (e.g. expose and developed freestanding PMMA, compression bonding of electroplating base and PMMA, low-stress electroplated films) have been developed to fabricate ultra thick PMMA molds with high aspect ratios (70:1) and high precision. Computational analysis was performed to estimate the miniature scroll pump performance characteristics.

  12. Dry Cleaning Technology of Silicon Wafer with a Line Beam for Semiconductor Fabrication by KrF Excimer Laser

    NASA Astrophysics Data System (ADS)

    Kim, Dae-Jin; Kim, Yong-Kee; Ryu, Je-Kil; Kim, Hyun-Jung

    2002-07-01

    The contaminants on a bare wafer or a patterned wafer can seriously impact the yield of manufacturing devices in semiconductor fabrication. In very large scale integrated circuit (VLSI) technology, as the device density increases, particularly for flat panel displays, the importance of cleaning also increases. The removal of particles and the Photoresist (PR) layer on a silicon wafer was investigated by a line beam of a KrF excimer laser in a cleanroom condition. This paper reports the effects of a high-energy laser beam onto the electrical, structural and morphological properties of the wafer and introduces a practical line beam laser cleaning method for particle removal and PR stripping. The removal of particles and the PR layer on a silicon wafer was performed using a KrF excimer laser in the cleanroom condition. The results of surface morphology were observed using a scanning electron microscope (SEM) and atomic force microscopy (AFM). The crystallization of the silicon wafer was observed by X-ray diffraction (XRD) studies. The electrical properties of the silicon wafer before and after laser irradiation were characterized by Hall measurements. The compositions of the PR covered wafers were determined by energy dispersive X-ray diffraction (EDX). The carrier concentration and resistivity of the bare silicon wafer were 1.4 1015 cm-3 and 17.7 ?{\\cdot}cm, respectively, before laser irradiation. The carrier concentration of the silicon wafers after laser irradiation was in the range of 1.1 1015-1.6 1015 cm-3, and the resistivity was in the range of 17.0-18.2 ?{\\cdot}cm. The carrier concentration and resistivity of the bare silicon wafers were not changed even after high-energy laser irradiation of up to 600 mJ/cm2. After 6-pulse laser irradiation, the PR layer of 0.82 ?m thickness was stripped perfectly with an energy density of 300 mJ/cm2 without the aid of any chemical or solvent. The ablation rates were 0.06 ?m/pulse for 100 mJ/cm2, 0.10 ?m/pulse for 200 mJ/cm2 and 0.13 ?m/pulse for 300 mJ/cm2. Dry laser cleaning technology shows that particles and organic compounds, like PR, on the bare silicon wafer can be effectively removed without any damage to the silicon substrate.

  13. Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size

    NASA Astrophysics Data System (ADS)

    Kim, Hee Yeoun; Yang, Chungmo; Park, Jae Hong; Jung, Ho; Kim, Taehyun; Kim, Kyung Tae; Lim, Sung Kyu; Lee, Sang Woo; Mitchell, Jay; Hwang, Wook Joong; Lee, Kwyro

    2013-06-01

    For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.

  14. Multi-dimensional multi-species modeling of transient electrodeposition in LIGA microfabrication.

    SciTech Connect

    Evans, Gregory Herbert; Chen, Ken Shuang

    2004-06-01

    This report documents the efforts and accomplishments of the LIGA electrodeposition modeling project which was headed by the ASCI Materials and Physics Modeling Program. A multi-dimensional framework based on GOMA was developed for modeling time-dependent diffusion and migration of multiple charged species in a dilute electrolyte solution with reduction electro-chemical reactions on moving deposition surfaces. By combining the species mass conservation equations with the electroneutrality constraint, a Poisson equation that explicitly describes the electrolyte potential was derived. The set of coupled, nonlinear equations governing species transport, electric potential, velocity, hydrodynamic pressure, and mesh motion were solved in GOMA, using the finite-element method and a fully-coupled implicit solution scheme via Newton's method. By treating the finite-element mesh as a pseudo solid with an arbitrary Lagrangian-Eulerian formulation and by repeatedly performing re-meshing with CUBIT and re-mapping with MAPVAR, the moving deposition surfaces were tracked explicitly from start of deposition until the trenches were filled with metal, thus enabling the computation of local current densities that potentially influence the microstructure and frictional/mechanical properties of the deposit. The multi-dimensional, multi-species, transient computational framework was demonstrated in case studies of two-dimensional nickel electrodeposition in single and multiple trenches, without and with bath stirring or forced flow. Effects of buoyancy-induced convection on deposition were also investigated. To further illustrate its utility, the framework was employed to simulate deposition in microscreen-based LIGA molds. Lastly, future needs for modeling LIGA electrodeposition are discussed.

  15. Equipment for On-Wafer Testing From 220 to 325 GHz

    NASA Technical Reports Server (NTRS)

    Samoska, Lorene; Peralta, Alejandro; Dawson, Douglas; Lee, Karen; Boll, Greg; Oleson, Chuck

    2006-01-01

    A system of electronic instrumentation, constituting the equivalent of a two-port vector network analyzer, has been developed for use in on-wafer measurement of key electrical characteristics of semiconductor devices at frequencies from 220 to 325 GHz. A prior system designed according to similar principles was reported in Equipment for On-Wafer Testing at Frequencies Up to 220 GHz (NPO-20760), NASA Tech Briefs, Vol. 25, No. 11 (November 2001), page 42. As one would expect, a major source of difficulty in progressing to the present higher-frequency-range system was the need for greater mechanical precision as wavelengths shorten into the millimeter range, approaching the scale of mechanical tolerances of prior systems. The system (see figure) includes both commercial off-the-shelf and custom equipment. As in the system of the cited prior article, the equipment includes test sets that are extended versions of commercial network analyzers that function in a lower frequency range. The extension to the higher frequency range is accomplished by use of custom frequency-extension modules that contain frequency multipliers and harmonic mixers. On-wafer measurement is made possible by waveguide wafer probes that were custom designed and built for this wavelength range, plus an on-wafer calibration substrate designed for use with these probes. In this case, the calibration substrate was specially fabricated by laser milling. The system was used to make the first on-wafer measurements of a semiconductor device in the frequency range from 220 to 320 GHz. Some of the measurement results showed that the device had gain.

  16. Innovative metrology for wafer edge defectivity in immersion lithography

    NASA Astrophysics Data System (ADS)

    Pollentier, I.; Iwamoto, F.; Kocsis, M.; Somanchi, A.; Burkeen, F.; Vedula, S.

    2007-03-01

    In semiconductor manufacturing, the control of defects at the edge of the wafer is a key factor to keep the number of yielding die on a wafer as high as possible. Using dry lithography, this control is typically done by an edge bead removal (EBR) process, which is understood well. Immersion lithography however changes this situation significantly. During this exposure, the wafer edge is locally in contact with water from the immersion hood, and particles can then be transported back and forth from the wafer edge area to the scanner wafer stage. Materiel in the EBR region can also potentially be damaged by the dynamic force of the immersion hood movement. In this paper, we have investigated the impact of immersion lithography on wafer edge defectivity. In the past, such work has been limited to the inspection of the flat top part of the wafer edge, due to the inspection challenges at the curved wafer edge and lack of a comprehensive defect inspection solution. This study utilized KLA-Tencor's VisEdge, a new automated edge inspection system, that provides full wafer edge imaging (top, side, bottom) using laser-based optics and multi-sensor detection, and where defects of interest can be classified with Automated Defect Classification (ADC) software. Using the VisEdge technology, the impact from the immersion lithography towards wafer edge defectivity is investigated. The work revealed several key challenges to keep the wafer edge related defectivity under control : choice of resist, optimization of EBR recipes, scanner pollution and related memory effects, wafer handling, device processing, etc... Contributing to the understanding of the mechanisms of wafer edge related immersion defects and to the optimization the die yield level, this technology is believed to be important when the immersion processes are introduced in semiconductor manufacturing.

  17. Electrooptic shutter devices utilizing PLZT ceramic wafers

    SciTech Connect

    Thornton, A.L.

    1981-01-01

    Optical transparency was achieved in lead zirconate-titanate ferroelectric ceramics by substituting moderate amounts of the element lanthanum (8 to 12%) for lead. These compositions exhibit the quadratic (Kerr) electrooptic effect. The excellent optical qualities of these materials (designated PLZT) has permitted the practical utilization of their electrooptic properties in a number of devices. All of these devices utilize the classic Kerr cell arrangement. A PLZT wafer with optical axis oriented at 45/sup 0/ with respect to the axes of polarization is sandwiched between crossed polarizers. Application of an electric field via an interdigital array of electrodes on opposing wafer surfaces forces the PLZT material into a tetragonal state with the resulting induced birefringence proportional to the square of the applied electric field. Hence, the electrooptic wafer provides a retardation of light so that a component is passed by the second crossed polarizer to achieve an ON or open state. Maximum transmission is achieved when the retardation is half-wave. Shutter devices developed by Sandia and those in continuing development are described with respect to operational characteristics and physical configuration. The devices range in size from very small apertures of 50 ..mu..m x 2 mm with center-to-center repeat dimensions of 125 ..mu..m - to very large - apertures of 15.2 cm in single pieces and mosaics with apertures of 15.2 cm x 20.3 cm. Major efforts have centered on shutter development for the protection of aircrew from eye-damaging weapon effects. Other devices are also described which: provide eye protection for welders, protect vidicon tubes, function as page composers for holographic memories serve as large aperture photographic shutters, provide stereoscopic three-dimensional TV displays, and serve as data links in a fiber-optic transmission path.

  18. Slip-Free Rapid Thermal Processing in Single Wafer Furnace

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-06-01

    Defect generation phenomena in Si wafers during atmospheric pressure rapid thermal processing (RTP) in a single wafer furnace (SWF) are investigated as a function of temperature, process time, wafer handling method and speed. The size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in controlling defect generation during RTP under given process conditions. Highly reproducible slip-free RTP results were achieved in 200-mm-diameter Si wafers processed at 1100°C for 60 s (up to 5 times) by optimizing the wafer handling method and speed.

  19. Resonance ultrasonic vibrations for crack detection in photovoltaic silicon wafers

    NASA Astrophysics Data System (ADS)

    Dallas, W.; Polupan, O.; Ostapenko, S.

    2007-03-01

    The resonance ultrasonic vibrations (RUV) technique is adapted for non-destructive crack detection in full-size silicon wafers for solar cells. The RUV methodology relies on deviation of the frequency response curve of a wafer, ultrasonically stimulated via vacuum coupled piezoelectric transducer, with a periphery crack versus regular non-cracked wafers as detected by a periphery mounted acoustic probe. Crack detection is illustrated on a set of cast wafers. We performed vibration mode identification on square-shaped production-grade Si wafers and confirmed by finite element analyses. The modelling was accomplished for the different modes of the resonance vibrations of a wafer with a periphery crack to assess the sensitivity of the RUV method relative to crack length and crack location.

  20. Fabrication of PMMA Microchip of Capillary Electrophoresis by Optimized UV-LIGA Process

    NASA Astrophysics Data System (ADS)

    Zhu, Xuelin; Liu, Gang; Xiong, Ying; Guo, Yuhua; Tian, Yangchao

    2006-04-01

    Design and fabrication of microfluidic devices on polymethylmethacrylate (PMMA) substrates for electrochemical analysis applications using improved UV-LIGA process are described. The micro-channel structures are transferred from Nickel mould into the plastic plates by hot embossing method. During the mould fabrication, the exposure process is optimized for the large ratio of exposed area to unexposed area of negative photo-resist (SU-8), then non-planar electroforming technique is used for the large line space of the SU8 photoresist mold. Microelectrodes for electrochemical detection are fabricated on other blank PMMA plates through lift-off process. Then these substrates with microchannels are bonded to PMMA plates with microelectrodes by thermal bonding method based on surface modification. In this study, the PMMA microchips of capillary electrophoresis for electrochemical detection (CE-ECD Chips) have been demonstrated by electrophoretic separation of L-ascorbic and uric acid. The results indicate that the fabrication of CE chips by this improved UV-LIGA process has potential of mass production with low cost.

  1. Mechanical and metallographic characterization of LIGA fabricated nickel and 80%Ni-20%Fe Permalloy

    SciTech Connect

    Christenson, T.R.; Buchheit, T.E.; Schmale, D.T.; Bourcier, R.J.

    1998-04-13

    A table top servohydraulic load frame equipped with a laser displacement measurement system was constructed for the mechanical characterization of LIGA fabricated electroforms. A drop in tensile specimen geometry which includes a pattern to identify gauge length via laser scanning has proven to provide a convenient means to monitor and characterize mechanical property variations arising during processing. In addition to tensile properties, hardness and metallurgical data were obtained for nickel deposit specimens of current density varying between 20 and 80 mA/cm{sup 2} from a sulfamate based bath. Data from 80/20 nickel-iron deposits is also presented for comparison. As expected, substantial mechanical property differences from bulk metal properties are observed as well as a dependence of material strength on current density which is supported by grain size variation. While elastic modulus values of the nickel electrodeposit are near 160 GPa, yield stress values vary by over 60%. A strong orientation in the metal electrodeposits as well as variations in nucleating and growth morphology present a concern for anisotropic and geometry dependent mechanical properties within and between different LIGA components.

  2. Wafer warpage characterization measurement with modified fringe reflection method

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2015-05-01

    We have demonstrated a modified fringe reflection method to compensate the warpage measurement errors caused by the height difference between optical reference mirror and wafer sample surface. We have used a linearity analysis approach to obtain the parabolic height errors for a 4-inch sapphire wafer warpage measurement, which is around 1.48 ?m of 100 ?m height difference. The experimental results shows the warp discrepancy of 6-inch sapphire wafer is less than 1 ?m compared with the reference Tropel instrument.

  3. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  4. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  5. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M.

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  6. Wafer-scale synthesis of monodisperse synthetic magnetic multilayer nanorods

    PubMed Central

    Zhang, Mingliang; Bechstein, Daniel J. B.; Wilson, Robert J.; Wang, Shan X.

    2014-01-01

    A double exposure technique has been used to fabricate nanoimprint stamps for making monodisperse nanorods with controllable lengths. The nanorod length is defined by a normal photolithography projection process whereas the nanorod width is defined by an edge-lithography process using a soft polydimethylsiloxane (PDMS) contact mask. Taking advantage of edge-lithography, the nanorod width can be less than the diffraction limit of the exposure light. Using these nanorod stamps, synthetic magnetic multilayer (SMM) nanorods have been fabricated using nanoimprint lithography, resulting in a length variation of ~3%. Nanorod magnetic properties have been characterized in both longitudinal and in-plane transverse directions of the nanorods. A theoretical model has been established to explain the magnetic responses and has revealed that both shape anisotropy and interlayer interactions are important in determining the properties of SMM nanorods. PMID:24329003

  7. Diamond MEMS: wafer scale processing, devices, and technology insertion

    NASA Astrophysics Data System (ADS)

    Carlisle, J. A.

    2009-05-01

    Diamond has long held the promise of revolutionary new devices: impervious chemical barriers, smooth and reliable microscopic machines, and tough mechanical tools. Yet it's been an outsider. Laboratories have been effectively growing diamond crystals for at least 25 years, but the jump to market viability has always been blocked by the expense of diamond production and inability to integrate with other materials. Advances in chemical vapor deposition (CVD) processes have given rise to a hierarchy of carbon films ranging from diamond-like carbon (DLC) to vapor-deposited diamond coatings, however. All have pros and cons based on structure and cost, but they all share some of diamond's heralded attributes. The best performer, in theory, is the purest form of diamond film possible, one absent of graphitic phases. Such a material would capture the extreme hardness, high Young's modulus and chemical inertness of natural diamond. Advanced Diamond Technologies Inc., Romeoville, Ill., is the first company to develop a distinct chemical process to create a marketable phase-pure diamond film. The material, called UNCD (for ultrananocrystalline diamond), features grain sizes from 3 to 300 nm in size, and layers just 1 to 2 microns thick. With significant advantages over other thin films, UNCD is designed to be inexpensive enough for use in atomic force microscopy (AFM) probes, microelectromechanical machines (MEMS), cell phone circuitry, radio frequency devices, and even biosensors.

  8. Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections

    NASA Astrophysics Data System (ADS)

    Lin, Chiung-Wen; Yang, Hsueh-An; Wang, Wei Chung; Fang, Weileun

    2007-06-01

    Packaging is an emerging technology for microsystem integration. The silicon-on-insulator (SOI) wafer has been extensively employed for micromachined devices for its reliable fabrication steps and robust structures. This research reports a packaging approach for silicon-on- insulator-micro-electro-mechanical system (SOI-MEMS) devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling and electroplating. These vias provide electrical signal paths to the MEMS device, while isolating MEMS devices from the outer environment. A high-strength hermetic sealing is then achieved after anodic bonding of the through-wafer-vias-embedded SOI wafer to a Pyrex 7740 glass. Moreover, the packaged SOI-MEMS chip is compatible with surface mount technology, and provides a superior way for 3D heterogeneous integration.

  9. Characterization Of The Ultratech Wafer Stepper

    NASA Astrophysics Data System (ADS)

    Hershel, Ron; Voison, Ron

    1982-09-01

    A brief characterization of the Ultratech Model 900 wafer stepper is presented. Excellent control critical dimensions for 1-gum minimum features is accomplished by using a broad spectral bandwidth for exposure which minimizes standing wave effects and by using numerical aperture of 0.315 illuminated with coherence factor of 0.45. Minimal variation in linewidth is seen over 5000A to 8000A poly and metal steps with little evidence of standing wave patterns in the resist profiles. A large depth of focus is obtained with a highly corrected 1:1 lens design which keeps astigmatism and field curvature below 0.5um. The automatic site-by-site alignment system on the Model 900 has proven extremely reliable at all wafer levels with a repeatability better than 0.16um (2 sigma). Lens-to-lens distortion below 0.2um (2 sigma) results from the inherent symmetry in the folded 1:1 design and from careful lens fabrication. A precision lenedistortion test is described with a 2 sigma error below 0.04um and the overlay distortion for the three Ultratech lenses is presented.

  10. Laser soft marking on silicon wafer

    NASA Astrophysics Data System (ADS)

    Khoong, L. E.; Lam, Y. C.; Zheng, H. Y.; Chen, X.

    2010-03-01

    A laser soft marking technique is developed for laser markings on a silicon wafer. Due to negligible surface modification, the laser soft wafer markings are invisible by naked eyes under room condition and are undetectable using sophisticated instruments. However, these laser markings are found to be visible to naked eyes through a differential condensation of water droplets on the laser-marked and unmarked silicon surfaces. To understand this phenomenon, a model is established to study the condensation of water droplets on laser-marked and unmarked silicon surfaces. Experimental observations and simulation results indicate that the laser soft marking could have modified the silicon surface with a thin polycrystalline silicon layer which has a much lower conductivity than the crystalline silicon. In addition, this thin layer exhibits a thermal conductivity which is approximately two orders of magnitude lower than that of its equivalent bulk material. As a result, heat transfer on the laser-marked silicon surface is much lower than the crystalline silicon and thus makes these laser soft markings easily visible visually under condensation.

  11. A Comparison of the LigaSure and Harmonic Scalpel in Thyroid Surgery: A Single Institution Review

    PubMed Central

    Zarebczan, Barbara; Mohanty, Devi; Chen, Herbert

    2010-01-01

    Background Over the last few years many surgeons have begun to utilize the LigaSure device or Harmonic scalpel to perform thyroid surgery. Several papers have demonstrated the benefits of these devices over traditional hand-tying techniques. The purpose of this study was to examine our institutions experience with the LigaSure device and Harmonic scalpel during thyroid surgery and to compare mean operative times and complications associated with each device. Methods A retrospective chart review was performed on all patients who underwent thyroid surgery using either the LigaSure device or Harmonic scalpel at a single institution between December 2005 and August 2009. Charts were reviewed for patient demographics, mean operative time, length of stay, and complications such as transient recurrent laryngeal nerve injury, hypocalcemia, and hematoma formation. Results Two hundred and thirty-one patients were included in the study, of whom 123 underwent total thyroidectomy and 108 underwent lobectomy. There was a significant decrease in the operative time for both thyroidectomies and lobectomies when the Harmonic scalpel was utilized. In regard to complications, there was no statistically significant difference in the number of transient and permanent recurrent laryngeal nerve injuries, percentage of patients developing hypocalcemia, or in the rate of hematoma development. Conclusion In this study, there was no difference in the rate of complications between the two devices. However, the use of the Harmonic scalpel significantly decreased operative time for both thyroidectomies and thyroid lobectomies when compared to the LigaSure device. PMID:20853030

  12. Comparison of lateral thermal damage of the human peritoneum using monopolar diathermy, Harmonic scalpel and LigaSure

    PubMed Central

    Druijani?, Nikica; Pogoreli?, Zenon; Perko, Zdravko; Mrkli?, Ivana; Tomi?, Snjeana

    2012-01-01

    Background New hemostatic technologies are often employed in open and laparoscopic surgery to reduce duration of surgery and complications. Monopolar diathermy, Harmonic scalpel and LigaSure are routinely used in open and laparoscopic surgery for tissue cutting and hemostasis. We compared lateral thermal damage following in vivo application of 3 commonly used instruments. Methods We used monopolar diathermy, Harmonic scalpel and LigaSure to coagulate and divide the peritoneum of patients who underwent median laparotomy. After anesthesia, median supraumbilical laparotomy was performed, and the peritoneum of each patient was coagulated using different devices. Using light microscopy and morphometric imaging analysis, the width of tissue lateral thermal damage was measured from the point of the peritoneal incision. Results We included 100 patients in our study. After a peritoneal incision, the mean lateral thermal damage of monopolar diathermy, Harmonic scalpel (output power 3), Harmonic scalpel (output power 5) and LigaSure were 215.79 ?m, 90.42 ?m, 127.48 ?m and 144.18 ?m, respectively. Conclusion The degree of lateral thermal spread varied by instrument type, power setting and application time. LigaSure and Harmonic scalpel were the safest and most efficient methods of tissue coagulation. Monopolar diathermy resulted in the greatest degree of thermal damage in tissues. PMID:22854112

  13. Fully-vectorial simulation and tolerancing of optical systems for wafer inspection by field tracing

    NASA Astrophysics Data System (ADS)

    Asoubar, Daniel; Schweitzer, Hagen; Hellmann, Christian; Kuhn, Michael; Wyrowski, Frank

    2015-06-01

    The simulation, design and tolerancing of optical systems for wafer inspection is a challenging task due to the different feature sizes, which are involved in these systems. On the one hand light is propagated through macroscopic lens systems and on the other hand light is diffracted at microscopic structures with features in the range of the wavelength of light. Due to this variety of scale plenty of different physical effects like refraction, diffraction, interference and polarization have to be taken into account for a realistic analysis of such inspection systems. We show that all of these effects can be included in a system simulation by field tracing, which combines physical and geometrical optics. The main idea is the decomposition of the complex optical setup in a sequence of subdomains. Per subdomain a different approximative or rigorous solution of Maxwell's equations is applied to propagate the light. In this work the different modeling techniques for the analysis of an exemplary wafer inspection system are discussed in detail. These techniques are mainly geometrical optics for the light propagation through macroscopic lenses, a rigorous Fourier Modal Method (FMM) for the modeling of light diffraction at the wafer microstructure and different free-space diffraction integrals. In combination with a numerically efficient algorithm for the coordinate transformation of electromagnetic fields, field tracing enables position and fabrication tolerancing. As an example different tilt tolerance effects on the polarization state and image contrast of a simple wafer inspection system are shown.

  14. Molecular and ionic contamination monitoring for cleanroom air and wafer surfaces

    NASA Astrophysics Data System (ADS)

    Sun, Peng; Adams, Marty; Shive, Larry; Pirooz, Saeed

    1997-09-01

    Advances in the electronic industry toward large-scale integration of semiconductor devices have placed strict demands on the ability to measure and monitor ultratrace levels of impurities. Even though they have been found to have increasingly detrimental impacts on the performance and yield of semiconductor products, organic and non-metal ionic contaminants have not received the same attention as particles and metallics. Method developments for ultratrace measurements of molecular and ionic contamination are far behind the demands. This paper describes the use of different sampling and analytical techniques to assess and monitor molecular and ionic contaminants in cleanroom ambient air and on wafer surfaces. Thermal desorption gas chromatography mass spectrometry/nitrogen phosphorous detector is used for the identification and quantification of organic contaminants. Ammonium (NH4+) and inorganic anions are analyzed by using capillary electrophoresis with indirect UV detection methods. The identification and quantification of specific organic compounds, which outgas from cleanroom ULPA filters and wafer package boxes and tend to adsorb on silicon wafers, will be demonstrated. Ammonium and anion contamination for different wafer cleaning processes will be compared. The capabilities, applications, and limitations of these techniques will be discussed in further details.

  15. "Performance Of A Wafer Stepper With Automatic Intra-Die Registration Correction."

    NASA Astrophysics Data System (ADS)

    van den Brink, M. A.; Wittekoek, S.; Linders, H. F. D.; van Hout, F. J.; George, R. A.

    1987-01-01

    An evaluation of a wafer stepper with the new improved Philips/ASM-L phase grating alignment system is reported. It is shown that an accurate alignment system needs an accurate X-Y-0 wafer stage and an accurate reticle Z stage to realize optimum overlay accuracy. This follows from a discussion of the overlay budget and an alignment procedure model. The accurate wafer stage permits high overlay accuracy using global alignment only, thus eliminating the throughput penalty of align-by-field schemes. The accurate reticle Z stage enables an intra-die magnification control with respect to the wafer scale. Various overlay data are reported, which have been measured with the automatic metrology program of the stepper. It is demonstrated that the new dual alignment system (with the external spatial filter) has improved the ability to align to weakly reflecting layers. The results are supported by a Fourier analysis of the alignment signal. Resolution data are given for the PAS 2500 projection lenses, which show that the high overlay accuracy of the system is properly matched with submicron linewidth control. The results of a recently introduced 20mm i-line lens with a numerical aperture of 0.4 (Zeiss 10-78-58) are included.

  16. Temperature rise of the mask-resist assembly during LIGA exposure.

    SciTech Connect

    Ting, Aili

    2004-11-01

    Deep X-ray lithography on PMMA resist is used in the LIGA process. The resist is exposed to synchrotron X-rays through a patterned mask and then is developed in a liquid developer to make high aspect ratio microstructures. The limitations in dimensional accuracies of the LIGA generated microstructure originate from many sources, including synchrotron and X-ray physics, thermal and mechanical properties of mask and resist, and from the kinetics of the developer. This work addresses the thermal analysis and temperature rise of the mask-resist assembly during exposure in air at the Advanced Light Source (ALS) synchrotron. The concern is that dimensional errors generated at the mask and the resist due to thermal expansion will lower the accuracy of the lithography. We have developed a three-dimensional finite-element model of the mask and resist assembly that includes a mask with absorber, a resist with substrate, three metal holders, and a water-cooling block. We employed the LIGA exposure-development software LEX-D to calculate volumetric heat sources generated in the assembly by X-ray absorption and the commercial software ABAQUS to calculate heat transfer including thermal conduction inside the assembly, natural and forced convection, and thermal radiation. at assembly outer and/or inner surfaces. The calculations of assembly maximum temperature. have been compared with temperature measurements conducted at ALS. In some of these experiments, additional cooling of the assembly was produced by forced nitrogen flow ('nitrogen jets') directed at the mask surface. The temperature rise in the silicon mask and the mask holder comes directly from the X-ray absorption, but nitrogen jets carry away a significant portion of heat energy from the mask surface, while natural convection carries away negligibly small amounts energy from the holder. The temperature rise in PMMA resist is mainly from heat conducted from the silicon substrate backward to the resist and from the inner cavity air forward to the resist, while the X-ray absorption is only secondary. Therefore, reduction of heat flow conducted from both substrate and cavity air to the resist is essential. An improved water-cooling block is expected to carry away most heat energy along the main heat conductive path, leaving the resist at a favorable working temperature.

  17. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, Gary S.

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  18. Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint

    SciTech Connect

    Rupnowski, P.; Sopori, B.

    2008-05-01

    This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

  19. Piezoresistive stress sensors on (110) silicon wafers

    NASA Technical Reports Server (NTRS)

    Kang, Y. L.; Suhling, J. C.; Jaeger, R. C.

    1992-01-01

    Structural reliability of electronic packages has become an increasing concern for a variety of reasons including the advent of higher integrated circuit densities, power density levels, and operating temperatures. A powerful method for experimental evaluation of die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, the basic equations needed for the design of stress sensors fabricated on the surface of (110) oriented silicon wafers have been presented. Several sensor rosette configurations have been explored, including the familiar three-element 0-45-90 rosette. Rosette designs have been found which minimize the necessary calibration procedures and permit more stress components to be measured. It has been established that stress sensors on the surface of (110) test chips are sensitive to four out of the six stress components at a point.

  20. Wafer Mapping Using Deuterium Enhanced Defect Characterization

    NASA Astrophysics Data System (ADS)

    Hossain, K.; Holland, O. W.; Hellmer, R.; Vanmil, B.; Bubulac, L. O.; Golding, T. D.

    2010-07-01

    Deuterium (as well as other hydrogen isotopes) binds with a wide range of morphological defects in semiconductors and, as such, becomes distributed similarly to those defects. Thus, the deuterium profile within the sample serves as the basis of a technique for defect mapping known as amethyst wafer mapping (AWM). The efficiency of this technique has been demonstrated by evaluation of ion-induced damage in implanted Si, as well as as-grown defects in HgCdTe (MCT) epilayers. The defect tagging or decoration capability of deuterium is largely material independent and applicable to a wide range of defect morphologies. A number of analytical techniques including ion channeling and etch pit density measurements were used to evaluate the AWM results.

  1. Overlay Tolerances For VLSI Using Wafer Steppers

    NASA Astrophysics Data System (ADS)

    Levinson, Harry J.; Rice, Rory

    1988-01-01

    In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his merchandise appear as attractive as possible, the lithographer is frequently placed in the position of having to explain subtle issues in order to justify his decisions. It is the purpose of this paper to provide that explanation.

  2. Thermal Warpage of Large Diameter Czochralski-Grown Silicon Wafers

    NASA Astrophysics Data System (ADS)

    Shimizu, Hirofumi; Aoshima, Takaaki

    1988-12-01

    Thermal warping of large diameter Czochralski-grown silicon wafers as affected by oxygen precipitation is investigated both experimentally and theoretically. The difference of wafer warpage and its shape between the heating and cooling processes is clarified by thermal stresses calculated from temperature gradients in wafers for each process. The critical temperatures for the slip occurrence are determined for the heating and cooling processes as a function of the microdefect density. Then, the optimized process conditions to avoid slip dislocations are obtained experimentally. The critical stress curve for the processed wafers in MOS devices is determined by comparison with the thermal stress curves calculated under various process conditions, and thereby predicting the slip-free conditions for wafers in a row with various diameters from 100 to 200 mm.

  3. A novel technique for cleaning semiconductor wafers using ultrasonic transducer

    NASA Astrophysics Data System (ADS)

    Nakade, Rugved; Yow, Raylon; Sayka, Tony; Sardar, Dhiraj

    2006-10-01

    An experiment was designed based on U.S. Patent no. 6,766,813 which describes a process that effectively cleans a semiconductor wafer with the help of ultrasonic vibrations. The semiconductor wafer was freely supported by a hollow cylindrical box made of foam. Two commonly occurring contaminants found on wafers in the industry are silicon and silicon dioxide. Micrometer sizes of these two materials were used to replicate contaminants that commonly occur in the industry. The wafer was then excited with the help of an ultrasonic transducer in the aim of knocking off these contaminants from the surface of the semiconductor wafer. Particle counts were taken with the help of a modified optical microscope before and after applying the ultrasonic vibration in order to determine the effectiveness of this technique.

  4. Backside EBR process performance with various wafer properties

    NASA Astrophysics Data System (ADS)

    Goto, Tomohiro; Shigemori, Kazuhito; Vangheluwe, Rik; Erich, Daub; Sanada, Masakazu

    2009-03-01

    In immersion lithography process, film stacking architecture will be necessary to avoid top coat film peeling. To achieve suitable stacking architecture for immersion lithography process, an EBR process that delivers tightly controlled film edge position and good uniformity around the wafer circumference is needed. We demonstrated a new bevel rinse system on a SOKUDO RF3 coat-and-develop track for immersion lithography. The performance of the new bevel rinse system for various wafer properties was evaluated. It was found that the bevel rinse system has a good controllability of film edge position and good uniformity around the wafer circumference. The results indicate that the bevel rinse system has a large margin for wafer centering accuracy, back side particles, wafer shape and substrates with good film edge position controllability, uniformity and clean apex. The system has been demonstrated to provide a suitable film stacking architecture for immersion lithography mass production process.

  5. Interferometric metrology of wafer nanotopography for advanced CMOS process integration

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Koliopoulos, Chris L.; Tang, Shouhong

    2001-12-01

    According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

  6. Reduction of Thermal Conductivity in Wafer-Bonded Silicon

    SciTech Connect

    ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

    2006-11-27

    Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

  7. LIGA fabrication of mm-wave accelerating cavity structures at the Advanced Photon Source (APS)

    SciTech Connect

    Song, J.J.; Bajikar, S.; Kang, Y.W.

    1997-08-01

    Recent microfabrication technologies based on the LIGA (German acronym for Lithographe, Galvanoformung, und Abformung) process have been applied to build high-aspect-ratio, metallic or dielectric planar structures suitable for high-frequency rf cavity structures. The cavity structures would be used as parts of linear accelerators, microwave undulators, and mm-wave amplifiers. The microfabrication process includes manufacture of precision x-ray masks, exposure of positive resist x-rays through the mask, resist development, and electroforming of the final microstructure. Prototypes of a 32-cell, 108-GHz constant-impedance cavity and a 66-cell, 94-GHz constant-gradient cavity were fabricated with the synchrotron radiation sources at APS and NSLS. This paper will present an overview of the new technology and details of the mm-wave cavity fabrication.

  8. Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage

    PubMed Central

    Rack, Alexander; Scheel, Mario; Danilewsky, Andreas N.

    2016-01-01

    Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1–2 ms followed by jumps faster than 2–6 m s−1, leading to a macroscopically observed average velocity of 0.028–0.055 m s−1. The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound. PMID:27006774

  9. Temperature rise of the silicon mask-PMMA resist assembly during LIGA exposure.

    SciTech Connect

    Ting, Aili

    2004-10-01

    Deep X-ray lithography on PMMA resist is used in the LIGA process. The resist is exposed to synchrotron X-rays through a patterned mask and then is developed in a liquid developer to make high aspect ratio microstructures. This work addresses the thermal analysis and temperature rise of the mask-resist assembly during exposure at the Advanced Light Source (ALS) synchrotron. The concern is that the thermal expansion will lower the accuracy of the lithography. We have developed a three-dimensional finite-element model of the mask and resist assembly. We employed the LIGA exposure-development software LEX-D and the commercial software ABAQUS to calculate heat transfer of the assembly during exposure. The calculations of assembly maximum temperature have been compared with temperature measurements conducted at ALS. The temperature rise in the silicon mask and the mask holder comes directly from the X-ray absorption, but forced convection of nitrogen jets carry away a significant portion of heat energy from the mask surface, while natural convection plays a negligible role. The temperature rise in PMMA resist is mainly from heat conducted from the silicon substrate backward to the resist and from the mask plate through inner cavity air forward to the resist, while the X-ray absorption is only secondary. Therefore, reduction of heat flow conducted from both substrate and cavity air to the resist is essential. An improved water-cooling block is expected to carry away most heat energy along the main heat conductive path, leaving the resist at a favorable working temperature.

  10. Capacitive micromachined ultrasonic transducers with through-wafer interconnects

    NASA Astrophysics Data System (ADS)

    Zhuang, Xuefeng

    Capacitive micromachined ultrasonic transducer (CMUT) is a promising candidate for making ultrasound transducer arrays for applications such as 3D medical ultrasound, non-destructive evaluation and chemical sensing. Advantages of CMUTs over traditional piezoelectric transducers include low-cost batch fabrication, wide bandwidth, and ability to fabricate arrays with broad operation frequency range and different geometric configurations on a single wafer. When incorporated with through-wafer interconnects, a CMUT array can be directly integrated with a front-end integrated circuit (IC) to achieve compact packaging and to mitigate the effects of the parasitic capacitance from the connection cables. Through-wafer via is the existing interconnect scheme for CMUT arrays, and many other types of micro-electro-mechanical system (MEMS) devices. However, to date, no successful through-wafer via fabrication technique compatible with the wafer-bonding method of making CMUT arrays has been demonstrated. The through-wafer via fabrication steps degrade the surface conditions of the wafer, reduce the radius of curvature, thus making it difficult to bond. This work focuses on new through-wafer interconnect techniques that are compatible with common MEMS fabrication techniques, including both surface-micromachining and direct wafer-to-wafer fusion bonding. In this dissertation, first, a through-wafer via interconnect technique with improved characteristics is presented. Then, two implementations of through-wafer trench isolation are demonstrated. The through-wafer trench methods differ from the through-wafer vias in that the electrical conduction is through the bulk silicon instead of the conductor in the vias. In the first implementation, a carrier wafer is used to provide mechanical support; in the second, mechanical support is provided by a silicon frame structure embedded inside the isolation trenches. Both implementations reduce fabrication complexity compared to the through-wafer via process, and result in low series resistance and small parasitic capacitance. Two-dimensional CMUT arrays incorporating trench-isolated interconnects show high output pressure (2.9 MPa), wide bandwidth (95%), small pulse-echo amplitude variation (sigma = 6.6% of the mean amplitude), and excellent element yield (100% in 16x16-element array). Volumetric ultrasound imaging was demonstrated by flip-chip bonding one of the fabricated 2D arrays to a custom-designed IC. An important added benefit of the trench-isolated interconnect is the capability to realize flexible arrays. A flexible 2D CMUT array is demonstrated by filling the trenches with polydimethylsiloxane (PDMS). The results presented in this dissertation show that through-wafer trench-isolation is a viable solution for providing electrical interconnects to CMUT elements. These techniques are potentially useful for providing through-wafer interconnects to many other types of MEMS sensors and actuators because of their post-process nature. The results also show that 2D CMUT arrays fabricated using wafer-bonding deliver good performance.

  11. Wafer-level filling of microfabricated atomic vapor cells based on thin-film deposition and photolysis of cesium azide

    SciTech Connect

    Liew, Li-Anne; Moreland, John; Gerginov, Vladislav

    2007-03-12

    The thin-film deposition and photodecomposition of cesium azide are demonstrated and used to fill arrays of miniaturized atomic resonance cells with cesium and nitrogen buffer gas for chip-scale atomic-based instruments. Arrays of silicon cells are batch fabricated on wafers into which cesium azide is deposited by vacuum thermal evaporation. After vacuum sealing, the cells are irradiated with ultraviolet radiation, causing the azide to photodissociate into pure cesium and nitrogen in situ. This technology integrates the vapor-cell fabrication and filling procedures into one continuous and wafer-level parallel process, and results in cells that are optically transparent and chemically pure.

  12. Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

    2014-01-01

    This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

  13. Oral Immunization with Escherichia coli Expressing a Lipidated Form of LigA Protects Hamsters against Challenge with Leptospira interrogans Serovar Copenhageni

    PubMed Central

    Lourdault, Kristel; Wang, Long-Chieh; Vieira, Ana; Matsunaga, James; Melo, Rita; Lewis, Michael S.; Gomes-Solecki, Maria

    2014-01-01

    Leptospirosis is a potentially fatal zoonosis transmitted by reservoir host animals that harbor leptospires in their renal tubules and shed the bacteria in their urine. Leptospira interrogans serovar Copenhageni transmitted from Rattus norvegicus to humans is the most prevalent cause of urban leptospirosis. We examined L. interrogans LigA, domains 7 to 13 (LigA7-13), as an oral vaccine delivered by Escherichia coli as a lipidated, membrane-associated protein. The efficacy of the vaccine was evaluated in a susceptible hamster model in terms of the humoral immune response and survival from leptospiral challenge. Four weeks of oral administration of live E. coli expressing LigA7-13 improved survival from intraperitoneal (i.p.) and intradermal (i.d.) challenge by L. interrogans serovar Copenhageni strain Fiocruz L1-130 in Golden Syrian hamsters. Immunization with E. coli expressing LigA7-13 resulted in a systemic antibody response, and a significant LigA7-13 IgG level after the first 2 weeks of immunization was completely predictive of survival 28 days after challenge. As in previous LigA vaccine studies, all immunized hamsters that survived infection had renal leptospiral colonization and histopathological changes. In summary, an oral LigA-based vaccine improved survival from leptospiral challenge by either the i.p. or i.d. route. PMID:24478102

  14. Factors affecting the spatial distribution of the principal midgap donor in semi-insulating gallium arsenide wafers

    NASA Astrophysics Data System (ADS)

    Blakemore, J. S.; Dobrilla, P.

    1985-07-01

    The spatial distribution of an extrinsic variable across a wafer from a melt-grown crystal can provide clues concerning processes during and following solidification. This has encouraged several recent wafer mapping studies in semi-insulating GaAs: for dislocations, for the midgap native donor known as EL2, and for other flaw-related properties. This paper provides maps for the optically measurable neutral EL2 concentration in wafers from Czochralski-grown GaAs crystals. These figures illustrate comments about the factors believed to influence the magnitude and spatial distribution of that midgap flaw. Those factors include the melt stoichiometry and convection, any post-freezing stress, dislocation climb as plastic relief from such stress, and defect reactions in hot solid GaAs. A full accounting for these factors has been hampered by the continuing lack of a generally accepted atomic-scale model for EL2.

  15. Optima XE Single Wafer High Energy Ion Implanter

    SciTech Connect

    Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny

    2008-11-03

    The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

  16. Development of optical automatic positioning and wafer defect detection system

    NASA Astrophysics Data System (ADS)

    Tien, Chuen-Lin; Lai, Qun-Huang; Lin, Chern-Sheng

    2016-02-01

    The data of a wafer with defects can provide engineers with very important information and clues to improve the yield rate and quality in manufacturing. This paper presents a microscope automatic positioning and wafer detection system with human-machine interface based on image processing and fuzzy inference algorithms. In the proposed system, a XY table is used to move the position of each die on 6 inch or 8 inch wafers. Then, a high-resolution CCD and one set of two-axis optical linear encoder are used to accurately measure the position on the wafer. Finally, the developed human-machine interface is used to display the current position of an actual wafer in order to complete automatic positioning, and a wafer map database can be created. In the process of defect detection, CCD is used for image processing, and during preprocessing, it is required to filter noise, acquire the defect characteristics, define the defective template, and then take the characteristic points of the defective template as the reference input for fuzzy inference. A high-accuracy optical automatic positioning and wafer defect detection system is thus constructed. This study focused on automatic detection of spots, scratches, and bruises, and attempted to reduce the time to detect defective die and improve the accuracy of determining the defects of semiconductor devices.

  17. Analysis of the interdigitated back contact solar cells: The n-type substrate lifetime and wafer thickness

    NASA Astrophysics Data System (ADS)

    Zhang, Wei; Chen, Chen; Jia, Rui; Sun, Yun; Xing, Zhao; Jin, Zhi; Liu, Xin-Yu; Liu, Xiao-Wen

    2015-10-01

    The n-type silicon integrated-back contact (IBC) solar cell has attracted much attention due to its high efficiency, whereas its performance is very sensitive to the wafer of low quality or the contamination during high temperature fabrication processing, which leads to low bulk lifetime τbulk. In order to clarify the influence of bulk lifetime on cell characteristics, two-dimensional (2D) TCAD simulation, combined with our experimental data, is used to simulate the cell performances, with the wafer thickness scaled down under various τbulk conditions. The modeling results show that for the IBC solar cell with high τbulk, (such as 1 ms-2 ms), its open-circuit voltage Voc almost remains unchanged, and the short-circuit current density Jsc monotonically decreases as the wafer thickness scales down. In comparison, for the solar cell with low τbulk (for instance, < 500 μs) wafer or the wafer contaminated during device processing, the Voc increases monotonically but the Jsc first increases to a maximum value and then drops off as the wafer’s thickness decreases. A model combing the light absorption and the minority carrier diffusion is used to explain this phenomenon. The research results show that for the wafer with thinner thickness and high bulk lifetime, the good light trapping technology must be developed to offset the decrease in Jsc. Project supported by the Chinese Ministry of Science and Technology Projects (Grant Nos. 2012AA050304 and Y0GZ124S01), the National Natural Science Foundation of China (Grant Nos. 11104319, 11274346, 51202285, 51402347, and 51172268), and the Fund of the Solar Energy Action Plan from the Chinese Academy of Sciences (Grant Nos. Y3ZR044001 and Y2YF014001).

  18. The uses of Man-Made diamond in wafering applications

    NASA Technical Reports Server (NTRS)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  19. Applications of atomic force microscopy for silicon wafer characterization

    SciTech Connect

    Suhren, M.; Graef, D.; Schmolke, R.; Piontek, H.; Wagner, P.

    1996-12-01

    AFM (Atomic Force Microscopy) is a highly sensitive tool for the analysis of the microroughness of Si wafers and for the investigation of crystal defects. AFM images of atomic steps were used for verification of the vertical AFM calibration on slightly misoriented Si(111) wafers after chemical etching and epitaxial deposition. The roughness analysis of etched, polished and epitaxial Si(100) wafers shows a reduction of the surface roughness by chemomechanical polishing by more than two orders of magnitude compared to an etched surface. The morphology of crystal originated particles on Si(100) appears as smooth surface depression after polishing and sharply defined pit after SCI treatment.

  20. On-Wafer Testing of Circuits Through 220 GHz

    NASA Technical Reports Server (NTRS)

    Gaier, Todd; Samoska, Lorene; Oleson, Charles; Boll, Greg

    1999-01-01

    We have jointly developed the capability to perform on-wafer s-parameter and noise figure measurements through 220 GHz. S-parameter test sets have been developed covering full waveguide bands of 90-140 GHz (WR-08) and 140-220 GHz (WR-05). The test sets have been integrated with coplanar probes to allow accurate measurements on-wafer. We present the design and performance of the test sets and wafer probes. We also present calibration data as well as measurements of active circuits at frequencies as high as 215 GHz.

  1. Potentials of LiGa(S 1-xSe x) 2 mixed crystals for optical frequency conversion

    NASA Astrophysics Data System (ADS)

    Huang, J.-J.; Atuchin, V. V.; Andreev, Yu. M.; Lanskii, G. V.; Pervukhina, N. V.

    2006-07-01

    Phase-matching conditions are considered for second harmonic generation (SHG) and optical parametric generation in LiGa(S 1-xSe x) 2 mixed crystals as a function of chemical composition under the supposition of linear dependence of refractive indices on x. It has been shown that by tuning x over the range 0-1 the SHG can be realized in XY plane for ?=2.1-7.8 ?m pumping at ?=43-90, in YZ plane for ?=2.1-2.2 and 4.8-7.8 ?m pumping at ?=0-90, and in XZ plane for ?=1.6-11.7 ?m pumping at ?=0-57. The LiGa(S 1-xSe x) 2 solid solutions are also attractive for design of tunable femtosecond pulse frequency converters with saving of pump pulse duration.

  2. Thermal spray and cold spray analysis of density, porosity, and tensile Specimens for use with LIGA applications

    SciTech Connect

    DECKER,MERLIN K.; SMITH,MARK F.

    2000-02-01

    This analysis provides a preliminary investigation into using Twin-Wire Arc Thermal Spray and Cold Spray as material deposition processes for LIGA applications. These spray material processes were studied to make an initial determination of their potential as alternatives to producing mechanical parts via the electroplating process. Three materials, UltraMachinable{reg_sign} Stainless Steel, BondArc{reg_sign}, and aluminum, were sprayed using Thermal Spray. Only aluminum was sprayed using the Cold Spray process. Following the spray procedure, the test specimens were released from a copper mold and then tested. Three tests, density, tensile strength, and porosity, were performed on the specimens to determine the spray effect on material properties. Twin-Wire Arc Thermal Spray did not demonstrate adequate deposition properties and does not appear to be a good process candidate for LIGA. However, Cold Spray yielded better density results and warrants further investigation to analyze the minimum feature size produced by the process.

  3. Extraction and Analysis of Noise Parameters of On Wafer HEMTs up to 26.5 GHz

    SciTech Connect

    Caddemi, Alina; Crupi, Giovanni; Macchiarella, Alessio

    2009-04-23

    This paper presents a procedure for extracting the four noise parameters of on wafer scaled HEMTs based on AlGaAs/GaAs heterostructure. This procedure relies on 50-{omega} noise figure measurements up to 26.5 GHz by determining the equivalent temperatures associated to the intrinsic resistances of the small signal equivalent circuit. The non-quasi-static effect associated to the gate-drain resistance R{sub gd} is accounted for by the noise model. A good agreement between measured and simulated noise figure is obtained and scaling of the noise parameters is reported.

  4. Arthroscopic wafer procedure for ulnar impaction syndrome.

    PubMed

    Colantoni, Julie; Chadderdon, Christopher; Gaston, R Glenn

    2014-02-01

    Ulnar impaction syndrome is abutment of the ulna on the lunate and triquetrum that increases stress and load, causing ulnar-sided wrist pain. Typically, ulnar-positive or -neutral variance is seen on a posteroanterior radiograph of the wrist. The management of ulnar impaction syndrome varies from conservative, symptomatic treatment to open procedures to shorten the ulna. Arthroscopic management has become increasingly popular for management of ulnar impaction with ulnar-positive variance of less than 3 mm and concomitant central triangular fibrocartilage complex tears. This method avoids complications associated with open procedures, such as nonunion and symptomatic hardware. The arthroscopic wafer procedure involves debridement of the central triangular fibrocartilage complex tear, along with debridement of the distal pole of the ulna causing the impaction. Debridement of the ulna arthroscopically is taken down to a level at which the patient is ulnar neutral or slightly ulnar negative. Previous studies have shown good results with relief of patient symptoms while avoiding complications seen with open procedures. PMID:24749031

  5. Arthroscopic Wafer Procedure for Ulnar Impaction Syndrome

    PubMed Central

    Colantoni, Julie; Chadderdon, Christopher; Gaston, R. Glenn

    2014-01-01

    Ulnar impaction syndrome is abutment of the ulna on the lunate and triquetrum that increases stress and load, causing ulnar-sided wrist pain. Typically, ulnar-positive or -neutral variance is seen on a posteroanterior radiograph of the wrist. The management of ulnar impaction syndrome varies from conservative, symptomatic treatment to open procedures to shorten the ulna. Arthroscopic management has become increasingly popular for management of ulnar impaction with ulnar-positive variance of less than 3 mm and concomitant central triangular fibrocartilage complex tears. This method avoids complications associated with open procedures, such as nonunion and symptomatic hardware. The arthroscopic wafer procedure involves debridement of the central triangular fibrocartilage complex tear, along with debridement of the distal pole of the ulna causing the impaction. Debridement of the ulna arthroscopically is taken down to a level at which the patient is ulnar neutral or slightly ulnar negative. Previous studies have shown good results with relief of patient symptoms while avoiding complications seen with open procedures. PMID:24749031

  6. Low-temperature full wafer adhesive bonding

    NASA Astrophysics Data System (ADS)

    Niklaus, Frank; Enoksson, Peter; Klvesten, Edvard; Stemme, Gran

    2001-03-01

    We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 m and 18 m. The tested polymer materials were benzocyclobutene (BCB) from Dow Chemical, a negative photoresist (ULTRA-i 300) and a positive photoresist (S1818) from Shipley, a polyimide (HTR3) from Arch Chemical and two different polyimides (PI2555 and PI2610) from DuPont. The polymer material, the bonding pressure and the pre-curing time and temperature for the polymer significantly influence void formation at the bond interface. High bonding pressure and optimum pre-curing times/temperatures counteract void formation. We present the process parameters to achieve void-free bonding with the BCB coating and with the ULTRA-i 300 photoresist coating as adhesive materials. Excellent void-free and strong bonds have been achieved by using BCB as the bonding material which requires a minimum bonding temperature of 180 C.

  7. Phoradendron liga (Gill. ex H. et A.) Eichl. (Viscaceae) used in folk medicine: anatomical, phytochemical, and immunochemical studies.

    PubMed

    Varela, Beatriz G; Fernández, Teresa; Ricco, Rafael A; Zolezzi, Paula Cerdá; Hajos, Silvia E; Gurni, Alberto A; Alvarez, Elida; Wagner, Marcelo L

    2004-09-01

    Phoradendron liga (Gill. ex H. et A.) Eichl. is a Viscaceae widely distributed in Argentina. It has been commonly used in folk medicine as a substitute of the European mistletoe (Viscum album L.) to decrease high blood pressure due to their external similarity. In this study, the anatomical features as well as micromolecular and macromolecular analysis of this species are reported. Anatomical study has shown that Phoradendron liga presents as anatomic features: papillous cuticle, clusters in leaves and stems, and isodiametric stone cells only in stems. The analysis of flavonoids showed that this species produces C-glycosylflavones and 3-desoxyproanthocyanidins. Protein study showed a protein pattern with components ranging from 14 to 90 kDa and the presence of related epitopes between the species was demonstrated by cross recognition using anti-Phoradendron and anti-Viscum antisera of both species by Western blot assay. In addition, a galactose specific lectin (L-Phl) was isolated form Phoradendron liga extracts. These results are part of a comprehensive project on Argentine hemiparasite species destinated to be applied to quality control of commercial samples and disclosed their potential use as a potential source for immunomodulatory compounds. PMID:15261970

  8. Surface defects in GaAs wafer processes

    NASA Astrophysics Data System (ADS)

    Matsushita, H.; Ishida, M.; Kikawa, J.

    1990-06-01

    The causes of micro- and macro-irregularities observed on GaAs(100) polished wafers were investigated. From the results, the wafer processes were improved so that a high-quality surface was obtained without orange peel, haze, or pits. For 3-inch wafers the flatness was improved to less than 2 ?m in TTV and the warp to less than 5 ?m. Improvements in the wafer processes were: development of a better polishing solution, filtering of this solution with maintenance of the pad conditions, thereby eliminating scratches, annealing at high temperature to eliminate pits, advances in slicing and lapping to reduce warp, and three-stage double-sided polishing to eliminate dimples and to improve TTV.

  9. Estimation of wafer warpage profile during thermal processing in microlithography

    NASA Astrophysics Data System (ADS)

    Tay, Arthur; Ho, Weng Khuen; Hu, Ni; Chen, Xiaoqi

    2005-07-01

    Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability, and linewidth control in various processing steps. Early detection will minimize cost and processing time. We propose in this article an in situ approach for estimating wafer warpage profile during the thermal processing steps in the microlithography process. The average air gap between wafer and bake-plate at multiple locations of a multizone bake-plate can be estimated and a profile can be obtained by joining these points. Experimental results demonstrate the feasibility and repeatability of the approach. This is a major improvement over our previously developed approach, in which only the average warpage could be obtained. The proposed approach requires no extra processing steps and time, as compared to conventional off-line methods.

  10. Infrared backwards laser melting of a silicon wafer

    NASA Astrophysics Data System (ADS)

    Lill, Patrick C.; Khler, Jrgen R.

    2015-11-01

    We investigate a method for melting a silicon wafer's rear side with a pulsed infrared laser (1064 nm) impinging onto the front side. The targeted application for this method is deep laser doping. Our numerical model simulates the evolution of the two-dimensional temperature distribution in the wafer caused by pulsed infrared laser irradiation. The model incorporates the temperature dependent material properties of silicon and the enthalpy-based phase change by means of finite volumes. The simulation yields spacial temperature distributions of the wafer's cross section at defined time steps. We obtain the laser parameters for a continuous melt depth of 40 m in a 200 m thick wafer from the analysis of the simulation results.

  11. Proceedings of the Low-Cost Solar Array Wafering Workshop

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1982-01-01

    The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

  12. Efficient data transmission from silicon wafer strip detectors

    SciTech Connect

    Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

    1991-12-31

    An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

  13. Particle-wafer interactions in semiaqueous silicon cleaning systems

    NASA Astrophysics Data System (ADS)

    Hupka, Lukasz

    During the semiconductor chip manufacturing process, a silicon wafer goes through a number of cycles in both hydrophilic and hydrophobic environments. As silicon chips become more sophisticated, the manufacturing process becomes more involved and new challenges are imposed by size reduction, increase in the aspect ratio and the formation of multilayer structures. Wafer cleaning processes emerge several times in one manufacturing cycle. By rule of thumb, it is necessary to remove wafer contamination by particles which are half of a feature size. This is an enormous challenge, keeping in mind that currently wafer structures are of nanometer size. The cleaning procedures which worked for the last 40 years are becoming ineffective and obsolete. The industry calls for more efficient cleaning procedures in terms of particle contamination removal, and at the same time less aggressive procedures to prevent damage/dissolution of the fragile and narrow wafer structures. Atomic Force Microscopy (AFM), besides being an imaging tool with nano resolution, proves to be an indispensable instrument to characterize interaction forces, lateral forces, and adhesion between micron and submicron contaminant particles and the wafer surfaces both in air and liquid. Using the AFM colloidal probe technique interaction forces were measured between a contaminant particle and a wafer surface. These measurements were done for the silica---silica hydrophilic system and for the silanated silica---silanated silica hydrophobic system. The influence of the nonaqueous component in semiconductor wafer cleaning solution on interaction forces was also investigated under both hydrophilic and hydrophobic conditions. In addition the effect of particle size on the interaction forces as well as particle removal rate under both conditions is addressed. While force/radius normalization of measured interaction forces works great for hydrophilic systems, it was found to significantly underestimate the influence of particle size in a hydrophobic system. A correction to the normalization of hydrophobic forces with respect to particle size has been proposed. The issue of nanobubble formation at hydrophobic surfaces under certain conditions has been investigated. The nanobubbles were observed under AFM and characterized with respect to size, shape and Laplace pressure. As wafer structures become smaller and more fragile, it is crucial to confront the impact of different manufacturing steps, including the process of cleaning, with the strength of wafer structures. The force required to remove a contaminant should be close to the force that damages a structure in order to maximize particle removal efficiency, but not higher than this force in order to avoid structure damage. Such measurements have been done with the AFM using lateral force mode of operation. Understanding and manipulation of the interaction forces has led to the design of novel semiconductor wafer cleaning solutions.

  14. Optimized features allocation technique for improved automated alignment of wafers

    NASA Astrophysics Data System (ADS)

    Parshin, Michael; Zalevsky, Zeev

    2009-02-01

    In this paper we present a new fuzzy logic based approach for automatic optimized features allocation. The technique is used for improved automatic alignment and classification of silicon wafers and chips that are used in the electronic industry. The proposed automatic image processing approach was realized and experimentally demonstrated in real industrial application with typical wafers. The automatic features allocation and grading supported the industrial requirements and could replace human expert based inspection that currently is performed manually.

  15. Stress rate and proof-testing of silicon wafers

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1985-01-01

    Fracture mechanics test methods were applied to evaluate the proof-test characteristics of single-crystal silicon wafers. The results indicate that the strength distribution of silicon wafers is truncated by proof-testing. No subcritical crack growth occurred during proof-loading, as inferred from the lack of a stress-rate effect on strength. Mechanical proof-testing appears to be an effective method for eliminating weak samples before cell processing.

  16. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2008-10-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  17. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  18. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-03-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  19. Strategy optimization for mask rule check in wafer fab

    NASA Astrophysics Data System (ADS)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  20. Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis

    SciTech Connect

    Tobin, K.W.

    2003-05-22

    This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

  1. Assessment of patients quality of life after haemorrhoidectomy using the LigaSure device

    PubMed Central

    Leksowski, Krzysztof

    2015-01-01

    Introduction Haemorrhoids are small anatomical structures within the anal canal that are involved in the proper functioning of the lower gastrointestinal tract. Factors favouring the development of haemorrhoidal disease are insufficient physical activity, prolonged sitting and hence a shortage of physical activity, as well as poor diet which lacks adequate amounts of fibre. The main symptom of this disease is bleeding with bright red blood just after defecation. Haemorrhoidal disease occurs when the ligamentous apparatus comes loose and the internal haemorrhoidal plexus translocates down, whereas haemorrhoids enlarge and move out of the anal canal. Haemorrhoidal disease treatment includes conservative, instrumental and surgical therapy. Aim To assess treatment and satisfaction in particular life domains after haemorrhoidectomy. Material and methods The research was undertaken in the General, Thoracic and Vascular Surgery Clinic of the 10th Military Clinical Hospital with Polyclinic in Bydgoszcz among 50 patients treated due to haemorrhoids and operated on in the period 20072008. The study evaluated quality of patients life after haemorrhoidectomy by Ferguson's method using a LigaSure appliance. Results The study investigated whether patients perceived a difference before and after surgery. The research proved that patients can describe disease symptoms and know the risk factors for haemorrhoids. In the studied group patients are able to describe characteristic signs of haemorrhoidal disease and also indicate differences in everyday life before and after the surgery. They can also describe and classify the pain before and 1 year after the haemorrhoidectomy, which was statistically significantly lower already 3 months after the operation. Conclusions Conducted examinations showed that sick people in the precise way were able to determine manifestations and know risk factors of the prevalence of disease hemorrhoidal. Operated sick people indicated the difference in quality of the life both before, as well as after the undergone treatment. After the operation of the haemorrhoids with method of Ferguson using LigaSure apparatus operated sick persons could distinguish and classify pain before the treatment as well as in a year after which was statistically characteristically lower already after three months from treatment. PMID:25960796

  2. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  3. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  4. High Throughput, Noncontact System for Screening Silicon Wafers Predisposed to Breakage During Solar Cell Production

    SciTech Connect

    Sopori, B.; Rupnowski, P.; Basnyat, P.; Mehta, V.

    2011-01-01

    We describe a non-contact, on-line system for screening wafers that are likely to break during solar cell/module fabrication. The wafers are transported on a conveyor belt under a light source, which illuminates the wafers with a specific light distribution. Each wafer undergoes a dynamic thermal stress whose magnitude mimics the highest stress the wafer will experience during cell/module fabrication. As a result of the stress, the weak wafers break, leaving only the wafers that are strong enough to survive the production processes. We will describe the mechanism of wafer breakage, introduce the wafer system, and discuss the results of the time-temperature (t-T) profile of wafers with and without microcracks.

  5. The influence of feature sidewall tolerance on minimum absorber thickness for LIGA x-ray masks

    SciTech Connect

    S. K. Griffiths; J. M. Hruby; A. Ting

    1999-02-01

    Minimizing mask absorber thickness is an important practical concern in producing very small features by the LIGA process. To assist in this minimization, the authors have developed coupled numerical models describing both the exposure and development of a thick PMMA resist. The exposure model addresses multi-wavelength, one-dimensional x-ray transmission through multiple beam filters, through the mask substrate and absorber, and the subsequent attenuation and photon absorption in the PMMA resist. The development model describes one-dimensional dissolution of a feature and its sidewalls, taking into account the variation in absorbed dose through the PMMA thickness. These exposure and development models are coupled in a single interactive code, permitting the automated adjustment of mask absorber thickness to yield a prescribed sidewall taper or dissolution distance. They have used this tool to compute the minimum required absorber thickness yielding a prescribed sidewall tolerance for exposures performed at the ALS, SSRL and NSLS synchrotron sources. Results are presented as a function of the absorbed dose for a range of the prescribed sidewall tolerance, feature size, PMMA thickness, mask substrate thickness and the development temperature.

  6. Electrocautery versus Ultracision versus LigaSure in Surgical Management of Hyperhidrosis.

    PubMed

    Divisi, Duilio; Di Leonardo, Gabriella; De Vico, Andrea; Crisci, Roberto

    2015-12-01

    Objective?The aim of the study was to evaluate the sympathectomy procedures for primary hyperhidrosis in terms of complications and effectiveness. Methods?From January 2010 to September 2012 we performed 130 sympathectomies in 65 patients, 27 males (42%) and 38 females (58%). Electrocoagulation was used in 20 procedures (15%), ultrasonic scalpel in 54 (42%), and radiofrequency dissector in 56 (43%). Seven patients (11%) underwent bilateral sympathectomy in the same surgical session, while in 58 (89%) the right surgical approach was delayed 30 days from the first procedure. Results?We noticed 12 complications (9%): (a) chest pain in 6 patients (4 with electrocoagulation, 1 with ultrasonic scalpel, and 1 with radiofrequency dissector), which disappeared in 20??1 day; (b) paresthesias in 3 electrocoagulation patients, was solved in 23??5 days; (c) bradycardia in 1 ultrasonic patient, normalized in 4th postoperative hour; (d) unilateral relapse in 2 electrocoagulation patients after the second side approach, positively treated in 1 patient by resurgery in video-assisted thoracoscopy (VAT). The quality-adjusted life year and the quality of life evaluation revealed a statistically significant improvement (p?=?0.02) in excessive sweating and general satisfaction after surgery, with Ultracision and LigaSure showing better findings than electrocoagulation. Conclusion?The latest generation devices offered greater efficacy in the treatment of hyperhidrosis, minimizing complications and facilitating the resumption of normal work and social activity of patients. PMID:25984779

  7. Critical dimension control for prevention of wafer-to-wafer and module-to-module difference

    NASA Astrophysics Data System (ADS)

    Deguchi, Masatoshi; Tanaka, Kouichirou; Nagatani, Naohiko; Miyata, Yuichiro; Yamashita, Mitsuo; Minami, Yoshiaki; Matsuyama, Yuji

    2004-05-01

    In recent years, the worldwide semiconductor market has changed drastically, and it is expected that the digital device market will continue to expand towards general consumer electronics and away from the personal computers that have been the core of the market. To accommodate this shift, the new devices will be diversified with improved productivity, higher process yield, and higher precision. Clean Track (LITHIUS) design also has been changed drastically to maintain equal productivity with new high throughput exposure equipment. Design changes include increasing the number of processing chambers by stacking reduced size modules in order to meet high throughput and small footprint requirements. However, this design change concept raises concerns about increased wafer-to-wafer difference (WtW) and module-to-module different (MtM). These variations can result in lower process yield and have a negative effect on design rule shrinkage. The primary causes of WtW difference and MtM difference stem from minute module hardware variations, module height differences, and module parameter adjustment differences during the installation of the tool. Previous Clean Track development focused mainly on reduction of module hardware difference as an approach to reduce WtW variation. However, to further improve lot level uniformity, it is necessary to reduce module height difference factors within the system and module adjustment disparities such as plate temperature calibrations. Highly temperature sensitive ArF processes have necessitated precise manual PEB temperature adjustments. These calibrations are labor intensive and require many field hours to ensure optimal CD uniformity. Therefore, an auto temperature measurement and adjustment tool is developed to eliminate the human error due to manual adjustment and minimize adjustment time. In order to meet demands for design rules shrinkage and increased process uniformity we minimized the WtW and MtM difference by using thermal history adjustment and transfer time control. This method is also used to improve within wafer CD control technology resulting in a more stable process. In this report, we introduce improved features to reduce WtW and MtM variation and their effect on CD uniformity with 193nm (ArF) resist and 248nm (KrF) resist.

  8. Fine Mapping of the Interaction between C4b-Binding Protein and Outer Membrane Proteins LigA and LigB of Pathogenic Leptospira interrogans.

    PubMed

    Breda, Leandro C D; Hsieh, Ching-Lin; Castiblanco Valencia, Mnica M; da Silva, Ludmila B; Barbosa, Angela S; Blom, Anna M; Yung-Fu, Chang; Isaac, Lourdes

    2015-10-01

    The complement system consists of more than 40 proteins that participate in the inflammatory response and in pathogen killing. Complement inhibitors are necessary to avoid the excessive consumption and activation of this system on host cells. Leptospirosis is a worldwide zoonosis caused by spirochetes from the genus Leptospira. Pathogenic leptospires are able to escape from complement activation by binding to host complement inhibitors Factor H [FH] and C4b-binding protein (C4BP) while non-pathogenic leptospires are rapidly killed in the presence of fresh serum. In this study, we demonstrate that complement control protein domains (CCP) 7 and 8 of C4BP ?-chain interact with the outer membrane proteins LcpA, LigA and LigB from the pathogenic leptospire L. interrogans. The interaction between C4BP and LcpA, LigA and LigB is sensitive to ionic strength and inhibited by heparin. We fine mapped the LigA and LigB domains involved in its binding to C4BP and heparin and found that both interactions are mediated through the bacterial immunoglobulin-like (Big) domains 7 and 8 (LigA7-8 and LigB7-8) of both LigA and LigB and also through LigB9-10. Therefore, C4BP and heparin may share the same binding sites on Lig proteins. PMID:26517116

  9. Fine Mapping of the Interaction between C4b-Binding Protein and Outer Membrane Proteins LigA and LigB of Pathogenic Leptospira interrogans

    PubMed Central

    Breda, Leandro C. D.; Hsieh, Ching-Lin; Castiblanco Valencia, Mónica M.; da Silva, Ludmila B.; Barbosa, Angela S.; Blom, Anna M.; Yung-Fu, Chang; Isaac, Lourdes

    2015-01-01

    The complement system consists of more than 40 proteins that participate in the inflammatory response and in pathogen killing. Complement inhibitors are necessary to avoid the excessive consumption and activation of this system on host cells. Leptospirosis is a worldwide zoonosis caused by spirochetes from the genus Leptospira. Pathogenic leptospires are able to escape from complement activation by binding to host complement inhibitors Factor H [FH] and C4b-binding protein (C4BP) while non-pathogenic leptospires are rapidly killed in the presence of fresh serum. In this study, we demonstrate that complement control protein domains (CCP) 7 and 8 of C4BP α-chain interact with the outer membrane proteins LcpA, LigA and LigB from the pathogenic leptospire L. interrogans. The interaction between C4BP and LcpA, LigA and LigB is sensitive to ionic strength and inhibited by heparin. We fine mapped the LigA and LigB domains involved in its binding to C4BP and heparin and found that both interactions are mediated through the bacterial immunoglobulin-like (Big) domains 7 and 8 (LigA7-8 and LigB7-8) of both LigA and LigB and also through LigB9-10. Therefore, C4BP and heparin may share the same binding sites on Lig proteins. PMID:26517116

  10. Comparison and Efficacy of LigaSure and Rubber Band Ligature in Closing the Inflamed Cecal Stump in a Rat Model of Acute Appendicitis

    PubMed Central

    Yeh, Chun-Chieh; Jan, Chia-Ing; Yang, Horng-Ren; Jeng, Long-Bin; Su, Wen-Pang

    2015-01-01

    Safety of either LigaSure or rubber band in closing inflamed appendiceal stump in acute appendicitis has been less investigated. In this study, cecal ligation followed by resecting inflamed cecum was performed to mimic appendectomy in a rat model of acute appendicitis. Rats were sacrificed immediately (Group A) and 7 days (Group B) after cecal resection, respectively. The cecal stumps were closed by silk ligature (S), 5 mm LigaSure (L), or rubber band (R). Seven days after cecal resection, the LigaSure (BL) and silk subgroups (BS) had significantly less intra-abdominal adhesion and better laparotomy wound healing than rubber band subgroup (BR). The initial bursting pressure at cecal stump was comparable among the three methods; along with tissue healing process, both BL and BS provided a higher bursting pressure than BR 7 days after appendectomy. BL subgroup had more abundant hydroxyproline deposition than BS and BR subgroup. Furthermore, serum TNF-α in BR group kept persistently increasing along with time after cecal resection. Thus, the finding that LigaSure but not rubber band is safe in sealing off the inflamed cecal stump in rat model of acute appendicitis suggests the possibility of applying LigaSure for appendectomy via single port procedure or natural orifice transluminal endoscopic surgery (NOTES). PMID:25699264

  11. Comparison and efficacy of LigaSure and rubber band ligature in closing the inflamed cecal stump in a rat model of acute appendicitis.

    PubMed

    Yeh, Chun-Chieh; Jan, Chia-Ing; Yang, Horng-Ren; Huang, Po-Han; Jeng, Long-Bin; Su, Wen-Pang; Chen, Hui-Chen

    2015-01-01

    Safety of either LigaSure or rubber band in closing inflamed appendiceal stump in acute appendicitis has been less investigated. In this study, cecal ligation followed by resecting inflamed cecum was performed to mimic appendectomy in a rat model of acute appendicitis. Rats were sacrificed immediately (Group A) and 7 days (Group B) after cecal resection, respectively. The cecal stumps were closed by silk ligature (S), 5 mm LigaSure (L), or rubber band (R). Seven days after cecal resection, the LigaSure (BL) and silk subgroups (BS) had significantly less intra-abdominal adhesion and better laparotomy wound healing than rubber band subgroup (BR). The initial bursting pressure at cecal stump was comparable among the three methods; along with tissue healing process, both BL and BS provided a higher bursting pressure than BR 7 days after appendectomy. BL subgroup had more abundant hydroxyproline deposition than BS and BR subgroup. Furthermore, serum TNF-? in BR group kept persistently increasing along with time after cecal resection. Thus, the finding that LigaSure but not rubber band is safe in sealing off the inflamed cecal stump in rat model of acute appendicitis suggests the possibility of applying LigaSure for appendectomy via single port procedure or natural orifice transluminal endoscopic surgery (NOTES). PMID:25699264

  12. Post exposure bake unit equipped with wafer-shape compensation technology

    NASA Astrophysics Data System (ADS)

    Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

    2007-03-01

    In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

  13. Scale

    ERIC Educational Resources Information Center

    Schaffhauser, Dian

    2009-01-01

    The common approach to scaling, according to Christopher Dede, a professor of learning technologies at the Harvard Graduate School of Education, is to jump in and say, "Let's go out and find more money, recruit more participants, hire more people. Let's just keep doing the same thing, bigger and bigger." That, he observes, "tends to fail, and fail

  14. Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering

    NASA Astrophysics Data System (ADS)

    Chen, Po-Ying; Tsai, Ming-Hsing; Yeh, Wen-Kuan; Jing, Ming-Haw; Chang, Yukon

    2009-12-01

    Silicon wafer breakage has become a major concern for all semiconductor fabrication lines because it is brittle, and thus high stresses are easily induced in its manufacture. The production cost of devices significantly increases even for a breakage loss of a few percent if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant. In this investigation, we develop a brand new approach to reducing breakage by using a charge-coupled device (CCD) to capture the cross-section image of the wafer at its edge; the data measured at the edge can be used to determine overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength, and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in the wafer bulk before failure. We also describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unidentified causes. Our analysis gives the optimal front size (B1), edge widths (A1,A2), and bevel angle (?) for the edge profiles of wafers to prevent wafer breakage. Briefly, when a suitable material and suitable process control approaches are utilized, silicon wafer breakage can be prevented. This is the first investigation providing evidence that whole-wafer strength is an important issue. We present a physical model to explain why wafer fracture has become an increasingly serious problem as the diameter of wafers has increased. The control of wafer edge geometry has been demonstrated to be an effective means of protecting wafers with large diameters against breakage. This model reveals that the breakage rate of wafers can be reduced by controlling the uniformity of the differences between the front size and the rear edge widths during the wafer manufacturing process.

  15. Quantitative phase measurement for wafer-level optics

    NASA Astrophysics Data System (ADS)

    Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

    2015-07-01

    Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

  16. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    NASA Astrophysics Data System (ADS)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  17. Enhancing direct laser patterning of Si wafers by polystyrene films

    NASA Astrophysics Data System (ADS)

    Haghizadeh, Anahita; Yang, Haeyeon; Peterson, Jacob; Kellar, Jon J.

    2015-03-01

    Interferential irradiation of high power laser pulses can produce arrays of periodic nanostructures on surfaces. Patterning Si wafers directly by high power laser pulses indicates that the trench depth is limited to the laser pulse intensity. We present our recent studies on direct laser patterning of polystyrene coated Si wafers, which are irradiated interferentially by high power laser pulses. Polystyrene films were formed on silicon wafers with thickness controlled based on a previously developed method. Interferential irradiations of laser pulses are applied on the polystyrene coated Si wafer. The laser pulse intensities are varied along with other interferential parameters such as interference angle and laser wavelengths of 532, 355, and 266nm. The polystyrene film is dissolved to expose the patterned Si surfaces. Atomic force microscopy (AFM) images from the patterned Si surfaces indicate that the area covered with the films has trenches deeper than those on bare Si wafers patterned at the same laser intensity. Furthermore, studies of AFM images indicate that the thicker the polystyrene coating, the deeper the trenches that are produced by direct laser patterning Si surfaces. The enhancement and modification due to polymer films may enhance the security features by improving the quality of holograms.

  18. Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.

    2004-01-01

    An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

  19. Bubble-Free Silicon Wafer Bonding in a Non-Cleanroom Environment

    NASA Astrophysics Data System (ADS)

    Stengl, R.; Ahn, K.-Y.; Gsele, U.

    1988-12-01

    Bubble-free bonding of 4-inch silicon wafers on either silicon or quartz wafers is achieved outside a cleanroom. Two wafers are stacked horizontally in a rack with the two mirror-polished surfaces facing each other. In order to avoid wafer contact during hydrophilization, cleaning, and drying, the wafers are separated in the rack by teflon spacers introduced at the wafer edges. After drying the wafers by a spin dryer, the spacers are removed and bonding occurs. Using this procedure we are also able to monitor the bonding process between quartz and silicon wafers at different temperatures. We find that the initial wafer bonding process at room temperature stops operating at temperatures above 200C.

  20. A novel post exposure bake technique to improve CD uniformity over product wafers

    NASA Astrophysics Data System (ADS)

    Takeishi, Tomoyuki; Hayasaki, K.; Shibata, Tsuyoshi

    2005-05-01

    The impact of wafer warpage on critical dimension (CD) control is getting larger in ArF lithography. The product wafers with stacked films are warped due to the stress caused by the difference in the film stack structure between the top side and the back side of the wafers. A typical warpage of the product wafers is of convex shape, and the amount of the warpage is larger than 50 ?m for 200mm wafer. On the other hand, proximity bake method is widely used in the Post Exposure Bake (PEB). When the warped wafer is placed on the hot plate, the gap between the wafer and the hot plate varies across the wafer. That is, the temperature of the wafer center is lower than that of wafer edge. Such a temperature variation affects CD uniformity within wafer. In particular the fact is obvious in ArF chemical amplified resist because PEB sensitivity of ArF resist is larger than 5nm/degree. In this study we optimize PEB zone temperature within wafer to suit the wafer warpage. This method is based on controlling zone temperature of the PEB hot plate with concentrically divided heaters. We carry out that the CD uniformity for the warped wafer is improved by 70% compared with the conventional process.

  1. Optical evaluation of ingot fixity in semiconductor wafer slicing

    NASA Astrophysics Data System (ADS)

    Ng, T. W.; Nallathamby, R.

    2004-11-01

    The fixity of an ingot may greatly affect the quality of wafers produced during a wire saw process and improved mechanical clamping is a means for improving ingot fixity. Here, an optical technique that is based on laser beam deflection is described. The technique was demonstrated on ingot assemblies subjected to impulse loads within a prescribed range using an original and improved clamping system. The technique revealed that the ingot assembly had lower degrees of mean displacement and standard displacement deviation under the improved clamping system. The data on warp obtained from the actual production of wafers corroborates this finding. The technique described is an effective method of quantitatively evaluating the fixity of ingots in a wafer wire saw process.

  2. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  3. Characterizing SOI Wafers By Use Of AOTF-PHI

    NASA Technical Reports Server (NTRS)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  4. Wafer Fusion for Integration of Semiconductor Materials and Devices

    SciTech Connect

    Choquette, K.D.; Geib, K.M.; Hou, H.Q.; Allerman, A.A.; Kravitz, S.; Follstaedt, D.M.; Hindi, J.J.

    1999-05-01

    We have developed a wafer fusion technology to achieve integration of semiconductor materials and heterostructures with widely disparate lattice parameters, electronic properties, and/or optical properties for novel devices not now possible on any one substrate. Using our simple fusion process which uses low temperature (400-600 C) anneals in inert N{sub 2} gas, we have extended the scope of this technology to examine hybrid integration of dissimilar device technologies. As a specific example, we demonstrate wafer bonding vertical cavity surface emitting lasers (VCSELs) to transparent AlGaAs and GaP substrates to fabricate bottom-emitting short wavelength VCSELs. As a baseline fabrication technology applicable to many semiconductor systems, wafer fusion will revolutionize the way we think about possible semiconductor devices, and enable novel device configurations not possible by epitaxial growth.

  5. On-wafer magnetic resonance of magnetite nanoparticles

    NASA Astrophysics Data System (ADS)

    Little, Charles A. E.; Russek, Stephen E.; Booth, James C.; Kabos, Pavel; Usselman, Robert J.

    2015-11-01

    Magnetic resonance measurements of ferumoxytol and TEMPO were made using an on-wafer transmission line technique with a vector network analyzer, allowing for broadband measurements of small sample volumes (4 nL) and small numbers of spins (1 nmol). On-wafer resonance measurements were compared with standard single-frequency cavity-based electron paramagnetic resonance (EPR) measurements using a new power conservation approach and the results show similar line shape. On-wafer magnetic resonance measurements using integrated microfluidics and microwave technology can significantly reduce the cost and sample volumes required for EPR spectral analysis and allow for integration of EPR with existing lab-on-a-chip processing and characterization techniques for point-of-care medical diagnostic applications.

  6. White-light interferometric microscopy for wafer defect inspection

    NASA Astrophysics Data System (ADS)

    Zhou, Renjie; Edwards, Christopher; Bryniarski, Casey; Dallmann, Marjorie F.; Popescu, Gabriel; Goddard, Lynford L.

    2015-03-01

    White-light imaging systems are free of laser-speckle. Thus, they offer high sensitivity for optical defect metrology, especially when used with interferometry based quantitative phase imaging. This can be a potential solution for wafer inspection beyond the 9 nm node. Recently, we built a white-light epi-illumination diffraction phase microscopy (epi-wDPM) for wafer defect inspection. The system is also equipped with an XYZ scanning stage and real-time processing. Preliminary results have demonstrated detection of 15 nm by 90 nm in a 9 nm node densely patterned wafer with bright-field imaging. Currently, we are implementing phase imaging with epi-wDPM for additional sensitivity.

  7. 450mm wafer patterning with jet and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  8. SUEX process optimization for ultra-thick high-aspect ratio LIGA imaging

    NASA Astrophysics Data System (ADS)

    Johnson, Donald W.; Goettert, Jost; Singh, Varshni; Yemane, Dawit

    2011-04-01

    The focus of this paper is on the use of SUEX Thick Dry Film Sheet (TDFS) laminates which DJ DevCorp is developing as a thick resist material in optical and X-ray lithography. Preliminary thick dry film sheets up to 1mm thickness were successfully prepared and patterned at the CAMD X-ray beamlines and presented at HARMST 2007. Recently, new results have been published using SUEX resist sheets in UV lithography showing great market potential including plating molds for metal microparts, polymer MEMS, multilayer microfluidics structures, BioMEMS, medical devices, wafer level packaging processes, and displays. The SUEX TDFS are available in a range of thicknesses from 100?m to 1mm or more and are pre-cut into a number of standard wafer sizes. This new material is a modified epoxy formulation containing an antimony-free photo acid generator (PAG) prepared under a highly controlled solvent-less process which provides uniform coatings between two throw-away layers of protective polyester film. As part of our initial studies resist layers of 250, 500 and 1000?m were laminated onto regular silicon wafers using a hot roll laminator at a speed of 1ft/min at 75C. The entire substrate preparation takes about 1 hour and with practice users can prepare up to 10 substrates in this time which are typically ready to use within 2 hours. In our efforts to develop a commercially viable product we have conducted experiments using standard equipment available at CAMD (Quintel UV aligner and CAMD XRLM 1 and 4 beamline). Initial X-ray exposure tests were done with a bottom dose ranging between 100 and 400 J/cm3 and a top/bottom dose ratio of less than 3 for sheets up to 2mm in thickness. Exposure time for typical conditions of the CAMD storage ring (ring current ranging between 100 and 160mA, beam lifetime of about 10hrs at 100mA ring current) is about 10-15min for a 4' wafer. After exposure the samples were immediately post exposure baked between 70C and 110C using a convection oven, taken out and cooled to RT then relaxed up to 3 days before development to reduce stress. Development was done in PGMEA for up to 3 hours for the 1000?m thick samples followed by a short IPA rinse and drying in air. Very high aspect ratios of 100 or more have been routinely patterned with nearly perfectly straight sidewalls (~1-1.5?m deviation for a 1mm tall structure) and excellent image fidelity.

  9. Scales

    ScienceCinema

    Murray Gibson

    2010-01-08

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain ? a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  10. Scales

    SciTech Connect

    Murray Gibson

    2007-04-27

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain — a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  11. Wafer heating mechanisms in a molecular gas, inductively coupled plasma: in situ, real time wafer surface measurements and three-dimensional thermal modeling

    SciTech Connect

    Titus, M. J.; Graves, D. B.

    2008-09-15

    The authors report measurements and modeling of wafer heating mechanisms in an Ar/O{sub 2} inductively coupled plasma (ICP). The authors employed a commercially available on-wafer sensor system (PlasmaTemp developed by KLA-Tencor) consisting of an on-board electronics module housing battery power and data storage with 30 temperature sensors embedded onto the wafer at different radial positions. This system allows for real time, in situ wafer temperature measurements. Wafer heating mechanisms were investigated by combining temperature measurements from the PlasmaTemp sensor wafer with a three-dimensional heat transfer model of the wafer and a model of the ICP. Comparisons between pure Ar and Ar/O{sub 2} discharges demonstrated that two additional wafer heating mechanisms can be important in molecular gas plasmas compared to atomic gas discharges. The two mechanisms are heating from the gas phase and O-atom surface recombination. These mechanisms were shown to contribute as much as 60% to wafer heating under conditions of low bias power. This study demonstrated how the 'on-wafer' temperature sensor not only yields a temperature profile distribution across the wafer, but can be used to help determine plasma characteristics, such as ion flux profiles or plasma processing temperatures.

  12. The Study of Deep Lithography and Moulding Process of LIGA Technique

    NASA Astrophysics Data System (ADS)

    Guo, Yuhua; Liu, Gang; Kan, Ya; Tian, Yangchao

    2007-01-01

    The knowledge of the development behavior, especially the development rate, is of primary importance for the study of deep x-ray lithography in LIGA technique. In the first part of this paper, we have measured the development rates of crosslinked PMMA foils irradiated in NSRL covering a wide dose range (bottom dose in the range:2.5-8.0 kJ/cm3). After the exposure, we use a so-called period-development method (to dip development in GG-developer for 20 minutes and clean in rinse solution for 40 minutes as a development period). For processing the experiment data, we get the KDβ model to describe our PMMA/GG-developer system. The aim of this work is to find out a stable experiment condition for deep X-ray lithography and development. The result shows that in small amount of dose (bottom dose range: 2.5-4 kJ/cm3), this model is very stable. While in large amount of dose (bottom dose range: 5-8kJ/cm3), the model becomes very sensitive and even unavailable. To verify the conclusion validity, the fixed dose range (bottom dose range: 3.5-4 kJ/cm3) is applied on PMMA microstructures. And the result shows an effective development process. In the following procedure, mold inserts can be produced by micro-electroforming and plastic replicas can be mass produced by hot embossing. To emboss high-aspect-ratio microstructures, the deformation of microstructures usually occurs due to the demolding forces between the sidewall of mold inserts and the thermoplastic (PMMA). To minimize the friction force the optimized experiment has been performed using Ni-PTFE compound material mold inserts. Typical defects like pull-up and damaged edges can be greatly reduced.

  13. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    SciTech Connect

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  14. On the viscoplastic response of a composite wafer

    NASA Technical Reports Server (NTRS)

    Valanis, K. C.; Landel, R. F.; Peng, S. T. J.

    1988-01-01

    In the present treatment of a viscoplastic composite wafer formed from a viscoplastic matrix that is reinforced by elastic or viscoplastic fibers attached to its plane surfaces, one constitutive equation is established by considering the viscoplastic behavior of the matrix as determined by an integral-type constitutive law whose intrinsic time-measure is pertinent to endochronic viscoplasticity. Attention is given to asymptotic cases where fiber stiffnesses and the hydrostatic modulus of the wafer are much larger than the latter's shear modulus. An explicit calculation is used when the stress field is uniaxial.

  15. Simulation of defect zones in scribed silicon wafers

    NASA Astrophysics Data System (ADS)

    Ogorodnikov, Alexey I.; Ogorodnikova, Olga M.; Tikhonov, Igor N.

    2010-11-01

    The paper presents the results of computer simulation of silicon wafers under scribe loading conditions. Finite Element (FE) analysis was applied to estimate a value of stresses and spread of defect zone around scratch line. It was revealed that due to impact of diamond tip, a complex stress-strain state is produced in the wafer, which is related to the appearance of defect zones in silicon. The approved methods of cutting simulation could be employed for various types of brittle materials to predict defects and damage of crystal during separation processing.

  16. Determination of stress in silicon wafers using Raman spectroscopy

    NASA Astrophysics Data System (ADS)

    De Biasio, M.; Neumaier, L.; Vollert, N.; Geier, E.; Roesner, M.; Hirschl, Ch.; Kraft, M.

    2015-06-01

    With a strong industrial trend towards using thin silicon in semiconductor devices, process legacy-induced stresses are matter of increasing practical importance. A key problem here is a lack of suitable metrology equipment for measuring inherent substrate material stresses in the manufacturing line. To overcome this, the use of Raman microspectrometry as a tool for measuring stress levels and distributions quantitatively on entire productive wafers was researched. Combining model cases, theoretical considerations and real-world samples, it could be shown that Raman can provide the necessary analytical accuracy and reliability, allowing to relate ensuing stress states e.g. to different wafer thinning process parameters.

  17. An application of selective electrochemical wafer thinning for silicon characterization

    SciTech Connect

    Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

    1990-01-01

    A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

  18. Wafer CD variation for random units of track and polarization

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

    2012-03-01

    After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle MTT and wafer intra-field MTT is shown for ENG process without polarization. The influence of different exposure conditions - with and without polarization of scanner laser source - on the average CD value for isolated and dense structures is demonstrated.

  19. The Relationship between the Bending Stress in Silicon Wafers and the Mechanical Strength of Silicon Crystals

    NASA Astrophysics Data System (ADS)

    Fukuda, Tetsuo

    1995-06-01

    Silicon wafers horizontally stacked in a vertical furnace bend downward due to their weight. Using a linear elastic theory, we calculated the shear stress caused by the wafer bending and investigated the mechanical strength by comparing the shear stress with the upper yield stress of silicon crystals. We concluded that the maximum shear stress increased with the increase in the wafer diameter, 0.20, 0.30, and 0.55 MPa for 6, 8, and 12 inch wafers. In bending the 12 inch wafers, oxygen precipitates, lowering the upper yield stress, caused serious wafer warping because the shear stress exceeded the lowered yield stress.

  20. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  1. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, Theodoer F. (31843 Miwok Trail, P.O. Box 1453, Evergreen, CO 80439)

    1995-01-01

    Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

  2. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  3. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications.

    PubMed

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called "Si photonics"). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  4. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    PubMed Central

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  5. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    NASA Astrophysics Data System (ADS)

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, Sanghyeon; Choi, Won Jun

    2016-02-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

  6. Multi-wafer slicing with a fixed abrasive

    NASA Technical Reports Server (NTRS)

    Schmid, Frederick (Inventor); Khattak, Chandra P. (Inventor); Smith, Maynard B. (Inventor)

    1988-01-01

    A wafering machine having a multiplicity of wire cutting blades supported by a bladehead reciprocally moving past a workpiece supported by a holder that rocks about an axis perpendicular to the wires at a frequency less than the reciprocation of the bladehead.

  7. Curvature measurement system of Si-wafer using circular gratings

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    2010-03-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. However, due to the prevalence of surface flatness measurement systems that flooded the market, the cycle time for curvature measurement system has become one of the critical factors for the user to consider. A simple and rapid whole-field curvature measurement system using a novel a computer aided phase shift reflection grating method has been developed and discussed in the previous publications. Laterals gratings in horizontal has vertical directions are needed in order to realize the curvature information on the wafer in both directions. In this paper, with same system setup, circular grating is being projected on to the specimen to measure the curvature distribution of the wafer. With the aid of coordinate-transform method and the digital phase-shifting technique, the digital images of reflected gratings are processed automatically and analyzed in the polar coordinate system. Unlike vertical or horizontal line gratings, the utilization of the circular gratings in radial shearing method provides curvature information in all directions, not only in one. Further, only four phase shifted images are captured and the measurement cycle time is thus reduced by half.

  8. Curvature measurement system of Si-wafer using circular gratings

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    2009-12-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. However, due to the prevalence of surface flatness measurement systems that flooded the market, the cycle time for curvature measurement system has become one of the critical factors for the user to consider. A simple and rapid whole-field curvature measurement system using a novel a computer aided phase shift reflection grating method has been developed and discussed in the previous publications. Laterals gratings in horizontal has vertical directions are needed in order to realize the curvature information on the wafer in both directions. In this paper, with same system setup, circular grating is being projected on to the specimen to measure the curvature distribution of the wafer. With the aid of coordinate-transform method and the digital phase-shifting technique, the digital images of reflected gratings are processed automatically and analyzed in the polar coordinate system. Unlike vertical or horizontal line gratings, the utilization of the circular gratings in radial shearing method provides curvature information in all directions, not only in one. Further, only four phase shifted images are captured and the measurement cycle time is thus reduced by half.

  9. Automatically Dressing Blades in Silicon-Wafer Cutting

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1985-01-01

    Inserts incorporated in support beams for silicon ingots automatically "dress" cutting blade during wafer slicing. Segments of blade-dressing material placed at regular intervals in graphite beam. Blade cuts into segments and dressed without operator intervention and without interrupting regular machine operation. Manual dressing eliminated, and production rates increased.

  10. Full wafer metrology for chemically graded thin films

    NASA Astrophysics Data System (ADS)

    Jobin, Marc; Jotterand, Stphane; Pellodi, Cdric; dos Santos, Sergio; Sandu, Cosmin Silviu; Wagner, Estelle; Benvenuti, Giacomo

    2012-04-01

    Combinatorial CBVD (Chemical Beam Vapor Deposition) is a thin film deposition technology which has the ability to produce multi-element thin films with large controlled composition spread gradients. If functional characterizations can be carried out systematically and rapidly on such graded films over full wafers, they enable to identify precisely the best film composition for a given application, and CBVD then easily allows for the deposition of the optimized film homogeneously on large wafers. In this article, we demonstrate the efficiency of such a process development based on the optimization of new Transparent Conductive Oxide thin films (TCO) of few % Nb doped TiO2. We have developed a full wafer metrology instrument which maps the optical thickness and the sheet resistance with a lateral resolution below 400um. We discuss the performance of various algorithms to extract the optical thickness from the white light reflectance measurement in the case of very small thickness. The sheet resistance is measured with an array of four AFM-like conductive cantilevers, allowing accurate sheet resistance (R) measurement where the standard tungsten four probes destroy porous thin oxide films. Application of these measurements to several Nb doped TiO2 films deposited on 4" wafer by CBVD is presented.

  11. Fabricating a Microcomputer on a Single Silicon Wafer

    NASA Technical Reports Server (NTRS)

    Evanchuk, V. L.

    1983-01-01

    Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

  12. Ablation and cleaning of wafer surface by excimer laser

    NASA Astrophysics Data System (ADS)

    Kim, Yong-Kee; Kim, Dae-Jin; Ryu, Je-Kil; Pak, Sung-Sik

    2001-06-01

    The importance of surface cleaning is an essential factor in VLSI technology, flat panel display, and data storage devices. The results of laser cleaning technology were studied using KrF excimer laser (248 nm) irradiation in cleanroom environment. The applied energy density was 200 - 800 mJ/cm2 at a repetition rate of 10 - 40 Hz with various focused beam widths. Results of photoresist stripping were made before and after laser irradiation with PR covered wafers and comparison of laser cleaning results were investigated as well with bare wafers. The atomic force microscopy (AFM) images of laser cleaning results were also presented and compared before and after laser irradiation. The surface roughness of AFM image of contaminated wafer surface before laser irradiation was 192 angstrom and that of after laser irradiation was 16.2 angstrom. The mechanism of laser cleaning and ablation is rapid thermal expansion of substrate surface induced by an instantaneous temperature rising due to laser irradiation. It is found that the temperature rising of the substrate surface was about 297 degree(s)C with a fluence of 400 mJ/cm2 at 300K. Laser dry cleaning technology easily removed fingerprints, submicron Al2O3 and SiO2 particulates intentionally contaminated on the top of the wafer surface without aids of toxic chemicals and deionized water.

  13. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    SciTech Connect

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

  14. A reclaiming process for solar cell silicon wafer surfaces.

    PubMed

    Pa, P S

    2011-01-01

    The low yield of epoxy film and Si3N4 thin-film deposition is an important factor in semiconductor production. A new design system using a set of three lamination-shaped electrodes as a machining tool and micro electro-removal as a precision reclaiming process of the Si3N4 layer and epoxy film removal from silicon wafers of solar cells surface is presented. In the current experiment, the combination of the small thickness of the anode and cathodes corresponds to a higher removal rate for the thin films. The combination of the short length of the anode and cathodes combined with enough electric power produces fast electroremoval. A combination of the small edge radius of the anode and cathodes corresponds to a higher removal rate. A higher feed rate of silicon wafers of solar cells combined with enough electric power produces fast removal. A precise engineering technology constructed a clean production approach for the removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers from solar cells that can reduce pollution and lower cost. PMID:21446525

  15. Interaction of an argon plasma jet with a silicon wafer

    NASA Astrophysics Data System (ADS)

    Engelhardt, Max; Pothiraja, Ramasamy; Kartaschew, Konstantin; Bibinov, Nikita; Havenith, Martina; Awakowicz, Peter

    2016-04-01

    A filamentary discharge is ignited in an argon plasma jet under atmospheric pressure conditions. The gas discharge is characterized with voltage-current measurements, optical emission spectroscopy and an ICCD-camera with a high temporal resolution down to 10 ns. In the effluent of the plasma jet, filaments come into contact with the surface of a silicon wafer and modify it, namely etching traces are produced and microcrystals are deposited. These traces are studied with optical and electron microscopes. The material of the deposited microcrystals and the surface modifications of the silicon wafer are analyzed with Raman microspectroscopy. Amorphous silicon is found within the etching traces. The largest part of the deposited microcrystals are composed of nitratine (NaNO3) and some of them are calcite (CaCO3). Analyzing the possible reasons for the silicon wafer modifications we come to the conclusion that plasmoids, which are produced near the substrate surface by interaction with ionization waves, are a plausible explanation for the observed surface modifications of the silicon wafer.

  16. Bonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits

    NASA Astrophysics Data System (ADS)

    Kim, Hyun S.; Blick, Robert H.; Kim, D. M.; Eom, C. B.

    2004-09-01

    We report a method for bonding silicon-on-insulator wafers onto glass wafers. After pre-cleaning the wafers by an ozone and ultraviolet exposure, followed by mega-sonic water rinse, the SOI wafers are bonded to glass wafers in a vacuum chamber. This is performed at a temperature of 400 °C under an applied voltage of 700 V. The interface between the glass and SOI wafer is tested mechanically and inspected by electron beam microscopy. Furthermore, we demonstrate removal of the silicon bulk layer after wafer bonding. The quality of the single crystalline Si thin film on the glass wafers has been verified by four-circle x-ray diffraction and scanning electron microscopy. This process will allow us the integration of thin-film electronics in biological sensor applications.

  17. Advanced FTIR technology for the chemical characterization of product wafers

    NASA Astrophysics Data System (ADS)

    Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

    2001-01-01

    Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers.

  18. An innovative platform for high-throughput high-accuracy lithography using a single wafer stage

    NASA Astrophysics Data System (ADS)

    Shibazaki, Yuichi; Kohno, Hirotaka; Hamatani, Masato

    2009-03-01

    For 32 nm half-pitch node, double patterning is recognized as the most promising technology since some significant obstacles still remain in EUV in terms of technology and cost. This means much higher productivity and overlay performance will be required for lithography tools. This paper shows the technical features of Nikon's new immersion tool, NSR-S620 based on newly developed platform "StreamlignTM" designed for 2nm overlay, 200wph throughput and 2week setup time. The S620 is built basically upon Nikon's Tandem Stage and Local Fill Nozzle technology, but has several additional features. For excellent overlay, laser encoders with short optical path are applied for wafer stage measurement in addition to interferometers. By using this hybrid metrology, the non-linearity of the encoder scale can be easily calibrated, while eliminating the air fluctuation error of interferometer. For high throughput, a method with a new alignment microscope system and a new auto focus mapping, called Stream Alignment is introduced. It makes it possible to reduce the overhead time between the exposures remarkably. The target productivity is 4,000 wafer outs per day. Accuracy is also improved because many more alignment points and a continuous wafer height map without stitching are available. Higher acceleration and faster scan velocity of the stages are also achieved by optimal vibration dynamics design and new control system. The main body, including the projection lens, is isolated by Sky Hook Technology used already on the NSR-SF150 and SF155 steppers, and also the reticle stage is mechanically isolated from the main body. With this new platform, the imaging performance can be maximized.

  19. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    SciTech Connect

    Qiusheng, Y. Senkai, C. Jisheng, P.

    2015-03-30

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  20. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    NASA Astrophysics Data System (ADS)

    Qiusheng, Y.; Senkai, C.; Jisheng, P.

    2015-03-01

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5m, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2m. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 m. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 m. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  1. Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

    PubMed

    Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Prez-Murano, F

    2008-07-30

    Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20m down to 200nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ?2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11)gcm(-2)Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer. PMID:21828759

  2. Mask blank defect printability comparison using optical and SEM mask and wafer inspection and bright field actinic mask imaging

    NASA Astrophysics Data System (ADS)

    Mangat, Pawitter; Verduijn, Erik; Wood, Obert R.; Benk, Markus P.; Wojdyla, Antoine; Goldberg, Kenneth A.

    2015-07-01

    Despite significant enhancements in defect detection using optical and e-beam methodology, the smaller length scales and increasing challenges of future technology nodes motivate ongoing research into the need and associated cost of actinic inspection for EUV masks. This paper reports an extensive study of two EUV patterned masks, wherein the mask blank defectivity was characterized using optical (mask and wafer) methods and bright-field mask imaging (using the SHARP actinic microscope) of previously identified blank defects. We find that the bright field actinic imaging tool microscope captures and images many defects that are not seen by the automated optical inspection of patterned masks and printed wafers. In addition, actinic review reveals the impact of multilayer damage and depicts the printability profile which can be used as an added metric to define the patterned mask repair and defect compensation strategies.

  3. Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

    NASA Astrophysics Data System (ADS)

    Altan, Hakan

    All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on transmission and mobility are quantitatively discussed.

  4. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Luo, Xianshu; Cao, Yulian; Song, Junfeng; Hu, Xiaonan; Cheng, Yungbing; Li, Chengming; Liu, Chongyang; Liow, Tsung-Yang; Yu, Mingbin; Wang, Hong; Wang, Qijie; Lo, Patrick Guo-Qiang

    2015-04-01

    Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS) fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W) bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP) laser, lateral-coupled distributed feedback (LC-DFB) laser with side wall grating, and mode-locked laser (MLL). From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC).

  5. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    NASA Astrophysics Data System (ADS)

    Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

    2016-02-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

  6. Wafer-level packaging with compression-controlled seal ring bonding

    DOEpatents

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  7. Single incision cholecystectomy using a clipless technique with LigaSure in a resource limited environment: The Bahamas experience

    PubMed Central

    Downes, Ross O.; McFarlane, Michael; Diggiss, Charles; Iferenta, James

    2015-01-01

    Background Scarless/single-incision laparoscopic cholecystectomy (SILC) is a new procedure. It affords a superior cosmetic outcome when compared to conventional laparoscopic cholecystectomy. We examine the application of this technique using LigaSure via a clipless method. The present study looks at the experience of a single surgeon using this method with initial evaluation of the safety, feasibility, affordability, and benefits of this procedure. Methods Twenty-eight patients underwent transumbilical SILC at Doctors Hospital from January to December, 2014. The cohort included both emergency and elective patients. There was no difference in the preoperative work-up as indicated. To perform the operation, a 22.5-cm linear incision was made through the umbilicus and the single port platform utilized. A 10mm 30-degree laparoscope, a 5mm LigaSure and straight instruments were used to perform the laparoscopic cholecystectomy procedure. Results All patients except two were operated on successfully. Conversion was considered the placement of an additional epigastric/Right upper quadrant (RUQ) port. The conversion rate to standard LC was 7%. No patient was converted to open cholecystectomy. In the 28 successfully completed patients, the median duration of the operation was 38.5min and estimated operative blood loss was 24ml. Patients were commenced on liquid diet immediately on being fully conscious and after return to the ward with an estimated time of 6h. The mean postoperative hospital stay was 1.4 days. Follow-up visits were conducted for all patients at 2-weeks intervals and continued for 6 weeks after surgery where possible. Two patients developed wound infections. All patients were satisfied with the good cosmetic effect of the surgery. The total satisfaction rate was 100%. Conclusions SILC is a safe and feasible technique for operating with scarless outcomes and reducing perioperative discomfort at the same time. The GelPOINTTM is a safe and feasible platform to be used. The procedure can be accomplished using regular instruments and laparoscope. Curved instruments and a bariatric length laparoscope may make the procedure easier and result in greater time saving. The addition of LigaSure decreases the complexity of the operation, decreases operative time and blood loss. The technique is economical in a resource-limited environment. PMID:25958050

  8. Chemical method for producing smooth surfaces on silicon wafers

    DOEpatents

    Yu, Conrad (Antioch, CA)

    2003-01-01

    An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

  9. Single Wafer Furnace and Its Thermal Processing Applications

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kuribayashi, Hiromitsu; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-07-01

    A resistively heated, vacuum and atmospheric pressure compatible, single wafer furnace (SWF) system is proposed to improve operational flexibility of conventional furnaces and productivity of single wafer rapid thermal processing (RTP) systems. The design concept and hardware configuration of the SWF system are described. The temperature measurement/control techniques and thermal characteristics of the SWF system are described. Typical process results in TiSi formation, implant anneal and thin oxide formation using the SWF system are reported. Due to the vertically stacked, dual chamber configuration and steady state temperature control, very flexible operation with a high throughput at a minimal power consumption (<3.5 kW per process chamber at 1150°C) was realized. Many thermal processes used in furnaces and RTP systems can easily be converted to SWF processes without decreasing cost performance and/or deteriorating process results by using the SWF system.

  10. Wafer-fused VECSELs emitting in the 1310nm waveband

    NASA Astrophysics Data System (ADS)

    Sirbu, A.; Pierscinski, K.; Mereuta, A.; Iakovlev, V.; Caliman, A.; Micovic, Z.; Volet, N.; Rautiainen, J.; Heikkinen, J.; Lyytikainen, J.; Rantamki, A.; Okhotnikov, O.; Kapon, E.

    2014-03-01

    Optically pumped wafer fused 1310 nm VECSELs have the advantage of high output power and wavelength agility. Gain mirrors in these lasers are formed by direct bonding of InAlGaAs/InP active cavities to Al(Ga)As/GaAs DBRs. We present for the first time Watt-level 1310 nm wafer-fused VCSELs based on gain mirrors with heat dissipation in the "flip-chip" configuration. Even though output power levels in this approach is lower than with intra-cavity diamond heat-spreaders, the "flip-chip configuration demonstrates higher quality optical emission and is preferable for industrial applications in optical amplifiers, intra-cavity doubled lasers, etc.

  11. A gas chromatographic air analyzer fabricated on a silicon wafer

    NASA Technical Reports Server (NTRS)

    Terry, S. C.; Jerman, J. H.; Angell, J. B.

    1979-01-01

    A miniature gas analysis system has been built based on the principles of gas chromatography (GC). The major components are fabricated in silicon using photolithography and chemical etching techniques, which allows size reductions of nearly three orders of magnitude compared to conventional laboratory instruments. The chromatography system consists of a sample injection valve and a 1.5-m-long separating capillary column, which are fabricated on a substrate silicon wafer. The output thermal conductivity detector is separately batch fabricated and integrably mounted on the substrate wafer. The theory of gas chromatography has been used to optimize the performance of the sensor so that separations of gaseous hydrocarbon mixtures are performed in less than 10 s. The system is expected to find application in the areas of portable ambient air quality monitors, implanted biological experiments, and planetary probes.

  12. Designing DWDM multiplexers on SiON wafers

    NASA Astrophysics Data System (ADS)

    Dragnea, Laurentiu

    2010-11-01

    I propose an integrated multiplexer/demultiplexer that use a concave blazed diffraction grating on SiON wafer. The paper presents a technology that overcome existing issues regarding implementation of such a microoptic device. Two types of similar integrated systems were developed but both of them have not minimized chromatic, astigmatism and spherical aberrations. Both systems use gold coating for vertical walls of diffraction grating that has reflection index lower than aluminum for wavelength used. Technology proposed in this paper minimizes the chromatic, astigmatism and spherical aberrations. Also is used aluminum for coating of vertical walls of diffraction grating. SiON wafer is etched with Argon plasma through photoresist mask with thickness of 0,8 ?m for grating configuration allowing reusing of the photoresist in next stage of coating. This makes possible that coating through liftoff to be aligned to vertical walls of concave diffraction grating, eliminating positioning errors due to coating mask.

  13. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    SciTech Connect

    Montoya, Angela C.; Maji, Arup K.

    2010-02-22

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  14. Joint Rigidity Assessment with Piezoelectric Wafers and Acoustic Waves

    NASA Astrophysics Data System (ADS)

    Montoya, Angela C.; Maji, Arup K.

    2010-02-01

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an `L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  15. Localized induction heating solder bonding for wafer level MEMS packaging

    NASA Astrophysics Data System (ADS)

    Yang, Hsueh-An; Wu, Mingching; Fang, Weileun

    2005-02-01

    This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was heated using induction heating causing the solder to reflow. The experiment results show that it took less than 1 min to complete the bonding process. In addition, the MEMS devices experienced a temperature of only 110 C during bonding, thus thin film materials would not be damaged. Moreover, the bond strength between silicon and silicon wafer was higher than 18 MPa. The step height of the feed-through wire (acting as the electrical feed-through of the bonded region) is sealed by the electroplated film. Thus, the flatness and roughness of the electroplated surface are recovered by the solder reflow, and the package for preventing water leakage can be achieved. The integration of the surface micromachined devices with the proposed packaging techniques was demonstrated.

  16. Sputter deposition of SiC coating on silicon wafers

    NASA Technical Reports Server (NTRS)

    Robson, M. T.; Blue, C. A.; Warrier, S. G.; Lin, R. Y.

    1992-01-01

    A study is conducted of the effect of substrate temperature during coating on the properties of coated SiC films on Si wafers, using a scratch test technique. While specimen temperature during coating has little effect on deposition rate, it significantly affects the durability of the coating. Scratch test damage to both film coating and substrate decreased with increasing deposition temperature, perhaps due to the rapid diffusion of the deposited atoms.

  17. Ultrahigh-vacuum field emitter array wafer tester

    SciTech Connect

    Gray, H.F.; Ardis, L.; Campisi, G.J.

    1987-02-01

    The device reported here allows the researcher the opportunity of gaining primitive yield information, threshold voltages, emission stability, and other information, e.g., gas effects, on field emitter arrays (FEA) which are microminiature ''vacuum tubes'' fabricated by microelectronic processing methods on silicon wafers, without scribing, dicing, and mounting each device on individual vacuum-compatible headers. This device also speeds up the entire data-acquisition process by requiring only one ultrahigh-vacuum pumpdown and one set of vacuum feedthroughs.

  18. Ultrahigh-vacuum field emitter array wafer tester

    NASA Astrophysics Data System (ADS)

    Gray, H. F.; Ardis, L.; Campisi, G. J.

    1987-02-01

    The device reported here allows the researcher the opportunity of gaining primitive yield information, threshold voltages, emission stability, and other information, e.g., gas effects, on field emitter arrays (FEA) which are microminiature ``vacuum tubes'' fabricated by microelectronic processing methods on silicon wafers, without scribing, dicing, and mounting each device on individual vacuum-compatible headers. This device also speeds up the entire data-acquisition process by requiring only one ultrahigh-vacuum pumpdown and one set of vacuum feedthroughs.

  19. Towards reduced impact of EUV mask defectivity on wafer

    NASA Astrophysics Data System (ADS)

    Jonckheere, R.; Van den Heuvel, D.; Pacco, A.; Pollentier, I.; Baudemprez, B.; Jehoul, C.; Hermans, J.; Hendrickx, E.

    2014-07-01

    The defectivity challenges of extreme ultraviolet (EUV) masks, that need to be addressed before production readiness of EUV lithography is assured from the mask perspective, are twofold. First, the EUV-specific defect type relating to the multi-layer (ML) mirror, the so-called ML-defects, require to become more detectable than they are printable. This not only requires proven capability of blank inspection, but also the existence of satisfactory printability mitigation strategies (comprising avoidance, pattern shift methodology, compensation repair). Both these assets need to become available within the mask supply chain, as there is little that can still be done about such residual defects at the wafer fab. In a production phase, finding unexpected printing ML-defects is unacceptable. It is shown how the specific way-of-working in use at imec, starting from the printed wafer, contributes to related learning and identification of remaining gaps, in getting this issue fully dealt with. The second challenge relates to particle contamination during use of the reticle at the wafer fab. Avoiding overlaycritical particles on the backside of NXE3100 reticles is facilitated by the established way-of-working. Minimizing the occurrence of particles "hopping" between reticles via the electrostatic clamp of the scanner (so-called clamp-traveling particles) is a major driver for appropriate mask cleaning. The latter may not have negative impact by frequent use, in view of the highly vulnerable EUV mask stack, and especially for the present "black-border" solution in which the ML is etched away at the image border on the reticle. A lot of effort is spent into monitoring of NXE3100 reticles for particle adders on the pattern side. This is realized by comparing past and present mask defect maps obtained by inspection of printed wafers with subsequent repeater analysis.

  20. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    NASA Astrophysics Data System (ADS)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 ?m AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 ?m pixel size and 160x120, 52 ?m pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  1. Measurement and modeling of time- and spatial-resolved wafer surface temperature in inductively coupled plasmas

    SciTech Connect

    Hsu, C. C.; Titus, M. J.; Graves, D. B.

    2007-05-15

    The transient temperature profile across a commercial wafer temperature sensor device in an inductively coupled Ar plasma is reported. The measured temperatures are compared to model predictions, based on a coupled plasma-wafer model. The radial temperature profile is the result of the radial profile in the ion energy flux. The ion energy flux profile is obtained by combining the Langmuir probe measurement, the ion wall flux probe measurement, and a plasma model. A methodology to estimate the ion flux profile using the sensor measurements has been validated by combining the plasma measurements, the wafer temperature measurements, and the plasma-wafer model. It is shown that with minimal heat transfer between the wafer and the chuck, the initial transient wafer temperature profile after plasma ignition can be used to estimate the ion energy flux profile across the wafer.

  2. A photo-sensor on thin polysilicon membrane embedded in wafer level package LED

    NASA Astrophysics Data System (ADS)

    Kim, Jin Kwan; Lee, Hee Chul

    2012-06-01

    A wafer level packaging LED with photo-sensor which is fabricated on thin poly-silicon membrane located on the corner of silicon cavity is presented in this paper. The wafer substrate was fabricated with (100) orientation silicon wafer and a cavity was etched on the top of the wafer with wet chemical anisotropic etching process for mounting a LED chip. A thin polysilicon membrane was fabricated on the corner of the cavity and a MSM (Metal Semiconductor Metal) type photo-sensor was fabricated on the thin polysilicon membrane. The photo-sensor fabrication and LED packaging were completed on wafer level. The embedded photo-sensor in a wafer level packaging LED is designed to measure light intensity of a LED. The membrane structure photo-sensor can sense the light of the mounted LED directly, so it can measure accurate light intensity of the wafer level packing LED.

  3. Influence of the bonding front propagation on the wafer stack curvature

    SciTech Connect

    Navarro, E.; Bréchet, Y.; Barthelemy, A.; Radu, I.; Pardoen, T.; Raskin, J.-P.

    2014-08-11

    The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

  4. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, C.M.; Hui, W.C.

    1996-11-19

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

  5. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, Conrad M.; Hui, Wing C.

    1996-01-01

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

  6. Stress measurement of thin wafer using reflection grating method

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand K.

    2010-08-01

    Flatness/Curvature measurement is critical in many Si-wafer based technologies ranging from micro-electronics to MEMS and to the current PV industry. As the thickness of the wafer becomes smaller there is an increased tendency for it to warp and this is not conducive to both patterning as well as dicing. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress measurement. The system was developed from our earlier works on Computer Aided Moir Methods and Novel Techniques in Reflection Moir, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this research, the system is calibrated with reference to stress measurement equipment from KLA-Tencor. Some initial results based on a joint project with Infineon Technologies are re-examined. The stress distribution of the wafers are derived with the aid of Stoney's equation. Finally, the results from our proposed system are compared and contrasted with data obtained from KLA-Tencor equipment.

  7. Nanoimprint template fabrication using wafer pattern for sub-30nm

    NASA Astrophysics Data System (ADS)

    Park, C. M.; Kim, K. J.; Lee, Y. J.; Cho, K. Y.; Lee, Y. M.; Park, J. O.; Kim, In S.; Yeo, J. H.; Choi, S. W.; Park, C. H.; Lee, D. H.; Lee, B. K.; Hwang, S. W.

    2010-03-01

    Patterning of sub-30 nm features using high resolution nano-imprint lithography (NIL) requires use of quartz templates. To this end, various fabrication methods such as e-beam lithography, edge lithography, and focused ion beam lithography were employed for the template formation. Despite significant advances using these methods, NIL template formation process suffers from low throughput and high cost of fabrication when compared with the fabrication of masks used in optical lithography. This is largely owing to a 4X difference in feature sizes involved for the fabrication of NIL template and optical lithography mask. In this paper, we report on a simple, cost-effective method for the fabrication of sub-30 nm NIL templates. Typical fabrication-time required for the formation of sub-30 nm HP templates using conventional Gaussian beam electron beam lithography, runs into several days. Additionally, complicated etch procedures must be employed for pattern transfer onto quartz substrates. Here we propose a low cost, simplified fabrication process for the formation of high resolution NIL templates using wafer pattern replication. We fabricated sub- 30nmHP poly-silicon lines and spaces on silicon wafer using multiple patterning technique. These patterns were subsequently transferred onto quartz substrates using NIL technique. Several types of features were studied to realize a template using the triple patterning technique described above. Results of wafer printing using the said template will be discussed.

  8. Physical mechanisms of copper-copper wafer bonding

    NASA Astrophysics Data System (ADS)

    Rebhan, B.; Hingerl, K.

    2015-10-01

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing.

  9. Commercial production of QWIP wafers by molecular beam epitaxy

    NASA Astrophysics Data System (ADS)

    Fastenau, J. M.; Liu, W. K.; Fang, X. M.; Lubyshev, D. I.; Pelzel, R. I.; Yurasits, T. R.; Stewart, T. R.; Lee, J. H.; Li, S. S.; Tidrow, M. Z.

    2001-06-01

    As the performance of quantum well infrared photodetectors (QWIPs) and QWIP-based imaging systems continues to improve, their demand will undoubtedly grow. This points to the importance of a reliable commercial supplier of semiconductor QWIP material on three inch and, in the near future, four-inch substrates. Molecular beam epitaxy (MBE) is the preferred technique for growing the demanding QWIP structure, as tight control is required over the material composition and layer thickness. We report the current status of MBE-grown GaAs-based QWIP structures in a commercial production environment at IQE. Uniformity data and run-to-run reproducibility on both three-inch and four-inch GaAs substrates are quantified using alloy composition and QW thickness. Initial results on growth technology transfer to a multi-wafer MBE reactor are also presented. High-resolution X-ray diffraction measurements demonstrate GaAs QW thickness variations and AlGaAs barrier compositions changes to be less than 4% and 1% Al, respectively, across four-inch QWIP wafers from both single- and multiple-wafer MBE platforms.

  10. Wettability investigating on the wet etching textured multicrystalline silicon wafer

    NASA Astrophysics Data System (ADS)

    Liu, Xiangju; Niu, Yuchao; Zhai, Tongguang; Ma, Yuying; Zhen, Yongtai; Ma, Xiaoyu; Gao, Ying

    2016-02-01

    In order to investigate the wettability properties of multicrystalline silicon (mc-Si), the different surface structures were fabricated on the as-cut p-type multi-wire slurry sawn mc-Si wafers, such as as-cut, polished and etched in various acid solutions. The contact angles and the XRD spectra of these samples were measured. It was noted that both the surface structures and the use of surfactant, such as Tween 80, made a stronger effect on wettability of the Si wafer. Due to the lipophilic groups of Tween 80 combined with the Si atoms while the hydrophilic groups of it were outward, a lipophilic surface of Si changed into a hydrophilic one and the rougher the surface, the stronger the hydrophily. Thus, it is feasible to add an appropriate surfactant into the etching solution during black-Si wafer fabrication for solar cells. In addition, different crystal plains of Si had different dangling bond density, so that their surface energies were different. A surface with higher surface energy could attract more water atoms and its wettability was better. However, the effect of crystal plain on the surface wettability was much weaker than surface morphology.

  11. B-Cell-Specific Peptides of Leptospira interrogans LigA for Diagnosis of Patients with Acute Leptospirosis

    PubMed Central

    Kanagavel, Murugesan; Shanmughapriya, Santhanam; Anbarasu, Kumarasamy

    2014-01-01

    Leptospirosis is a reemerging infectious disease that is underdiagnosed and under-recognized due to low-sensitivity and cumbersome serological tests. Rapid reliable alternative tests are needed for early diagnosis of the disease. Considering the importance of the pathogenesis-associated leptospiral LigA protein expressed in vivo, we have evaluated its application in the diagnosis of the acute form of leptospirosis. The C-terminal coding sequence of ligA (ligA-C) was cloned into pET15b and expressed in Escherichia coli. Furthermore, the B-cell-specific epitopes were predicted and were synthesized as peptides for evaluation along with recombinant LigA-C. Epitope 1 (VVIENTPGK), with a VaxiJen score of 1.3782, and epitope 2 (TALSVGSSK), with a score of 1.2767, were utilized. A total of 140 serum samples collected from leptospirosis cases during the acute stage of the disease and 138 serum samples collected from normal healthy controls were utilized for evaluation. The sensitivity, specificity, positive predictive value, and negative predictive value were calculated for the recombinant LigA-C-specific IgM enzyme-linked immunosorbent assay (ELISA) and were found to be 92.1%, 97.7%, 92.8%, and 97.5%, respectively. Epitopes 1 and 2 used in the study showed 5.1 to 5.8% increased sensitivity over recombinant LigA-C in single and combination assays for IgM antibody detection. These findings suggest that these peptides may be potential candidates for the early diagnosis of leptospirosis. PMID:24403522

  12. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates

    NASA Astrophysics Data System (ADS)

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-10-01

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the melt-back effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4 off-axis Si enhances the step-flow growth at 1200?C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20??m was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude.

  13. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    SciTech Connect

    Daix, N. Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 10{sup 9} cm{sup ?2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 20003000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  14. Classical Molecular Dynamics and Self-Consistent Tight-Binding Simulations of Si-Si Wafer Bonding.

    NASA Astrophysics Data System (ADS)

    Lepage, J. G.; Kim, Jeongnim; Wilkins, John W.; Kirchhoff, Florian

    2000-03-01

    We have carried out a series of atomistic simulations of the room temperature bonding of clean, defect-free Si wafers under UHV conditions using Classical Molecular Dynamics (CMD) and Self-Consistent Tight-Binding (SCTB) Our simulations indicate that even when the wafers are perfectly aligned, bonding does not typically result in the formation of bulk crystalline Si. Instead, the basic geometry of the original dimerized surface tends to persist, producing an interface characterized by linked dimers. As the wafers bond, considerable chemical energy is released resulting in rapid heating (up to 800 K) at the interface. However, this heat is rapidly conducted away from the interface and so does not have an appreciable annealing effect. Large-scale CMD calculations show that the ground state energy of the bonded system is sensitively dependent on twist angle. The SCTB calculations were performed using the using the parameterization of Lenosky et al.( Thomas J. Lenosky, Joel D. Kress, Inhee Kwon, Arthur F. Voter, Byard Edwards, David F. Richards, Sang Yang, and James B. Adams, Phys. Rev. B 55), 1528 (1997).

  15. The optimization of FA/O barrier slurry with respect to removal rate selectivity on patterned Cu wafers

    NASA Astrophysics Data System (ADS)

    Yi, Hu; Yan, Li; Yuling, Liu; Yangang, He

    2016-02-01

    Because the polishing of different materials is required in barrier chemical mechanical planarization (CMP) processes, the development of a kind of barrier slurry with improved removal rate selectivity for Cu/barrier/TEOS would reduce erosion and dishing defects on patterned Cu wafers. In this study, we developed a new benzotriazole-free barrier slurry named FA/O barrier slurry, containing 20 mL/L of the chelating agent FA/O, 5 mL/L surfactant, and a 1:5 concentration of abrasive particles. By controlling the polishing slurry ingredients, the removal rate of different materials could be controlled. For process integration considerations, the effect of the FA/O barrier slurry on the dielectric layer of the patterned Cu wafer was investigated. After CMP processing by the FA/O barrier slurry, the characteristics of the dielectric material were tested. The results showed that the dielectric characteristics met demands for industrial production. The current leakage was of pA scale. The resistance and capacitance were 2.4 kω and 2.3 pF, respectively. The dishing and erosion defects were both below 30 nm in size. CMP-processed wafers using this barrier slurry could meet industrial production demands. Project supported by the Special Project Items No. 2 in National Long-Term Technology Development Plan (No. 2009ZX02308), the Natural Science Foundation of Hebei Province (No. F2012202094), and the Doctoral Program Foundation of Xinjiang Normal University Plan (No. XJNUBS1226).

  16. Penetration of plasma into the wafer-focus ring gap in capacitively coupled plasmas

    SciTech Connect

    Babaeva, Natalia Y.; Kushner, Mark J.

    2007-06-01

    In plasma etching equipment for microelectronics fabrication, there is an engineered gap between the edge of the wafer and wafer terminating structures, such as focus rings. The intended purpose of these structures is to make the reactant fluxes uniform to the edge of the wafer and so prevent a larger than desired edge exclusion where useful products cannot be obtained. The wafer-focus ring gap (typically<1 mm) is a mechanical requirement to allow for the motion of the wafer onto and off of the substrate. Plasma generated species can penetrate into this gap and under the beveled edge of the wafer, depositing films and possibly creating particles which produce defects. In this paper, we report on a computational investigation of capacitively coupled plasma reactors with a wafer-focus ring gap. The penetration of plasma generated species (i.e., ions and radicals) into the wafer-focus ring gap is discussed. We found that the penetration of plasma into the gap and under the wafer bevel increases as the size of the gap approaches and exceeds the Debye length in the vicinity of the gap. Deposition of, for example, polymer by neutral species inside the gap and under the wafer is less sensitive to the size of the gap due the inability of ions, which might otherwise sputter the film, to penetrate into the gap.

  17. Wafer shape compensation at the track PEB for improved CD uniformity

    NASA Astrophysics Data System (ADS)

    Michaelson, Timothy; Dai, Junyan; Chen, Lu; Cervera, Hiram; Lue, Brian; Herchen, Harald; Vellore, Kim; Bekiaris, Nikolaos

    2008-03-01

    This paper investigates the feasibility of using an electrostatic chuck (ESC) on a post exposure bake (PEB) plate in the track to improve the critical dimension uniformity (CDU) for bowed wafers. Although it is more conventional to consider vacuum chucking during PEB, electrostatic chucking offers some potential advantages, chief among which is the fact that electrostatic chucking does not require any type of a seal between the wafer and the PEB plate whereas vacuum chucking does. Such a seal requires contact and therefore has the potential to generate backside particles on the wafer. Electrostatic chucking therefore has the potential for a cleaner overall process. Three different PEB plates were tested in the course of this investigation, a non-chucking PEB plate (SRHP), a PEB plate equipped with a vacuum chuck (VRHP), and a PEB plate equipped with an ESC (eBHP). It was found that CD uniformities were up to 84 percent lower for bowed wafers that were chucked during PEB relative to wafers that were not chucked. In every case tested, wafers processed through chucking PEB plates showed lower CDUs than wafers processed through the non-chucking plate. CDU results were similar between vacuum chucked wafers and electrostatic chucked wafers. Based on the results presented in this paper, it can be concluded that electrostatic chucking during PEB is a feasible method for controlling CD uniformities on bowed wafers.

  18. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  19. Multiproject wafers: not just for million-dollar mask sets

    NASA Astrophysics Data System (ADS)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task dictates careful consideration of the alternative methods.

  20. Science and technology of plasma activated direct wafer bonding

    NASA Astrophysics Data System (ADS)

    Roberds, Brian Edward

    This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600spC), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100spC). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

  1. High transmittance silicon terahertz polarizer using wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Yu, Ting-Yang; Tsai, Hsin-Cheng; Wang, Shiang-Yu; Luo, Chih-Wei; Chen, Kuan-Neng

    2015-08-01

    Due to the difficulties faced in fabricating robust Terahertz (THz) optical components with low Fresnel reflection loss, the need to increase the efficiency of THz system with reduced cost is still considered as one of the most essential tasks. In this report, a new low cost THz polarizer with robust structure is proposed and demonstrated. This new THz wire grid polarizer was based on an anti-reflection (AR) layer fabricated with low temperature metal bonding and deep reactive ion etching (DRIE). After patterning Cu wire gratings and the corresponding In/Sn solder ring on the individual silicon wafers, the inner gratings were sealed by wafer-level Cu to In/Sn guard ring bonding, providing the protection against humidity oxidation and corrosion. With the low eutectic melting point of In/Sn solder, wafers could be bonded face to face below 150°C. Two anti-reflection layers on both outward surfaces were fabricated by DRIE. With the mixing of empty holes and silicon, the effective refractive index was designed to be the square root of the silicon refractive index. The central frequency of the anti-reflection layers was designed between 0.5THz to 2THz with an approximate bandwidth of 0.5THz. The samples were measured with a commercial free-standing wire grid polarizer by a THz time domain spectroscopy (THz-TDS) from 0.2THz to 2.2THz. The power transmittance is close to 100% at central frequency. Extinction ratio of the polarizer is between 20dB to 40dB depending on the frequency. The advantages of this new polarizer include high transmittance, robust structure and low cost with no precision optical alignment required.

  2. Advanced Ceramic Wafer Seals Demonstrated at 2000 deg. F

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Durable, high-temperature sliding seals are required in advanced hypersonic engines and around movable control surfaces on future vehicles. These seals must operate at temperatures of 2000 to 2500 F, limit hot gas flow, remain resilient for multiple cycles, and resist scrubbing damage against rough surfaces. Current seal designs do not meet these demanding requirements, so the NASA Glenn Research Center is developing advanced seals and preload devices to overcome these shortfalls. An advanced ceramic wafer seal design and two silicon nitride compression spring designs were evaluated in a series of compression, scrub, and flow tests.

  3. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  4. Automotive SOI-BCD Technology Using Bonded Wafers

    NASA Astrophysics Data System (ADS)

    Himi, H.; Fujino, S.

    2008-11-01

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N+ layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  5. Automotive SOI-BCD Technology Using Bonded Wafers

    SciTech Connect

    Himi, H.; Fujino, S.

    2008-11-03

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N{sup +} layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  6. Propagation of Nd-laser pulses through crystalline silicon wafers

    SciTech Connect

    Kirichenko, N A; Kuzmin, P G; Shcherbina, M E

    2011-07-31

    Propagation of pulses from an Nd:YAG laser (wavelength, 1.064 {mu}m; pulse duration, 270 ns; pulse energy, 225 {mu}J) through crystalline silicon wafers is studied experimentally. Mathematical modelling of the process is performed: the heat conduction equation is solved numerically, the temperature dependences of the absorption and refraction of a substance, as well as generation of nonequilibrium carriers by radiation are taken into account. The constructed model satisfactorily explains the experimentally observed intensity oscillations of transmitted radiation. (interaction of laser radiation with matter)

  7. Warpage Analysis of Silicon Wafer in Ingot Slicing by Wire-Saw Machine

    NASA Astrophysics Data System (ADS)

    Yamada, Toshiro; Kinai, Fumiaki; Ichikawa, Takesh; Yokoyama, Atsushi; Fukunaga, Moritaka; Ohshita, Takashi

    2004-06-01

    It is possible thermal expansion from heat generation by slicing deforms a single-crystal silicon ingot but the authors can find no report on the point. In addition, numerical analysis is useful to clarify the mechanism of wafer warping but no paper has been reported the numerical analysis from the start to end of the wafer slicing process. The authors carried out experiments for the wafer slicing. In addition, a finite element analysis was carried out in order to solve the warping mechanism from the start to end of the wafer slicing process. The warp of wafer in the vertical direction was 6.05 ? m in the experiment whereas the warp in the finite element analysis was 5.30 ? m. The result by the finite element analysis gave good agreement with experimental one. This paper suggests that thermal expansion of the ingot has great influence on the warp of wafer.

  8. On the residual stress and fracture strength of crystalline silicon wafers

    NASA Astrophysics Data System (ADS)

    Yang, Chris; Mess, Frank; Skenes, Kevin; Melkote, Shreyes; Danyluk, Steven

    2013-01-01

    This letter reports on residual stress measurement in thin crystalline silicon wafers with a full-field near-infrared polariscope. Residual stress is analyzed in combination with observed surface defects, and the results are related to measured fracture strength variation in the wafers. Measurements indicate that there is a sawing process-related residual stress in the as-cut wafers, and that etch-removal of ˜5 μm from the wafer surface eliminates a damage layer that can significantly reduce the residual stress in the wafer, and therefore increases the observed fracture strength. There is a corresponding 2 to 3 μm reduction in the observed characteristic defect size after etching. Fracture strength anisotropy observed in the wafers is related to defect orientation (scratching grooves and microcracks) caused by the sawing process.

  9. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

    1979-01-01

    A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

  10. DoseSim: Microsoft-Windows graphical user interface for using synchrotron x-ray exposure and subsequent development in the LIGA process

    NASA Astrophysics Data System (ADS)

    Meyer, P.; Schulz, J.; Hahn, L.

    2003-02-01

    The LIGA process, which combines x-ray lithography with electroplating and moulding, is a technique used worldwide for the fabrication of high aspect ratio microstructures. In the first step (x-ray lithography), a resist layer is applied to a metal-coated substrate, which is then patterned by shadow printing through an x-ray mask with synchrotron radiation. The second step consists in dissolving the exposed parts or the unexposed parts, of a positive and negative resist, respectively, in an organic developer. A graphical user interface has been developed, working under Windows, which meets the necessary requirements of a LIGA x-ray beamline. The code currently permits the computation of synchrotron radiation from bending magnets, the effects of the optical properties of materials, and the necessary parameters for the resist exposure. Also, this program is highly flexible and allows the user to access many annexed calculation possibilities, for example, optimization of the absorber thickness for a desired dose after the absorber, filter possibilities for a desired ratio top dose/bottom dose, calculation of the necessary time to develop the exposed resist. The comparison of results of this code and data used by different x-ray LIGA centers will be given. A general overview of the possibilities of this program will be presented.

  11. Photostimulated near-infrared persistent luminescence as a new optical read-out from Cr3+-doped LiGa5O8

    PubMed Central

    Liu, Feng; Yan, Wuzhao; Chuang, Yen-Jun; Zhen, Zipeng; Xie, Jin; Pan, Zhengwei

    2013-01-01

    In conventional photostimulable storage phosphors, the optical information written by x-ray or ultraviolet irradiation is usually read out as a visible photostimulated luminescence (PSL) signal under the stimulation of a low-energy light with appropriate wavelength. Unlike the transient PSL, here we report a new optical read-out form, photostimulated persistent luminescence (PSPL) in the near-infrared (NIR), from a Cr3+-doped LiGa5O8 NIR persistent phosphor exhibiting a super-long NIR persistent luminescence of more than 1,000?h. An intense PSPL signal peaking at 716?nm can be repeatedly obtained in a period of more than 1,000?h when an ultraviolet-light (250360?nm) pre-irradiated LiGa5O8:Cr3+ phosphor is repeatedly stimulated with a visible light or a NIR light. The LiGa5O8:Cr3+ phosphor has promising applications in optical information storage, night-vision surveillance, and in vivo bio-imaging. PMID:23532003

  12. The terminal portion of leptospiral immunoglobulin-like protein LigA confers protective immunity against lethal infection in the hamster model of leptospirosis

    PubMed Central

    Silva, verton F.; Medeiros, Marco A.; McBride, Alan J. A.; Matsunaga, Jim; Esteves, Gabriela S.; Ramos, Joo G. R.; Santos, Cleiton S.; Croda, Jlio; Homma, Akira; Dellagostin, Odir A.; Haake, David A.; Reis, Mitermayer G.; Ko, Albert I.

    2007-01-01

    Subunit vaccines are a potential intervention strategy against leptospirosis, which is a major public health problem in developing countries and a veterinary disease in livestock and companion animals worldwide. Leptospiral immunoglobulin-like (Lig) proteins are a family of surface-exposed determinants that have Ig-like repeat domains found in virulence factors such as intimin and invasin. We expressed fragments of the repeat domain regions of LigA and LigB from Leptospira interrogans serovar Copenhageni. Immunization of Golden Syrian hamsters with Lig fragments in Freunds adjuvant induced robust antibody responses against recombinant protein and native protein, as detected by ELISA and immunoblot, respectively. A single fragment, LigANI, which corresponds to the six carboxy-terminal Ig-like repeat domains of the LigA molecule, conferred immunoprotection against mortality (67-100%, P <0.05) in hamsters which received a lethal inoculum of L. interrogans serovar Copenhageni. However, immunization with this fragment did not confer sterilizing immunity. These findings indicate that the carboxy-terminal portion of LigA is an immunoprotective domain and may serve as a vaccine candidate for human and veterinary leptospirosis. PMID:17629368

  13. FDTD simulation of an 1x2 beam splitter using photonic bandgap on SOI wafer

    NASA Astrophysics Data System (ADS)

    Tsao, Shyh-Lin; Yang, Lan-Chih; Huang, Hsin-Chun; Hu, Shu-Fen

    2003-12-01

    In recent years, SOI optical waveguide is an attractive component of optical waveguide elements. Because fabrication of complementary metal oxide semiconductor (CMOS) electronic devices on SOI wafers shows promising results in the future low-power, high speed electronic device, and SOI opto-electronic integrated devices becomes an important issue[1]. Owing to the presence of periodically positioned scatters, the PBG theory is based on the principle of localization. If periodicity is equal or near a wavelength, the frequency of lightwave within the bandgap is stuck inside the material and not allowed to propagation. Recently, PBG have been suggested for a variety of optoelectronic applications, such as ultra low threshold lasers, high transmission waveguides with a bending radius comparable to the light wavelength[2]. In this paper, we design and analyze the 3 db 1x2 PBG splitter on SOI wafer, we simulated the 1x2 PBG splitter by finite difference time domain ( FDTD ) technology. In this work, our designed SOI wafer waveguide includes a 0.4 ?m oxide layer and a 1.5 ?m crystal silicon surface layer. The buried oxide structure is a planar slab working as the lower cladding ( nsio2 = 1.5 ) layer, the surface silicon layer (nsi = 3.5 ) is the waveguide core and the top cladding is air ( nair = 1 ). The width of rib waveguide is 4?m. The device is less than 30?m2, the input lightwave is separated into two opposite directions. In the future, we expect such a novel device can be applied in many very large scale opto-electronic integrated circuits. Reference [1] A. Layadi, A. Vonsovical, R. Orobtchouk, D. Pascal, and A. Koster, 'Low loss optical waveguide on standard SOI/SIMOX substrate', Optical Communication, vol. 146, pp. 31-33, 1998. [2] Park Young-Jin, A. Herschlein and W. Wiesbeck, 'A photonic bandgap (PBG) structure for guiding and suppressing surface waves in millimeter-wave antennas', IEEE Transactions on Microwave Theory and Techniques, vol. 49, pp. 1854-1859, 2001.

  14. A practical approach to LWIR wafer-level optics for thermal imaging systems

    NASA Astrophysics Data System (ADS)

    Symmons, Alan; Pini, Ray

    2013-06-01

    The development and implementation of wafer level packaging for commercial microbolometers has opened the pathway towards full wafer-based thermal imaging systems. The next challenge in development is moving from discrete element LWIR imaging systems to a wafer based optical system, similar to lens assemblies found in cell phone cameras. This paper will compare a typical high volume thermal imaging design manufactured from discrete lens elements to a similar design optimized for manufacture through a wafer based approach. We will explore both performance and cost tradeoffs as well as review the manufacturability of all designs.

  15. Effect of internal stresses on the mechanical parameters of silicon wafers

    SciTech Connect

    Oksanich, A.P.; Cherner, V.M.; Tuzovskii, K.A.

    1988-12-01

    The authors examined how the mechanical parameters of silicon wafers vary with the stress area. The polished (100) wafers were cut from a billet grown by Czochralski's method. The internal stresses were produced by moving the wafers in and out of an oven having a working zone at 1420 K. Then the oxide film was removed. The area of the stressed parts was determined by photoelasticity. The mechanical parameters were measured with contactless pneumatic loading and continuous central deflection measurement. The internal stresses affect the properties; at a given load the central deflection in an unstressed wafer is larger than in a stressed one.

  16. Determination of wafer center position during the transfer process by using the beam-breaking method

    NASA Astrophysics Data System (ADS)

    Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

    2014-09-01

    A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human-machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions.

  17. Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

    NASA Astrophysics Data System (ADS)

    Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

    2015-07-01

    Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

  18. The optimization of CD uniformity and measurement on mask and wafer

    NASA Astrophysics Data System (ADS)

    Choi, Yongkyoo; Kim, Munsik; Han, Oscar

    2007-05-01

    As pattern size is shrinking, required mask CD specification is tighter and its effect on wafer patterning is more severe. To enhance the device performance, wafer CD uniformity should be enhanced and controlled by mask global CD uniformity. Mask global CD uniformity usually can be enhanced by mask process and optimal fogging effect correction. To enhance the mask global CD uniformity on mask, resist process and FEC (Fogging Effect Correction), reliable CD measurement tool and methods are necessary. Recently, group CD using OCD(Spectroscopic Ellipsometer) or AIMS(Aerial Image Measurement and Simulation) is used to represent global CD variation on mask. These methods are removing local CD variation on mask. Because local CD variation on wafer is large compared with the effect of local CD variation of mask, global CD uniformity can be measured with suppressed local CD variation [1]. In this paper, local CD variation of mask and wafer is evaluated, and area CD and smoothing methods are used to measure CD on mask and wafer, and the correlation of global CD of mask and field CD of wafer are evaluated. By these methods, CD measurement repeatability can be enhanced to get closer correlation of mask and wafer. Close correlation makes fine CD correction on mask to get better field CD uniformity on wafer. And the repeatability of field to field CD uniformity of wafer is evaluated according to measurement tool of CD-SEM and scatterometry.

  19. Measuring the thickness profiles of wafers to subnanometer resolution using Fabry-Perot interferometry

    SciTech Connect

    Farrant, David I.; Arkwright, John W.; Fairman, Philip S.; Netterfield, Roger P

    2007-05-20

    The resolution of an angle-scanning technique for measuring transparent optical wafers is analyzed, and it is shown both theoretically and experimentally that subnanometer resolution can be readily achieved. Data are acquired simultaneously over the whole area of the wafer, producing two-dimensional thickness variation maps in as little as 10 s.Repeatabilities of 0.07 nm have been demonstrated, and wafers of up to100 mm diameter have been measured, with1 mm or better spatial resolution. A technique for compensating wafer and system aberrations is incorporated and analyzed.

  20. Patterning of photocleavable zwitterionic polymer brush fabricated on silicon wafer.

    PubMed

    Kamada, Tomohiro; Yamazawa, Yuka; Nakaji-Hirabayashi, Tadashi; Kitano, Hiromi; Usui, Yuki; Hiroi, Yoshiomi; Kishioka, Takahiro

    2014-11-01

    Brushes of a polymer, namely poly(carboxymethylbetaine) (PCMB), were fabricated on silicon wafers by reversible addition-fragmentation chain-transfer (RAFT) polymerization using a surface-confined RAFT agent having an aromatic group at its bottom. The polymer brush showed effective suppression of the non-specific adsorption of bovine serum albumin (BSA) and adhesion of fibroblasts (3T3 cells). In contrast, BSA and 3T3 cells significantly adsorbed on and adhered to positively or negatively charged polymer brushes fabricated by the same procedure. Upon UV irradiation at 193 nm, the thickness of the PCMB brush with an aromatic group at its bottom decreased significantly whereas PCMB prepared using a surface-confined RAFT agent without an aromatic group needed a much higher irradiation dose to afford a comparable decrease in thickness. These results indicate a preferential cleavage of the PCMB brush due to photodecomposition of the phenyl group at the bottom. BSA and 3T3 cells non-specifically adsorbed on and adhered to the UV irradiation-induced hollow spaces, respectively. Furthermore, a designed pattern with a resolution of 5 ?m was successfully made on the PCMB brush above the silicon wafer by simple UV irradiation. These results suggest that the surface-confined aromatic RAFT agent will be quite useful for simple photolithography in biomedical fields. PMID:25466462

  1. Dual-Side Wafer Processing and Resonant Tunneling Transistor Applications

    SciTech Connect

    Moon, J.S.; Simmons, J.A.; Wendt, J.R.; Hietala, V.M.; Reno, J.L.; Baca, W.E.; Blount, M.A.

    1999-07-20

    We describe dual-side wafer processing and its application to resonant tunneling transistors in a planar configuration. The fabrication technique utilizes a novel flip-chip, wafer thinning process called epoxy-bond and stop-etch (EBASE) process, where the substrate material is removed by selective wet etching and stopped at an etch-stop layer. This EBASE method results in a semiconductor epitaxial layer that is typically less than a micron thick and has a mirror-finish, allowing backside gates to be placed in close proximity to frontside gates. Utilizing this technique, a resonant tunneling transistor--the double electron layer tunneling transistor (DELTT)--can be fabricated in a fully planar configuration, where the tunneling between two selectively-contacted 2DEGs in GaAs or InGaAs quantum wells is modulated by surface Schottky gate. Low temperature electrical characterization yields source-drain I-V curves with a gate-tunable negative differential resistance.

  2. Steel bridge fatigue crack detection with piezoelectric wafer active sensors

    NASA Astrophysics Data System (ADS)

    Yu, Lingyu; Giurgiutiu, Victor; Ziehl, Paul; Ozevin, Didem; Pollock, Patrick

    2010-04-01

    Piezoelectric wafer active sensors (PWAS) are well known for its dual capabilities in structural health monitoring, acting as either actuators or sensors. Due to the variety of deterioration sources and locations of bridge defects, there is currently no single method that can detect and address the potential sources globally. In our research, our use of the PWAS based sensing has the novelty of implementing both passive (as acoustic emission) and active (as ultrasonic transducers) sensing with a single PWAS network. The combined schematic is using acoustic emission to detect the presence of fatigue cracks in steel bridges in their early stage since methods such as ultrasonics are unable to quantify the initial condition of crack growth since most of the fatigue life for these details is consumed while the fatigue crack is too small to be detected. Hence, combing acoustic emission with ultrasonic active sensing will strengthen the damage detection process. The integration of passive acoustic emission detection with active sensing will be a technological leap forward from the current practice of periodic and subjective visual inspection, and bridge management based primarily on history of past performance. In this study, extensive laboratory investigation is performed supported by theoretical modeling analysis. A demonstration system will be presented to show how piezoelectric wafer active sensor is used for acoustic emission. Specimens representing complex structures are tested. The results will also be compared with traditional acoustic emission transducers to identify the application barriers.

  3. Process Performance of Optima XEx Single Wafer High Energy Implanter

    SciTech Connect

    Kim, J. H.; Yoon, Jongyoon; Kondratenko, S.; David, J.; Rubin, L. M.; Jang, I. S.; Cha, J. C.; Joo, Y. H.; Lee, A. B.; Jin, S. W.

    2011-01-07

    To meet the process requirements for well formation in future CMOS memory production, high energy implanters require more robust angle, dose, and energy control while maintaining high productivity. The Optima XEx high energy implanter meets these requirements by integrating a traditional LINAC beamline with a robust single wafer handling system. To achieve beam angle control, Optima XEx can control both the horizontal and vertical beam angles to within 0.1 degrees using advanced beam angle measurement and correction. Accurate energy calibration and energy trim functions accelerate process matching by eliminating energy calibration errors. The large volume process chamber and UDC (upstream dose control) using faraday cups outside of the process chamber precisely control implant dose regardless of any chamber pressure increase due to PR (photoresist) outgassing. An optimized RF LINAC accelerator improves reliability and enables singly charged phosphorus and boron energies up to 1200 keV and 1500 keV respectively with higher beam currents. A new single wafer endstation combined with increased beam performance leads to overall increased productivity. We report on the advanced performance of Optima XEx observed during tool installation and volume production at an advanced memory fab.

  4. Photonic crystal preparation by a wafer bonding approach

    NASA Astrophysics Data System (ADS)

    Yamamoto, Noritsugu; Ogawa, Shinpei; Imada, Masahiro; Noda, Susumu

    2001-10-01

    Various important scientific and engineering applications, such as control of spontaneous emission, zero-threshold lasing, sharp bending of light, and trapping of photons, are expected by using photonic bandgap (PBG) crystals with artificially introduced defect states and/ or light-emitters. Realizing the maximum potential of photonic crystals requires the following steps: (i) construct a three-dimensional (3D) crystal with a complete photonic bandgap in the optical wavelength region; (ii) introduce an arbitrary defect into the crystal at an arbitrary position; (iii) introduce an efficient light-emitter; and, (iv) use an electronically conductive crystal, as this is desirable for actual device application. Although various approaches to constructing 3D crystals have been proposed and investigated, none of these reports satisfies the above requirements simultaneously. To develop complete 3D crystals at infrared (5-10um) to near-infrared wavelengths (1-2um), we stacked III-V semiconductor gratings into a diamond structure by means of wafer bonding and a laser-beam-assisted very precise alignment technique. Since the crystal is constructed with III-V semiconductors, which are widely used for optoelectronic devices, requirement (iii) is satisfied. Moreover, as the wafer bonding enables us to construct an arbitrary structure and to form an electronically conductive interface, all the above requirements (i)-(iv) will be satisfied. In this paper, we review our approach for creating full 3D photonic bandgap crystals at near-infrared wavelengths.

  5. Deposition and removal of sodium contamination on silicon wafers

    NASA Astrophysics Data System (ADS)

    Constant, I.; Tardif, F.; Derrien, J.

    2000-01-01

    In this paper investigations are performed in order to understand the source of sodium contamination in clean-room environments and to find different cleaning processes able to limit or suppress sodium deposition. In a clean-room environment, the human being has been identified as one of the major sources of sodium. The airborne sodium contamination is essentially transmitted in particle form. In order to limit sodium deposition from the air, the wafers awaiting subsequent processing need to be stored in a protective box or placed far from the human environment and should not be left for much more than 1 week in a class 1 clean room. Also, wet chemistries could cause sodium contamination on wafers particularly during the deionized water rinse. In order to limit the possible contamination, the sodium deposition mechanisms have been studied: they show the typical characteristics of Langmuir adsorption. Temperature and ionic concentration are both parameters which influence the deposition. In water, sodium deposition can be avoided by introducing acid or alkaline solutions or increasing the temperature: it can be drastically reduced by adding traces of HCl (0.01%). Finally, other cleaning chemistries such as SC1 (NH4 OH-H2 O2 -H2 O) in 0.25:1:5 proportion, SC2 (HCl-H2 O2 -H2 O) in 1:1:5 proportion, 0.1% HF and SPM (H2 SO4 -H2 O2 ) in 3:1 proportion reduce the contamination as well.

  6. Laser-Assisted Chemical Polishing of Silicon (112) Wafers

    NASA Astrophysics Data System (ADS)

    Dandekar, Niru; Chivas, Robert; Silverman, Scott; Kou, Xiaolu; Goorsky, Mark

    2012-10-01

    Pulsed laser-assisted chemical etching (PLACE) offers an advanced, novel substrate preparation method for molecular beam epitaxy (MBE) growth of mercury cadmium telluride on silicon (112) wafers. By controlling the laser fluence, the chemical etch process is refined into a final polish step. PLACE offers surface roughness on the order of chemical mechanical polishing standards and has been verified by 488-nm Raman and high-resolution x-ray diffraction as causing no surface or subsurface damage. To the contrary, experiments show that using PLACE not only alters the surface chemically but also removes subsurface damage through recrystallization reaching micron depths. The process occurs in a modular vacuum chamber that could conceivably be transferred between tools so that vacuum is not broken between polishing and MBE deposition. PLACE can achieve ultra-high-purity and fine dimensional control since it is a dry process relying on pyrolytic vapor-phase reactions initiated, and constrained, by a pulsed laser. Since the process is a function of laser fluence and optics, it is imminently scalable to 6-inch wafer sizes and beyond.

  7. Simultaneous dose and focus monitoring on product wafers

    NASA Astrophysics Data System (ADS)

    Eichelberger, Brad J.; Dinu, Berta; Pedut, H.

    2003-05-01

    As the design rules shrink below 130nm it will become increasingly important to monitor and control focus and dose in-line, on product wafers to maintain the ever-decreasing process window. On process layers today, it is not uncommon to see focus related errors equaling between 50-100nm in magnitude. Today these errors go undetected and CD changes are typically corrected by making a dose correction to the exposure tool. However, corrections using dose can lead to significantly smaller process latitude and therefore, products out of spec. Using a technique that was first developed by Christopher Ausschnitt at IBM Microelectronics it is possible to monitor focus and dose on production layers with a single compact target. Extending this technology on an advanced optical tool allows for precise measurements of focus and dose errors. This paper will describe the methodology of inline focus and dose monitoring using this technique on 130nm process technology with an outlook on the expectations for future nodes. Results, including focus and dose sensitivity from multiple process steps on production wafers will be shown.

  8. Alternative fabrication process for edgeless detectors on 6 in. wafers

    NASA Astrophysics Data System (ADS)

    Kalliopuska, Juha; Eränen, Simo; Virolainen, Tuula

    2011-05-01

    VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150 μm thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 5×5 and 1×1 cm2 edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.4×1.4 cm2 Medipix2 edgeless pixel detectors were also fabricated.This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100 μm from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50-70 nA/cm2 and 580-660 pF/cm2 at, respectively, 40 V reverse bias for the p-on-n. For the n-on-n design these parameters were 116-118 nA/cm2 and 930-960 pF/cm2. The breakdown voltages were above 150 V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13-28 V.

  9. High-accuracy inspection of defects and profile of wafers by phase measuring deflectometry

    NASA Astrophysics Data System (ADS)

    Yue, Huimin; Wu, Yuxiang; Zhao, Biyu; Ou, Zhonghua; Liu, Yong

    2014-09-01

    The demands of the less-defective and high-flatness wafers are urgent in many wafer based technologies ranging from micro-electronics to the current photovoltaic industry. As the wafer becomes thinner and larger to cope with the advances in those industries, there is an increasing possibility of the emerging of crack and warp on the wafer surface. High-accuracy inspection of defects and profile are thus necessary to ensure the reliability of device. Phase measuring deflectometry(PMD) is a fast, cost-effective and high accuracy measurement technology which has been developed in recent years. As a slope measurement technology, PMD possesses a high sensitivity. Very small slope variation will lead to a large variation of the phase. PMD is very possible to have a good performance in the wafer inspection. In this paper, the requirements of the wafer inspection in the industries are discussed, and compatibility of PMD and those requirements is analyzed. In the experimental work, PMD gets the slope information of the wafer surface directly. The curvature or height information can be acquired simply by the derivation or integral of the slope. PMD is proved to make a superior result in high-precision defect detecting and shape measurement of wafer by the analysis of experiment results.

  10. Experimental investigation of piezoelectric wafers in monitoring the resin transfer moulding process

    NASA Astrophysics Data System (ADS)

    Wang, Xiaoming; Ehlers, Claus; Kissinger, Christian; Neitzel, Manfred; Ye, Lin; Mai, Yiu-Wing

    1998-02-01

    The objective of monitoring the composite manufacturing process resin transfer moulding (RTM) is pursued by means of applying piezoelectric wafers. First, the sensitivity of the piezoelectric wafers to their area wetted by a viscous liquid was evaluated to shed light on the possibility of utilizing the wafers for the inspection of the resin flow front during RTM. Further, the wafers were immersed in various liquids of different viscosity, to confirm their ability to distinguish such difference. The ability would then be employed to monitor the curing process before gelling of resins. Thirdly, the experimental set-up proved the validity of the wafers for sensing the change of temperature associated with the curing process around the gel point. The overall capability of the piezoelectric wafers to monitor the injection and curing process of thermosets in RTM was investigated, incorporating the wafers in random glass fibre mats of a preform injected with a thermoset resin. Experimental verification has shown promising results and demonstrated potential for using piezoelectric wafers as a novel method for complete process monitoring of composite manufacturing.

  11. Low target power wafer sputtering regime identified during magnetron tantalum barrier physical vapor deposition

    SciTech Connect

    Stout, Phillip J.; Denning, Dean J.; Michaelson, Lynne M.; Bagchi, Sandeep; Zhang Da; Ventzek, Peter L. G.

    2005-07-15

    A wafer sputtering regime has been identified during tantalum barrier deposition using a magnetron physical vapor deposition (MPVD) tool. The MPVD tools are designed to operate at high target powers (tens of kW) where the highly directed energetic metal (athermal metal) is the dominant metal species incident on the wafer. Although athermal metal gives better coverage than neutral metal (thermal) due to the narrower range of incident strike angles to the wafer, shadowing by the feature geometries is still a concern. Having available a wafer sputter regime or 'resputter' regime in a PVD tool allows for redistribution of metal from horizontal surfaces in the feature exposed to the plasma to vertical surfaces in the feature. The key in obtaining a wafer sputter regime is the operation of the plasma source in a range that the wafer bias power is effective at generating a sufficient self-bias for sputtering to occur. Discussed are modeling results which predict the wafer sputtering regime and the experimental confirmation that the low target power wafer sputter regime exists. The identified sputter regime in MPVD is such that there is a net deposition of metal at the field. Metal thickness reduction does occur at the trench and via bottoms where much of the unionized metal is being shadowed yielding a lower deposition to sputtering ratio compared to the field.

  12. A Wafer Transfer Technology for MEMS Adaptive Optics

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean V.

    2001-01-01

    Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

  13. Nanotribology of nanooxide materials in ionic liquids on silicon wafers

    NASA Astrophysics Data System (ADS)

    Hamidunsani, Ahmad Termizi; Radiman, Shahidan; Hassan, Masjuki Haji; Rahman, Irman Abdul

    2015-09-01

    Nanotribological properties have a significant impact on daily life. Ionic liquids (ILs) are becoming new favourable lubricants currently in researches. Addition of nanooxide materials in lubricants provide improvements to new technology. In this study, we determine nanotribological properties of BMIM+BF4- IL addition of different amount of ZnO nanomaterial on single crystals silicon wafer (Si110). The viscosity changes of IL samples against temperature increase were determined by rheological method. Nanotribological properties were determined by changes in friction coefficient and wear rate on silicon substrate surfaces using a reciprocating friction and wear monitor in 1 hour duration time. Aluminium cylinders acted as pins used to rub Si (110) substrate sample surfaces. Thus, on range between 0 mg to 3.5 mg of ZnO nanooxide material dispersed in 10ml BMIM+BF4- showed a good friction coefficient, wear and surface roughness reduction.

  14. Precise Fabrication of Silicon Wafers Using Gas Cluster Ion Beams

    SciTech Connect

    Isogai, Hiromichi; Toyoda, Eiji; Izunome, Koji; Kashima, Kazuhiko; Mashita, Takafumi; Toyoda, Noriaki; Yamada, Isao

    2009-03-10

    Precise surface processing of a silicon wafer was studied by using a gas cluster ion beam (GCIB). The damage caused to the silicon surface was strongly dependent on irradiation parameters. The extent of damage varied with the species of source gas and the acceleration voltage (Va) of cluster ions. It also varied with the cluster size and residual gas pressure. The influence of electron acceleration voltage (Ve) used for ionization of a neutral cluster was also investigated. The irradiation damage, such as an amorphous silicon (a-Si) layer, a mixed layer of a-Si and c-Si (transition layer), and surface roughness, was increased with Ve. It is suggested that the increase in the amount of energy per atom was induced by high Ve, because of variation of the cluster size and/or cluster charge. An undamaged smooth surface can be produced by Ar-GCIB irradiation at low Ve and Va.

  15. Transient photoluminescence from silicon wafers: Finite element analysis

    NASA Astrophysics Data System (ADS)

    Wang, Kai; McLean, William; Kampwerth, Henner

    2013-10-01

    This paper presents an accurate and practical mathematical model of time-resolved photoluminescence (PL) response from silicon wafers generated by fast repetitive excitation pulses. The model is valid under low level injection condition and takes into account the depth dependence of carrier generation, diffusion, and surface recombination. Finite element analysis is employed for the carrier density and PL computations. By comparing computational results with results obtained from PC1D (a computer program solving fully coupled nonlinear equations for quasi-one-dimensional carrier transportation in crystalline semiconductor devices, especially focusing on photovoltaic devices), the validity of this method is confirmed. Early stage application and the limitations of this method have been studied, and future work has been proposed.

  16. Effect of lubricant environment on saw damage in silicon wafers

    NASA Technical Reports Server (NTRS)

    Kuan, T. S.; Shih, K. K.; Vanvechten, J. A.; Westdorp, W. A.

    1982-01-01

    The chemomechanical effect of lubricant environments on the inner diameter (ID) sawing induced surface damage in Si wafers was tested for four different lubricants: water, dielectric oil, and two commercial cutting solutions. The effects of applying different potential on Si crystals during the sawing were also tested. It is indicated that the number and depth of surface damage are sensitive to the chemical nature of the saw lubricant. It is determined that the lubricants that are good catalysts for breaking Si bonds can dampen the out of plane blade vibration more effectively and produce less surface damage. Correlations between the applied potential and the depth of damage in the dielectric oil and one of the commercial cutting solutions and possible mechanisms involved are discussed.

  17. Zinc sulfide nanowire arrays on silicon wafers for field emitters

    NASA Astrophysics Data System (ADS)

    Chen, Zhi-Gang; Cheng, Lina; Zou, Jin; Yao, Xiangdong; Qing Max Lu, Gao; Cheng, Hui-Ming

    2010-02-01

    Wurtzite structured zinc sulfide (ZnS) nanowire arrays are synthesized on silicon (111) wafers by a facile evaporation-condensation approach. These ZnS nanowire arrays possess predominant field emission properties with a low turn-on field of 2.9 V m-1, a low threshold field of 4.25 V m-1, a high field-enhancement factor (over 2700), and a high stability with a low fluctuation (~0.8%). The improved field emission performance of these ZnS nanowire arrays is attributed to their specific crystallographic featurearray structures with nanotips and high single crystallinity. These results suggest that such ZnS nanowire arrays can be used as building blocks for field emitters.

  18. Characterization of semiconductor surface-emitting laser wafers

    SciTech Connect

    Gourley, P.L.; Vawter, G.A.; Brennan, T.M.; Hammons, B.E.

    1990-01-01

    The development of epitaxial semiconductor surface-emitting lasers has begun in recent years. These lasers are ultra-short (few {mu}m) Fabry-Perot resonators comprising epitaxial multilayer semiconductor mirrors and quantum well active regions. The resonators are single crystals grown along the lasing axis by molecular beam epitaxy (MBE) or chemical vapor deposition (CVD). They offer significant advances over conventional cleaved, edge-emitting lasers for creating lasers with single elements of 2 dimensional arrays, low beam divergence, engineered active regions, single longitudinal modes, and improved temperature characteristics. To realize the high potential of these new laser structures, techniques for characterizing the laser wafer after growth and between fabrication steps must be developed. In this paper we discuss several optical techniques that we have developed for this emerging surface-emitting laser technology.

  19. Homogenization of CZ Si wafers by Tabula Rasa annealing

    NASA Astrophysics Data System (ADS)

    Meduňa, M.; Caha, O.; Kuběna, J.; Kuběna, A.; Buršík, J.

    2009-12-01

    The precipitation of interstitial oxygen in Czochralski grown silicon has been investigated by infrared absorption spectroscopy, chemical etching, transmission electron microscopy and X-ray diffraction after application of homogenization annealing process called Tabula Rasa. The influence of this homogenization step consisting in short time annealing at high temperature has been observed for various temperatures and times. The experimental results involving the interstitial oxygen decay in Si wafers and absorption spectra of SiOx precipitates during precipitation annealing at 1000C were compared with other techniques for various Tabula Rasa temperatures. The differences in oxygen precipitation, precipitate morphology and evolution of point defects in samples with and without Tabula Rasa applied is evident from all used experimental techniques. The results qualitatively correlate with prediction of homogenization annealing process based on classical nucleation theory.

  20. Visible luminescence from silicon wafers subjected to stain etches

    NASA Technical Reports Server (NTRS)

    Fathauer, R. W.; George, T.; Ksendzov, A.; Vasquez, R. P.

    1992-01-01

    Etching of Si in a variety of solutions is known to cause staining. These stain layers consist of porous material similar to that produced by anodic etching of Si in HF solutions. In this work, photoluminescence peaked in the red from stain-etched Si wafers of different dopant types, concentrations, and orientations produced in solutions of HF:HNO3:H2O was observed. Luminescence is also observed in stain films produced in solutions of NaNO2 in HF, but not in stain films produced in solutions of CrO3 in HF. The luminescence spectra are similar to those reported recently for porous Si films produced by anodic etching in HF solutions. However, stain films are much easier to produce, requiring no special equipment.

  1. Chemical strategies for die/wafer submicron alignment and bonding.

    SciTech Connect

    Martin, James Ellis; Baca, Alicia I.; Chu, Dahwey; Rohwer, Lauren Elizabeth Shea

    2010-09-01

    This late-start LDRD explores chemical strategies that will enable sub-micron alignment accuracy of dies and wafers by exploiting the interfacial energies of chemical ligands. We have micropatterned commensurate features, such as 2-d arrays of micron-sized gold lines on the die to be bonded. Each gold line is functionalized with alkanethiol ligands before the die are brought into contact. The ligand interfacial energy is minimized when the lines on the die are brought into registration, due to favorable interactions between the complementary ligand tails. After registration is achieved, standard bonding techniques are used to create precision permanent bonds. We have computed the alignment forces and torque between two surfaces patterned with arrays of lines or square pads to illustrate how best to maximize the tendency to align. We also discuss complex, aperiodic patterns such as rectilinear pad assemblies, concentric circles, and spirals that point the way towards extremely precise alignment.

  2. Effects of wafer bow and warpage on the integrity of thin gate oxides

    NASA Astrophysics Data System (ADS)

    Thakur, R. P. S.; Chhabra, N.; Ditali, A.

    1994-06-01

    We have studied the effects of initial wafer bow and warpage on the integrity of thinner gate oxides grown by both furnace and rapid thermal processing (RTP) methods. There is evidence of a correlation between wafer warpage and bow to the charge-to-breakdown characteristics of the gate oxide. An almost linear increase in defect density was observed when plotted as a function of increasing wafer warpage. The lifetime (t50%) of the samples with initial warpage of 10 ?m or less is reported higher than those with initial warpage of more than 60 ?m for both furnace and RTP-grown oxides. The value of bow for the warped samples was taken for cases with the highest positive and negative values so both kinds of shape trends could be investigated. With initial wafer warpage ranging from 4 to 70 ?m, we present the results of wafer dimensional analysis and correlate these to defect density and lifetime studies for thin gate oxides.

  3. Multiple-surface interferometry of highly reflective wafer by wavelength tuning.

    PubMed

    Kim, Yangjin; Hibino, Kenichi; Hanayama, Ryohei; Sugita, Naohiko; Mitsuishi, Mamoru

    2014-09-01

    The surface shape and optical thickness variation of a lithium niobate (LNB) wafer were measured simultaneously using a wavelength-tuning interferometer with a new phase-shifting algorithm. It is necessary to suppress the harmonic signals for testing a highly reflective sample such as a crystal wafer. The LNB wafer subjected to polishing, which is in optical contact with a fused-silica (FS) supporting plate, generates six different overlapping interference fringes. The reflectivity of the wafer is typically 15%, yielding significant harmonic signals. The new algorithm can flexibly select the phase-shift interval and effectively suppress the harmonic signals and crosstalk. Experimental results indicated that the optical thickness variation of the LNB wafer was measured with an accuracy of 2 nm. PMID:25321495

  4. Modelling wafer bow in silicon-polycrystalline CVD diamond substrates for GaN-based devices

    NASA Astrophysics Data System (ADS)

    Edwards, M. J.; Bowen, C. R.; Allsopp, D. W. E.; Dent, A. C. E.

    2010-09-01

    Composite silicon-polycrystalline chemical vapour deposition (CVD) diamond wafers are potential substrates for GaN-based devices for use in harsh environments due to their high thermal conductivity and chemical stability. When cooled from a typical diamond deposition temperature of approximately 800 to 25 C wafer bowing arises from a mismatch in the coefficients of thermal expansion of silicon and polycrystalline diamond. In this paper 100 mm diameter silicon-polycrystalline diamond wafers have been modelled using ANSYS finite element software to investigate their bowing behaviour as a function of temperature and geometry. The maximum bow of a wafer occurred where the thicknesses of both the silicon and polycrystalline diamond layers was almost identical; this has been confirmed using analytical methods. Strategies are discussed for reducing wafer bow.

  5. Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

    SciTech Connect

    Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

    2006-03-13

    An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection.

  6. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbracher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-07-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  7. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbrecher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-01-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  8. High performance LWIR microbolometer with Si/SiGe quantum well thermistor and wafer level packaging

    NASA Astrophysics Data System (ADS)

    Roer, Audun; Lapadatu, Adriana; Bring, Martin; Wolla, Erik; Hohler, Erling; Kittilsland, Gjermund

    2011-11-01

    An uncooled microbolometer with peak responsivity in the long wave infrared region of the electromagnetic radiation is developed at Sensonor Technologies. It is a 384 x 288 focal plane array with a pixel pitch of 25?m, based on monocrystalline Si/SiGe quantum wells as IR sensitive material. The high sensitivity (TCR) and low 1/f noise are the main performance characteristics of the product. The frame rate is maximum 60Hz and the output interface is digital (LVDS). The quantum well thermistor material is transferred to the read-out integrated circuit (ROIC) by direct wafer bonding. The ROIC wafer containing the released pixels is bonded in vacuum with a silicon cap wafer, providing hermetic encapsulation at low cost. The resulting wafer stack is mounted in a standard ceramic package. In this paper the architecture of the pixels and the ROIC, the wafer packaging and the electro-optical measurement results are presented.

  9. Effects of wafer impedance on the monitoring and control of ion energy in plasma reactors

    SciTech Connect

    Sobolewski, Mark A.

    2006-09-15

    Ion kinetic energy in plasma reactors is controlled by applying radio-frequency (rf) substrate bias, but the efficiency and reproducibility of such control will be affected if the wafer being processed has a significant electrical impedance. Here, the effects of wafer impedance were studied by modeling and electrical measurements. Models of wafer impedance were proposed and tested by comparing model predictions to measured electrical wave forms. The tests were performed in an inductively coupled plasma reactor in 50% Ar, 50% CF{sub 4} gas at a pressure of 1.33 Pa (10 mTorr), rf bias frequencies of 0.1-10 MHz, rf bias amplitudes of 20-300 V, and inductive source powers of 100-500 W. At high bias frequencies, the dominant contribution to the wafer impedance was the capacitance of the gap between the wafer and its chuck. At low bias frequencies, however, a resistance associated with the contact between the wafer and the chuck became significant. Electrical wave forms and ion energy distributions were most sensitive to wafer impedance at low bias frequencies and low bias amplitudes. At low bias frequencies, model predictions indicate that the wafer impedance produces an undesirable variation in surface potential, sheath voltage, and ion energy across the wafer surface. Because it neglects wafer impedance effects, a technique that analyzes electrical wave forms to determine ion currents, sheath voltages, and ion energy distributions was found to suffer significant errors at low bias frequencies and amplitudes. Nevertheless, the technique provided accurate results at moderate to high bias frequency and amplitude.

  10. A universal process development methodology for complete removal of residues from 300mm wafer edge bevel

    NASA Astrophysics Data System (ADS)

    Randall, Mai; Linnane, Michael; Longstaff, Chris; Ueda, Kenichi; Winter, Tom

    2006-03-01

    Many yield limiting, etch blocking defects are attributed to "flake" type contamination from the lithography process. The wafer edge bevel is a prime location for generation of this type of defect. Wafer bevel quality is not readily observed with top down or even most off axis inspection equipment. Not all chemistries are removed with one "universal" cleaning process. IC manufacturers must maximize usable silicon area as well. These requirements have made traditional chemical treatments to clean the wafer edge inadequate for many chemistry types used in 193nm processing. IBM has evaluated a method to create a robust wafer bevel and backside cleaning process. An August Technology AXi TM Series advanced macro inspection tool with E20 TM edge inspection module has been used to check wafer bevel cleanliness. Process impact on the removal of post apply residues has been investigated. The new process used backside solvent rinse nozzles only and cleaned the wafer bevel completely. The use of the topside edge solvent clean nozzles was eliminated. Thickness, wet film defect measurements (wet FM), and pattern wafer defect monitors showed no difference between the new backside rinse edge bead removal process and the process of record. Solvent topside edge bead removal of both bottom anti-reflective coatings and resist materials showed better cut width control and uniformity. We conclude that the topside solvent edge bead removal nozzle can be removed from the process. Backside solvent rinse nozzles can clean the backside of the wafer, the wafer bevel, and can wrap to the front edge of the wafer to provide a uniform edge bead removal cut width that is not sensitive to coater module tolerances. Recommendations are made for changes to the typical preventive maintenance procedures.

  11. The role of Gliadel wafers in the treatment of newly diagnosed GBM: a meta-analysis

    PubMed Central

    Xing, Wei-kang; Shao, Chuan; Qi, Zhen-yu; Yang, Chao; Wang, Zhong

    2015-01-01

    Background Standard treatment for high-grade glioma (HGG) includes surgery followed by radiotherapy and/or chemotherapy. Insertion of carmustine wafers into the resection cavity as a treatment for malignant glioma is currently a controversial topic among neurosurgeons. Our meta-analysis focused on whether carmustine wafer treatment could significantly benefit the survival of patients with newly diagnosed glioblastoma multiforme (GBM). Method We searched the PubMed and Web of Science databases without any restrictions on language using the keywords Gliadel wafers, carmustine wafers, BCNU wafers, or interstitial chemotherapy in newly diagnosed GBM for the period from January 1990 to March 2015. Randomized controlled trials (RCTs) and cohort studies/clinical trials that compared treatments designed with and without carmustine wafers and which reported overall survival or hazard ratio (HR) or survival curves were included in this study. Moreover, the statistical analysis was conducted by the STATA 12.0 software. Results Six studies including two RCTs and four cohort studies, enrolling a total of 513 patients (223 with and 290 without carmustine wafers), matched the selection criteria. Carmustine wafers showed a strong advantage when pooling all the included studies (HR =0.63, 95% confidence interval (CI) =0.490.81; P=0.019). However, the two RCTs did not show a statistical increase in survival in the group with carmustine wafer compared to the group without it (HR =0.51, 95% CI =0.181.41; P=0.426), while the cohort studies demonstrated a significant survival increase (HR =0.59, 95% CI =0.440.79; P<0.0001). Conclusion Carmustine-impregnated wafers play a significant role in improving survival when used for patients with newly diagnosed GBM. More studies should be designed for newly diagnosed GBM in the future. PMID:26170620

  12. Creating a single twin boundary between two CdTe (111) wafers with controlled rotation angle by wafer bonding

    SciTech Connect

    Sun, Ce; Lu, Ning; Wang, Jinguo; Lee, Jihyung; Peng, Xin; Kim, Moon J.; Klie, Robert F.

    2013-12-16

    The single twin boundary with crystallographic orientation relationship (1{sup ¯}1{sup ¯}1{sup ¯})//(111) [01{sup ¯}1]//[011{sup ¯}] was created by wafer bonding. Electron diffraction patterns and high-resolution transmission electron microscopy images demonstrated the well control of the rotation angle between the bonded pair. At the twin boundary, one unit of wurtzite structure was found between two zinc-blende matrices. High-angle annular dark-field scanning transmission electron microscopy images showed Cd- and Te-terminated for the two bonded portions, respectively. The I-V curve across the twin boundary showed increasingly nonlinear behavior, indicating a potential barrier at the bonded twin boundary.

  13. Infrared differential interference contrast microscopy for overlay metrology on 3D-interconnect bonded wafers

    NASA Astrophysics Data System (ADS)

    Ku, Yi-sha; Shyu, Deh-Ming; Lin, Yeou-Sung; Cho, Chia-Hung

    2013-04-01

    Overlay metrology for stacked layers will be playing a key role in bringing 3D IC devices into manufacturing. However, such bonded wafer pairs present a metrology challenge for optical microscopy tools by the opaque nature of silicon. Using infrared microscopy, silicon wafers become transparent to the near-infrared (NIR) wavelengths of the electromagnetic spectrum, enabling metrology at the interface of bonded wafer pairs. Wafers can be bonded face to face (F2F) or face to back (F2B) which the stacking direction is dictated by how the stacks are carried in the process and functionality required. For example, Memory stacks tend to use F2B stacking enables a better managed design. Current commercial tools use single image technique for F2F bonding overlay measurement because depth of focus is sufficient to include both surfaces; and use multiple image techniques for F2B overlay measurement application for the depth of focus is no longer sufficient to include both stacked wafer surfaces. There is a need to specify the Z coordinate or stacking wafer number through the silicon when visiting measurement wafer sites. Two shown images are of the same (X, Y) but separate Z location acquired at focus position of each wafer surface containing overlay marks. Usually the top surface image is bright and clear; however, the bottom surface image is somewhat darker and noisier as an adhesive layer is used in between to bond the silicon wafers. Thus the top and bottom surface images are further processed to achieve similar brightness and noise level before merged for overlay measurement. This paper presents a special overlay measurement technique, using the infrared differential interference contrast (DIC) microscopy technique to measure the F2B wafer bonding overlay by a single shot image. A pair of thinned wafers at 50 and 150 μm thickness is bonded on top of a carrier wafer to evaluate the bonding overlay. It works on the principle of interferometry to gain information about the optical path length of the stacked wafers, to enhance the image contrast of overlay marks features even though they are locating in different Z plane. A two dimensional mirror-symmetric overlay marks for both top and bottom processing wafers is designed and printed in each die in order to know and realize the best achievable wafer to wafer bonding processing. A self-developed analysis algorithms is used to identify the overlay error between the stacking wafers and the interconnect structures. The experimental overlay results after wafer bonding including inter-die and intra-die analysis results will be report in the full paper. Correlation of overlay alignment offset data to electrical yield, provides an early indication of bonded wafer yield.

  14. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates.

    PubMed

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-01-01

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the "melt-back" effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4 off-axis Si enhances the step-flow growth at 1200?C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20??m was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude. PMID:26487465

  15. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates

    PubMed Central

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-01-01

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the melt-back effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4 off-axis Si enhances the step-flow growth at 1200?C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20??m was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude. PMID:26487465

  16. Evaluation of the technical feasibility and effective cost of various wafer thicknesses for the manufacture of solar cells

    NASA Technical Reports Server (NTRS)

    1978-01-01

    Three wafering demonstration runs were completed on the Yasunaga wire saw. Wafer thickness/taper uniformity is excellent. Many small problems were encountered with Yasunaga accessories, slowing the effort. A wafer characterization cycle was defined and will be initiated during the next period.

  17. Mapping of Defects in Large-Area Silicon Carbide Wafers via Photoluminescence and its Correlation with Synchrotron White Beam X-Ray Topography

    SciTech Connect

    Chen, Yi; Balaji, R.; Dudley, Michael; Murthy, Madhu; Maximenko, Serguei I.; Freitas, Jamie A.

    2008-12-12

    Comparative studies of defect microstructure in 4H-SiC wafers have been carried out using photoluminescence (PL) imaging and grazing-incidence Synchrotron White Beam X-ray Topography. Images of low angle grain boundaries on the PL images correlate well with SWBXT observations, and similar correlation can be established for some micropipe images although the latter is complicated by the overall level of distortion and misorientation associated with the low angle grain boundaries and the fact that many of the micropipes are located in or close to the boundaries. This validation indicates that PL imaging may provide a rapid way of imaging such defect structures in large-scale SiC wafers.

  18. Therml & Gravitational Stress in Si Wafers; Lim. on Process Htg & Cool. Rates

    Energy Science and Technology Software Center (ESTSC)

    1997-01-14

    The MacWafer code determines maximum allowable processing temperatures and maximum heating and cooling rates for thermal processing of silicon semiconductor wafers in single and multiple wafer furnaces. The program runs interactively on Macintosh, PC, and workstation computers. Execution time is typically 20 seconds on a Macintosh 68040 processor operating at 33 MHz. Gravitational stresses and displacements are first calculated based on the user''s input of a support system consisting of a ring beneath the wafermoreand/or arbitrarily placed point supports. The maximum operating temperature is then deduced by comparing the calculated gravitational stresses with the temperature-dependent wafer strength. At lower temperatures, the difference between wafer strength and gravitational stress is used to determine the allowable thermal stress, and hence the allowable radial temperature difference across the wafer. Finally, an analytical model of radial heat transfer in a batch furnace yields the maximum heating or cooling rate as a function of the allowable temperature difference based on the user''s inputs of wafer spacing and furnace power. Outputs to the screen include plots of stress components and vertical displacement, as well as tables of maximum stresses and maximum heating and cooling rates as a function of temperature. All inputs and outputs may be directed to user-named files for further processing or graphical display.less

  19. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

    PubMed

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-01-01

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180??m) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping. PMID:24820403

  20. A fast in situ approach to estimating wafer warpage profile during thermal processing in microlithography

    NASA Astrophysics Data System (ADS)

    Hu, Ni; Tay, Arthur; Tsai, Kuen-Yu

    2006-08-01

    Wafer warpage can affect device performance, reliability and linewidth control in various processing steps in microelectronics manufacturing. Early detection will minimize cost and processing time. We have previously demonstrated an on-line approach for detecting wafer warpage and the profile of the warped wafer. The proposed approach demonstrates that the profile of the wafer can be computed during thermal processing steps in the lithography sequence. However, the approach is computationally intensive and information is made available at the end of the thermal processing step. Any attempts at real-time correction of the wafer temperature are thus not possible. In this paper, we proposed an in situ approach to detect wafer warpage and its profile midway through the thermal process. Based on first principles thermal modelling, we are able to detect and estimate the profile of a warped wafer from available temperature measurements. The proposed approach can be implemented on conventional thermal processing systems. Experimental results demonstrate the feasibility and repeatability of the approach. A 75% improvement in computational time is achieved with the proposed approach.

  1. Design of Single-Wafer Furnace and Its Rapid Thermal Processing Applications

    NASA Astrophysics Data System (ADS)

    Yoo, Woo Sik; Fukada, Takashi; Kuribayashi, Hiromitsu; Kitayama, Hirofumi; Takahashi, Nobuaki; Enjoji, Keiichi; Sunohara, Kiyoshi

    2000-11-01

    A resistively heated, vacuum- and atmospheric-pressure-compatible, single-wafer furnace (SWF) system is designed to improve the operational flexibility of conventional furnaces and the productivity of single-wafer rapid thermal processing (RTP) systems. The heat source design and system operation concepts are described. The temperature measurement/control techniques and thermal characteristics of the heat source are described. The heat transfer mechanism between the heat source and Si wafer is discussed. Temperature and process uniformity in SWF were demonstrated in TiSi formation, implant annealing and thin-oxide formation. The defect-generation phenomenon in Si wafers during atmospheric pressure RTP in a SWF system is investigated as a function of temperature, process time, wafer handling method and speed. Highly repeatable slip-free RTP results were achieved in 200-mm-diameter Si wafers processed at 1100°C for 60 s (up to 5 times) through the optimization of the wafer handling method and speed.

  2. Across-wafer CD uniformity control through lithography and etch process: experimental verification

    NASA Astrophysics Data System (ADS)

    Zhang, Qiaolin; Tang, Cherry; Cain, Jason; Hui, Angela; Hsieh, Tony; Maccrae, Nick; Singh, Bhanwar; Poolla, Kameshwar; Spanos, Costas J.

    2007-03-01

    Process variation on lot-to-lot and wafer-to-wafer level has been well addressed using R2R control in advanced process control, however, to tackle the ever increasing die-to-die (i.e. across-wafer) level process variation at the 65nm technology node and beyond, the process control must be extended into finer domain: across-wafer level. A novel model based process control approach [2] was proposed to reduce the critical dimension (CD) variation on across-wafer level. The central idea of the proposed approach is to compensate for upstream and downstream systematic CD variation by adjusting the across-wafer Post-Exposure Bake (PEB) temperature profile of a multi-zone bake plate. A temperature-to-offset model relating the PEB temperature profile of multi-zone bake plate to its heater zone offsets was constructed experimentally using wireless temperature sensors from OnWafer Technologies. The baseline post-etch CD signature and plasma etch bias signature were extracted to characterize the lithography and etch processes. And a post-etch CD variation reduction of 40% was realized in the verification experiment, which validated the efficacy of the proposed approach.

  3. Passive compliant wafer stage for single-step nano-imprint lithography

    NASA Astrophysics Data System (ADS)

    Choi, Kee-Bong; Lee, Jae Jong

    2005-07-01

    Nano-imprint lithography, which has the advantages of simplicity, low cost, high replication fidelity and relatively high throughput, requires surface contact between a template with nano patterns and a wafer that transfers the patterns. This article presents the wafer stage for single-step nano-imprint lithography. The wafer stage has a six degree-of-freedom compliant mechanism for complete contact between the surface of the template and the surface of the wafer. The compliant mechanism consists of an inner mechanism for in-plane motion and an outer mechanism for out-of-plane motion. The inner and outer mechanisms have symmetric flexures, which were machined monolithically, onto each plane to cope with thermal deformation. The wafer stage, which was designed to satisfy stiffness requirements, is analyzed with the aid of a dynamic model for a flexure mechanism and a finite element method. Experiments were conducted on the wafer stage in a nano-imprint machine, and nano patterns with linewidths of 100 and 86nm were transferred successfully. This result verifies that the proposed wafer stage can be used in nano-imprint lithography.

  4. Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010

    SciTech Connect

    Lorenz, A.

    2011-06-01

    1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

  5. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss

    NASA Astrophysics Data System (ADS)

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-05-01

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 ?m) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

  6. Validation of thermodesorption method for analysis of semi-volatile organic compounds adsorbed on wafer surface.

    PubMed

    Hayeck, Nathalie; Gligorovski, Sasho; Poulet, Irène; Wortham, Henri

    2014-05-01

    To prevent the degradation of the device characteristics it is important to detect the organic contaminants adsorbed on the wafers. In this respect, a reliable qualitative and quantitative analytical method for analysis of semi-volatile organic compounds which can adsorb on wafer surfaces is of paramount importance. Here, we present a new analytical method based on Wafer Outgassing System (WOS) coupled to Automated Thermal Desorber-Gas chromatography-Mass spectrometry (ATD-GC-MS) to identify and quantify volatile and semi-volatile organic compounds from 6", 8" and 12" wafers. WOS technique allows the desorption of organic compounds from one side of the wafers. This method was tested on three important airborne contaminants in cleanroom i.e. tris-(2-chloroethyl) phosphate (TCEP), tris-(2-chloroisopropyl) phosphate (TCPP) and diethyl phthalate (DEP). In addition, we validated this method for the analysis and quantification of DEP, TCEP and TCPP and we estimated the backside organic contamination which may contribute to the front side of the contaminated wafers. We are demonstrating that WOS/ATD-GC-MS is a suitable and highly efficient technique for desorption and quantitative analysis of organophosphorous compounds and phthalate ester which could be found on the wafer surface. PMID:24720963

  7. Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

    NASA Technical Reports Server (NTRS)

    Okojie, Robert S. (Inventor)

    2002-01-01

    A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

  8. Therml & Gravitational Stress in Si Wafers; Lim. on Process Htg & Cool. Rates

    Energy Science and Technology Software Center (ESTSC)

    1997-01-14

    The MacWafer code determines maximum allowable processing temperatures and maximum heating and cooling rates for thermal processing of silicon semiconductor wafers in single and multiple wafer furnaces. The program runs interactively on Macintosh, PC, and workstation computers. Execution time is typically 20 seconds on a Macintosh 68040 processor operating at 33 MHz. Gravitational stresses and displacements are first calculated based on the user''s input of a support system consisting of a ring beneath the wafermore » and/or arbitrarily placed point supports. The maximum operating temperature is then deduced by comparing the calculated gravitational stresses with the temperature-dependent wafer strength. At lower temperatures, the difference between wafer strength and gravitational stress is used to determine the allowable thermal stress, and hence the allowable radial temperature difference across the wafer. Finally, an analytical model of radial heat transfer in a batch furnace yields the maximum heating or cooling rate as a function of the allowable temperature difference based on the user''s inputs of wafer spacing and furnace power. Outputs to the screen include plots of stress components and vertical displacement, as well as tables of maximum stresses and maximum heating and cooling rates as a function of temperature. All inputs and outputs may be directed to user-named files for further processing or graphical display.« less

  9. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss

    PubMed Central

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-01-01

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180??m) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping. PMID:24820403

  10. AWV: high-throughput cross-array cross-wafer variation mapping

    NASA Astrophysics Data System (ADS)

    Yeo, Jeong-Ho; Lee, Byoung-Ho; Lee, Tae-Yong; Greenberg, Gadi; Meshulach, Doron; Ravid, Erez; Levi, Shimon; Kan, Kobi; Shabtay, Saar; Cohen, Yehuda; Rotlevi, Ofer

    2008-03-01

    Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision (TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

  11. Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers Used for PV Cells: Preprint

    SciTech Connect

    Guthrey, H.; Gorman, B.; Al-Jassim, M.

    2011-07-01

    As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay (uPCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

  12. Microlenticular lens replication by the combination of gas-assisted imprint technology and LIGA-like process

    NASA Astrophysics Data System (ADS)

    Yeh, Chia-Hung; Shih, Ching-Jui; Wang, Hsuan-Cheng; Chang, Fuh-Yu; Young, Hong-Tsu; Chang, Wen-Chuan

    2012-09-01

    A mold used in creating diffractive optical elements significantly affects the quality of these devices. In this study, we improved traditional microlens fabrication processes, which have shortcomings, mainly by combining gas-assisted imprint technology and the lithographie galvanoformung abformung (LIGA)-like process. This combination resulted in the production of high-quality optical components with high replication rates, high uniformity, large areas and high flexibility. Given the pixel size of the panel used, the optimal viewing distance, the film thickness and the glass thickness in the formula, we could determine the radius of curvature and the thickness of the lens. By the use of U-groove machining, precise electroforming and embossing to produce polydimethylsiloxane (PDMS) molds, lens film elements can be produced via an ultraviolet (UV)-cured molding process that converts microlenses into flexible polyethylene terephthalate films. In this study, the microlenticular lens mold is fabricated by U-groove machining, Ni electroforming and PDMS casting. Then, the PDMS mold with microlenticular lens structure is used in the gas-assisted UV imprint process and the PET film with microlenticular lens array is obtained. The lenticular lens had a radius of curvature and height of 228 and 18 µm, respectively. A 3D confocal laser microscope was used to measure the radius of curvature and the spacing of the metal molds, nickel (Ni) molds, PDMS molds and the finished thin-film products. The geometry of the final microlenticular lens was very close to the design values. All geometric errors were below 5%, the surface roughness reached the optical level (with all Ra values less than 10 nm) and the replication rate was 95%. The results demonstrate that this process can be used to fabricate gapless, lenticular-shaped, high-precision microlens arrays with a unitary curvature.

  13. Kinetic mechanism and fidelity of nick sealing by Escherichia coli NAD+-dependent DNA ligase (LigA).

    PubMed

    Chauleau, Mathieu; Shuman, Stewart

    2016-03-18

    Escherichia coli DNA ligase (EcoLigA) repairs 3'-OH/5'-PO4 nicks in duplex DNA via reaction of LigA with NAD(+) to form a covalent LigA-(lysyl-Nζ)-AMP intermediate (step 1); transfer of AMP to the nick 5'-PO4 to form an AppDNA intermediate (step 2); and attack of the nick 3'-OH on AppDNA to form a 3'-5' phosphodiester (step 3). A distinctive feature of EcoLigA is its stimulation by ammonium ion. Here we used rapid mix-quench methods to analyze the kinetic mechanism of single-turnover nick sealing by EcoLigA-AMP. For substrates with correctly base-paired 3'-OH/5'-PO4 nicks, kstep2 was fast (6.8-27 s(-1)) and similar to kstep3 (8.3-42 s(-1)). Absent ammonium, kstep2 and kstep3 were 48-fold and 16-fold slower, respectively. EcoLigA was exquisitely sensitive to 3'-OH base mispairs and 3' N:abasic lesions, which elicited 1000- to >20000-fold decrements in kstep2. The exception was the non-canonical 3' A:oxoG configuration, which EcoLigA accepted as correctly paired for rapid sealing. These results underscore: (i) how EcoLigA requires proper positioning of the nick 3' nucleoside for catalysis of 5' adenylylation; and (ii) EcoLigA's potential to embed mutations during the repair of oxidative damage. EcoLigA was relatively tolerant of 5'-phosphate base mispairs and 5' N:abasic lesions. PMID:26857547

  14. Kinetic mechanism and fidelity of nick sealing by Escherichia coli NAD+-dependent DNA ligase (LigA)

    PubMed Central

    Chauleau, Mathieu; Shuman, Stewart

    2016-01-01

    Escherichia coli DNA ligase (EcoLigA) repairs 3′-OH/5′-PO4 nicks in duplex DNA via reaction of LigA with NAD+ to form a covalent LigA-(lysyl-Nζ)–AMP intermediate (step 1); transfer of AMP to the nick 5′-PO4 to form an AppDNA intermediate (step 2); and attack of the nick 3′-OH on AppDNA to form a 3′-5′ phosphodiester (step 3). A distinctive feature of EcoLigA is its stimulation by ammonium ion. Here we used rapid mix-quench methods to analyze the kinetic mechanism of single-turnover nick sealing by EcoLigA–AMP. For substrates with correctly base-paired 3′-OH/5′-PO4 nicks, kstep2 was fast (6.8–27 s−1) and similar to kstep3 (8.3–42 s−1). Absent ammonium, kstep2 and kstep3 were 48-fold and 16-fold slower, respectively. EcoLigA was exquisitely sensitive to 3′-OH base mispairs and 3′ N:abasic lesions, which elicited 1000- to >20000-fold decrements in kstep2. The exception was the non-canonical 3′ A:oxoG configuration, which EcoLigA accepted as correctly paired for rapid sealing. These results underscore: (i) how EcoLigA requires proper positioning of the nick 3′ nucleoside for catalysis of 5′ adenylylation; and (ii) EcoLigA's potential to embed mutations during the repair of oxidative damage. EcoLigA was relatively tolerant of 5′-phosphate base mispairs and 5′ N:abasic lesions. PMID:26857547

  15. CDU improvement with wafer warpage control oven for high-volume manufacturing

    NASA Astrophysics Data System (ADS)

    Tomita, T.; Weichert, H.; Hornig, S.; Trepte, S.; Shite, H.; Uemura, R.; Kitano, J.

    2009-03-01

    Immersion lithography has been developed for 45nm technology node generation during the last several years. Currently, IC manufacturers are moving to high volume production using immersion lithography. Due to the demand of IC manufactures, as the critical dimension (CD) target size is shrinking, there are more stringent requirements for CD control. Post Exposure Bake (PEB) process, which is the polymer de-protection process after exposure, is one of the important processes to control the CD in the 193nm immersion lithography cluster. Because of the importance of the PEB process for CD uniformity, accurate temperature control is a high priority. Tokyo Electron LTD (TEL) has been studying the temperature control of PEB plates. From our investigation, total thermal history during the PEB process is a key point for controlling intra wafer and inter wafer CD [1]. Further, production wafers are usually warped, which leads to a nonuniform thermal energy distribution during the PEB process. So, it is necessary to correct wafer warpage during the baking process in order to achieve accurate CD control on production wafers. TEL has developed a new PEB plate for 45nm technology node mass production, which is able to correct wafer warpage. The new PEB plate succeeded in controlling the wafer temperature on production wafers using its warpage control function. In this work, we evaluated CD process capability using the wafer warpage control PEB plate, which is mounted on a CLEAN TRACKTM LITHIUS ProTM-i (TEL) linked with the latest immersion exposure tool. The evaluation was performed together with an IC manufacturer on their 45nm production substrates in order to determine the true performance in production.

  16. Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

    NASA Astrophysics Data System (ADS)

    Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

    2015-02-01

    The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

  17. W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

    NASA Technical Reports Server (NTRS)

    Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

    1997-01-01

    Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

  18. A 2-in. mosaic wafer made of a single-crystal diamond

    NASA Astrophysics Data System (ADS)

    Yamada, H.; Chayahara, A.; Mokuno, Y.; Kato, Y.; Shikata, S.

    2014-03-01

    We synthesized a mosaic diamond wafer 2 in. in size (40 60 mm2), which consisted of 24 single-crystal diamond (SCD) plates 10 10 mm2 in area, by using microwave plasma chemical vapor deposition. Even by using a cloning technique, cracking frequently occurred and the non-uniformity was remarkable for wafers that were larger than 1 in. in size. This has not been observed in smaller samples before. Appropriate crystallographic directions could avoid the cracking and is one of the predominant factors in fabricating large area SCD wafers. Comparison with numerical simulations highlighted the importance of uniformity of the substrate temperature distribution on the uniformity of the growth.

  19. Charge-Noise-Free Lateral Quantum Dot Devices with Undoped Si/SiGe Wafer

    NASA Astrophysics Data System (ADS)

    Obata, T.; Takeda, K.; Kamioka, J.; Kodera, T.; Akhtar, W. M.; Sawano, K.; Oda, S.; Shiraki, Y.; Tarucha, S.

    We develop quantum dots in a single layered MOS structure using an undoped Si/SiGe wafer. By applying a positive bias on the surface gates, electrons are accumulated in the Si channel. Clear Coulomb diamond and double dot charge stability diagrams are measured. The temporal fluctuation of the current is traced, to which we apply the Fourier transform analysis. The power spectrum of the noise signal is inversely proportional to the frequency, and is different from the inversely quadratic behavior known for quantum dots made in doped wafers. Our results indicate that the source of charge noise for the doped wafers is related to the 2DEG dopant.

  20. Wafer chamber having a gas curtain for extreme-UV lithography

    DOEpatents

    Kanouff, Michael P.; Ray-Chaudhuri, Avijit K.

    2001-01-01

    An EUVL device includes a wafer chamber that is separated from the upstream optics by a barrier having an aperture that is permeable to the inert gas. Maintaining an inert gas curtain in the proximity of a wafer positioned in a chamber of an extreme ultraviolet lithography device can effectively prevent contaminants from reaching the optics in an extreme ultraviolet photolithography device even though solid window filters are not employed between the source of reflected radiation, e.g., the camera, and the wafer. The inert gas removes the contaminants by entrainment.

  1. Development of a fixed abrasive slicing technique (FAST) for reducing the cost of photovoltaic wafers

    SciTech Connect

    Schmid, F. )

    1991-12-01

    This report examines a wafer slicing technique developed by Crystal Systems, Inc. that reduces the cost of photovoltaic wafers. This fixed, abrasive slicing technique (FAST) uses a multiwire bladepack and a diamond-plated wirepack; water is the coolant. FAST is in the prototype production stage and reduces expendable material costs while retaining the advantages of a multiwire slurry technique. The cost analysis revealed that costs can be decreased by making more cuts per bladepack and slicing more wafers per linear inch. Researchers studied the degradation of bladepacks and increased wirepack life. 21 refs.

  2. Correlation of 150-mm silicon wafer site flatness with stepper performance for deep submicron applications

    NASA Astrophysics Data System (ADS)

    Huff, Howard R.; Vigil, Joseph C.; Kuyel, Birol; Chan, David Y.; Nguyen, Long P.

    1992-06-01

    An experimental study was conducted to correlate wafer site flatness SFQD with stepper performance for half-micron lines and spaces. CD measurements were taken on wafers patterned on both GCA pre-production XLS i-line and SVGL Micrascan-90 DUV steppers as well as focus measurements on the Micrascan-90. Wafer site flatness SFQD less than 0.3 micrometers was observed to be a sufficiently small variable in CD non-uniformities for these initial half-micron stepper applications.

  3. The removal of deformed submicron particles from silicon wafers by spin rinse and megasonics

    NASA Astrophysics Data System (ADS)

    Zhang, Fan; Busnaina, Ahmed A.; Fury, Michael A.; Wang, Shi-Qing

    2000-02-01

    In order to successfully clean particulate contamination from wafer surfaces, it is necessary to understand the adhesion and deformation between the particles and the substrate in contact. The adhesion and removal mechanisms of deformed submicron particles have not been addressed in many previous studies. Submicron polystyrene latex particles (0.1-0.5 µm) were deposited on silicon wafers and removed by spin rinse and megasonic cleanings. Particle rolling is identified as the major removal mechanism for the deformed submicron particles from silicon wafers. Megasonics provides larger streaming velocity because of the extremely thin boundary layer resulting in a larger removal force that is capable of achieving complete removal of contamination particles.

  4. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sang Min; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Vukkadala, Pradeep; Awasthi, Amartya; Kim, J. H.; Veeraraghavan, Sathish; Choi, DongSub; Huang, Kevin; Dighe, Prasanna; Lee, Cheouljung; Byeon, Jungho; Dey, Soham; Sinha, Jaydeep

    2015-03-01

    Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes - which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.

  5. OPC hotspot identification challenges: ORC vs. PWQ on wafer

    NASA Astrophysics Data System (ADS)

    Poock, Andre; McGowan, Sarah; Weisbuch, Francois; Schnasse, Guido; Ghaskadvi, Rajesh

    2008-10-01

    The identification of OPC induced litho hotspots within the product design is essential and a must to make sure that a new OPC model is working correctly and does no harm to the design and future product. Several techniques and methods for OPC verification and identification of hotspots are known and long adopted within the field. An optical rule check done by the simulation software after OPC is one way of identifying hotspots within the design of the whole chip. This is typically done by using a DRC-type width or space check on simulation contours (nominal exposure contour or process window contours). However, the pass/fail nature of this check at a single CD value requires good calibration of the simulation model to avoid false positives and ease of disposition at tapeout. Another method is the process window qualification method which uses the defect inspection of a focus exposure matrix wafer for OPC hotspot identification. However, this can not be done prior to ordering a mask. Based on a 45nm line space layer OPC qualification, we will demonstrate how optical rule check and process window qualification is performed, what the individual results will be, and how they can be used for OPC quality evaluation. The general goal of this work is to show the capabilities of optical rule check and process window qualification, compare both methods, and detect limitations.

  6. A metallic buried interconnect process for through-wafer interconnection

    NASA Astrophysics Data System (ADS)

    Ji, Chang-Hyeon; Herrault, Florian; Allen, Mark G.

    2008-08-01

    In this paper, we present the design, fabrication process and experimental results of electroplated metal interconnects buried at the bottom of deep silicon trenches with vertical sidewalls. A manual spray-coating process along with a unique trench-formation process has been developed for the electroplating of a metal interconnection structure at the bottom surface of the deep trenches. The silicon etch process combines the isotropic dry etch process and conventional Bosch process to fabricate a deep trench with angled top-side edges and vertical sidewalls. The resulting trench structure, in contrast to the trenches fabricated by wet anisotropic etching, enables spray-coated photoresist patterning with good sidewall and top-side edge coverage while maintaining the ability to form a high-density array of deep trenches without excessive widening of the trench opening. A photoresist spray-coating process was developed and optimized for the formation of electroplating mold at the bottom of 300 m deep trenches having vertical sidewalls. A diluted positive tone photoresist with relatively high solid content and multiple coating with baking between coating steps has been experimentally proven to provide high quality sidewall and edge coverage. To validate the buried interconnect approach, a three-dimensional daisy chain structure having a buried interconnect as the bottom connector and traces on the wafer surface as the top conductor has been designed and fabricated.

  7. Shop-floor scheduling of semiconductor-wafer manufacturing

    SciTech Connect

    Resende, M.G.D.C.

    1987-01-01

    Semiconductor wafer fabrication is perhaps the most complex manufacturing process found today, with a wide range of complex issues related to production planning and scheduling. Computer-integrated manufacturing (CIM) systems make is possible, in theory, to use global factory state information for factory control decisions. The possibility of making decisions on an expanded information set raises two of the research questions treated in this dissertation: How should global information be summarized and used for decisions and how much improvement can one expect as a result, compared with decisions based on local information This research investigates lot release control and dispatching policies for shop-level scheduling of a semiconductor fab. The author introduces a closed-loop scheduling policy, called Starvation Avoidance, that makes use of global factory state information and that in simulation experiments compares favorably to traditional scheduling policies (that use local and global information) with respect to the tradeoff between throughput and queueing time. The virtual inventory of the bottleneck resource is defined to be the work content at the bottleneck of all jobs either at the bottleneck station or expected to arrive at the bottleneck within a given lead time.

  8. Evolution of grain structures during directional solidification of silicon wafers

    NASA Astrophysics Data System (ADS)

    Lin, H. K.; Wu, M. C.; Chen, C. C.; Lan, C. W.

    2016-04-01

    The evolution of grain structures, especially the types of grain boundaries (GBs), during directional solidification is crucial to the electrical properties of multicrystalline silicon used for solar cells. To study this, the electric molten zone crystallization (EMZC) of silicon wafers at different drift speeds from 2 to 6 mm/min was considered. It was found that <111> orientation was dominant at the lower drift velocity, while <112> orientation at the higher drift velocity. Most of the non-∑GBs tended to align with the thermal gradient, but some tilted toward the unfavorable grains having higher interfacial energies. On the other hand, the tilted ∑3GBs tended to decrease during grain competition, except at the higher speed, where the twin nucleation became frequent. The competition of grains separated by ∑GBs could be viewed as the interactions of GBs that two coherent ∑3n GBs turned into one ∑3nGB following certain relations as reported before. On the other hand, when ∑ GBs met non-∑ GBs, the non-∑ GBs remained which explained the decrease of ∑ GBs at the lower speed.

  9. Adhesive disbond detection using piezoelectric wafer active sensors

    NASA Astrophysics Data System (ADS)

    Roth, William; Giurgiutiu, Victor

    2015-04-01

    The aerospace industry continues to increase the use of adhesives for structural bonding due to the increased joint efficiency (reduced weight), even distribution of the load path and decreases in stress concentrations. However, the limited techniques for verifying the strength of adhesive bonds has reduced its use on primary structures and requires an intensive inspection schedule. This paper discusses a potential structural health monitoring (SHM) technique for the detection of disbonds through the in situ inspection of adhesive joints. This is achieved through the use of piezoelectric wafer active sensors (PWAS), thin unobtrusive sensors which are permanently bonded to the aircraft structure. The detection method discussed in this study is electromechanical impedance spectroscopy (EMIS), a local vibration method. This method detects disbonds from the change in the mechanical impedance of the structure surrounding the disbond. This paper will discuss how predictive modeling can provide valuable insight into the inspection method, and provide better results than empirical methods alone. The inspection scheme was evaluated using the finite element method, and the results were verified experimentally using a large aluminum test article, and included both pristine and disbond coupons.

  10. Fast wafer-level detection and control of interconnect reliability

    NASA Astrophysics Data System (ADS)

    Foley, Sean; Molyneaux, James; Mathewson, Alan

    2000-08-01

    Many of the technological advances in the semiconductor industry have led to dramatic increases in device density and performance in conjunction with enhanced circuit reliability. As reliability is improved, the time taken to characterize particular failure modes with traditional test methods is getting substantially longer. Furthermore, semiconductor customers expect low product cost and fast time-to-market. The limits of traditional reliability testing philosophies are being reached and new approaches need to be investigated to enable the next generation of highly reliable products to be tested. This is especially true in the area of IC interconnect, where significant challenges are predicted for the next decade. A number of fast, wafer level test methods exist for interconnect reliability evaluation. The relative abilities of four such methods to detect the quality and reliability of IC interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are bench-marked against conventional package level Median Time to Failure results. The Isothermal test method combine with SWEAT-type test structures is shown to be the most suitable combination for defect detection and interconnect reliability control over very short test times.

  11. Defect Characterization of 4H-SiC Wafers for Power Electronic Device Applications.

    NASA Astrophysics Data System (ADS)

    Cicero, G.; Ferrero, S.; Cocuzza, M.; Giorgis, F.; Mandracci, P.; Ricciardi, C.; Scaltrito, L.; Pirri, C. F.; Richieri, G.; Sgorlon, C.

    2002-03-01

    Silicon carbide is a wide band gap semiconductor, interesting for its physical properties such as high breakdown field, high saturated drift velocity and high thermal conductivity, which has been intensively studied in the last years. Although the high potentiality of this material, the SiC technology shows at the moment some limitations and requires further study in order to obtain electronic devices with the same quality standards of the Si technology. Indeed, the reliability of SiC-based devices is strictly correlated to the defects present in the crystalline structure. We have focused our investigation on 4H-SiC wafers and on 4H epitaxial layers in order to determine in both the situations the different type of defects. A preliminary investigation has been performed by optical microscopy and Scanning Electron Microscopy with the aim to evidence the defect morphology on large scale. A deeper insight on the defects typology has been obtained by Atomic Force Microscopy, Profilometer technique, Micro-Raman and Micro-Photoluminescence spectroscopies. Different types of defects such as micropipes, comets, super dislocations, etch pits and so on, have been characterized finding particular physical finger-prints. This investigation is aimed at correlating the defects and the electrical properties of SiC for power electronic device applications.

  12. Hydrogen-induced program threshold voltage degradation analysis in SONOS wafer

    NASA Astrophysics Data System (ADS)

    Lin, Qing; Zhao, Crystal; Sheng, Nan

    2016-02-01

    This paper studies the hydrogen-induced program state threshold voltage degradation in SONOS wafers, which ultimately impacts wafer sort test yield. During wafer sort step, all individual integrated circuits noted as die are tested for functional defects by applying special test patterns to them. The proportion between the passing die (good die) and the non-passing die (bad die) is sort yield. The different N2/H2 ratio in IMD1 alloy process yields differently at flash checkerboard test. And the SIMS curves were also obtained to depict the distribution profile of H+ in SONOS ONO stack structure. It is found that, the H+ accumulated in the interface between the Tunnel oxide and Si layer, contributes the charge loss in Oxynitride layer, which leads to the program threshold voltage degradation and even fall below lower specification limit, and then impacts the sort yield of SONOS wafers.

  13. Plastically deformed Ge-crystal wafers as elements for neutron focusing monochromator

    NASA Astrophysics Data System (ADS)

    Hiraka, H.; Ohkubo, K.; Furusaka, M.; Kiyanagi, Y.; Yamada, K.; Morishita, K.; Nakajima, K.

    2012-11-01

    Plastically deformed Ge-crystal wafers that have the cylindrical shape with a large curvature were characterized by neutron diffraction. The box-type rocking curve of Bragg reflection with the angular width of ?box?2 in FWHM, which is observable in the monochromatic neutron diffraction, results in an enhancement in the angle-integrated intensity (I?). Besides, I? efficiently increases by stacking such Ge wafers. In the course of white neutron diffraction, the reflected-beam width near the focus point becomes sharper than the initial beam width. Further, the dependence of the horizontal beam width on the distance between the sample and detector is quantitatively explained by taking account of the large ?box, the small mosaic spread of ??0.1, and the thickness of the wafers. On the basis of these characterizations, use of plastically deformed Ge wafers as elements for high-luminance neutron monochromator is proposed.

  14. Diffusion length and resistivity distribution characteristics of silicon wafer by photoluminescence

    SciTech Connect

    Baek, Dohyun; Lee, Jaehyeong; Choi, Byoungdeog

    2014-10-15

    Highlights: Analytical photoluminescence efficiency calculation and PL intensity ratio method are developed. Wafer resistivity and diffusion length characteristics are investigated by PL intensity ratio. PL intensity is well correlated with resistivity, diffusion length or defect density on wafer measurement. - Abstract: Photoluminescence is a convenient, contactless method to characterize semiconductors. Its use for room-temperature silicon characterization has only recently been implemented. We have developed the PL efficiency theory as a function of substrate doping densities, bulk trap density, photon flux density, and reflectance and compared it with experimental data initially for bulk Si wafers. New developed PL intensity ratio method is able to predict the silicon wafer properties, such as doping densities, minority carrier diffusion length and bulk trap density.

  15. Nanoetching process on silicon solar cell wafers during mass production for surface texture improvement.

    PubMed

    Ahn, Chisung; Kulkarni, Atul; Ha, Soohyun; Cho, Yujin; Kim, Jeongin; Park, Heejin; Kim, Taesung

    2014-12-01

    Major challenge in nanotechnology is to improve the solar cells efficiency. This can be achieved by controlling the silicon solar cell wafer surface structure. Herein, we report a KOH wet etching process along with an ultrasonic cleaning process to improve the surface texture of silicon solar cell wafers. We evaluated the KOH temperature, concentration, and ultra-sonication time. It was observed that the surface texture of the silicon solar wafer changed from a pyramid shape to a rectangular shape under edge cutting as the concentration of the KOH solution was increased. We controlled the etching time to avoid pattern damage and any further increase of the reflectance. The present study will be helpful for the mass processing of silicon solar cell wafers with improved reflectance. PMID:25971104

  16. Trans-wafer removal of metallization using a nanosecond Tm:fiber laser

    NASA Astrophysics Data System (ADS)

    Mingareev, Ilya; Berger, Sascha; Tetz, Thomas; Abdulfattah, Ali; Sincore, Alex M.; Shah, Lawrence; Richardson, Martin C.

    2015-03-01

    By utilizing photon energies considerably smaller than the semiconductors' energy band gap, space-selective modifications can be induced in semiconductors beyond the laser-incident surface. Previously, we demonstrated that back surface modifications could be produced in 500-600 ?m thin Si and GaAs wafers independently without affecting the front surface. In this paper, we present our latest studies on trans-wafer processing of semiconductors using a self-developed nanosecond-pulsed thulium fiber laser operating at the wavelength 2 ?m. A qualitative study of underlying physical mechanisms responsible for material modification was performed. We explored experimental conditions that will enable many potential applications such as trans-wafer metallization removal for PV cell edge isolation, selective surface annealing and wafer scribing. These processes were investigated by studying the influence of process parameters on the resulting surface morphology, microstructure and electric properties.

  17. Photocatalytic water disinfection by simple and low-cost monolithic and heterojunction ceramic wafers.

    PubMed

    Makwana, Neel M; Hazael, Rachael; McMillan, Paul F; Darr, Jawwad A

    2015-06-01

    In this work, the photocatalytic disinfection of Escherichia coli (E. coli) using dual layer ceramic wafers, prepared by a simple and low-cost technique, was investigated. Heterojunction wafers were prepared by pressing TiO2 and WO3 powders together into 2 layers within a single, self-supported monolith. Data modelling showed that the heterojunction wafers were able to sustain the formation of charged species (after an initial "charging" period). In comparison, a wafer made from pure TiO2 showed a less desirable bacterial inactivation profile in that the rate decreased with time (after being faster initially). The more favourable kinetics of the dual layer system was due to superior electron-hole vectorial charge separation and an accumulation of charges beyond the initial illumination period. The results demonstrate the potential for developing simplified photocatalytic devices for rapid water disinfection. PMID:25976167

  18. {ital In} {ital situ} wafer temperature monitoring of silicon etching using diffuse reflectance spectroscopy

    SciTech Connect

    Booth, J.L.; Beard, B.T.; Stevens, J.E.; Blain, M.G.; Meisenheimer, T.L.

    1996-07-01

    Real time, {ital in} {ital situ} temperature measurements during chemical downstream etching of silicon wafers have been performed using a diffuse reflectance spectroscopy based sensor [Weilmeier {ital et} {ital al}., Can. J. Phys. {bold 69}, 422 (1991)]. The spectrometer has a spatial resolution of 1 cm{sup 2}, updates the temperature every 2 s, and has a temperature resolution of better than 1{degree}C. The thermal time constant the wafers and the thermally regulated electrostatic chuck (10{degree}C{lt}{ital T}{lt}90{degree}C) varied between 7 and 30 s depending on clamping and backside gas pressure. The exothermic etch process is accompanied by increases in the silicon wafer temperature consistent with the thermal conductivity conditions and with the etch chemistry. The temperature uniformity across the wafers was better than 2{degree}C during the entire etch process. {copyright} {ital 1996 American Vacuum Society}

  19. Eutectic bonding of a Ti sputter coated, carbon aerogel wafer to a Ni foil

    SciTech Connect

    Jankowski, A.F.; Hayes, J.P.; Kanna, R.L.

    1994-06-01

    The formation of high energy density, storage devices is achievable using composite material systems. Alternate layering of carbon aerogel wafers and Ni foils with rnicroporous separators is a prospective composite for capacitor applications. An inherent problem exists to form a physical bond between Ni and the porous carbon wafer. The bonding process must be limited to temperatures less than 1000{degrees}C, at which point the aerogel begins to degrade. The advantage of a low temperature eutectic in the Ni-Ti alloy system solves this problem. Ti, a carbide former, is readily adherent as a sputter deposited thin film onto the carbon wafer. A vacuum bonding process is then used to join the Ni foil and Ti coating through eutectic phase formation. The parameters required for successfld bonding are described along with a structural characterization of the Ni foil-carbon aerogel wafer interface.

  20. Characterization and control of wafer charging effects during high-current ion implantation

    SciTech Connect

    Current, M.I.; Lukaszek, W.; Dixon, W.; Vella, M.C.; Messick, C.; Shideler, J.; Reno, S.

    1994-02-01

    EEPROM-based sense and memory devices provide direct measures of the charge flow and potentials occurring on the surface of wafers during ion beam processing. Sensor design and applications for high current ion implantation are discussed.