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1

A wafer-scale 3-D circuit integration technology  

Microsoft Academic Search

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances.

James A. Burns; Brian F. Aull; Chenson K. Chen; Chang-Lee Chen; Craig L. Keast; Jeffrey M. Knecht; V. Suntharalingam; K. Warner; P. W. Wyatt; D.-R. W. Yost

2006-01-01

2

Wafer-scale charge isolation technique  

SciTech Connect

An apparatus and method are described which improve the performance of charge-coupled devices (CCD) in the presence of ionizing radiation. The invention is a wafer scale charge isolation technique which inhibits or reduces the flow of electrons created by the passage of ionizing radiation in the bulk regions of a silicon CCD. The technique has been tested in a device designed for operating in the infra-red wavelength band. The technique prevents charge from reaching the active charge collection volume of a pixel in a CCD.

Colella, N.J.; Kimbrough, J.R.

1994-12-31

3

Parallel Assembly of LIGA Components  

SciTech Connect

In this paper, a prototype robotic workcell for the parallel assembly of LIGA components is described. A Cartesian robot is used to press 386 and 485 micron diameter pins into a LIGA substrate and then place a 3-inch diameter wafer with LIGA gears onto the pins. Upward and downward looking microscopes are used to locate holes in the LIGA substrate, pins to be pressed in the holes, and gears to be placed on the pins. This vision system can locate parts within 3 microns, while the Cartesian manipulator can place the parts within 0.4 microns.

Christenson, T.R.; Feddema, J.T.

1999-03-04

4

Wafer-Scale Microtensile Testing of Thin Films  

Microsoft Academic Search

This paper reports on the mechanical characterization of thin films using the microtensile technique performed for the first time at the wafer scale. Multiple test structures are processed and sequentially measured on the same silicon substrate, thus eliminating delicate handling of individual samples. The current layout uses 26 test structures evenly distributed over a 4-in wafer, each of them carrying

Joo Gaspar; Marek E. Schmidt; Jochen Held; Oliver Paul

2009-01-01

5

Low cost camera modules using integration of wafer-scale optics and wafer-level packaging of image sensors  

NASA Astrophysics Data System (ADS)

Using wafer scale optics, wafer scale integration, and wafer level packaging of image sensor, we developed small form factor (3.3mmx3.3mmx2.5mm), low manufacturing cost, Pb-free solder reflow compatible digital camera modules which are suitable for many applications including mobile electronic devices, automotives, security, and medical applications.

Han, Hongtao; Main, Keith

2009-11-01

6

Wafer Scale Homogeneous Bilayer Graphene Films by Chemical Vapor Deposition  

Microsoft Academic Search

The discovery of electric field induced bandgap opening in bilayer graphene opens new door for making semiconducting graphene without aggressive size scaling or using expensive substrates. However, bilayer graphene samples have been limited to um size scale thus far, and synthesis of wafer scale bilayer graphene posts tremendous challenge. Here we report homogeneous bilayer graphene films over at least 2

Seunghyun Lee; Kyunghoon Lee; Zhaohui Zhong

2010-01-01

7

Wafer-scale aluminum nano-plasmonics  

NASA Astrophysics Data System (ADS)

The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

2014-09-01

8

Wafer Scale Homogeneous Bilayer Graphene Films by Chemical Vapor Deposition  

E-print Network

oxide. (b) Optical microscopy image showing the edge of a bilayer graphene film. (c) AFM imageWafer Scale Homogeneous Bilayer Graphene Films by Chemical Vapor Deposition Seunghyun Lee gap opening in bilayer graphene opens a new door for making semiconducting graphene without aggressive

Zhong, Zhaohui

9

Wafer-scale process for fabricating arrays of nanopore devices  

E-print Network

Wafer-scale process for fabricating arrays of nanopore devices Amir G. Ahmadi Georgia Institute.nair@chbe.gatech.edu Abstract. Nanopore-based single-molecule analysis is a subject of strong scientific and technological chemistry. Previously demonstrated methods have been confined to the production of single nanopore de- vices

Nair, Sankar

10

Liga developer apparatus system  

DOEpatents

A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

Boehme, Dale R. (Pleasanton, CA); Bankert, Michelle A. (San Francisco, CA); Christenson, Todd R. (Albuquerque, NM)

2003-01-01

11

LIGA Micromachining  

NSDL National Science Digital Library

This YouTube video, created by Southwest Center for Microsystems Education (SCME), provides an overview of the LIGA (Lithography, Electroplating, and Molding) technique for micromachining. The lecture runs for 7:25 seconds and describes LIGA as part of micromachining fabrication, including lithography, process, and post-process steps. More information can be found on the SCME website. 

2014-07-31

12

Wafer-scale Reduced Graphene Oxide Films for Nanomechanical Devices  

Microsoft Academic Search

We report a process to form large-area, few-monolayer graphene oxide films and then recover the outstanding mechanical properties found in graphene to fabricate high Young's modulus ( ) 185 GPa), low-density nanomechanical resonators. Wafer-scale films as thin as 4 nm are sufficiently robust that they can be delaminated intact and resuspended on a bed of pillars or field of holes.

Jeremy T. Robinson; Maxim Zalalutdinov; Jeffrey W. Baldwin; Eric S. Snow; Zhongqing Wei; Paul Sheehan; Brian H. Houston

2008-01-01

13

Wafer-scale fabrication of nanoapertures using corner lithography.  

PubMed

Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated--based on a theoretical foundation including a statistical analysis--with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures. PMID:23792365

Burouni, Narges; Berenschot, Erwin; Elwenspoek, Miko; Sarajlic, Edin; Leussink, Pele; Jansen, Henri; Tas, Niels

2013-07-19

14

Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays  

NASA Technical Reports Server (NTRS)

The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

2009-01-01

15

Wafer-scale reduced graphene oxide films for nanomechanical devices.  

PubMed

We report a process to form large-area, few-monolayer graphene oxide films and then recover the outstanding mechanical properties found in graphene to fabricate high Young's modulus ( =185 GPa), low-density nanomechanical resonators. Wafer-scale films as thin as 4 nm are sufficiently robust that they can be delaminated intact and resuspended on a bed of pillars or field of holes. From these films, we demonstrate radio frequency resonators with quality factors (up to 4000) and figures of merit ( f x Q>10(11)) well exceeding those of pure graphene resonators reported to date. These films' ability to withstand high in-plane tension (up to 5 N/m) as well as their high Q-values reveals that film integrity is enhanced by platelet-platelet bonding unavailable in pure graphite. PMID:18781807

Robinson, Jeremy T; Zalalutdinov, Maxim; Baldwin, Jeffrey W; Snow, Eric S; Wei, Zhongqing; Sheehan, Paul; Houston, Brian H

2008-10-01

16

Wafer-scale arrays of epitaxial ferroelectric nanodiscs and nanorings  

NASA Astrophysics Data System (ADS)

Wafer-scale arrays of well-ordered Pb(Zr0.2Ti0.8)O3 nanodiscs and nanorings were fabricated on the entire area (10 mm 10 mm) of the SrRuO3 bottom electrode on an SrTiO3 single-crystal substrate using the laser interference lithography (LIL) process combined with pulsed laser deposition. The shape and size of the nanostructures were controlled by the amount of PZT deposited through the patterned holes and the temperature of the post-crystallization steps. X-ray diffraction and transmission electron microscopy confirmed that (001)-oriented PZT nanostructures were grown epitaxially on the SrRuO3(001) bottom electrode layer covering the (001)-oriented single-crystal substrate. The domain structures of PZT nano-islands were characterized by reciprocal space mapping using synchrotron x-ray radiation. Ferroelectric properties of each PZT nanostructure were characterized by scanning force microscopy in the piezoresponse mode.

Han, Hee; Ji, Ran; Park, Yong Jun; Lee, Sung Kyun; LeRhun, Gwenael; Alexe, Marin; Nielsch, Kornelius; Hesse, Dietrich; Gsele, Ulrich; Baik, Sunggi

2009-01-01

17

Wafer-scale 3D integration of silicon-on-insulator RF amplifiers  

E-print Network

RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens ...

Keast, Craig L.

18

Integration of self-assembled carbon nanotube transistors: statistics and gate engineering at the wafer scale  

Microsoft Academic Search

We present a full process based on chemical vapour deposition that allows fabrication and integration at the wafer scale of carbon-nanotube-based field effect transistors. We make a statistical analysis of the integration yield that allows assessment of the parameter fluctuations of the titanium-nanotube contact obtained by self-assembly. This procedure is applied to raw devices without post-process. Statistics at the wafer

L. Marty; A. Bonhomme; A. Iaia; E. Andr; E. Rauwel; C. Dubourdieu; A. Toffoli; F. Ducroquet; A. M. Bonnot; V. Bouchiat

2006-01-01

19

Laser removal of Aluminum links for applications in wafer scale integrated circuits  

E-print Network

of MASTER OF SCIENCE May 1987 Major Subject: Electrical Engineering LASER REMOVAL OF ALUMINUM LINKS FOR APPLICATIONS IN WAFER SCALE INTEGRATED CIRCUITS A Thesis HARSHAVADAN B. PARIKH Approved ss to style snd content by: M. H, Weichold (Chairman... on the wafer between the modules. This structure has the feature of reconfigurability for fault tolerance and self healing using electrically alterable inter- connection. This feature provides that signals and power for any module can be connected...

Parikh, Harshavadan B.

2012-06-07

20

100GHz Transistors from Wafer-Scale Epitaxial Graphene  

Microsoft Academic Search

The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon

Y.-M. Lin; C. Dimitrakopoulos; K. A. Jenkins; D. B. Farmer; H.-Y. Chiu; A. Grill; Ph. Avouris

2010-01-01

21

Wafer-scale growth of single-crystal monolayer graphene on reusable hydrogen-terminated germanium.  

PubMed

The uniform growth of single-crystal graphene over wafer-scale areas remains a challenge in the commercial-level manufacturability of various electronic, photonic, mechanical, and other devices based on graphene. Here, we describe wafer-scale growth of wrinkle-free single-crystal monolayer graphene on silicon wafer using a hydrogen-terminated germanium buffer layer. The anisotropic twofold symmetry of the germanium (110) surface allowed unidirectional alignment of multiple seeds, which were merged to uniform single-crystal graphene with predefined orientation. Furthermore, the weak interaction between graphene and underlying hydrogen-terminated germanium surface enabled the facile etch-free dry transfer of graphene and the recycling of the germanium substrate for continual graphene growth. PMID:24700471

Lee, Jae-Hyun; Lee, Eun Kyung; Joo, Won-Jae; Jang, Yamujin; Kim, Byung-Sung; Lim, Jae Young; Choi, Soon-Hyung; Ahn, Sung Joon; Ahn, Joung Real; Park, Min-Ho; Yang, Cheol-Woong; Choi, Byoung Lyong; Hwang, Sung-Woo; Whang, Dongmok

2014-04-18

22

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.  

PubMed

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ?1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications. PMID:24909098

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-01

23

Toward wafer-scale patterning of freestanding intermetallic nanowires.  

PubMed

Individual metal alloy nanowires of constant diameter and high aspect ratio have previously been self-assembled at selected locations on atomic force microscope (AFM) probes by the method reported in Yazdanpanah et al (2005 J. Appl. Phys. 98 073510). This process relies on the room temperature crystallization of an ordered phase of silver-gallium. A parallel version of this method has been implemented in which a substrate, either an array of micromachined tips (similar to tips on AFM probes) or a lithographically patterned planar substrate, is brought into contact with a continuous, nearly planar film of melted gallium. In several runs, freestanding wires are fabricated with diameters of 40-400 nm, lengths of 4-80 m, growth rates of 80-170 nm s( - 1) and, most significantly, with yields of up to 97% in an array of 422 growth sites. These results demonstrate the feasibility of developing a batch manufacturing process for the decoration of wafers of AFM tips and other structures with selectively patterned freestanding nanowires. PMID:21673382

Jalilian, Romaneh; Rivera, Jose; Askari, Davood; Arva, Sreenath; Rathfon, Jeremy M; Cohn, Robert W; Yazdanpanah, Mehdi M

2011-07-22

24

Toward wafer-scale patterning of freestanding intermetallic nanowires  

NASA Astrophysics Data System (ADS)

Individual metal alloy nanowires of constant diameter and high aspect ratio have previously been self-assembled at selected locations on atomic force microscope (AFM) probes by the method reported in Yazdanpanah et al (2005 J. Appl. Phys. 98 073510). This process relies on the room temperature crystallization of an ordered phase of silver-gallium. A parallel version of this method has been implemented in which a substrate, either an array of micromachined tips (similar to tips on AFM probes) or a lithographically patterned planar substrate, is brought into contact with a continuous, nearly planar film of melted gallium. In several runs, freestanding wires are fabricated with diameters of 40-400 nm, lengths of 4-80 m, growth rates of 80-170 nm s - 1 and, most significantly, with yields of up to 97% in an array of 422 growth sites. These results demonstrate the feasibility of developing a batch manufacturing process for the decoration of wafers of AFM tips and other structures with selectively patterned freestanding nanowires.

Jalilian, Romaneh; Rivera, Jose; Askari, Davood; Arva, Sreenath; Rathfon, Jeremy M.; Cohn, Robert W.; Yazdanpanah, Mehdi M.

2011-07-01

25

Wafer-scale metasurface for total power absorption, local field enhancement and single  

E-print Network

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule. Effective electric and magnetic currents supported by SIOM metasurface We perform electromagnetic simulations of a 1 m ? 1 m area that models the SEM image of the SIOM metasurface shown as Figure S1a

26

Control of wafer-scale non-uniformity in chemical-mechanical planarization by face-up polishing  

E-print Network

Chemical-mechanical planarization (CMP) is a key process in the manufacture of ultra-large-scale-integrated (ULSI) semiconductor devices. A major concern in CMP is non-uniform planarization, or polishing, at the wafer-scale ...

Mau, Catherine (Catherine K.)

2008-01-01

27

Wafer-scale nanoconical frustum array crystalline silicon solar cells: promising candidates for ultrathin device applications  

NASA Astrophysics Data System (ADS)

A high photocurrent of 36.96 mA cm-2 was achieved for wafer-scaled crystalline Si solar cells with hexagonal nanoconical frustum arrays at the surface. Optical simulations showed that the expected photocurrent of 10 ?m thick nanostructured cells could slightly exceed the Lambertian limit.A high photocurrent of 36.96 mA cm-2 was achieved for wafer-scaled crystalline Si solar cells with hexagonal nanoconical frustum arrays at the surface. Optical simulations showed that the expected photocurrent of 10 ?m thick nanostructured cells could slightly exceed the Lambertian limit. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr01656d

Cho, Yunae; Gwon, Minji; Park, Hyeong-Ho; Kim, Joondong; Kim, Dong-Wook

2014-07-01

28

Wafer scale nano-membranes supported on a silicon microsieve using thin-film transfer technology  

Microsoft Academic Search

A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independent of the thin film, which is later transferred onto it by fusion bonding, thus providing flexibility in design and processing steps. Using this thin-film transfer technique, nano-membranes down

Sandeep Unnikrishnan; Henri Jansen; Erwin Berenschot; Miko Elwenspoek

2008-01-01

29

LIGA Micromachining: Infrastructure Establishment  

SciTech Connect

LIGA is a micromachining technology that uses high energy x-rays from a synchrotron to create patterns with small lateral dimensions in a deep, non-conducting polymeric resist. Typical dimensions for LIGA parts are microns to tens of microns in lateral size, and hundreds of microns to millimeters in depth. Once the resist is patterned, metal is electrodeposited in the features to create metal microparts, or to create a metal mold for subsequent replication. The acronym LIGA comes from the German words for lithography, electroforming, and molding, and the technology has been under worldwide development for more than a decade. over the last five years, a full-service capability to produce metal microparts using the LIGA process has been established at Sandia national Laboratories, California. This report describes the accomplishments made during the past two years in infrastructure establishment funded by a Laboratory Directed Research and Development (LDRD) project entitled ''LIGA Micromachining.'' Specific topics include photoresist processing for LIGA mask making, x-ray scanning equipment, plating bath instrumentation, plating uniformity, and software architecture.

Alfredo M. Morales; Barry V. Hess; Dale R. Boehme; Jill M. Hruby; John S. Krafcik; Robert H. Nilson; Stewart K. Griffiths; William D. Bonivert

1999-02-01

30

200 mm wafer-scale epitaxial transfer of single crystal Si on glass by anodic bonding of silicon-on-insulator wafers  

NASA Astrophysics Data System (ADS)

We report a low-temperature (350 C) anodic bonding followed by grind/etch-back method for a 200 mm wafer-scale epitaxial transfer of ultrathin (1.9 k) single crystalline Si on Pyrex glass. Standard back-end-of-line 3 k SiN/3 k undoped silicon glass passivating films were used as the buffer layers between the silicon-on-insulator wafer and the glass wafer. The quality and strain-free state of the transferred transparent Si film to glass was characterized by cross-sectional transmission electron microscopy, x-ray diffraction (XRD), and high-resolution XRD. Complete removal of the bulk Si after bonding was ascertained by Auger electron spectroscopy spectra and depth profiling. Strong adhesion between the transferred film and the glass wafer was verified by standard tape adhesion tests. This process will pave the way for future generations of Si-based microelectronics including bioelectronics.

Teh, W. H.; Trigg, Alastair; Tung, C. H.; Kumar, R.; Balasubramanian, N.; Kwong, D. L.

2005-08-01

31

Growth of wafer-scale MoS2 monolayer by magnetron sputtering.  

PubMed

The two-dimensional layer of molybdenum disulfide (MoS2) exhibits promising prospects in the applications of optoelectronics and valleytronics. Herein, we report a successful new process for synthesizing wafer-scale MoS2 atomic layers on diverse substrates via magnetron sputtering. Spectroscopic and microscopic results reveal that these synthesized MoS2 layers are highly homogeneous and crystallized; moreover, uniform monolayers at wafer scale can be achieved. Raman and photoluminescence spectroscopy indicate comparable optical qualities of these as-grown MoS2 with other methods. The transistors composed of the MoS2 film exhibit p-type performance with an on/off current ratio of ?10(3) and hole mobility of up to ?12.2 cm(2) V(-1) s(-1). The strategy reported herein paves new ways towards the large scale growth of various two-dimensional semiconductors with the feasibility of controllable doping to realize desired p- or n-type devices. PMID:25569291

Tao, Junguang; Chai, Jianwei; Lu, Xin; Wong, Lai Mun; Wong, Ten It; Pan, Jisheng; Xiong, Qihua; Chi, Dongzhi; Wang, Shijie

2015-01-28

32

Comprehensive investigation of sequential plasma activated Si/Si bonded interfaces for nano-integration on the wafer scale.  

PubMed

The sequentially plasma activated bonding of silicon wafers has been investigated to facilitate the development of chemical free, room temperature and spontaneous bonding required for nanostructure integration on the wafer scale. The contact angle of the surface and the electrical and nanostructural behavior of the interface have been studied. The contact angle measurements show that the sequentially plasma (reactive ion etching plasma followed by microwave radicals) treated surfaces offer highly reactive and hydrophilic surfaces. These highly reactive surfaces allow spontaneous integration at the nanometer scale without any chemicals, external pressure or heating. Electrical characteristics show that the current transportation across the nanobonded interface is dependent on the plasma parameters. High resolution transmission electron microscopy results confirm nanometer scale bonding which is needed for the integration of nanostructures. The findings can be applied in spontaneous integration of nanostructures such as nanowires/nanotubes/quantum dots on the wafer scale. PMID:20208123

Kibria, M G; Zhang, F; Lee, T H; Kim, M J; Howlader, M M R

2010-04-01

33

Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices  

PubMed Central

In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32?A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50?kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

2014-01-01

34

Wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible biomedical platform.  

PubMed

We present wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible parylene platform, as progress toward sustainably powering biomedical microsystems suitable for implantable and wearable applications. All-solid-state, low-profile (<30?m), and high-density (up to ~500?F/mm(2)) micro-supercapacitors are formed on an ultrathin (~20?m) freestanding parylene film by a wafer-scale parylene packaging process in combination with a polyaniline (PANI) nanowire growth technique assisted by surface plasma treatment. These micro-supercapacitors are highly flexible and shown to be resilient toward flexural stress. Further, direct integration of micro-supercapacitors into a radio frequency (RF) rectifying circuit is achieved on a single parylene platform, yielding a complete RF energy harvesting microsystem. The system discharging rate is shown to improve by ~17 times in the presence of the integrated micro-supercapacitors. This result suggests that the integrated micro-supercapacitor technology described herein is a promising strategy for sustainably powering biomedical microsystems dedicated to implantable and wearable applications. PMID:25653069

Maeng, Jimin; Meng, Chuizhou; Irazoqui, Pedro P

2015-02-01

35

Wafer-scale integration of graphene-based electronic, optoelectronic and electroacoustic devices.  

PubMed

In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

2014-01-01

36

Face-to-face transfer of wafer-scale graphene films.  

PubMed

Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene. PMID:24336218

Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H; Loh, Kian Ping

2014-01-01

37

Face-to-face transfer of wafer-scale graphene films  

NASA Astrophysics Data System (ADS)

Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene.

Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

2014-01-01

38

Advancing quasi-freestanding epitaxial graphene electronics through integration of wafer scale hexagonal boron nitride dielectrics  

NASA Astrophysics Data System (ADS)

A key limitation to graphene based electronics is graphene's interaction with dielectric interfaces. SiO2 and various high-k gate dielectrics can introduce scattering from charged surface states, impurities, and surface optical phonons; degrading the transport properties of graphene. Hexagonal boron nitride (h-BN) exhibits an atomically smooth surface that is expected to be free of dangling bonds, leading to an interface that is relatively free of surface charge traps and adsorbed impurities. Additionally, the decreased surface optical phonon interaction from h-BN is expected to further reduce scattering. While h-BN gated graphene FETs have been demonstrated on a small scale utilizing CVD grown or exfoliated graphene, integrating quasi-freestanding epitaxial graphene (QFEG) with h-BN gate dielectrics on a wafer scale has not been explored. We present results from the first large scale CVD growth of h-BN and its subsequent transfer to a 75mm QFEG wafer. The effects of growth conditions on the thickness and quality of the h-BN film and its potential and limitations as a gate dielectric to QFEG are discussed. The introduction of charged impurities during the transfer process resulted in an average degradation in mobility of only 9%. Despite the slight degradation, we show that h-BN is highly beneficial compared to high-k dielectrics when the charged impurity concentration of QFEG is below 5x1012cm-2. Here we show improvements in mobility of >3x and intrinsic cutoff frequency of >2x compared to HfO2.

Bresnehan, Michael S.; Hollander, Matthew J.; Marucci, Rebecca L.; LaBella, Michael; Trumbull, Kathleen A.; Cavalero, Randal; Snyder, David W.; Robinson, Joshua A.

2012-09-01

39

LIGAS INTERNAS DEPORTES INDIVIDUALES  

E-print Network

LIGAS INTERNAS DEPORTES INDIVIDUALES BASES DE COMPETICI?N AJEDREZ Art. 1.- Participantes 1 decidirá el equipo que representará a la Universidad de Alicante en el Campeonato Autonómico del Deporte ?nico de Competición (técnico del Servicio de Deportes) y se podrán presentar hasta 48 horas después de

Escolano, Francisco

40

Wafer-scale design of lightweight and transparent electronics that wraps around hairs.  

PubMed

Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-?m thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease. PMID:24399363

Salvatore, Giovanni A; Mnzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Bthe, Lars; Trster, Gerhard

2014-01-01

41

Wafer-scale design of lightweight and transparent electronics that wraps around hairs  

NASA Astrophysics Data System (ADS)

Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-?m thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12?V and above 1?MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

Salvatore, Giovanni A.; Mnzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Bthe, Lars; Trster, Gerhard

2014-01-01

42

C-and L-band erbium-doped waveguide lasers with wafer-scale silicon nitride cavities  

E-print Network

C- and L-band erbium-doped waveguide lasers with wafer-scale silicon nitride cavities Purnawirman,1; posted April 22, 2013 (Doc. ID 187023); published May 20, 2013 We report on integrated erbium and a top erbium-doped aluminum oxide layer deposited as the final step in the fabrication process

Reif, Rafael

43

Wafer-scale selective area growth of GaN hexagonal prismatic nanostructures on c-sapphire substrate  

E-print Network

1 Wafer-scale selective area growth of GaN hexagonal prismatic nanostructures on c-sapphire;2 ABSTRACT Selective area growth of GaN nanostructures has been performed on full 2" c-sapphire substrates that GaN nanostructures are grown in epitaxy with c-sapphire with lateral overgrowths on the mask. Strain

Paris-Sud XI, Université de

44

Toward the synthesis of wafer-scale single-crystal graphene on copper foils.  

PubMed

In this research, we constructed a controlled chamber pressure CVD (CP-CVD) system to manipulate graphene's domain sizes and shapes. Using this system, we synthesized large (~4.5 mm(2)) single-crystal hexagonal monolayer graphene domains on commercial polycrystalline Cu foils (99.8% purity), indicating its potential feasibility on a large scale at low cost. The as-synthesized graphene had a mobility of positive charge carriers of ~11,000 cm(2) V(-1) s(-1) on a SiO(2)/Si substrate at room temperature, suggesting its comparable quality to that of exfoliated graphene. The growth mechanism of Cu-based graphene was explored by studying the influence of varied growth parameters on graphene domain sizes. Cu pretreatments, electrochemical polishing, and high-pressure annealing are shown to be critical for suppressing graphene nucleation site density. A pressure of 108 Torr was the optimal chamber pressure for the synthesis of large single-crystal monolayer graphene. The synthesis of one graphene seed was achieved on centimeter-sized Cu foils by optimizing the flow rate ratio of H(2)/CH(4). This work should provide clear guidelines for the large-scale synthesis of wafer-scale single-crystal graphene, which is essential for the optimized graphene device fabrication. PMID:22966902

Yan, Zheng; Lin, Jian; Peng, Zhiwei; Sun, Zhengzong; Zhu, Yu; Li, Lei; Xiang, Changsheng; Samuel, E Loc; Kittrell, Carter; Tour, James M

2012-10-23

45

High speed wafer scale bulge testing for the determination of thin film mechanical properties  

PubMed Central

A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 ?m in width comprised of 72010 nm thick low pressure chemical vapor deposited silicon nitride with ?20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to ?8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (?350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Youngs modulus was estimated for the films assuming a Poissons ratio of v=0.25. Calculations to determine Youngs modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Youngs modulus for the smaller membranes. The deflection measurements of three 12001200 ?m2 Si3N4?x membranes were taken at increased pressures (>25 kPa) to increase nonlinearity and better determine Youngs modulus. This pressure-deflection data were fit to an analytical solution and Youngs modulus estimated to be 2573 GPa, close to those previously reported in literature. PMID:20515176

Orthner, M. P.; Rieth, L. W.; Solzbacher, F.

2010-01-01

46

Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale.  

PubMed

We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13??107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production. PMID:24289275

Ho, Jian-Wei; Wee, Qixun; Dumond, Jarrett; Tay, Andrew; Chua, Soo-Jin

2013-01-01

47

Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale  

PubMed Central

We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13??107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production. PMID:24289275

2013-01-01

48

Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale  

NASA Astrophysics Data System (ADS)

We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production.

Ho, Jian-Wei; Wee, Qixun; Dumond, Jarrett; Tay, Andrew; Chua, Soo-Jin

2013-12-01

49

A clean wafer-scale chip-release process without dicing based on vapor phase etching  

Microsoft Academic Search

A new method to release MEMS chips from a wafer without dicing is presented. It can be applied whenever SOI wafers are used that are structured from both the device and the handle side using DRIE. This method enables the release of extremely fragile structures without any mechanical impact on the chips. No more dicing residues or debris are created

T. Overstolz; P. A. Clerc; W. Noell; M. Zickar; N. F. de Rooij

2004-01-01

50

LIGA Micromachining Process Overview  

NSDL National Science Digital Library

This animation, created by Southwest Center for Microsystems Education (SCME), provides an overview of the LIGA micromachining process. Here, viewers will learn about the functionality of this process, including how its use for the "fabrication of high aspect ratio micro-sized components. This animation was produced by the Southwest Center for Microsystems Education and based on a process overview by HT Microanalytical." Further resources can be found on the SCME website in the MEMS Micromachining Overview, and select Educational Materials to access more learning modules.

2014-08-04

51

Atomic layer lithography of wafer-scale nanogap arrays for extreme confinement of electromagnetic waves.  

PubMed

Squeezing light through nanometre-wide gaps in metals can lead to extreme field enhancements, nonlocal electromagnetic effects and light-induced electron tunnelling. This intriguing regime, however, has not been readily accessible to experimentalists because of the lack of reliable technology to fabricate uniform nanogaps with atomic-scale resolution and high throughput. Here we introduce a new patterning technology based on atomic layer deposition and simple adhesive-tape-based planarization. Using this method, we create vertically oriented gaps in opaque metal films along the entire contour of a millimetre-sized pattern, with gap widths as narrow as 9.9 , and pack 150,000 such devices on a 4-inch wafer. Electromagnetic waves pass exclusively through the nanogaps, enabling background-free transmission measurements. We observe resonant transmission of near-infrared waves through 1.1-nm-wide gaps (?/1,295) and measure an effective refractive index of 17.8. We also observe resonant transmission of millimetre waves through 1.1-nm-wide gaps (?/4,000,000) and infer an unprecedented field enhancement factor of 25,000. PMID:23999053

Chen, Xiaoshu; Park, Hyeong-Ryeol; Pelton, Matthew; Piao, Xianji; Lindquist, Nathan C; Im, Hyungsoon; Kim, Yun Jung; Ahn, Jae Sung; Ahn, Kwang Jun; Park, Namkyoo; Kim, Dai-Sik; Oh, Sang-Hyun

2013-01-01

52

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy.  

PubMed

The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures ("metasurfaces") can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

Wang, Dongxing; Zhu, Wenqi; Best, Michael D; Camden, Jon P; Crozier, Kenneth B

2013-01-01

53

14C autoradiography with a novel wafer scale CMOS Active Pixel Sensor  

NASA Astrophysics Data System (ADS)

14C autoradiography is a well established technique for structural and metabolic analysis of cells and tissues. The most common detection medium for this application is film emulsion, which offers unbeatable spatial resolution due to its fine granularity but at the same time has some limiting drawbacks such as poor linearity and rapid saturation. In recent years several digital detectors have been developed, following the technological transition from analog to digital-based detection systems in the medical and biological field. Even so such digital systems have been greatly limited by the size of their active area (a few square centimeters), which have made them unsuitable for routine use in many biological applications where sample areas are typically ~ 10-100 cm2. The Multidimensional Integrated Intelligent Imaging (MI3-Plus) consortium has recently developed a new large area CMOS Active Pixel Sensor (12.8 cm 13.1 cm). This detector, based on the use of two different pixel resolutions, is capable of providing simultaneously low noise and high dynamic range on a wafer scale. In this paper we will demonstrate the suitability of this detector for routine beta autoradiography in a comparative approach with widely used film emulsion.

Esposito, M.; Anaxagoras, T.; Larner, J.; Allinson, N. M.; Wells, K.

2013-01-01

54

Wafer-scale highly-transparent and superhydrophilic sapphires for high-performance optics.  

PubMed

We reported the wafer-scale highly-transparent and superhydrophilic sapphires with antireflective subwavelength structures (SWSs) which were fabricated by dry etching using thermally dewetted gold (Au) nanomasks. Their optical transmittance properties were experimentally and theoretically investigated. The density, size, and period of the thermally dewetted Au nanopatterns can be controlled by the Au film thickness. For the sapphire with both-side SWSs at 5 nm of Au film, the average total transmittance (T(avg)) of ~96.5% at 350-800 nm was obtained, indicating a higher value than those of the flat sapphire (T(avg)~85.6%) and the sapphire with one-side SWSs (T(avg)~91%), and the less angle-dependent transmittance property was observed. The calculated transmittance results also showed a similar tendency to the measured data. The SWSs enhanced significantly the surface hydrophilicity of sapphires, exhibiting a water contact angle (?(c)) of < 5 for Au film of 5 nm compared to ?(c)~37 of the flat sapphire. PMID:23187471

Leem, Jung Woo; Yu, Jae Su

2012-11-19

55

A wafer-scale backplane-assisted resonating nanoantenna array SERS device created by tunable thermal dewetting nanofabrication  

NASA Astrophysics Data System (ADS)

A tunable lithography-less nanofabrication process using a metal thin-film thermal dewetting technique has been developed to fabricate wafer-scale and uniform plasmonic substrates at low cost for optimal performance in surface enhanced Raman scattering (SERS) applications. The relationship between the tunable parameters of this process and the corresponding optical and plasmonic characteristic is investigated both experimentally and theoretically to understand the deterministic design of an optimal SERS device with a three-dimensional plasmonic nanoantenna structure. The enhancement of SERS using various nanoplasmonic particle sizes, structure lengths, lateral hot spot spacings and resonating effects are examined and demonstrated. We achieve a uniform optimal enhancement factor of 1.38 108 on a 4 in wafer-scale SERS substrate with a backplane-assisted resonating nanoantenna array design. Sensitive environmental nitrate sensing, vitamin detection and oligonucleotide identification are demonstrated on the high-performance SERS device.

Chang, Te-Wei; Ranjan Gartia, Manas; Seo, Sujin; Hsiao, Austin; Logan Liu, Gang

2014-04-01

56

Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors  

NASA Astrophysics Data System (ADS)

Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm2/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

Kim, SangHyeon; Ikku, Yuki; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung; Takenaka, Mitsuru; Takagi, Shinichi

2014-07-01

57

Crack-release transfer method of wafer-scale grown graphene onto large-area substrates.  

PubMed

We developed a crack-release graphene transfer technique for opening up possibilities for the fabrication of graphene-based devices. Graphene film grown on metal catalysts/SiO2/Si wafer should be scathelessly peeled for sequent transferring to a target substrate. However, when the graphene is grown on the metal catalyst on a silicon substrate, there is a large tensile stress resulting from the difference of the coefficient of thermal expansion in the catalyst and silicon. The conventional methods of detaching graphene from metal catalysts were found to induce considerable mechanical damage on graphene films during separation processes including metal wet etching. Here we report a new technique wherein bubbles generated by electrolysis reaction separate thin metal catalysts from the SiO2/Si wafer. The dry attachment of graphene to the target wafer was processed utilizing a wafer to wafer bonding technique in a vacuum. We measured the microscopic image, Raman spectra, and electrical properties of the transferred graphene. The optical and electrical properties of the graphene transferred by the bubbles/dry method are better than those of the graphene obtained by mechanical/wet transfer. PMID:24967530

Lee, Jooho; Kim, Yongsung; Shin, Hyeon-Jin; Lee, ChangSeung; Lee, Dongwook; Lee, Sunghee; Moon, Chang-Yul; Lee, Su Chan; Kim, Sun Jun; Ji, Jae Hoon; Yoon, Hyong Seo; Jun, Seong Chan

2014-08-13

58

Wafer-scale coplanar waveguide slot-coupled Ka-band patch antenna for electronic scanning array of a future satellite communications system  

Microsoft Academic Search

This paper discussed about the successful simulated and measured data of the wafer-scale CPW slot-coupled Ka-band patch antenna presented above strongly advocate its candidacy for future integration with a MEMS-switched control board. Since it is a single-layer embodiment of the slot-coupling feed method, the total system weight is minimized and the complexity of the wafer-scale fabrication process is reduced. This,

Steven D. Keller; Steven J. Weiss; Ronald G. Polcawich; Daniel C. Judy

2008-01-01

59

Study of wafer thickness scaling in n-type rear-emitter solar cells with different bulk lifetimes  

NASA Astrophysics Data System (ADS)

In case of the n-type rear-emitter solar cell (n-RESC), wafer thickness scaling down has been studied and simulated under different bulk lifetimes (?bulk). The effect of minority-carrier lifetime of bulk ?bulk on photovoltaic properties has been studied by using a symmetrical front-and-rear electrode structure, followed by a discussion of the physical mechanism. Simulation results show that by decreasing the wafer thickness, high energy-conversion efficiency can be achieved, even though a low bulk lifetime substrate is used, suggesting a cost-effective way to manufacture the high efficiency n-RESC. In addition, emitter saturation current density (Joe) of the n-RESC has also been extracted.

Chen, Chen; Zhang, Wei; Xing, Zhao; Sun, Yun; Jia, Rui; Jin, Zhi; Liu, Xinyu; Redwing, Joan M.

2014-08-01

60

Double oxide deposition and etching nanolithography for wafer-scale nanopatterning with high-aspect-ratio using photolithography  

NASA Astrophysics Data System (ADS)

We report a nanolithography technique for the high aspect-ratio nanostructure manufacturing using DODE (double oxide deposition and etching) process. Conventional microfabrication processes are integrated to manufacture nanostructure arrays with sub-100 nm of linewidth. This lithography method is developed to overcome resolution limits of photolithography. High aspect-ratio nanostructures with sub-100 nm of lindewidth were fabricated on wafer-scale substrate without nanolithography techniques. The DODE lithography process presented enabled to pave a way to overcome limitations of nanolithography processes and allowed to manufacture large-scale nanostructures using photolithography and thin film deposition and dry etching processes.

Seo, Jungho; Cho, Hanchul; Lee, Ju-kyung; Lee, Jinyoung; Busnaina, Ahmed; Lee, HeaYeon

2013-07-01

61

Fabrication of large-scale monocrystalline silicon micro-mirror arrays using adhesive wafer transfer bonding  

NASA Astrophysics Data System (ADS)

Today, spatial light modulators (SLMs) based on individually addressable micro-mirrors play an important role for use in DUV lithography and adaptive optics. Especially the mirror planarity and stability are important issues for these applications. Mono-crystalline silicon as mirror material offers a great possibility to combine the perfect surface with the good mechanical properties of the crystalline material. Nevertheless, the challenge is the integration of mono-crystalline silicon in a CMOS process with low temperature budget (below 450C) and restricted material options. Thus, standard processes like epitaxial growth or re-crystallization of poly-silicon cannot be used. We will present a CMOS-compatible approach, using adhesive wafer transfer bonding with Benzocyclobutene (BCB) of a 300nm thin silicon membrane, located on a SOI-donor wafer. After the bond process, the SOI-donor wafer is grinded and spin etched to remove the handle silicon and the buried oxide layer, which results in a transfer of the mono-crystalline silicon membrane to the CMOS wafer. This technology is fully compatible for integration in a CMOS process, in order to fabricate SLMs, consisting of one million individually addressable mono-crystalline silicon micro-mirrors. The mirrors, presented here, have a size of 1616 ?m2. Deflection is achieved by applying a voltage between the mirrors and the underlying electrodes of the CMOS electronics. In this paper, we will present the fabrication process as well as first investigations of the mirror properties.

Zimmer, Fabian; Niklaus, Frank; Lapisa, Martin; Ludewig, Thomas; Bring, Martin; Friedrichs, Martin; Bakke, Thor; Schenk, Harald; van der Wijngaart, Wouter

2009-02-01

62

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays  

NASA Astrophysics Data System (ADS)

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 ?m is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 ?m 25 ?m that are arranged on read-out-wafers in arrays with 320 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Bjrn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Gran; Niklaus, Frank

2013-09-01

63

Activities of LIGA and Nano LIGA Technologies at BSRF  

Microsoft Academic Search

Beijing Synchrotron Radiation Facility (BSRF ) is a partly dedicated synchrotron radiation ( SR) source operated in either parasitic or dedicated mode. LIGA research at BSRF started from 1993 and focused in the first two steps of deep X-ray lithography and electroplating. Scanning exposure chamber of deep X-ray lithography was first built in 1996 on a 3W1 wiggler beamline with

F. Yi; J. Zhang; C. Xie; D. Wang; D. Chen

2006-01-01

64

Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales  

NASA Astrophysics Data System (ADS)

We introduce a method to fabricate solid-state nanopores with sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer using CMOS compatible semiconductor processes. Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated to have high uniformity (+/-0.5 nm) across the wafer. Arrays of nanopores were fabricated with an average size of 18 +/- 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling. Shorts between the membrane-embedded metals were occasionally created after pore formation, but the RIE based pores had a much better yield (99%) of unshorted electrodes compared to TEM drilled pores (<10%). A double-stranded DNA of length 1 kbp was translocated through the multi-layer structure RIE-based nanopore demonstrating that the pores were open. The ionic current through the pore can be modulated with a gain of 3 using embedded electrodes functioning as a gate in 0.1 mM KCl aqueous solution. This fabrication approach can potentially pave the way to manufacturable nanopore arrays with the ability to electrically control the movement of single or double-stranded DNA inside the pore with embedded electrodes.We introduce a method to fabricate solid-state nanopores with sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer using CMOS compatible semiconductor processes. Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated to have high uniformity (+/-0.5 nm) across the wafer. Arrays of nanopores were fabricated with an average size of 18 +/- 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling. Shorts between the membrane-embedded metals were occasionally created after pore formation, but the RIE based pores had a much better yield (99%) of unshorted electrodes compared to TEM drilled pores (<10%). A double-stranded DNA of length 1 kbp was translocated through the multi-layer structure RIE-based nanopore demonstrating that the pores were open. The ionic current through the pore can be modulated with a gain of 3 using embedded electrodes functioning as a gate in 0.1 mM KCl aqueous solution. This fabrication approach can potentially pave the way to manufacturable nanopore arrays with the ability to electrically control the movement of single or double-stranded DNA inside the pore with embedded electrodes. Electronic supplementary information (ESI) available: Additional data, instrumentation and data analysis methods. See DOI: 10.1039/c3nr06723h

Bai, Jingwei; Wang, Deqiang; Nam, Sung-Wook; Peng, Hongbo; Bruce, Robert; Gignac, Lynn; Brink, Markus; Kratschmer, Ernst; Rossnagel, Stephen; Waggoner, Phil; Reuter, Kathleen; Wang, Chao; Astier, Yann; Balagurusamy, Venkat; Luan, Binquan; Kwark, Young; Joseph, Eric; Guillorn, Mike; Polonsky, Stanislav; Royyuru, Ajay; Papa Rao, S.; Stolovitzky, Gustavo

2014-07-01

65

Stationary Optical Concentrator Designs and Wafer Scale Monolithic Integration of Semiconductor Devices for Next Generation Photovoltaic Panels  

NASA Astrophysics Data System (ADS)

A major barrier in utilizing solar energy for large scale deployment is the cost of the photovoltaic (PV) systems. Several approaches have been used for the cost reduction such as by modifying PV system designs in addition to enhancing the efficiency of solar cells. Due to the high cost of materials, minimizing the use of solar cells such as in concentrator type systems is highly attractive for reducing the cost of the PV modules by focusing the incident light onto the PV cell. However concentrator PV systems (CPV) require constant tracking of the sun and hence are complex in design and expensive to operate, except in limited situations such as large scale PV power plants. It is desirable to design new concentrator type systems that do not require continuous tracking of the sun. These systems could ultimately reduce the PV system cost to a minimum while maximizing the power conversion efficiency. In this thesis we propose a simple design for a stationary concentrator photovoltaic (SCPV) system that could significantly reduce the cost of generating electricity using PV devices. Using optical ray tracing simulations, we have been able to design SCPV systems that could reduce the PV module cost by 2--10 times without compromising on the power conversion efficiency of the system. Another alternative approach for sustainable high efficiency PV system design is to develop low cost PV cells for terrestrial applications. To meet the demands of low cost and large scale production, larger and thinner (or flexible) substrates are required. We demonstrated the feasibility of fabricating monolithic interconnected PV devices at the wafer scale (2 inch wafers). In this study, GaSb PV cells grown on semi-insulating GaAs were used as the model material. Crucial device fabrication steps such as a selective etching process have been developed that is necessary for isolating individual devices on the wafer and interconnecting them with sub-micron scale accuracy. Selective etching of GaSb and GaAs has been developed for isolation of GaSb devices on semi-insulating GaAs substrates. Smooth side wall morphology and desirable depth profile of the etched structures have been accomplished using optimized etching conditions presented in this thesis. Device fabrication of series interconnected GaSb PV cells on a GaAs substrate with single-sided metal contacts has been successfully demonstrated.

Kim, Jung Min

66

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking  

PubMed Central

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 m larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 m CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 m and 0.5 m, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-01-01

67

Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics  

SciTech Connect

Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2?V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure?wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

Sangwan, Vinod K.; Jariwala, Deep; McMorrow, Julian J.; He, Jianting; Lauhon, Lincoln J. [Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208 (United States); Everaerts, Ken [Department of Chemistry, Northwestern University, Evanston, Illinois 60208 (United States); Grayson, Matthew [Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, Illinois 60208 (United States); Marks, Tobin J., E-mail: t-marks@northwestern.edu, E-mail: m-hersam@northwestern.edu; Hersam, Mark C., E-mail: t-marks@northwestern.edu, E-mail: m-hersam@northwestern.edu [Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208 (United States); Department of Chemistry, Northwestern University, Evanston, Illinois 60208 (United States)

2014-02-24

68

LIGAS INTERNAS DEPORTES DE EQUIPO  

E-print Network

LIGAS INTERNAS DEPORTES DE EQUIPO BASES DE COMPETICI?N BALONCESTO Art. 1.- Participantes 1 sanciones serán dirigidas y resueltas por el Juez ?nico de Competición (un técnico del Servicio de Deportes, plazo y forma de inscripción y de pago, serán los publicados en la página web del Servicio de Deportes

Escolano, Francisco

69

C- and L-band erbium-doped waveguide lasers with wafer-scale silicon nitride cavities.  

PubMed

We report on integrated erbium-doped waveguide lasers designed for silicon photonic systems. The distributed Bragg reflector laser cavities consist of silicon nitride waveguide and grating features defined by wafer-scale immersion lithography and a top erbium-doped aluminum oxide layer deposited as the final step in the fabrication process. The resulting inverted ridge waveguide yields high optical intensity overlap with the active medium for both the 0.98 ?m pump (89%) and 1.5 ?m laser (87%) wavelengths with a pump-laser intensity overlap of >93%. We obtain output powers of up to 5 mW and show lasing at widely spaced wavelengths within both the C and L bands of the erbium gain spectrum (1536, 1561, and 1596 nm). PMID:23862218

Purnawirman; Sun, J; Adam, T N; Leake, G; Coolbaugh, D; Bradley, J D B; Shah Hosseini, E; Watts, M R

2013-06-01

70

Facile fabrication of wafer-scale MoS2 neat films with enhanced third-order nonlinear optical performance.  

PubMed

Wafer-scale MoS2 neat films with controllable thicknesses were successfully fabricated by vacuum filtering liquid-exfoliated MoS2 dispersions. The obtained MoS2 filtered thin films were systematically characterized by UV-Vis spectroscopy, Fourier transform infrared spectroscopy (FTIR), Raman spectroscopy, atomic force microscopy (AFM) and scanning electron microscopy (SEM). It was found that the fabricated scalable MoS2 films have a smooth surface and high optical homogeneity verified by AFM and a collimated 532 nm beam, respectively. We investigated the ultrafast nonlinear optical (NLO) properties of the filtered films by an open aperture Z-scan method using 515 and 1030 nm femtosecond laser pulses. Saturable absorption was observed at both 515 and 1030 nm with the figure of merit (FOM) values as ?3.3 10(-12) esu cm and ?3.4 10(-14) esu cm, respectively. The observation of ultrafast NLO performance of the MoS2 filtered films indicates that vacuum filtration is a feasible method for the fabrication of optical thin films, which can be expanded to fabricate other two-dimensional films from the corresponding dispersions. This easy film fabrication technology will greatly enlarge the application of graphene analogues including graphene in photonic devices, especially of MoS2 as a saturable absorber. PMID:25597818

Zhang, Xiaoyan; Zhang, Saifeng; Chang, Chunxia; Feng, Yanyan; Li, Yuanxin; Dong, Ningning; Wang, Kangpeng; Zhang, Long; Blau, Werner J; Wang, Jun

2015-02-01

71

Nanogap-enhanced infrared spectroscopy with template-stripped wafer-scale arrays of buried plasmonic cavities.  

PubMed

We have combined atomic layer lithography and template stripping to produce a new class of substrates for surface-enhanced infrared absorption (SEIRA) spectroscopy. Our structure consists of a buried and U-shaped metal-insulator-metal waveguide whose folded vertical arms efficiently couple normally incident light. The insulator is formed by atomic layer deposition (ALD) of Al2O3 and precisely defines the gap size. The buried nanocavities are protected from contamination by a silicon template until ready for use and exposed by template stripping on demand. The exposed nanocavity generates strong infrared resonances, tightly confines infrared radiation into a gap that is as small as 3 nm (?/3300), and creates a dense array of millimeter-long hotspots. After partial removal of the insulators, the gaps are backfilled with benzenethiol molecules, generating distinct Fano resonances due to strong coupling with gap plasmons, and a SEIRA enhancement factor of 10(5) is observed for a 3 nm gap. Because of the wafer-scale manufacturability, single-digit-nanometer control of the gap size via ALD, and long-term storage enabled by template stripping, our buried plasmonic nanocavity substrates will benefit broad applications in sensing and spectroscopy. PMID:25423481

Chen, Xiaoshu; Cirac, Cristian; Smith, David R; Oh, Sang-Hyun

2015-01-14

72

Slip, Crystal Orientation, and Damage Evolution During Thermal Cycling in High-Strain Wafer-Level Chip-Scale Packages  

NASA Astrophysics Data System (ADS)

Wafer-level chip-scale package samples with pre-cross-sectioned edge rows were thermally cycled to study microstructure evolution and damage development. Electron backscattered diffraction (EBSD) and high-energy x-ray diffraction were used to obtain Sn grain orientations and the average coefficient of thermal expansion normal to the board in every joint of the package for samples in the as-fabricated and thermally cycled conditions. The results indicated a near-random distribution of joint orientation. Optical, scanning electron microscopy, and EBSD methods were used to characterize microstructure changes in pre-cross-sectioned samples due to thermal cycling. Slip trace analysis and Orientation Imaging Microscopy (OIM) show that slip systems with high Schmid factors (estimated global shear stress based on the package neutral point) are responsible for the observed microstructure evolution during thermal cycling, which provides information about slip systems that are more easily activated. Two joints were analyzed in detail to evaluate slip activity at different stages of their thermal history. The first case showed that a solidification twin grain boundary misorientation deviated from the twin relationship due to slip activity during thermal cycling, which can influence damage development and the path of crack propagation. The second case showed a new grain orientation developing due to gradual lattice rotation about the Sn [110] axis by a continuous recrystallization mechanism. This rotation was correlated with the operation of slip system { 110 )< {001}. Small tin whiskers emerged from the initially polished chip interface and grew with increasing thermal cycles until a crack developed in the solder that relieved the stress. As the local stresses are not known experimentally, this analysis provides observations that can be compared with a crystal plasticity model simulation.

Zhou, Bite; Zhou, Quan; Bieler, Thomas R.; Lee, Tae-kyu

2015-01-01

73

Imaging ATUM ultrathin section libraries with WaferMapper: a multi-scale approach to EM reconstruction of neural circuits  

PubMed Central

The automated tape-collecting ultramicrotome (ATUM) makes it possible to collect large numbers of ultrathin sections quicklythe equivalent of a petabyte of high resolution images each day. However, even high throughput image acquisition strategies generate images far more slowly (at present ~1 terabyte per day). We therefore developed WaferMapper, a software package that takes a multi-resolution approach to mapping and imaging select regions within a library of ultrathin sections. This automated method selects and directs imaging of corresponding regions within each section of an ultrathin section library (UTSL) that may contain many thousands of sections. Using WaferMapper, it is possible to map thousands of tissue sections at low resolution and target multiple points of interest for high resolution imaging based on anatomical landmarks. The program can also be used to expand previously imaged regions, acquire data under different imaging conditions, or re-image after additional tissue treatments. PMID:25018701

Hayworth, Kenneth J.; Morgan, Josh L.; Schalek, Richard; Berger, Daniel R.; Hildebrand, David G. C.; Lichtman, Jeff W.

2014-01-01

74

Laparoscopic Decortication of Hilar Renal Cysts Using LigaSure  

PubMed Central

Background and Objectives: In this study, we evaluated the safety and efficacy of using the LigaSure sealing system (Valleylab, Boulder, Colorado) for laparoscopic decortication of symptomatic hilar renal cysts. Methods: Seventeen patients underwent laparoscopic decortication of hilar renal cysts with the LigaSure system. Our study included only symptomatic, Bosniak type 1, simple and symptomatic renal cysts. The operative route, transperitoneal or retroperitoneal, was planned according to the location confirmed by computed tomography. The patients' symptoms were preoperatively and postoperatively evaluated by the Wong-Baker visual pain scale. Operative measures and radiologic outcomes were prospectively evaluated. Results: The mean age of the patients was 56.4 years, and the mean follow-up period was 12.5 months. Preoperative computed tomography showed only a single cyst in 15 patients (88.2%) and showed two separate cysts in 2 cases (11.8%). The cysts were located in the perihilar region close to the vascular structure in all patients. A transperitoneal approach was used in 9 patients, and a retroperitoneal approach was used in 8 patients. The mean operative time and hospitalization time were 56.4 minutes and 1.2 days, respectively. Minor complications were observed in 3 patients. Symptomatic and radiologic success rates of 94.2% and 100%, respectively, were achieved. Conclusion: Laparoscopic decortication of symptomatic hilar renal cystsfirst reported in the literature in this studyusing the LigaSure sealing system is feasible, effective, and safe, even if the cyst is located in the perihilar area. PMID:24960497

Tepeler, Abdulkadir; Gunes, Mustafa; S?lay, Mesrur Selcuk; Akman, Tolga; Akcay, Muzaffer; Armagan, Abdullah; Onol, Sinasi Yavuz

2014-01-01

75

Transport limitations in electrodeposition for LIGA microdevice fabrication  

NASA Astrophysics Data System (ADS)

To better understand and to help optimize the electroforming portion of the LIGA process, we have developed one and two- dimensional numerical models describing electrodeposition of metal into high aspect-ratio molds. The one-dimensional model addresses dissociation, diffusion, electromigration, and deposition of multiple ion species. The two-dimensional model is limited to a single species, but includes transport induced by forced flow of electrolyte outside the mold and by buoyancy associated with metal ion depletion within the mold. To guide model development and to validate these models, we have also conducted a series of laboratory experiments using a sulfamate bath to deposit nickel in cylindrical molds having aspect ratios up to twenty-five. The experimental results indicate that current densities well in excess of diffusion-limited currents may still yield acceptable morphologies in the deposited metal. However, the numerical models demonstrate that such large ion fluxes cannot be sustained by convection within the mold resulting from flow across the mold top. Instead, calculations suggest that the observed hundred-fold enhancement of transport probably results from natural convection within the molds and that buoyancy-driven flows may be critical to metal ion transport even in micron-scale features having very large aspect ratios. Taking advantage of this enhanced ion transport may allow order-of-magnitude reductions in electroforming times for LIGA microdevice fabrication.

Griffiths, Stewart K.; Nilson, Robert H.; Bradshaw, R. W.; Ting, Aili; Bonivert, William D.; Hachman, John T.; Hruby, Jill M.

1998-08-01

76

Silicon Wafer Epitaxy  

NSDL National Science Digital Library

This Quicktime animation shows an optional process for creating silicon epitaxial wafers. The animations shows a trichlorosilane gas being injected which creates a monocrystaline film atop the preexisting wafer. This is the seventh animation in a series of how silicon wafers are created. The previous animation showing silicon wafer polishing can be seen here.The next and final animation in this sequence about silicon wafer laser inspection can be seen here.

2009-10-19

77

The Covidien LigaSure Maryland Jaw Device.  

PubMed

Since its invention nearly 20 years ago, the Covidien LigaSure device along with its ForceTriad generator has dominated the Electrothermal Bipolar Vessel Sealing market. The LigaSure was used for surgical procedures, both open and laparoscopic. The purpose of this review is to provide evidence of the safety and utility of the LigaSure device compared to more traditional means of hemostasis and its ultrasonic competitor, particularly in laparoscopic applications. We will provide evidence related to electrothermal bipolar vessel sealing in general and look specifically at Covidien's newest product, the LigaSure Maryland Jaw Device. PMID:25431842

Zaidi, Nisar; Glover, Anthony R; Sidhu, Stanley B

2015-03-01

78

Layer-controlled, wafer-scale, and conformal synthesis of tungsten disulfide nanosheets using atomic layer deposition.  

PubMed

The synthesis of atomically thin transition-metal disulfides (MS2) with layer controllability and large-area uniformity is an essential requirement for their application in electronic and optical devices. In this work, we describe a process for the synthesis of WS2 nanosheets through the sulfurization of an atomic layer deposition (ALD) WO3 film with systematic layer controllability and wafer-level uniformity. The X-ray photoemission spectroscopy, Raman, and photoluminescence measurements exhibit that the ALD-based WS2 nanosheets have good stoichiometry, clear Raman shift, and bandgap dependence as a function of the number of layers. The electron mobility of the monolayer WS2 measured using a field-effect transistor (FET) with a high-k dielectric gate insulator is shown to be better than that of CVD-grown WS2, and the subthreshold swing is comparable to that of an exfoliated MoS2 FET device. Moreover, by utilizing the high conformality of the ALD process, we have developed a process for the fabrication of WS2 nanotubes. PMID:24252136

Song, Jeong-Gyu; Park, Jusang; Lee, Wonseon; Choi, Taejin; Jung, Hanearl; Lee, Chang Wan; Hwang, Sung-Hwan; Myoung, Jae Min; Jung, Jae-Hoon; Kim, Soo-Hyun; Lansalot-Matras, Clement; Kim, Hyungjun

2013-12-23

79

Fast and robust hydrogen sensors based on discontinuous palladium films on polyimide, fabricated on a wafer scale.  

PubMed

Fast hydrogen sensors based on discontinuous palladium (Pd) films on supporting polyimide layers, fabricated by a cost-efficient and full-wafer compatible process, are presented. The films, deposited by electron-beam evaporation with a nominal thickness of 1.5 nm, consist of isolated Pd islands that are separated by nanoscopic gaps. On hydrogenation, the volume expansion of Pd brings initially separated islands into contact which leads to the creation of new electrical pathways through the film. The supporting polyimide layer provides both sufficient elasticity for the Pd nanoclusters to expand on hydrogenation and a sufficiently high surface energy for good adhesion of both film and contacting electrodes. The novel order of the fabrication processes involves a dicing step prior to the Pd deposition and stencil lithography for the patterning of microelectrodes. This allows us to preserve the as-deposited film properties. The devices work at room temperature, show response times of a few seconds and have a low power consumption of some tens of nW. PMID:21098952

Kiefer, T; Villanueva, L G; Fargier, F; Favier, F; Brugger, J

2010-12-17

80

Scheduling semiconductor wafer fabrication  

Microsoft Academic Search

The impact that scheduling can have on the performance of semi-conductor wafer fabrication facilities is assessed. The performance measure considered is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative, but fictitious, semiconductor wafer

LAWRENCE M. WEIN

1988-01-01

81

Silicon Wafer Polishing  

NSDL National Science Digital Library

This Quicktime animation demostrates the final polishing and cleaning processes required for creating semiconductor devices and integrated circuits. This animation is the sixth in a series of how silicon wafers are created. The previous animation showing silicon wafer lapping can be seen here. The next animation in this sequence about the optional silicon wafer epitaxy process can be seen here.

2009-10-21

82

Silicon Wafer Lapping  

NSDL National Science Digital Library

This Quicktime animation shows how the machining process of "lapping" removes controlled amounts of silicon from a wafer in order to ensure flatness of the silicon wafer. This process removes particles and improves the quality of the wafer after they are cut. This animation is the fifth in a series of how silicon wafers are created.The previous animation showing silicon ingot edge profiling can be seen here.The next animation in this sequence about silicon wafer polishing can be seen here.

2010-02-08

83

Final-part metrology for LIGA springs, Build Group 1.  

SciTech Connect

The LIGA spring is a recently designed part for defense program applications. The Sandia California LIGA team has produced an initial group build of these nickel alloy parts. These are distinctive in having a macroscopic lateral size of about 1 cm, while requiring microscopic dimensional precision on the order of a few micrometers. LIGA technology capabilities at Sandia are able to manufacture such precise structures. While certain aspects of the LIGA process and its production capabilities have been dimensionally characterized in the past, [1-6] the present work is exclusive in defining a set of methods and techniques to inspect and measure final LIGA nickel alloy parts in large prototype quantities. One hundred percent inspection, meaning that every single LIGA part produced needs to be measured, ensures quality control and customer satisfaction in this prototype production run. After a general visual inspection of the parts and an x-ray check for voids, high precision dimensional metrology tools are employed. The acquired data is analyzed using both in house and commercially available software. Examples of measurements illustrating these new metrology capabilities are presented throughout the report. These examples furthermore emphasize that thorough inspection of every final part is not only essential to characterize but also improve the LIGA manufacturing process.

Aigeldinger, Georg; Skala, Dawn M.; Ceremuga, Joseph T.; Mills, Bernice E.

2004-03-01

84

Application Specific Wafer Stepper  

NASA Astrophysics Data System (ADS)

Overlay, throughput and lens performance are three critical parameters of optical alignment equipment. High overlay accuracy will give high die yields for alignment sensitive parts or can allow designers to use tighter design rules which will allow a shrink of the chip and more chips per wafer. This work contains high overlay accuracy data obtained during the processing of production wafer lots of a 64K HRAM (Hierarchical RAM) device using an ASM Lithography PAS 2000 Wafer Stepper.

Fallon, Dick; Shih, James R.

1987-01-01

85

Micro-grippers for assembly of LIGA parts  

SciTech Connect

This paper describes ongoing testing of two microgrippers for assembly of LIGA (Lithographie Galvanoformung Abformung) parts. The goal is to place 100 micron outside diameter (OD) LIGA gears with a 50 micron inner diameter hole onto pins ranging from 35 to 49 microns. The first micro gripper is a vacuum gripper made of a 100 micron OD stainless steel tube. The second micro gripper is a set of tweezers fabricated using the LIGA process. Nickel, Permalloy, and copper materials are tested. The tweezers are actuated by a collet mechanism which is closed by a DC linear motor.

Feddema, J.; Polosky, M.; Christenson, T.; Spletzer, B.; Simon, R.

1997-12-31

86

100-nm-Scale Alignment using Laser Beam Diffraction Pattern Observation Techniques and Wafer Fusion for Realizing Three-Dimensional Photonic Crystal Structure  

Microsoft Academic Search

We previously proposed a new method for realizing three-dimensional photonic crystals in the optical wavelength region, where two-dimensional basic structures are aligned using a laser beam diffraction pattern observation techniqueand stacked by means of a wafer fusion.In this method, it is essential to align the two-dimensional basic structures with an accuracy of optical wavelength order at wafer fusion.In this work,

Noritsugu Yamamoto; Susumu Noda

1998-01-01

87

Cantilevered multilevel LIGA devices and methods  

DOEpatents

In the formation of multilevel LIGA microstructures, a preformed sheet of photoresist material, such as polymethylmethacrylate (PMMA) is patterned by exposure through a mask to radiation, such as X-rays, and developed using a developer to remove the exposed photoresist material. A first microstructure is then formed by electroplating metal into the areas from which the photoresist has been removed. Additional levels of microstructure are added to the initial microstructure by covering the first microstructure with a conductive polymer, machining the conductive polymer layer to reveal the surface of the first microstructure, sealing the conductive polymer and surface of the first microstructure with a metal layer, and then forming the second level of structure on top of the first level structure. In such a manner, multiple layers of microstructure can be built up to allow complex cantilevered microstructures to be formed.

Morales, Alfredo Martin (Pleasanton, CA); Domeier, Linda A. (Danville, CA)

2002-01-01

88

Miniature Scroll Pumps Fabricated by LIGA  

NASA Technical Reports Server (NTRS)

Miniature scroll pumps have been proposed as roughing pumps (low - vacuum pumps) for miniature scientific instruments (e.g., portable mass spectrometers and gas analyzers) that depend on vacuum. The larger scroll pumps used as roughing pumps in some older vacuum systems are fabricated by conventional machining. Typically, such an older scroll pump includes (1) an electric motor with an eccentric shaft to generate orbital motion of a scroll and (2) conventional bearings to restrict the orbital motion to a circle. The proposed miniature scroll pumps would differ from the prior, larger ones in both design and fabrication. A miniature scroll pump would include two scrolls: one mounted on a stationary baseplate and one on a flexure stage (see figure). An electromagnetic actuator in the form of two pairs of voice coils in a push-pull configuration would make the flexure stage move in the desired circular orbit. The capacitance between the scrolls would be monitored to provide position (gap) feedback to a control system that would adjust the drive signals applied to the voice coils to maintain the circular orbit as needed for precise sealing of the scrolls. To minimize power consumption and maximize precision of control, the flexure stage would be driven at the frequency of its mechanical resonance. The miniaturization of these pumps would entail both operational and manufacturing tolerances of <1 m. Such tight tolerances cannot be achieved easily by conventional machining of high-aspect-ratio structures like those of scroll-pump components. In addition, the vibrations of conventional motors and ball bearings exceed these tight tolerances by an order of magnitude. Therefore, the proposed pumps would be fabricated by the microfabrication method known by the German acronym LIGA ( lithographie, galvanoformung, abformung, which means lithography, electroforming, molding) because LIGA has been shown to be capable of providing the required tolerances at large aspect ratios.

Wiberg, Dean; Shcheglov, Kirill; White, Victor; Bae, Sam

2009-01-01

89

Wafer scale micromachine assembly method  

DOEpatents

A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.

Christenson, Todd R. (Albuquerque, NM)

2001-01-01

90

Wafer level reliability testing: An idea whose time has come  

NASA Technical Reports Server (NTRS)

Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

Trapp, O. D.

1987-01-01

91

Wafer characteristics via reflectometry  

DOEpatents

Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

Sopori, Bhushan L. (Denver, CO)

2010-10-19

92

Scriber for silicon wafers  

NASA Technical Reports Server (NTRS)

A device for dividing silicon wafers into rectangular chips is characterized by a base including a horizontally oriented bed with a planar support surface, a vacuum chuck adapted to capture a silicon wafer seated on the support for translation in mutually perpendicular directions. A stylus support mounted on the bed includes a shaft disposed above and extended across the bed and a truck mounted on the shaft and supported thereby for linear translation along a path extended across the bed a vertically oriented scribe has a diamond tip supported by the truck also adapted as to engage a silicon wafer captured by the chuck and positioned beneath it in order to form score lines in the surface of the wafer as linear translation is imparted to the truck. A chuck positioning means is mounted on the base and is connected to the chuck for positioning the chuck relative to the stylus.

Yamakawa, K. A.; Fortier, E. P. (inventors)

1981-01-01

93

Reciprocating Saw for Silicon Wafers  

NASA Technical Reports Server (NTRS)

Concept increases productivity and wafer quality. Cutting wafers from silicon ingots produces smooth wafers at high rates with reduced blade wear. Involves straight reciprocating saw blade and slight rotation of ingot between cutting strokes. Many parallel blades combined to cut many wafers simultaneously from ingot.

Morrison, A. D.; Collins, E. R., Jr.

1985-01-01

94

Stable wafer-carrier system  

DOEpatents

One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

2013-10-22

95

Development of miniaturized piezoelectric actuators for optical applications realized using LIGA technology  

Microsoft Academic Search

To combine the advantages of the LIGA technology and piezoelectric materials, first prototypes of movable elastic LIGA structures have been realized on piezoelectric substrates. The structures consist of a flexible beam fixed to the piezoelectric substrate at its two ends in order to amplify the d31-contraction of the piezoelectric substrate. By using this flexible LIGA beam as a magnification mechanism,

H. Debeda; T. v. Freyhold; J. Mohr; U. Wallrabe; J. Wengelink

1999-01-01

96

Wafer screening device and methods for wafer screening  

DOEpatents

Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

Sopori, Bhushan; Rupnowski, Przemyslaw

2014-07-15

97

Recent Developments in Microsystems Fabricated by the Liga-Technique  

NASA Technical Reports Server (NTRS)

As an example of microsystems fabricated by the LIGA-technique (x-ray lithography, electroplating and molding), three systems are described and characterized: a triaxial acceleration sensor system, a micro-optical switch, and a microsystem for the analysis of pollutants. The fabrication technologies are reviewed with respect to the key components of the three systems: an acceleration sensor, and electrostatic actuator, and a spectrometer made by the LIGA-technique. Aa micro-pump and micro-valve made by using micromachined tools for molding and optical fiber imaging are made possible by combining LIGA and anisotropic etching of silicon in a batch process. These examples show that the combination of technologies and components is the key to complex microsystems. The design of such microsystems will be facilitated is standardized interfaces are available.

Schulz, J.; Bade, K.; El-Kholi, A.; Hein, H.; Mohr, J.

1995-01-01

98

Wafer-scale Epitaxial Graphene Growth on the Si-face of Hexagonal SiC (0001) for High Frequency Transistors  

Microsoft Academic Search

Up to two layers of epitaxial graphene have been grown on the Si-face of two-inch SiC wafers exhibiting room-temperature Hall mobilities up to 1800 cm^2\\/Vs, measured from ungated, large, 160 micron x 200 micron Hall bars, and up to 4000 cm^2\\/Vs, from top-gated, small, 1 micron x 1.5 micron Hall bars. The growth process involved a combination of a cleaning

Christos Dimitrakopoulos; Yu-Ming Lin; Alfred Grill; Damon B. Farmer; Marcus Freitag; Yanning Sun; Shu-Jen Han; Zhihong Chen; Keith A. Jenkins; Yu Zhu; Zihong Liu; Timothy J. McArdle; John A. Ott; Robert Wisnieff; Phaedon Avouris

2010-01-01

99

Structured wafer for device processing  

DOEpatents

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Okandan, Murat; Nielson, Gregory N

2014-05-20

100

Structured wafer for device processing  

DOEpatents

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Okandan, Murat; Nielson, Gregory N

2014-11-25

101

Osmolarity, a Key Environmental Signal Controlling Expression of Leptospiral Proteins LigA and LigB and the Extracellular Release of LigA  

Microsoft Academic Search

The high-molecular-weight leptospiral immunoglobulin-like repeat (Lig) proteins are expressed only by virulent low-passage forms of pathogenic Leptospira species. We examined the effects of growth phase and environmental signals on the expression, surface exposure, and extracellular release of LigA and LigB. LigA was lost from stationary-phase cells, while LigB expression was maintained. The loss of cell-associated LigA correlated with selective release

James Matsunaga; Yolanda Sanchez; Xiaoyi Xu; David A. Haake

2005-01-01

102

Etching Of Semiconductor Wafer Edges  

DOEpatents

A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

Kardauskas, Michael J. (Billerica, MA); Piwczyk, Bernhard P. (Dunbarton, NH)

2003-12-09

103

A LIGA Fabricated Quadrupole Array for Mass Spectroscopy  

NASA Technical Reports Server (NTRS)

A linear array of nine quadrupoles was fabricated using the LIGA process. Pole heights ranging from 1 to 3 mm were fabricated using synchrotron X-ray exposures to form free standing polymethylmethacrylate (PMMA) molds into which copper, gold or nickel were electroplated.

Jackson, K.; Wiberg, D. V.; Hecht, M. H.; Orient, O. J.; Chutjian, A.; Yee, K.; Fuerstenau, S.; Brennen, R. A.; Hruby, J.; Bonivert, W.

1997-01-01

104

Prediction of etching-shape anomaly due to distortion of ion sheath around a large-scale three-dimensional structure by means of on-wafer monitoring technique and computer simulation  

NASA Astrophysics Data System (ADS)

A system for predicting distortion of a profile during plasma etching was developed. The system consists of a combination of measurement and simulation. An on-wafer sheath-shape sensor for measuring the plasma-sheath parameters (sheath potential and thickness) on the stage of the plasma etcher was developed. The sensor has numerous small electrodes for measuring sheath potential and saturation ion-current density, from which sheath thickness can be calculated. The results of the measurement show reasonable dependence on source power, bias power and pressure. Based on self-consistent calculation of potential distribution and ion- and electron-density distributions, simulation of the sheath potential distribution around an arbitrary 3D structure and the trajectory of incident ions from the plasma to the structure was developed. To confirm the validity of the distortion prediction by comparing it with experimentally measured distortion, silicon trench etching under chlorine inductively coupled plasma (ICP) was performed using a sample with a vertical step. It was found that the etched trench was distorted when the distance from the step was several millimetres or less. The distortion angle was about 20 at maximum. Measurement was performed using the on-wafer sheath-shape sensor in the same plasma condition as the etching. The ion incident angle, calculated as a function of distance from the step, successfully reproduced the experimentally measured angle, indicating that the combination of measurement by the on-wafer sheath-shape sensor and simulation can predict distortion of an etched structure. This prediction system will be useful for designing devices with large-scale 3D structures (such as those in MEMS) and determining the optimum etching conditions to obtain the desired profiles.

Kubota, Tomohiro; Ohtake, Hiroto; Araki, Ryosuke; Yanagisawa, Yuuki; Iwasaki, Takuya; Ono, Kohei; Miwa, Kazuhiro; Samukawa, Seiji

2013-10-01

105

Atomic scale fabrication of dangling bond structures on hydrogen passivated Si(0 0 1) wafers processed and nanopackaged in a clean room environment  

NASA Astrophysics Data System (ADS)

Specific surfaces allowing the ultra-high vacuum (UHV) creation of electronic interconnects and atomic nanostructures are required for the successful development of novel nanoscale electronic devices. Atomically flat and reconstructed Si(0 0 1):H surfaces are serious candidates for that role. In this work such Si:H surfaces were prepared in a cleanroom environment on 200 mm silicon wafers with a hydrogen bake and were subsequently bonded together to ensure the surface protection, and allow their transportation and storage for several months in air. Given the nature of the bonding, which was hydrophobic with weak van der Waals forces, we were then able to de-bond them in UHV. We show that the quality of the de-bonded Si:H surface enables the "at will" construction of sophisticated and complex dangling bond (DB) nanostructures by atomically precise scanning tunneling microscope (STM) tip induced desorption of hydrogen atoms. The DB structures created on slightly doped Si:H samples were characterized by scanning tunneling microscopy and spectroscopy (STM/STS) performed at 4 K. Our results demonstrate that DB nanostructures fabricated on UHV de-bonded Si(0 0 1):H wafers could be directly incorporated in future electronics as interconnects and parts of nanoscale logic circuits.

Kolmer, Marek; Godlewski, Szymon; Zuzak, Rafal; Wojtaszek, Mateusz; Rauer, Caroline; Thuaire, Aurlie; Hartmann, Jean-Michel; Moriceau, Hubert; Joachim, Christian; Szymonski, Marek

2014-01-01

106

Bondability of processed glass wafers  

NASA Astrophysics Data System (ADS)

The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness will result in small real area of contact, and therefore yield voids in the bonding interface. Usually, the root mean square roughness (RMS) or the mean roughness (Ra) are used as parameters to evaluate the wafer bondability. It was found from experience that for a bondable wafer surface the mean roughness must be in the subnanometer range, preferentially less than 0.5 nm. When the surface roughness exceeds a critical value, the wafers will not bond at all. However RMS and Ra were found to be not sufficient for evaluating the wafer bondability. Hence one tried to relate wafer bonding to the spatial spectrum of the wafer surface profile and indeed some empirical relations that have been found. The first, who proposed a theory on the problem of the closing gaps between contacted wafers was Stengl. This gap-closing theory was then further developed by Tong and Gosele. The elastomechanics theory was used to study the balance between the decrease of surface energy due to the bonding and the increase of elastic energy due to the distortion of the wafer. They considered the worst case by assuming that both wafers have a waviness, with a wavelength (lambda) and a height amplitude h, resulting in a gap height of 2h in a head to head position. This theory is simple and can be used in practice, for studying the formation of the voids, or for constructing design rules for the bonding of deliberately structured wafers. But it is insufficient to know what is the real area of contact in the wafer interface after contact at room temperature because the wafer surface always possesses a random distribution of the surface topography. Therefore Gui developed a continuous model on the influence of the surface roughness to wafer bonding, that is based on a statistical surface roughness model Pandraud demonstrated experimentally that direct bonding between processed glass wafers is possible. This result cannot be explained by considering the RMS value of the surfaces only, because the wafers used show a RMS value larger than 1 nm. Based on the approach exposed in reference six, a rigorous analysis of wafer bonding of these processed glass wafers is presented. We will discuss the relation between the bonding process and different waveguide technologies used for implementing optical waveguides into one or both glass wafers, and give examples of optical devices benefiting from such a bonding process.

Pandraud, Gregory; Gui, Cheng-Qun; Pigeon, Florent; Lambeck, Paul V.; Parriaux, Olivier M.

1999-09-01

107

Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.  

PubMed

Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 m thick Si wafers with about 1 m variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale. PMID:24457563

Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

2014-01-01

108

A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications  

NASA Astrophysics Data System (ADS)

A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 C W-1. The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S21) is below 0.4 dB from 0 to 40 GHz and the return loss (S11) is less than -20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S21 shifting caused by the packaging structure is below 0.5 dB, and S11 is less than -10 dB from 8 GHz to 14 GHz.

Geng, Fei; Ding, Xiao-yun; Xu, Gao-wei; Luo, Le

2009-10-01

109

Total x-ray power measurements in the Sandia LIGA program  

Microsoft Academic Search

Total X-ray power measurements using aluminum block calorimetry and other techniques were made at LIGA X-ray scanner synchrotron beamlines located at both the Advanced Light Source (ALS) and the Advanced Photon Source (APS). This block calorimetry work was initially performed on the LIGA beamline 3.3.1 of the ALS to provide experimental checks of predictions of the LEX-D (LIGA Exposure- Development)

Michael E. Malinowski; Aili Ting

2005-01-01

110

Laser wafering for silicon solar  

Microsoft Academic Search

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g\\/W{sub p} (grams\\/peak watt) polysilicon usage

Thomas Aquinas Friedmann; William C. Sweatt; Bradley Howell Jared

2011-01-01

111

High aspect ratio electrostatic micro actuators using LIGA process  

Microsoft Academic Search

High-power electrostatic microactuators using LIGA process have been fabricated. Comb drive type actuators and a wobble motor\\u000a were designed and fabricated. A basic structure of the microactuators was composed of movable and fixed electrodes of Ni,\\u000a a sacrificial layer of SiO2 and a Si substrate, and carried out by one mask process. As design rules, a minimum resist width of

R. Kondo; S. Takimoto; K. Suzuki; S. Sugiyama

2000-01-01

112

Fabrication of microneedle array using inclined LIGA process  

Microsoft Academic Search

We demonstrate a novel fabrication techonology for painless microneedle array with PMMA (PolyMethylMeta Acrylic). In order to make painless transdermal microneedle array for drug injection and blood extraction, inclined LIGA process is applied to demonstrate the fabrication feasibility. This process provides more sharp, robust and high out-of-plane microneedle array structure than conventional silicon based microneedle array. The microneedle proto-types, which

Moon; Sang-Jun; S. S. Lee

2003-01-01

113

Design Study of Wafer Seals for Future Hypersonic Vehicles  

NASA Technical Reports Server (NTRS)

Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2005-01-01

114

Micromanipulator vision for wafer probing  

Microsoft Academic Search

An overview is presented of a micromanipulator vision system for use in automating various functions during the testing of a wafer for semiconductor parameters and inspection of VLSI circuits. It is assumed that the wafer under test is not necessarily in its proper orientation. It is required that certain probes be lowered automatically onto certain pads to inject test vectors

R. V. Dantu; N. J. Dimopoulos; R. V. Patel; A. J. Al-Khalili

1989-01-01

115

Gettering Silicon Wafers with Phosphorus  

NASA Technical Reports Server (NTRS)

Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

Daiello, R. V.

1983-01-01

116

Silicon cast wafer recrystallization for photovoltaic applications  

E-print Network

Current industry-standard methods of manufacturing silicon wafers for photovoltaic (PV) cells define the electrical properties of the wafer in a first step, and then the geometry of the wafer in a subsequent step. The ...

Hantsoo, Eerik T. (Eerik Torm)

2008-01-01

117

Adhesive wafer-to-wafer bonding using contact imprinting  

NASA Astrophysics Data System (ADS)

The present work proposes an adhesive bonding technique, at wafer level, using SU-8 negative photoresist as intermediate layer. The adhesive was selective imprint on one of the bonding surface. The main applications are in microfluidic area where a low temperature bonding is required. The method consists of three major steps. First the adhesive layer is deposited on one of the bonding surface by contact imprinting from a dummy wafer where the SU-8 photoresist was initially spun, or from a Teflon cylinder. Second, the wafers to be bonded are placed in contact and aligned. In the last step, the bonding process is performed at temperatures between 100C and 200C, a pressure of 1000 N in vacuum on a classical wafer bonding system. The results indicate a low stress value induced by the bonding technique. In the same time the process presents a high yield: 95-100%. The technique was successfully tested in the fabrication process of a dielectrophoretic device.

Yu, Liming; Pang, Ah Ju; Chen, Bangtao; Tay, Francis E. H.; Iliescu, Ciprian

2006-12-01

118

Enhanced adhesion for LIGA microfabrication by using a buffer layer  

DOEpatents

The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

Bajikar, Sateesh S. (San Jose, CA); De Carlo, Francesco (Darien, IL); Song, Joshua J. (Naperville, IL)

2001-01-01

119

MEMS Wafer-level Packaging Technology Using LTCC Wafer  

NASA Astrophysics Data System (ADS)

This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature co-fired ceramic (LTCC) wafer, in which multi-layer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of micro electro mechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (-40C30min/+125C30min) by diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection methods; The electrical connection is established by porous Au bumps, which are a part of Au vias exposed in wet-etched cavities on the LTCC wafer. 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

Mohri, Mamoru; Esashi, Masayoshi; Tanaka, Shuji

120

Wafer-Level Thermocompression Bonds  

E-print Network

Thermocompression bonding of gold is a promising technique for achieving low temperature, wafer-level bonding without the application of an electric field or complicated pre-bond cleaning procedure. The presence of a ductile ...

Tsau, Christine H.

121

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.  

PubMed

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

2014-08-15

122

Wafer handling and placement tool  

DOEpatents

A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

Witherspoon, Linda L. (22 Cottonwood La., Los Lunas, NM 87031)

1988-01-05

123

Characterization of Sidewall and Planar Surfaces of Electroformed LIGA Parts  

SciTech Connect

The nature of surfaces and the way they interact with each other during sliding contact can have a direct bearing on the performance of a microelectromechanical (MEMS) device. Therefore, a study was undertaken to characterize the surfaces of LIGA fabricated Ni and Cu components. Sidewall and planar surfaces were examined by scanning electron microscopy (SEM) and atomic force microscopy (AFM). Surface roughness was quantified using the AFM. Post-processing (e.g. lapping, removal of polymer film) can profoundly influence the morphology of LIGA components. Edge rounding and smearing of ductile materials during lapping can result in undesirable sidewall morphologies. By judicious selection of AFM scan sizes, the native roughness ({approximately}10 nm RMS) can be distinguished from that arising due to post processing, e.g. scratches, debris, polymer films. While certain processing effects on morphology such as those due to lapping or release etch can be controlled, the true side wall morphology appears to be governed by the morphology of the polymer mold or by the electroforming process itself, and may be much less amenable to modification.

PRASAD,SOMURI V.; HALL,AARON C.; DUGGER,MICHAEL T.

2000-10-01

124

GEM-type detectors using LIGA and etchable glass technologies  

SciTech Connect

Gas electron multipliers (GEMS) have been made by a deep X-ray lithography technique (LIGA process) using synchrotron radiation on polymethylmethacrylate (PMMA) and by UV processes using a UV etchable glass. Gain, stability and rate capability for these detectors are described.The LIGA detectors described consist of PMMA sheets of various thicknesses, 125mm to 350mm, and have 150mm x 150mm square holes spaced with a pitch of 300mm. Thin copper electrodes are plated on the top and bottom surfaces using a Damascene method, followed by electroless plating of the copper onto a palladium-tin base layer. For various thicknesses of PMMA measurements have been made of absolute gain vs. voltage, time stability of gain, and rate capability. The operating gas mixture was usually Ar/CO2 (70/30) gas, but some tests were also done using P10 gas. We also made GEM-like detectors using the UV etchable glass called Foturan, patterned by exposure to UV light and subsequent etching. A few measurements using these detectors will be reported, including avalanche gain and time stability.

Ahn, S.K.; Kim, J.G.; Perez-Mendez, V.; Chang, S.; Jackson, K.H.; Kadyk, J.A.; Wenzel, W.A.; Cho, G.

2001-11-02

125

Development of Megasonic cleaning for silicon wafers. Final report  

SciTech Connect

The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

Mayer, A.

1980-09-01

126

LIGA-based microsystem manufacturing:the electrochemistry of through-mold depostion and material properties.  

SciTech Connect

The report presented below is to appear in ''Electrochemistry at the Nanoscale'', Patrik Schmuki, Ed. Springer-Verlag, (ca. 2005). The history of the LIGA process, used for fabricating dimensional precise structures for microsystem applications, is briefly reviewed, as are the basic elements of the technology. The principal focus however, is on the unique aspects of the electrochemistry of LIGA through-mask metal deposition and the generation of the fine and uniform microstructures necessary to ensure proper functionality of LIGA components. We draw from both previously published work by external researchers in the field as well as from published and unpublished studies from within Sandia.

Kelly, James J. (Sandia National Laboratories, Livermore, CA); Goods, Steven Howard (Sandia National Laboratories, Livermore, CA)

2005-06-01

127

Nano-particle laser removal from silicon wafers  

NASA Astrophysics Data System (ADS)

A laser shock cleaning (LSC) technique as a new dry cleaning methodology has been applied to remove micro and nano-scale inorganic particulate contaminants. Shock wave is generated in the air just above the wafer surface by focusing intensive laser beam. The velocity of shock wave can be controlled to 10,000 m/sec. The sub-micron sized silica and alumina particles are attempted to remove from bare silicon wafer surfaces. More than 95% of removal efficiency of the both particles are carried out by the laser-induced airborne shock waves. In the final, a removal of nano-scale slurry particles from real patterned wafers are successfully demonstrated by LSC after chemical-mechanical polishing (CMP) process.

Lee, J. M.; Cho, S. H.; Kim, T. H.; Park, Jin-Goo; Busnaina, Ahmed A.

2003-11-01

128

Wafer Nanotopography Effects on CMP: Experimental Validation of Modeling Methods , Duane S. Boning1  

E-print Network

length scale on unpatterned silicon wafers. Chemical mechanical polishing (CMP) of de- posited or grown films (e.g., oxide or nitride) on such wafers can generate undesirable film thin- ning which can into thin film thickness variations. In addition to presenting these experimental results, modeling

Boning, Duane S.

129

Wafer characteristics via reflectometry and wafer processing apparatus and method  

DOEpatents

An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

Sopori, Bhushan L. (Denver, CO)

2007-07-03

130

Selective area growth of InP in shallow trench isolation on large scale Si(001) wafer using defect confinement technique  

NASA Astrophysics Data System (ADS)

Heterogeneous integration of III-V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III-V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III-V virtual substrates on large-scale Si substrates.

Merckling, C.; Waldron, N.; Jiang, S.; Guo, W.; Richard, O.; Douhard, B.; Moussa, A.; Vanhaeren, D.; Bender, H.; Collaert, N.; Heyns, M.; Thean, A.; Caymax, M.; Vandervorst, W.

2013-07-01

131

Injection-moulded fibre ribbon connectors for parallel optical links fabricated by the LIGA technique  

Microsoft Academic Search

Using the LIGA technique prototypes of twelve-fibre-wide ribbon connector ferrules have been developed that provide low-loss physical-contact multimode connections for parallel interfaces. The ferrules are injection moulded and the modular mould insert has been fabricated by means of microtechnology (LIGA) and electro-discharge machining. After assembling, mated couples of these ferrules show average insertion loss values of 0.35 dB and have

Karlheinz Dunkel; Hans-Dieter Bauer; Wolfgang Ehrfeld; Jens Hofeld; Lutz Weber; Gnter Hrcher; Gottfried Mller

1998-01-01

132

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

Vosen, S.R.

1999-07-27

133

Heating device for semiconductor wafers  

DOEpatents

An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

Vosen, Steven R. (Berkeley, CA)

1999-01-01

134

Acoustic emission monitoring during laser shock cleaning of silicon wafers  

Microsoft Academic Search

A laser shock cleaning is a new dry cleaning methodology for the effective removal of submicron sized particles from solid surfaces. This technique uses a plasma shock wave produced by laser-induced air breakdown, which has applied to remove nano-scale silica particles from silicon wafer surfaces in this work. In order to characterize the laser shock cleaning process, acoustic waves generated

T. Kim; J. M. Lee; S. H. Cho; T. H. Kim

2005-01-01

135

Silicon Wafer Processing Dr. Seth P. Bates  

E-print Network

Silicon Wafer Processing Dr. Seth P. Bates Applied Materials Summer, 2000 Objective To provide from blank silicon wafers. Goals The Transfer Plan provides a curriculum covering the process of manufacturing integrated circuits from the silicon wafer blanks, using the equipment manufactured by Applied

Colton, Jonathan S.

136

APPLIED PHYSICS REVIEWSFOCUSED REVIEW Adhesive wafer bonding  

E-print Network

APPLIED PHYSICS REVIEWS­FOCUSED REVIEW Adhesive wafer bonding F. Niklausa Microsystem Technology 9 February 2006 Wafer bonding with intermediate polymer adhesives is an important fabrication-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive

Salama, Khaled

137

NREL Core Program; Session: Wafer Silicon (Presentation)  

SciTech Connect

This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

Wang, Q.

2008-04-01

138

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress  

NASA Astrophysics Data System (ADS)

Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. Although uniform process-induced stress is easily corrected, nonuniform stress across the wafer is much more problematic, often resulting in noncorrectable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such nonuniform stress-induced wafer distortions. Wafer geometry data can be related to in-plane distortion of the wafer pulled flat by an exposure tool vacuum chuck, which in turn relates to overlay error. This paper will explore the relationship between wafer geometry and overlay error by the use of silicon test wafers with deliberate stress variations, i.e., engineered stress monitor (ESM) wafers. A process will be described that allows the creation of ESM wafers with nonuniform stress and includes many thousands of overlay targets for a detailed characterization of each wafer. Because the spatial character of the stress variation is easily changed, ESM wafers constitute a versatile platform for exploring nonuniform stress. We have fabricated ESM wafers of several different types, e.g., wafers where the center area has much higher stress than the outside area. Wafer geometry is measured with an optical metrology tool. After fabrication of the ESM wafers including alignment marks and first level overlay targets etched into the wafer, we expose a second level resist pattern designed to overlay with the etched targets. After resist patterning, relative overlay error is measured using standard optical methods. An innovative metric from the wafer geometry measurements is able to predict the process-induced overlay error. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

Brunner, Timothy A.; Menon, Vinayan C.; Wong, Cheuk Wun; Gluschenkov, Oleg; Belyansky, Michael P.; Felix, Nelson M.; Ausschnitt, Christopher P.; Vukkadala, Pradeep; Veeraraghavan, Sathish; Sinha, Jaydeep K.

2013-10-01

139

Wafering economies for industrialization from a wafer manufacturer's viewpoint  

NASA Technical Reports Server (NTRS)

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

140

Deposition uniformity inspection in IC wafer surface  

NASA Astrophysics Data System (ADS)

This paper focuses on the task of automatic visual inspection of color uniformity on the surface of integrated circuits (IC) wafers arising from the layering process. The oxide thickness uniformity within a given wafer with a desired target thickness is of great importance for modern semiconductor circuits with small oxide thickness. The non-uniform chemical vapor deposition (CVD) on a wafer surface will proceed to fail testing in Wafer Acceptance Test (WAT). Early detection of non-uniform deposition in a wafer surface can reduce material waste and improve production yields. The fastest and most low-priced inspection method is a machine vision-based inspection system. In this paper, the proposed visual inspection system is based on the color representations which were reflected from wafer surface. The regions of non-uniform deposition present different colors from the uniform background in a wafer surface. The proposed inspection technique first learns the color data via color space transformation from uniform deposition of normal wafer surfaces. The individual small region statistical comparison scheme then proceeds to the testing wafers. Experimental results show that the proposed method can effectively detect the non-uniform deposition regions on the wafer surface. The inspection time of the deposited wafers is quite compatible with the atmospheric pressure CVD time.

Li, W. C.; Lin, Y. T.; Jeng, J. J.; Chang, C. L.

2014-03-01

141

The LIGA technique-A novel concept for microstructures and the combination with Si-technologies by injection molding  

Microsoft Academic Search

The LIGA technique originally developed to fabricate separation nozzles for the enrichment of uranium has been expanded into a universal technology for the fabrication of microstructures with high aspect ratio and free lateral shaping. The LIGA process consists of three basic process steps: deep-etch lithography by means of synchrotron radiation, electroforming, and plastic molding. The choice of materials ranges from

W. Menz; W. Bacher; M. Harmening; A. Michel

1991-01-01

142

Wafer bonding for three dimensional (3D) integration  

NASA Astrophysics Data System (ADS)

Wafer scale 3D integration is recognized as an emerging technology to increase the performance of ICs. When bonding with processed ICs, the bonding process must be compatible with IC back-end processing. The fraction of bonded area was examined by optical inspection and BCB was selected as the baseline glue after achieving reproducible void-free bonding. Bond strength at the glue interface of bonded wafers was quantified by four-point bending. Using four point bending, the following effects of BCB glue on the bonding integrity were evaluated; (1) employment of adhesion promoter, (2) BCB glue thickness and (3) material stack. When the adhesion promoter is used, bond strength increases at both BCB bonds of 2.6 mum and 0.4 mum. These results also demonstrate that BCB glue thickness affects the bond strength at the glue interface with thicker glue layers corresponding to higher bond strength. The decrease in bond strength observed for thin BCB is due to a decrease of plastic dissipation energy, Gplastic, which is proportional to BCB thickness. In both bonded wafer pairs that include a PECVD oxide deposited silicon wafer and a glass wafer, bond strengths are linearly proportional to BCB thickness. With these results, the relationship between Gplastic , and bond breaking energy, Gtip, and BCB thickness, t is observed to be Gplastic ? 0.3 Gtip t. The effects of thermal cycling on bond strength and residual stress at the interface between BCB and a PECVD oxide, and the thermal stability of BCB were evaluated by four point bending and wafer curvature measurements. Stress relaxation of the PECVD oxide layer during thermal cycling leads to a decrease in the deformation energy due to residual stress, G residual, and to an increase in bond strength. In thermal cycling performed at temperatures of 350 and 400C, it is observed that the relaxation of residual stress occurs predominantly during the first thermal cycle. Conclusively, the BCB process for wafer-to-wafer bonding applications is stabilized after four cycles at a temperature of 400C. Thermal cycling performed at a temperature 450C leads to cohesive failure within the BCB layer with low bond strength (<0.5 J/m2).

Kwon, Yongchai

2003-10-01

143

Macroporous-based micromachining on full wafers  

Microsoft Academic Search

This paper reports on a technique of macroporous-based micromachining for full wafers. A 3.6kW xenon lamp of whose intensity can be varied is employed to generate electronic holes during the etching. In order to apply a uniform electric field to whole 3in. wafer, a mesh electrode is formed on the backside of the wafer after implantation of an n+ layer.

H. Ohji; S. Izuo; P. J. French; K. Tsutsumi

2001-01-01

144

Strength of Silicon Wafers: Fracture Mechanics Approach  

SciTech Connect

This paper describes a model to predict mechanical strength distribution of silicon wafers. A generalized expression, based on a multimodal Weibull distribution, is proposed to describe the strength of a brittle material with surface, edge, and bulk flaws. The specific case of a cast, unpolished photovoltaic (PV) wafer is further analyzed. Assuming that surface microcracks constitute the dominant mechanism of wafer breakage, this model predicts the strength distribution of PV silicon that matches well the experimental results available in the literature.

Rupnowski, P.; Sopori, B.

2009-01-01

145

Effect of Wafer Bow and Etch Patterns in Direct Wafer Bonding  

E-print Network

Direct wafer bonding has been identified as an en-abling technology for microelectromechanical systems (MEMS). As the complexity of devices increase and the bonding of multiple patterned wafers is required, there is a need ...

Spearing, S. Mark

146

Material electronic quality specification factors for polycrystalline silicon wafers  

SciTech Connect

The authors present a scheme to monitor quality (diffusion length) improvement, or upgrading, for inhomogeneous polycrystalline silicon wafers. Statistically-based parameters and scaling factors are defined to represent individual regions of varying diffusion length, and are used to follow material electronic property changes from crystal growth through upgrading steps, including phosphorus diffusion, hydrogen passivation and aluminum firing. Measurements of diffusion length using two different methods, SPV and IRPC are used.

Bailey, J. [Univ. of California, Berkeley, CA (United States). Dept. of Materials Science and Mineral Engineering; Kalejs, J.P.; Keaveny, C. [ASE Americas, Billerica, MA (United States)

1994-12-31

147

Stress Voiding During Wafer Processing  

SciTech Connect

Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

Yost, F.G.

1999-03-01

148

Combustion synthesis of LiGa and LiAl intermetallic alloys  

NASA Astrophysics Data System (ADS)

LiAl and LiGa intermetallic alloys have been synthesized using the simultaneous combustion mode of combustion synthesis. LiAl intermetallic is potentially suitable as a temper alloy for producing aluminum-lithium alloys and as an anodic material for high-energy batteries. LiGa can be used as a reduction alloy to recover valuable reactive metals from molten salt effluent in actinide recovery technology. The effects of particle size, preignition heating rate, and theoretical green density on the ignition and combustion temperatures have been studied in an effort to more precisely control the synthesis reaction of these intermetallics. A lithium particle size of -20 /xm was found to be suitable when the combustion synthesis reaction was conducted at a high heating rate (>1.0 cC/s) and a moderate green density (55 to 65 pct theoretical). Preignition diffusion is suggested as the cause for low exothermic heat release at high green densities. A combustion temperature above the melting point of the LiGa intermetallic compound can be achieved under optimized conditions. However, the exothermicity and, therefore, the adiabatic temperature is too low for either LiAl or LiGa to be produced by the propagating mode of combustion synthesis.

Pritchett, S. R.; Mishra, B.; Moore, J. J.

1995-02-01

149

Fabrication of 3D High Aspect Ratio Micro-Fluidic Components Using Laser Machining and LIGA  

Microsoft Academic Search

The fabrication of a microdevice often requires the combination of several techniques in its processing sequence. This allows for the benefits of individual techniques to fabricate an optimised product. In this paper, we present a complementary process involving laser micromachining and LIGA for the fabrication of a microflask. Examples of the benefits of this tandem include the removal of resist

Richard L. Barber; Muralidhar Ghantasala; Terence W. Turney; Erol Harvey

150

Electrostatic Wafer Chuck for Electron Beam Microfabrication  

Microsoft Academic Search

Vacuum wafer chucks are useless for electron beam microfabrication. An analysis of the required electrostatic forces and frequency response of a specimen wafer on a field plate is made. An experimental electrostatic chuck and its high voltage square wave power supply have been fabricated. Full clamping action has been provided by electrostatic pressures of 1?6 atm, and 1 atm pressures

George A. Wardly

1973-01-01

151

Total x-ray power measurements in the Sandia LIGA program.  

SciTech Connect

Total X-ray power measurements using aluminum block calorimetry and other techniques were made at LIGA X-ray scanner synchrotron beamlines located at both the Advanced Light Source (ALS) and the Advanced Photon Source (APS). This block calorimetry work was initially performed on the LIGA beamline 3.3.1 of the ALS to provide experimental checks of predictions of the LEX-D (LIGA Exposure- Development) code for LIGA X-ray exposures, version 7.56, the version of the code in use at the time calorimetry was done. These experiments showed that it was necessary to use bend magnet field strengths and electron storage ring energies different from the default values originally in the code in order to obtain good agreement between experiment and theory. The results indicated that agreement between LEX-D predictions and experiment could be as good as 5% only if (1) more accurate values of the ring energies, (2) local values of the magnet field at the beamline source point, and (3) the NIST database for X-ray/materials interactions were used as code inputs. These local magnetic field value and accurate ring energies, together with NIST database, are now defaults in the newest release of LEX-D, version 7.61. Three dimensional simulations of the temperature distributions in the aluminum calorimeter block for a typical ALS power measurement were made with the ABAQUS code and found to be in good agreement with the experimental temperature data. As an application of the block calorimetry technique, the X-ray power exiting the mirror in place at a LIGA scanner located at the APS beamline 10 BM was measured with a calorimeter similar to the one used at the ALS. The overall results at the APS demonstrated the utility of calorimetry in helping to characterize the total X-ray power in LIGA beamlines. In addition to the block calorimetry work at the ALS and APS, a preliminary comparison of the use of heat flux sensors, photodiodes and modified beam calorimeters as total X-ray power monitors was made at the ALS, beamline 3.3.1. This work showed that a modification of a commercially available, heat flux sensor could result in a simple, direct reading beam power meter that could be a useful for monitoring total X-ray power in Sandia's LIGA exposure stations at the ALS, APS and Stanford Synchrotron Radiation Laboratory (SSRL).

Malinowski, Michael E. (Sandia National Laboratories, Livermore, CA); Ting, Aili (Sandia National Laboratories, Livermore, CA)

2005-08-01

152

Methane production using resin-wafer electrodeionization  

SciTech Connect

The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

2014-03-25

153

Adhesive wafer bonding using a molded thick benzocyclobutene layer for wafer-level integration of MEMS and LSI  

NASA Astrophysics Data System (ADS)

This paper describes a wafer bonding process using a 50 m thick benzocyclobutene (BCB) layer which has vias and metal electrodes. The vias were fabricated by molding BCB using a glass mold. During the molding, worm-like voids grew between BCB and the mold due to the shrinkage of polymerizing BCB. They were completely removed by subsequent reflowing in N2. After patterning Al on the reflowed BCB for the electrodes and via connections, bonding with a glass substrate was performed. Voidless bonding without damage in the vias and electrodes was achieved. Through the process, the control of the polymerization degree of BCB is important, and thus the polymerization degree was evaluated by Fourier transform infrared spectroscopy. The developed process is useful for the wafer-bonding-based integration of different devices, e.g. micro electro mechanical systems and large-scale integrated circuits.

Makihata, M.; Tanaka, S.; Muroyama, M.; Matsuzaki, S.; Yamada, H.; Nakayama, T.; Yamaguchi, U.; Mima, K.; Nonomura, Y.; Fujiyoshi, M.; Esashi, M.

2011-08-01

154

Development of megasonic cleaning for silicon wafers  

NASA Technical Reports Server (NTRS)

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Mayer, A.

1980-01-01

155

Three wafer stacking for 3D integration.  

SciTech Connect

Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

2011-11-01

156

The Imaging Properties of a Silicon Wafer X-Ray Telescope  

NASA Technical Reports Server (NTRS)

Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

1994-01-01

157

Everything Wafers: A Guide to Semiconductor Substrates  

NSDL National Science Digital Library

This website contains information on characteristics and properties of semiconductor wafers. Topics include types of substrates, process dependent characteristics, properties of semiconductors, cleaving, etching and other topics, along with related terms and links.

158

Modelling deformation and fracture in confectionery wafers  

NASA Astrophysics Data System (ADS)

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

2015-01-01

159

Grinding characteristics of micro-abrasive pellet tools fabricated by a LIGA-like process  

Microsoft Academic Search

The purpose of this paper was to investigate the wearing and grinding characteristics of the micro-abrasive pellet tools with 46?m diamond particles fabricated by a LIGA-like process that has micro-lithography with photoresist mold and nickel\\/diamond composite electroforming. The results showed that when the micro-pellet tool containing partial resist joint with a root on the substrate was designed and fabricated, the

S. Y. Luo; T. H. Yu; C. Y. Liu; M. H. Chen

2009-01-01

160

A Transdermal Drug Delivery System Based on LIGA Technology and Soft Lithography  

NASA Astrophysics Data System (ADS)

This report presents a transdermal drug delivery system based on LIGA fabricated microparts. It is a portable device combining a magnetically actuated micro gear pump with a microneedle array. The fluidic behaviour of the system is analyzed in order to predict its performance according to the dimension of the microparts and then compared to experimental data. The manufacturing process of both micropump and microneedle array are described.

Matteucci, Marco; Perennes, Frederic; Marmiroli, Benedetta; Di Fabrizio, Enzo

2007-01-01

161

Diamond-like nanocomposite coatings for LIGA-fabricated nickel alloy parts.  

SciTech Connect

A commercial plasma enhanced chemical vapor deposition (PECVD) technique with planetary substrate rotation was used to apply a thin (200-400 nm thick) conformal diamond-like carbon (DLC) coating (known as a diamond-like nanocomposite (DLN)) on LIGA fabricated Ni-Mn alloy parts. The PECVD technique is known to overcome the drawbacks associated with the line-of-sight nature of physical vapor deposition (PVD) and substrate heating inherent with traditional chemical vapor deposition (CVD). The purpose of the present study is to characterize the coverage, adhesion, and tribological (friction and wear) behavior of DLN coatings applied to planar and sidewall surfaces of small featured LIGA Ni-Mn fabricated parts, e.g. 280 {micro}m thick sidewalls. Friction and wear tests were performed in dry nitrogen, dry air, and air with 50% RH at Hertzian contact pressures ranging from 0.3 to 0.6 GPa. The friction coefficient of bare Ni-Mn alloy was determined to be 0.9. In contrast, low friction coefficients ({approx}0.02 in dry nitrogen and {approx}0.2 in 50% RH air) and minimal amount of wear were exhibited for the DLN coated LIGA Ni-Mn alloy parts and test coupons. This behavior was due to the ability of the coating to transfer to the rubbing counterface providing low interfacial shear at the sliding contact; resultantly, coating one surface was adequate for low friction and wear. In addition, a 30 nm thick titanium bond layer was determined to be necessary for good adhesion of DLN coating to Ni-Mn alloy substrates. Raman spectroscopy and cross-sectional SEM with energy dispersive x-ray analysis revealed that the DLN coatings deposited by the PECVD with planetary substrate rotation covered both the planar and sidewall surfaces of LIGA fabricated parts, as well as narrow holes of 300 {micro}m (0.012 inch) diameter.

Prasad, Somuri V.; Scharf, Thomas W.

2005-03-01

162

Porous solid ion exchange wafer for immobilizing biomolecules  

SciTech Connect

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

Arora, Michelle B. (Woodridge, IL); Hestekin, Jamie A. (Morton Grove, IL); Lin, YuPo J. (Naperville, IL); St. Martin, Edward J. (Libertyville, IL); Snyder, Seth W. (Lincolnwood, IL)

2007-12-11

163

Wafer-size free-standing single-crystalline graphene device arrays  

NASA Astrophysics Data System (ADS)

We report an approach of wafer-scale addressable single-crystalline graphene (SCG) arrays growth by using pre-patterned seeds to control the nucleation. The growth mechanism and superb properties of SCG were studied. Large array of free-standing SCG devices were realized. Characterization of SCG as nano switches shows excellent performance with life time (>22 000 times) two orders longer than that of other graphene nano switches reported so far. This work not only shows the possibility of producing wafer-scale high quality SCG device arrays but also explores the superb performance of SCG as nano devices.

Li, Peng; Jing, Gaoshan; Zhang, Bo; Sando, Shota; Cui, Tianhong

2014-08-01

164

Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics  

SciTech Connect

Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020from $0.15 per kilowatt hour to less than $0.07. 1366s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with todays state-of-the-art technologies. 1366s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366s technology, the cost of silicon wafers could be reduced by 80%.

None

2010-01-15

165

Wafer-fused semiconductor radiation detector  

DOEpatents

Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

Lee, Edwin Y. (Livermore, CA); James, Ralph B. (Livermore, CA)

2002-01-01

166

Laser furnace and method for zone refining of semiconductor wafers  

NASA Technical Reports Server (NTRS)

A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

1988-01-01

167

Biocompatible "click" wafer bonding for microfluidic devices.  

PubMed

We introduce a novel dry wafer bonding concept designed for permanent attachment of micromolded polymer structures to surface functionalized silicon substrates. The method, designed for simultaneous fabrication of many lab-on-chip devices, utilizes a chemically reactive polymer microfluidic structure, which rapidly bonds to a functionalized substrate via"click" chemistry reactions. The microfluidic structure consists of an off-stoichiometry thiol-ene (OSTE) polymer with a very high density of surface bound thiol groups and the substrate is a silicon wafer that has been functionalized with common bio-linker molecules. We demonstrate here void free, and low temperature (< 37 C) bonding of a batch of OSTE microfluidic layers to a silane functionalized silicon wafer. PMID:22760578

Saharil, Farizah; Carlborg, Carl Fredrik; Haraldsson, Tommy; van der Wijngaart, Wouter

2012-09-01

168

Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage  

NASA Astrophysics Data System (ADS)

This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ?50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (? 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu-precipitates (upto 50 nm) compresses Si-lattice to facilitate Si-XII/III

Kulshreshtha, Prashant Kumar

169

Damage Identification in Aging Aircraft Structures with Piezoelectric Wafer Active Sensors  

E-print Network

) reduces total life cycle cost and increases safety and availability of military and commercial aircraft the advancing crack tip. For commercial aircraft, NASA's Aviation Safety Program considers a large-scale deployDamage Identification in Aging Aircraft Structures with Piezoelectric Wafer Active Sensors VICTOR

Giurgiutiu, Victor

170

Geometry control of recrystallized silicon wafers for solar applications  

E-print Network

The cost of manufacturing crystalline silicon wafers for use in solar cells can be reduced by eliminating the waste streams caused by sawing ingots into individual wafers. Professor Emanuel Sachs has developed a new method ...

Ruggiero, Christopher W

2009-01-01

171

Bubble-domain circuit wafer evaluation coil set  

NASA Technical Reports Server (NTRS)

Coil structures have been designed to permit nondestructive testing of bubble wafers. Wafers can be electrically or optically inspected and operated from quasi-static frequency to maximum device operating frequency.

Chen, T. T.; Williams, J. L.

1975-01-01

172

Wafer-level package interconnect options  

Microsoft Academic Search

As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare

Jayaprakash Balachandran; Steven Brebels; Geert Carchon; Maarten Kuijk; Walter De Raedt; Bart K. J. C. Nauwelaers; Eric Beyne

2006-01-01

173

Wafer Backside Anisotropic Wet Etching of Silicon  

NSDL National Science Digital Library

This animation, created by Southwest Center for Microsystems Education (SCME), illustrates how the "wafer backside anisotropic wet etching of silicon is used to form the pressure sensor chamber." Further information and resources can be found on the SCME website.

2014-07-30

174

Silicon waveguides produced by wafer bonding  

SciTech Connect

X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 {mu}m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides to excite single guided modes at typical x-ray energies.

Poulsen, M.; Jensen, F.; Bunk, O.; Feidenhans'l, R.; Breiby, D.W. [Department of Micro and Nanotechnology, Technical University of Denmark, Oersteds Plads, DK-2800 Kgs. Lyngby (Denmark) and Materials Research Department, Risoe National Laboratory, Frederiksborgvej 399, DK-4000 Roskilde (Denmark); DANCHIP, Technical University of Denmark, Oersteds Plads, DK-2800 Kgs. Lyngby (Denmark); Materials Research Department, Risoe National Laboratory, Frederiksborgvej 399, DK-4000 Roskilde (Denmark); Danish Polymer Centre, Risoe National Laboratory, Frederiksborgvej 399, DK-4000 Roskilde (Denmark)

2005-12-26

175

REDUCING MANUFACTURING CYCLE TIME OF WAFER FAB WITH SIMULATION  

Microsoft Academic Search

Wafer Fabrication process is the starting point of making any computers or integrated circuit (IC) products. It is complex. On average, a wafer needs to go through more than 300 operational steps before shipping for assembly and test. It requires high investment. This makes the control of wafer fab very challenging and the results can be very encouraging. A simulation

Giam Kim Toh; Ui Wei Teck; Alimin Lie; George Sun; Wang Ming; Kelvin Kok

176

Strength of Si Wafers with Microcracks: A Theoretical Model (Poster)  

SciTech Connect

A new analytical expression that takes into account the surface, edge, and bulk properties of a wafer has been proposed to describe the strength of the brittle materials. A new proposed fracture-mechanics numerical simulation successfully predicted the strength of the cast silicon wafers. It has been shown that the predicted wafer strength distribution agrees well with the available experimental results.

Rupnowski, P.; Sopori, B.

2008-05-01

177

Defect detection in patterned wafers using multichannel Scanning Electron Microscope  

E-print Network

Defect detection in patterned wafers using multichannel Scanning Electron Microscope Maria Zontak using Scanning Electron Microscope (SEM) images. A wafer is irradiated with a focused beam of electrons s t r a c t Recent computational methods of wafer defect detection often inspect Scanning Electron

Cohen, Israel

178

Optical Cluster Eye fabricated on wafer-level.  

PubMed

Wafer-level optics is considered as a cost-effective approach to miniaturized cameras, because fabrication and assembly are carried out for thousands of lenses in parallel. However, in most cases the micro-optical fabrication process is not mature enough to reach the required accuracy of the optical elements, which may have complex profiles and sags in the mm-scale. Contrary, the creation of microlens arrays is well controllable so that we propose a multi aperture system called "Optical Cluster Eye" which is based on conventional micro-optical fabrication techniques. The proposed multi aperture camera consists of many optical channels each transmitting a segment of the whole field of view. The design of the system provides the stitching of the partial images, so that a seamless image is formed and a commercially available image sensor can be used. The system can be fabricated on wafer-level with high yield due to small aperture diameters and low sags. The realized optics has a lateral size of 2.2 2.9 mm2, a total track length of 1.86 mm, and captures images at VGA video resolution. PMID:21935117

Meyer, Julia; Brckner, Andreas; Leitel, Robert; Dannberg, Peter; Bruer, Andreas; Tnnermann, Andreas

2011-08-29

179

Design of electrostatically levitated micromachined rotational gyroscope based on UV-LIGA technology  

NASA Astrophysics Data System (ADS)

The prevailing micromachined vibratory gyroscope typically has a proof mass connected to the substrate by a mechanical suspension system, which makes it face a tough challenge to achieve tactical or inertial grade performance levels. With a levitated rotor as the proof mass, a micromachined rotational gyroscope will potentially have higher performance than vibratory gyroscope. Besides working as a moment rebalance dual-axis gyroscope, the micromachined rotational gyroscope based on a levitated rotor can simultaneously work as a force balance tri-axis accelerometer. Micromachined rotational gyroscope based on an electrostatically levitated silicon micromachined rotor has been notably developed. In this paper, factors in designing a rotational gyro/accelerometer based on an electrostatically levitated disc-like rotor, including gyroscopic action of micro rotor, methods of stable levitation, micro displacement detection and control, rotation drive and speed control, vacuum packaging and microfabrication, are comprehensively considered. Hence a design of rotational gyro/accelerometer with an electroforming nickel rotor employing low cost UV-LIGA technology is presented. In this design, a wheel-like flat rotor is proposed and its basic dimensions, diameter and thickness, are estimated according to the required loading capability. Finally, its micromachining methods based on UV-LIGA technology and assembly technology are discussed.

Cui, Feng; Chen, Wenyuan; Su, Yufeng; Zhang, Weiping; Zhao, Xiaolin

2004-12-01

180

Combination of a fluidic micro-oscillator and micro-actuator in LIGA-technique for medical application  

Microsoft Academic Search

In this paper for the first time a modular built dynamic microsystem consisting of a combination of two separately fully functional fluidic devices fabricated by the LIGA-technique is presented. One of the two devices is a fluidic micro-oscillator, which needs only one fluid supply to generate an oscillating fluid jet at its two output ports. The other device is a

Ute Gebhard; Herbert Hein; E. Just; P. Ruther

1997-01-01

181

Compliant membranes improve resolution in full-wafer micro/nanostencil lithography.  

PubMed

This work reports on a considerable resolution improvement of micro/nanostencil lithography when applied on full-wafer scale by using compliant membranes to reduce gap-induced pattern blurring. Silicon nitride (SiN) membranes are mechanically decoupled from a rigid silicon (Si) frame by means of four compliant, protruding cantilevers. When pressing the stencil into contact with a surface to be patterned, the membranes thus adapt to the surface independently and reduce the gap between the membrane and the substrate even over large, uneven surfaces. Finite element modeling (FEM) simulations show that compliant membranes can deflect vertically 40 ?m which is a typical maximal non-planarity observed in standard Si wafers, due to polishing. Microapertures in the stencil membrane are defined by UV lithography and nanoapertures, down to 200 nm in diameter, using focused ion beam (FIB). A thin aluminium (Al) layer is deposited through both compliant and non-compliant membranes on a Si wafer, for comparison. The blurring in the case of compliant membranes is up to 95% reduced on full-wafer scale compared to standard (non-compliant) membranes. PMID:22170588

Sidler, Katrin; Villanueva, Luis G; Vazquez-Mena, Oscar; Savu, Veronica; Brugger, Juergen

2012-02-01

182

Optical cavity furnace for semiconductor wafer processing  

DOEpatents

An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

Sopori, Bhushan L.

2014-08-05

183

Devices using resin wafers and applications thereof  

DOEpatents

Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL); St. Martin, Edward (Libertyville, IL); Arora, Michelle (Woodridge, IL); de la Garza, Linda (Woodridge, IL)

2009-03-24

184

Etching methodologies in ?111?-oriented silicon wafers  

Microsoft Academic Search

New methodologies in anisotropic wet-chemical etching of ?111?-oriented silicon, allowing useful process designs combined with smart mask-to-crystal-orientation-alignment are presented in this paper. The described methods yield smooth surfaces as well as high-quality plan-parallel beams and membranes. With a combination of pre-etching and wall passivation, structures can be etched at different depths in a wafer. Designs, using the ?111?-crystal orientation, supplemented

R. Edwin Oosterbroek; J. W. Berenschot; H. V. Jansen; A. J. Nijdam; G. Pandraud; A. van den Berg; M. C. Elwenspoek

2000-01-01

185

Precipitating Chromium Impurities in Silicon Wafers  

NASA Technical Reports Server (NTRS)

Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

Salama, A. M.

1982-01-01

186

Optoelectronic interconnects for 3D wafer stacks  

Microsoft Academic Search

Wafer and chip stacking are envisioned as a means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input\\/output communication channels within the layers of

David E. Ludwig; John C. Carson; Louis S. Lome

1996-01-01

187

Super-flat wafer chucks: from simulation and testing to a complete 300mm wafer chuck with low wafer deformation between pins  

NASA Astrophysics Data System (ADS)

Berliner Glas is a privately owned, mid-sized manufacturer of precision opto-mechanics in Germany. One specialty of Berliner Glas is the design and production of high performance vacuum and electrostatic wafer chucks. Driven by the need of lithography and inspection for smaller overlay values, we pursue the production of an ideally flat wafer chuck. An ideally flat wafer chuck holds a wafer with a completely flat backside and without lateral distortion within the wafer surface. Key parameters in influencing the wafer chucks effective flatness are thermal performance and thermal management, roughness of the surface, choice of materials and the contact area between wafer and wafer chuck. In this presentation we would like to focus on the contact area. Usually this is decreased as much as possible to avoid sticking effects and the chance of trapped particles between the chuck surface and the backside of the wafer. This can be realized with a pin structure on the chuck surface. Making the pins smaller and moving pins further apart from each other makes the contact area ever smaller but also adds new challenges to achieve a flat and undistorted wafer on the chuck. We would like to address methods of designing and evaluating such a pin structure. This involves not only the capability to simulate the ideal pattern of pins on the chuck's surface, for which we will present 2D and 3D simulation results. As well, we would like to share first results of our functional models. Finally, measurement capability has to be ensured, which means improving and further development of Fizeau flatness test interferometers.

Mller, Renate; Afanasiev, Kanstantin; Ziemann, Marcel; Schmidt, Volker

2014-04-01

188

"Performance Of A Wafer Stepper With Automatic Intra-Die Registration Correction."  

NASA Astrophysics Data System (ADS)

An evaluation of a wafer stepper with the new improved Philips/ASM-L phase grating alignment system is reported. It is shown that an accurate alignment system needs an accurate X-Y-0 wafer stage and an accurate reticle Z stage to realize optimum overlay accuracy. This follows from a discussion of the overlay budget and an alignment procedure model. The accurate wafer stage permits high overlay accuracy using global alignment only, thus eliminating the throughput penalty of align-by-field schemes. The accurate reticle Z stage enables an intra-die magnification control with respect to the wafer scale. Various overlay data are reported, which have been measured with the automatic metrology program of the stepper. It is demonstrated that the new dual alignment system (with the external spatial filter) has improved the ability to align to weakly reflecting layers. The results are supported by a Fourier analysis of the alignment signal. Resolution data are given for the PAS 2500 projection lenses, which show that the high overlay accuracy of the system is properly matched with submicron linewidth control. The results of a recently introduced 20mm i-line lens with a numerical aperture of 0.4 (Zeiss 10-78-58) are included.

van den Brink, M. A.; Wittekoek, S.; Linders, H. F. D.; van Hout, F. J.; George, R. A.

1987-01-01

189

Molecular and ionic contamination monitoring for cleanroom air and wafer surfaces  

NASA Astrophysics Data System (ADS)

Advances in the electronic industry toward large-scale integration of semiconductor devices have placed strict demands on the ability to measure and monitor ultratrace levels of impurities. Even though they have been found to have increasingly detrimental impacts on the performance and yield of semiconductor products, organic and non-metal ionic contaminants have not received the same attention as particles and metallics. Method developments for ultratrace measurements of molecular and ionic contamination are far behind the demands. This paper describes the use of different sampling and analytical techniques to assess and monitor molecular and ionic contaminants in cleanroom ambient air and on wafer surfaces. Thermal desorption gas chromatography mass spectrometry/nitrogen phosphorous detector is used for the identification and quantification of organic contaminants. Ammonium (NH4+) and inorganic anions are analyzed by using capillary electrophoresis with indirect UV detection methods. The identification and quantification of specific organic compounds, which outgas from cleanroom ULPA filters and wafer package boxes and tend to adsorb on silicon wafers, will be demonstrated. Ammonium and anion contamination for different wafer cleaning processes will be compared. The capabilities, applications, and limitations of these techniques will be discussed in further details.

Sun, Peng; Adams, Marty; Shive, Larry; Pirooz, Saeed

1997-09-01

190

Wafer-Level Membrane-Transfer Process for Fabricating MEMS  

NASA Technical Reports Server (NTRS)

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

191

Assembly and Hermetic Encapsulation of Wafer Level Secondary Batteries  

Microsoft Academic Search

A new technology was developed for the construction and hermetic encapsulation of chip-size secondary lithium-ion batteries on a wafer-level plane. To reduce the size of the package and improve the handling and assembly of miniature batteries, we established a wafer-level process that combines foil processing of Li batteries and wafer technologies for battery contacts and encapsulation. Parylene and thin-film metal

K. Marquardt; R. Hahn; T. Luger; H. Reichl

2006-01-01

192

Electrooptic shutter devices utilizing PLZT ceramic wafers  

SciTech Connect

Optical transparency was achieved in lead zirconate-titanate ferroelectric ceramics by substituting moderate amounts of the element lanthanum (8 to 12%) for lead. These compositions exhibit the quadratic (Kerr) electrooptic effect. The excellent optical qualities of these materials (designated PLZT) has permitted the practical utilization of their electrooptic properties in a number of devices. All of these devices utilize the classic Kerr cell arrangement. A PLZT wafer with optical axis oriented at 45/sup 0/ with respect to the axes of polarization is sandwiched between crossed polarizers. Application of an electric field via an interdigital array of electrodes on opposing wafer surfaces forces the PLZT material into a tetragonal state with the resulting induced birefringence proportional to the square of the applied electric field. Hence, the electrooptic wafer provides a retardation of light so that a component is passed by the second crossed polarizer to achieve an ON or open state. Maximum transmission is achieved when the retardation is half-wave. Shutter devices developed by Sandia and those in continuing development are described with respect to operational characteristics and physical configuration. The devices range in size from very small apertures of 50 ..mu..m x 2 mm with center-to-center repeat dimensions of 125 ..mu..m - to very large - apertures of 15.2 cm in single pieces and mosaics with apertures of 15.2 cm x 20.3 cm. Major efforts have centered on shutter development for the protection of aircrew from eye-damaging weapon effects. Other devices are also described which: provide eye protection for welders, protect vidicon tubes, function as page composers for holographic memories serve as large aperture photographic shutters, provide stereoscopic three-dimensional TV displays, and serve as data links in a fiber-optic transmission path.

Thornton, A.L.

1981-01-01

193

Wafer-level assembly and sealing of a MEMS nanoreactor for in situ microscopy  

NASA Astrophysics Data System (ADS)

This paper presents a new process for the fabrication of MEMS-based nanoreactors for in situ atomic-scale imaging of nanoparticles under relevant industrial conditions. The fabrication of the device is completed fully at wafer level in an ISO 5 clean room and it is based on silicon fusion bonding and thin film encapsulation for sealed lateral electrical feedthroughs. The fabrication process considerably improves the performances of previous nanoreactors. The wafer-level assembly allows faster preparation of devices, hydrocarbon contamination is no longer observed and the control of the channel height leads to a better flow reproducibility. The channel is shown to be sufficiently hermetic to work in the vacuum of a transmission electron microscope while a pressure of 100 kPa is maintained inside the nanoreactor. The transparency is demonstrated by the atomic scale imaging of YBCO nanoparticles, with a line spacing resolution of 0.19 nm.

Mele, L.; Santagata, F.; Pandraud, G.; Morana, B.; Tichelaar, F. D.; Creemer, J. F.; Sarro, P. M.

2010-08-01

194

Auto Defect Classification (ADC) Value for Patterned Wafer Inspection Systems in PLY Within a High Volume Wafer Manufacturing Fabrication Facility  

E-print Network

silicon wafer and repeats a process of depositing multiple layers of material on the wafer topped with a photo sensitive top layer. Using photo- litholography to expose the wafer, exposed areas will be vulnerable or hardened to the chemical etching...-6 Industry Overview . 7-10 Literary Research 11-13 Challenge 13-14 Project Outline 14 Goals... 14-16 Result 1 - Blocked Etch . 17-20 Moving Median...

Durniak, John

2010-05-14

195

Monolithically integrated thin film III-V\\/Si solar panel on wafer for active power management  

Microsoft Academic Search

We have demonstrated a monolithically integrated solar panel on Si that allows scaling of cell output voltage on the wafer level. Our design also incorporates integrated bypass diodes and the possible incorporation of CMOS for active power management at the materials integration level. In addition, we have demonstrated the first GaAsP\\/SiGe dual junction solar cell on Si that provides the

Arthur J. Pitera; John Hennessy; Andrew C. Malonis; E. A Fitzgerald; S. A. Ringel

2011-01-01

196

Mechanisms for room temperature direct wafer bonding  

NASA Astrophysics Data System (ADS)

Reducing the temperature needed for high strength bonding which was and is driven by the need to reduce effects of coefficient of thermal expansion mismatch, reduce thermal budgets, and increase throughput has led to the development of plasma treatment procedures capable of bonding Si wafers below 300 C with a bond strength equivalent to Si bulk. Despite being widely used, the physical and chemical mechanisms enabling low temperature wafer bonding have remained poorly understood. We developed an understanding of the beneficial surface modifications by plasma and a model based on short range low temperature diffusion through bonding experiments combined with results from spectroscopic ellipsometry, depth resolving Auger electron spectroscopy, and transmission electron microscopy measurements. We also present experimental results showing that even at room temperature reasonable bond strength can be achieved. We conclude that the gap closing mechanism is therefore a process which balances the lowering of the total energy by minimizing the sum of the free surface energy (maximizing the contact area between the surfaces) and strain energy in the oxide at the bond interface.

Plach, T.; Hingerl, K.; Tollabimazraehno, S.; Hesser, G.; Dragoi, V.; Wimplinger, M.

2013-03-01

197

Wafer-scale synthesis of monodisperse synthetic magnetic multilayer nanorods.  

PubMed

A double exposure technique has been used to fabricate nanoimprint stamps for making monodisperse nanorods with controllable lengths. The nanorod length is defined by a normal photolithography projection process whereas the nanorod width is defined by an edge-lithography process using a soft polydimethylsiloxane (PDMS) contact mask. Taking advantage of edge-lithography, the nanorod width can be less than the diffraction limit of the exposure light. Using these nanorod stamps, synthetic magnetic multilayer (SMM) nanorods have been fabricated using nanoimprint lithography, resulting in a length variation of ?3%. Nanorod magnetic properties have been characterized in both longitudinal and in-plane transverse directions of the nanorods. A theoretical model has been established to explain the magnetic responses and has revealed that both shape anisotropy and interlayer interactions are important in determining the properties of SMM nanorods. PMID:24329003

Zhang, Mingliang; Bechstein, Daniel J B; Wilson, Robert J; Wang, Shan X

2014-01-01

198

Hypervelocity impact on silicon wafers with metallic and polymeric coatings  

Microsoft Academic Search

Current and near future developments in microsystem technologies (MST, also known as MEMS) are defining a new trend towards lower mass, smaller volume spacecraft, without loss of functionality. The MST spacecraft components are etched onto silicon wafers coated with different metallic or polymeric material layers (typically 1-2 microns in thickness). These silicon wafers are then integrated to provide the spacecraft

E. A. Taylor; H. J. Scott; M. Abraham; A. T. Kearsley

2001-01-01

199

Through wafer via technology for 3-D packaging  

Microsoft Academic Search

Through wafer via fabrication has been one of the key technologies for 3-D packaging and microsystem packaging. Four different through wafer via fabrication technologies and applications are reviewed, such as laser drilling, deep reactive ion etching (DRIE), photo assisted electro chemical etching (PAECE) and KOH etching. Especially, KOH etching is widely used in bulk micromachining of microelectromechanical system (MEMS) fabrication

Guoqiang Feng; Xiao Peng; Jian Cai; Shuidi Wang

2005-01-01

200

Particulate contamination removal from wafers using plasmas and mechanical agitation  

DOEpatents

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Selwyn, Gary S. (Los Alamos, NM)

1998-01-01

201

Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint  

SciTech Connect

This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

Rupnowski, P.; Sopori, B.

2008-05-01

202

Near 13% Efficiency Shunt Free Solar Cells on RGS Wafers  

Microsoft Academic Search

Direct casting of silicon into wafers allows to produce wafers much more cheaply than in traditional block casting methods. RGS (ribbon growth on substrate) is such a method. In order for RGS to be cost effective sufficient cell efficiencies must be realized. In this paper we present a 12.9% efficient screen printed RGS cell. This is an increase of 0.6%

Antonius Burgers; Astrid Gutjahr; Leon Laas; Axel Schonecker; Sven Seren; Giso Hahn

2006-01-01

203

High density plasma flood system for wafer charge neutralisation  

Microsoft Academic Search

The Plasma Flood System, a low energy electron generator, has been widely used as an effective tool to neutralise wafer charging induced by ion implantation. Although it has been successful in achieving the full device yield under high current ion implantation, further advancement in device design imposed a need to minimise the wafer charging down to a few volts due

Hiroyuki Ito; Hiroshi Asechia; Yasuhiko Matsunaga; Masahiko Niwayamab; Kenji Yoneda; Michael Vella; Mike Reilly; Walt Hacker

1999-01-01

204

Sacrificial wafer bonding for planarization after very deep etching  

Microsoft Academic Search

A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of polymer bonding followed by

Vincent L. Spiering; J. W. Berenschot; Miko Elwenspoek; Jan H. J. Fluitman

1995-01-01

205

Advanced Dicing Technology for Semiconductor WaferStealth Dicing  

Microsoft Academic Search

ldquoStealth dicing (SD)rdquo was developed to solve inherent problems of a dicing process such as debris contaminants and unnecessary thermal damages on a work wafer. A completely dry process is another big advantage over other dicing methods. In SD, the laser beam power of transmissible wavelength is absorbed only around focal point in the wafer by utilizing the temperature dependence

Masayoshi Kumagai; Naoki Uchiyama; Etusji Ohmura; Ryuji Sugiura; Kazuhiro Atsumi; Kenshi Fukumitsu

2007-01-01

206

Wafer quality analysis of various scribe line mark designs  

NASA Astrophysics Data System (ADS)

Scribe Line Marks (SLM) printed on substrates are a standard method used by modern scanners for wafer alignment. Light reflected from the SLM forms a diffraction pattern which is used to determine the exact position of the wafer. The signal strength of the diffraction order needs to reach a certain threshold for the scanner to detect it. The marks are changed as the wafers go through various processes and are buried underneath complex film stacks. These processes and stacks can severely reduce wafer quality (WQ). Equipment manufactures recommend several variations of the SLM to improve WQ but these variations are not effective for certain advanced processes. This paper discusses theoretical analysis of how SLM designs affect wafer quality, addresses the challenge of self-aligned double patterning (SADP) on SLMs and experimentally verifies results using various structures.

Zhou, Jianming; Hickman, Craig; He, Yuan; Light, Scott; Lamonds, Lucas; deVilliers, Anton

2011-03-01

207

Rapid defect detections of bonded wafer using near infrared polariscope  

NASA Astrophysics Data System (ADS)

In modern field of microelectronics and MEMS, wafer bonding has emerged as an important processing step in wide range of manufacturing applications. During the manufacturing process, even in the modern clean room, small defects result from trapped particles and gas bubbles exist at bonded interface. Defects and trapped particles may exist on the top and bottom of the wafers, or at the interface of bonded wafer pair. These inclusions will generate high stress around debond region at the wafers bonded interface. In this paper, inspection at the bonded interface will be the interest of investigation. Since silicon wafer is opaque to visible light, defect detection at the bonded interface of silicon wafer is not possible. Due to the fact that silicon wafer is transparent to wavelength greater than 1150nm, an Near Infrared Polariscope which has showed some promises on residual stress measurement on silicon devices has been adapted and developed. This method is based on the well known photoelastic principles, where the stress variations are measured based on the changes of light propagation velocity in birefringence material. The results are compared and contrast with conventional Infrared Transmission Imaging tool (IRT) which is widely used to inspect the bonded silicon wafer. In this research, the trapped particles that are not visible via conventional infrared transmission method are identified via the generated residual stress pattern. The magnitude of the residual stress fields associated with each defect is examined qualitatively and quantitatively. The stress field generated at the wafers bonded interface will looks like a 'butterfly' pattern. Wafer pairs Pyrex-Si and Si-Si bonded interface will be examined.

Ng, Chi Seng; Asundi, Anand K.

2011-10-01

208

Wafer Inspection in the Photolithography Process  

NSDL National Science Digital Library

This is a description for a learning module from Maricopa Advanced Technology Education Center. This PDF describes the module; access may be purchased by visiting the MATEC website. In this module, your learners begin to master the sensitive after develop inspection (ADI) methods that follow photolithography. MATEC describes macro- and micro-inspection techniques and distinguishes qualitative (inspection) from quantitative (metrology) methods. The chief focus is on teaching learners to examine wafers under an optical microscope; a simulated microscope is also provided in a computer-based training (CBT) format. The module covers edge bead inspection and provides extensive practice in flash boundary inspection, including evaluating Nikon crosses, overlay boxes, scanning electronic microscope features, resolution bars, Verniers, and product identification numbers.

209

Double exposure as a method to correct on-wafer CD variations: a proposal  

NASA Astrophysics Data System (ADS)

Keeping across-field CD variation on the wafer within the tight limits imposed by 28nm and other advanced technologies is a challenge, particularly in a foundry where designs of different customers are realized. We propose a cost-efficient, fast, and flexible method to improve CD uniformity and correct reticle or design-induced variation, by applying a second exposure to the wafer, in the form of a grey scale map created with a low grade correction reticle. Compared to CD correction by subsequent modification of the primary reticle, this method has the potential of much higher spatial resolution and simpler logistics, which make it an attractive alternative especially for prototyping and lowvolume production.

Hotzel, Arthur; Bald, Holger

2012-02-01

210

Comparison and Efficacy of LigaSure and Rubber Band Ligature in Closing the Inflamed Cecal Stump in a Rat Model of Acute Appendicitis  

PubMed Central

Safety of either LigaSure or rubber band in closing inflamed appendiceal stump in acute appendicitis has been less investigated. In this study, cecal ligation followed by resecting inflamed cecum was performed to mimic appendectomy in a rat model of acute appendicitis. Rats were sacrificed immediately (Group A) and 7 days (Group B) after cecal resection, respectively. The cecal stumps were closed by silk ligature (S), 5?mm LigaSure (L), or rubber band (R). Seven days after cecal resection, the LigaSure (BL) and silk subgroups (BS) had significantly less intra-abdominal adhesion and better laparotomy wound healing than rubber band subgroup (BR). The initial bursting pressure at cecal stump was comparable among the three methods; along with tissue healing process, both BL and BS provided a higher bursting pressure than BR 7 days after appendectomy. BL subgroup had more abundant hydroxyproline deposition than BS and BR subgroup. Furthermore, serum TNF-? in BR group kept persistently increasing along with time after cecal resection. Thus, the finding that LigaSure but not rubber band is safe in sealing off the inflamed cecal stump in rat model of acute appendicitis suggests the possibility of applying LigaSure for appendectomy via single port procedure or natural orifice transluminal endoscopic surgery (NOTES).

Yeh, Chun-Chieh; Jan, Chia-Ing; Yang, Horng-Ren; Jeng, Long-Bin; Su, Wen-Pang

2015-01-01

211

Extraction and Analysis of Noise Parameters of On Wafer HEMTs up to 26.5 GHz  

SciTech Connect

This paper presents a procedure for extracting the four noise parameters of on wafer scaled HEMTs based on AlGaAs/GaAs heterostructure. This procedure relies on 50-{omega} noise figure measurements up to 26.5 GHz by determining the equivalent temperatures associated to the intrinsic resistances of the small signal equivalent circuit. The non-quasi-static effect associated to the gate-drain resistance R{sub gd} is accounted for by the noise model. A good agreement between measured and simulated noise figure is obtained and scaling of the noise parameters is reported.

Caddemi, Alina; Crupi, Giovanni; Macchiarella, Alessio [Dipartimento di Fisica della Materia e Ingegneria Elettronica, University of Messina, Salita Sperone 31, 98166-Messina (Italy)

2009-04-23

212

Wafer-level vacuum/hermetic packaging technologies for MEMS  

NASA Astrophysics Data System (ADS)

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

213

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.  

PubMed

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. PMID:24700434

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

214

The influence of feature sidewall tolerance on minimum absorber thickness for LIGA x-ray masks  

SciTech Connect

Minimizing mask absorber thickness is an important practical concern in producing very small features by the LIGA process. To assist in this minimization, the authors have developed coupled numerical models describing both the exposure and development of a thick PMMA resist. The exposure model addresses multi-wavelength, one-dimensional x-ray transmission through multiple beam filters, through the mask substrate and absorber, and the subsequent attenuation and photon absorption in the PMMA resist. The development model describes one-dimensional dissolution of a feature and its sidewalls, taking into account the variation in absorbed dose through the PMMA thickness. These exposure and development models are coupled in a single interactive code, permitting the automated adjustment of mask absorber thickness to yield a prescribed sidewall taper or dissolution distance. They have used this tool to compute the minimum required absorber thickness yielding a prescribed sidewall tolerance for exposures performed at the ALS, SSRL and NSLS synchrotron sources. Results are presented as a function of the absorbed dose for a range of the prescribed sidewall tolerance, feature size, PMMA thickness, mask substrate thickness and the development temperature.

S. K. Griffiths; J. M. Hruby; A. Ting

1999-02-01

215

The uses of Man-Made diamond in wafering applications  

NASA Technical Reports Server (NTRS)

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Fallon, D. B.

1982-01-01

216

Techniques for on-wafer reliability testing for MMICs  

NASA Astrophysics Data System (ADS)

Two Compliant Interconnected Structures (CISs) have been designed and fabricated to enable accelerated DC life tests to be performed at the wafer level. The first CIS was fabricated using Kapton polyimide, the second with borosilicate glass. Both structures are capable of providing bias to the GaAs wafers at 24O C for an extended period of time. Three inch wafers that contain process test characterization vehicles, a distribution amplifier, and three stage amplifiers, were used to demonstrate the feasibility of the techniques.

Saito, Yoshio

1995-09-01

217

Wafer-bonded 2-D CMUT arrays incorporating through-wafer trench-isolated interconnects with a supporting frame.  

PubMed

This paper reports on wafer-bonded, fully populated 2-D capacitive micromachined ultrasonic transducer (CMUT) arrays. To date, no successful through-wafer via fabrication technique has been demonstrated that is compatible with the wafer-bonding method of making CMUT arrays. As an alternative to through-wafer vias, trench isolation with a supporting frame is incorporated into the 2-D arrays to provide through-wafer electrical connections. The CMUT arrays are built on a silicon-on-insulator (SOI) wafer, and all electrical connections to the array elements are brought to the back side of the wafer through the highly conductive silicon substrate. Neighboring array elements are separated by trenches on both the device layer and the bulk silicon. A mesh frame structure, providing mechanical support, is embedded between silicon pillars, which electrically connect to individual elements. We successfully fabricated a 16 x 16-element 2-D CMUT array using wafer bonding with a yield of 100%. Across the array, the pulse-echo amplitude distribution is uniform (rho = 6.6% of the mean amplitude). In one design, we measured a center frequency of 7.6 MHz, a peak-to-peak output pressure of 2.9 MPa at the transducer surface, and a 3-dB fractional bandwidth of 95%. Volumetric ultrasound imaging was demonstrated by chip-to-chip bonding one of the fabricated 2-D arrays to a custom-designed integrated circuit (IC). This study shows that through-wafer trench-isolation with a supporting frame is a viable solution for providing electrical interconnects to CMUT elements and that 2-D arrays fabricated using waferbonding deliver good performance. PMID:19213645

Zhuang, Xuefeng; Wygant, Ira O; Lin, Der-Song; Kupnik, Mario; Oralkan, Omer; Khuri-Yakub, Butrus T

2009-01-01

218

Low-temperature full wafer adhesive bonding  

NASA Astrophysics Data System (ADS)

We have systematically investigated the influence of different bonding parameters on void formation in a low-temperature adhesive bonding process. As a result of these studies we present guidelines for void free adhesive bonding of 10 cm diameter wafers. We have focused on polymer coatings with layer thicknesses between 1 m and 18 m. The tested polymer materials were benzocyclobutene (BCB) from Dow Chemical, a negative photoresist (ULTRA-i 300) and a positive photoresist (S1818) from Shipley, a polyimide (HTR3) from Arch Chemical and two different polyimides (PI2555 and PI2610) from DuPont. The polymer material, the bonding pressure and the pre-curing time and temperature for the polymer significantly influence void formation at the bond interface. High bonding pressure and optimum pre-curing times/temperatures counteract void formation. We present the process parameters to achieve void-free bonding with the BCB coating and with the ULTRA-i 300 photoresist coating as adhesive materials. Excellent void-free and strong bonds have been achieved by using BCB as the bonding material which requires a minimum bonding temperature of 180 C.

Niklaus, Frank; Enoksson, Peter; Klvesten, Edvard; Stemme, Gran

2001-03-01

219

Contactless Characterization of Silicon Wafers Dieter K. Schroder  

E-print Network

strength thin film. The sensor electrode is held above the wafer by a porous ceramic air bearing, which Surface scattering, SEM/EDS, Raman Bulk Impurities Microwave-photoconductance decay, surface photovoltage

Schroder, Dieter K.

220

A ultra-high-vacuum wafer-fusion-bonding system.  

PubMed

The design of heterojunction devices is typically limited by material integration constraints and the energy band alignment. Wafer bonding can be used to integrate material pairs that cannot be epitaxially grown together due to large lattice mismatch. Control of the energy band alignment can be provided by formation of interface dipoles through control of the surface chemistry. We have developed an ultra-high-vacuum system for wafer-fusion-bonding semiconductors with in situ control and measurement of surface properties relevant to interface dipoles. A wafer-fusion-bonding chamber with annealing capabilities was integrated into an ultra-high-vacuum system with a sputtering chamber and an x-ray photoelectron spectroscopy system for preparing and measuring the surface chemistry of wafers prior to bonding. The design of the system along with initial results for the fusion-bonded InGaAs/Si heterojunction is presented. PMID:22667658

McKay, Kyle; Wolter, Scott; Kim, Jungsang

2012-05-01

221

Proceedings of the Low-Cost Solar Array Wafering Workshop  

NASA Technical Reports Server (NTRS)

The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

Morrison, A. D.

1982-01-01

222

Photoelastic characterization of Si wafers by scanning infrared polariscope  

NASA Astrophysics Data System (ADS)

A small amount of birefringence caused by the photoelastic effect from residual strains, crystal-defects-induced strains, and process-induced strains in Si wafers has been measured by using an improved version of a scanning infrared polariscope (SIRP). The SIRP presented here has high sensitivity sufficient to detect the small amount of strain induced near the wafer-supporting finger by the wafer weight itself. It is found that an anomalous amount of strain is induced by slip-line generation during the thermal process and also that a concentric ring pattern of strain is induced by OSF rings. From these results, it is suggested that SIRP is very useful for Si wafer inspection and Si process evaluation in various phases.

Fukuzawa, M.; Yamada, M.

2001-07-01

223

A ultra-high-vacuum wafer-fusion-bonding system  

NASA Astrophysics Data System (ADS)

The design of heterojunction devices is typically limited by material integration constraints and the energy band alignment. Wafer bonding can be used to integrate material pairs that cannot be epitaxially grown together due to large lattice mismatch. Control of the energy band alignment can be provided by formation of interface dipoles through control of the surface chemistry. We have developed an ultra-high-vacuum system for wafer-fusion-bonding semiconductors with in situ control and measurement of surface properties relevant to interface dipoles. A wafer-fusion-bonding chamber with annealing capabilities was integrated into an ultra-high-vacuum system with a sputtering chamber and an x-ray photoelectron spectroscopy system for preparing and measuring the surface chemistry of wafers prior to bonding. The design of the system along with initial results for the fusion-bonded InGaAs/Si heterojunction is presented.

McKay, Kyle; Wolter, Scott; Kim, Jungsang

2012-05-01

224

Electrochemical method for defect delineation in silicon-on-insulator wafers  

DOEpatents

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Guilinger, Terry R. (Albuquerque, NM); Jones, Howland D. T. (Albuquerque, NM); Kelly, Michael J. (Albuquerque, NM); Medernach, John W. (Albuquerque, NM); Stevenson, Joel O. (Albuquerque, NM); Tsao, Sylvia S. (Albuquerque, NM)

1991-01-01

225

Design and electrical characterization of a novel wafer level package for RF MEMS applications  

Microsoft Academic Search

This paper describes the electrical design and characterization through modeling of a novel wafer level package for RF MEMS applications (RF switches, micro antennas, micro-machined passives, resonators, etc). The package consists of a bottom wafer, which is MEMS wafer and a cap wafer that has a micro-machined cavity for the space necessary for the movement of the MEMS device. The

N. D. Rotaru; C. S. Premachandran; M. K. Iyer

2003-01-01

226

Thin Film Encapsulation for Secondary Batteries on Wafer Level  

Microsoft Academic Search

This paper presents results concerning the realization and characterization of thin film encapsulated wafer-level batteries. Initially, the technology concept for the construction and hermetic encapsulation of chip-size lithium-ion secondary batteries on wafer level is introduced. Parylene and thin-film metal deposition was used for hermetic encapsulation of the batteries. With this technology, battery sizes between 1 mm2 and 1 cm2, and

K. Marquardt; R. Hahn; T. Lugerl; H. Reichl

2006-01-01

227

Automated reticle inspection data analysis for wafer fabs  

NASA Astrophysics Data System (ADS)

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-03-01

228

Automated reticle inspection data analysis for wafer fabs  

NASA Astrophysics Data System (ADS)

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

229

Further investigation of EUV process sensitivities for wafer track processing  

NASA Astrophysics Data System (ADS)

As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.

Bradon, Neil; Nafus, K.; Shite, H.; Kitano, J.; Kosugi, H.; Goethals, M.; Cheng, S.; Hermans, J.; Hendrickx, E.; Baudemprez, B.; Van Den Heuvel, D.

2010-04-01

230

Application of EEM fluorescence spectroscopy in understanding of the "LIGA" phenomenon in the Bay of Biscay (France)  

NASA Astrophysics Data System (ADS)

Marine mucilage is present in all oceans over the world, and in particular in the Mediterranean Sea and in the Pacific Ocean. Surface water warming and hydrodynamic processes can favor the coalescence of marine mucilage, large marine aggregates representing an ephemeral and extreme habitat for biota. DOM is a heterogeneous, complex mixture of compounds, including extracellular polymeric substances (EPS), with wide ranging chemical properties and it is well known to interact with pollutants and to affect their transport and their fate in aquatic environment. The LIGA French research program focuses on tracing colloidal dissolved organic matter (DOM) sources and cycling in the Bay of Biscay (South Western French coast). This ephemeral phenomenon (called "LIGA" in the South West of France) has been observed more than 750 times since 2010. It presents a great ecological impact on marine ecosystems and has been shown to be concomitant with the development of pathogen organisms. A one-year intensive survey of fluorescent DOM was undertaken. From April 2013 until May 2014, water samples were monthly collected from the Adour River (main fresh water inputs) and from 2 sites in the Bay of Biscay at 3 depths of the water column (surface water, at the maximum of chlorophyll-a, and deep water). Moreover, intensified samplings took place from the appearance of the phenomenon twice a week during 4 weeks. UV/visible absorbance and excitation emission matrix (EEM) fluorescence spectroscopy combined with PARAFAC and PCA analyses have been used to characterize colloidal DOM in the Bay of Biscay in order to estimate DOM sources as well as spatial and temporal variability of DOM properties. The preliminary results, obtained for about 70 samples of this survey, have already highlighted spatial and temporal variations of DOM optical properties and a peculiar fluorescent component (exc300nm/em338nm) was detected while the LIGA phenomenon arises. The appearance of this specific fluorescence signal seems to be correlated with high freshwater and terrestrial DOM inputs combined with physical forcing (flows, swell) as well as a rise in temperature and sunshine. This work already allowed us to identify different sources of colloidal DOM in the Bay of Biscay and highlighted a specific fingerprint of the LIGA phenomenon. The combination of EEM fluorescence spectroscopy with PARAFAC and PCA analyses appears thus to be a very powerful tool for the long term monitoring of such a phenomenon and would be very useful for a better understanding of the biogeochemical processes in marine environments and of the marine colloidal DOM ecodynamics.

Parot, Jrmie; Susperregui, Nicolas; Rouaud, Vanessa; Dubois, Laurent; Anglade, Nathalie; Parlanti, Edith

2014-05-01

231

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.  

PubMed

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging. PMID:22966554

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

232

Performance of Ultra Hard Carbon Wear Coatings on Microgears Fabricated by Liga  

SciTech Connect

Stiction and friction are of concern for the reliable, long-term application of Ni-alloy micromachines. We have found that the application of a 30-70 nm hard carbon coating produces a significant reduction in the friction coefficient and wear rate of electroformed Ni substrates in reciprocating sliding contact under simulated MEMS operating conditions. To evaluate the performance of coated components, a series of 70-pm-thick microgears ranging in diameter from 0.2 to 2.2 mm were fabricated from electroformed Ni via standard LIGA processes and fixtured on posts in preparation for the coating procedure. A pulsed vacuum- arc deposition process was used to deposit a carbon coating on the gears with the plasma incident at a shallow angle to the gears' top surface. A sample bias of -2 keV was used in order to produce a coating with relatively low stress and good adhesion while maintaining high hardness. This coating process is known to be somewhat comformal to the component surfaces. The coating uniformity, particularly in the high-aspect-ratio areas between the gear teeth, was evaluated with micro-Raman spectroscopy. It is shown that the coating can be applied uniformly on the top gear surface. Between the gear teeth the coating was the same thickness as on top of the gear down to a point 50 ~m below the top surface. Below that point (i.e. between 50 and 70 Lm), the coating thickness is somewhat thinner, but is still present. These results demonstrate that it is possible to a deposit hard carbon coating on microgears to reduce friction and wear in micromachines.

Ager III, J.W.; Brown, I.G.; Christenson, T.R.; Dugger, M.T.; Follstaedt, D.M.; Knapp, J.A.; Monteiro, O.R.

1998-12-18

233

Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis  

SciTech Connect

This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

Tobin, K.W.

2003-05-22

234

SUEX process optimization for ultra-thick high-aspect ratio LIGA imaging  

NASA Astrophysics Data System (ADS)

The focus of this paper is on the use of SUEX Thick Dry Film Sheet (TDFS) laminates which DJ DevCorp is developing as a thick resist material in optical and X-ray lithography. Preliminary thick dry film sheets up to 1mm thickness were successfully prepared and patterned at the CAMD X-ray beamlines and presented at HARMST 2007. Recently, new results have been published using SUEX resist sheets in UV lithography showing great market potential including plating molds for metal microparts, polymer MEMS, multilayer microfluidics structures, BioMEMS, medical devices, wafer level packaging processes, and displays. The SUEX TDFS are available in a range of thicknesses from 100?m to 1mm or more and are pre-cut into a number of standard wafer sizes. This new material is a modified epoxy formulation containing an antimony-free photo acid generator (PAG) prepared under a highly controlled solvent-less process which provides uniform coatings between two throw-away layers of protective polyester film. As part of our initial studies resist layers of 250, 500 and 1000?m were laminated onto regular silicon wafers using a hot roll laminator at a speed of 1ft/min at 75C. The entire substrate preparation takes about 1 hour and with practice users can prepare up to 10 substrates in this time which are typically ready to use within 2 hours. In our efforts to develop a commercially viable product we have conducted experiments using standard equipment available at CAMD (Quintel UV aligner and CAMD XRLM 1 and 4 beamline). Initial X-ray exposure tests were done with a bottom dose ranging between 100 and 400 J/cm3 and a top/bottom dose ratio of less than 3 for sheets up to 2mm in thickness. Exposure time for typical conditions of the CAMD storage ring (ring current ranging between 100 and 160mA, beam lifetime of about 10hrs at 100mA ring current) is about 10-15min for a 4' wafer. After exposure the samples were immediately post exposure baked between 70C and 110C using a convection oven, taken out and cooled to RT then relaxed up to 3 days before development to reduce stress. Development was done in PGMEA for up to 3 hours for the 1000?m thick samples followed by a short IPA rinse and drying in air. Very high aspect ratios of 100 or more have been routinely patterned with nearly perfectly straight sidewalls (~1-1.5?m deviation for a 1mm tall structure) and excellent image fidelity.

Johnson, Donald W.; Goettert, Jost; Singh, Varshni; Yemane, Dawit

2011-04-01

235

Integration of RF-MEMS, passives and CMOS-IC on silicon substrate by low temperature wafer to wafer bonding technique  

Microsoft Academic Search

In this paper, a novel platform technology for system level integration of RF-MEMS, RF passives and CMOS-IC on silicon substrate is reported. The RF passives and RF MEMS devices are fabricated on a low resistivity silicon wafer using Cu damascene process. After bonding the wafer to a CMOS wafer with recesses using benzocyclobutene (BCB) as intermediate layer and subsequently removal

Q. X. Zhang; H. Y. Li; M. Tang; A. B. Yu; E. B. Liao; Rong Yang; G. Q. Lo; N. Balasubramanian; D. L. Kwong

2008-01-01

236

Critical dimension control for prevention of wafer-to-wafer and module-to-module difference  

NASA Astrophysics Data System (ADS)

In recent years, the worldwide semiconductor market has changed drastically, and it is expected that the digital device market will continue to expand towards general consumer electronics and away from the personal computers that have been the core of the market. To accommodate this shift, the new devices will be diversified with improved productivity, higher process yield, and higher precision. Clean Track (LITHIUS) design also has been changed drastically to maintain equal productivity with new high throughput exposure equipment. Design changes include increasing the number of processing chambers by stacking reduced size modules in order to meet high throughput and small footprint requirements. However, this design change concept raises concerns about increased wafer-to-wafer difference (WtW) and module-to-module different (MtM). These variations can result in lower process yield and have a negative effect on design rule shrinkage. The primary causes of WtW difference and MtM difference stem from minute module hardware variations, module height differences, and module parameter adjustment differences during the installation of the tool. Previous Clean Track development focused mainly on reduction of module hardware difference as an approach to reduce WtW variation. However, to further improve lot level uniformity, it is necessary to reduce module height difference factors within the system and module adjustment disparities such as plate temperature calibrations. Highly temperature sensitive ArF processes have necessitated precise manual PEB temperature adjustments. These calibrations are labor intensive and require many field hours to ensure optimal CD uniformity. Therefore, an auto temperature measurement and adjustment tool is developed to eliminate the human error due to manual adjustment and minimize adjustment time. In order to meet demands for design rules shrinkage and increased process uniformity we minimized the WtW and MtM difference by using thermal history adjustment and transfer time control. This method is also used to improve within wafer CD control technology resulting in a more stable process. In this report, we introduce improved features to reduce WtW and MtM variation and their effect on CD uniformity with 193nm (ArF) resist and 248nm (KrF) resist.

Deguchi, Masatoshi; Tanaka, Kouichirou; Nagatani, Naohiko; Miyata, Yuichiro; Yamashita, Mitsuo; Minami, Yoshiaki; Matsuyama, Yuji

2004-05-01

237

Comparison of measurement methods for microsystem components: application to microstructures made by the deep x-ray lithography process (x-ray LIGA)  

Microsoft Academic Search

The LIGA (a German acronym for lithography, electroplating and molding) process using highly parallel x-rays permits the production of a microstructure with still unique characteristics: high aspect ratio, high accuracy, high perpendicularity and lower roughness of the side wall. From a marketing point of view, this qualitative description might suffice to attract users to the technology. Regarding widespread commercialization and

Pascal Meyer; Olaf Mder; Volker Saile; Joachim Schulz

2009-01-01

238

Transparent masks for aligned deep x-ray lithography/LIGA: low-cost high-performance alternative using glass membranes  

NASA Astrophysics Data System (ADS)

Deep x-ray lithography/LIGA has proven to be a well established framework of x-ray based technologies for the fabrication of microstructures and pseudo three-dimensional objects. Inherently, x-ray lithography/LIGA is not fully three-dimensional because of the principle of simple shadow printing onto resists of constant thickness. Thus, it would be impossible to obtain 3D spheres, but series of stacked monolithic 2D cylinders. Hence, until recently, LIGA was mainly concerned with simple uni-level (1D) monolithic structures, using optically opaque mask-membranes like Be, Si or Ti with grown-on Au absorbers. In the course for mastering pseudo three-dimensional microstructures like micro-coils or electromagnetic applications, an alignment in between the lithographic steps becomes necessary which requires optically transparent membrane materials, if optical alignment is chosen. Diamond or SiC membranes are the actual suitable materials for such purposes, but their pricing and/or process robustness inhibit their frequent use in simple projects. We would like to report on a new promising material: a glued-on thin glass membrane. The advantages are incomparably lower costs compared to Diamond or SiC technologies, a considerable ease of fabrication, handling, quite favorable mechanical/optical properties, sufficient for lithographic purposes and multi-level deep x-ray lithography/LIGA activities.

Kupka, Roland K.; Megtert, Stephan; Roulliay, Marc; Bouamrane, Faycal

1998-09-01

239

Scale  

ERIC Educational Resources Information Center

The common approach to scaling, according to Christopher Dede, a professor of learning technologies at the Harvard Graduate School of Education, is to jump in and say, "Let's go out and find more money, recruit more participants, hire more people. Let's just keep doing the same thing, bigger and bigger." That, he observes, "tends to fail, and fail

Schaffhauser, Dian

2009-01-01

240

Low-temperature titanium-based wafer bonding  

NASA Astrophysics Data System (ADS)

This thesis presents novel methods of metal-based wafer bonding at back-end-of-the-line (BEOL) compatible conditions (?450C). For the first time to our knowledge, 200 mm diameter oxidized Si wafers are bonded with prime Si wafers using 10-300 nm thick Ti as bonding intermediate at 300-450C. Nearly void-free bonding with strong mechanical integrity has been confirmed. Moreover, microcavity formation has been demonstrated by bonding of patterned wafers. Both Rutherford backscattering spectroscopy (RBS) and Auger electron spectroscopy (AES) show clear evidence of Si and Ti interdiffusion, whereas high-resolution transmission electron microscopy (HRTEM) reveals an approximately 8 nm thick amorphous layer at the bonding interface. Those results indicate that the strong adhesion at the Ti/Si bonding interface is attributed to a solid-state amorphization (SSA) assisted by interdiffusion. A key effort is devoted to fundamental investigation of low-temperature transition metal(TM)/Si-based wafer bonding. With the extensive work on Ti/Si system, additional experiments are performed with six other TM/Si systems, namely Ni/Si, Co/Si, Pd/Si, Hf/Si, Au/Si and Ta/Si. The results indicate there are two principal requirements for TM/Si-based wafer bonding: (1) intimate contact (able to break through kinetic barriers), and (2) adequate chemical bonding. Three kinetic barriers addressed in this thesis are: (1) enclosed microvoids due to surface roughness, (2) gas molecules at the bonding interface, and (3) interfacial oxides. Presence of these barriers can prevent formation of intimate contact, consequently retarding or even blocking interfacial interactions for chemical bonding. The unique properties of Group IVA metals (e.g., Ti and Hf) to reduce native SiO2 on Si surfaces and their exceptionally large solid solubility for O2 and N2, help overcome those issues. Once kinetic barriers are surmounted, the key for strong metal/Si-based wafer bonding is formation of chemical bonds, aided primarily by interdiffusion. According to their principal bonding mechanisms, the examined seven TM/Si-based wafer bonding can be divided into three groups: (1) silicidation bonding (Ni/Si, Co/Si and Pd/Si), (2) solid-state amorphization bonding (Ti/Si and Hf/Si), and (3) eutectic bonding (Au/Si). One of the major thesis contributions is the development and identification of a new type of metal-based wafer bonding, i.e. SSA bonding.

Yu, Jian

241

Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers  

NASA Technical Reports Server (NTRS)

An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

Simons, Rainee N.

2004-01-01

242

Study of the uniformity of high resistivity neutron doped silicon wafers for silicon drift detectors  

NASA Astrophysics Data System (ADS)

The DSI collaboration goal has been the development of large-area silicon drift detectors (SDD) adapted to large-scale production in industry. Such a development is necessary for the use of SDDs in large tracking systems, such as the one proposed for the ALICE experiment at LHC (see Ref. [1]). One of the necessary steps towards large-scale production is the study of the doping uniformity in commercially available Si wafers. We have performed a series of measurements aimed at the evaluation of large-scale fluctuations of doping concentration and of the possible influence on the detector quality induced by processing steps. In this paper, we report final results of both resistivity fluctuations and leakage currents measurements.

Beol, S.; Bonvicini, V.; Burger, P.; Casse, G.; Giubellino, P.; Idzik, M.; Kolojvari, A.; Rashevsky, A.; Riccati, L.; Vacchi, A.; Zampa, N.

2001-11-01

243

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness  

SciTech Connect

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

Fong, Theodore E.

2013-05-06

244

Characterizing SOI Wafers By Use Of AOTF-PHI  

NASA Technical Reports Server (NTRS)

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

245

Microwave Induced Direct Bonding of Single Crystal Silicon Wafers  

NASA Technical Reports Server (NTRS)

We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

Budraa, N. K.; Jackson, H. W.; Barmatz, M.

1999-01-01

246

450mm wafer patterning with jet and flash imprint lithography  

NASA Astrophysics Data System (ADS)

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

247

An application of selective electrochemical wafer thinning for silicon characterization  

SciTech Connect

A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

1990-01-01

248

Scales  

SciTech Connect

Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

Murray Gibson

2007-04-27

249

Toward 300 mm wafer-scalable high-performance polycrystalline chemical vapor deposited graphene transistors.  

PubMed

The largest applications of high-performance graphene will likely be realized when combined with ubiquitous Si very large scale integrated (VLSI) technology, affording a new portfolio of "back end of the line" devices including graphene radio frequency transistors, heat and transparent conductors, interconnects, mechanical actuators, sensors, and optical devices. To this end, we investigate the scalable growth of polycrystalline graphene through chemical vapor deposition (CVD) and its integration with Si VLSI technology. The large-area Raman mapping on CVD polycrystalline graphene on 150 and 300 mm wafers reveals >95% monolayer uniformity with negligible defects. About 26,000 graphene field-effect transistors were realized, and statistical evaluation indicates a device yield of ? 74% is achieved, 20% higher than previous reports. About 18% of devices show mobility of >3000 cm(2)/(V s), more than 3 times higher than prior results obtained over the same range from CVD polycrystalline graphene. The peak mobility observed here is ? 40% higher than the peak mobility values reported for single-crystalline graphene, a major advancement for polycrystalline graphene that can be readily manufactured. Intrinsic graphene features such as soft current saturation and three-region output characteristics at high field have also been observed on wafer-scale CVD graphene on which frequency doubler and amplifiers are demonstrated as well. Our growth and transport results on scalable CVD graphene have enabled 300 mm synthesis instrumentation that is now commercially available. PMID:25198884

Rahimi, Somayyeh; Tao, Li; Chowdhury, Sk Fahad; Park, Saungeun; Jouvray, Alex; Buttress, Simon; Rupesinghe, Nalin; Teo, Ken; Akinwande, Deji

2014-10-28

250

Influence of gas composition on wafer temperature in a tungsten chemical vapor deposition reactor: Experimental measurements, model  

E-print Network

include a gas phase transport submodel and a wafer submodel to account for the interactions between/wafer boundary condition solved simultaneously with the wafer dy- namical submodel can provide insightful

Rubloff, Gary W.

251

Imaging crystal orientations in multicrystalline silicon wafers via photoluminescence  

E-print Network

) Crystal phase and growth orientation dependence of GaAs nanowires on NixGay seeds via vaporImaging crystal orientations in multicrystalline silicon wafers via photoluminescence H. C. Sio, Z-mediated nonclassical crystal growth of sodium fluorosilicate nanowires and nanoplates AIP Advances 1, 042165 (2011

252

Vibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements  

E-print Network

effects on the manufacturing processes. In addition, vibration analysis of wiresaw can leadVibration Analysis of Wiresaw Manufacturing Processes and Wafer Surface Measurements I. Kao (PI), S the yield per crystal and to reduce the cost. In this paper, the vibration model of wiresaw system

Kao, Imin

253

THIN GLASS OPTIC AND SILICON WAFER DEFORMATION AND KINEMATIC CONSTRAINT  

Microsoft Academic Search

To meet these assembly and metrology challenges, we present how thin materials such as silicon and glass wafers deform and how they can be constrained to minimize these effects. Both analytical calculations and finite element analyses (FEA) are utilized to understand the effects of gravity on foil deformation while varying parameters such as foil thickness and angle of inclination. Friction

Craig R. Forest; Mireille Akilian; Guillaume Vincent; Alexandre Lamure; Mark L. Schattenburg

2003-01-01

254

Reducing Cycle Time at an Ibm Wafer Fabrication Facility  

Microsoft Academic Search

In 1991, IBM San Jose decided to produce and sell magnetic heads for computer disk drives on the open market to original equipment manufacturers. However, as IBM's wafer fabrication facility increased the number of products it manufactured, its manufacturing cycle time lengthened. Since cycle time is important in competing in the open market, IBM San Jose formed a study team

Lieven DEMEESTER; C. S. Tang

1996-01-01

255

Crack propagation and fracture in silicon wafers under thermal stress  

PubMed Central

The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing. PMID:24046487

Danilewsky, Andreas; Wittge, Jochen; Kiefl, Konstantin; Allen, David; McNally, Patrick; Garagorri, Jorge; Elizalde, M. Reyes; Baumbach, Tilo; Tanner, Brian K.

2013-01-01

256

Scatterometry on pelliclized masks: an option for wafer fabs  

NASA Astrophysics Data System (ADS)

Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

2007-03-01

257

Full wafer metrology for chemically graded thin films  

NASA Astrophysics Data System (ADS)

Combinatorial CBVD (Chemical Beam Vapor Deposition) is a thin film deposition technology which has the ability to produce multi-element thin films with large controlled composition spread gradients. If functional characterizations can be carried out systematically and rapidly on such graded films over full wafers, they enable to identify precisely the best film composition for a given application, and CBVD then easily allows for the deposition of the optimized film homogeneously on large wafers. In this article, we demonstrate the efficiency of such a process development based on the optimization of new Transparent Conductive Oxide thin films (TCO) of few % Nb doped TiO2. We have developed a full wafer metrology instrument which maps the optical thickness and the sheet resistance with a lateral resolution below 400um. We discuss the performance of various algorithms to extract the optical thickness from the white light reflectance measurement in the case of very small thickness. The sheet resistance is measured with an array of four AFM-like conductive cantilevers, allowing accurate sheet resistance (R) measurement where the standard tungsten four probes destroy porous thin oxide films. Application of these measurements to several Nb doped TiO2 films deposited on 4" wafer by CBVD is presented.

Jobin, Marc; Jotterand, Stphane; Pellodi, Cdric; dos Santos, Sergio; Sandu, Cosmin Silviu; Wagner, Estelle; Benvenuti, Giacomo

2012-04-01

258

Novel adhesive development for CMOS-compatible thin wafer handling  

Microsoft Academic Search

3D integration is a promising technology for advancing the performance of semiconductors since it can provide higher density, faster speed and better power efficiency in a smaller form factor [13]. The Through Silicon Via (TSV) is an important component for achieving the benefits of 3D integrated semiconductors. However, depending on the temporary wafer bonding technology's behavior during processing at temperatures

K. Tamura; K. Nakada; N. Taneichi; P. Andry; J. Knickerbocker; C. Rosenthal

2010-01-01

259

Nanomechanical optical devices fabricated with aligned wafer bonding  

Microsoft Academic Search

This paper reports on a new method for making some types of integrated optical nanomechanical devices. Intensity modulators as well as phase modulators were fabricated using several silicon micromachining techniques, including chemical mechanical polishing and aligned wafer bonding. This new method enables batch fabrication of the nanomechanical optical devices, and enhances their performance

C. Gui; G. J. Veldhuis; T. M. Koster; P. V. Lambeck; J. W. Berenschot; J. G. E. Gardeniers; M. Elwenspoek

1998-01-01

260

Localized induction heating solder bonding for wafer level MEMS packaging  

Microsoft Academic Search

This paper reports a new solder bonding method for the wafer level packaging of MEMS devices. Electroplated magnetic film was heated using induction heating causing the solder to reflow. The experiment results show that it took less than 1 min to complete the bonding process. In addition, the MEMS devices experienced a temperature of only 110 C during bonding, thus

Hsueh-An Yang; Mingching Wu; Weileun Fang

2005-01-01

261

Crack propagation and fracture in silicon wafers under thermal stress.  

PubMed

The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing. PMID:24046487

Danilewsky, Andreas; Wittge, Jochen; Kiefl, Konstantin; Allen, David; McNally, Patrick; Garagorri, Jorge; Elizalde, M Reyes; Baumbach, Tilo; Tanner, Brian K

2013-08-01

262

Steel Bridge Fatigue Crack Detection with Piezoelectric Wafer Active Sensors  

E-print Network

Steel Bridge Fatigue Crack Detection with Piezoelectric Wafer Active Sensors Lingyu Yu1 , Victor acoustic emission to detect the presence of fatigue cracks in steel bridges in their early stage since primarily on history of past performance. In this study, extensive laboratory investigation is performed

Giurgiutiu, Victor

263

Ultraviolet laser removal of small metallic particles from silicon wafers  

Microsoft Academic Search

Laser removal of small 1?m sized copper, gold and tungsten particles from silicon wafer surfaces was carried out using ultraviolet radiation at 266nm generated by Nd:YAG harmonic generation. Successful removal of both copper and gold particles from the surface was achieved whereas tungsten particles proved to be difficult to remove. The cleaning efficiency was increased with an increase of laser

C. Curran; J. M. Lee; K. G. Watkins

2002-01-01

264

Characterization, modeling, and design of an electrostatic chuck with improved wafer temperature uniformity  

NASA Astrophysics Data System (ADS)

The resulting temperature distribution of a silicon wafer held by an electrostatic chuck (ESC) in an electron-cyclotron-resonance chemical vapor deposition (ECR-CVD) reactor is characterized and modeled. The effects of the clamping voltage VESC, pressure between the ESC and wafer PHe, and the surface finish and pattern on the ESC are investigated. Heat transfer coefficients between the wafer and various ESCs are determined experimentally. A model is developed to predict the temperature distribution at the surface of the wafer, and used to explain the experimentally observed temperature variations both within wafer and between different chucks. The model is then used to aid in the design of an ESC which provides improved temperature uniformity at the wafer surface. The results of this study indicate: (a) the thermal resistances across the interface between the wafer and ESC control both the absolute wafer temperature and the wafer temperature uniformity; (b) the surface roughness of the ESC and the size of the ``contact'' regions are major design factors controlling the absolute temperature of the waferthe temperature can be adjusted by varying the value of VESC and fine tuned by adjusting the value of PHe; (c) the nonuniform temperature distribution across the wafer surface is dictated by the surface pattern on the ESC, the variation in surface roughness, and the size of the ESC relative to the wafer; (d) wafer temperature variations from chuck to chuck are reduced by controlling the surface finish of the ESC and by ensuring that PHe is a dominant heat transfer mechanism; and (e) maximum uniformity in the temperature of the wafer is obtained when the radius of the ESC is matched as closely as possible to that of the wafer. We have shown that numerical heat transfer models can be used to optimize the geometry of the ESC to provide a uniform distribution of temperature across the surface of the wafer.

Olson, Kurt A.; Kotecki, David E.; Ricci, Anthony J.; Lassig, Stephan E.; Husain, Anwar

1995-02-01

265

Fine Keyed Alignment and Bonding for Wafer-Level 3D ICs  

Microsoft Academic Search

Precise wafer-to-wafer alignment accuracy is crucial to interconnecting circuits on different wafers in three dimensional integrated circuits. We discuss the use of fabricated structures on wafer surfaces to mechanically achieve higher alignment accuracy than can be achieved with our existing (baseline) alignment protocol. The keyed alignment structures rely on structures with tapered side-walls that can slide into each after two

Sang Hwui Lee; Frank Niklaus; J. Jay McMahon; Jian Yu; Ravi J. Kumar; Hui-feng Li; Ronald J. Gutmann; Timothy S. Cale; J.-Q. Lu

266

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment  

NASA Technical Reports Server (NTRS)

Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

2013-01-01

267

B-Cell-Specific Peptides of Leptospira interrogans LigA for Diagnosis of Patients with Acute Leptospirosis  

PubMed Central

Leptospirosis is a reemerging infectious disease that is underdiagnosed and under-recognized due to low-sensitivity and cumbersome serological tests. Rapid reliable alternative tests are needed for early diagnosis of the disease. Considering the importance of the pathogenesis-associated leptospiral LigA protein expressed in vivo, we have evaluated its application in the diagnosis of the acute form of leptospirosis. The C-terminal coding sequence of ligA (ligA-C) was cloned into pET15b and expressed in Escherichia coli. Furthermore, the B-cell-specific epitopes were predicted and were synthesized as peptides for evaluation along with recombinant LigA-C. Epitope 1 (VVIENTPGK), with a VaxiJen score of 1.3782, and epitope 2 (TALSVGSSK), with a score of 1.2767, were utilized. A total of 140 serum samples collected from leptospirosis cases during the acute stage of the disease and 138 serum samples collected from normal healthy controls were utilized for evaluation. The sensitivity, specificity, positive predictive value, and negative predictive value were calculated for the recombinant LigA-C-specific IgM enzyme-linked immunosorbent assay (ELISA) and were found to be 92.1%, 97.7%, 92.8%, and 97.5%, respectively. Epitopes 1 and 2 used in the study showed 5.1 to 5.8% increased sensitivity over recombinant LigA-C in single and combination assays for IgM antibody detection. These findings suggest that these peptides may be potential candidates for the early diagnosis of leptospirosis. PMID:24403522

Kanagavel, Murugesan; Shanmughapriya, Santhanam; Anbarasu, Kumarasamy

2014-01-01

268

Formation of Surface Microcrack for Separation of Nonmetallic Wafers Into Chips  

Microsoft Academic Search

High quality separation of wafers into chips is important to the electronic industry. Since chips often operate at a high power level ~Bar-Cohen @1#, Suhir @2#! wafers with high quality edges are required. Most of the defects, e.g., microcracks, dislocations, etc., form during cutting. During heating, the defects at the edge of a wafer ~with a size larger than some

T. Elperin; A. Kornilov; G. Rudin

2009-01-01

269

Wafer mapping of total dose failure thresholds in a bipolar recessed field oxide technology  

SciTech Connect

Ionizing radiation failure thresholds were measured across a silicon wafer using 10 KeV x-rays to determine the success of hardened process modifications and to examine wafer level hardness assurance screening techniques. Topological wafer maps of the total dose failure response for Signetics 74F00 circuits are presented.

Titus, J.L.; Platteter, D.G.

1987-12-01

270

System analysis of wafer logistics information management for IC packaging foundry in Taiwan  

Microsoft Academic Search

The IC manufacturing related business had been remarkably developed for the past decade in Taiwan. In addition to the well-known wafer fabrication industries, the IC design house and IC packaging\\/testing business together form a contiguous supply chain form material to system in Taiwan. Logistics and information management of the wafer is the key linkage in the wafer foundry process. The

Yu-Chuan Liu

2008-01-01

271

A LOW COST WAFER-LEVEL MEMS PACKAGING TECHNOLOGY Pejman Monajemi, Paul J. Joseph*  

E-print Network

A LOW COST WAFER-LEVEL MEMS PACKAGING TECHNOLOGY Pejman Monajemi, Paul J. Joseph* , Paul A. Kohl-cost low-temperature packaging technique for wafer-level encapsulation of MEMS devices fabricated on any arbitrary substrate. The packaging process presented here does not involve wafer bonding and can be applied

Ayazi, Farrokh

272

GaAs-Wafer Dicing Using the Water jet Guided Laser  

Microsoft Academic Search

Semiconductor wafers are getting thinner and thinner. GaAs wafers are not excluded by this trend. Since new dicing technologies are required for wafer thicknesses less than 150 m. Significant differences are noted among existing dicing methods. Abrasive sawing does not provide the desired cutting speed and yield because of mechanical damage (cracking, chipping). Cutting with conventional lasers should be avoided

Delphine Perrottet; Akos Spiegel; Simone Amorosi; Bernold Richerzhagen

273

Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers for PV Cells  

SciTech Connect

As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay ({mu}PCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

Guthrey, H.; Gorman, B.; Al-Jassim, M.

2011-01-01

274

Enhanced capture rate for haze defects in production wafer inspection  

NASA Astrophysics Data System (ADS)

Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure involved scanning with three different recipe types: Standard Inspection: Nominal recipe with a low false alarm rate was used to scan the wafer and repeaters were extracted from the final defect map. Haze Monitoring Application: Recipe sensitivity was enhanced and run on a single field column from which on repeating defects were extracted. Enhanced Repeater Extractor: Defect processing included the two parallel routes: a nominal recipe for the random defects and the new high sensitive repeater extractor algorithm. The results showed that the new application (recipe #3) had the highest capture rate on haze defects and detected new repeater defects not found in the first two recipes. In addition, the recipe was much simpler to setup since repeaters are filtered separately from random defects. We expect that in the future, with the advent of mask-less lithography and EUV lithography, the monitoring of field and die repeating defects on the wafer will become a necessity for process control in the semiconductor fab.

Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

2010-03-01

275

Liquid crystal lens auto-focus extended to optical image stabilization for wafer level camera  

NASA Astrophysics Data System (ADS)

Miniaturization and reduction of production cost of optical components in consumer electronics leads to wafer level optics. This miniaturization, associated with the increase of CMOS sensors resolution, generates new needs such as auto-focus (AF) and optical image stabilization (OIS) in order to reduce the blurring caused by hand jitter. In this paper, we propose a wafer scale technology to perform AF and introduce OIS functionality. We managed to create a tunable focal lens by filling with nematic liquid crystal (LC) an assembly of two glass substrates coated with circular hole patterned chromium electrodes and resistive transparent layers of Poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT-PSS). When a voltage with tunable magnitude and frequency is applied to the electrodes, the resistive layer creates a non-uniform voltage distribution from the edge to the center of the aperture which depends on electrical parameters of PEDOT-PSS and LC. The resultant electric field generates a gradient orientation of the nematic director which allows to focus light polarized along the director. It is also possible to shift the optical axis of the lens by dividing the hole patterned electrodes in several sectors and to apply different voltages on each sectors. The principle of the shifting effect has been demonstrated but its magnitude has to be increased by using more adapted electrode structure to ensure the OIS function. Finally, we characterised the dynamical behaviour of the lens in both focus and shifting modes.

Fraval, Nicolas; Berier, Frdric

2011-03-01

276

A hermetic and room-temperature wafer bonding technique based on integrated reactive multilayer systems  

NASA Astrophysics Data System (ADS)

This paper focuses on direct deposition and patterning of reactive and nano-scale multilayer films at wafer level. These multilayer structures are called integrated reactive material systems (iRMS). In contrast to the typically used nickel (Ni)/ aluminum (Al) systems, in this work we needed to have our total multilayer film thicknesses smaller than 2.5?m to reduce stress within the multilayer as well as deposition costs. Thus, we introduced new high energetic iRMS. These films were deposited by using alternating magnetron sputtering from high purity Al- and palladium (Pd)-targets to obtain films with a defined Al:Pd atomic ratio. In this paper, we present the result for reaction characteristics and reaction velocities which were up to 72.5?m?s?1 for bond frames with lateral dimensions as low as 20?m. Furthermore, the feasibility of silicon (Si)Si, Siglass as well as Siceramic hermetic and metallic wafer bonding at room temperature is presented. We show that by using this bond technology, strong (maximum shear strengths of 235?MPa) and hermetically sealed bond interfaces can be achieved without any additional solder material.

Braeuer, J.; Gessner, T.

2014-11-01

277

Wafer-level packaging with compression-controlled seal ring bonding  

DOEpatents

A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Farino, Anthony J

2013-11-05

278

A photo-sensor on thin polysilicon membrane embedded in wafer level package LED  

NASA Astrophysics Data System (ADS)

A wafer level packaging LED with photo-sensor which is fabricated on thin poly-silicon membrane located on the corner of silicon cavity is presented in this paper. The wafer substrate was fabricated with (100) orientation silicon wafer and a cavity was etched on the top of the wafer with wet chemical anisotropic etching process for mounting a LED chip. A thin polysilicon membrane was fabricated on the corner of the cavity and a MSM (Metal Semiconductor Metal) type photo-sensor was fabricated on the thin polysilicon membrane. The photo-sensor fabrication and LED packaging were completed on wafer level. The embedded photo-sensor in a wafer level packaging LED is designed to measure light intensity of a LED. The membrane structure photo-sensor can sense the light of the mounted LED directly, so it can measure accurate light intensity of the wafer level packing LED.

Kim, Jin Kwan; Lee, Hee Chul

2012-06-01

279

Influence of the bonding front propagation on the wafer stack curvature  

NASA Astrophysics Data System (ADS)

The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

Navarro, E.; Brchet, Y.; Barthelemy, A.; Radu, I.; Pardoen, T.; Raskin, J.-P.

2014-08-01

280

Photostimulated near-infrared persistent luminescence as a new optical read-out from Cr3+-doped LiGa5O8  

PubMed Central

In conventional photostimulable storage phosphors, the optical information written by x-ray or ultraviolet irradiation is usually read out as a visible photostimulated luminescence (PSL) signal under the stimulation of a low-energy light with appropriate wavelength. Unlike the transient PSL, here we report a new optical read-out form, photostimulated persistent luminescence (PSPL) in the near-infrared (NIR), from a Cr3+-doped LiGa5O8 NIR persistent phosphor exhibiting a super-long NIR persistent luminescence of more than 1,000?h. An intense PSPL signal peaking at 716?nm can be repeatedly obtained in a period of more than 1,000?h when an ultraviolet-light (250360?nm) pre-irradiated LiGa5O8:Cr3+ phosphor is repeatedly stimulated with a visible light or a NIR light. The LiGa5O8:Cr3+ phosphor has promising applications in optical information storage, night-vision surveillance, and in vivo bio-imaging. PMID:23532003

Liu, Feng; Yan, Wuzhao; Chuang, Yen-Jun; Zhen, Zipeng; Xie, Jin; Pan, Zhengwei

2013-01-01

281

Slumping of Si wafers at high temperature  

NASA Astrophysics Data System (ADS)

Space X-ray imaging telescopes have delivered unique observations that have been significantly contributing to many important discoveries of current astrophysics. For future telescopes with a larger collecting area and a better angular resolution, the limiting factor is their X-ray reflecting mirror array. Therefore, for a successful construction of future lightweight and highly reflecting X-ray mirrors, new cost-effective technologies and progressive materials are needed. Currently, the very promising materials are silicon foils which are commercially produced on a large scale. We focused on the plastic deformation of thin monocrystalline silicon foils, which was necessary for the precise thermal forming of the foils to 3D shapes. To achieve the plastic deformation, we applied forced slumping at temperatures from 1200 to 1400C. The final shapes and the surface quality of the foils were measured using a Taylor Hobson contact profilometer and examined with an Atomic Forced Microscopy. We studied the effects of temperature, applied slumping force, heattreatment time, crystal orientation, and furnace atmosphere on the shape and surface quality of the formed foils.

Mika, M.; Jankovsky, O.; Simek, P.; Lutyakov, O.; Havlikova, R.; Sofer, Z.; Hudec, R.; Pina, L.; Inneman, A.; Sveda, L.; Marsikova, V.

2013-05-01

282

Wafer-fused VECSELs emitting in the 1310nm waveband  

NASA Astrophysics Data System (ADS)

Optically pumped wafer fused 1310 nm VECSELs have the advantage of high output power and wavelength agility. Gain mirrors in these lasers are formed by direct bonding of InAlGaAs/InP active cavities to Al(Ga)As/GaAs DBRs. We present for the first time Watt-level 1310 nm wafer-fused VCSELs based on gain mirrors with heat dissipation in the "flip-chip" configuration. Even though output power levels in this approach is lower than with intra-cavity diamond heat-spreaders, the "flip-chip configuration demonstrates higher quality optical emission and is preferable for industrial applications in optical amplifiers, intra-cavity doubled lasers, etc.

Sirbu, A.; Pierscinski, K.; Mereuta, A.; Iakovlev, V.; Caliman, A.; Micovic, Z.; Volet, N.; Rautiainen, J.; Heikkinen, J.; Lyytikainen, J.; Rantamki, A.; Okhotnikov, O.; Kapon, E.

2014-03-01

283

Chemical method for producing smooth surfaces on silicon wafers  

DOEpatents

An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

Yu, Conrad (Antioch, CA)

2003-01-01

284

Towards large size substrates for III-V co-integration made by direct wafer bonding on Si  

NASA Astrophysics Data System (ADS)

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

2014-08-01

285

Electrophoretic Photoresist Application for High Topography Wafer Surfaces  

Microsoft Academic Search

As wafer surfaces become topographically more challenging, achieving uniform resist coatings in deep vias, over high mesas, and three-dimensional (3-D) features may no longer be possible using conventional, solvent based, spin-coated liquid photoresist (LPR). Thinning of the resist on the high areas and pooling of the resist in the deep areas are common problems. Electrophoretic photoresist (EPR) may be used

James Tajadod; Henry Hendriks; John Klocke; Antonio Morales; Heather Rapuano

286

Wafer-level radiometric performance testing of uncooled microbolometer arrays  

NASA Astrophysics Data System (ADS)

A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 ?m AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 ?m pixel size and 160x120, 52 ?m pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

2014-03-01

287

On-wafer calibration using space-conservative (SOLT) standards  

Microsoft Academic Search

In this paper the accuracy of on-wafer calibration using space-conservative (SOLT) standards is evaluated. The calibration approach relies on measurement-based standard definitions. Results are presented using CPW standards with 50 and 300 micron offsets, over the range from .045-65 GHz. In comparing to a multi-line TRL, the magnitude of the difference between the S-parameters is less than 0.05 up to

M. Imparato; T. Weller; L. Dunleavy

1999-01-01

288

Performance limiting micropipe defects in silicon carbide wafers  

Microsoft Academic Search

Reports on the characteristics of a major defect in mass-produced silicon carbide wafers which severely limits the performance of silicon carbide power devices. Micropipe defects originating in 4H- and 6H-SiC substrates were found to cause pre-avalanche reverse-bias point failures in most epitaxially-grown pn junction devices of 1 mm2 or larger in area. Until such defects are significantly reduced from their

Philip G. Neudeck; Anthony J. Powell

1994-01-01

289

Reduction of electrostatically adhered particles on wafer backside using ionizers  

Microsoft Academic Search

In this paper we provide results and discussion on the positive impact of ionizer(s) used in multiple configurations on wafer back-side and front-side particle adders in PVD processing tools. We present a hypothesis, followed by testing, that establishes a relationship between electrical surface charge collection data and particle data obtained in a laboratory setting and real world fabrication facility (fab)

Viraj Pandit; Emery Kuo

2010-01-01

290

Method for making circular tubular channels with two silicon wafers  

DOEpatents

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

Yu, Conrad M. (Antioch, CA); Hui, Wing C. (Campbell, CA)

1996-01-01

291

Method for making circular tubular channels with two silicon wafers  

DOEpatents

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

Yu, C.M.; Hui, W.C.

1996-11-19

292

Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers  

E-print Network

Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive advantage of copper-to-copper (Cu-to-Cu) bonding with the increased adhesion strength and robustness of dielectric adhesive bonding using benzocyclobutene (BCB) is discussed. Critical processing challenges

Salama, Khaled

293

Thermomechanical Reliability Study of Benzocyclobutene Film in Wafer-Level Chip-Size Package  

NASA Astrophysics Data System (ADS)

A new wafer-level chip-scale package process for high-performance, low-cost packaging has been developed based on passivation with low dielectric constant. This process is simpler and shorter when using permanent photosensitive benzocyclobutene (BCB) compared with the conventional process. However, cracks nucleating on the BCB cause serious reliability problems. The major reasons for cracking of the BCB layer seem to be both thermal stress and a shortage of BCB cross-linking agent (cyclobutene). The stress was reduced by optimizing the thickness of the BCB layer and the underlying stress buffer layer. The BCB cracking resistance was improved by creating more cross-linking agent at the final curing process through modification of the photolithography processes.

Lee, K.-O.

2012-04-01

294

Wafer shape compensation at the track PEB for improved CD uniformity  

NASA Astrophysics Data System (ADS)

This paper investigates the feasibility of using an electrostatic chuck (ESC) on a post exposure bake (PEB) plate in the track to improve the critical dimension uniformity (CDU) for bowed wafers. Although it is more conventional to consider vacuum chucking during PEB, electrostatic chucking offers some potential advantages, chief among which is the fact that electrostatic chucking does not require any type of a seal between the wafer and the PEB plate whereas vacuum chucking does. Such a seal requires contact and therefore has the potential to generate backside particles on the wafer. Electrostatic chucking therefore has the potential for a cleaner overall process. Three different PEB plates were tested in the course of this investigation, a non-chucking PEB plate (SRHP), a PEB plate equipped with a vacuum chuck (VRHP), and a PEB plate equipped with an ESC (eBHP). It was found that CD uniformities were up to 84 percent lower for bowed wafers that were chucked during PEB relative to wafers that were not chucked. In every case tested, wafers processed through chucking PEB plates showed lower CDUs than wafers processed through the non-chucking plate. CDU results were similar between vacuum chucked wafers and electrostatic chucked wafers. Based on the results presented in this paper, it can be concluded that electrostatic chucking during PEB is a feasible method for controlling CD uniformities on bowed wafers.

Michaelson, Timothy; Dai, Junyan; Chen, Lu; Cervera, Hiram; Lue, Brian; Herchen, Harald; Vellore, Kim; Bekiaris, Nikolaos

2008-03-01

295

Reactor scaling for large area plasma processing  

NASA Astrophysics Data System (ADS)

Migration to 300 mm wafer size is a topic of active research and development in semiconductor processing. Plasma process tool development for 300 mm wafers faces significant technical challanges, particularly from the point of view of process uniformity across the wafer. Process and reactor modeling can play a complementary role in tool design and development. Many of the models in the literature have focused thus far on discharge physics aspects of the modeling excercise. In this work, we also focus on gas flow and other reactor issues. The model involves two dimensional solution to compressible gas flow, energy and multispecies conservation equations. A simplified chemical scheme for the chlorine etching of silicon is considered. Simulation results are presented for various reactor geometrical parameters, pressures, and flow rates. Scaling to 300 mm wafer is discussed.

Meyyappan, M.

1996-10-01

296

Improved surface quality of anisotropically etched silicon {111} planes for mm-scale integrated optics  

E-print Network

We have studied the surface quality of millimeter-scale optical mirrors produced by etching CZ and FZ silicon wafers in potassium hydroxide to expose the $\\{111\\}$ planes. We find that the FZ surfaces have four times lower noise power at spatial frequencies up to $500\\, {mm}^{-1}$. We conclude that mirrors made using FZ wafers have higher optical quality.

Cotter, J P; Kraft, M; Hinds, E A

2013-01-01

297

An improved calibration technique for on-wafer large-signal transistor characterization  

Microsoft Academic Search

The on-wafer measurement of complex quantities and absolute power levels of active devices is truly significant for nonlinear device characterization and modeling. An original procedure, which allows one to perform both the vector and the power calibrations at the RF wafer probe tips used for on-wafer measurement of two-port devices, is presented. The measurement system is based on an automatic

Andrea Ferrero; Umberto Pisani

1993-01-01

298

Wafer-level manufacturing technology of glass microlenses  

NASA Astrophysics Data System (ADS)

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

299

Alternative fabrication process for edgeless detectors on 6 in. wafers  

NASA Astrophysics Data System (ADS)

VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150 ?m thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 55 and 11 cm2 edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.41.4 cm2 Medipix2 edgeless pixel detectors were also fabricated.This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100 ?m from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50-70 nA/cm2 and 580-660 pF/cm2 at, respectively, 40 V reverse bias for the p-on-n. For the n-on-n design these parameters were 116-118 nA/cm2 and 930-960 pF/cm2. The breakdown voltages were above 150 V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13-28 V.

Kalliopuska, Juha; Ernen, Simo; Virolainen, Tuula

2011-05-01

300

THz quantum cascade lasers with wafer bonded active regions.  

PubMed

We demonstrate terahertz quantum-cascade lasers with a 30 ?m thick double-metal waveguide, which are fabricated by stacking two 15 ?m thick active regions using a wafer bonding process. By increasing the active region thickness more optical power is generated inside the cavity, the waveguide losses are decreased and the far-field is improved due to a larger facet aperture. In this way the output power is increased by significantly more than a factor of 2 without reducing the maximum operating temperature and without increasing the threshold current. PMID:23188348

Brandstetter, M; Deutsch, C; Benz, A; Cole, G D; Detz, H; Andrews, A M; Schrenk, W; Strasser, G; Unterrainer, K

2012-10-01

301

Propagation of Nd-laser pulses through crystalline silicon wafers  

SciTech Connect

Propagation of pulses from an Nd:YAG laser (wavelength, 1.064 {mu}m; pulse duration, 270 ns; pulse energy, 225 {mu}J) through crystalline silicon wafers is studied experimentally. Mathematical modelling of the process is performed: the heat conduction equation is solved numerically, the temperature dependences of the absorption and refraction of a substance, as well as generation of nonequilibrium carriers by radiation are taken into account. The constructed model satisfactorily explains the experimentally observed intensity oscillations of transmitted radiation. (interaction of laser radiation with matter)

Kirichenko, N A; Kuzmin, P G; Shcherbina, M E [Wave Research Center, A.M. Prokhorov General Physics Institute, Russian Academy of Sciences, Moscow (Russian Federation)

2011-07-31

302

Network analyzer calibration for cryogenic on-wafer measurements  

SciTech Connect

A cryogenic probe station for on-wafer microwave measurements has been developed at Sandia National Laboratories to explore the basic device physics and characterize advanced components for low-temperature applications. The station was designed to operate over a temperature range of 20 to 300 K with a frequency range of DC to 50 GHz. Due to the vacuum and the low temperature environment, the use of microwave probes and the calibration of network analyzer measurements are somewhat elaborate. This paper presents guidelines for probe use and calibration in this environment.

Hietala, V.M.; Housel, M.S.; Caldwell, R.B.

1994-04-01

303

Addressable Inverter Matrix Tests Integrated-Circuit Wafer  

NASA Technical Reports Server (NTRS)

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Buehler, Martin G.

1988-01-01

304

Characterization of wafer charging mechanisms and oxide survival prediction methodology  

SciTech Connect

Unipolar, EEPROM-based peak potential sensors and current sensors have been used to characterize the I-V relationship of charging transients which devices normally experience during the course of ion implantation. The results indicate that the charging sources may appear to behave like current-sources or voltage-sources, depending on the impedance of the load. This behavior may be understood in terms of plasma concepts. The ability to empirically characterize the I-V characteristics of charging sources using the CHARM-2 monitor wafers opens the way for prediction of failure rates of oxides subjected to specific processes, if the oxide Q{sub bd} distributions are known.

Lukaszek, W.; Dixon, W. [Stanford Univ., CA (United States). Center for Integrated Systems; Vella, M. [Lawrence Berkeley Lab., CA (United States). Accelerator and Fusion Research Div.; Messick, C.; Reno, S.; Shideler, J. [National Semiconductor, West Jordan, UT (United States)

1994-04-01

305

Pressureless wafer bonding by turning hillocks into abnormal grain growths in Ag films  

NASA Astrophysics Data System (ADS)

We demonstrate pressureless wafer bonding using silver abnormal grain growth caused by stress migration at 250 C, which is very low for a direct solid-state bonding temperature. The bonding achieved a die-shear strength of more than 50 MPa, which exceeds the fracture toughness of Si wafer. Various deposition temperatures for the silver films, i.e., initial residual stress, reveal that the bonding process is driven by thermomechanical stress. Abnormal grain growth is induced at the contact interface instead of hillocks growing on the film surface. Pressureless wafer bonding can be applied to advanced devices such as thin-wafer multi-chip integrations.

Oh, Chulmin; Nagao, Shijo; Kunimune, Teppei; Suganuma, Katsuaki

2014-04-01

306

Improved quality control of silicon wafers using novel off-line air pocket image analysis  

NASA Astrophysics Data System (ADS)

Air pockets (APK) occur randomly in Czochralski (Cz) grown silicon (Si) crystals and may become included in wafers after slicing and polishing. Previously the only APK of interest were those that intersected the front surface of the wafer and therefore directly impacted device yield. However mobile and other electronics have placed new demands on wafers to be internally APK-free for reasons of thermal management and packaging yield. We present a novel, recently patented, APK image processing technique and demonstrate the use of that technique, off-line, to improve quality control during wafer manufacturing.

Valley, John F.; Sanna, M. Cristina

2014-08-01

307

The optimization of CD uniformity and measurement on mask and wafer  

NASA Astrophysics Data System (ADS)

As pattern size is shrinking, required mask CD specification is tighter and its effect on wafer patterning is more severe. To enhance the device performance, wafer CD uniformity should be enhanced and controlled by mask global CD uniformity. Mask global CD uniformity usually can be enhanced by mask process and optimal fogging effect correction. To enhance the mask global CD uniformity on mask, resist process and FEC (Fogging Effect Correction), reliable CD measurement tool and methods are necessary. Recently, group CD using OCD(Spectroscopic Ellipsometer) or AIMS(Aerial Image Measurement and Simulation) is used to represent global CD variation on mask. These methods are removing local CD variation on mask. Because local CD variation on wafer is large compared with the effect of local CD variation of mask, global CD uniformity can be measured with suppressed local CD variation [1]. In this paper, local CD variation of mask and wafer is evaluated, and area CD and smoothing methods are used to measure CD on mask and wafer, and the correlation of global CD of mask and field CD of wafer are evaluated. By these methods, CD measurement repeatability can be enhanced to get closer correlation of mask and wafer. Close correlation makes fine CD correction on mask to get better field CD uniformity on wafer. And the repeatability of field to field CD uniformity of wafer is evaluated according to measurement tool of CD-SEM and scatterometry.

Choi, Yongkyoo; Kim, Munsik; Han, Oscar

2007-05-01

308

True wafer temperature during metallization in physical vapor deposition cluster tools  

NASA Astrophysics Data System (ADS)

Aluminum metallization is an important process for planarization and interconnect applications. Wafer temperature during deposition is one of the key parameter determining film properties such as reflectivity and resistivity. Results of experiments carried out in order to characterize the thermal behavior of product wafers during physical vapor deposition, primarily aluminum and wafer degas will be presented. The effects of back and front side depositions, backside gas pressure and plasma power level on deposition temperature are all investigated. The utility of real time in-situ temperature monitoring on every product wafer in all deposition chambers within a cluster tool and the advantages provided in terms of process monitoring are discussed.

Adel, Michael E.; Mangan, Shmuel; Grunes, Howard; Parkhe, Vijay

1994-09-01

309

Determination of wafer center position during the transfer process by using the beam-breaking method  

NASA Astrophysics Data System (ADS)

A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human-machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions.

Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

2014-09-01

310

Creating a single twin boundary between two CdTe (111) wafers with controlled rotation angle by wafer bonding  

SciTech Connect

The single twin boundary with crystallographic orientation relationship (1{sup }1{sup }1{sup })//(111) [01{sup }1]//[011{sup }] was created by wafer bonding. Electron diffraction patterns and high-resolution transmission electron microscopy images demonstrated the well control of the rotation angle between the bonded pair. At the twin boundary, one unit of wurtzite structure was found between two zinc-blende matrices. High-angle annular dark-field scanning transmission electron microscopy images showed Cd- and Te-terminated for the two bonded portions, respectively. The I-V curve across the twin boundary showed increasingly nonlinear behavior, indicating a potential barrier at the bonded twin boundary.

Sun, Ce; Lu, Ning; Wang, Jinguo; Lee, Jihyung; Peng, Xin; Kim, Moon J., E-mail: moonkim@utdallas.edu [Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, Texas 75080 (United States); Klie, Robert F. [Department of Physics, University of Illinois at Chicago, Chicago, Illinois 60607 (United States)] [Department of Physics, University of Illinois at Chicago, Chicago, Illinois 60607 (United States)

2013-12-16

311

Development of GaN wafers via the ammonothermal method  

NASA Astrophysics Data System (ADS)

This paper reviews the current progress of ammonothermal growth at SixPoint Materials and discusses some of the remaining challenges to commercialize the technology. The mass production of the ammonothermal grown wafers of GaN for high power devices has substantial commercial potential but is currently limited by two problems: impurities which lead to semitransparent coloration and stress in the crystals which leads to cracking. To improve the coloration, it is important to understand and reduce the impurities in the crystal. Oxygen impurities were found to be the primary source of coloration. By reducing the oxygen impurities the absorption coefficient at 450 nm was improved to 3.9 cm-1 yielding semitransparent crystals. The second and more serious issue is a cracking that occurs when thick boules are produced. Currently we routinely produce ammonothermal growth over a millimeter in thickness without any cracking. However, as the thickness increases cracks develop. From a production viewpoint, the production of thick crystals is beneficial since it allows a single wafer to be processed into many. By improving a variety of parameters, the crack density was reduced and the maximum crack-free growth increased from 1 mm to 2.6 mm.

Letts, Edward; Hashimoto, Tadao; Hoff, Sierra; Key, Daryl; Male, Keith; Michaels, Mathew

2014-10-01

312

Process Performance of Optima XEx Single Wafer High Energy Implanter  

NASA Astrophysics Data System (ADS)

To meet the process requirements for well formation in future CMOS memory production, high energy implanters require more robust angle, dose, and energy control while maintaining high productivity. The Optima XEx high energy implanter meets these requirements by integrating a traditional LINAC beamline with a robust single wafer handling system. To achieve beam angle control, Optima XEx can control both the horizontal and vertical beam angles to within 0.1 degrees using advanced beam angle measurement and correction. Accurate energy calibration and energy trim functions accelerate process matching by eliminating energy calibration errors. The large volume process chamber and UDC (upstream dose control) using faraday cups outside of the process chamber precisely control implant dose regardless of any chamber pressure increase due to PR (photoresist) outgassing. An optimized RF LINAC accelerator improves reliability and enables singly charged phosphorus and boron energies up to 1200 keV and 1500 keV respectively with higher beam currents. A new single wafer endstation combined with increased beam performance leads to overall increased productivity. We report on the advanced performance of Optima XEx observed during tool installation and volume production at an advanced memory fab.

Kim, J. H.; Yoon, Jongyoon; Kondratenko, S.; David, J.; Rubin, L. M.; Jang, I. S.; Cha, J. C.; Joo, Y. H.; Lee, A. B.; Jin, S. W.

2011-01-01

313

Patterning of photocleavable zwitterionic polymer brush fabricated on silicon wafer.  

PubMed

Brushes of a polymer, namely poly(carboxymethylbetaine) (PCMB), were fabricated on silicon wafers by reversible addition-fragmentation chain-transfer (RAFT) polymerization using a surface-confined RAFT agent having an aromatic group at its bottom. The polymer brush showed effective suppression of the non-specific adsorption of bovine serum albumin (BSA) and adhesion of fibroblasts (3T3 cells). In contrast, BSA and 3T3 cells significantly adsorbed on and adhered to positively or negatively charged polymer brushes fabricated by the same procedure. Upon UV irradiation at 193nm, the thickness of the PCMB brush with an aromatic group at its bottom decreased significantly whereas PCMB prepared using a surface-confined RAFT agent without an aromatic group needed a much higher irradiation dose to afford a comparable decrease in thickness. These results indicate a preferential cleavage of the PCMB brush due to photodecomposition of the phenyl group at the bottom. BSA and 3T3 cells non-specifically adsorbed on and adhered to the UV irradiation-induced hollow spaces, respectively. Furthermore, a designed pattern with a resolution of 5?m was successfully made on the PCMB brush above the silicon wafer by simple UV irradiation. These results suggest that the surface-confined aromatic RAFT agent will be quite useful for simple photolithography in biomedical fields. PMID:25466462

Kamada, Tomohiro; Yamazawa, Yuka; Nakaji-Hirabayashi, Tadashi; Kitano, Hiromi; Usui, Yuki; Hiroi, Yoshiomi; Kishioka, Takahiro

2014-11-01

314

A Progl-am for Simulation of Semiconductol-Wafer Fabrication  

E-print Network

to analyze issues such as fak-'out design. capacity analysis, production forecasts. and fab start in a clean room environmenl since even the smallest dust particle can e on a chip. Wafers follow e s c i s e q u e n c e of process ;teps. which transform a blank wafer

Resende, Mauricio G. C.

315

Damage Identification in Aging Aircraft Structures with Piezoelectric Wafer Active Sensors  

E-print Network

and increases safety and availability of military and commercial aircraft. Although the incor- poration of IVHMDamage Identification in Aging Aircraft Structures with Piezoelectric Wafer Active Sensors VICTOR: Piezoelectric wafer active sensors can be applied to aging aircraft structures to monitor the onset and progress

Giurgiutiu, Victor

316

Manufacture and Metrology of 300 mm Silicon Wafers with Ultra-Low Thickness Variation  

NASA Astrophysics Data System (ADS)

With the evolution of exposure tools for optical lithography towards larger numerical apertures, the semiconductor industry expects continued demand for improved wafer flatness at the exposure site. The allowable site flatness for 300 mm wafers is expected to be less than 45 nm by 2010 and it may be as low as 25 nm by 2015 according to the International Technology Roadmap for Semiconductors (ITRS 2006). This requires wafers with low thickness variation and presents a challenge for both wafer polishing and metrology tools, which must be capable of meeting the specifications. We report the results of fabricating 300 mm silicon wafers with very low thickness variation using magnetorheological finishing (MRF), a deterministic subaperture finishing process. The wafer thickness metrology, which guided the finishing process, was provided by an infrared interferometer developed at the National Institute of Standards and Technology (NIST). The finishing method in combination with the interferometric wafer metrology enabled the fabrication of 300 mm silicon wafers with a total thickness variation (TTV) of about 40 nm, and between 10 nm and 15 nm thickness variation at 25 mm25 mm exposure sites.

Griesmann, Ulf; Wang, Quandou; Tricard, Marc; Dumas, Paul; Hall, Christopher

2007-09-01

317

Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer Fabrication  

Microsoft Academic Search

This paper concerns performance modeling of semiconductor manufacturing operations. More specifically, it focuses on queueing network models for an analysis of wafer fabrication facilities. The congestion problems that plague wafer fabrication facilities are described in general terms, and several years' operating data from one particular facility are summarized. A simple queueing network model of that facility is constructed, and the

HONG CHEN; J. MICHAEL HARRISON; AVI MANDELBAUM; ANN VAN ACKERE; LAWRENCE M. WEIN

1988-01-01

318

3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces.  

E-print Network

3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces. Journal: 2008 Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces Jian-Qiang Lu1 , J. Jay Mc approaches to 3D integration using adhesive, metal, and metal/adhesive as the bonding interfaces

Salama, Khaled

319

Power and energy transduction analysis of piezoelectric wafer-active sensors for  

E-print Network

the damage of the structure is inferred from the changes in load and strain distributions measuredArticle Power and energy transduction analysis of piezoelectric wafer-active sensors for structural of power and energy transduction in piezoelectric wafer-active sensors (PWAS) for structural health

Giurgiutiu, Victor

320

Across wafer focus mapping and its applications in advanced technology nodes  

Microsoft Academic Search

The understanding of focus variation across a wafer is crucial to CD control (both ACLV and AWLV) and pattern fidelity on the wafer and chip levels. This is particularly true for the 65nm node and beyond, where focus margin is shrinking with the design rules, and is turning out to be one of the key process variables that directly impact

Gary Zhang; Stephen DeMoor; Scott Jessen; Qizhi He; Winston Yan; Sopa Chevacharoenkul; Venugopal Vellanki; Patrick Reynolds; Joe Ganeshan; Jan Hauschild; Marco Pieters

2006-01-01

321

Absolute micro-encoder using image obtained by ball lens assembled inside wafer  

Microsoft Academic Search

An absolute micro-encoder based on code imaging is demonstrated. As the lens for the code imaging, a ? 300 m ball lens is assembled inside the cavity between wafer-bonded Pyrex glass and suspensions inside a Si wafer. By designing the appropriate lens holder, the assembling accuracy of the ball lens can be of the same level as that of the

Minoru Sasaki; Fuki Nakai; Kazuhiro Hane; Kanji Yokomizo; Kazuhito Hori

2006-01-01

322

Micro crack detection of multi-crystalline silicon solar wafer using machine vision techniques  

Microsoft Academic Search

Purpose The detection of invisible micro cracks (?-cracks) in multi-crystalline silicon (mc-si) solar wafers is difficult because of the wafers' heterogeneously textured backgrounds. The difficulty is twofold. First, invisible ?-cracks must be visualized to imaging devices. Second, an image processing sequence capable of extracting ?-cracks from the captured images must be developed. The purpose of this paper is to

Yih-Chih Chiou; Jian-Zong Liu; Yu-Teng Liang

2011-01-01

323

Detection of Cracks in Single-Crystalline Silicon Wafers Using Impact Testing  

Microsoft Academic Search

This thesis is about detection of cracks in single-crystalline silicon wafers by using a vibration method in the form of an impact test. The goal to detect cracks from vibration measurements introduced by striking the silicon wafer with an impact hammer. Such a method would reduce costs in the production of solar cells. It is an inexpensive, relatively simple method

Christina Hilmersson

2006-01-01

324

Crack detection in single-crystalline silicon wafers using impact testing  

Microsoft Academic Search

This paper presents acoustic measurements obtained by mechanically exciting vibratory modes in single-crystalline silicon wafers with hairline periphery cracks of different type and location. The data presented shows a dependence of natural frequencies, peak amplitudes and damping levels of four audio vibration modes in the frequency range up to 1000Hz on crack type and crack location. Data from defective wafers

C. Hilmersson; D. P. Hess; W. Dallas; S. Ostapenko

2008-01-01

325

Low temperature sacrificial wafer bonding for planarization after very deep etching  

Microsoft Academic Search

A new technique, at temperatures of 150C or 450C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of (1) polymer bonding

V. L. Spiering; J. W. Berenschot; M. Elwenspoek; J. H. J. Fluitman

1994-01-01

326

A Study of Lean Production Management in the Crystal Wafer Processing at TXC  

E-print Network

A Study of Lean Production Management in the Crystal Wafer Processing at TXC 032 034090324 2007-5-17 #12; "" #12; ABSTRACT Lean production mode is a management method at applying the lean production management principle in the crystal wafer process of TXC. Combining the lean

Wang, Ji

327

Wafer based aberration metrology for lithographic systems using overlay measurements on targets  

E-print Network

Wafer based aberration metrology for lithographic systems using overlay measurements on targets projection system from wafer metrology data. For this, new types of phase-shift gratings (PSG) are introduced metrology tool. In this way, the overlay error can be used as a measurand based on which the phase

328

Characterization of Piezoelectric Wafer Active Sensors Victor Giurgiutiu* and Andrei N. Zagrai  

E-print Network

, these piezoelectric wafers act as both sensors and actuators. In addition, their frequency bandwidth is orders of magnitude larger than that of conventional modal analysis equipment. They can form sensor and actuator wafer to excite the structure and an array of PVDF film sensors to pick up the forced vibration response

Giurgiutiu, Victor

329

A full wafer dicing free dry release process for MEMS devices  

Microsoft Academic Search

This paper presents a full wafer, dicing free, dry release process using hydrofluoric acid (HF) vapour phase etching (VPE) for MEMS sensors and actuators fabricated using silicon on insulator (SOI) wafers. It is particularly beneficial to MEMS sensors whose performance benefits from a large proof mass, for example accelerometers and gyroscopes. Such a fabrication method was first proposed by Overstolz

I. Sari; I. Zeimpekis; M. Kraft

2010-01-01

330

Computationally efficient modeling of wafer temperatures in a low-pressure chemical vapor deposition furnace  

Microsoft Academic Search

A new thermal model is developed to predict wafer temperatures within a hot-wall low pressure chemical vapor deposition furnace based on the furnace wall temperatures as measured by thermocouples. Based on an energy balance of the furnace system, this model is a transformed linear model which captures the nonlinear relationship between the furnace wall temperature distribution and the wafer temperature

Qinghua He; S. Joe Qin; Anthony J. Toprac

2003-01-01

331

Iron detection in polished and epitaxial silicon wafers using generation lifetime measurements  

Microsoft Academic Search

For iron detection in silicon, minority carrier diffusion length measurements are often used. These methods analyze only the bulk properties of the wafer and therefore failed in the case of epitaxial wafers due to the disturbing influence of the highly doped substrate. A technique is presented for the determination of the iron content in epitaxial as well as in polished

Guenther Obermeier; Diethard Huber

1997-01-01

332

UNCERTAINTY IN THE TEMPERATURE OF SILICON WAFERS MEASURED BY RADIATION THERMOMETRY BASED UPON A POLARIZATION TECHNIQUE  

Microsoft Academic Search

The emissivity behaviour of a silicon wafer under various conditions was theoretically and experimentally investigated. As a result, the quantitative relationship between the ratio of p-polarized radiance to s- polarized one, and polarized emissivities was obtained irrespective of the emissivity change of wafers due to the oxide film thickness under the wide variations of resistivity. Based on the result, we

Tohru Iuchi; Atsushi Gogami

333

An algebraic expression to count the number of chips on a wafer  

Microsoft Academic Search

Most chip-counting algorithms use the Pythagorean theorem; in effect, a grid of chips is superimposed over the wafer, and the radial distance from the center of the water to the outermost vertex of each potential chip site is computed. Only those chips are counted for which this radial distance is less than the effective radius of the wafer. To minimize

A. V. Ferris-Prabhu

1989-01-01

334

Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs  

E-print Network

Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs J Montopolis Drive, Austin TX 78741 Abstract -- Electrical and mechanical impacts of wafer bonding and thinning structures. In addition to the bonding and thinning required for a two-level 3D IC stack, an additional

Salama, Khaled

335

Modified Roberts-Langenbeck test for measuring thickness and refractive index variation of silicon wafers.  

PubMed

We describe a method to simultaneously measure thickness variation and refractive index homogeneity of 300 mm diameter silicon wafers using a wavelength-shifting Fizeau interferometer operating at 1550 nm. Only three measurements are required, corresponding to three different cavity configurations. A customized phase shifting algorithm is used to suppress several high order harmonics and minimize intensity sampling errors. The new method was tested with both silicon and fused silica wafers and measurement results proved to be highly repeatable. The reliability of the method was further verified by comparing the measured thickness variation of a 150 mm diameter wafer to a measurement of the wafer flatness after bonding the wafer to an optical flat. PMID:23037060

Park, Jungjae; Chen, Lingfeng; Wang, Quandou; Griesmann, Ulf

2012-08-27

336

High performance LWIR microbolometer with Si/SiGe quantum well thermistor and wafer level packaging  

NASA Astrophysics Data System (ADS)

An uncooled microbolometer with peak responsivity in the long wave infrared region of the electromagnetic radiation is developed at Sensonor Technologies. It is a 384 x 288 focal plane array with a pixel pitch of 25?m, based on monocrystalline Si/SiGe quantum wells as IR sensitive material. The high sensitivity (TCR) and low 1/f noise are the main performance characteristics of the product. The frame rate is maximum 60Hz and the output interface is digital (LVDS). The quantum well thermistor material is transferred to the read-out integrated circuit (ROIC) by direct wafer bonding. The ROIC wafer containing the released pixels is bonded in vacuum with a silicon cap wafer, providing hermetic encapsulation at low cost. The resulting wafer stack is mounted in a standard ceramic package. In this paper the architecture of the pixels and the ROIC, the wafer packaging and the electro-optical measurement results are presented.

Roer, Audun; Lapadatu, Adriana; Bring, Martin; Wolla, Erik; Hohler, Erling; Kittilsland, Gjermund

2011-11-01

337

Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint  

SciTech Connect

Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

Johnston, S.; Yan, F.; Zaunbracher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

2011-07-01

338

Multiple-surface interferometry of highly reflective wafer by wavelength tuning.  

PubMed

The surface shape and optical thickness variation of a lithium niobate (LNB) wafer were measured simultaneously using a wavelength-tuning interferometer with a new phase-shifting algorithm. It is necessary to suppress the harmonic signals for testing a highly reflective sample such as a crystal wafer. The LNB wafer subjected to polishing, which is in optical contact with a fused-silica (FS) supporting plate, generates six different overlapping interference fringes. The reflectivity of the wafer is typically 15%, yielding significant harmonic signals. The new algorithm can flexibly select the phase-shift interval and effectively suppress the harmonic signals and crosstalk. Experimental results indicated that the optical thickness variation of the LNB wafer was measured with an accuracy of 2 nm. PMID:25321495

Kim, Yangjin; Hibino, Kenichi; Hanayama, Ryohei; Sugita, Naohiko; Mitsuishi, Mamoru

2014-09-01

339

Chemical strategies for die/wafer submicron alignment and bonding.  

SciTech Connect

This late-start LDRD explores chemical strategies that will enable sub-micron alignment accuracy of dies and wafers by exploiting the interfacial energies of chemical ligands. We have micropatterned commensurate features, such as 2-d arrays of micron-sized gold lines on the die to be bonded. Each gold line is functionalized with alkanethiol ligands before the die are brought into contact. The ligand interfacial energy is minimized when the lines on the die are brought into registration, due to favorable interactions between the complementary ligand tails. After registration is achieved, standard bonding techniques are used to create precision permanent bonds. We have computed the alignment forces and torque between two surfaces patterned with arrays of lines or square pads to illustrate how best to maximize the tendency to align. We also discuss complex, aperiodic patterns such as rectilinear pad assemblies, concentric circles, and spirals that point the way towards extremely precise alignment.

Martin, James Ellis; Baca, Alicia I.; Chu, Dahwey; Rohwer, Lauren Elizabeth Shea

2010-09-01

340

MEMS feedback control using through-wafer optical device monitoring  

NASA Astrophysics Data System (ADS)

As microelectromechanical systems (MEMS) become widely implemented, the application of closed-loop control methods to MEMS will lead to higher degrees of certainty and reliability of microelectromechanical operation in physically demanding environments. By including planar diffractive optics in these systems, an optical method of determining MEMS microstructure position that is fully decoupled from the means of mechanical actuation can be realized. This paper presents the result of initial research evaluating both open and closed-loop nonlinear proportional-integral-differential (PID) control routines using a 1.3 micrometers wavelength through-wafer free-space optical probe to obtain a position signal from a lateral comb resonator fabricated using Chronos Integrated Microsystems' Multi-User MEMS Process service. The implementation of sliding control methods is illustrated through simulation results, and the design considerations for a proposed integrated optical monitoring architecture is presented.

Dawson, Jeremy M.; Wang, Limin; Chen, Jingdong; Famouri, Parviz F.; Hornak, Lawrence A.

2000-08-01

341

Microhardness of sputter-deposited zirconia films on silicon wafers  

SciTech Connect

Calcia-stabilized zirconia films were deposited on the surface of silicon <111> wafers using radio frequency (rf) magnetron sputter deposition. Deposition was conducted at substrate temperatures that varied in the range of 80--900 C. X-ray diffractometry results showed that all the films consisted of cubic zirconia. The fracture surface morphology and etched surfaces of the films were studied using scanning electron microscopy (SEM). Depending on the deposition temperature, the structure of the film was either columnar or equiaxed. The transition temperature from the columnar structure to the equiaxed structure was at a ratio of deposition temperature to melting temperature of {approximately}0.42. The microhardness of the films was evaluated using a developed model that is based on the plastic zone analysis below a diamond (Vickers) indentor. From this model, the microhardness was found to increase as the deposition temperature increased, which was probably because the hardness of ceramic materials decreases as the defect concentration increases.

Pakala, M.; Walls, H.; Lin, R.Y. [Univ. of Cincinnati, OH (United States). Dept. of Materials Science and Engineering

1997-06-01

342

A Wafer Transfer Technology for MEMS Adaptive Optics  

NASA Technical Reports Server (NTRS)

Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

Yang, Eui-Hyeok; Wiberg, Dean V.

2001-01-01

343

Effect of lubricant environment on saw damage in silicon wafers  

NASA Technical Reports Server (NTRS)

The chemomechanical effect of lubricant environments on the inner diameter (ID) sawing induced surface damage in Si wafers was tested for four different lubricants: water, dielectric oil, and two commercial cutting solutions. The effects of applying different potential on Si crystals during the sawing were also tested. It is indicated that the number and depth of surface damage are sensitive to the chemical nature of the saw lubricant. It is determined that the lubricants that are good catalysts for breaking Si bonds can dampen the out of plane blade vibration more effectively and produce less surface damage. Correlations between the applied potential and the depth of damage in the dielectric oil and one of the commercial cutting solutions and possible mechanisms involved are discussed.

Kuan, T. S.; Shih, K. K.; Vanvechten, J. A.; Westdorp, W. A.

1982-01-01

344

Long persistent near infrared luminescence nanoprobes LiGa5O8:Cr3+-PEG-OCH3 for in vivo imaging  

NASA Astrophysics Data System (ADS)

The Cr3+-doped LiGa5O8 nanoparticles (LGNPs) with long-persistent near-infrared phosphorescence were obtained through a sol-gel approach followed by heat treatment at 800 C in air. The obtained results reveal that the nanoparticles with an average diameter of 100 nm are well defined and have pure structure of LiGa5O8. After illumination for 3 min using a 254 nm UV lamp, the LGNPs exhibit strong near-infrared peak at ca. 720 nm belonging to tissue transparency window which can last for more than 1 h. Via surface modified with PEG-5000-OCH3, the LGNPs-PEG-OCH3 exhibit excellent biocompatibility and low toxicity. Under in vitro pre-excitation using a 254 nm UV lamp for 3 min, the in vivo distribution of the LGNPs-PEG-OCH3 in the abdomen can be detected in real time for more than 1 h. All the results indicate that the LGNPs-PEG-OCH3 can be used as potential nanoprobes to realize in vivo, real time and long time imaging with high sensitivity.

Fu, Xiaoyan; Liu, Chunlin; Shi, Junpeng; Man, Huizi; Xu, Jia; Zhang, Hongwu

2014-09-01

345

Infrared differential interference contrast microscopy for overlay metrology on 3D-interconnect bonded wafers  

NASA Astrophysics Data System (ADS)

Overlay metrology for stacked layers will be playing a key role in bringing 3D IC devices into manufacturing. However, such bonded wafer pairs present a metrology challenge for optical microscopy tools by the opaque nature of silicon. Using infrared microscopy, silicon wafers become transparent to the near-infrared (NIR) wavelengths of the electromagnetic spectrum, enabling metrology at the interface of bonded wafer pairs. Wafers can be bonded face to face (F2F) or face to back (F2B) which the stacking direction is dictated by how the stacks are carried in the process and functionality required. For example, Memory stacks tend to use F2B stacking enables a better managed design. Current commercial tools use single image technique for F2F bonding overlay measurement because depth of focus is sufficient to include both surfaces; and use multiple image techniques for F2B overlay measurement application for the depth of focus is no longer sufficient to include both stacked wafer surfaces. There is a need to specify the Z coordinate or stacking wafer number through the silicon when visiting measurement wafer sites. Two shown images are of the same (X, Y) but separate Z location acquired at focus position of each wafer surface containing overlay marks. Usually the top surface image is bright and clear; however, the bottom surface image is somewhat darker and noisier as an adhesive layer is used in between to bond the silicon wafers. Thus the top and bottom surface images are further processed to achieve similar brightness and noise level before merged for overlay measurement. This paper presents a special overlay measurement technique, using the infrared differential interference contrast (DIC) microscopy technique to measure the F2B wafer bonding overlay by a single shot image. A pair of thinned wafers at 50 and 150 ?m thickness is bonded on top of a carrier wafer to evaluate the bonding overlay. It works on the principle of interferometry to gain information about the optical path length of the stacked wafers, to enhance the image contrast of overlay marks features even though they are locating in different Z plane. A two dimensional mirror-symmetric overlay marks for both top and bottom processing wafers is designed and printed in each die in order to know and realize the best achievable wafer to wafer bonding processing. A self-developed analysis algorithms is used to identify the overlay error between the stacking wafers and the interconnect structures. The experimental overlay results after wafer bonding including inter-die and intra-die analysis results will be report in the full paper. Correlation of overlay alignment offset data to electrical yield, provides an early indication of bonded wafer yield.

Ku, Yi-sha; Shyu, Deh-Ming; Lin, Yeou-Sung; Cho, Chia-Hung

2013-04-01

346

Lee, et al., "Wafer Nanotopography Effects..." MRS Spring Meeting April 20011 Brian Lee, Duane S. Boning (MIT)  

E-print Network

Jiang Sun (Philips Semiconductor) Michael Lacy (Lam Research) #12;Lee, et al., "Wafer Nanotopography EffectsLee, et al., "Wafer Nanotopography Effects..." MRS Spring Meeting ­ April 20011 Brian Lee, Duane S Shift in Tucson, AZ 100 nm -100 nm #12;Lee, et al., "Wafer Nanotopography Effects..." MRS Spring Meeting

Boning, Duane S.

347

Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers Used for PV Cells: Preprint  

SciTech Connect

As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay (uPCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

Guthrey, H.; Gorman, B.; Al-Jassim, M.

2011-07-01

348

Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers  

NASA Technical Reports Server (NTRS)

A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

Okojie, Robert S. (Inventor)

2002-01-01

349

Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010  

SciTech Connect

1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

Lorenz, A.

2011-06-01

350

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss  

PubMed Central

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180??m) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping. PMID:24820403

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-01-01

351

AWV: high-throughput cross-array cross-wafer variation mapping  

NASA Astrophysics Data System (ADS)

Minute variations in advanced VLSI manufacturing processes are well known to significantly impact device performance and die yield. These variations drive the need for increased measurement sampling with a minimal impact on Fab productivity. Traditional discrete measurements such as CDSEM or OCD, provide, statistical information for process control and monitoring. Typically these measurements require a relatively long time and cover only a fraction of the wafer area. Across array across wafer variation mapping ( AWV) suggests a new approach for high throughput, full wafer process variation monitoring, using a DUV bright-field inspection tool. With this technique we present a full wafer scanning, visualizing the variation trends within a single die and across the wafer. The underlying principle of the AWV inspection method is to measure variations in the reflected light from periodic structures, under optimized illumination and collection conditions. Structural changes in the periodic array induce variations in the reflected light. This information is collected and analyzed in real time. In this paper we present AWV concept, measurements and simulation results. Experiments were performed using a DUV bright-field inspection tool (UVision (TM), Applied Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and normal wafers. AWV and CDSEM results are presented to reflect CD variations within a memory array and across wafers.

Yeo, Jeong-Ho; Lee, Byoung-Ho; Lee, Tae-Yong; Greenberg, Gadi; Meshulach, Doron; Ravid, Erez; Levi, Shimon; Kan, Kobi; Shabtay, Saar; Cohen, Yehuda; Rotlevi, Ofer

2008-03-01

352

A self-priming, high performance, check valve diaphragm micropump made from SOI wafers  

NASA Astrophysics Data System (ADS)

In this paper, we describe a self-priming high performance piezoelectrically actuated check valve diaphragm micropump. The micropump was fabricated from three wafers: two silicon-on-insulator (SOI) wafers and one silicon wafer. A process named 'SOI/SOI wafer bonding and etching back followed by a second wafer bonding' was developed in order to make the core components of this device which included an inlet check valve, an outlet check valve, a diaphragm and a chamber. The movable structures of this device, i.e. the check valves and the diaphragm, were fabricated from the device layers of the two bonded SOI wafers. Taking advantages of SOI wafer technology and etch-stop layers, the vertical parameters of the movable structures were precisely controlled in fabrication. The micropump was self-priming without any pre-filling process. The pumping rate of the micropump was linearly adjustable from 0 to 650l m min-1 by adjusting frequency. The maximum pumping rate was 860 l min-1 and the maximum pumping pressure was approximately 10.5 psi. The power consumption of the device was less than 1.2 mW.

Kang, Jianke; Mantese, Joseph V.; Auner, Gregory W.

2008-12-01

353

CDU improvement with wafer warpage control oven for high-volume manufacturing  

NASA Astrophysics Data System (ADS)

Immersion lithography has been developed for 45nm technology node generation during the last several years. Currently, IC manufacturers are moving to high volume production using immersion lithography. Due to the demand of IC manufactures, as the critical dimension (CD) target size is shrinking, there are more stringent requirements for CD control. Post Exposure Bake (PEB) process, which is the polymer de-protection process after exposure, is one of the important processes to control the CD in the 193nm immersion lithography cluster. Because of the importance of the PEB process for CD uniformity, accurate temperature control is a high priority. Tokyo Electron LTD (TEL) has been studying the temperature control of PEB plates. From our investigation, total thermal history during the PEB process is a key point for controlling intra wafer and inter wafer CD [1]. Further, production wafers are usually warped, which leads to a nonuniform thermal energy distribution during the PEB process. So, it is necessary to correct wafer warpage during the baking process in order to achieve accurate CD control on production wafers. TEL has developed a new PEB plate for 45nm technology node mass production, which is able to correct wafer warpage. The new PEB plate succeeded in controlling the wafer temperature on production wafers using its warpage control function. In this work, we evaluated CD process capability using the wafer warpage control PEB plate, which is mounted on a CLEAN TRACKTM LITHIUS ProTM-i (TEL) linked with the latest immersion exposure tool. The evaluation was performed together with an IC manufacturer on their 45nm production substrates in order to determine the true performance in production.

Tomita, T.; Weichert, H.; Hornig, S.; Trepte, S.; Shite, H.; Uemura, R.; Kitano, J.

2009-03-01

354

Low temperature solder process to join a copper tube to a silicon wafer  

NASA Astrophysics Data System (ADS)

With the application for wafer level packages, which could be Complementary Metal-Oxide-Semiconductor (CMOS) based, and which requires a reduced atmosphere, a copper tube connection to a vacuum pump and the package is proposed. The method evaluated uses laser assisted brazing of a solder, to join the copper tube to a silicon wafer. The method was applied to a silicon wafer coated with a metallic interface to bond to the solder. The hermeticity of the joint was tested with a helium leak rate tester and the bonding energy thermal extent was verified with a thin layer of indium that melted wherever the substrate temperature rose above its melting temperature.

Versteeg, Christo; Scarpim de Souza, Marcio

2014-06-01

355

Wavelength control in fabrication of wafer fused VCSELs emitting in the 1310 nm waveband  

NASA Astrophysics Data System (ADS)

Emission wavelength setting of 1310nm-waveband VCSELs designed for coarse wavelength division multiplexing (CWDM) 4x10 Gbps fiber-optics transmission can be controlled thanks to the wafer fusion fabrication approach. This approach allows performing the cavity adjustment before bonding the distributed Bragg reflectors (DBRs) to the active cavity of the device. Cavity adjustment was performed by digital etching with nanometer precision and proves to be very effective in compensating for epitaxial growth thickness off-set relative to nominal design and thickness nonuniformity across the wafer. With this fabrication approach we reach on fused VCSEL wafers more than 90% yield of devices that fit the CWDM wavelength slots.

Sirbu, A.; Iakovlev, V.; Mereuta, A.; Caliman, A.; Suruceanu, G.; Mickovic, Z.; Kapon, Eli

2014-05-01

356

SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories  

NASA Astrophysics Data System (ADS)

Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

2010-05-01

357

Development of a fixed abrasive slicing technique (FAST) for reducing the cost of photovoltaic wafers  

SciTech Connect

This report examines a wafer slicing technique developed by Crystal Systems, Inc. that reduces the cost of photovoltaic wafers. This fixed, abrasive slicing technique (FAST) uses a multiwire bladepack and a diamond-plated wirepack; water is the coolant. FAST is in the prototype production stage and reduces expendable material costs while retaining the advantages of a multiwire slurry technique. The cost analysis revealed that costs can be decreased by making more cuts per bladepack and slicing more wafers per linear inch. Researchers studied the degradation of bladepacks and increased wirepack life. 21 refs.

Schmid, F. (Crystal Systems, Inc., Salem, MA (United States))

1991-12-01

358

W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas  

NASA Technical Reports Server (NTRS)

Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

1997-01-01

359

Laser cleaning of silicon wafers: mechanisms and efficiencies  

NASA Astrophysics Data System (ADS)

We report on experiments on the underlying physical mechanisms in the Dry-(DLC) and Steam Laser Cleaning (SLC) process. Using a frequency doubled, Q-switched Nd:YAG laser (FWHMequals8 ns), we removed polystyrene (PS) particles with diameters from 110-2000 nm from industrial silicon wafers by the DLC process. The experiments have been carried out both in ambient conditions as well as in high vacuum (10-6mbar) and the cleaned areas have been characterized by atomic force microscopy for damage inspection. Besides the determining the cleaning thresholds in laser fluence for a large interval of particle sizes we could show that particle removal in DLC is due to a combination of at least three effects: thermal substrate expansion, local substrate ablation due to field enhancement at the particle and explosive evaporation of absorbed humidity from the air. Which effect dominates the process is subject to the boundary conditions. For our laser parameters no damage free DLC was possible, i.e. whenever a particle was removed by DLC we damaged the substrate by local field enhancement. In our SLC experiments we determined the amount of superheating of a liquid layer adjacent to surfaces with controlled roughness that is necessary, in good agreement with theoretical predictions. Rough surfaces exhibited only a much smaller superheating.

Mosbacher, Mario; Bertsch, M.; Muenzer, H.-J.; Dobler, V.; Runge, B.-U.; Baeuerle, Dieter; Boneberg, Johannes; Leiderer, Paul

2002-02-01

360

Development of thin edgeless silicon pixel sensors on epitaxial wafers  

NASA Astrophysics Data System (ADS)

The paper reports on the development of novel p-on-n thin edgeless planar pixel sensors, compatible with ALICE front-end electronics, fabricated by FBK on epitaxial material. The focus of the activity is the minimization of the material budget required for hybrid pixel detectors. This goal has been addressed in two different stages. In the first one, planar pixel detectors fabricated on epitaxial wafers have been thinned and bonded to the readout chips. The second stage is described by the present paper: the `active edge' concept has been studied for the reduction of the dead area at the periphery of the devices. An overview of the key technological steps and of the electrical characterization of the fabricated sensors is given. In addition, the preliminary results on the static behavior of test sensors after neutron irradiation at different fluences (up to 2.5 1015 1 MeV-neq/cm2) are reported. The results demonstrate that these kinds of devices are a viable solution for the reduction of the material budget while maintaining the typical electrical characteristics expected from radiation silicon sensors.

Boscardin, M.; Bosisio, L.; Contin, G.; Giacomini, G.; Manzari, V.; Orzan, G.; Rashevskaya, I.; Ronchin, S.; Zorzi, N.

2014-09-01

361

Dual-illumination NIR system for wafer level defect inspection  

NASA Astrophysics Data System (ADS)

CdZnTe is a high efficiency, room temperature radiation detection material that has attracted great interesting in medical and security applications. CZT crystals can be grown by various methods. Particularly, CZT grown with the Transfer Heater Method (THM) method have been shown to have fewer defects and greater material uniformity. In this work, we developed a proof-of-concept dual lighting NIR imaging system that can be implemented to quickly and nondestructively screen CZT boule and wafers during the manufacturing process. The system works by imaging the defects inside CZT at a shallow depth of focus, taking a stack of images step by step at different depths through the sample. The images are then processed with in-house software, which can locate the defects at different depths, construct the 3D mapping of the defects, and provide statistical defect information. This can help with screening materials for use in detector manufacturing at an early stage, which can significantly reduce the downstream cost of detector fabrication. This inspection method can also be used to help the manufacturer understand the cause of the defect formation and ultimately improve the manufacturing process.

Williams, Yana; Harding, Kevin; Abramovich, Gil; Nafis, Christopher; Tkaczyk, Eric; Andreini, Kristian; Chen, Henry; Bindley, Glenn

2010-08-01

362

Design Of An Optical Linewidth Standard Reference Material For Wafers  

NASA Astrophysics Data System (ADS)

Optical linewidth measurements on patterned wafers are complicated by the wide variety of materials and correspondingly wide variation in optical parameters, complex refractive index and thickness, used in the manufacture of integrated circuits. It has been shown that in addition to linewidth, two key parameters, the normalized local reflectance R and the optical phase difference ? at the line edge, determine the characteristics of the optical image and, therefore, affect the accuracy and precision of linewidth measurements. Both of these parameters, R and ?, are dependent upon the illuminating wavelength or spectral bandpass and the coherence parameter of the optical system. To achieve the measurement precision and accuracy required for VLSI dimensions (e.g., 10% tolerance for 1-?m linewidths), it is necessary to control coherence, spectral bandpass, and image integrity as well as to achieve reproducible edge detection and focus criteria. When a system can be operated without further operator intervention despite changes in the materials being mea-sured, it is possible to calibrate the linewidth measurement system using a standard fabri-cated from only a few materials representing a range of image characteristics. The desirable characteristics of such a standard are discussed with respect to durability, edge definition, and equivalence of the image characteristics to materials used in the manufacture of ICs. A prototype design consisting of combinations of SiO2 and chromium layers on a silicon substrate is presented.

Nyyssonen, Diana

1982-10-01

363

Wafer-level self-packaged infrared microsensors  

NASA Astrophysics Data System (ADS)

One common requirement of microbolometers fabricated on both rigid and flexible substrates is the need for vacuum packaging to eliminate the thermal conductivity of air and achieve high performance. However, vacuum packaging of microbolometers is expensive and is a limiting factor in achieving truly low-cost uncooled infrared detection. Vacuum packing of microbolometers on flexible substrates requires a novel approach unless flexibility is to be sacrificed. This paper explores the vacuum packaging of microbolometers through self-packaging. In this case, the micromachined encapsulation in a vacuum cavity is investigated through computer simulation of microbolometers in flexible polyimide films and through the encapsulation of microbolometers on rigid Si substrates with a Si3N4 shell. In this manner, self packaged uncooled microbolometers were fabricated on a Si wafer with semiconducting yttrium barium copper oxide (YBCO) as the infrared sensing material. The self-packaged structure is designed such that it can be covered with a superstrate, yielding low stress in the flexible skin sensors and better detection figures of merit. The devices have demonstrated voltage responsivities over 103 V/W, detectivities above 106 cm Hz1/2/W and temperature coefficient of resistance around -3.3% K-1. Computer simulations using CoventorWare and MEMulator have been used to determine suitable materials for the process, the optimum design of a vacuum element and a streamlined process flow.

Mahmoud, Aamer; Dave, Aasutosh; Celik-Butler, Zeynep; Butler, Donald P.

2004-08-01

364

Room-temperature GaAs/InP wafer bonding with extremely low resistance  

NASA Astrophysics Data System (ADS)

Low-temperature direct wafer bonding is a promising technique for fabricating multijunction solar cells with more than four junctions in order to obtain high conversion efficiencies. However, it has been difficult to reduce the bond interface resistance between a GaAs-based subcell wafer and an InP-based subcell wafer. We found that a novel bonding structure comprising heavily Zn-doped (1 1019 cm?3) p+-GaAs and S-doped (3 1018 cm?3) n-InP had an interface resistance of 2.5 10?5 ?cm2, which is the lowest value ever reported. This result suggests that the newly developed room-temperature wafer bonding technique has high potential to realize high-efficiency multijunction solar cells.

Uchida, Shiro; Watanabe, Tomomasa; Yoshida, Hiroshi; Tange, Takashi; Arimochi, Masayuki; Ikeda, Masao; Dai, Pan; He, Wei; Ji, Lian; Lu, Shulong; Yang, Hui

2014-11-01

365

A study of defects on EUV mask using blank inspection, patterned mask inspection, and wafer inspection  

SciTech Connect

The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing. yet link data is available for understanding native defects on real masks. In this paper, a full-field EUV mask is fabricated to investigate the printability of various defects on the mask. The printability of defects and identification of their source from mask fabrication to handling were studied using wafer inspection. The printable blank defect density excluding particles and patterns is 0.63 cm{sup 2}. Mask inspection is shown to have better sensitivity than wafer inspection. The sensitivity of wafer inspection must be improved using through-focus analysis and a different wafer stack.

Huh, S.; Ren, L.; Chan, D.; Wurm, S.; Goldberg, K. A.; Mochi, I.; Nakajima, T.; Kishimoto, M.; Ahn, B.; Kang, I.; Park, J.-O.; Cho, K.; Han, S.-I.; Laursen, T.

2010-03-12

366

Low Loss, Finite Width Ground Plane, Thin Film Microstrip Lines on Si Wafers  

NASA Technical Reports Server (NTRS)

Si RFICs on standard, 2 Omega-cm. Si wafers require novel transmission lines to reduce the loss caused by the resistive substrate. One such transmission line is commonly called Thin Film Microstrip (TFMS), which is created by depositing a metallic ground plane, thin insulating layers, and the microstrip lines on the Si wafer. Thus, the electric fields are isolated from the Si wafer. In this paper, it is shown through experimental results that the ground plane of TFMS may be finite width and comparable to the strip width in size while still achieving low loss on 2 Omega-cm Si. Measured effective permittivity shows that the field interaction with the Si wafer is small.

Ponchak, George E.; Margomenos, Alexandros; Katehi, Linda P. B.

1999-01-01

367

Effect of wafer bow on electrostatic chucking and back side gas cooling  

NASA Astrophysics Data System (ADS)

Electrostatic chucks (ESCs) are used in the semiconductor industry to clamp wafers to a pedestal and combined with back side gas (BSG) cooling to control temperature during processing. The effect of wafer bow in an ESC/BSG system is studied theoretically and experimentally. An equilibrium model is developed that predicts the maximum allowed bow for initial chucking and the maximum BSG pressure once the wafer is chucked. Experimental chucking and BSG pressure data show the maximum initial bow that can be chucked agree with model predictions. Hysteresis in pressure versus flow data is also consistent with the model. The model does not predict some features of thin wafers with highly stressed films. However, deviations between the model and data in this nonlinear regime are expected. By combining the theory with the experimental data, a method to determine a safe BSG/ESC operating range is given.

Goodman, Daniel L.

2008-12-01

368

Rizatriptan wafer--sublingual vs. placebo at the onset of acute migraine.  

PubMed

Rizatriptan wafer is a 5HT1B/1D agonist for use in the acute treatment of migraine. It is a freeze-fried formulation, approved for oral administration, which dissolves on the tongue and is swallowed with saliva. In this study the efficacy of sublingually administered rizatriptan 10-mg wafer was evaluated in a randomized, double-blind, placebo-controlled, out-patient study involving 39 migraineurs. Patients were instructed to treat a migraine at the onset of pain in order to evaluate time of onset of pain relief and pain relief at 1 h. The average time to onset of relief was 25 min for patients treated with rizatriptan wafer and 27 min for patients treated with placebo. At 1 h, 50% of the patients receiving rizatriptan wafer and 50% of the patients receiving placebo experienced significant relief. Implications and potential reasons for a high placebo response are discussed. PMID:11075843

Klapper, J A; O'Connor, S

2000-07-01

369

Standardizing and improving test wafer processes : inventory optimization and a days of inventory pull system  

E-print Network

Over the past few years, the Intel Fab-17 facility has aggressively pursued lean methodology to reduce the manufacturing costs associated with its aging 200mm diameter wafer process. One area ripe with improvement opportunities ...

Johnson, David W. (David William), S.M. Massachusetts Institute of Technology

2009-01-01

370

Analysis of organic contaminants from silicon wafer and disk surfaces by thermal desorption-GC-MS  

NASA Astrophysics Data System (ADS)

Organic contaminants can affect semiconductor wafer processing including gate oxide integrity, polysilicon growth, deep ultraviolet photoresist line-width, and cleaning & etching steps. Organophosphates are known to counter dope silicon wafers. Organic contaminants in disk drives can cause failures due to stiction or buildup on the heads. Therefore, it is important to identify organic contaminants adsorbed on wafer or disk surfaces and find their sources so they can be either completely eliminated or at least controlled. Dynamic headspace TD-GC-MS (Thermal Desorption-Gas Chromatography-Mass Spectrometry) methods are very sensitive and can be used to identify organic contaminants on disks and wafers, in air, or outgassing from running drives or their individual components.

Camenzind, Mark J.; Ahmed, Latif; Kumar, Anurag

1999-03-01

371

On-wafer vector network analyzer measurements in the 220-325 Ghz frequency band  

NASA Technical Reports Server (NTRS)

We report on a full two-port on-wafer vector network analyzer test set for the 220-325 GHz (WR3) frequency band. The test set utilizes Oleson Microwave Labs frequency extenders with the Agilent 8510C network analyzer. Two port on-wafer measurements are made with GGB Industries coplanar waveguide (CPW) probes. With this test set we have measured the WR3 band S-parameters of amplifiers on-wafer, and the characteristics of the CPW wafer probes. Results for a three stage InP HEMT amplifier show 10 dB gain at 235 GHz [1], and that of a single stage amplifier, 2.9 dB gain at 231 GHz. The approximate upper limit of loss per CPW probe range from 3.0 to 4.8 dB across the WR3 frequency band.

Fung, King Man Andy; Dawson, D.; Samoska, L.; Lee, K.; Oleson, C.; Boll, G.

2006-01-01

372

Fab cycle time improvement through inventory control : a wafer starts approach  

E-print Network

Intel's Colorado Springs wafer fabrication facility, known internally as F23, has undertaken several initiatives to reduce cycle time including High Precision Maintenance (HPM), content reduction through the application ...

Ward, Matthew John

2007-01-01

373

Thermally stimulated luminescence in full-size 4H-SiC wafers  

NASA Astrophysics Data System (ADS)

We performed non-contact and non-destructive spatially resolved characterization of traps and recombination centres in two-inch-diameter p-type 4H-SiC wafers using thermally stimulated luminescence (TSL) and scanning room temperature photoluminescence (PL). The TSL glow-curve maximum is located at about 190 K for the Al-doped wafers and the TSL spectrum has a maximum at 1.8 eV, which coincides with the spectrum of the `red' PL band in the same crystal. The TSL intensity exhibits a noticeable inhomogeneity across the wafers. The spatial distribution shows a negative contrast compared to PL maps, indicating a variation of concentration of the TSL centres across the wafer. The origin of the centres is discussed.

Ostapenko, S.; Suleimanov, Yu. M.; Tarasov, I.; Lulu, S.; Saddow, S. E.

2002-12-01

374

In-Situ Measurement of Pressure and Friction During CMP of Contoured Wafers  

Microsoft Academic Search

In situ fluid film pressure and interfacial friction measurements during chemical mechanical planarization (CMP) are reported over a range of applied loads (27.6-41.4 kPA or 4-6 psi) and relative pad\\/wafer velocities . The slurry film pressure beneath contoured test wafers was measured using a novel experimental setup that enables dynamic data collection. The friction data have a repeatability of .

A. M. Scarfo; Vincent P. Manno; Chris B. Rogers; Sriram Anjur; Mansour Moinpour

2005-01-01

375

The Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics  

Microsoft Academic Search

Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconnect has been proposed as a useful technology for building ultra-compact MPPs since it provides a simplified mechanism for interconnecting stacked multichip substrates. This paper presents the offset cube, a new network topology designed to exploit the packaging benefits of through-wafer optical interconnect

W. Stephen Lacy; Jos L. Cruz-Rivera; D. Scott Wills

1998-01-01

376

Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom  

DOEpatents

An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL)

2008-11-18

377

Endpoint detectable plating through femtosecond laser drilled glass wafers for electrical interconnections  

Microsoft Academic Search

An endpoint detectable plating process to avoid over-electroplating was proposed and performed in this work. The technology was developed for fabrication of Pyrex glass wafer with electrical feed-throughs. Thin film of gold was deposited on the glass wafer prior to the femtosecond laser drilling. When the growing metal in the through-holes was contacted to the metal, a resistance between the

Takashi Abe; Xinghua Li; Masayoshi Esashi

2003-01-01

378

Piezoelectric Wafer Embedded Active Sensors for Aging Aircraft Structural Health Monitoring  

Microsoft Academic Search

Piezoelectric wafer active sensors may be applied on aging aircraft structures to monitor the onset and progress of structural damage such as fatigue cracks and corrosion. The state of the art in piezoelectric-wafer active sensors structural health monitoring and damage detection is reviewed. Methods based on (a) elastic wave propagation and (b) the Electro-Mechanical (E\\/M) impedance technique are cited and

Victor Giurgiutiu; Andrei Zagrai; Jing Jing Bao

2002-01-01

379

Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom  

DOEpatents

An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

Lin, YuPo J. (Naperville, IL); Henry, Michael P. (Batavia, IL); Snyder, Seth W. (Lincolnwood, IL)

2011-07-12

380

A Novel Method of Electron Beam Recording on a Si Wafer  

NASA Astrophysics Data System (ADS)

A p-type Si wafer covered with a SiO2 film is proposed as a recording medium. When an electron beam of 20 keV irradiates the wafer at a dosage of 2 10-7 C/cm2 or more, surface photovoltage decreases at the points irradiated by the electron beam. Thus, Roman characters recorded with the electron beam have been successfully interpreted with an improved flying-spot scanner.

Munakata, Chusuke; Miyazaki, Masaru

1981-04-01

381

In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation  

PubMed Central

Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-nave adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

2013-01-01

382

Influence of the Viscoelastic Properties of the Polyimide Dielectric Coating on the Wafer Warpage  

NASA Astrophysics Data System (ADS)

Polyimide is widely used as the dielectric material in wafer level packaging. One potential problem with its application is the warpage and stress generated in the curing process. This paper investigated the material properties of polyimide and its influence on the wafer warpage. The viscoelastic properties of polyimide film were measured and a mathematical model of the properties was developed. Finite element analysis of the wafer warpage was performed and this indicates that the viscoelastic material model gave the best prediction. To better understand the causation of the warpage, curvature evolution of the polyimide-coated silicon wafer during its curing process was measured by a multi-beam optical sensor system. It was found that the warpage was mainly induced by the coefficient of thermal expansion mismatch and that the cure shrinkage of polyimide had little effect. Additionally, the effect of the cooling rate on the wafer warpage was also studied. Both simulation and experiment results showed that a slower cooling rate in the temperature range around the glass transition temperature ( T g) of polyimide will help to reduce the final wafer warpage.

Zhu, Chunsheng; Ning, Wenguo; Xu, Gaowei; Luo, Le

2014-09-01

383

Wafer Bonding and Layer Transfer Processes for High Efficiency Solar Cells  

SciTech Connect

A wafer-bonded four-junction cell design consisting of InGaAs, InGaAsP, GaAs, and Ga0.5In0.5P subcells that could reach one-sun AM0 efficiencies of 35.4% is described. The design relies on wafer-bonding and layer transfer for integration of non-lattice-matched subcells. Wafer bonding and layer transfer processes have shown promise in the fabrication of InP/Si epitaxial templates for growth of the bottom InGaAs and InGaAsP subcells on a Si support substrate. Subsequent wafer bonding and layer transfer of a thin Ge layer onto the lower subcell stack can serve as an epitaxial template for GaAs and Ga0.5In0.5P subcells. Additionally, wafer bonded Ge/Si substrates offer the possibility to improve the mechanical performance of existing triple-junction solar cell designs, while simultaneously reducing their cost. Present results indicate that optically active III/V compound semiconductors can be grown on both Ge/Si and InP/Si heterostructures. Current-voltage electrical characterization of the interfaces of these structures indicates that both InP/Si and Ge/Si interfaces have specific resistances lower than 0.1 W?cm2 for heavily doped wafer bonded interfaces, enabling back surface power extraction from the finished cell structure.

Zahler, J. M.; Fontcuberta i Morral, A.; Ahn, C. G.; Atwater, H. A.; Wanlass, M. W.; Chu, C.; Iles, P. A.

2003-05-01

384

Nonuniformities of electrical resistivity in undoped 6H-SiC wafers  

SciTech Connect

Chemical elemental analysis, temperature-dependent Hall measurements, deep-level transient spectroscopy, and contactless resistivity mapping were performed on undoped semi-insulating (SI) and lightly nitrogen-doped conducting 6H-SiC crystals grown by physical vapor transport (PVT). Resistivity maps of commercial semi-insulating SiC wafers revealed resistivity variations across the wafers between one and two orders of magnitude. Two major types of variations were identified. First is the U-shape distribution with low resistivity in the center and high in the periphery of the wafer. The second type had an inverted U-shape distribution. Secondary-ion-mass spectrometry measurements of the distribution of nitrogen concentration along the growth axis and across the wafers sliced from different locations of lightly nitrogen-doped 6H-SiC boules were conducted. The measured nitrogen concentration gradually decreased along the growth direction and from the center to the periphery of the wafers. This change gives rise to the U-like distribution of resistivity in wafers of undoped SI-SiC. The concentrations of deep electron traps exhibited similar dependence. Compensation of nitrogen donors by these traps can result in the inverted U-like distribution of resistivity. Possible reasons for the observed nonuniformities include formation of a (0001) facet in PVT growth coupled with orientation-dependent nitrogen incorporation, systematic changes of the gas phase composition, and increase of the deposition temperature during boule growth.

Li, Q.; Polyakov, A.Y.; Skowronski, M.; Sanchez, E.K.; Loboda, M.J.; Fanton, M.A.; Bogart, T.; Gamble, R.D. [Department of Materials Science and Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania 15213 (United States); Dow Corning Compound Semiconductor, Midland, Michigan 48686 (United States); Pennsylvania State University Electro-Optics Center, 559A Freeport Road, Freeport, Pennsylvania 16229 (United States)

2005-06-01

385

Relationship between coefficient of friction and surface roughness of wafer in nanomachining process  

NASA Astrophysics Data System (ADS)

Fixed abrasive polishing technology can obtain a nanoscale surface and is one of the future nano machining directions. The coefficient of friction between the pad and the wafer in the polishing process can influence on the surface quality of the wafer. The relationship between the coefficient of friction and surface roughness of the wafer was investigated to improve the efficiency and surface quality. Based on the Florida model, the adhesion, asperity plough and abrasive plough from the pad in the polishing process was analyzed. The friction force per unit area was calculated by the properties of the pad and wafer. Based on the rod model, the actual contact area was calculated by the surface roughness and the properties of the pad and wafer. The relational model between the surface roughness of the wafer and the friction coefficient was established. The model was verified by the experiments of fixed abrasive polishing of BK7 glass. When the friction coefficient is less than 1.9, the data of the experiment and theory match very well in the comparison process.

Li, Jun; Xia, Lei; Li, Pengpeng; Zhu, Yongwei; Sun, Yuli; Zuo, Dunwen

2013-08-01

386

High aspect ratio nano-fabrication of photonic crystal structures on glass wafers using chrome as hard mask  

NASA Astrophysics Data System (ADS)

Wafer-scale nano-fabrication of silicon nitride (Si x N y ) photonic crystal (PhC) structures on glass (quartz) substrates is demonstrated using a thin (30 nm) chromium (Cr) layer as the hard mask for transferring the electron beam lithography (EBL) defined resist patterns. The use of the thin Cr layer not only solves the charging effect during the EBL on the insulating substrate, but also facilitates high aspect ratio PhCs by acting as a hard mask while deep etching into the Si x N y . A very high aspect ratio of 10:1 on a 60 nm wide grating structure has been achieved while preserving the quality of the flat top of the narrow lines. The presented nano-fabrication method provides PhC structures necessary for a high quality optical response. Finally, we fabricated a refractive index based PhC sensor which shows a sensitivity of 185 nm per RIU.

Nazmul Hossain, Md; Justice, John; Lovera, Pierre; McCarthy, Brendan; O'Riordan, Alan; Corbett, Brian

2014-09-01

387

High aspect ratio nano-fabrication of photonic crystal structures on glass wafers using chrome as hard mask.  

PubMed

Wafer-scale nano-fabrication of silicon nitride (Si x N y ) photonic crystal (PhC) structures on glass (quartz) substrates is demonstrated using a thin (30 nm) chromium (Cr) layer as the hard mask for transferring the electron beam lithography (EBL) defined resist patterns. The use of the thin Cr layer not only solves the charging effect during the EBL on the insulating substrate, but also facilitates high aspect ratio PhCs by acting as a hard mask while deep etching into the Si x N y . A very high aspect ratio of 10:1 on a 60 nm wide grating structure has been achieved while preserving the quality of the flat top of the narrow lines. The presented nano-fabrication method provides PhC structures necessary for a high quality optical response. Finally, we fabricated a refractive index based PhC sensor which shows a sensitivity of 185 nm per RIU. PMID:25116111

Hossain, Md Nazmul; Justice, John; Lovera, Pierre; McCarthy, Brendan; O'Riordan, Alan; Corbett, Brian

2014-09-01

388

Modeling of hydrophilic wafer bonding by molecular dynamics simulations  

NASA Astrophysics Data System (ADS)

The role of moisture in hydrophilic wafer bonding was modeled using molecular dynamics computer simulations of interface formation between amorphous silica surfaces. Three different surface treatments were used in order to determine the effect of moisture on the formation of siloxane (Si-O-Si) bridges across the interface at two temperatures. The three surface conditions that were studied were: (a) wet interfaces containing 1 monolayer of water adsorbed at the interface (based on the room temperature bulk density of water), (b) hydroxylated interfaces with concentrations of 3-5 silanols/nm2 on each surface and no excess water molecules initially in the system, and (c) pristine interfaces that had only Si and O and no water or H present. The surfaces were slowly brought together and siloxane bond formation was monitored. In the pristine interfaces, siloxane bridges formed across the interface by the coalescence of various defect species in each surface. A bimodal distribution of siloxane bond angles formed during the first 2.5 of approach after the first siloxane bond was formed. These bond angles were much lower than and higher than the bulk average, indicating the formation of less stable bonds. The hydroxylated (with no excess water) and wet surfaces showed a more uniform distribution of siloxane bond angles, with no highly reactive small bond angles forming. The presence of water molecules enhanced H-bond formation across the interface, but trapped water molecules inhibited formation of the strong siloxane bridges across the interface. In real systems, high temperatures are required to remove this trapped moisture.

Litton, David A.; Garofalini, Stephen H.

2001-06-01

389

P/N InP solar cells on Ge wafers  

NASA Technical Reports Server (NTRS)

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented indicating InP/Ge has more power output than GaAs/Ge cells at fluences in excess of this value.

Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

1994-01-01

390

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers  

NASA Astrophysics Data System (ADS)

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

2009-03-01

391

Wafer-scale metasurface for total power absorption, local field enhancement and  

E-print Network

resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large small areas (usually ,1 mm2 ). Ref. 9 aimed to address this by instead employing silver nanocubes and evaporation techniques. These consist of silver nanoparticle islands formed over a silver mirror, with an SiO2

392

Reliability evaluation and structure design optimization of Wafer Level Chip Scale Packaging (WLCSP)  

Microsoft Academic Search

In this study a WLCSP structure in microelectronic application is considered. In the current development of WLCSP solder post is used to bridge the die and solder bump to release part of the stress concentration caused by mismatch of Thermal Expansion Coefficient (CTE). Thermal cycle reliability analysis on solder joints with 3D finite element simulation is firstly carried out. The

Shan Gao; Jupyo Hong; Jinsu Kim; Jingu Kim; Seogmoon Choi; Sung Yi

2008-01-01

393

Efficient optimization of high vacuum chemical vapor deposition of niobium oxide on full wafer scale  

NASA Astrophysics Data System (ADS)

A systematic study of niobium oxide deposition using niobium tetraethoxy-dimethyl-amino-ethoxide (Nb(OEt)4(dmae)) precursor is presented. The deposition process was conducted in a high-vacuum chemical vapor deposition machine with precursor flux gradient capability. An efficient optimization of the deposition process was achieved and both mass-transport- and chemical-reaction-limited regimes were identified.

Dabirian, A.; Kuzminykh, Y.; Harada, S.; Parsons, C.; Sandu, S. C.; Wagner, E.; Benvenuti, G.; Rushworth, S.; Muralt, P.; Hoffmann, P.

2010-02-01

394

Wafer-scale graphene\\/ferroelectric hybrid devices for low-voltage electronics  

Microsoft Academic Search

Preparing graphene and its derivatives on functional substrates may open enormous opportunities for exploring the intrinsic electronic properties and new functionalities of graphene. However, efforts in replacing SiO2 have been greatly hampered by a very low sample yield of the exfoliation and related transferring methods. Here, we report a new route in exploring new graphene physics and functionalities by transferring

Yi Zheng; Guang-Xin Ni; Sukang Bae; Chun-Xiao Cong; Orhan Kahya; Chee-Tat Toh; Hye Ri Kim; Danho Im; Ting Yu; Jong Hyun Ahn; Byung Hee Hong; Barbaros zyilmaz

2011-01-01

395

ISOTROPIC ETCHING OF 111 SCS FOR WAFER-SCALE MANUFACTURING OF PERFECTLY HEMISPHERICAL SILICON MOLDS  

E-print Network

are XeF2 and HF-Nitric acid etching. XeF2 is a gas phase etch, in which the XeF2 sublimates at room as a buffer gas. HNA, which is typically a combination of HF and Nitric acid diluted by Acetic acid or water, makes use of the oxidizing properties of Nitric acid in combination with the SiO2 consuming properties

Afshari, Ehsan

396

Wafer-Scale High-Throughput Ordered Growth of Vertically Aligned ZnO Nanowire  

E-print Network

of other materials, such as polymers, Si, and glass. This combined approach demonstrates a novel method in energy harvesting, sensing, optoelectronics, and electronic devices. KEYWORDS ZnO, nanowire, arrays- dimensional nanostructured building blocks for en- ergy harvesting,1-5 sensing,6,7 optoelectronic,8

Wang, Zhong L.

397

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers  

NASA Technical Reports Server (NTRS)

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Larkin, David J. (inventor); Powell, J. Anthony (inventor)

1992-01-01

398

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers  

NASA Technical Reports Server (NTRS)

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Powell, J. Anthony (inventor)

1991-01-01

399

Structural Damage Detection with Piezoelectric Wafer Active Sensors  

NASA Astrophysics Data System (ADS)

Piezoelectric wafer active sensors (PWAS) are lightweight and inexpensive enablers for a large class of damage detection and structural health monitoring (SHM) applications. This paper starts with a brief review of PWAS physical principles and basic modelling and continues by considering the various ways in which PWAS can be used for damage detection: (a) embedded guided-wave ultrasonics, i.e., pitch-catch, pulse-echo, phased arrays, thickness mode; (b) high-frequency modal sensing, i.e., the electro-mechanical (E/M) impedance method; (c) passive detection, i.e., acoustic emission and impact detection. An example of crack-like damage detection and localization with PWAS phased arrays on a small metallic plate is given. The modelling of PWAS detection of disbond damage in adhesive joints is achieved with the analytical transfer matrix method (TMM). The analytical methods offer the advantage of fast computation which enables parameter studies and carpet plots. A parametric study of the effect of crack size and PWAS location on disbond detection is presented. The power and energy transduction between PWAS and structure is studied analytically with a wave propagation method. Special attention is given to the mechatronics modeling of the complete transduction cycle from electrical excitation into ultrasonic acoustic waves by the piezoelectric effect, the transfer through the structure, and finally reverse piezoelectric transduction to generate the received electric signal. It is found that the combination of PWAS size and wave frequency/wavelength play an important role in identifying transduction maxima and minima that could be exploited to achieve an optimum power-efficient design. The multi-physics finite element method (MP-FEM), which permits fine discretization of damaged regions and complicated structural geometries, is used to study the generation of guided waves in a plate from an electrically excited transmitter PWAS and the capture of these waves as electric signals at a receiver PWAS. Wave diffraction from a hole damage is illustrated through time-frame snapshots. The paper ends with conclusions and suggestions for further work.

Giurgiutiu, Victor

2011-07-01

400

Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).  

PubMed

A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (?TAS), analytical and bio-analytical applications, and MEMS packaging. PMID:21387022

Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

2011-04-21

401

Synthesis and thermionic emission properties of graphitic carbon nanofibres supported on Si wafers or carbon felt  

NASA Astrophysics Data System (ADS)

Preparation procedures and thermionic emission properties of graphitic carbon nanofibres (GCNFs) supported on Si wafer or commercial carbon felt supports are reported. GCNF/native-oxide Si wafer, GCNF/oxidized Si wafer, GCNF/Ni-coated Si wafer and GCNF/carbon felt nanocomposites are obtained by growing GCNFs from growth catalyst nanoparticles supported on these supports. Narrow herringbone GCNF/SiO2/carbon felt mats are prepared from growth catalyst nanoparticles supported on fumed silica flakes. Due to weak GCNF-to-support binding in GCNF/Si wafer mats, GCNF/carbon felt mats and GCNF/SiO2/carbon felt mats, mechanical loss of the GCNF component is facile. However, carbothermal reduction of GCNF/SiO2/carbon felt nanocomposites affords mechanically robust GCNF/SiC/carbon felt mats. Thermionic electron energy distribution profiles recorded for these new nanofibre compositions indicate classic free-electron emission with estimated work functions (4.25-4.91 eV) slightly lower than those observed for un-doped graphite or carbon nanotubes. Electron energy distributions along the low energy leading region of the profiles display a cascade of emission peaks equally spaced by ca 0.014 eV, tentatively attributed to electron emission from localized GCNF edge sites.

Li, Jiang; Robinson, Vance S.; Liu, Yang; Lu, Weijie; Fisher, Timothy S.; Lukehart, Charles M.

2007-08-01

402

Reliability study of wafer bonding for micro-electro-mechanical systems  

NASA Astrophysics Data System (ADS)

Wafer bonding has attracted significant attention in applications that require integration of Micro-Electro-Mechanical Systems (MEMS) with Integrated Circuits (IC). The integration of monolithic MEMS and electronic devices is difficult because of issues such as material compatibility, process compliance and thermal budget. It is important to establish a wafer bonding process which provides long-term protection for the MEMS devices yet does not affect their performance. The attentions for such integration are at the die level and wafer level. Recently, the trend is toward wafer-level integration as a cost effective solution to combine sensing, logic, actuation and communications on a single platform. This paper describes the development of low temperature bonding techniques for post-CMOS MEMS integration in system-on-chip (SOC) applications. The bonding methods discussed in this paper involve Benzocyclobutene polymer (BCB) as glue layer to joint two 200 mm wafers together. The bonding temperature is lower than 400C. Four-point bending and stud-pull methods were used to investigate the mechanical properties of the bonding interfaces. These methods can provide critical information such as adhesion energy and bonding strength of the bonded interfaces. Initial test results at room temperature showed that the BCB bond stayed intact up to an average stress of 50 MPa. It was observed that the BCB bond strength decreased with increasing temperatures and the energy release rate decreased with decreasing BCB thickness.

Almasri, Mahmoud; Altemus, Bruce; Gracias, Alison; Clow, Larry; Tokranova, Natalya; Castracane, James; Xu, Bai

2004-01-01

403

Reliability study of wafer bonding for micro-electro-mechanical systems  

NASA Astrophysics Data System (ADS)

Wafer bonding has attracted significant attention in applications that require integration of Micro-Electro-Mechanical Systems (MEMS) with Integrated Circuits (IC). The integration of monolithic MEMS and electronic devices is difficult because of issues such as material compatibility, process compliance and thermal budget. It is important to establish a wafer bonding process which provides long-term protection for the MEMS devices yet does not affect their performance. The attentions for such integration are at the die level and wafer level. Recently, the trend is toward wafer-level integration as a cost effective solution to combine sensing, logic, actuation and communications on a single platform. This paper describes the development of low temperature bonding techniques for post-CMOS MEMS integration in system-on-chip (SOC) applications. The bonding methods discussed in this paper involve Benzocyclobutene polymer (BCB) as glue layer to joint two 200 mm wafers together. The bonding temperature is lower than 400C. Four-point bending and stud-pull methods were used to investigate the mechanical properties of the bonding interfaces. These methods can provide critical information such as adhesion energy and bonding strength of the bonded interfaces. Initial test results at room temperature showed that the BCB bond stayed intact up to an average stress of 50 MPa. It was observed that the BCB bond strength decreased with increasing temperatures and the energy release rate decreased with decreasing BCB thickness.

Almasri, Mahmoud; Altemus, Bruce; Gracias, Alison; Clow, Larry; Tokranova, Natalya; Castracane, James; Xu, Bai

2003-12-01

404

Microwave ECR plasma electron flood for low pressure wafer charge neutralization  

SciTech Connect

Modern ion implanters typically use dc arc discharge Plasma Electron Floods (PEFs) to neutralize wafer charge. The arc discharge requires using at least some refractory metal hardware, e.g. a thermionically emitting filament, which can be undesirable in applications where no metallic contamination is critical. rf discharge PEFs have been proposed to mitigate contamination risks but the gas flows required can result in high process chamber pressures. Axcelis has developed a microwave electron cyclotron resonance (ECR) PEF to provide refractory metals contamination-free wafer neutralization with low gas flow requirement. Our PEF uses a custom, reentrant cusp magnet field providing ECR and superior electron confinement. Stable PEF operation with extraction slits sized for 300 mm wafers can be attained at Xe gas flows lower than 0.2 sccm. Electron extraction currents can be as high as 20 mA at absorbed microwave powers < 70 W. On Axcelis' new medium current implanter, plasma generation has proven robust against pressure transients caused by, for example, photoresist outgassing by high power ion beams. Charge monitor and floating potential measurements along the wafer surface corroborate adequate wafer charge neutralization for low energy, high current ion beams.

Vanderberg, Bo; Nakatsugawa, Tomoya; Divergilio, William [Axcelis Technologies Inc., 108 Cherry Hill Drive, Beverly, MA 01915 (United States)

2012-11-06

405

First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies  

NASA Technical Reports Server (NTRS)

Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.

Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Lai, R.

2008-01-01

406

Initiation time of near-infrared laser-induced slip on the surface of silicon wafers  

SciTech Connect

We have determined the initiation time of laser-induced slip on a silicon wafer surface subjected to a near-infrared continuous-wave laser by numerical simulations and experiments. First, numerical analysis was performed based on the heat transfer and thermoelasticity model to calculate the resolved shear stress and the temperature-dependent yield stress. Slip initiation time was predicted by finding the time at which the resolved shear stress reached the yield stress. Experimentally, the slip initiation time was measured by using a laser scattering technique that collects scattered light from the silicon wafer surface and detects strong scattering when the surface slip is initiated. The surface morphology of the silicon wafer surface after laser irradiation was also observed using an optical microscope to confirm the occurrence of slip. The measured slip initiation times agreed well with the numerical predictions.

Choi, Sungho [Graduate School of Mechanical Engineering, Hanyang University, Seoul 133791 (Korea, Republic of); Jhang, Kyung-Young, E-mail: kyjhang@hanyang.ac.kr [School of Mechanical Engineering, Hanyang University, Seoul 133791 (Korea, Republic of)

2014-06-23

407

Integratible process for fabrication of fluidic microduct networks on a single wafer  

NASA Astrophysics Data System (ADS)

We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 mm, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectric materials.

Matzke, Carolyn M.; Ashby, Carol I. H.; Bridges, Monica M.; Griego, Leonardo; Wong, C. Channy

1999-08-01

408

Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer  

SciTech Connect

We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

1999-09-07

409

Improved light extraction of wafer-bonded AlGaInP LEDs by surface roughening  

NASA Astrophysics Data System (ADS)

By using the wafer bonding technique and wet etching process, a wafer bonded thin film AlGaInP LED with wet etched n-AlGaInP surfaces was fabricated. The morphology of the etched surface exhibits a pyramid-like feature. The wafer was cut into 270 270 ?m2 chips and then packaged into TO-18 without epoxy resin. With 20-mA current injection, the light intensity and output power of LED-I with surface roughening respectively reach 315 mcd and 4.622 mW, which was 1.7 times higher than that of LED-II without surface roughening. The enhancement of output power in LED-I can be attributed to the pyramid-like surface, which not only reduces the total internal reflection at the semiconductor-air interface but also effectively guides more photons into the escape angle for emission from the LED device.

Zike, Liu; Wei, Gao; Chen, Xu; Deshu, Zou; Yuan, Qin; Jing, Guo; Guangdi, Shen

2010-11-01

410

CD Reference Materials Fabricated on Monolithic 200 mm Wafers for Automated Metrology Tool Applications  

NASA Astrophysics Data System (ADS)

Recently, prototype isolated-line, single-crystal critical dimension (CD) reference materials (SCCDRMs) with linewidths as narrow as 40 nm1.5 nm have been reported. These reference materials, designated NIST Prototype Reference Material (RM) 8111, were configured as 10 mm by 11 mm silicon test chips mounted in 200 mm carrier wafers. The RM 8111 chips were fabricated using microelectromechanical (MEMS) process techniques, which assure the alignment of the sidewalls of the features to silicon (111) lattice planes, and were calibrated in a sequence involving atomic force microscopy (AFM) and high resolution transmission electron microscopy (HRTEM) metrology. This paper reports initial results on SCCDRMs fabricated on 200 mm bulk wafers; this monolithic approach would eliminate the need for carrier wafers.

Allen, Richard A.; Dixson, Ronald G.; Cresswell, Michael W.; Guthrie, William F.; Shulver, Byron J. R.; Bunting, A. S.; Stevenson, J. T. M.; Walton, Anthony J.

2007-09-01

411

Gettering of metal impurities by using phosphorus diffusion in UMG silicon wafers  

NASA Astrophysics Data System (ADS)

Upgraded metallurgical grade (UMG) silicon is a cost-effective and energy-efficient silicon material for the production of solar cells. UMG silicon wafers with 5N purity include various kinds of metal impurities like Fe, Ni, Cu, and Co, which may limit the electrical performance of UMG silicon wafers and solar cells. Phosphorus diffusion gettering, which can effectively reduce the transition-metal impurities in the bulk of UMG silicon wafers and enhance the minority carrier lifetime (MCLT), is a well-known process to improve the performance of solar cells in the photovoltaic (PV) industry. In this study, phosphorus diffusion gettering was used at a constant temperature of 700 for 5 hours, and the effects of the gettering process were confirmed by measuring the MCLTs and the efficiencies of the solar cells. Depth profiles of the Fe concentration before and after the gettering process were compared using secondary ion mass spectroscopy (SIMS) measurements.

Yoon, Sung Yean; Kim, Jeong; Choi, Kyoon

2012-06-01

412

Modification of time dependence in thermal wave signal from ion implanted wafers  

NASA Astrophysics Data System (ADS)

The thermal wave signal from ion implanted silicon wafers exhibits gradual change as a function of time after implant. This change in thermal wave signal can affect the long term repeatability of measurements made on implant monitors. This paper describes a method for reducing, and in many cases eliminating, the time dependence of the thermal wave signal. Wafers implanted with B +, P +, and As + at doses ranging from 10 11 to 10 14 ions/cm 2 and energies from 60-100 keV were subjected to l temperature anneals for varying times. The decay factor was studied as a function of anneal temperature and time. The effect of exposure of the wafers to UV radiation is also discussed.

Pearce, N. O.; Bokharey, Z.; Kamenitsa, D.; Simonton, R.; Tripsas, N.; Mehrotra, B.

1993-04-01

413

Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias  

NASA Astrophysics Data System (ADS)

The presented wafer-level packaging technology enables the direct integration of electrical interconnects during low-temperature wafer bonding of a cap substrate featuring through silicon vias (TSVs) onto a MEMS device wafer. The hybrid bonding process is based on hydrophilic direct bonding of plasma-activated Si/SiO2 surfaces and the simultaneous interconnection of the device metallization layers with Cu TSVs by transient liquid phase (TLP) bonding of ultra-thin AuSn connects. The direct bond enables precise geometry definition between device and cap substrate, whereas the TLP bonding does not require a planarization of the interconnect metallization before bonding. The complete process flow is successfully validated and the fabricated devices' characterization evidenced ohmic interconnects without interfacial voids in the TLP bond.

Khne, Stphane; Hierold, Christofer

2011-08-01

414

Improving wafer level CD uniformity for logic applications utilizing mask level metrology and process  

NASA Astrophysics Data System (ADS)

Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit (IC). The extension of 193nm based lithography usage combined with design rule shrinkage makes process control, in particular the wafer level CDU control, an extremely important and challenging task in IC manufacturing. In this study the WLCD-CDC closed loop solution offered by Carl Zeiss SMS was examined. This solution aims to improve the wafer level intra-field CDU without the need to run wafer prints and extensive wafer CD metrology. It combines two stand-alone tools: The WLCD tool which measures CD based on aerial imaging technology while applying the exact scanner-used illumination conditions to the photomask and the CDC tool which utilizes an ultra-short femto-second laser to write intra-volume shading elements (Shade-In Elements) inside the photomask bulk material. The CDC process changes the dose going through the photomask down to the wafer, hence the wafer level intra-field CDU improves. The objective of this study was to evaluate how CDC process is affecting the CD for different type of features and pattern density which are typical for logic and system on chip (SOC) devices. The main findings show that the linearity and proximity behavior is maintained by the CDC process and CDU and CDC Ratio (CDCR) show a linear behavior for the different feature types. Finally, it was demonstrated that the CDU errors of the targeted (critical) feature have been effectively eliminated. In addition, the CDU of all other features have been significantly improved as well.

Cohen, Avi; Trautzsch, Thomas; Buttgereit, Ute; Graitzer, Erez; Hanuka, Ori

2013-09-01

415

Experimental measurements of spatial particle removal from silicon wafers by megasonic energy  

NASA Astrophysics Data System (ADS)

An experimental study was conducted in a megasonic cleaning tank containing deionized water to determine the influence of acoustic power, cleaning time, water temperature and dissolved gas content on the local and total cleaning efficiency of 0.5 micron silicon particles deposited on silicon wafers. The experimental system included a 2.54 cm by 15.24 cm flat piezoelectric transducer mounted on the bottom of the tank that operated at 910 kHz. The water temperature was controlled using an electric emersion heater. A flow recirculation system contained a filter for particle removal and a degasser connected to vacuum to control the dissolved gas content. A dissolved oxygen meter was used to monitor the dissolved oxygen content and a model was developed to predict the total dissolved gas content of the water. A statistical approach was used to design a factorial four-factor two-level experiment. Two values of each variable, power, time, temperature, and gas content, were used. Two wafers were used in each experiment and each test was replicated for a total of 64 wafers. By performing an analysis of variance test, power, time and dissolved gas content had a significant effect on the cleaning results. Reduction in dissolved gas content and increasing the transducer power and cleaning time enhance the cleaning efficiency. A change of temperature from 25C to 50C had no significant effect on particle removal. Cleaning was most pronounced in the center of the wafers located near the center of the acoustic beam above the transducer. Cleaning efficiency was negative in some locations near the perimeter indicating particle redeposition. Wafer damage is suspected for 8 wafers when the dissolved gas content was low, the water temperature was 50C and the cleaning time was 10 minutes.

Yang, Ching-Hsu

2001-06-01

416

Local interstitial delivery of z-butylidenephthalide by polymer wafers against malignant human gliomas.  

PubMed

We have shown that the natural compound z-butylidenephthalide (Bdph), isolated from the chloroform extract of Angelica sinensis, has antitumor effects. Because of the limitation of the blood-brain barrier, the Bdph dosage required for treatment of glioma is relatively high. To solve this problem, we developed a local-release system with Bdph incorporated into a biodegradable polyanhydride material, p(CPP-SA; Bdph-Wafer), and investigated its antitumor effects. On the basis of in vitro release kinetics, we demonstrated that the Bdph-Wafer released 50% of the available Bdph by the sixth day, and the release reached a plateau phase (90% of Bdph) by the 30th day. To investigate the in situ antitumor effects of the Bdph-Wafer on glioblastoma multiforme (GBM), we used 2 xenograft animal models-F344 rats (for rat GBM) and nude mice (for human GBM)-which were injected with RG2 and DBTRG-05MG cells, respectively, for tumor formation and subsequently treated subcutaneously with Bdph-Wafers. We observed a significant inhibitory effect on tumor growth, with no significant adverse effects on the rodents. Moreover, we demonstrated that the antitumor effect of Bdph on RG2 cells was via the PKC pathway, which upregulated Nurr77 and promoted its translocation from the nucleus to the cytoplasm. Finally, to study the effect of the interstitial administration of Bdph in cranial brain tumor, Bdph-Wafers were surgically placed in FGF-SV40 transgenic mice. Our Bdph-Wafer significantly reduced tumor size in a dose-dependent manner. In summary, our study showed that p(CPP-SA) containing Bdph delivered a sufficient concentration of Bdph to the tumor site and effectively inhibited the tumor growth in the glioma. PMID:21565841

Harn, Horng-Jyh; Lin, Shinn-Zong; Lin, Po-Cheng; Liu, Cyong-Yue; Liu, Po-Yen; Chang, Li-Fu; Yen, Ssu-Yin; Hsieh, Dean-Kuo; Liu, Fu-Chen; Tai, Dar-Fu; Chiou, Tzyy-Wen

2011-06-01

417

Electrical performances and structural designs of copper bonding in wafer-level three-dimensional integration.  

PubMed

The integrity of bonded Cu interconnects in wafer-level three-dimensional integration has been investigated as the function of pattern size and density, as well as bonding process parameter. The desired pattern density coupled with the application of bonding process profile we developed gives optimal yield and alignment accuracy, and provides excellent electrical connectivity and contact resistance through the entire wafer. This result is a key milestone in establishing the manufacturability of Cu-based interconnections for 3D integration technology. PMID:21770156

Chen, K N; Young, A M; Lee, S H; Lu, J Q

2011-06-01

418

Lateral cavity photonic crystal surface emitting laser based on commercial epitaxial wafer.  

PubMed

A lateral cavity photonic crystal surface emitting laser (LC-PCSEL) with airholes of cone-like shape etched near to the active layer is fabricated. It employs only a simple commercial epitaxial wafer without DBR and needs no wafer bonding technique. Surface emitting lasing action at 1575 nm with power of 1.8 mW is observed at room temperature, providing potential values for mass production of electrically driven PCSELs with low cost. Additionally, Fano resonance is utilized to analyze aperture equivalence of PC, and energy distribution in simplified laser structure is simulated to show oscillation and transmission characteristics of laser. PMID:23571974

Wang, Yufei; Qu, Hongwei; Zhou, Wenjun; Qi, Aiyi; Zhang, Jianxin; Liu, Lei; Zheng, Wanhua

2013-04-01

419

Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner  

NASA Technical Reports Server (NTRS)

The Genesis sample return capsule, though broken during the landing impact, contained most of the shattered ultra-pure solar wind collectors comprised of silicon and other semiconductor wafers materials. Post-flight analysis revealed that all wafer fragments were littered with surface particle contamination from spacecraft debris as well as soil from the impact site. This particulate contamination interferes with some analyses of solar wind. In early 2005, the Genesis science team decided to investigate methods for removing the surface particle contamination prior to solar wind analysis.

Calaway, Michael J.; Rodriquez, M. C.; Allton, J. H.; Stansbery, E. K.

2009-01-01

420

Process for the homoepitaxial growth of single-crystal silicon carbide films on silicon carbide wafers  

NASA Technical Reports Server (NTRS)

The invention is a method for growing homoepitaxial films of SiC on low tilt angle vicinal (0001) SiC wafers. The invention proposes and teaches a new theoretical model for the homoepitaxial growth of SiC films on (0001) SiC substrates. The inventive method consists of preparing the growth surface of SiC wafers slightly off-axis (from less the 0.1 to 6 deg) from the (0001) plane, subjecting the growth surface to a suitable etch, and then growing the homoepitaxial film using conventional SiC growth techniques.

Powell, J. Anthony (inventor)

1993-01-01

421

Behavior of Cu and Zn Impurities on GaAs Wafer Surfaces  

NASA Astrophysics Data System (ADS)

Surface Cu and Zn contamination levels of intentionally contaminated GaAs wafers were measured by total reflection X-ray fluorescence (TXRF). Cu and Zn are both major metallic impurities on GaAs wafer surfaces, but their adsorption behaviors in an organic base solution were quite different. Surface concentration of Cu was much higher than that of Zn when concentrations of Cu and Zn in the organic base solution were the same. Cleaning effects of running deionized water rinse in an ultrasonic bath (U-RDIW) were also studied. Surface concentrations of Cu and Zn were drastically reduced by U-RDIW rinse.

Shibaya, Hiroshi

1995-08-01

422

Wafer bonding and layer transfer processes for 4-junction high efficiency solar cells  

Microsoft Academic Search

A four-junction cell design consisting of InGaAs, InGaAsP, GaAs, and Ga0.5In0.5P subcells could reach 1AM0 efficiencies of 35.4%, but relies on the integration of non-lattice-matched materials. Wafer bonding and layer transfer processes show promise in the fabrication of InP\\/Si epitaxial templates for growth of the bottom InGaAs and InGaAsP subcells on a Si support substrate. Subsequent wafer bonding and layer

James M. Zahler; A. Fontcuberta i Morral; Chang-Geun Ahn; Harry A. Atwater; Mark W. Wanlass; Charles Chu; Peter A. Iles

2002-01-01

423

1.3-microm optically-pumped semiconductor disk laser by wafer fusion.  

PubMed

We report a wafer-fused high power optically-pumped semiconductor disk laser operating at 1.3 microm. An InP-based active medium was fused with a GaAs/AlGaAs distributed Bragg reflector, resulting in an integrated monolithic gain mirror. Over 2.7 W of output power, obtained at temperature of 15 degrees C, represents the best achievement reported to date for this type of lasers. The results reveal an essential advantage of the wafer fusing technique over both monolithically grown AlGaInAs/GaInAsP- and GaInNAs-based structures. PMID:19466154

Lyytikinen, Jari; Rautiainen, Jussi; Toikkanen, Lauri; Sirbu, Alexei; Mereuta, Alexandru; Caliman, Andrei; Kapon, Eli; Okhotnikov, Oleg G

2009-05-25

424

Measurement of principal refractive indices of birefringent wafer by analysis of Fabry-Perot interference fringes.  

PubMed

We developed an efficient method for measuring the principal refractive indices and thickness of an optically anisotropic wafer that involves the analysis of Fabry-Perot interference fringes. Utilizing the birefringence of the medium, the 2? phase ambiguity was readily resolved in single-wavelength measurements of the birefringent medium index. Although the accuracy of the index measurements is limited due to the innate ambiguity, our analysis method overcame this limit and could determine the principal refractive indices and thickness with an uncertainty of 10(-5). Our method was validated against measurements of a lithium niobate wafer for which the values of the indices are precisely known. PMID:25321129

Choi, Hee Joo; Cha, Myoungsik

2014-08-20

425

Study on higher harmonic suppression using edge filter and polished Si wafer  

SciTech Connect

Higher harmonics contamination is a severe problem in synchrotron beamlines where grating monochromators are used. In these beamlines, absorption edge filters and critical angle mirrors are used to suppress the harmonic contaminations. In the present study, carried out using Indus-1 reflectivity beamline, a harmonic suppression characteristic of Al edge filter and polished silicon wafer are determined. It is found that the Al filter suppresses higher harmonics in 27% range whereas the polished silicon wafer can suppress the higher harmonics below 1%. The results of comparative study are discussed.

Gupta, R. K., E-mail: rkg@rrcat.gov.in; Singh, Amol, E-mail: rkg@rrcat.gov.in; Modi, Mohammed H., E-mail: rkg@rrcat.gov.in; Lodha, G. S., E-mail: rkg@rrcat.gov.in [X-ray Optics Section, ISU Division, Raja Ramanna Centre for Advanced Technology, Indore-452013 (India)

2014-04-24

426

Thermal and structural assessments of a ceramic wafer seal in hypersonic engines  

NASA Technical Reports Server (NTRS)

The thermal and structural performances of a ceramic wafer seal in a simulated hypersonic engine environment are numerically assessed. The effects of aerodynamic heating, surface contact conductance between the seal and its adjacent surfaces, flow of purge coolant gases, and leakage of hot engine flow path gases on the seal temperature were investigated from the engine inlet back to the entrance region of the combustion chamber. Finite element structural analyses, coupled with Weibull failure analyses, were performed to determine the structural reliability of the wafer seal.

Tong, Mike T.; Steinetz, Bruce M.

1991-01-01

427

Production of low cost silicon wafers by continuous casting method-development of drip-controlled method  

Microsoft Academic Search

The continuous casting method (CCM) has been designed to obtain low cost silicon wafers. This method has the objective of wafer cost reduction production effect through the installation of a pre-heating zone and a crystal growth and cooling zone separately on both sides of a silicon melting and injecting zone. We have developed the drip-controlled method (DCM) as a casting

S. Goda; T. Moritani; Y. Hatanaka; H. Shimizu; I. Hide

1994-01-01

428

Simplified 2-D Modeling of Power and Energy Transduction of Piezoelectric Wafer Active Sensors for Structural Health Monitoring  

E-print Network

of the structure is inferred from the changes in load and strain distributions measured by the sensors; and (bSimplified 2-D Modeling of Power and Energy Transduction of Piezoelectric Wafer Active Sensors an investigation of 2-D power and energy transduction in piezoelectric wafer active sensors (PWAS) for structural

Giurgiutiu, Victor

429

Wafer-level integrated electrospray emitters for a pumpless microthruster system operating in high efficiency ion-mode  

Microsoft Academic Search

Microfabrication, wafer-level integration, and characterization of internally fed arrays of electrospray thrusters for spacecraft propulsion are discussed. 5 ?m inner diameter, 100 ?m long capillaries and 150-to-300 ?m diameter annular extractor electrodes are integrated vertically via a polymer based wafer bonding process, allowing high yield and post testing disassembly of the bonded stack. The small inner diameter of the capillaries

Caglar Ataman; Simon Dandavino; Herbert Shea

2012-01-01

430

A Platform for Three-dimensional On-chip Photonics: Multi-bonded Silicon-On-Insulator wafers  

E-print Network

silicon nano-wire waveguides. Additionally, if the temperature process is limited to about 600°C, whichA Platform for Three-dimensional On-chip Photonics: Multi-bonded Silicon-On-Insulator wafers Amir interference coupler is fabricated on a double-bounded Silicon-on-insulator wafer. Optical characterizations

Chen, Ray

431

Preparation and characterization of Al/Al2O3/Cu SIN tunnel junctions microfabricated with a full wafer process  

E-print Network

Preparation and characterization of Al/Al2O3/Cu SIN tunnel junctions microfabricated with a full at Storrs We have developed a "full wafer" process for producing Al/Al2O3/Cu superconductor the "full wafer" process developed for Nb/Al 2 O 3 /Nb superconductor-insulator-superconductor (SIS) devices

Neuhauser, Barbara

432

IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 1, FEBRUARY 2007 19 Wafer-Level Packaging of Micromechanical  

E-print Network

IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 1, FEBRUARY 2007 19 Wafer-Level Packaging, IEEE, and Paul A. Kohl, Member, IEEE Abstract--An approach to low-cost, wafer-level packaging in a protective overcoat. The protected MEMS device can then be handled and packaged like an integrated circuit

Ayazi, Farrokh

433

2392 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 12, DECEMBER 2000 Iron Contamination in Silicon Wafers Measured  

E-print Network

and silicon-on-insulator (SOI) wafers. What other technique can detect iron density in a simple, rapid2392 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 12, DECEMBER 2000 Iron Contamination generation lifetime tech- nique is used to determine the iron density in boron-doped silicon wafers

Schroder, Dieter K.

434

Generation of SWNTs on Si Wafer by Alcohol Catalytic CVD Shigeo Maruyama, Shohei Chiashi and Yuhei Miyauchi  

E-print Network

Generation of SWNTs on Si Wafer by Alcohol Catalytic CVD Shigeo Maruyama, Shohei Chiashi and Yuhei ACCVD technique, lower temperature generation of SWNTs on Al patterned Si surface should be principally possible. We tried to generate SWNTs on Si wafer by ACCVD technique. Zeolite particles supporting Fe

Maruyama, Shigeo

435

Generation and Recombination Carrier Lifetimes in 4H SiC Epitaxial Wafers , M. J. Loboda1)  

E-print Network

Generation and Recombination Carrier Lifetimes in 4H SiC Epitaxial Wafers G. Chung1) , M. J. Loboda comparative studies of recombination and carrier lifetimes in SiC. For the first time, both generation-wafer structures. The ratio of the generation to recombination lifetime is much different in SiC compared to Si

Schroder, Dieter K.

436

Ligatoxin B, a new cytotoxic protein with a novel helix-turn-helix DNA-binding domain from the mistletoe Phoradendron liga.  

PubMed Central

A new basic protein, designated ligatoxin B, containing 46 amino acid residues has been isolated from the mistletoe Phoradendron liga (Gill.) Eichl. (Viscaceae). The protein's primary structure, determined unambiguously using a combination of automated Edman degradation, trypsin enzymic digestion, and tandem MS analysis, was 1-KSCCPSTTAR-NIYNTCRLTG-ASRSVCASLS-GCKIISGSTC-DSGWNH-46. Ligatoxin B exhibited in vitro cytotoxic activities on the human lymphoma cell line U-937-GTB and the primary multidrug-resistant renal adenocarcinoma cell line ACHN, with IC50 values of 1.8 microM and 3.2 microM respectively. Sequence alignment with other thionins identified a new member of the class 3 thionins, ligatoxin B, which is similar to the earlier described ligatoxin A. As predicted by the method of homology modelling, ligatoxin B shares a three-dimensional structure with the viscotoxins and purothionins and so may have the same mode of cytotoxic action. The novel similarities observed by structural comparison of the helix-turn-helix (HTH) motifs of the thionins, including ligatoxin B, and the HTH DNA-binding proteins, led us to propose the working hypothesis that thionins represent a new group of DNA-binding proteins. This working hypothesis could be useful in further dissecting the molecular mechanisms of thionin cytotoxicity and of thionin opposition to multidrug resistance, and useful in clarifying the physiological function of thionins in plants. PMID:12049612

Li, Shi-Sheng; Gullbo, Joachim; Lindholm, Petra; Larsson, Rolf; Thunberg, Eva; Samuelsson, Gunnar; Bohlin, Lars; Claeson, Per

2002-01-01

437

Simultaneous analysis of edge quality parameters for submillimeter-thick silicon wafer bar with Fourier optics  

NASA Astrophysics Data System (ADS)

This paper proposes an edge quality assessment system for a submillimeter thick wafer bar suitable for semiconductor and hard disk drive industries. Our key approach is based on Fourier optics analysis in a retro-reflective optical architecture featuring nondestructive and noncontact measurement. In our proposed design, a collimated optical beam is incident on a submillimeter thick wafer bar from its side. In this way, part of the optical beam is reflected back and is then Fourier transformed on a two-dimensional image sensor. By investigating the far-field diffraction pattern, important parameters of the wafer bar such as thickness, surface parallelism, edge parallelism, and surface defect can simultaneously be analyzed. To our knowledge, this is the first time that these important parameters are analyzed by only one system. Other key features include low cost and vibration insensitivity. Our field test study using a 635-nm wavelength laser and a 15-cm plano-convex lens for specified 246-?m thick rectangular wafer bars shows that our retro-reflective approach can measure the bar thickness within its specified +/-10 ?m. It can also simultaneously evaluate the remaining desired parameters and can distinguish nicely edged bars from poorly edged bars. Other key features include low cost, ease of implementation, robustness, and low component counts.

Sumriddetchkajorn, Sarun; Chaitavon, Kosom

2011-02-01

438

Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.  

PubMed

We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results. PMID:19473926

Logan, Andrew; Yeow, John T W

2009-05-01

439

RECYCLING OF SILICON-WAFERS PRODUCTION WASTES TO SIALON BASED CERAMICS WITH IMPROVED MECHANICAL PROPERTIES  

EPA Science Inventory

A high-temperature SHS reactor capable of operating at a maximum pressure of 300 psi was designed, developed, and successfully tested. Silicon wafers production wastes were collected and characterized for particle size, phases using X-ray diffraction (XRD), and morphology o...

440

Improvements of adhesion and hydrophobicity of wafer bevel in water immersion lithography  

NASA Astrophysics Data System (ADS)

In this study, we focus on the controllability of a wafer bevel from adhesion and hydrophobicity viewpoints in order to solve the problems of film peeling and microdroplet formation around wafer bevels, which result in pattern defects. Hexamethyldisilazane (HMDS) treatment is a common solution to these problems. We examine a novel wafer bevel treatment utilizing silane coupling agents (SCAs) for obtaining high adhesion and hydrophobicity. SCAs comprise trimethoxysilanol and organic functional groups. These groups react with inorganic substrates and films just over the surface subjected to a novel chemical treatment (NCT), respectively. Several organic functional groups both with and without fluorine are examined. The hydrophobicity is estimated from the static and receding contact angles of water. The adhesion strength is measured from the stress required for pulling the topcoat film away from the substrate subjected to the NCT. The coating performance of chemicals on the surface by the NCT and the aging stability of the formulated solution of the SCAs are examined for optimizing the composition of the NCT solution. Further, we verify the film peeling behavior and water leakage in wafers having a topcoat, ArF resist, and bottom antireflective coating (BARC) using a quasi-immersion exposure stage.

Ishibash, Takeo; Terai, Mamoru; Hagiwara, Takuya; Kumada, Teruhiko; Hanawa, Tetsuro; Takebe, Yoko; Yokokoji, Osamu; Fujiwara, Tomoharu; Akiyama, Hiroshi

2008-03-01

441

Dependence of nickel gettering on crystalline nature in as-grown Czochralski silicon wafer  

NASA Astrophysics Data System (ADS)

The efficiency of nickel gettering in vacancy- and interstitial-silicon-dominant crystalline nature was studied using wafers cut along the axial direction of a CZ-grown silicon ingot grown with a variable v/G ratio. Six crystalline areas (V-rich, P-band, PV, PI, B-band, and I-rich) were present within one wafer. Nickel gettering efficiency was estimated before and after a typical NAND-flash-memory heat-treatment. With as-grown CZ silicon wafers, nickel gettering depends on the crystalline nature, i.e., nickel atoms are mainly gathered at oxygen precipitates in bulk at vacancy-dominant crystalline regions and at the surface of pure silicon in the interstitial-silicon-dominant crystal region (PI). Rapid thermal annealing of a CZ silicon wafer at 1175 C for 10 s in Ar/NH3 mixture ambient completely erased the dependency of nickel gettering on the crystalline nature and demonstrated an excellent getting ability for nickel contamination via the relaxation gettering of oxygen precipitates.

Lee, In-Ji; Paik, Ungyu; Park, Jea-Gun

2013-02-01

442

Thermal compression wafer bonding of tungsten applied to fabrication of small-period tungsten woodpile structures  

E-print Network

Thermal compression wafer bonding of tungsten applied to fabrication of small-period tungsten on the thermal compression bonding of tungsten at very high temperatures and pressures, and the realization of a 3D tungsten woodpile structure using this method. The structure is fabricated by holographic

Klotzkin, David

443

Disbond detection in adhesively-bonded structures using piezoelectric wafer active sensors  

E-print Network

Disbond detection in adhesively-bonded structures using piezoelectric wafer active sensors Adrian, Columbia, SC 29208 ABSTRACT Adhesively bonded joints between metallic and composite plates are gaining a study of the use of guided Lamb waves for disbond detection in adhesively bonded layered media using

Giurgiutiu, Victor

444

Piezoelectric Wafer Embedded Active Sensors for Aging Aircraft Structural Health Monitoring  

E-print Network

be applied on aging aircraft structures to monitor the onset and progress of structural damage fleet is raising major concerns. An assessment is needed of how the aircraft airworthiness is effected41 Piezoelectric Wafer Embedded Active Sensors for Aging Aircraft Structural Health Monitoring

Giurgiutiu, Victor

445

Title: Corrosion Damage Detection with Piezoelectric Wafer Active Sensors Authors: Dustin T. Thomas  

E-print Network

0 Title: Corrosion Damage Detection with Piezoelectric Wafer Active Sensors Authors: Dustin T structural problems is corrosion. In fact the KC-135 now costs $1.2 billion a year to repair corrosion) in a pitch-catch configuration. The sensors were placed on a grid pattern. Material loss through corrosion

Giurgiutiu, Victor

446

Corrosion Damage Detection with Piezoelectric Wafer Active Sensors Dustin Thomas, John Welter  

E-print Network

1 Corrosion Damage Detection with Piezoelectric Wafer Active Sensors Dustin Thomas, John Welter Air a priority issue for today's Air Force. One of the most critical structural problems is corrosion. In fact the KC-135 now costs $1.2 billion a year to repair corrosion. In this paper, we plan to show the use

Giurgiutiu, Victor

447

Reduce your cycle time by utilizing automation for wafer test data collection  

Microsoft Academic Search

Many strategies are generally applied in the semiconductor industry to reduce cycle times. This technical paper describes an integrated automation environment that has been implemented on the various tester platforms at Kilby Center (KFAB) of Texas Instruments (TI). In addition to reducing wafer test cycle time, the tester automation eliminates human errors, which is an added benefit over vendor \\

Navin Tandon; Adriana Sanchez; Simran Arora; Faisal Yousuf; Jeff Miller; Randy Elder

2003-01-01

448

Model checker aided design of a controller for a wafer scanner  

Microsoft Academic Search

For a case-study of a wafer scanner from the semiconductor industry it is shown how model checking techniques can be used to compute (i) a simple yet optimal deadlock avoidance policy, and (ii) an infinite schedule that op- timizes throughput. Deadlock avoidance is studied based on a simple finite state model using Smv, and for throughput analysis a more detailed

Martijn Hendriks; Barend Van Den Nieuwelaar; Frits W. Vaandrager

2006-01-01

449

FPGA-realization of a motion control IC for wafer-handling robot  

Microsoft Academic Search

The work studies to apply a novel FPGA (Field Programmable Gate Arrays) technology to realize a motion control IC for wafer-handling robot which has three-DOF (Degree of freedom) and each axis is driven by PMSM (Permanent Magnet Synchronous Motor). The motion control IC proposed in this paper has two modules. The first module is a Nios II processor which is

Ying-Shieh Kung; Cheng-Ting Hsu; Hsin-Hung Chou; Tai-Wei Tsui

2010-01-01

450

Theoretical calculation of the acoustic force on a patterned silicon wafer during megasonic cleaning  

E-print Network

circuits prior to packaging, namely a micron-size silicon ridge and a metal wire tens to hundreds. S0021-8979 00 03017-6 I. INTRODUCTION Megasonic waves have been extensively used to remove patterned wafers for instance vias clean- ing with megasonic waves. However, little is known about

Deymier, Pierre

451

Title: Recent Advances in the Use of Piezoelectric Wafer Active Sensors for Structural Health Monitoring  

E-print Network

, inexpensive, non-invasive, elastic wave generators/detectors that can be easily affixed to a structure in a large metallic plate. The embedded ultrasonic structural radar (EUSR) algorithm is used to process the generation of Lamb waves with piezoelectric wafer active sensors (PWAS)[4]. PWAS are inexpensive, non

Giurgiutiu, Victor

452

Heat transfer from a horizontal wafer-based disk of multi-chip modules  

Microsoft Academic Search

Convective heat transfer characteristics above a horizontal wafer-based disk heated with 15 simulated chips in unobstructed ambient air have been experimentally investigated under both stationary and rotating disk conditions. Relevant parameters influencing heat transfer performance studied are the Grashof number and rotational Reynolds number. Their effects on heat transfer characteristics in such configurations of stationary and rotational heated disks are

Y. R. Shieh; C. J. Li; Y. H. Hung

1999-01-01

453

Board level drop impact reliability analysis for compliant wafer level package through modeling approaches  

Microsoft Academic Search

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. In this paper, a new compliant Wafer Level Package technology is proposed which can accommodate the CTE mismatch between the chip and PCB substrate and consequently should be more reliable without the application of underfill. The purpose of this study is

Chaoping Yuan; K. L. Pan; Weiyang Qiu; Jing Liu

2009-01-01

454

Micromachining of high-contrast optical waveguides in (111) silicon wafers  

Microsoft Academic Search

A fabrication technique by KOH etching for very thin free standing plane parallel silicon bridges in a (111) silicon wafer is presented. The applications of such a stress free slab as an evanescent optical waveguide sensor of unusually high sensitivity are discussed

G. Pandraud; G. Veldhuis; J. W. Berenschot; A. J. Nijdam; H. J. W. M. Hoekstra; O. Parriaux; P. V. Lambeck

2000-01-01

455

Surface Deposition of Ionic Contaminants on Silicon Wafers in a Cleanroom Environment  

Microsoft Academic Search

The adsorption and desorption behaviors of ionic micro-contaminants on the silicon wafers in a cleanroom environment were investigated in this study. The experimental measurements showed that the surface density of ionic contaminants was significantly affected by both the exposure time and the properties of contaminants. The rate parameters of a kinetic model for surface deposition were determined by numerical optimization

I-Kai Lin; Hsunling Bai; Bi-Jun Wu

2009-01-01

456

Wafer and reticle positioning system for the extreme ultraviolet lithography engineering test stand  

Microsoft Academic Search

This paper is an overview of the wafer and reticle positioning system of the Extreme Ultraviolet Lithography (EUVL) Engineering Test Stand (ETS). EUVL represents one of the most promising technologies for supporting the integrated circuit (IC) industry's lithography needs for critical features below 100 nm. EUVL research and development includes development of capabilities for demonstrating key EUV technologies. The ETS

John B. Wronosky; Tony G. Smith; Marcus J. Craig; Beverly R. Sturgis; Joel R. Darnold; David K. Werling; Mark A. Kincy; Daniel A. Tichenor; Mark E. Williams; Paul M. Bischoff

2000-01-01

457

Optical properties of polycrystalline silicon thin films deposited by single-wafer chemical vapor deposition  

Microsoft Academic Search

The ellipsometric study of polycrystalline silicon films deposited using a single wafer rapid thermal chemical vapor deposition reactor under varying conditions of temperature and doping is presented. In particular, using spectroscopic ellipsometry in the visible spectral range, we determined the thickness of the films and the structural changes as a function of the deposition temperature. A different film structure, from

M. Marazzi; M. E. Giardini; A. Borghesi; A. Sassella; M. Alessandri; G. Ferroni

1997-01-01

458

Seamless On-Wafer Integration of Si(100) MOSFETs and GaN HEMTs  

E-print Network

The first on-wafer integration of Si(100) MOSFETs and AlGaN/GaN high electron mobility transistors (HEMTs) is demonstrated. To enable a fully Si-compatible process, we fabricated a novel Si(100)-GaN-Si(100) virtual substrate ...

Piner, Edwin L.

459

Direct To Digital Holography For High Aspect Ratio Inspection of Semiconductor Wafers  

NASA Astrophysics Data System (ADS)

Direct to Digital Holography (DDH) has been developed as a semiconductor wafer inspection tool and in particular as a tool for seeing defects in high aspect ratio (HAR) structures on semiconductor wafers and also for seeing partial-height defects. While the tool works very well for general wafer inspection, it has unusual capabilities for high aspect ratio inspection (HARI) and for detecting thin residual film defects (partial height defects). Inspection of HAR structures is rated as one of the highest unmet priorities of the member companies of International SEMATECH, and finding residual thin film defects (in some cases called "stringers") is also a very difficult challenge. The capabilities that make DDH unusually sensitive include: 1) the capture of the whole waveboth the classical amplitude captured by traditional optical systems, and the phase of the wave, with phase potentially measured to 1/1000'th of a wavelength or 2 to 3 Angstroms for a deep ultra-violet (DUV) laser; 2) heterodyne detectionthis allows it to capture very low signal levels; and 3) a head-on geometry using a collimated laser beam that allows best penetration of HAR structures. The basic features and methods of this patented technology are presented, along with simple calculations of signal strength and expected noise levels for various circumstances. Full-wave numerical calculations of electromagnetic field penetration into HAR contacts and experimental results from various wafer types and structures are also presented.

Thomas, C. E. (Tommy); Hunt, Martin A.; Bahm, Tracy M.; Baylor, Larry R.; Bingham, Philip R.; Chidley, Matthew D.; Dai, Xiaolong; Delahanty, Robert J.; El-Khashab, Ayman; Gilbert, Judd M.; Goddard, James S.; Hanson, Gregory R.; Hickson, Joel D.; Hylton, Kathy W.; John, George C.; Jones, Michael L.; Mayo, Michael W.; Marek, Christopher; Price, John H.; Rasmussen, David A.; Schaefer, Louis J.; Schulze, Mark A.; Shen, Bichuan; Smith, Randall G.; Su, Allen N.; Tobin, Kenneth W.; Usry, William R.; Voelkl, Edgar; Weber, Karsten S.; Owen, Robert W.

2003-09-01

460

Fatigue crack detection in thick steel structures with piezoelectric wafer active sensors  

Microsoft Academic Search

This paper presents a set of numerical and experimental results on the use of guided waves for structural health monitoring (SHM) of crack growth during a fatigue test in a thick steel plate used for civil engineering application. The capability of embedded piezoelectric wafer active sensors (PWAS) to perform in situ nondestructive evaluation (NDE) is explored. Numerical simulation and experimental

M. Gresil; L. Yu; V. Giurgiutiu

2011-01-01

461

Porosity evaluation of PoSi wafer using a nondestructive ultrasonic technic  

E-print Network

Porosity evaluation of PoSi wafer using a nondestructive ultrasonic technic J. Bustilloa , J measurement methods of PoSi are currently destructive. Therefore in this study a nondestructive ultrasonic travelling through it, ultrasonic non-destructive testing can be a good way to measure these parameters [9

Boyer, Edmond

462

Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine  

PubMed Central

Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR). Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A), and lactose monohydrate as ingredient, of hydrophilic matrix former (B) on the bioadhesive force, disintegration time, percent (%) swelling index, and time taken for 70% drug release (t70%). The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD) analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design. PMID:23781498

Dey, Surajit; Parcha, Versha; Bhattacharya, Shiv Sankar; Ghosh, Amitava

2013-01-01

463

Functionalized silicon nanoparticles from reactive cavitation erosion of silicon wafers.  

PubMed

A new sonochemical process for the top-down production of silicon nanoparticles (<1 nm) with surface functional groups is described. The procedure involves a combination of acoustic cavitation erosion of a single-crystalline silicon surface coupled with simultaneous reaction with a reactive organic compound such as 1-hexyne. The sonochemical formation of the photoluminescent silicon nanoparticles by reactive cavitation erosion can be easily up-scaled. PMID:25494039

Wang, Hongqiang; Xu, Zejing; Fink, Mark J; Shchukin, Dmitry; Mitchell, Brian S

2015-01-01

464

Molecular-Scale Quantum Dots from Carbon Nanotube Heterojunctions  

E-print Network

Molecular-Scale Quantum Dots from Carbon Nanotube Heterojunctions Bhupesh Chandra,,#,¶ Joydeep chiralities. These measurements reveal asymmetric IV-characteristics and the presence of a quantum dot (QD deposition across open slits (100 µm wide) on Si/SiO2 wafers,7 then characterized using Rayleigh scattering

Heinz, Tony F.

465

Introduction! Low Cost, High Volume, Scale-up Photovoltaic Manufacturing!  

E-print Network

! Production flow Challenges Solutions Composition Sands Poly Si Ingots Wafers Cells Modules High volume mfgIntroduction! Low Cost, High Volume, Scale-up Photovoltaic Manufacturing! Prof. Shreyes Melkote, Manufacturing Research Center, Georgia Institute of Technology Photovoltaics (PV) will be part of the energy mix

Das, Suman

466

A novel photosensitive material for redistribution and stress buffer reduction on 300mm wafers  

NASA Astrophysics Data System (ADS)

The widespread adoption of advanced packaging techniques is driven by electrical device performance and chip form factor considerations. Flipchip packaging is currently growing at a 25% compound annual rate and it is expected that 90% of all 65 nm logic devices will be bumped. To ensure optimal productivity and cost of ownership, it is imperative to employ lithographic materials that are optimized for these applications and that meet all device specifications. Bump processing typically has one or more levels that require a permanent layer either to relieve stress on the die (stress buffer layer) or to redistribute electrical connections (redistribution layer). Since these layers remain on the wafer, the mechanical and electrical properties of the material are as important as the lithographic properties. This study will characterize a novel negative, siloxane (Shin-Etsu SINR (R)) photoresist for the redistribution and stress buffer application on 300 mm wafers. Siloxanes are a good choice for redistribution and stress buffer layers because of their excellent physical properties, ease of processing and relatively low cure temperatures. The lithographic performance of the SINR is optimized using a broad band, low numerical aperture, 1X stepper. This study evaluates softbake, post exposure bake (PEB), develop conditions and exposure optimization. Due to decreasing feature size at the redistribution level, it is critical to demonstrate CD uniformity and resolution across the entire 300 mm wafer surface. While the CD uniformity data is collected on 300 mm wafers, all process optimization results will be applicable for all standard wafer sizes. The physical properties of the SINR material are evaluated through curing temperature studies and sputtering tests.

Flack, Warren W.; Nguyen, Ha-Ai; Capsuto, Elliott

2006-03-01