Science.gov

Sample records for wafer scale liga

  1. A Batch Wafer Scale LIGA Assembly and Packaging Technique vai Diffusion Bonding

    SciTech Connect

    Christenson, T.R.; Schmale, D.T.

    1999-01-27

    A technique using diffusion bonding (or solid-state welding) has been used to achieve batch fabrication of two- level nickel LIGA structures. Interlayer alignment accuracy of less than 1 micron is achieved using press-fit gauge pins. A mini-scale torsion tester was built to measure the diffusion bond strength of LIGA formed specimens that has shown successful bonding at temperatures of 450"C at 7 ksi pressure with bond strength greater than 100 Mpa. Extensions to this basic process to allow for additional layers and thereby more complex assemblies as well as commensurate packaging are discussed.

  2. LIGA Scanner Control Software

    Energy Science and Technology Software Center (ESTSC)

    1999-02-01

    The LIGA Scanner Software is a graphical user interface package that facilitates controlling the scanning operation of x-rays from a synchrotron and sample manipulation for making LIGA parts. The process requires scanning of the LIGA mask and the PMMA resist through a stationary x-ray beam to provide an evenly distributed x-ray exposure over the wafer. This software package has been written specifically to interface with Aerotech motor controllers.

  3. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  4. Wafer-scale Mitochondrial Membrane Potential Assays

    PubMed Central

    Lim, Tae-Sun; Davila, Antonio; Zand, Katayoun; Douglas, Wallace C.; Burke, Peter J.

    2012-01-01

    It has been reported that mitochondrial metabolic and biophysical parameters are associated with degenerative diseases and the aging process. To evaluate these biochemical parameters, current technology requires several hundred milligrams of isolated mitochondria for functional assays. Here, we demonstrate manufacturable wafer-scale mitochondrial functional assay lab-on-a-chip devices, which require mitochondrial protein quantities three orders of magnitude less than current assays, integrated onto 4” standard silicon wafer with new fabrication processes and materials. Membrane potential changes of isolated mitochondria from various well-established cell lines such as human HeLa cell line (Heb7A), human osteosarcoma cell line (143b) and mouse skeletal muscle tissue were investigated and compared. This second generation integrated lab-on-a-chip system developed here shows enhanced structural durability and reproducibility while increasing the sensitivity to changes in mitochondrial membrane potential by an order of magnitude as compared to first generation technologies. We envision this system to be a great candidate to substitute current mitochondrial assay systems. PMID:22627274

  5. Eutectic bonds on wafer scale by thin film multilayers

    NASA Astrophysics Data System (ADS)

    Christensen, Carsten; Bouwstra, Siebe

    1996-09-01

    The use of gold based thin film multilayer systems for forming eutectic bonds on wafer scale is investigated and preliminary results will be presented. On polished 4 inch wafers different multilayer systems are developed using thin film techniques and bonded afterwards under reactive atmospheres and different bonding temperatures and forces. Pull tests are performed to extract the bonding strengths.

  6. Parallel Assembly of LIGA Components

    SciTech Connect

    Christenson, T.R.; Feddema, J.T.

    1999-03-04

    In this paper, a prototype robotic workcell for the parallel assembly of LIGA components is described. A Cartesian robot is used to press 386 and 485 micron diameter pins into a LIGA substrate and then place a 3-inch diameter wafer with LIGA gears onto the pins. Upward and downward looking microscopes are used to locate holes in the LIGA substrate, pins to be pressed in the holes, and gears to be placed on the pins. This vision system can locate parts within 3 microns, while the Cartesian manipulator can place the parts within 0.4 microns.

  7. Wafer-scale aluminum nano-plasmonics

    NASA Astrophysics Data System (ADS)

    George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

    2014-09-01

    The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

  8. IGBT scaling principle toward CMOS compatible wafer processes

    NASA Astrophysics Data System (ADS)

    Tanaka, Masahiro; Omura, Ichiro

    2013-02-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

  9. Liga developer apparatus system

    DOEpatents

    Boehme, Dale R.; Bankert, Michelle A.; Christenson, Todd R.

    2003-01-01

    A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

  10. Wafer-scale aluminum plasmonics for fluorescence based biodetection

    NASA Astrophysics Data System (ADS)

    Farhang, Arash; George, Matthew C.; Williamson, Brent; Black, Mike; Wangensteen, Ted; Fraser, James; Petrova, Rumyana; Prestgard, Kent

    2015-08-01

    Moxtek has leveraged existing capabilities in wafer-scale patterning of sub-wavelength wire grid polarizers into the fabrication of 1D and 2D periodic aluminum plasmonic structures. This work will discuss progress in 200 mm diameter wafer-scale fabrication, with detailed emphasis within the realm of microarray based fluorescence detection. Aluminum nanohole arrays in a hexagonal lattice are first numerically investigated. The nanohole array geometry and periodicity are specifically tuned to coincide both with the excitation of the fluorophore Cy3, and to provide a high field enhancement within the nanoholes where labeled biomolecules are captured. This is accomplished through numerical modelling, nanofabrication, SEM imaging, and optical characterization. A 200mm diameter wafer, patterned with the optically optimized nanohole array, is cut into standard 1x3 inch microscope slide pieces and then subsequently printed with various antigens at 9 different concentrations. A sandwich bioassay is then carried out, using the corresponding conjugate antibodies in order to demonstrate specificity. The nanohole array exhibit a 3-4 times total fluorescence enhancement of Cy3, when compared to a leading commercial microarray glass slide.

  11. Wafer-scale plasmonic and photonic crystal sensors

    NASA Astrophysics Data System (ADS)

    George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

    2015-08-01

    200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

  12. Wafer-scale fabrication of nanoapertures using corner lithography

    NASA Astrophysics Data System (ADS)

    Burouni, Narges; Berenschot, Erwin; Elwenspoek, Miko; Sarajlic, Edin; Leussink, Pele; Jansen, Henri; Tas, Niels

    2013-07-01

    Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated—based on a theoretical foundation including a statistical analysis—with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures.

  13. Wrinkled bilayer graphene with wafer scale mechanical strain

    NASA Astrophysics Data System (ADS)

    Mikael, Solomon; Seo, Jung-Hun; Javadi, Alireza; Gong, Shaoqin; Ma, Zhenqiang

    2016-05-01

    Wafer-scale strained bilayer graphene is demonstrated by employing a silicon nitride (Si3N4) stressor layer. Different magnitudes of compressive stress up to 840 MPa were engineered by adjusting the Si3N4 deposition recipes, and different strain conditions were analyzed using Raman spectroscopy. The strained graphene displayed significant G peak shifts and G peak splitting with 16.2 cm-1 and 23.0 cm-1 of the G band and two-dimensional band shift, which corresponds to 0.26% of strain. Raman mapping of large regions of the graphene films found that the largest shifts/splitting occurred near the bilayer regions of the graphene films. The significance of our approach lies in the fact that it can be performed in a conventional microfabrication process, i.e., the plasma enhanced chemical vapor deposition system, and thus easily implemented for large scale production.

  14. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture

  15. Video-rate fuzzy Golay processor for wafer scale integration

    SciTech Connect

    Steinvorth, R.H.

    1987-01-01

    The fuzzy Golay transformation is a novel approach for gray-level image processing. Fuzzy-set theory is used to modify the binary image processing techniques developed by M. J. Golay to permit direct gray-level image processing without thresholding. The comparison between gray-level pixels is accomplished with the Pixel Closeness Value (PCV) while comparison between gray-level neighborhoods uses the Neighborhood Closeness Value (NCV). Feature extraction is done by comparing the gray-level image neighborhood to a subset of the fourteen Golay neighborhoods using the NCV function. The Fuzzy Golay Processor (FGP) is an architecture designed to implement the fuzzy Golay transformation. The design of the FGP has been optimized to permit a successful implementation in Wafer Scale Integration (WSI). A system containing four FGPs is capable of performing thirty fuzzy Golay transformations per second on a 256 by 256 eight-bit pixel image. Such a system could fit on a four-inch wafer with enough redundant dies to allow a 30% die yield. The required dies are four Input-Output Modules (IOM) and 56 Neighborhood Evaluation Modules (NEM).

  16. Wafer-scale micro-optics replication technology

    NASA Astrophysics Data System (ADS)

    Rossi, Markus; Rudmann, Hartmut; Marty, Brigitte; Maciossek, Andreas

    2003-11-01

    For many high-volume applications of micro-optical elements and systems the most cost-effective fabrication technology is replication in polymer materials with techniques such as UV embossing, hot embossing, and injection molding. Replication significantly reduces the cost in volume production in comparison to silicon-based etched components. However, the temperature and humidity stability of most commercial polymers is not suitable for the application of replicated elements in areas such as telecom or datacom. A process based on UV-replication in chemically durable polymers has been developed. Technologies for all fabrication steps from mastering over tooling to replication on wafer-scale, post-processing and characterization are described. We present results of various projects with double-sided micro-optics for telecom/datacom and various sensor applications.

  17. Designing defect spins for wafer-scale quantum technologies

    SciTech Connect

    Koehl, William F.; Seo, Hosung; Galli, Giulia; Awschalom, David D.

    2015-11-27

    The past decade has seen remarkable progress in the development of the nitrogen-vacancy (NV) defect center in diamond, which is one of the leading candidates for quantum information technologies. The success of the NV center as a solid-state qubit has stimulated an active search for similar defect spins in other technologically important and mature semiconductors, such as silicon carbide. If successfully combined with the advanced microfabrication techniques available to such materials, coherent quantum control of defect spins could potentially lead to semiconductor-based, wafer-scale quantum technologies that make use of exotic quantum mechanical phenomena like entanglement. In this article, we describe the robust spin property of the NV center and the current status of NV center research for quantum information technologies. We then outline first-principles computational modeling techniques based on density functional theory to efficiently search for potential spin defects in nondiamond hosts suitable for quantum information applications. The combination of computational modeling and experimentation has proven invaluable in this area, and we describe the successful interplay between theory and experiment achieved with the divacancy spin qubit in silicon carbide.

  18. Wafer-Scale Microwire Transistor Array Fabricated via Evaporative Assembly.

    PubMed

    Park, Jae Hoon; Sun, Qijun; Choi, Yongsuk; Lee, Seungwoo; Lee, Dong Yun; Kim, Yong Hoon; Cho, Jeong Ho

    2016-06-22

    One-dimensional (1D) nano/microwires have attracted significant attention as promising building blocks for various electronic and optical device applications. The integration of these elements into functional device networks with controlled alignment and density presents a significant challenge for practical device applications. Here, we demonstrated the fabrication of wafer-scale microwire field-effect transistor (FET) arrays based on well-aligned inorganic semiconductor microwires (indium-gallium-zinc-oxide (IGZO)) and organic polymeric insulator microwires fabricated via a simple and large-area evaporative assembly technique. This microwire fabrication method offers a facile approach to precisely manipulating the channel dimensions of the FETs. The resulting solution-processed monolithic IGZO microwire FETs exhibited a maximum electron mobility of 1.02 cm(2) V(-1) s(-1) and an on/off current ratio of 1 × 10(6). The appropriate choice of the polymeric microwires used to define the channel lengths enabled fine control over the threshold voltages of the devices, which were employed to fabricate high-performance depletion-load inverters. Low-voltage-operated microwire FETs were successfully fabricated on a plastic substrate using a high-capacitance ion gel gate dielectric. The microwire fabrication technique involving evaporative assembly provided a facile, effective, and reliable method for preparing flexible large-area electronics. PMID:27228025

  19. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  20. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  1. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates.

    PubMed

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-19

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes. PMID:26789103

  2. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates

    NASA Astrophysics Data System (ADS)

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-01

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes.

  3. Transfer-Free, Wafer-Scale Manufacturing of Graphene-Based Electromechanical Resonant Devices

    NASA Astrophysics Data System (ADS)

    Cullinan, Michael; Gorman, Jason

    2013-03-01

    Nanoelectromechanical (NEMS) resonators offer the potential to extend the limits of force and mass detection due to their small size, high natural frequencies and high Q-factors. Graphene-based NEMS resonators are particularly promising due to their high elastic modulus and atomic thickness. However, widespread use of graphene in such systems is limited by the way in which graphene-based devices are typically fabricated. Most graphene-based NEMS devices are fabricated in a ``one-off'' manner using slow, limited scale methods such as mechanical exfoliation, electron beam lithography, or transfer from copper foils which can't be incorporated into standard micro/nanofabrication lines. This talk will present a method that can be used to manufacture graphene-based NEMS devices at the wafer scale using conventional microfabrication techniques. In this method graphene is grown directly on thin film copper using chemical vapor deposition. The copper film is then patterned and etched to produce graphene-based NEMS resonators. This talk will also address some of the challenges in fabricating a large number of graphene devices at the wafer scale including achieving high uniformity across the wafer, increasing device-to-device repeatability, and producing high device yields.

  4. Wafer-scale growth of VO2 thin films using a combinatorial approach

    PubMed Central

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

    2015-01-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that ‘electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

  5. Fabrication of wafer-scale nanopatterned sapphire substrate through phase separation lithography

    NASA Astrophysics Data System (ADS)

    Guo, Xu; Ni, Mengyang; Zhuang, Zhe; Dai, Jiangping; Wu, Feixiang; Cui, Yushuang; Yuan, Changsheng; Ge, Haixiong; Chen, Yanfeng

    2016-04-01

    A phase separation lithography (PSL) based on polymer blend provides an extremely simple, low-cost, and high-throughput way to fabricate wafer-scale disordered nanopatterns. This method was introduced to fabricate nanopatterned sapphire substrates (NPSSs) for GaN-based light-emitting diodes (LEDs). The PSL process only involved in spin-coating of polystyrene (PS)/polyethylene glycol (PEG) polymer blend on sapphire substrate and followed by a development with deionized water to remove PEG moiety. The PS nanoporous network was facilely obtained, and the structural parameters could be effectively tuned by controlling the PS/PEG weight ratio of the spin-coating solution. 2-in. wafer-scale NPSSs were conveniently achieved through the PS nanoporous network in combination with traditional nanofabrication methods, such as O2 reactive ion etching (RIE), e-beam evaporation deposition, liftoff, and chlorine-based RIE. In order to investigate the performance of such NPSSs, typical blue LEDs with emission wavelengths of ~450 nm were grown on the NPSS and a flat sapphire substrate (FSS) by metal-organic chemical vapor deposition, respectively. The integral photoluminescence (PL) intensity of the NPSS LED was enhanced by 32.3 % compared to that of the FSS-LED. The low relative standard deviation of 4.7 % for PL mappings of NPSS LED indicated the high uniformity of PL data across the whole 2-in. wafer. Extremely simple, low cost, and high throughput of the process and the ability to fabricate at the wafer scale make PSL a potential method for production of nanopatterned sapphire substrates.

  6. Self-adaptive phosphor coating technology for wafer-level scale chip packaging

    NASA Astrophysics Data System (ADS)

    Linsong, Zhou; Haibo, Rao; Wei, Wang; Xianlong, Wan; Junyuan, Liao; Xuemei, Wang; Da, Zhou; Qiaolin, Lei

    2013-05-01

    A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.

  7. Wafer scale interdigitated nanoelectrode devices functionalized using a MEMS-based deposition system

    NASA Astrophysics Data System (ADS)

    Martinez-Rivas, A.; Carcenac, F.; Saya, D.; Séverac, C.; Nicu, L.; Vieu, C.

    2012-03-01

    This paper reports on a methodology to elaborate interdigitated nanoelectrode devices (INDs) at the wafer scale, relying on a mix-and-match process which combines proximity optical lithography and electron beam lithography. An optimum exposure dose allowed fabricating nanodevices, at the wafer level, with a successful yield of 97%. The final devices are bonded onto conventional TO-8 packages. Electrical characterization in a short-circuited nanoelectrode is performed, revealing a 230 µΩ cm resistivity value at 23 °C. A MEMS-based spotter made of cantilevers (called Bioplume) has been used to obtain precise functionalization of the INDs with sub-picoliter volume solutions. These INDs are the basis of multiple tunnel junction nanodevices, intended to serve as novel highly sensitive nanobiosensors.

  8. High-precision micro-optic elements by wafer-scale replication on arbitrary substrates

    NASA Astrophysics Data System (ADS)

    Dannberg, Peter; Bierbaum, Ralf; Erdmann, Lars; Krehl, A.; Braeuer, Andreas H.

    1999-09-01

    A solution is described for replication of polymer microoptical elements on arbitrary substrates. The replication is done on wafer scale level and includes the adjustment step between the optical elements and the substrate. Demonstrators are various microlens arrays, structures for the efficient coupling between monomode waveguides or multimode fibers and photodiodes, and between multimode waveguides and LED's. Out of the many different replication techniques, UV-reaction molding is chosen for this application. This technique has advantages against hot embossing and injection molding. Network polymers which are stable against temperature changes can be used. The replication is made in thin layers on a solid substrate resulting in high mechanical stability and very good flatness of the samples. The process introduces mechanical stress nor thermal load on the substrate which can be a fully processed semiconductor wafer containing elements like diodes or LEDs.

  9. 200 mm wafer-scale epitaxial transfer of single crystal Si on glass by anodic bonding of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Teh, W. H.; Trigg, Alastair; Tung, C. H.; Kumar, R.; Balasubramanian, N.; Kwong, D. L.

    2005-08-01

    We report a low-temperature (350 °C) anodic bonding followed by grind/etch-back method for a 200 mm wafer-scale epitaxial transfer of ultrathin (1.9 kÅ) single crystalline Si on Pyrex glass. Standard back-end-of-line 3 kÅ SiN/3 kÅ undoped silicon glass passivating films were used as the buffer layers between the silicon-on-insulator wafer and the glass wafer. The quality and strain-free state of the transferred transparent Si film to glass was characterized by cross-sectional transmission electron microscopy, x-ray diffraction (XRD), and high-resolution XRD. Complete removal of the bulk Si after bonding was ascertained by Auger electron spectroscopy spectra and depth profiling. Strong adhesion between the transferred film and the glass wafer was verified by standard tape adhesion tests. This process will pave the way for future generations of Si-based microelectronics including bioelectronics.

  10. LIGA Micromachining: Infrastructure Establishment

    SciTech Connect

    Alfredo M. Morales; Barry V. Hess; Dale R. Boehme; Jill M. Hruby; John S. Krafcik; Robert H. Nilson; Stewart K. Griffiths; William D. Bonivert

    1999-02-01

    LIGA is a micromachining technology that uses high energy x-rays from a synchrotron to create patterns with small lateral dimensions in a deep, non-conducting polymeric resist. Typical dimensions for LIGA parts are microns to tens of microns in lateral size, and hundreds of microns to millimeters in depth. Once the resist is patterned, metal is electrodeposited in the features to create metal microparts, or to create a metal mold for subsequent replication. The acronym LIGA comes from the German words for lithography, electroforming, and molding, and the technology has been under worldwide development for more than a decade. over the last five years, a full-service capability to produce metal microparts using the LIGA process has been established at Sandia national Laboratories, California. This report describes the accomplishments made during the past two years in infrastructure establishment funded by a Laboratory Directed Research and Development (LDRD) project entitled ''LIGA Micromachining.'' Specific topics include photoresist processing for LIGA mask making, x-ray scanning equipment, plating bath instrumentation, plating uniformity, and software architecture.

  11. Wafer-scale manufacturing and integration of micro-optical systems

    NASA Astrophysics Data System (ADS)

    Kathman, Alan D.; Boomgarden, Mark

    2001-11-01

    Demand for optical components and subsystems has exploded in the last decade. The question directed at component providers by customers is no longer when can you make it? The critical question is now become when can you make it in high volume? Wafer scale manufacturing, developed for the integrated circuit industry, has transitioned into the realm of optical fabrication and assembly. Photonic Chip optical subassemblies are products fabricated using these techniques. To create them, the optical elements are lithographically generated with integrated alignment and bonding features. Wafers of complimentary elements can be aligned and bonded at the wafer level, assembling hundreds of optical systems in parallel with a single operation. Electro-optical components, such as source and detector elements can be assembled into the system at the chip level, using flip-chip die bonding to complete the mechanical and electrical connection. The striking features of this manufacturing method are its parallel assembly techniques, broad use of automation, and very attractive intrinsic cost at high volume.

  12. Wafer-Scale, Homogeneous MoS2 Layers on Plastic Substrates for Flexible Visible-Light Photodetectors.

    PubMed

    Lim, Yi Rang; Song, Wooseok; Han, Jin Kyu; Lee, Young Bum; Kim, Sung Jun; Myung, Sung; Lee, Sun Sook; An, Ki-Seok; Choi, Chel-Jong; Lim, Jongsun

    2016-07-01

    An appropriate solution is suggested for synthesizing wafer-scale, continuous, and stoichiometric MoS2 layers with spatial homogeneity at the low temperature of 450 °C. It is also demonstrated that the MoS2 -based visible-light photodetector arrays are both fabricated on 4 inch SiO2 /Si wafer and polyimide films, revealing 100% active devices with a narrow photocurrent distribution and excellent mechanical durability. PMID:27119775

  13. Wafer-scale high-throughput ordered growth of vertically aligned ZnO nanowire arrays.

    PubMed

    Wei, Yaguang; Wu, Wenzhuo; Guo, Rui; Yuan, Dajun; Das, Suman; Wang, Zhong Lin

    2010-09-01

    This article presents an effective approach for patterned growth of vertically aligned ZnO nanowire (NW) arrays with high throughput and low cost at wafer scale without using cleanroom technology. Periodic hole patterns are generated using laser interference lithography on substrates coated with the photoresist SU-8. ZnO NWs are selectively grown through the holes via a low-temperature hydrothermal method without using a catalyst and with a superior control over orientation, location/density, and as-synthesized morphology. The development of textured ZnO seed layers for replacing single crystalline GaN and ZnO substrates extends the large-scale fabrication of vertically aligned ZnO NW arrays on substrates of other materials, such as polymers, Si, and glass. This combined approach demonstrates a novel method of manufacturing large-scale patterned one-dimensional nanostructures on various substrates for applications in energy harvesting, sensing, optoelectronics, and electronic devices. PMID:20681617

  14. A Method to Pattern Silver Nanowires Directly on Wafer-Scale PDMS Substrate and Its Applications.

    PubMed

    Chou, Namsun; Kim, Youngseok; Kim, Sohee

    2016-03-01

    This study describes a fabrication method of microsized AgNW patterns based on poly dimethylsiloxane (PDMS) substrate using a poly(p-xylylene) (parylene) stencil technique. Various patterns of AgNW conductive sheets were created on the wafer scale area in the forms of straight and serpentine lines, texts, and symbols, which dimensions ranged from a few tens of micrometers to hundreds of micrometers. We demonstrated the electrical performance of straight line and serpentine line patterned AgNW electrodes when subjected to mechanical strains. The gauge factor and stretchability ranged from 0.5 to 55.2 at 2% uniaxial strain and from 4.7 to 55.7%, respectively, depending on the shapes and structures of the AgNW electrodes. Using the developed AgNW patterning technique, we fabricated strain sensors to detect small body signals epidermally such as hand motion, eye blink and heart rate. Also, tactile sensors were fabricated and exhibited the sensitivity of 3.91 MPa(-1) in the pressure range lower than 50 kPa, and 0.28 MPa(-1) in the pressure range greater than 50 kPa up to 1.3 MPa. From these results, we concluded that the proposed technique enables the fabrication of reliable AgNW patterns on wafer-scale PDMS substrate and the potential applications for various flexible electronic devices. PMID:26882099

  15. Wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible biomedical platform.

    PubMed

    Maeng, Jimin; Meng, Chuizhou; Irazoqui, Pedro P

    2015-02-01

    We present wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible parylene platform, as progress toward sustainably powering biomedical microsystems suitable for implantable and wearable applications. All-solid-state, low-profile (<30 μm), and high-density (up to ~500 μF/mm(2)) micro-supercapacitors are formed on an ultrathin (~20 μm) freestanding parylene film by a wafer-scale parylene packaging process in combination with a polyaniline (PANI) nanowire growth technique assisted by surface plasma treatment. These micro-supercapacitors are highly flexible and shown to be resilient toward flexural stress. Further, direct integration of micro-supercapacitors into a radio frequency (RF) rectifying circuit is achieved on a single parylene platform, yielding a complete RF energy harvesting microsystem. The system discharging rate is shown to improve by ~17 times in the presence of the integrated micro-supercapacitors. This result suggests that the integrated micro-supercapacitor technology described herein is a promising strategy for sustainably powering biomedical microsystems dedicated to implantable and wearable applications. PMID:25653069

  16. Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

    PubMed Central

    Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

    2014-01-01

    In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

  17. Wafer-scale process and materials optimization in cross-flow atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Lecordier, Laurent Christophe

    The exceptional thickness control (atomic scale) and conformality (uniformity over nanoscale 3D features) of atomic layer deposition (ALD) has made it the process of choice for numerous applications from microelectronics to nanotechnology, and for a wide variety of ALD processes and resulting materials. While its benefits derive from self-terminated chemisorbed reactions of alternatively supplied gas precursors, identifying a suitable process window in which ALD's benefits are realized can be a challenge, even in favorable cases. In this work, a strategy exploiting in-situ gas phase sensing in conjunction with ex-situ measurements of the film properties at the wafer scale is employed to explore and optimize the prototypical Al2O3 ALD process. Downstream mass-spectrometry is first used to rapidly identify across the [H2O x Al(CH3)3] process space the exposure conditions leading to surface saturation. The impact of precursor doses outside as well as inside the parameter space outlined by mass-spectrometry is then investigated by characterizing film properties across 100 mm wafer using spectroscopic ellipsometry, CV and IV electrical characterization, XPS and SIMS. Under ideal dose conditions, excellent thickness uniformity was achieved (1sigma/mean<1%) in conjunction with a deposition rate and electrical properties in good agreement with best literature data. As expected, under-dosing of precursor results in depletion of film growth in the flow direction across the wafer surface. Since adsorbed species are reactive with respect to subsequent dose of the complementary precursor, such depletion magnifies non-uniformities as seen in the cross-flow reactor, thereby decorating deviations from a suitable ALD process recipe. Degradation of the permittivity and leakage current density across the wafer was observed though the film composition remained unchanged. Upon higher water dose in the over-exposure regime, deposition rates increased by up to 40% while the uniformity

  18. Face-to-face transfer of wafer-scale graphene films

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying

  19. Face-to-face transfer of wafer-scale graphene films.

    PubMed

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying

  20. Assembly of LIGA using Electric Fields

    SciTech Connect

    FEDDEMA, JOHN T.; WARNE, LARRY K.; JOHNSON, WILLIAM A.; OGDEN, ALLISON J.; ARMOUR, DAVID L.

    2002-04-01

    The goal of this project was to develop a device that uses electric fields to grasp and possibly levitate LIGA parts. This non-contact form of grasping would solve many of the problems associated with grasping parts that are only a few microns in dimensions. Scaling laws show that for parts this size, electrostatic and electromagnetic forces are dominant over gravitational forces. This is why micro-parts often stick to mechanical tweezers. If these forces can be controlled under feedback control, the parts could be levitated, possibly even rotated in air. In this project, we designed, fabricated, and tested several grippers that use electrostatic and electromagnetic fields to grasp and release metal LIGA parts. The eventual use of this tool will be to assemble metal and non-metal LIGA parts into small electromechanical systems.

  1. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

    PubMed Central

    Berman, Diana; Deshmukh, Sanket A.; Narayanan, Badri; Sankaranarayanan, Subramanian K. R. S.; Yan, Zhong; Balandin, Alexander A.; Zinovev, Alexander; Rosenmann, Daniel; Sumant, Anirudha V.

    2016-01-01

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the process can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. In addition, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics. PMID:27373740

  2. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale.

    PubMed

    Berman, Diana; Deshmukh, Sanket A; Narayanan, Badri; Sankaranarayanan, Subramanian K R S; Yan, Zhong; Balandin, Alexander A; Zinovev, Alexander; Rosenmann, Daniel; Sumant, Anirudha V

    2016-01-01

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the process can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. In addition, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics. PMID:27373740

  3. Wafer-scale fabrication and growth dynamics of suspended graphene nanoribbon arrays

    NASA Astrophysics Data System (ADS)

    Suzuki, Hiroo; Kaneko, Toshiro; Shibuta, Yasushi; Ohno, Munekazu; Maekawa, Yuki; Kato, Toshiaki

    2016-06-01

    Adding a mechanical degree of freedom to the electrical and optical properties of atomically thin materials can provide an excellent platform to investigate various optoelectrical physics and devices with mechanical motion interaction. The large scale fabrication of such atomically thin materials with suspended structures remains a challenge. Here we demonstrate the wafer-scale bottom-up synthesis of suspended graphene nanoribbon arrays (over 1,000,000 graphene nanoribbons in 2 × 2 cm2 substrate) with a very high yield (over 98%). Polarized Raman measurements reveal graphene nanoribbons in the array can have relatively uniform-edge structures with near zigzag orientation dominant. A promising growth model of suspended graphene nanoribbons is also established through a comprehensive study that combined experiments, molecular dynamics simulations and theoretical calculations with a phase-diagram analysis. We believe that our results can contribute to pushing the study of graphene nanoribbons into a new stage related to the optoelectrical physics and industrial applications.

  4. Fabrication of CVD graphene-based devices via laser ablation for wafer-scale characterization

    NASA Astrophysics Data System (ADS)

    Mackenzie, David M. A.; Buron, Jonas D.; Whelan, Patrick R.; Jessen, Bjarke S.; Silajdźić, Adnan; Pesquera, Amaia; Centeno, Alba; Zurutuza, Amaia; Bøggild, Peter; Petersen, Dirch H.

    2015-12-01

    Selective laser ablation of a wafer-scale graphene film is shown to provide flexible, high speed (1 wafer/hour) device fabrication while avoiding the degradation of electrical properties associated with traditional lithographic methods. Picosecond laser pulses with single pulse peak fluences of 140 mJ cm-2 for 1064 nm, 40 mJ cm-2 for 532 nm, and 30 mJ cm-2 for 355 nm are sufficient to ablate the graphene film, while the ablation onset for Si/SiO2 (thicknesses 500 μm/302 nm) did not occur until 240 mJ cm-2, 150 mJ cm-2, and 135 mJ cm-2, respectively, allowing all wavelengths to be used for graphene ablation without detectable substrate damage. Optical microscopy and Raman Spectroscopy were used to assess the ablation of graphene, while stylus profilometery indicated that the SiO2 substrate was undamaged. CVD graphene devices were electrically characterized and showed comparable field-effect mobility, doping level, on-off ratio, and conductance minimum before and after laser ablation fabrication.

  5. Wafer-scale epitaxial graphene on SiC for sensing applications

    NASA Astrophysics Data System (ADS)

    Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

    2015-12-01

    The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

  6. Wafer-scale growth of MoS2 thin films by atomic layer deposition.

    PubMed

    Pyeon, Jung Joon; Kim, Soo Hyun; Jeong, Doo Seok; Baek, Seung-Hyub; Kang, Chong-Yun; Kim, Jin-Sang; Kim, Seong Keun

    2016-05-19

    The wafer-scale synthesis of MoS2 layers with precise thickness controllability and excellent uniformity is essential for their application in the nanoelectronics industry. Here, we demonstrate the atomic layer deposition (ALD) of MoS2 films with Mo(CO)6 and H2S as the Mo and S precursors, respectively. A self-limiting growth behavior is observed in the narrow ALD window of 155-175 °C. Long H2S feeding times are necessary to reduce the impurity contents in the films. The as-grown MoS2 films are amorphous due to the low growth temperature. Post-annealing at high temperatures under a H2S atmosphere efficiently improves the film properties including the crystallinity and chemical composition. An extremely uniform film growth is achieved even on a 4 inch SiO2/Si wafer. These results demonstrate that the current ALD process is well suited for the synthesis of MoS2 layers for application in industry. PMID:27166838

  7. Wafer-scale growth of MoS2 thin films by atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Pyeon, Jung Joon; Kim, Soo Hyun; Jeong, Doo Seok; Baek, Seung-Hyub; Kang, Chong-Yun; Kim, Jin-Sang; Kim, Seong Keun

    2016-05-01

    The wafer-scale synthesis of MoS2 layers with precise thickness controllability and excellent uniformity is essential for their application in the nanoelectronics industry. Here, we demonstrate the atomic layer deposition (ALD) of MoS2 films with Mo(CO)6 and H2S as the Mo and S precursors, respectively. A self-limiting growth behavior is observed in the narrow ALD window of 155-175 °C. Long H2S feeding times are necessary to reduce the impurity contents in the films. The as-grown MoS2 films are amorphous due to the low growth temperature. Post-annealing at high temperatures under a H2S atmosphere efficiently improves the film properties including the crystallinity and chemical composition. An extremely uniform film growth is achieved even on a 4 inch SiO2/Si wafer. These results demonstrate that the current ALD process is well suited for the synthesis of MoS2 layers for application in industry.

  8. Wafer scale fabrication of submicron chessboard gratings using phase masks in proximity lithography

    NASA Astrophysics Data System (ADS)

    Stuerzebecher, Lorenz; Harzendorf, Torsten; Fuchs, Frank; Zeitner, Uwe D.

    2012-03-01

    One and two dimensional grating structures with submicron period have a huge number of applications in optics and photonics. Such structures are conventionally fabricated using interference or e-beam lithography. However, both technologies have significant drawbacks. Interference lithography is limited to rather simple geometries and the sequential writing scheme of e-beam lithography leads to time consuming exposures for each grating. We present a novel fabrication technique for this class of microstructures which is based on proximity lithography in a mask aligner. The technology is capable to pattern a complete wafer within less than one minute of exposure time and offers thereby high lateral resolution and a reliable process. Our advancements compared to standard mask aligner lithography are twofold: First of all, we are using periodic binary phase masks instead of chromium masks to generate an aerial image of high resolution and exceptional light efficiency at certain distances behind the mask. Second, a special mask aligner illumination set-up is employed which allows to precisely control the incidence angles of the exposure light. This degree of freedom allows both, to shape the aerial image (e. g. transformation of a periodic spot pattern into a chessboard pattern) and to increase its depth of focus considerably. That way, our technology enables the fabrication of high quality gratings with arbitrary geometry in a fast and stable wafer scale process.

  9. Terahertz wafer-scale mobility mapping of graphene on insulating substrates without a gate.

    PubMed

    Buron, Jonas D; Mackenzie, David M A; Petersen, Dirch H; Pesquera, Amaia; Centeno, Alba; Bøggild, Peter; Zurutuza, Amaia; Jepsen, Peter U

    2015-11-30

    We demonstrate wafer-scale, non-contact mapping of essential carrier transport parameters, carrier mobility (µdrift), carrier density (Ns), DC sheet conductance (σdc), and carrier scattering time (τsc) in CVD graphene, using spatially resolved terahertz time-domain conductance spectroscopy. σdc and τsc are directly extracted from Drude model fits to terahertz conductance spectra obtained in each pixel of 10 × 10 cm2 maps with a 400 µm step size. σdc- and τsc-maps are translated into µdrift and Ns maps through Boltzmann transport theory for graphene charge carriers and these parameters are directly compared to van der Pauw device measurements on the same wafer. The technique is compatible with all substrate materials that exhibit a reasonably low absorption coefficient for terahertz radiation. This includes many materials used for transferring CVD graphene in production facilities as well as in envisioned products, such as polymer films, glass substrates, cloth, or paper substrates. PMID:26698704

  10. High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity.

    PubMed

    Kang, Kibum; Xie, Saien; Huang, Lujie; Han, Yimo; Huang, Pinshane Y; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-04-30

    The large-scale growth of semiconducting thin films forms the basis of modern electronics and optoelectronics. A decrease in film thickness to the ultimate limit of the atomic, sub-nanometre length scale, a difficult limit for traditional semiconductors (such as Si and GaAs), would bring wide benefits for applications in ultrathin and flexible electronics, photovoltaics and display technology. For this, transition-metal dichalcogenides (TMDs), which can form stable three-atom-thick monolayers, provide ideal semiconducting materials with high electrical carrier mobility, and their large-scale growth on insulating substrates would enable the batch fabrication of atomically thin high-performance transistors and photodetectors on a technologically relevant scale without film transfer. In addition, their unique electronic band structures provide novel ways of enhancing the functionalities of such devices, including the large excitonic effect, bandgap modulation, indirect-to-direct bandgap transition, piezoelectricity and valleytronics. However, the large-scale growth of monolayer TMD films with spatial homogeneity and high electrical performance remains an unsolved challenge. Here we report the preparation of high-mobility 4-inch wafer-scale films of monolayer molybdenum disulphide (MoS2) and tungsten disulphide, grown directly on insulating SiO2 substrates, with excellent spatial homogeneity over the entire films. They are grown with a newly developed, metal-organic chemical vapour deposition technique, and show high electrical performance, including an electron mobility of 30 cm(2) V(-1) s(-1) at room temperature and 114 cm(2) V(-1) s(-1) at 90 K for MoS2, with little dependence on position or channel length. With the use of these films we successfully demonstrate the wafer-scale batch fabrication of high-performance monolayer MoS2 field-effect transistors with a 99% device yield and the multi-level fabrication of vertically stacked transistor devices for three

  11. Wafer-scale MoS2 thin layers prepared by MoO3 sulfurization.

    PubMed

    Lin, Yu-Chuan; Zhang, Wenjing; Huang, Jing-Kai; Liu, Keng-Ku; Lee, Yi-Hsien; Liang, Chi-Te; Chu, Chih-Wei; Li, Lain-Jong

    2012-10-21

    Atomically thin molybdenum disulfide (MoS(2)) layers have attracted great interest due to their direct-gap property and potential applications in optoelectronics and energy harvesting. Meanwhile, they are extremely bendable, promising for applications in flexible electronics. However, the synthetic approach to obtain large-area MoS(2) atomic thin layers is still lacking. Here we report that wafer-scale MoS(2) thin layers can be obtained using MoO(3) thin films as a starting material followed by a two-step thermal process, reduction of MoO(3) at 500 °C in hydrogen and sulfurization at 1000 °C in the presence of sulfur. Spectroscopic, optical and electrical characterizations reveal that these films are polycrystalline and with semiconductor properties. The obtained MoS(2) films are uniform in thickness and easily transferable to arbitrary substrates, which make such films suitable for flexible electronics or optoelectronics. PMID:22983609

  12. Wafer-scale, three-dimensional helical porous thin films deposited at a glancing angle

    NASA Astrophysics Data System (ADS)

    Huang, Zhifeng; Bai, Fan

    2014-07-01

    Minimization of helices opens a door to impose novel functions derived from the dimensional shrinkage of optical, mechanical and electronic devices. Glancing angle deposition (GLAD) enables one to deposit three-dimensional helical porous thin films (HPTFs) composed of separated spiral micro/nano-columns. GLAD integrates a series of advantageous features, including one-step deposition, wafer-scale production with mono-handedness of spirals, flexible engineering of spiral materials and dimensions, and the adaption to various kinds of substrates. Herein, we briefly review the fabrication of HPTFs by GLAD, specific growth mechanisms, physical properties in structures, mechanics and chiral optics, and the emerging applications in green energy. A prospective outlook is presented to illuminate some promising developments in enantioselection, bio-dynamic analyses, wirelessly-controlled drug delivery and mass production.

  13. Near-infrared tailored thermal emission from wafer-scale continuous-film resonators.

    PubMed

    Roberts, Alexander S; Chirumamilla, Manohar; Thilsing-Hansen, Kasper; Pedersen, Kjeld; Bozhevolnyi, Sergey I

    2015-09-21

    We experimentally investigate the near-infrared emission from simple-to-fabricate, continuous-film Fabry-Perot-type resonators, consisting only of unstructured dielectric and metallic films. We show that the proposed configuration is suitable for realization of narrowband emitters, tunable in ranges from mid- to near-infrared, and demonstrate emission centered at the wavelength of 1.7 μm, which corresponds to the band gap energy of GaSb-based photodetectors. The emission is measured at 748 K and follows well the emissivity as predicted from reflection measurements and Kirchhoff's reciprocity. The considered emitter configuration is spectrally highly tunable and, consisting of only few unstructured layers, is amenable to wafer-scale fabrication at low cost by use of standard deposition procedures. PMID:26406741

  14. High speed wafer scale bulge testing for the determination of thin film mechanical properties

    NASA Astrophysics Data System (ADS)

    Orthner, M. P.; Rieth, L. W.; Solzbacher, F.

    2010-05-01

    A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50-150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 μm in width comprised of 720±10 nm thick low pressure chemical vapor deposited silicon nitride with ˜20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to ˜8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (˜350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young's modulus was estimated for the films assuming a Poisson's ratio of v =0.25. Calculations to determine Young's modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young's modulus for the smaller membranes. The deflection measurements of three 1200×1200 μm2 Si3N4-x

  15. High speed wafer scale bulge testing for the determination of thin film mechanical properties

    PubMed Central

    Orthner, M. P.; Rieth, L. W.; Solzbacher, F.

    2010-01-01

    A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50–150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 μm in width comprised of 720±10 nm thick low pressure chemical vapor deposited silicon nitride with ∼20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to ∼8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (∼350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young’s modulus was estimated for the films assuming a Poisson’s ratio of v=0.25. Calculations to determine Young’s modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young’s modulus for the smaller membranes. The deflection measurements of three 1200×1200

  16. High speed wafer scale bulge testing for the determination of thin film mechanical properties.

    PubMed

    Orthner, M P; Rieth, L W; Solzbacher, F

    2010-05-01

    A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50-150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 microm in width comprised of 720+/-10 nm thick low pressure chemical vapor deposited silicon nitride with approximately 20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to approximately 8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (approximately 350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young's modulus was estimated for the films assuming a Poisson's ratio of v=0.25. Calculations to determine Young's modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young's modulus for the smaller membranes. The deflection

  17. Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale

    PubMed Central

    2013-01-01

    We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production. PMID:24289275

  18. Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale

    NASA Astrophysics Data System (ADS)

    Ho, Jian-Wei; Wee, Qixun; Dumond, Jarrett; Tay, Andrew; Chua, Soo-Jin

    2013-12-01

    We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production.

  19. Wafer-scale fabrication and growth dynamics of suspended graphene nanoribbon arrays

    PubMed Central

    Suzuki, Hiroo; Kaneko, Toshiro; Shibuta, Yasushi; Ohno, Munekazu; Maekawa, Yuki; Kato, Toshiaki

    2016-01-01

    Adding a mechanical degree of freedom to the electrical and optical properties of atomically thin materials can provide an excellent platform to investigate various optoelectrical physics and devices with mechanical motion interaction. The large scale fabrication of such atomically thin materials with suspended structures remains a challenge. Here we demonstrate the wafer-scale bottom–up synthesis of suspended graphene nanoribbon arrays (over 1,000,000 graphene nanoribbons in 2 × 2 cm2 substrate) with a very high yield (over 98%). Polarized Raman measurements reveal graphene nanoribbons in the array can have relatively uniform-edge structures with near zigzag orientation dominant. A promising growth model of suspended graphene nanoribbons is also established through a comprehensive study that combined experiments, molecular dynamics simulations and theoretical calculations with a phase-diagram analysis. We believe that our results can contribute to pushing the study of graphene nanoribbons into a new stage related to the optoelectrical physics and industrial applications. PMID:27250877

  20. Wafer-Scale Monolayer Films of Semiconducting Metal Dichalcogenides for High-Performance Electronics

    NASA Astrophysics Data System (ADS)

    Xie, Saien; Kang, Kibum; Huang, Lujie; Han, Yimo; Huang, Pinshane; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-03-01

    Two-dimensional semiconducting transition metal dichalcogenides (TMDs) have shown their potential in electronics, optoelectronic and valleytronis. However, large-scale growth methods reported to date have only produced materials with limited structural and electrical uniformity, hindering further technological applications. Here we present a 4-inch scale growth of continuous monolayer molybdenum disulfide (MoS2) and tungsten disulfide (WS2) films that show excellent structural and electrical uniformity over the entire wafer using metal-organic chemical vapor deposition. The resulting monolayer films show high mobility of 30 cm2/Vs at room temperature, as well as the phonon-limited transport for MoS2, regardless of the channel length and device location. They allow for the batch fabrication of monolayer MoS2 field effect transistors with a 99% yield, which display spatially-uniform n-type transistor operation with a high on/off ratio. We further demonstrate the multi-level growth and fabrication of vertically-stacked monolayer MoS2 films and devices, which could enable the development of novel three-dimensional circuitry and device integration.

  1. Resolution enhancement using plasmonic metamask for wafer-scale photolithography in the far field

    PubMed Central

    Baek, Seunghwa; Kang, Gumin; Kang, Min; Lee, Chang-Won; Kim, Kyoungsik

    2016-01-01

    Resolution enhancement in far-field photolithography is demonstrated using a plasmonic metamask in the proximity regime, in which Fresnel diffraction is dominant. The transverse magnetic component of the diffracted wave from the photomask, which reduces the pattern visibility and lowers the resolution, was successfully controlled by coupling with the anti-symmetric mode of the excited surface plasmon. We obtained a consistently finely-patterned photoresist surface at a distance of up to 15 μm from the mask surface for 3-μm-pitch slits because of conserved field visibility when propagating from the near-field to the proximity regime. We confirmed that sharp edge patterning is indeed possible when using a wafer-scale photomask in the proximity photolithography regime. Our plasmonic metamask method produces cost savings for ultra-large-scale high-density display fabrication by maintaining longer photomask lifetimes and by allowing sufficient tolerance for the distance between the photomask and the photoresist. PMID:27457127

  2. Resolution enhancement using plasmonic metamask for wafer-scale photolithography in the far field.

    PubMed

    Baek, Seunghwa; Kang, Gumin; Kang, Min; Lee, Chang-Won; Kim, Kyoungsik

    2016-01-01

    Resolution enhancement in far-field photolithography is demonstrated using a plasmonic metamask in the proximity regime, in which Fresnel diffraction is dominant. The transverse magnetic component of the diffracted wave from the photomask, which reduces the pattern visibility and lowers the resolution, was successfully controlled by coupling with the anti-symmetric mode of the excited surface plasmon. We obtained a consistently finely-patterned photoresist surface at a distance of up to 15 μm from the mask surface for 3-μm-pitch slits because of conserved field visibility when propagating from the near-field to the proximity regime. We confirmed that sharp edge patterning is indeed possible when using a wafer-scale photomask in the proximity photolithography regime. Our plasmonic metamask method produces cost savings for ultra-large-scale high-density display fabrication by maintaining longer photomask lifetimes and by allowing sufficient tolerance for the distance between the photomask and the photoresist. PMID:27457127

  3. Wafer-scale MoS2 thin layers prepared by MoO3 sulfurization

    NASA Astrophysics Data System (ADS)

    Lin, Yu-Chuan; Zhang, Wenjing; Huang, Jing-Kai; Liu, Keng-Ku; Lee, Yi-Hsien; Liang, Chi-Te; Chu, Chih-Wei; Li, Lain-Jong

    2012-09-01

    Atomically thin molybdenum disulfide (MoS2) layers have attracted great interest due to their direct-gap property and potential applications in optoelectronics and energy harvesting. Meanwhile, they are extremely bendable, promising for applications in flexible electronics. However, the synthetic approach to obtain large-area MoS2 atomic thin layers is still lacking. Here we report that wafer-scale MoS2 thin layers can be obtained using MoO3 thin films as a starting material followed by a two-step thermal process, reduction of MoO3 at 500 °C in hydrogen and sulfurization at 1000 °C in the presence of sulfur. Spectroscopic, optical and electrical characterizations reveal that these films are polycrystalline and with semiconductor properties. The obtained MoS2 films are uniform in thickness and easily transferable to arbitrary substrates, which make such films suitable for flexible electronics or optoelectronics.Atomically thin molybdenum disulfide (MoS2) layers have attracted great interest due to their direct-gap property and potential applications in optoelectronics and energy harvesting. Meanwhile, they are extremely bendable, promising for applications in flexible electronics. However, the synthetic approach to obtain large-area MoS2 atomic thin layers is still lacking. Here we report that wafer-scale MoS2 thin layers can be obtained using MoO3 thin films as a starting material followed by a two-step thermal process, reduction of MoO3 at 500 °C in hydrogen and sulfurization at 1000 °C in the presence of sulfur. Spectroscopic, optical and electrical characterizations reveal that these films are polycrystalline and with semiconductor properties. The obtained MoS2 films are uniform in thickness and easily transferable to arbitrary substrates, which make such films suitable for flexible electronics or optoelectronics. Electronic supplementary information (ESI) available. See DOI: 10.1039/c2nr31833d

  4. Wafer-scale high-resolution patterning of reduced graphene oxide films for detection of low concentration biomarkers in plasma

    NASA Astrophysics Data System (ADS)

    Kim, Jinsik; Chae, Myung-Sic; Lee, Sung Min; Jeong, Dahye; Lee, Byung Chul; Lee, Jeong Hoon; Kim, Youngsoo; Chang, Suk Tai; Hwang, Kyo Seon

    2016-08-01

    Given that reduced graphene oxide (rGO)-based biosensors allow disposable and repeatable biomarker detection at the point of care, we developed a wafer-scale rGO patterning method with mass productivity, uniformity, and high resolution by conventional micro-electro-mechanical systems (MEMS) techniques. Various rGO patterns were demonstrated with dimensions ranging from 5 μm up to several hundred μm. Manufacture of these patterns was accomplished through the optimization of dry etching conditions. The axis-homogeneity and uniformity were also measured to verify the uniform patternability in 4-inch wafer with dry etching. Over 66.2% of uniform rGO patterns, which have deviation of resistance within range of ±10%, formed the entire wafer. We selected amyloid beta (Aβ) peptides in the plasma of APP/PS1 transgenic mice as a study model and measured the peptide level by resistance changes of highly uniform rGO biosensor arrays. Aβ is a pathological hallmark of Alzheimer’s disease and its plasma concentration is in the pg mL‑1 range. The sensor detected the Aβ peptides with ultra-high sensitivity; the LOD was at levels as low as 100 fg mL‑1. Our results provide biological evidences that this wafer-scale high-resolution patterning method can be used in rGO-based electrical diagnostic devices for detection of low-level protein biomarkers in biofluids.

  5. Wafer-scale high-resolution patterning of reduced graphene oxide films for detection of low concentration biomarkers in plasma.

    PubMed

    Kim, Jinsik; Chae, Myung-Sic; Lee, Sung Min; Jeong, Dahye; Lee, Byung Chul; Lee, Jeong Hoon; Kim, YoungSoo; Chang, Suk Tai; Hwang, Kyo Seon

    2016-01-01

    Given that reduced graphene oxide (rGO)-based biosensors allow disposable and repeatable biomarker detection at the point of care, we developed a wafer-scale rGO patterning method with mass productivity, uniformity, and high resolution by conventional micro-electro-mechanical systems (MEMS) techniques. Various rGO patterns were demonstrated with dimensions ranging from 5 μm up to several hundred μm. Manufacture of these patterns was accomplished through the optimization of dry etching conditions. The axis-homogeneity and uniformity were also measured to verify the uniform patternability in 4-inch wafer with dry etching. Over 66.2% of uniform rGO patterns, which have deviation of resistance within range of ±10%, formed the entire wafer. We selected amyloid beta (Aβ) peptides in the plasma of APP/PS1 transgenic mice as a study model and measured the peptide level by resistance changes of highly uniform rGO biosensor arrays. Aβ is a pathological hallmark of Alzheimer's disease and its plasma concentration is in the pg mL(-1) range. The sensor detected the Aβ peptides with ultra-high sensitivity; the LOD was at levels as low as 100 fg mL(-1). Our results provide biological evidences that this wafer-scale high-resolution patterning method can be used in rGO-based electrical diagnostic devices for detection of low-level protein biomarkers in biofluids. PMID:27506288

  6. Wafer-scale high-resolution patterning of reduced graphene oxide films for detection of low concentration biomarkers in plasma

    PubMed Central

    Kim, Jinsik; Chae, Myung-Sic; Lee, Sung Min; Jeong, Dahye; Lee, Byung Chul; Lee, Jeong Hoon; Kim, YoungSoo; Chang, Suk Tai; Hwang, Kyo Seon

    2016-01-01

    Given that reduced graphene oxide (rGO)-based biosensors allow disposable and repeatable biomarker detection at the point of care, we developed a wafer-scale rGO patterning method with mass productivity, uniformity, and high resolution by conventional micro-electro-mechanical systems (MEMS) techniques. Various rGO patterns were demonstrated with dimensions ranging from 5 μm up to several hundred μm. Manufacture of these patterns was accomplished through the optimization of dry etching conditions. The axis-homogeneity and uniformity were also measured to verify the uniform patternability in 4-inch wafer with dry etching. Over 66.2% of uniform rGO patterns, which have deviation of resistance within range of ±10%, formed the entire wafer. We selected amyloid beta (Aβ) peptides in the plasma of APP/PS1 transgenic mice as a study model and measured the peptide level by resistance changes of highly uniform rGO biosensor arrays. Aβ is a pathological hallmark of Alzheimer’s disease and its plasma concentration is in the pg mL−1 range. The sensor detected the Aβ peptides with ultra-high sensitivity; the LOD was at levels as low as 100 fg mL−1. Our results provide biological evidences that this wafer-scale high-resolution patterning method can be used in rGO-based electrical diagnostic devices for detection of low-level protein biomarkers in biofluids. PMID:27506288

  7. Wafer-scale arrays of nonvolatile polymer memories with microprinted semiconducting small molecule/polymer blends.

    PubMed

    Bae, Insung; Hwang, Sun Kak; Kim, Richard Hahnkee; Kang, Seok Ju; Park, Cheolmin

    2013-11-13

    Nonvolatile ferroelectric-gate field-effect transistors (Fe-FETs) memories with solution-processed ferroelectric polymers are of great interest because of their potential for use in low-cost flexible devices. In particular, the development of a process for patterning high-performance semiconducting channel layers with mechanical flexibility is essential not only for proper cell-to-cell isolation but also for arrays of flexible nonvolatile memories. We demonstrate a robust route for printing large-scale micropatterns of solution-processed semiconducting small molecules/insulating polymer blends for high performance arrays of nonvolatile ferroelectric polymer memory. The nonvolatile memory devices are based on top-gate/bottom-contact Fe-FET with ferroelectric polymer insulator and micropatterned semiconducting blend channels. Printed micropatterns of a thin blended semiconducting film were achieved by our selective contact evaporation printing, with which semiconducting small molecules in contact with a micropatterned elastomeric poly(dimethylsiloxane) (PDMS) mold were preferentially evaporated and absorbed into the PDMS mold while insulating polymer remained intact. Well-defined micrometer-scale patterns with various shapes and dimensions were readily developed over a very large area on a 4 in. wafer, allowing for fabrication of large-scale printed arrays of Fe-FETs with highly uniform device performance. We statistically analyzed the memory properties of Fe-FETs, including ON/OFF ratio, operation voltage, retention, and endurance, as a function of the micropattern dimensions of the semiconducting films. Furthermore, roll-up memory arrays were produced by successfully detaching large-area Fe-FETs printed on a flexible substrate with a transient adhesive layer from a hard substrate and subsequently transferring them to a nonplanar surface. PMID:24070419

  8. Surface plasmon assisted hot electron collection in wafer-scale metallic-semiconductor photonic crystals.

    PubMed

    Chou, Jeffrey B; Li, Xin-Hao; Wang, Yu; Fenning, David P; Elfaer, Asmaa; Viegas, Jaime; Jouiad, Mustapha; Shao-Horn, Yang; Kim, Sang-Gook

    2016-09-01

    Plasmon assisted photoelectric hot electron collection in a metal-semiconductor junction can allow for sub-bandgap optical to electrical energy conversion. Here we report hot electron collection by wafer-scale Au/TiO2 metallic-semiconductor photonic crystals (MSPhC), with a broadband photoresponse below the bandgap of TiO2. Multiple absorption modes supported by the 2D nano-cavity structure of the MSPhC extend the photon-metal interaction time and fulfill a broadband light absorption. The surface plasmon absorption mode provides access to enhanced electric field oscillation and hot electron generation at the interface between Au and TiO2. A broadband sub-bandgap photoresponse centered at 590 nm was achieved due to surface plasmon absorption. Gold nanorods were deposited on the surface of MSPhC to study localized surface plasmon (LSP) mode absorption and subsequent injection to the TiO2 catalyst at different wavelengths. Applications of these results could lead to low-cost and robust photo-electrochemical applications such as more efficient solar water splitting. PMID:27607726

  9. Wafer-scale synthesis of multi-layer graphene by high-temperature carbon ion implantation

    SciTech Connect

    Kim, Janghyuk; Lee, Geonyeop; Kim, Jihyun

    2015-07-20

    We report on the synthesis of wafer-scale (4 in. in diameter) high-quality multi-layer graphene using high-temperature carbon ion implantation on thin Ni films on a substrate of SiO{sub 2}/Si. Carbon ions were bombarded at 20 keV and a dose of 1 × 10{sup 15 }cm{sup −2} onto the surface of the Ni/SiO{sub 2}/Si substrate at a temperature of 500 °C. This was followed by high-temperature activation annealing (600–900 °C) to form a sp{sup 2}-bonded honeycomb structure. The effects of post-implantation activation annealing conditions were systematically investigated by micro-Raman spectroscopy and transmission electron microscopy. Carbon ion implantation at elevated temperatures allowed a lower activation annealing temperature for fabricating large-area graphene. Our results indicate that carbon-ion implantation provides a facile and direct route for integrating graphene with Si microelectronics.

  10. Wafer-scale design of lightweight and transparent electronics that wraps around hairs

    NASA Astrophysics Data System (ADS)

    Salvatore, Giovanni A.; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

    2014-01-01

    Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

  11. Wafer-scale self-organized InP nanopillars with controlled orientation for photovoltaic devices.

    PubMed

    Sanatinia, Reza; Berrier, Audrey; Dhaka, Veer; Perros, Alexander P; Huhtio, Teppo; Lipsanen, Harri; Anand, Srinivasan

    2015-10-16

    A unique wafer-scale self-organization process for generation of InP nanopillars is demonstrated, which is based on maskless ion-beam etching (IBE) of InP developed to obtain the nanopillars, where the height, shape, and orientation of the nanopillars can be varied by controlling the processing parameters. The fabricated InP nanopillars exhibit broadband suppression of the reflectance, 'black InP,' a property useful for solar cells. The realization of a conformal p-n junction for carrier collection, in the fabricated solar cells, is achieved by a metalorganic vapor phase epitaxy (MOVPE) overgrowth step on the fabricated pillars. The conformal overgrowth retains the broadband anti-reflection property of the InP nanopillars, indicating the feasibility of this technology for solar cells. Surface passivation of the formed InP nanopillars using sulfur-oleylamine solution resulted in improved solar-cell characteristics. An open-circuit voltage of 0.71 V and an increase of 0.13 V compared to the unpassivated device were achieved. PMID:26403979

  12. Wafer-scale highly-transparent and superhydrophilic sapphires for high-performance optics.

    PubMed

    Leem, Jung Woo; Yu, Jae Su

    2012-11-19

    We reported the wafer-scale highly-transparent and superhydrophilic sapphires with antireflective subwavelength structures (SWSs) which were fabricated by dry etching using thermally dewetted gold (Au) nanomasks. Their optical transmittance properties were experimentally and theoretically investigated. The density, size, and period of the thermally dewetted Au nanopatterns can be controlled by the Au film thickness. For the sapphire with both-side SWSs at 5 nm of Au film, the average total transmittance (T(avg)) of ~96.5% at 350-800 nm was obtained, indicating a higher value than those of the flat sapphire (T(avg)~85.6%) and the sapphire with one-side SWSs (T(avg)~91%), and the less angle-dependent transmittance property was observed. The calculated transmittance results also showed a similar tendency to the measured data. The SWSs enhanced significantly the surface hydrophilicity of sapphires, exhibiting a water contact angle (θ(c)) of < 5° for Au film of 5 nm compared to θ(c)~37° of the flat sapphire. PMID:23187471

  13. Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy

    PubMed Central

    Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

    2013-01-01

    The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (“metasurfaces”) can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

  14. A wafer-scale backplane-assisted resonating nanoantenna array SERS device created by tunable thermal dewetting nanofabrication

    NASA Astrophysics Data System (ADS)

    Chang, Te-Wei; Ranjan Gartia, Manas; Seo, Sujin; Hsiao, Austin; Logan Liu, Gang

    2014-04-01

    A tunable lithography-less nanofabrication process using a metal thin-film thermal dewetting technique has been developed to fabricate wafer-scale and uniform plasmonic substrates at low cost for optimal performance in surface enhanced Raman scattering (SERS) applications. The relationship between the tunable parameters of this process and the corresponding optical and plasmonic characteristic is investigated both experimentally and theoretically to understand the deterministic design of an optimal SERS device with a three-dimensional plasmonic nanoantenna structure. The enhancement of SERS using various nanoplasmonic particle sizes, structure lengths, lateral hot spot spacings and resonating effects are examined and demonstrated. We achieve a uniform optimal enhancement factor of 1.38 × 108 on a 4 in wafer-scale SERS substrate with a backplane-assisted resonating nanoantenna array design. Sensitive environmental nitrate sensing, vitamin detection and oligonucleotide identification are demonstrated on the high-performance SERS device.

  15. Crack-release transfer method of wafer-scale grown graphene onto large-area substrates.

    PubMed

    Lee, Jooho; Kim, Yongsung; Shin, Hyeon-Jin; Lee, ChangSeung; Lee, Dongwook; Lee, Sunghee; Moon, Chang-Yul; Lee, Su Chan; Kim, Sun Jun; Ji, Jae Hoon; Yoon, Hyong Seo; Jun, Seong Chan

    2014-08-13

    We developed a crack-release graphene transfer technique for opening up possibilities for the fabrication of graphene-based devices. Graphene film grown on metal catalysts/SiO2/Si wafer should be scathelessly peeled for sequent transferring to a target substrate. However, when the graphene is grown on the metal catalyst on a silicon substrate, there is a large tensile stress resulting from the difference of the coefficient of thermal expansion in the catalyst and silicon. The conventional methods of detaching graphene from metal catalysts were found to induce considerable mechanical damage on graphene films during separation processes including metal wet etching. Here we report a new technique wherein bubbles generated by electrolysis reaction separate thin metal catalysts from the SiO2/Si wafer. The dry attachment of graphene to the target wafer was processed utilizing a wafer to wafer bonding technique in a vacuum. We measured the microscopic image, Raman spectra, and electrical properties of the transferred graphene. The optical and electrical properties of the graphene transferred by the bubbles/dry method are better than those of the graphene obtained by mechanical/wet transfer. PMID:24967530

  16. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  17. Field-effect transistors based on wafer-scale, highly uniform few-layer p-type WSe2

    NASA Astrophysics Data System (ADS)

    Campbell, Philip M.; Tarasov, Alexey; Joiner, Corey A.; Tsai, Meng-Yen; Pavlidis, Georges; Graham, Samuel; Ready, W. Jud; Vogel, Eric M.

    2016-01-01

    The synthesis of few-layer tungsten diselenide (WSe2) via chemical vapor deposition typically results in highly non-uniform thickness due to nucleation initiated growth of triangular domains. In this work, few-layer p-type WSe2 with wafer-scale thickness and electrical uniformity is synthesized through direct selenization of thin films of e-beam evaporated W on SiO2 substrates. Raman maps over a large area of the substrate show small variations in the main peak position, indicating excellent thickness uniformity across several square centimeters. Additionally, field-effect transistors fabricated from the wafer-scale WSe2 films demonstrate uniform electrical performance across the substrate. The intrinsic field-effect mobility of the films at a carrier concentration of 3 × 1012 cm-2 is 10 cm2 V-1 s-1. The unprecedented uniformity of the WSe2 on wafer-scale substrates provides a substantial step towards producing manufacturable materials that are compatible with conventional semiconductor fabrication processes.

  18. Field-effect transistors based on wafer-scale, highly uniform few-layer p-type WSe2.

    PubMed

    Campbell, Philip M; Tarasov, Alexey; Joiner, Corey A; Tsai, Meng-Yen; Pavlidis, Georges; Graham, Samuel; Ready, W Jud; Vogel, Eric M

    2016-01-28

    The synthesis of few-layer tungsten diselenide (WSe2) via chemical vapor deposition typically results in highly non-uniform thickness due to nucleation initiated growth of triangular domains. In this work, few-layer p-type WSe2 with wafer-scale thickness and electrical uniformity is synthesized through direct selenization of thin films of e-beam evaporated W on SiO2 substrates. Raman maps over a large area of the substrate show small variations in the main peak position, indicating excellent thickness uniformity across several square centimeters. Additionally, field-effect transistors fabricated from the wafer-scale WSe2 films demonstrate uniform electrical performance across the substrate. The intrinsic field-effect mobility of the films at a carrier concentration of 3 × 10(12) cm(-2) is 10 cm(2) V(-1) s(-1). The unprecedented uniformity of the WSe2 on wafer-scale substrates provides a substantial step towards producing manufacturable materials that are compatible with conventional semiconductor fabrication processes. PMID:26743173

  19. Surface microstructuring of biocompatible bone analogue material HAPEX using LIGA technique and embossing

    NASA Astrophysics Data System (ADS)

    Schneider, Andreas; Rea, Susan; Huq, Ejaz; Bonfield, William

    2003-04-01

    HAPEX is an artificial bone analogue composite based on hydroxyapatite and polyethylene, which can be applied for growth of bone cells. Due to its biocompatibility and favourable mechanical properties, HAPEX is used for orthopaedic implants like tympanic (middle ear) bones. The morphology of HAPEX surfaces is of high interest and it is believed that surface structuring on a micron scale might improve the growth conditions for bone cells. A new and simple approach for the microstructuring of HAPEX surfaces has been investigated using LIGA technique. LIGA is a combination of several processes, in particular lithography, electroplating and forming/moulding. For HAPEX surface structuring, arrays of dots, grids and lines with typical lateral dimension ranging from 5 μm to 50 μm were created on a chromium photomask and the patterns were transferred into thick SU-8 photoresist (structure height > 10 μm) by UV lithography. Subsequently, the SU-8 structures served as moulds for electroplating nickel on Si wafers and nickel substrates. The final nickel microstructures were used as embossing master for the HAPEX material. Embossing was carried out using a conventional press (> 500 hPa) with the facility to heat the master and the HAPEX. The temperature ranged from ambient to a few degrees above glass transition temperature (Tg) of HAPEX. The paper will include details of the fabrication process and process tolerances in lateral and vertical directions. Data obtained are correlated to the temperature used during embossing.

  20. Wafer-scale arrayed p-n junctions based on few-layer epitaxial GaTe

    NASA Astrophysics Data System (ADS)

    Yuan, Xiang; Tang, Lei; Hu, Weida; Xiu, Faxian

    2015-03-01

    Two dimensional (2D) materials have showed appealing applications in electronics and optoelectronics. Gapless graphene presents ultra-broadband and fast photoresponse while the 2D semiconducting MoS2 and GaTe exhibit highly sensitive and tunable responsivity to the visible light. However, the device yield and its repeatability call for a further improvement of 2D materials to render large-scale uniformity. Here we report a layer-by-layer growth of the wafer-scale GaTe by molecular beam epitaxy. To develop the arrayed p-n junctions, the few-layer GaTe was grew on three-inch Si wafers. The resultant diodes reveal good rectifying characteristics and photoresponse with maximum photodetection responsivity of 2.74 A/W and photovoltaic external quantum efficiency up to 62%. The photocurrent reaches saturation very fast within 22 μs and shows no sign of device degradation after 1.37 million cycles of operation. Most strikingly, such high performance has been achieved across the entire wafer, making the volume production of devices accessible. Finally, several photo-images was acquired by using these photodiodes with a reasonable contrast and resolution, demonstrating for the first time the potential for these 2D technology coming into the real life.

  1. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    NASA Astrophysics Data System (ADS)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  2. Wafer-scale fabrication of transistors using CVD-grown graphene and its application to inverter circuit

    NASA Astrophysics Data System (ADS)

    Nakaharai, Shu; Iijima, Tomohiko; Ogawa, Shinichi; Yagi, Katsunori; Harada, Naoki; Hayashi, Kenjiro; Kondo, Daiyu; Takahashi, Makoto; Li, Songlin; Tsukagoshi, Kazuhito; Sato, Shintaro; Yokoyama, Naoki

    2015-04-01

    Graphene transistors were fabricated by a wafer-scale “top-down” process using a graphene sheet formed by the chemical vapor deposition (CVD) method. The devices have a dual-gated structure with an ion-irradiated channel, in which transistor polarity can be electrostatically controlled. We demonstrated, at room temperature, an on/off operation of current and electrostatic control of transistor polarity. By combining two dual-gated transistors, a six-terminal device was fabricated with three top gates and two ion-irradiated channels. In this device, we demonstrated an inverter operation.

  3. Fabrication of a wafer-scale uniform array of single-crystal organic nanowire complementary inverters by nanotransfer printing

    NASA Astrophysics Data System (ADS)

    Park, Kyung Sun; Baek, Jangmi; Koo Lee, Yong-Eun; Sung, Myung Mo

    2015-02-01

    We report the fabrication and electrical characterization of a wafer-scale array of organic complementary inverters using single-crystal 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-PEN) and fullerene (C60) nanowires as p- and n-channels, respectively. Two arrays of single-crystal organic nanowires were generated consecutively on desired locations of a common substrate with a desired mutual alignment by a direct printing method (liquid-bridge-mediated nanotransfer molding). Another direct printing of silver micron scale structures, as source and drain electrodes, on the substrate with the two printed nanowire arrays produced an array of complementary inverters with a bottom gate, top contact configuration. Field-effect mobilities of single-crystal TIPS-PEN and C60 nanowire field-effect transistors (FETs) in the arrays were uniform with 1.01 ± 0.14 and 0.10 ± 0.01 cm2V-1 s-1, respectively. A wafer-scale array of complementary inverters produced all by the direct printing method showed good performance with an average gain of 25 and with low variations among the inverters.

  4. Inspection strategy for LIGA microstructures using a programmable optical microscope.

    SciTech Connect

    Kurfess, Thomas R; Aigeldinger, Georg; Ceremuga, Joseph T.

    2004-07-01

    The LIGA process has the ability to fabricate very precise, high aspect ratio mesoscale structures with microscale features [l]. The process consists of multiple steps before a final part is produced. Materials native to the LIGA process include metals and photoresists. These structures are routinely measured for quality control and process improvement. However, metrology of LIGA structures is challenging because of their high aspect ratio and edge topography. For the scale of LIGA structures, a programmable optical microscope is well suited for lateral (XU) critical dimension measurements. Using grayscale gradient image processing with sub-pixel interpolation, edges are detected and measurements are performed. As with any measurement, understanding measurement uncertainty is necessary so that appropriate conclusions are drawn from the data. Therefore, the abilities of the inspection tool and the obstacles presented by the structures under inspection should be well understood so that precision may be quantified. This report presents an inspection method for LIGA microstructures including a comprehensive assessment of the uncertainty for each inspection scenario.

  5. Fabrication method for chip-scale-vacuum-packages based on a chip-to-wafer-process

    NASA Astrophysics Data System (ADS)

    Bauer, J.; Weiler, D.; Ruß, M.; Heß, J.; Yang, P.; Voß, J.; Arnold, N.,; Vogt, H.

    2010-10-01

    This paper introduces a simple vacuum packaging method which is based on a Chip-to-Wafer process. The MEMS-device is provided with an electroplated solder frame. A Si-lid with the same solder frame is mounted on each die of the wafer using a flip chip process. The same materials for lid and substrate are used in order to reduce the mechanical stress due to the same thermal coefficients of expansion. The resulting cavity between die and lid can be evacuated and hermetically sealed with an eutectic soldering process. The feasibility of the method is demonstrated with an infrared focal plane array (IR-FPA). In this case, the Si-lid acts as an optical window and contains an anti reflective layer for the 8-14 μm wavelength area on both sides. The long-term vacuum stability is supported by a getter film inside the package. This method simplifies the sawing process and has the additional cost benefit that it is possible to package only known good dies.

  6. Stationary Optical Concentrator Designs and Wafer Scale Monolithic Integration of Semiconductor Devices for Next Generation Photovoltaic Panels

    NASA Astrophysics Data System (ADS)

    Kim, Jung Min

    A major barrier in utilizing solar energy for large scale deployment is the cost of the photovoltaic (PV) systems. Several approaches have been used for the cost reduction such as by modifying PV system designs in addition to enhancing the efficiency of solar cells. Due to the high cost of materials, minimizing the use of solar cells such as in concentrator type systems is highly attractive for reducing the cost of the PV modules by focusing the incident light onto the PV cell. However concentrator PV systems (CPV) require constant tracking of the sun and hence are complex in design and expensive to operate, except in limited situations such as large scale PV power plants. It is desirable to design new concentrator type systems that do not require continuous tracking of the sun. These systems could ultimately reduce the PV system cost to a minimum while maximizing the power conversion efficiency. In this thesis we propose a simple design for a stationary concentrator photovoltaic (SCPV) system that could significantly reduce the cost of generating electricity using PV devices. Using optical ray tracing simulations, we have been able to design SCPV systems that could reduce the PV module cost by 2--10 times without compromising on the power conversion efficiency of the system. Another alternative approach for sustainable high efficiency PV system design is to develop low cost PV cells for terrestrial applications. To meet the demands of low cost and large scale production, larger and thinner (or flexible) substrates are required. We demonstrated the feasibility of fabricating monolithic interconnected PV devices at the wafer scale (2 inch wafers). In this study, GaSb PV cells grown on semi-insulating GaAs were used as the model material. Crucial device fabrication steps such as a selective etching process have been developed that is necessary for isolating individual devices on the wafer and interconnecting them with sub-micron scale accuracy. Selective etching of

  7. Wafer-Scale and Wrinkle-Free Epitaxial Growth of Single-Orientated Multilayer Hexagonal Boron Nitride on Sapphire.

    PubMed

    Jang, A-Rang; Hong, Seokmo; Hyun, Chohee; Yoon, Seong In; Kim, Gwangwoo; Jeong, Hu Young; Shin, Tae Joo; Park, Sung O; Wong, Kester; Kwak, Sang Kyu; Park, Noejung; Yu, Kwangnam; Choi, Eunjip; Mishchenko, Artem; Withers, Freddie; Novoselov, Kostya S; Lim, Hyunseob; Shin, Hyeon Suk

    2016-05-11

    Large-scale growth of high-quality hexagonal boron nitride has been a challenge in two-dimensional-material-based electronics. Herein, we present wafer-scale and wrinkle-free epitaxial growth of multilayer hexagonal boron nitride on a sapphire substrate by using high-temperature and low-pressure chemical vapor deposition. Microscopic and spectroscopic investigations and theoretical calculations reveal that synthesized hexagonal boron nitride has a single rotational orientation with AA' stacking order. A facile method for transferring hexagonal boron nitride onto other target substrates was developed, which provides the opportunity for using hexagonal boron nitride as a substrate in practical electronic circuits. A graphene field effect transistor fabricated on our hexagonal boron nitride sheets shows clear quantum oscillation and highly improved carrier mobility because the ultraflatness of the hexagonal boron nitride surface can reduce the substrate-induced degradation of the carrier mobility of two-dimensional materials. PMID:27120101

  8. Wafer scale fabrication of highly dense and uniform array of sub-5 nm nanogaps for surface enhanced Raman scatting substrates.

    PubMed

    Cai, Hongbing; Wu, YuKun; Dai, Yanmeng; Pan, Nan; Tian, Yangchao; Luo, Yi; Wang, Xiaoping

    2016-09-01

    Metallic nanogap is very important for a verity of applications in plasmonics. Although several fabrication techniques have been proposed in the last decades, it is still a challenge to produce uniform nanogaps with a few nanometers gap distance and high throughput. Here we present a simple, yet robust method based on the atomic layer deposition (ALD) and lift-off technique for patterning ultranarrow nanogaps array. The ability to accurately control the thickness of the ALD spacer layer enables us to precisely define the gap size, down to sub-5 nm scale. Moreover, this new method allows to fabricate uniform nanogaps array along different directions densely arranged on the wafer-scale substrate. It is demonstrated that the fabricated array can be used as an excellent substrate for surface enhanced Raman scatting (SERS) measurements of molecules, even on flexible substrates. This uniform nanogaps array would also find its applications for the trace detection and biosensors. PMID:27607684

  9. Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

    NASA Astrophysics Data System (ADS)

    Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

    2014-02-01

    Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

  10. Wafer-scale, conformal and direct growth of MoS2 thin films by atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Jang, Yujin; Yeo, Seungmin; Lee, Han-Bo-Ram; Kim, Hyungjun; Kim, Soo-Hyun

    2016-03-01

    Molybdenum disulfide (MoS2) thin films were grown directly on SiO2 covered wafers by atomic layer deposition (ALD) at the deposition temperatures ranging from 175 to 225 °C using molybdenum hexacarbonyl [Mo(CO)6] and H2S plasma as the precursor and reactant, respectively. Self-limited film growth on the thermally-grown SiO2 substrate was observed with both the precursor and reactant pulsing time. The growth rate was ∼0.05 nm/cycle and a short incubation cycle of around 13 was observed at a deposition temperature of 175 °C. The MoS2 films formed nanocrystalline microstructure with a hexagonal crystal system (2H-MoS2), which was confirmed by X-ray diffraction and transmission electron microscopy. Single crystal MoS2 nanosheets, ∼20 nm in size, were fabricated by controlling the number of ALD cycles. The ALD-MoS2 thin films exhibited good stoichiometry with negligible C impurities, approximately 0.1 at.% from Rutherford backscattering spectrometry (RBS). X-ray photoelectron spectroscopy confirmed the formation of chemical bonding from MoS2. The step coverage of ALD-MoS2 was approximately 75% at a 100 nm sized trench. Overall, the ALD-MoS2 process made uniform deposition possible on the wafer-scale (4 in. in diameter).

  11. Highly Transparent Wafer-Scale Synthesis of Crystalline WS2 Nanoparticle Thin Film for Photodetector and Humidity-Sensing Applications.

    PubMed

    Pawbake, Amit S; Waykar, Ravindra G; Late, Dattatray J; Jadkar, Sandesh R

    2016-02-10

    In the present investigation, we report a one-step synthesis method of wafer-scale highly crystalline tungsten disulfide (WS2) nanoparticle thin film by using a modified hot wire chemical vapor deposition (HW-CVD) technique. The average size of WS2 nanoparticle is found to be 25-40 nm over an entire 4 in. wafer of quartz substrate. The low-angle XRD data of WS2 nanoparticle shows the highly crystalline nature of sample along with orientation (002) direction. Furthermore, Raman spectroscopy shows two prominent phonon vibration modes of E(1)2g and A1g at ∼356 and ∼420 cm(-1), respectively, indicating high purity of material. The TEM analysis shows good crystalline quality of sample. The synthesized WS2 nanoparticle thin film based device shows good response to humidity and good photosensitivity along with good long-term stability of the device. It was found that the resistance of the films decreases with increasing relative humidity (RH). The maximum humidity sensitivity of 469% along with response time of ∼12 s and recovery time of ∼13 s were observed for the WS2 thin film humidity sensor device. In the case of photodetection, the response time of ∼51 s and recovery time of ∼88 s were observed with sensitivity ∼137% under white light illumination. Our results open up several avenues to grow other transition metal dichalcogenide nanoparticle thin film for large-area nanoelectronics as well as industrial applications. PMID:26771049

  12. Wafer-level-scale package of MEMS device by eutectic bonding method

    NASA Astrophysics Data System (ADS)

    Chen, Sihai; Ma, Hong; Chen, Mingxiang; Xiong, Tao; Liu, Sheng; Yi, Xinjian

    2003-12-01

    This paper reports the preliminary results for an on-going program in wafer-level MEMS package. In this particular paper, three closed-loop microheaters of 5μm, 7μm and 9μm width were designed. By reactive ion sputtering technique, two classes of samples were presented. The first one was first co-sputtered with nickel / chromium (Ni/Cr) alloy and then sputtered with gold(Au) metal as heating material; the second one was sputtered with Cr, tin (Sn) and Au respectively as heating material. The bonding of the former sample based on the Ni/Cr and Au heating material failed. The eutectic bonding experiment of the later sample based on the Cr, Sn and Au heating material by global heating method was completed in annealing oven at temperature of about 400 for 20 minutes. The SEM testing result showed the eutectic bonding of Au-Sn by global heating was successful. More results will be reported in future.

  13. Wafer-level scale package of MEMS device by eutectic bonding method

    NASA Astrophysics Data System (ADS)

    Chen, Sihai; Ma, Hong; Chen, Mingxiang; Xiong, Tao; Liu, Sheng; Yi, Xinjian

    2004-01-01

    This paper reports the preliminary results for an on-going program in wafer-level MEMS package. In this particular paper, three closed-loop microheaters of 5μm, 7μm and 9μm width were designed. By reactive ion sputtering technique, two classes of samples were presented. The first one was first co-sputtered with nickel / chromium (Ni/Cr) alloy and then sputtered with gold(Au) metal as heating material; the second one was sputtered with Cr, tin (Sn) and Au respectively as heating material. The bonding of the former sample based on the Ni/Cr and Au heating material failed. The eutectic bonding experiment of the later sample based on the Cr, Sn and Au heating material by global heating method was completed in annealing oven at temperature of about 400 deg. C. for 20 minutes. The SEM testing result showed the eutectic bonding of Au-Sn by global heating was successful. More results will be reported in future.

  14. Wafer-Scale Nanopillars Derived from Block Copolymer Lithography for Surface-Enhanced Raman Spectroscopy.

    PubMed

    Li, Tao; Wu, Kaiyu; Rindzevicius, Tomas; Wang, Zhongli; Schulte, Lars; Schmidt, Michael S; Boisen, Anja; Ndoni, Sokol

    2016-06-22

    We report a novel nanofabrication process via block copolymer lithography using solvent vapor annealing. The nanolithography process is facile and scalable, enabling fabrication of highly ordered periodic patterns over entire wafers as substrates for surface-enhanced Raman spectroscopy (SERS). Direct silicon etching with high aspect ratio templated by the block copolymer mask is realized without any intermediate layer or external precursors. Uniquely, an atomic layer deposition (ALD)-assisted method is introduced to allow reversing of the morphology relative to the initial pattern. As a result, highly ordered silicon nanopillar arrays are fabricated with controlled aspect ratios. After metallization, the resulting nanopillar arrays are suitable for SERS applications. These structures readily exhibit an average SERS enhancement factor of above 10(8), SERS uniformities of 8.5% relative standard deviation across 4 cm, and 6.5% relative standard deviation over 5 × 5 mm(2) surface area, as well as a very low SERS background. The as-prepared SERS substrate, with a good enhancement and large-area uniformity, is promising for practical SERS sensing applications. PMID:27254397

  15. 12-inch-wafer-scale CMOS active-pixel sensor for digital mammography

    NASA Astrophysics Data System (ADS)

    Heo, Sung Kyn; Kosonen, Jari; Hwang, Sung Ha; Kim, Tae Woo; Yun, Seungman; Kim, Ho Kyung

    2011-03-01

    This paper describes the development of an active-pixel sensor (APS) panel, which has a field-of-view of 23.1×17.1 cm and features 70-μm-sized pixels arranged in a 3300×2442 array format, for digital mammographic applications. The APS panel was realized on 12-inch wafers based on the standard complementary metal-oxide-semiconductor (CMOS) technology without physical tiling processes of several small-area sensor arrays. Electrical performance of the developed panel is described in terms of dark current, full-well capacity and leakage current map. For mammographic imaging, the optimized CsI:Tl scintillator is experimentally determined by being combined with the developed panel and analyzing im aging characteristics, such as modulation-transfer function, noise-power spectrum, detective quantum efficiency, image l ag, and contrast-detail analysis by using the CDMAM 3.4 phantom. With these results, we suggest that the developed CMOS-based detector can be used for conventional and advanced digital mammographic applications.

  16. Modeling electrodeposition for LIGA microdevice fabrication

    SciTech Connect

    Griffiths, S.K.; Nilson, R.H.; Bradshaw, R.W.

    1998-02-01

    To better understand and to help optimize the electroforming portion of the LIGA process, we have developed one and two-dimensional numerical models describing electrode-position of metal into high aspect-ratio molds. The one-dimensional model addresses dissociation, diffusion, electromigration, and deposition of multiple ion species. The two-dimensional model is limited to a single species, but includes transport induced by forced flow of electrolyte outside the mold and by buoyancy associated with metal ion depletion within the mold. To guide model development and to validate these models, we have also conducted a series of laboratory experiments using a sulfamate bath to deposit nickel in cylindrical molds having aspect ratios up to twenty-five. The experimental results indicate that current densities well in excess of the diffusion-limited currents may still yield metal deposits of acceptable morphology. However, the numerical models demonstrate that such large ion fluxes cannot be sustained by convection within the mold resulting from flow across the mold top. Instead, calculations suggest that the observed enhancement of transport probably results from natural convection within the molds, and that buoyancy-driven flows may be critical to metal ion transport even in micron-scale features having very large aspect ratios. Taking advantage of this enhanced ion transport may allow order-of-magnitude reductions in electroforming times for LIGA microdevice fabrication. 42 refs., 14 figs., 1 tab.

  17. Wafer-scale single-domain-like graphene by defect-selective atomic layer deposition of hexagonal ZnO

    NASA Astrophysics Data System (ADS)

    Park, Kyung Sun; Kim, Sejoon; Kim, Hongbum; Kwon, Deokhyeon; Koo Lee, Yong-Eun; Min, Sung-Wook; Im, Seongil; Choi, Hyoung Joon; Lim, Seulky; Shin, Hyunjung; Koo, Sang Man; Sung, Myung Mo

    2015-10-01

    Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity.Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also

  18. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

    NASA Astrophysics Data System (ADS)

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-02-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

  19. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

    PubMed Central

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-01-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

  20. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors.

    PubMed

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-01-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8" glass wafer. PMID:26861833

  1. Wafer-scale single-domain-like graphene by defect-selective atomic layer deposition of hexagonal ZnO.

    PubMed

    Park, Kyung Sun; Kim, Sejoon; Kim, Hongbum; Kwon, Deokhyeon; Lee, Yong-Eun Koo; Min, Sung-Wook; Im, Seongil; Choi, Hyoung Joon; Lim, Seulky; Shin, Hyunjung; Koo, Sang Man; Sung, Myung Mo

    2015-11-14

    Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with a hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in the free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field-effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity. PMID:26452020

  2. Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics.

    PubMed

    Heo, Jinseong; Byun, Kyung-Eun; Lee, Jaeho; Chung, Hyun-Jong; Jeon, Sanghun; Park, Seongjun; Hwang, Sungwoo

    2013-01-01

    Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V. PMID:24256403

  3. Fabrication of miniaturized electrostatic deflectors using LIGA

    SciTech Connect

    Jackson, K.H.; Khan-Malek, C.; Muray, L.P.

    1997-04-01

    Miniaturized electron beam columns ({open_quotes}microcolumns{close_quotes}) have been demonstrated to be suitable candidates for scanning electron microscopy (SEM), e-beam lithography and other high resolution, low voltage applications. In the present technology, microcolumns consist of {open_quotes}selectively scaled{close_quotes} micro-sized lenses and apertures, fabricated from silicon membranes with e-beam lithography, reactive ion beam etching and other semiconductor thin-film techniques. These miniaturized electron-optical elements provide significant advantages over conventional optics in performance and ease of fabrication. Since lens aberrations scale roughly with size, it is possible to fabricate simple microcolumns with extremely high brightness sources and electrostatic objective lenses, with resolution and beam current comparable to conventional e-beam columns. Moreover since microcolumns typically operate at low voltages (1 KeV), the proximity effects encountered in e-beam lithography become negligible. For high throughput applications, batch fabrication methods may be used to build large parallel arrays of microcolumns. To date, the best reported performance with a 1 keV cold field emission cathode, is 30 nm resolution at a working distance of 2mm in a 3.5mm column. Fabrication of the microcolumn deflector and stigmator, however, have remained beyond the capabilities of conventional machining operations and semiconductor processing technology. This work examines the LIGA process as a superior alternative to fabrication of the deflectors, especially in terms of degree of miniaturization, dimensional control, placement accuracy, run-out, facet smoothness and choice of suitable materials. LIGA is a combination of deep X-ray lithography, electroplating, and injection molding processes which allow the fabrication of microstructures.

  4. Wafer scale fabrication of carbon nanotube thin film transistors with high yield

    NASA Astrophysics Data System (ADS)

    Tian, Boyuan; Liang, Xuelei; Yan, Qiuping; Zhang, Han; Xia, Jiye; Dong, Guodong; Peng, Lianmao; Xie, Sishen

    2016-07-01

    Carbon nanotube thin film transistors (CNT-TFTs) are promising candidates for future high performance and low cost macro-electronics. However, most of the reported CNT-TFTs are fabricated in small quantities on a relatively small size substrate. The yield of large scale fabrication and the performance uniformity of devices on large size substrates should be improved before the CNT-TFTs reach real products. In this paper, 25 200 devices, with various geometries (channel width and channel length), were fabricated on 4-in. size ridged and flexible substrates. Almost 100% device yield were obtained on a rigid substrate with high out-put current (>8 μA/μm), high on/off current ratio (>105), and high mobility (>30 cm2/V.s). More importantly, uniform performance in 4-in. area was achieved, and the fabrication process can be scaled up. The results give us more confidence for the real application of the CNT-TFT technology in the near future.

  5. Wafer-scale fabrication of nanofluidic arrays and networks using nanoimprint lithography and lithographically patterned nanowire electrodeposition gold nanowire masters.

    PubMed

    Halpern, Aaron R; Donavan, Keith C; Penner, Reginald M; Corn, Robert M

    2012-06-01

    Wafer scale (cm(2)) arrays and networks of nanochannels were created in polydimethylsiloxane (PDMS) from a surface pattern of electrodeposited gold nanowires in a master-replica process and characterized with scanning electron microscopy (SEM), atomic force microscopy (AFM), and fluorescence imaging measurements. Patterns of gold nanowires with cross-sectional dimensions as small as 50 nm in height and 100 nm in width were prepared on silica substrates using the process of lithographically patterned nanowire electrodeposition (LPNE). These nanowire patterns were then employed as masters for the fabrication of inverse replica nanochannels in a special formulation of PDMS. SEM and AFM measurements verified a linear correlation between the widths and heights of the nanowires and nanochannels over a range of 50 to 500 nm. The PDMS replica was then oxygen plasma-bonded to a glass substrate in order to create a linear array of nanofluidic channels (up to 1 mm in length) filled with solutions of either fluorescent dye or 20 nm diameter fluorescent polymer nanoparticles. Nanochannel continuity and a 99% fill success rate was determined from the fluorescence imaging measurements, and the electrophoretic injection of both dye and nanoparticles in the nanochannel arrays was also demonstrated. Employing a double LPNE fabrication method, this master-replica process was also used to create a large two-dimensional network of crossed nanofluidic channels. PMID:22533970

  6. Integration of hexagonal boron nitride with quasi-freestanding epitaxial graphene: toward wafer-scale, high-performance devices.

    PubMed

    Bresnehan, Michael S; Hollander, Matthew J; Wetherington, Maxwell; LaBella, Michael; Trumbull, Kathleen A; Cavalero, Randal; Snyder, David W; Robinson, Joshua A

    2012-06-26

    Hexagonal boron nitride (h-BN) is a promising dielectric material for graphene-based electronic devices. Here we investigate the potential of h-BN gate dielectrics, grown by chemical vapor deposition (CVD), for integration with quasi-freestanding epitaxial graphene (QFEG). We discuss the large scale growth of h-BN on copper foil via a catalytic thermal CVD process and the subsequent transfer of h-BN to a 75 mm QFEG wafer. X-ray photoelectron spectroscopy (XPS) measurements confirm the absence of h-BN/graphitic domains and indicate that the film is chemically stable throughout the transfer process, while Raman spectroscopy indicates a 42% relaxation of compressive stress following removal of the copper substrate and subsequent transfer of h-BN to QFEG. Despite stress-induced wrinkling observed in the films, Hall effect measurements show little degradation (<10%) in carrier mobility for h-BN coated QFEG. Temperature dependent Hall measurements indicate little contribution from remote surface optical phonon scattering and suggest that, compared to HfO(2) based dielectrics, h-BN can be an excellent material for preserving electrical transport properties. Graphene transistors utilizing h-BN gates exhibit peak intrinsic cutoff frequencies >30 GHz (2.4× that of HfO(2)-based devices). PMID:22545808

  7. Wafer-scale fabrication of self-actuated piezoelectric nanoelectromechanical resonators based on lead zirconate titanate (PZT)

    NASA Astrophysics Data System (ADS)

    Dezest, D.; Thomas, O.; Mathieu, F.; Mazenq, L.; Soyer, C.; Costecalde, J.; Remiens, D.; Deü, J. F.; Nicu, L.

    2015-03-01

    In this paper we report an unprecedented level of integration of self-actuated nanoelectromechanical system (NEMS) resonators based on a 150 nm thick lead zirconate titanate (PZT) thin film at the wafer-scale. A top-down approach combining ultraviolet (UV) lithography with other standard planar processing technologies allows us to achieve high-throughput manufacturing. Multilayer stack cantilevers with different geometries have been implemented with measured fundamental resonant frequencies in the megahertz range and Q-factor values ranging from ~130 in air up to ~900 in a vacuum at room temperature. A refined finite element model taking into account the exact configuration of the piezoelectric stack is proposed and demonstrates the importance of considering the dependence of the beam’s cross-section upon the axial coordinate. We extensively investigate both experimentally and theoretically the transduction efficiency of the implemented piezoelectric layer and report for the first time at this integration level a piezoelectric constant of {{d}31}=15  fm V-1. Finally, we discuss the current limitations to achieve piezoelectric detection.

  8. Facile fabrication of wafer-scale MoS2 neat films with enhanced third-order nonlinear optical performance.

    PubMed

    Zhang, Xiaoyan; Zhang, Saifeng; Chang, Chunxia; Feng, Yanyan; Li, Yuanxin; Dong, Ningning; Wang, Kangpeng; Zhang, Long; Blau, Werner J; Wang, Jun

    2015-02-21

    Wafer-scale MoS2 neat films with controllable thicknesses were successfully fabricated by vacuum filtering liquid-exfoliated MoS2 dispersions. The obtained MoS2 filtered thin films were systematically characterized by UV-Vis spectroscopy, Fourier transform infrared spectroscopy (FTIR), Raman spectroscopy, atomic force microscopy (AFM) and scanning electron microscopy (SEM). It was found that the fabricated scalable MoS2 films have a smooth surface and high optical homogeneity verified by AFM and a collimated 532 nm beam, respectively. We investigated the ultrafast nonlinear optical (NLO) properties of the filtered films by an open aperture Z-scan method using 515 and 1030 nm femtosecond laser pulses. Saturable absorption was observed at both 515 and 1030 nm with the figure of merit (FOM) values as ∼3.3 × 10(-12) esu cm and ∼3.4 × 10(-14) esu cm, respectively. The observation of ultrafast NLO performance of the MoS2 filtered films indicates that vacuum filtration is a feasible method for the fabrication of optical thin films, which can be expanded to fabricate other two-dimensional films from the corresponding dispersions. This easy film fabrication technology will greatly enlarge the application of graphene analogues including graphene in photonic devices, especially of MoS2 as a saturable absorber. PMID:25597818

  9. Three-dimensional LIGA structures for use in tagging

    NASA Astrophysics Data System (ADS)

    Cox, Adam G.; Garcia, Ephrahim

    1999-07-01

    Nature provides many examples of organisms capable of attaching themselves to other organisms. Seeds and some parasitic insects, for example, have attachment mechanisms that allow them to remain undetected for long periods of time. Such properties may be useful in military and law enforcement tagging situations, where one desires the discrete placement of an active or passive device on an unwitting host. This paper describes the development of 3D micro-scale burrs, that can readily attach to clothing, and are capable of opening the door to new methods of tracking. With the development of bulk micro-machining techniques such as LIGA and MEMS the ability to develop such a carrier taggent has arisen. 3D micro-scale burrs, made of electrodeposited nickel, have been developed using the LIGA process and have been tested for use as carriers for micro- sensors and emitters both active and passive.

  10. Wafer-scale monodomain films of spontaneously aligned single-walled carbon nanotubes.

    PubMed

    He, Xiaowei; Gao, Weilu; Xie, Lijuan; Li, Bo; Zhang, Qi; Lei, Sidong; Robinson, John M; Hároz, Erik H; Doorn, Stephen K; Wang, Weipeng; Vajtai, Robert; Ajayan, Pulickel M; Adams, W Wade; Hauge, Robert H; Kono, Junichiro

    2016-07-01

    The one-dimensional character of electrons, phonons and excitons in individual single-walled carbon nanotubes leads to extremely anisotropic electronic, thermal and optical properties. However, despite significant efforts to develop ways to produce large-scale architectures of aligned nanotubes, macroscopic manifestations of such properties remain limited. Here, we show that large (>cm(2)) monodomain films of aligned single-walled carbon nanotubes can be prepared using slow vacuum filtration. The produced films are globally aligned within ±1.5° (a nematic order parameter of ∼1) and are highly packed, containing 1 × 10(6) nanotubes in a cross-sectional area of 1 μm(2). The method works for nanotubes synthesized by various methods, and film thickness is controllable from a few nanometres to ∼100 nm. We use the approach to create ideal polarizers in the terahertz frequency range and, by combining the method with recently developed sorting techniques, highly aligned and chirality-enriched nanotube thin-film devices. Semiconductor-enriched devices exhibit polarized light emission and polarization-dependent photocurrent, as well as anisotropic conductivities and transistor action with high on/off ratios. PMID:27043199

  11. Wafer-scale monodomain films of spontaneously aligned single-walled carbon nanotubes

    NASA Astrophysics Data System (ADS)

    He, Xiaowei; Gao, Weilu; Xie, Lijuan; Li, Bo; Zhang, Qi; Lei, Sidong; Robinson, John M.; Hároz, Erik H.; Doorn, Stephen K.; Wang, Weipeng; Vajtai, Robert; Ajayan, Pulickel M.; Adams, W. Wade; Hauge, Robert H.; Kono, Junichiro

    2016-07-01

    The one-dimensional character of electrons, phonons and excitons in individual single-walled carbon nanotubes leads to extremely anisotropic electronic, thermal and optical properties. However, despite significant efforts to develop ways to produce large-scale architectures of aligned nanotubes, macroscopic manifestations of such properties remain limited. Here, we show that large (>cm2) monodomain films of aligned single-walled carbon nanotubes can be prepared using slow vacuum filtration. The produced films are globally aligned within ±1.5° (a nematic order parameter of ∼1) and are highly packed, containing 1 × 106 nanotubes in a cross-sectional area of 1 μm2. The method works for nanotubes synthesized by various methods, and film thickness is controllable from a few nanometres to ∼100 nm. We use the approach to create ideal polarizers in the terahertz frequency range and, by combining the method with recently developed sorting techniques, highly aligned and chirality-enriched nanotube thin-film devices. Semiconductor-enriched devices exhibit polarized light emission and polarization-dependent photocurrent, as well as anisotropic conductivities and transistor action with high on/off ratios.

  12. 200 mm wafer-scale substrate transfer of 0.13 μm Cu/low-k (Black Diamond™) dual-damascene interconnection to glass substrates

    NASA Astrophysics Data System (ADS)

    Teh, W. H.; Kumar, R.; Kwong, D. L.

    2005-07-01

    We report a low-temperature (350 °C) pulsed-voltage anodic bonding followed by grind/etch-back method for 200 mm wafer-scale substrate transfer of 0.13μmCu/low-k (Black Diamond™) dual-damascene interconnection to glass substrates. Standard back-end-of-line (BEOL) 3kÅSiN/3kÅ undoped Si glass passivating films were used as buffer layers between donor wafer and glass wafer to facilitate the bonding. We demonstrate removal of the silicon bulk layer to leave behind a transparent (˜1.25μm thick) 0.13μm BEOL circuit on a 1-mm-thick glass wafer. The quality of the mechanical and electrical integrity of the deep submicron BEOL circuit is confirmed by focused ion beam-scanning electron microscopy microscopy and I-V characterization on via chain test structures. This technique has potential applications for bioelectronics and optoelectronics integration schemes.

  13. Wafer-scale synthesis of thickness-controllable MoS2 films via solution-processing using a dimethylformamide/n-butylamine/2-aminoethanol solvent system

    NASA Astrophysics Data System (ADS)

    Yang, Jaehyun; Gu, Yeahyun; Lee, Eunha; Lee, Hyangsook; Park, Sang Han; Cho, Mann-Ho; Kim, Yong Ho; Kim, Yong-Hoon; Kim, Hyoungsub

    2015-05-01

    The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates.The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the

  14. Slip, Crystal Orientation, and Damage Evolution During Thermal Cycling in High-Strain Wafer-Level Chip-Scale Packages

    NASA Astrophysics Data System (ADS)

    Zhou, Bite; Zhou, Quan; Bieler, Thomas R.; Lee, Tae-kyu

    2015-03-01

    Wafer-level chip-scale package samples with pre-cross-sectioned edge rows were thermally cycled to study microstructure evolution and damage development. Electron backscattered diffraction (EBSD) and high-energy x-ray diffraction were used to obtain Sn grain orientations and the average coefficient of thermal expansion normal to the board in every joint of the package for samples in the as-fabricated and thermally cycled conditions. The results indicated a near-random distribution of joint orientation. Optical, scanning electron microscopy, and EBSD methods were used to characterize microstructure changes in pre-cross-sectioned samples due to thermal cycling. Slip trace analysis and Orientation Imaging Microscopy™ (OIM) show that slip systems with high Schmid factors (estimated global shear stress based on the package neutral point) are responsible for the observed microstructure evolution during thermal cycling, which provides information about slip systems that are more easily activated. Two joints were analyzed in detail to evaluate slip activity at different stages of their thermal history. The first case showed that a solidification twin grain boundary misorientation deviated from the twin relationship due to slip activity during thermal cycling, which can influence damage development and the path of crack propagation. The second case showed a new grain orientation developing due to gradual lattice rotation about the Sn [110] axis by a continuous recrystallization mechanism. This rotation was correlated with the operation of slip system . Small tin whiskers emerged from the initially polished chip interface and grew with increasing thermal cycles until a crack developed in the solder that relieved the stress. As the local stresses are not known experimentally, this analysis provides observations that can be compared with a crystal plasticity model simulation.

  15. Miniature Inchworm Actuators Fabricated by Use of LIGA

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok

    2003-01-01

    Miniature inchworm actuators that would have relatively simple designs have been proposed for applications in which there are requirements for displacements of the order of microns or tens of microns and for the ability to hold their positions when electric power is not applied. The proposed actuators would be members of the class of microelectromechanical systems (MEMS), but would be designed and fabricated following an approach that is somewhat unusual for MEMS. Like other MEMS actuators, the proposed inchworm actuators could utilize thermoplastic, bimetallic, shape-memory-alloy, or piezoelectric actuation principles. The figure depicts a piezoelectric inchworm actuator according to the proposal. As in other inchworm actuators, linear motion of an extensible member would be achieved by lengthening and shortening the extensible member in synchronism with alternately clamping and releasing one and then the other end of the member. In this case, the moving member would be the middle one; the member would be piezoelectric and would be shortened by applying a voltage to it. The two outer members would also be piezoelectric; the release of the clamps on the upper or lower end would be achieved by applying a voltage to the electrodes on the upper or lower ends, respectively, of these members. Usually, MEMS actuators cannot be fabricated directly on the side walls of silicon wafers, yet the geometry of this actuator necessitates such fabrication. The solution, according to the proposal, would be to use the microfabrication technique known by the German acronym LIGA - "lithographie, galvanoformung, abformung," which means lithography, electroforming, molding. LIGA involves x-ray lithography of a polymer film followed by selective removal of material to form a three-dimensional pattern from which a mold is made. Among the advantages of LIGA for this purpose are that it is applicable to a broad range of materials, can be used to implement a variety of designs, including

  16. MUSE - a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer-scale integration. Technical report

    SciTech Connect

    Rader, C.M.; Allen, D.L.; gLASCO , D.B.; Woodward, C.E.

    1990-05-18

    This report describes an architecture for a highly parallel system of computational processors specialized for real-time adaptive antenna nulling computations with many degrees of freedom, which we call MUSE (Matrix Update Systolic Experiment), and a specific realization of MUSE for 64 degrees of freedom. Each processor uses the CORDIC algorithm and has been designed as a single integrated circuit. Ninety-six such processors working together can update the 64-element nulling weights based on 300 new observations in only 6.7 milliseconds. This is equivalent to 2.88 Giga-ops for a conventional processor. The computations are accurate enough to support 50 decibel of signal-to-noise improvement in a sidelobe canceller. The connectivity between processors is quite simple and permits MUSE to be realized on a single large wafer, using restructurable VLSI (Very Large Scale Integration). The complete design of such a wafer is described.

  17. Machining lead wafers

    SciTech Connect

    Schamaun, R.T.

    1987-09-01

    Recently, MEC-6 machined some 4-inch-diameter lead wafers to precision tolerances. The tolerance on the wafer thickness was +-0.000080 inch. A diamond tool was used to machine the wafers on a Moore No. 3 lathe. This report discusses the methods used to machine the wafers, the fixtures used to hold the wafers, and the inspection methods and results.

  18. Imaging ATUM ultrathin section libraries with WaferMapper: a multi-scale approach to EM reconstruction of neural circuits

    PubMed Central

    Hayworth, Kenneth J.; Morgan, Josh L.; Schalek, Richard; Berger, Daniel R.; Hildebrand, David G. C.; Lichtman, Jeff W.

    2014-01-01

    The automated tape-collecting ultramicrotome (ATUM) makes it possible to collect large numbers of ultrathin sections quickly—the equivalent of a petabyte of high resolution images each day. However, even high throughput image acquisition strategies generate images far more slowly (at present ~1 terabyte per day). We therefore developed WaferMapper, a software package that takes a multi-resolution approach to mapping and imaging select regions within a library of ultrathin sections. This automated method selects and directs imaging of corresponding regions within each section of an ultrathin section library (UTSL) that may contain many thousands of sections. Using WaferMapper, it is possible to map thousands of tissue sections at low resolution and target multiple points of interest for high resolution imaging based on anatomical landmarks. The program can also be used to expand previously imaged regions, acquire data under different imaging conditions, or re-image after additional tissue treatments. PMID:25018701

  19. Optimization and scale-down of wafer-based resist strip and rinse processes for photomask production

    NASA Astrophysics Data System (ADS)

    Aggus, Brant L.; Weaver, Gene

    2002-03-01

    Retrofitting of wafer processing equipment is a common scenario in the photomask industry, as most available tools are built to accommodate the high throughput and substrate size of wafers. The acid process tanks in use at most mask shops are built to suit a single rack of 25 8 inch wafers, each coated with roughly two microns of photoresist. Conversely, a typical photomask shop sends one to two masks at a time through the resist strip line, each coated with 4500 angstroms of resist. The amount of unused volume of active chemical within an 8 inch X 8.5 inch X 10 inch acid tank when it is dumped is enough to warrant a hardware change. Experimentation has shown that it is possible to decrease Piranha usage by 43 percent by optimizing tank size for photomasks. The same logic applies to quick dump rinsers (QDRs). Additionally, water is wasted with 'spray down' processes, whereby masks are sprayed via perforated bars or nozzles. Because a < 0.5 μm viscous sublayer can not be practically achieved through spraying the mask, better cleaning performance is obtained with a bottom-filled weiring process. This is demonstrated through experimental results and theoretical mass transfer models.

  20. Laser wafering for silicon solar.

    SciTech Connect

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  1. Wafer-scale pixelated scintillator and specially designed data acquisition system for fiber optic taper array-coupled digital x-ray detector

    NASA Astrophysics Data System (ADS)

    Zhao, Zhigang; Li, Ji; Lei, Yaohu; Wang, Ru; Ren, Jianping; Qiao, Jian; Niu, Hanben

    2015-09-01

    A digital x-ray detector scheme based on a pixelated scintillator coupled with a fiber optic (FOT) array is suitable for many high-resolution x-ray imaging applications. However, certain challenges need to be addressed for fabrication of wafer-scale uniform pixelated x-ray scintillators. In addition, difficulties associated with implementation of the data acquisition system for acquiring output image data from the multiple image sensors used in the detector also need to be addressed. In this paper, a 2×2 FOT array-coupled digital x-ray detector scheme using a 5-in. pixelated scintillator is proposed. A novel fabrication setup along with the corresponding processes for fabricating the wafer-scale pixelated scintillator and implementation of a specially designed embedded data acquisition system based on a single embedded micro-processer (ARM) and four field-programmable gate array (FPGA) chips are discussed in detail. Preliminary experiments demonstrate that this pixelated scintillator-based digital x-ray detector scheme with an active imaging area of about 100 mm×100 mm shows considerable potential for use in high-resolution x-ray imaging.

  2. Large-area, wafer-scale epitaxial growth of germanium on silicon and integration of high-performance transistors

    NASA Astrophysics Data System (ADS)

    Ghosh, Swapnadip

    Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the ˜105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress

  3. Wafer-scale double-layer stacked Au/Al2O3@Au nanosphere structure with tunable nanospacing for surface-enhanced Raman scattering.

    PubMed

    Hu, Zhaosheng; Liu, Zhe; Li, Lin; Quan, Baogang; Li, Yunlong; Li, Junjie; Gu, Changzhi

    2014-10-15

    Fabricating perfect plasmonic nanostructures has been a major challenge in surface enhanced Raman scattering (SERS) research. Here, a double-layer stacked Au/Al2O3@Au nanosphere structures is designed on the silicon wafer to bring high density, high intensity "hot spots" effect. A simply reproducible high-throughput approach is shown to fabricate feasibly this plasmonic nanostructures by rapid thermal annealing (RTA) and atomic layer deposition process (ALD). The double-layer stacked Au nanospheres construct a three-dimensional plasmonic nanostructure with tunable nanospacing and high-density nanojunctions between adjacent Au nanospheres by ultrathin Al2O3 isolation layer, producing highly strong plasmonic coupling so that the electromagnetic near-field is greatly enhanced to obtain a highly uniform increase of SERS with an enhancement factor (EF) of over 10(7). Both heterogeneous nanosphere group (Au/Al2O@Ag) and pyramid-shaped arrays structure substrate can help to increase the SERS signals further, with a EF of nearly 10(9). These wafer-scale, high density homo/hetero-metal-nanosphere arrays with tunable nanojunction between adjacent shell-isolated nanospheres have significant implications for ultrasensitive Raman detection, molecular electronics, and nanophotonics. PMID:24995658

  4. Wafer-scale epitaxial lift-off of optoelectronic grade GaN from a GaN substrate using a sacrificial ZnO interlayer

    NASA Astrophysics Data System (ADS)

    Rajan, Akhil; Rogers, David J.; Ton-That, Cuong; Zhu, Liangchen; Phillips, Matthew R.; Sundaram, Suresh; Gautier, Simon; Moudakir, Tarik; El-Gmili, Youssef; Ougazzaden, Abdallah; Sandana, Vinod E.; Teherani, Ferechteh H.; Bove, Philippe; Prior, Kevin A.; Djebbour, Zakaria; McClintock, Ryan; Razeghi, Manijeh

    2016-08-01

    Full 2 inch GaN epilayers were lifted off GaN and c-sapphire substrates by preferential chemical dissolution of sacrificial ZnO underlayers. Modification of the standard epitaxial lift-off (ELO) process by supporting the wax host with a glass substrate proved key in enabling full wafer scale-up. Scanning electron microscopy and x-ray diffraction confirmed that intact epitaxial GaN had been transferred to the glass host. Depth-resolved cathodoluminescence (CL) analysis of the bottom surface of the lifted-off GaN layer revealed strong near-band-edge (3.33 eV) emission indicating a superior optical quality for the GaN which was lifted off the GaN substrate. This modified ELO approach demonstrates that previous theories proposing that wax host curling was necessary to keep the ELO etch channel open do not apply to the GaN/ZnO system. The unprecedented full wafer transfer of epitaxial GaN to an alternative support by ELO offers the perspective of accelerating industrial adoption of the expensive GaN substrate through cost-reducing recycling.

  5. Understanding and Tailoring the Mechanical Properties of LIGA Fabricated Materials

    SciTech Connect

    Buchheit, T.E.; Christenson, T.R.; Lavan, D.A.; Schmale, D.T.

    1999-01-25

    LIGA fabricated materials and components exhibit several processing issues affecting their metallurgical and mechanical properties, potentially limiting their usefulness for MEMS applications. For example, LIGA processing by metal electrodeposition is very sensitive to deposition conditions which causes significant processing lot variations of mechanical and metallurgical properties. Furthermore, the process produces a material with a highly textured lenticular rnicrostructural morphology suggesting an anisotropic material response. Understanding and controlling out-of-plane anisotropy is desirable for LIGA components designed for out-of-plane flexures. Previous work by the current authors focused on results from a miniature servo-hydraulic mechanical test frame constructed for characterizing LIGA materials. Those results demonstrated microstructural and mechanical properties dependencies with plating bath current density in LIGA fabricated nickel (LIGA Ni). This presentation builds on that work and fosters a methodology for controlling the properties of LIGA fabricated materials through processing. New results include measurement of mechanical properties of LIGA fabricated copper (LIGA Cu), out-of-plane and localized mechanical property measurements using compression testing and nanoindentation of LIGA Ni and LIGA Cu.

  6. Fast and robust hydrogen sensors based on discontinuous palladium films on polyimide, fabricated on a wafer scale.

    PubMed

    Kiefer, T; Villanueva, L G; Fargier, F; Favier, F; Brugger, J

    2010-12-17

    Fast hydrogen sensors based on discontinuous palladium (Pd) films on supporting polyimide layers, fabricated by a cost-efficient and full-wafer compatible process, are presented. The films, deposited by electron-beam evaporation with a nominal thickness of 1.5 nm, consist of isolated Pd islands that are separated by nanoscopic gaps. On hydrogenation, the volume expansion of Pd brings initially separated islands into contact which leads to the creation of new electrical pathways through the film. The supporting polyimide layer provides both sufficient elasticity for the Pd nanoclusters to expand on hydrogenation and a sufficiently high surface energy for good adhesion of both film and contacting electrodes. The novel order of the fabrication processes involves a dicing step prior to the Pd deposition and stencil lithography for the patterning of microelectrodes. This allows us to preserve the as-deposited film properties. The devices work at room temperature, show response times of a few seconds and have a low power consumption of some tens of nW. PMID:21098952

  7. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  8. Cyanoacrylate bonding of thick resists for LIGA

    NASA Astrophysics Data System (ADS)

    Rogers, James G., IV; Marques, Christophe; Kelly, Kevin W.; Sangishetty, Venkat; Khan Malek, Chantal G.

    1996-09-01

    The MicroSystems Engineering Team ((mu) SET) at Louisiana State University, in close collaboration with the Center for Advanced Microstructures and Devices, has successfully completed the lithography and electroplating steps of the LIGA process sequence using cyanoacrylate to bond a PMMA resist layer to a nickel surface. Nickel microstructures 300 micrometers in height have been electroplated. Tests were performed which indicate that the bond between cyanoacrylate and nickel is much stronger than the bond between PMMA and nickel.

  9. LIGA microsystems aging : evaluation and mitigation.

    SciTech Connect

    Cadden, Charles H.; Yang, Nancy Y. C.; San Marchi, Christopher W.

    2003-12-01

    The deployment of LIGA structures in DP applications requires a thorough understanding of potential long term physical and chemical changes that may occur during service. While these components are generally fabricated from simple metallic systems such as copper, nickel and nickel alloys, the electroplating process used to form them creates microstructural features which differ from those found in conventional (e.g. ingot metallurgy) processing of such materials. Physical changes in non-equilibrium microstructures may occur due to long term exposure to temperatures sufficient to permit atomic and vacancy mobility. Chemical changes, particularly at the surfaces of LIGA parts, may occur in the presence of gaseous chemical species (e.g. water vapor, HE off-gassing compounds) and contact with other metallic structures. In this study, we have characterized the baseline microstructure of several nickel-based materials that are used to fabricate LIGA structures. Solute content and distribution was found to have a major effect on the electroplated microstructures. Microstructural features were correlated to measurements of hardness and tensile strength. Dormancy testing was conducted on one of the baseline compositions, nickel-sulfamate. Groups of specimens were exposed to controlled thermal cycles; subsequent examinations compared properties of 'aged' specimens to the baseline conditions. Results of our testing indicate that exposure to ambient temperatures (-54 C to 71 C) do not result in microstructural changes that might be expected to significantly effect mechanical performance. Additionally, no localized changes in surface appearance were found as a result of contact between electroplated parts.

  10. High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth.

    PubMed

    Miao, Xin; Chabak, Kelson; Zhang, Chen; Mohseni, Parsian K; Walker, Dennis; Li, Xiuling

    2015-05-13

    Wafer-scale defect-free planar III-V nanowire (NW) arrays with ∼100% yield and precisely defined positions are realized via a patterned vapor-liquid-solid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 10(4), 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 × 1.5 cm(2) chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics. PMID:25494481

  11. Method to reduce particles and defects on unprocessed wafers caused by clusterization and cross contamination from processed wafers

    NASA Astrophysics Data System (ADS)

    Sant, Sanket

    2012-10-01

    One of the leading problems in the semiconductor industry with device scaling is defects and particles. Of this the most important ones are particles that can clusterize (condensate) with exposure to atmosphere. These clusters can be formed by residual halides or halide structures on the wafer surface reacting with surface moisture which is unavoidable. Such clusters can prove detrimental to the processed wafer, but more interestingly can migrate inside the FOUP onto unetched wafers. This migration of clusters can cause micro masking and other defects when these wafers are processed. This reduces the wafer yield and is challenging to resolve as we move towards smaller nodes. In this work, different methods of eliminating cross condensation defects and avoiding cluster formation on processed wafers are discussed. UV, Ozone and heat are the primary candidates explored and the mechanism behind each method is explored and optimized. Impact of each mechanism on wafer yield, part corrosion in a reactor platform and wafer throughput has been studied.

  12. Wafer-scale monolayer MoS2 grown by chemical vapor deposition using a reaction of MoO3 and H2S.

    PubMed

    Kim, Youngchan; Bark, Hunyoung; Ryu, Gyeong Hee; Lee, Zonghoon; Lee, Changgu

    2016-05-11

    Monolayer MoS2 nanosheets are potentially useful in optoelectronics, photoelectronics, and nanoelectronics due to their flexibility, mechanical strength, and direct band gap of 1.89 eV. Experimentalists have studied the synthesis of MoS2 using chemical vapor deposition (CVD) methods in an effort to fabricate wafer-scale nanofilms with a high uniformity and continuity for practical electronic applications. In this work, we applied the CVD method to a reaction of MoO3 powder and H2S gas to grow high-quality polycrystalline monolayer MoS2 sheets with unprecedented uniformity over an area of several centimeters. The monolayer MoS2 was characterized using Raman spectroscopy, photoluminescence (PL) spectroscopy, atomic force microscopy (AFM), x-ray photoemission spectroscopy (XPS), and transmission electron microscopy (TEM). The top-gate field-effect transistor prepared with a 30 nm HfO2 capping layer displayed an electrical mobility of 1 cm(2) v(-1) s(-1) and an I on/off of ~10(5). This method paves the way for the development of practical devices with MoS2 monolayers and advances fundamental research. PMID:27058779

  13. Wafer-scale monolayer MoS2 grown by chemical vapor deposition using a reaction of MoO3 and H2S

    NASA Astrophysics Data System (ADS)

    Kim, Youngchan; Bark, Hunyoung; Ryu, Gyeong Hee; Lee, Zonghoon; Lee, Changgu

    2016-05-01

    Monolayer MoS2 nanosheets are potentially useful in optoelectronics, photoelectronics, and nanoelectronics due to their flexibility, mechanical strength, and direct band gap of 1.89 eV. Experimentalists have studied the synthesis of MoS2 using chemical vapor deposition (CVD) methods in an effort to fabricate wafer-scale nanofilms with a high uniformity and continuity for practical electronic applications. In this work, we applied the CVD method to a reaction of MoO3 powder and H2S gas to grow high-quality polycrystalline monolayer MoS2 sheets with unprecedented uniformity over an area of several centimeters. The monolayer MoS2 was characterized using Raman spectroscopy, photoluminescence (PL) spectroscopy, atomic force microscopy (AFM), x-ray photoemission spectroscopy (XPS), and transmission electron microscopy (TEM). The top-gate field-effect transistor prepared with a 30 nm HfO2 capping layer displayed an electrical mobility of 1 cm2 v‑1 s‑1 and an I on/off of ~105. This method paves the way for the development of practical devices with MoS2 monolayers and advances fundamental research.

  14. LigaSure Hemorrhoidectomy for Symptomatic Hemorrhoids: First Pediatric Experience.

    PubMed

    Grossmann, Ole; Soccorso, Giampiero; Murthi, Govind

    2015-08-01

    Hemorrhoids are uncommon in children. Third and fourth degree symptomatic hemorrhoids may be surgically excised. We describe the first experience of using LigaSure (Covidien, Mansfield, Massachusetts, United States) to perform hemorrhoidectomies in children. LigaSure hemorrhoidectomy has been well described in adults and is found to be superior in patient tolerance as compared with conventional hemorrhoidectomy. PMID:24918403

  15. Solution structure of leptospiral LigA4 Big domain.

    PubMed

    Mei, Song; Zhang, Jiahai; Zhang, Xuecheng; Tu, Xiaoming

    2015-11-13

    Pathogenic Leptospiraspecies express immunoglobulin-like proteins which serve as adhesins to bind to the extracellular matrices of host cells. Leptospiral immunoglobulin-like protein A (LigA), a surface exposed protein containing tandem repeats of bacterial immunoglobulin-like (Big) domains, has been proved to be involved in the interaction of pathogenic Leptospira with mammalian host. In this study, the solution structure of the fourth Big domain of LigA (LigA4 Big domain) from Leptospira interrogans was solved by nuclear magnetic resonance (NMR). The structure of LigA4 Big domain displays a similar bacterial immunoglobulin-like fold compared with other Big domains, implying some common structural aspects of Big domain family. On the other hand, it displays some structural characteristics significantly different from classic Ig-like domain. Furthermore, Stains-all assay and NMR chemical shift perturbation revealed the Ca(2+) binding property of LigA4 Big domain. PMID:26449456

  16. Final-part metrology for LIGA springs, Build Group 1.

    SciTech Connect

    Aigeldinger, Georg; Skala, Dawn M.; Ceremuga, Joseph T.; Mills, Bernice E.

    2004-03-01

    The LIGA spring is a recently designed part for defense program applications. The Sandia California LIGA team has produced an initial group build of these nickel alloy parts. These are distinctive in having a macroscopic lateral size of about 1 cm, while requiring microscopic dimensional precision on the order of a few micrometers. LIGA technology capabilities at Sandia are able to manufacture such precise structures. While certain aspects of the LIGA process and its production capabilities have been dimensionally characterized in the past, [1-6] the present work is exclusive in defining a set of methods and techniques to inspect and measure final LIGA nickel alloy parts in large prototype quantities. One hundred percent inspection, meaning that every single LIGA part produced needs to be measured, ensures quality control and customer satisfaction in this prototype production run. After a general visual inspection of the parts and an x-ray check for voids, high precision dimensional metrology tools are employed. The acquired data is analyzed using both in house and commercially available software. Examples of measurements illustrating these new metrology capabilities are presented throughout the report. These examples furthermore emphasize that thorough inspection of every final part is not only essential to characterize but also improve the LIGA manufacturing process.

  17. Microstructural Evolution of SAC305 Solder Joints in Wafer Level Chip-Scale Packaging (WLCSP) with Continuous and Interrupted Accelerated Thermal Cycling

    NASA Astrophysics Data System (ADS)

    Zhou, Quan; Zhou, Bite; Lee, Tae-Kyu; Bieler, Thomas

    2016-06-01

    Four high-strain design wafer level chip scale packages were given accelerated thermal cycling with a 10°C/min ramp rate and 10 min hold times between 0°C and 100°C to examine the effects of continuous and interrupted thermal cycling on the number of cycles to failure. The interruptions given two of the samples were the result of periodic examinations using electron backscattered pattern mapping, leading to room temperature aging of 30 days-2.5 years after increments of about 100 cycles at several stages of the cycling history. The continuous thermal cycling resulted in solder joints with a much larger degree of recrystallization, whereas the interrupted thermal cycling tests led to much less recrystallization, which was more localized near the package side, and the crack was more localized near the interface and had less branching. The failure mode for both conditions was still the same, with cracks nucleating along the high angle grain boundaries formed during recrystallization. In conditions where there were few recrystallized grains, recovery led to formation of subgrains that strengthened the solder, and the higher strength led to a larger driving force for crack growth through the solder, leading to failure after less than half of the cycles in the continuous accelerated thermal cycling condition. This work shows that there is a critical point where sufficient strain energy accumulation will trigger recrystallization, but this point depends on the rate of strain accumulation in each cycle and various recovery processes, which further depends on local crystal orientations, stress state evolution, and specific activated slip and twinning systems.

  18. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis

    NASA Astrophysics Data System (ADS)

    Zhao, C.; Konstantinidis, A. C.; Zheng, Y.; Anaxagoras, T.; Speller, R. D.; Kanicki, J.

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm-1 and a DQE of around 0.5 at spatial frequencies  <1 mm-1. In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered.

  19. Microstructural Evolution of SAC305 Solder Joints in Wafer Level Chip-Scale Packaging (WLCSP) with Continuous and Interrupted Accelerated Thermal Cycling

    NASA Astrophysics Data System (ADS)

    Zhou, Quan; Zhou, Bite; Lee, Tae-Kyu; Bieler, Thomas

    2016-02-01

    Four high-strain design wafer level chip scale packages were given accelerated thermal cycling with a 10°C/min ramp rate and 10 min hold times between 0°C and 100°C to examine the effects of continuous and interrupted thermal cycling on the number of cycles to failure. The interruptions given two of the samples were the result of periodic examinations using electron backscattered pattern mapping, leading to room temperature aging of 30 days-2.5 years after increments of about 100 cycles at several stages of the cycling history. The continuous thermal cycling resulted in solder joints with a much larger degree of recrystallization, whereas the interrupted thermal cycling tests led to much less recrystallization, which was more localized near the package side, and the crack was more localized near the interface and had less branching. The failure mode for both conditions was still the same, with cracks nucleating along the high angle grain boundaries formed during recrystallization. In conditions where there were few recrystallized grains, recovery led to formation of subgrains that strengthened the solder, and the higher strength led to a larger driving force for crack growth through the solder, leading to failure after less than half of the cycles in the continuous accelerated thermal cycling condition. This work shows that there is a critical point where sufficient strain energy accumulation will trigger recrystallization, but this point depends on the rate of strain accumulation in each cycle and various recovery processes, which further depends on local crystal orientations, stress state evolution, and specific activated slip and twinning systems.

  20. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    PubMed

    Zhao, C; Konstantinidis, A C; Zheng, Y; Anaxagoras, T; Speller, R D; Kanicki, J

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm(-1) and a DQE of around 0.5 at spatial frequencies  <1 mm(-1). In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered. PMID:26540090

  1. Wafer scale micromachine assembly method

    DOEpatents

    Christenson, Todd R.

    2001-01-01

    A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.

  2. Micro-grippers for assembly of LIGA parts

    SciTech Connect

    Feddema, J.; Polosky, M.; Christenson, T.; Spletzer, B.; Simon, R.

    1997-12-31

    This paper describes ongoing testing of two microgrippers for assembly of LIGA (Lithographie Galvanoformung Abformung) parts. The goal is to place 100 micron outside diameter (OD) LIGA gears with a 50 micron inner diameter hole onto pins ranging from 35 to 49 microns. The first micro gripper is a vacuum gripper made of a 100 micron OD stainless steel tube. The second micro gripper is a set of tweezers fabricated using the LIGA process. Nickel, Permalloy, and copper materials are tested. The tweezers are actuated by a collet mechanism which is closed by a DC linear motor.

  3. Scriber for silicon wafers

    NASA Technical Reports Server (NTRS)

    Yamakawa, K. A.; Fortier, E. P. (Inventor)

    1981-01-01

    A device for dividing silicon wafers into rectangular chips is characterized by a base including a horizontally oriented bed with a planar support surface, a vacuum chuck adapted to capture a silicon wafer seated on the support for translation in mutually perpendicular directions. A stylus support mounted on the bed includes a shaft disposed above and extended across the bed and a truck mounted on the shaft and supported thereby for linear translation along a path extended across the bed a vertically oriented scribe has a diamond tip supported by the truck also adapted as to engage a silicon wafer captured by the chuck and positioned beneath it in order to form score lines in the surface of the wafer as linear translation is imparted to the truck. A chuck positioning means is mounted on the base and is connected to the chuck for positioning the chuck relative to the stylus.

  4. Wafer characteristics via reflectometry

    DOEpatents

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  5. Reciprocating Saw for Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.; Collins, E. R., Jr.

    1985-01-01

    Concept increases productivity and wafer quality. Cutting wafers from silicon ingots produces smooth wafers at high rates with reduced blade wear. Involves straight reciprocating saw blade and slight rotation of ingot between cutting strokes. Many parallel blades combined to cut many wafers simultaneously from ingot.

  6. Cantilevered multilevel LIGA devices and methods

    DOEpatents

    Morales, Alfredo Martin; Domeier, Linda A.

    2002-01-01

    In the formation of multilevel LIGA microstructures, a preformed sheet of photoresist material, such as polymethylmethacrylate (PMMA) is patterned by exposure through a mask to radiation, such as X-rays, and developed using a developer to remove the exposed photoresist material. A first microstructure is then formed by electroplating metal into the areas from which the photoresist has been removed. Additional levels of microstructure are added to the initial microstructure by covering the first microstructure with a conductive polymer, machining the conductive polymer layer to reveal the surface of the first microstructure, sealing the conductive polymer and surface of the first microstructure with a metal layer, and then forming the second level of structure on top of the first level structure. In such a manner, multiple layers of microstructure can be built up to allow complex cantilevered microstructures to be formed.

  7. Miniature Scroll Pumps Fabricated by LIGA

    NASA Technical Reports Server (NTRS)

    Wiberg, Dean; Shcheglov, Kirill; White, Victor; Bae, Sam

    2009-01-01

    Miniature scroll pumps have been proposed as roughing pumps (low - vacuum pumps) for miniature scientific instruments (e.g., portable mass spectrometers and gas analyzers) that depend on vacuum. The larger scroll pumps used as roughing pumps in some older vacuum systems are fabricated by conventional machining. Typically, such an older scroll pump includes (1) an electric motor with an eccentric shaft to generate orbital motion of a scroll and (2) conventional bearings to restrict the orbital motion to a circle. The proposed miniature scroll pumps would differ from the prior, larger ones in both design and fabrication. A miniature scroll pump would include two scrolls: one mounted on a stationary baseplate and one on a flexure stage (see figure). An electromagnetic actuator in the form of two pairs of voice coils in a push-pull configuration would make the flexure stage move in the desired circular orbit. The capacitance between the scrolls would be monitored to provide position (gap) feedback to a control system that would adjust the drive signals applied to the voice coils to maintain the circular orbit as needed for precise sealing of the scrolls. To minimize power consumption and maximize precision of control, the flexure stage would be driven at the frequency of its mechanical resonance. The miniaturization of these pumps would entail both operational and manufacturing tolerances of <1 m. Such tight tolerances cannot be achieved easily by conventional machining of high-aspect-ratio structures like those of scroll-pump components. In addition, the vibrations of conventional motors and ball bearings exceed these tight tolerances by an order of magnitude. Therefore, the proposed pumps would be fabricated by the microfabrication method known by the German acronym LIGA ( lithographie, galvanoformung, abformung, which means lithography, electroforming, molding) because LIGA has been shown to be capable of providing the required tolerances at large aspect ratios.

  8. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  9. Wafer level reliability testing: An idea whose time has come

    NASA Technical Reports Server (NTRS)

    Trapp, O. D.

    1987-01-01

    Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

  10. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  11. Thinning of PLZT ceramic wafers for sensor integration

    NASA Astrophysics Data System (ADS)

    Jin, Na; Liu, Weiguo

    2010-08-01

    Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

  12. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  13. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  14. Within-wafer CD variation induced by wafer shape

    NASA Astrophysics Data System (ADS)

    Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

    2016-03-01

    In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer

  15. Laser-LIGA for Ni microcantilevers

    NASA Astrophysics Data System (ADS)

    Jin, Hengyi; Harvey, Erol C.; Hayes, Jason P.; Ghantasala, Muralidhar K.; Fu, Yao; Jolic, Karlo; Solomon, Matthew; Graves, Kynan

    2002-11-01

    This paper presents our design and experimental results of nickel microcantilevers, which were fabricated using a laser-LIGA process, based on KrF (248 nm) excimer laser micromachining. A chrome-on-quartz mask, containing the desired mask patterns was prepared for this work. The substrate of copper (30 μm thick) clad printed circuit board (PCB) was laminated with Laminar 5038 photopolymer to be laser patterned. Following laser patterning and laser cleaning, all the samples were electroformed with nickel on top of the copper layer. To release the Ni microcantilevers, the excimer laser was employed again to remove the polymer in the localised area to facilitate Cu selective etching. Here, copper acted as the sacrificial layer as well. The Cu selective etching was carried out with ~ 20 % (wt) aqueous solution of ammonium persulfate. Because the Cu selective etching is isotropic, some undercuts happened next to the anchor area. The samples were characterised using optical microscope, confocal laser scanning microscope and SEM, and some of Ni cantilevers were tested electro-thermally. Their performance was analyzed with respect to the simulation results.

  16. Etching Of Semiconductor Wafer Edges

    DOEpatents

    Kardauskas, Michael J.; Piwczyk, Bernhard P.

    2003-12-09

    A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

  17. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  18. Osmolarity, a Key Environmental Signal Controlling Expression of Leptospiral Proteins LigA and LigB and the Extracellular Release of LigA

    PubMed Central

    Matsunaga, James; Sanchez, Yolanda; Xu, Xiaoyi; Haake, David A.

    2005-01-01

    The high-molecular-weight leptospiral immunoglobulin-like repeat (Lig) proteins are expressed only by virulent low-passage forms of pathogenic Leptospira species. We examined the effects of growth phase and environmental signals on the expression, surface exposure, and extracellular release of LigA and LigB. LigA was lost from stationary-phase cells, while LigB expression was maintained. The loss of cell-associated LigA correlated with selective release of a lower-molecular-weight form of LigA into the culture supernatant, while LigB and the outer membrane lipoprotein LipL41 remained associated with cells. Addition of tissue culture medium to leptospiral culture medium induced LigA and LigB expression and caused a substantial increase in released LigA. The sodium chloride component of tissue culture medium was primarily responsible for the enhanced release of LigA. Addition of sodium chloride, potassium chloride, or sodium sulfate to leptospiral medium to physiological osmolarity caused the induction of both cell-associated LigA and LigB, indicating that osmolarity regulates the expression of Lig proteins. Osmotic induction of Lig expression also resulted in enhanced release of LigA and increased surface exposure of LigB, as determined by surface immunofluorescence. Osmolarity appears to be a key environmental signal that controls the expression of LigA and LigB. PMID:15618142

  19. Recent Developments in Microsystems Fabricated by the Liga-Technique

    NASA Technical Reports Server (NTRS)

    Schulz, J.; Bade, K.; El-Kholi, A.; Hein, H.; Mohr, J.

    1995-01-01

    As an example of microsystems fabricated by the LIGA-technique (x-ray lithography, electroplating and molding), three systems are described and characterized: a triaxial acceleration sensor system, a micro-optical switch, and a microsystem for the analysis of pollutants. The fabrication technologies are reviewed with respect to the key components of the three systems: an acceleration sensor, and electrostatic actuator, and a spectrometer made by the LIGA-technique. Aa micro-pump and micro-valve made by using micromachined tools for molding and optical fiber imaging are made possible by combining LIGA and anisotropic etching of silicon in a batch process. These examples show that the combination of technologies and components is the key to complex microsystems. The design of such microsystems will be facilitated is standardized interfaces are available.

  20. Wafer-scale crack-free AlGaN on GaN through two-step selective-area growth for optically pumped stimulated emission

    NASA Astrophysics Data System (ADS)

    Ko, Young-Ho; Bae, Sung-Bum; Kim, Sung-Bock; Kim, Dong Churl; Leem, Young Ahn; Cho, Yong-Hoon; Nam, Eun-Soo

    2016-07-01

    Crack-free AlGaN template has been successfully grown over entire 2-in. wafer by using 2-step selective-area growth (SAG). The GaN truncated structure was obtained by vertical growth mode with low growth temperature. AlGaN of second step was grown under lateral growth mode. Low pressure enhanced the relative ratio of lateral to vertical growth rate as well as absolute overall growth rate. High V/III ratio was favorable for lateral growth mode. Crack-free planar AlGaN was obtained under low pressure of 30 Torr and high V/III ratio of 4400. The AlGaN was crack-free over entire 2-in. wafer and had quite uniform Al-mole fraction. The dislocation density of the AlGaN with 20% Al-composition was as low as ~7.6×108 /cm2, measured by cathodoluminescence. GaN/AlGaN multi-quantum well (MQW) with cladding and waveguide layers were grown on the crack-free AlGaN template with low dislocation density. It was confirmed that the MQW on the AlGaN template emitted the stimulated emission at 355.5 nm through optical pumping experiment. The AlGaN obtained by 2-step SAG would provide high crystal quality for highly-efficient optoelectronic devices as well as the ultraviolet laser diode.

  1. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the

  2. Wafer level warpage characterization of 3D interconnect processing wafers

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2012-03-01

    We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 μm after thinning down to the nominal thickness of 75 μm and 50 μm. The measurement precision is better than 2 um.

  3. Development of a LIGA-based elastodynamic flying mechanism

    NASA Astrophysics Data System (ADS)

    Cox, Adam G.; Garcia, Ephrahim

    1998-07-01

    With the emergence of MEMS and LIGA technology piezoceramics can be integrated to create tiny solid state devices. The precision motion that piezoelectric materials can provide is complimented by the tolerances that can be achieved through MEMS and LIGA micromachining. The integration of these two technologies is ideal for microactuation. A LIGA based devices has been developed that is capable of amplifying small motions from a piezoelectric element into an output stroke angle large enough to produce flight. Micro flight is a difficult aerodynamic problem. With small wing areas conventional lift requires velocities that are difficult to achieve. However it is possible to induce lift using drag in the same manner as some birds and insects. Flapping is a highly efficient way to produce flight. For sustained low energy flight both insects and birds use a complex elastodynamic system that only requires them to excite it at its natural frequency. The actuation device presented is based on the same flight principle of insects and birds, a resonating elastodynamic system excited at its natural frequency or at a lower harmonic. This allows for long distance flights that require little energy. Piezoceramics posses a high energy level and force output that can excite the device and induce a flapping motion. The dynamics of the system rely on the LIGA flexure mechanism, the piezoelectric element, as well as the aerodynamic interaction of the wing and the air which is a complex nonlinear problem.

  4. Wafer-scale controlled exfoliation of metal organic vapor phase epitaxy grown InGaN/GaN multi quantum well structures using low-tack two-dimensional layered h-BN

    NASA Astrophysics Data System (ADS)

    Ayari, Taha; Sundaram, Suresh; Li, Xin; El Gmili, Youssef; Voss, Paul L.; Salvestrini, Jean Paul; Ougazzaden, Abdallah

    2016-04-01

    Recent advances in epitaxial growth have led to the growth of III-nitride devices on 2D layered h-BN. This advance has the potential for wafer-scale transfer to arbitrary substrates, which could improve the thermal management and would allow III-N devices to be used more flexibly in a broader range of applications. We report wafer scale exfoliation of a metal organic vapor phase epitaxy grown InGaN/GaN Multi Quantum Well (MQW) structure from a 5 nm thick h-BN layer that was grown on a 2-inch sapphire substrate. The weak van der Waals bonds between h-BN atomic layers break easily, allowing the MQW structure to be mechanically lifted off from the sapphire substrate using a commercial adhesive tape. This results in the surface roughness of only 1.14 nm on the separated surface. Structural characterizations performed before and after the lift-off confirm the conservation of structural properties after lift-off. Cathodoluminescence at 454 nm was present before lift-off and 458 nm was present after. Electroluminescence near 450 nm from the lifted-off structure has also been observed. These results show that the high crystalline quality ultrathin h-BN serves as an effective sacrificial layer—it maintains performance, while also reducing the GaN buffer thickness and temperature ramps as compared to a conventional two-step growth method. These results support the use of h-BN as a low-tack sacrificial underlying layer for GaN-based device structures and demonstrate the feasibility of large area lift-off and transfer to any template, which is important for industrial scale production.

  5. Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

    PubMed Central

    Thomson, Stephen R. D.; Perron, Justin K.; Kimball, Mark O.; Mehta, Sarabjit; Gasparini, Francis M.

    2014-01-01

    Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale. PMID:24457563

  6. Augmented reality for wafer prober

    NASA Astrophysics Data System (ADS)

    Gilgenkrantz, Pascal

    2011-03-01

    The link between wafer manufacturing and wafer test is often weak: without common information system, Test engineers have to read locations of test structures from reference documents and search them on the wafer prober screen. Mask Data Preparation team is ideally placed to fill this gap, given its relationship with both design and manufacturing sides. With appropriate design extraction scripts and design conventions, mask engineers can provide exact wafer locations of all embedded test structures to avoid a painful camera search. Going a step further, it would be a great help to provide to wafer probers a "map" of what was build on wafers. With this idea in mind, mask design database can simply be provided to Test engineers; but the real added value would come from a true integration of real-wafer camera views and design database used for wafer manufacturing. As proven by several augmented reality applications, like Google Maps' mixed Satellite/Map view, mixing a real-world view with its theoretical model is very useful to understand the reality. The creation of such interface can only be made by a wafer prober manufacturer, given the high integration of these machines with their control panel. But many existing software libraries could be used to plot the design view matching the camera view. Standard formats for mask design are usually GDSII and OASIS (SEMI P39 standard); multiple free software and commercial viewers/editors/libraries for these formats are available.

  7. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  8. Ulnar Impaction Syndrome: Ulnar Shortening vs. Arthroscopic Wafer Procedure

    PubMed Central

    Smet, Luc De; Vandenberghe, Lore; Degreef, Ilse

    2014-01-01

    The outcome of ulnar shortenings was compared with that of arthroscopic wafer resections for ulnar impaction (or abutment) syndrome in patients with a positive ulnar variance. The outcome was measured by DASH score, visual analog scale for pain, and working incapacity. The mean DASH score in the ulnar shortening group was 26; in the wafer group it was 36. The VAS scores were respectively 4.4 and 4.6. The working incapacity was 7?months in the ulnar shortening group and 6.1 months in the wafer group. The differences between the two groups were not statistically significant. PMID:25032075

  9. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  10. W-band LiGA fabricated klystron

    NASA Astrophysics Data System (ADS)

    Song, Liqun

    2002-01-01

    Klystrino-W-band klystron was proposed by scientists at SLAC to satisfy recent applications in advanced accelerators, medical treatment, radars and communications. LiGA (a German acronym for lithographe, galvanoformung, and abformung) is introduced in the fabrication of klystrino for the first time in the history of microwave tube fabrication. The cold test experiments show that LiGA fabrication yields best surface smoothness compared with an alternative way EDM (Electrical Discharge Machining). Resultantly LiGA fabricated klystrino has the smallest wall loss which maximizes the circuit efficiency of the output structure. A multiple-gap coupled cavity is motivated to be employed as the klystrino output cavity for maximizing the efficiency. Klytrino is simulated by 1-D, 2-D and 3-D simulation codes. Particularly a complete klystrino is simulated intensively using 2-D MAGIC Particle-in-Cell (PIC) code either for beam absence or beam presence. Many simulation techniques are developed such as model transformation from 3-D to 2-D, circuit parameter simulation, dispersion characteristic analysis, pre bunched electron beam mode and so on. Klystrino, as a 3-D structure, is modeled by 3-D MAFIA for analyzing the cold circuit properties. 3-D MAGIC is explored to simulate klystrino for the actual structure analysis and actual beam interaction process observation.

  11. In-situ detection method for wafer movement and micro-arc discharge around a wafer in plasma etching process using electrostatic chuck wafer stage with built-in acoustic emission sensor

    NASA Astrophysics Data System (ADS)

    Kasashima, Yuji; Tabaru, Tatsuo; Yasaka, Mitsuo; Kobayashi, Yoshikazu; Akiyama, Morito; Nabeoka, Natsuko; Motomura, Taisei; Sakamoto, Shingo; Uesugi, Fumihiko

    2014-01-01

    We report an electrostatic chuck (ESC) wafer stage with a built-in acoustic emission (AE) sensor for detecting anomalies occurring around a wafer during plasma etching. The built-in AE sensor detects acoustic waves caused by wafer movement and micro-arc discharge with high sensitivity, and identifies these anomalies based on the frequency characteristics of the waves. The results demonstrate the effectiveness of using an ESC wafer stage with a built-in AE sensor for in-situ anomaly detection, which can improve the production yield and overall equipment efficiency in large scale integrated circuit (LSI) manufacturing.

  12. [Thyroidectomy with LigaSure versus traditional thyroidectomy: our experience].

    PubMed

    Marrazzo, Antonio; Casà, Luigi; David, Massimo; Lo Gerfo, Domenico; Noto, Antonio; Riili, Ignazio; Taormina, Pietra

    2007-01-01

    Over the past few decades the surgical strategy for both benign and malignant thyroid diseases has undergone several changes. In particular, total thyroidectomy today has become the routine operation for most thyroid diseases. The complications of this surgical procedure, though of multifactorial aetiopathogenesis, are often related to the efficacy of the haemostasis. Our aim in this study was to verify whether the use of the new LigaSure haemostatic system is capable of reducing the incidence of these complications as well as operative times and length of hospital stay as compared to the conventional haemostatic procedures. Twenty-five patients were randomly assigned to thyroidectomy with LigaSureTM (group A), and 25 to total thyroidectomy using the conventional haemostasis procedures (group B). Of these, 39 were women and 11 men, with a mean age +/- standard deviation of 52.26 +/- 13.57 years. In both groups the thyroidectomy was performed according to the standard total thyroidectomy surgical technique entailing the placement of two aspiration drainages at the end of the operation. As regards the assessment of operative times, these were significantly lower in thyroidectomy with LigaSureTM compared to traditional thyroidectomy (duration: 60 +/- 14.8 min [range: 60-105) in group A versus 92.4 +/- 27.5 min [range: 70-150] in group B, p = 0.02). The total amount of fluid drained postoperatively was substantially similar in the two groups (145 +/- 80 cc in group A versus 140 +/- 64.1 cc in group B). The incidence of postoperative complications was also similar in the two groups. We had only one case of haemorrhage in a patient submitted to thyroidectomy with LigaSureTM, 8 cases of transitory hypocalcaemia, 3 of which in patients with LigaSure thyroidectomy and 5 in patients treated with traditional thyroidectomy (p = 0.42), 2 cases of stupor of the recurrent nerve (1 in group A and 1 in group B) and a single definitive recurrent lesion in a group B patient with

  13. Wafer Replacement Cluster Tool (Presentation);

    SciTech Connect

    Branz, H. M.

    2008-04-01

    This presentation on wafer replacement cluster tool discusses: (1) Platform for advanced R and D toward SAI 2015 cost goal--crystal silicon PV at area costs closer to amorphous Si PV, it's 15% efficiency, inexpensive substrate, and moderate temperature processing (<800 C); (2) Why silicon?--industrial and knowledge base, abundant and environmentally benign, market acceptance, and good efficiency; and (3) Why replace wafers?--expensive, high embedded energy content, and uses 50-100 times more silicon than needed.

  14. Wafer handling and placement tool

    DOEpatents

    Witherspoon, Linda L.

    1988-01-05

    A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

  15. Note: Near infrared interferometric silicon wafer metrology

    NASA Astrophysics Data System (ADS)

    Choi, M. S.; Park, H. M.; Joo, K. N.

    2016-04-01

    In this investigation, two near infrared (NIR) interferometric techniques for silicon wafer metrology are described and verified with experimental results. Based on the transparent characteristic of NIR light to a silicon wafer, the fiber based spectrally resolved interferometry can measure the optical thickness of the wafer and stitching low coherence scanning interferometry can reconstruct entire surfaces of the wafer.

  16. Wafer dicing utilizing unique beam shapes

    NASA Astrophysics Data System (ADS)

    Lizotte, Todd; Ohar, Orest

    2007-09-01

    Laser dicing of wafers is of keen interest to the semiconductor and LED industry. Devices such as ASICs, Ultra-thin Wafer Scale Packages and LEDS are unique in that they typically are formed from various materials in a multilayered structure. Many of these layers include active device materials, passivation coatings, conductors and dielectric films all deposited on top of a bulk wafer substrate and all potentially having differing ablation thresholds. These composite multi-layered structures require high finesse laser processes to ensure yields, cut quality and low process cost. Such processes have become very complex over the years as new devices have become miniaturized, requiring smaller kerf sizes. Of critical concern is the need to minimize substrate micro-cracking or lift off of upper layers along the dicing streets which directly corresponds to bulk device strength and device operational integrity over its projected lifetime. Laser processes involving the sequential use of single or multiple diode pumped solid state (DPSS) lasers, such as UV DPSS (355nn, 266nm, 532 nm), VIS DPSS (~532 nm) and IR DPSS (1064nm, 1070nm) as well as (UV, VIS, NIR, FIR and Eye Safe Wavelengths) DPFL (Diode Pumped Fiber Lasers) lasers to penetrate various and differing material layers and substrates including Silicon Carbide (SiC), Silicon, GaAs and Sapphire. Development of beam shaping optics with the purpose of permitting two or more differing energy densities within a single focused or imaged beam spot would provide opportunities for pre-processing or pre-scribing of thinner cover layers, while following through with a higher energy density segment to cut through the bulk base substrates. This paper will describe the development of beam shaping optical elements with unique beam shapes that could benefit dicing and patterning of delicate thin film coatings. Various designs will be described, with processing examples using LED wafer materials.

  17. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    NASA Astrophysics Data System (ADS)

    Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

    2014-08-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

  18. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    PubMed

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. PMID:25053702

  19. Development of Megasonic cleaning for silicon wafers. Final report

    SciTech Connect

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  20. Wafer sampling by regression for systematic wafer variation detection

    NASA Astrophysics Data System (ADS)

    Moon, Byungsool; McNames, James; Whitefield, Bruce; Rudolph, Paul; Zola, Jeff

    2005-05-01

    In-line measurements are used to monitor semiconductor manufacturing processes for excessive variation using statistical process control (SPC) chart techniques. Systematic spatial wafer variation often occurs in a recognizable pattern across the wafer that is characteristic of a particular manufacturing step. Visualization tools are used to associate these patterns with specific manufacturing steps preceding the measurement. Acquiring the measurements is an expensive and slow process. The number of sites measured on a wafer must be minimized while still providing sufficient data to monitor the process. We address two key challenges to effective wafer-level monitoring. The first challenge is to select a small sample of inspection sites that maximize detection sensitivity to the patterns of interest, while minimizing the confounding effects of other types of wafer variation. The second challenge is to develop a detection algorithm that maximizes sensitivity to the patterns of interest without exceeding a user-specified false positive rate. We propose new sampling and detection methods. Both methods are based on a linear regression model with distinct and orthogonal components. The model is flexible enough to include many types of systematic spatial variation across the wafer. Because the components are orthogonal, the degree of each type of variation can be estimated and detected independently with very few samples. A formal hypothesis test can then be used to determine whether specific patterns are present. This approach enables one to determine the sensitivity of a sample plan to patterns of interest and the minimum number of measurements necessary to adequately monitor the process.

  1. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    DOEpatents

    Bajikar, Sateesh S.; De Carlo, Francesco; Song, Joshua J.

    2001-01-01

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  2. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    SciTech Connect

    Bajikar, Sateesh S.; De Carlo, Francesco; Song, Joshua J.

    2004-01-27

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  3. Selective area growth of InP in shallow trench isolation on large scale Si(001) wafer using defect confinement technique

    NASA Astrophysics Data System (ADS)

    Merckling, C.; Waldron, N.; Jiang, S.; Guo, W.; Richard, O.; Douhard, B.; Moussa, A.; Vanhaeren, D.; Bender, H.; Collaert, N.; Heyns, M.; Thean, A.; Caymax, M.; Vandervorst, W.

    2013-07-01

    Heterogeneous integration of III-V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III-V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III-V virtual substrates on large-scale Si substrates.

  4. Fabrication of Compound Refractive X-ray Lenses Using LIGA Process and Performance Tests

    SciTech Connect

    Lee, Jin Pyoung; Kim, Guk Bae; Kim, Jong Hyun; Chang, Suk Sang; Lee, Sang Joon

    2007-01-19

    Recent advances of X-ray microscopy technology enable the visualization of some micro/nano-scale objects which optical microscopy and electron microscopy cannot be used to observe. The X-ray microscopy can be applied to observe the internal structure of a thicker sample than the electron microscopy can, and its spatial resolution is higher than that of the optical microscopy. Moreover, it has a powerful element specific imaging ability. For further improving the X-ray microscope, it is indispensable to make X-ray optics for focusing X-rays more effectively. Recently, various X-ray lenses such as diffraction lenses of FZP(Fresnel zone plate) and spatter-sliced FZT, total reflection lenses of K-B(Kirkpatrick-Baez) mirror and Wolter mirror, and refractive lens of CRL(compound refractive lens) were introduced. Compared with the other types of lenses, CRL is easy to fabricate and handle. In this study, we designed and fabricated various types of CRLs using LIGA(LIthographie, Galvanoformung, Abformtechnik) process, and used PMMA(Poly(methyl methacrylate)) material as the material of CRL. Their performances are tested with varying parameters such as parabolic/kinoform shape, radius of curvature, wall thickness between adjacent lenses, and width of lenses. The performance tests were carried out by using a simple synchrotron X-ray imaging method. The tests results revealed that hard x-rays could be condensed well by the CRL of PMMA material at the focal point we expect We captured sample images one-dimensionally magnified by CRLs. Furthermore, we found which parameter is more effective for enhancing focus efficiency and which parameter should be considered more carefully in the fabrication process of LIGA.

  5. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R.

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  6. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  7. Nano-particle laser removal from silicon wafers

    NASA Astrophysics Data System (ADS)

    Lee, J. M.; Cho, S. H.; Kim, T. H.; Park, Jin-Goo; Busnaina, Ahmed A.

    2003-11-01

    A laser shock cleaning (LSC) technique as a new dry cleaning methodology has been applied to remove micro and nano-scale inorganic particulate contaminants. Shock wave is generated in the air just above the wafer surface by focusing intensive laser beam. The velocity of shock wave can be controlled to 10,000 m/sec. The sub-micron sized silica and alumina particles are attempted to remove from bare silicon wafer surfaces. More than 95% of removal efficiency of the both particles are carried out by the laser-induced airborne shock waves. In the final, a removal of nano-scale slurry particles from real patterned wafers are successfully demonstrated by LSC after chemical-mechanical polishing (CMP) process.

  8. GEM-type detectors using LIGA and etchable glass technologies

    SciTech Connect

    Ahn, S.K.; Kim, J.G.; Perez-Mendez, V.; Chang, S.; Jackson, K.H.; Kadyk, J.A.; Wenzel, W.A.; Cho, G.

    2001-11-02

    Gas electron multipliers (GEMS) have been made by a deep X-ray lithography technique (LIGA process) using synchrotron radiation on polymethylmethacrylate (PMMA) and by UV processes using a UV etchable glass. Gain, stability and rate capability for these detectors are described.The LIGA detectors described consist of PMMA sheets of various thicknesses, 125mm to 350mm, and have 150mm x 150mm square holes spaced with a pitch of 300mm. Thin copper electrodes are plated on the top and bottom surfaces using a Damascene method, followed by electroless plating of the copper onto a palladium-tin base layer. For various thicknesses of PMMA measurements have been made of absolute gain vs. voltage, time stability of gain, and rate capability. The operating gas mixture was usually Ar/CO2 (70/30) gas, but some tests were also done using P10 gas. We also made GEM-like detectors using the UV etchable glass called Foturan, patterned by exposure to UV light and subsequent etching. A few measurements using these detectors will be reported, including avalanche gain and time stability.

  9. Manufacturing microcomponents for optical information technology using the LIGA technique

    NASA Astrophysics Data System (ADS)

    Bauer, Hans-Dieter; Ehrfeld, Wolfgang; Hossfeld, Jens; Paatzsch, Thomas

    1999-09-01

    Recently, splices and connectors for fibers ribbons, optical cross connects and especially planar waveguide devices have been fabricated via LIGA in combination with precision engineering techniques. LIGA combines high precision and mass production capability, necessary for products designed for applications in the telecom and datacom market. In this presentation the fabrication of three-level molding and embossing tools is presented, which have been used for the manufacturing of waveguide prestructures consisting of waveguide channels and bier-to-waveguide coupling grooves. The precision of the tools is better than 1 micrometers in all directions, which allows for simple passive pigtailing. A first product, a precision of the tool is better than 1 micrometers in all directions, which allows for simple passive pigtailing. A first product, sixfold array of 4 X 4 multimode star couplers has been realized. The molding behavior of PMMA and COC material has been tested and compared. Production and assembly was tested by fabricating a series of 300 star couplers. The average insertion los has been found better than 9dB, the uniformity better than 3dB, both measured at 830nm. THe device is designed for application in optical backplanes for high-speed computers.

  10. Allowable silicon wafer thickness versus diameter for ingot rotation ID wafering

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1982-01-01

    Inner diameter (ID) wafering of ingot rotation reduce the ID saw blade diameter was investigated. The blade thickness can be reduced, resulting in minimal kerf loss. However, significant breakage of wafers occurs during the rotation wafering as the wafer thickness decreases. Fracture mechanics was used to develop an equation relating wafer thickness, diameter and fracture behavior at the point of fracture by using a model of a wafer, supported by a center column and subjected to a cantilever force. It is indicated that the minimum allowable wafer thickness does not increase appreciably with increasing wafer diameter and that fracture through the thickness rather than through the center supporting column limits the minimum allowable wafer thickness. It is suggested that the minimum allowable wafer thickness can be reduced by using a vacuum chuck on the wafer surface to enhance cleavage fracture of the center core and by using 111 ingots.

  11. LIGA-based microsystem manufacturing:the electrochemistry of through-mold depostion and material properties.

    SciTech Connect

    Kelly, James J. (Sandia National Laboratories, Livermore, CA); Goods, Steven Howard (Sandia National Laboratories, Livermore, CA)

    2005-06-01

    The report presented below is to appear in ''Electrochemistry at the Nanoscale'', Patrik Schmuki, Ed. Springer-Verlag, (ca. 2005). The history of the LIGA process, used for fabricating dimensional precise structures for microsystem applications, is briefly reviewed, as are the basic elements of the technology. The principal focus however, is on the unique aspects of the electrochemistry of LIGA through-mask metal deposition and the generation of the fine and uniform microstructures necessary to ensure proper functionality of LIGA components. We draw from both previously published work by external researchers in the field as well as from published and unpublished studies from within Sandia.

  12. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Astrophysics Data System (ADS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-02-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  13. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  14. Fabrication of Spiral Micro-Coil Utilizing LIGA Process

    NASA Astrophysics Data System (ADS)

    Shimada, Osamu; Kusumi, Shinji; Mekaru, Harutaka; Sato, Noriaki; Shimizu, Masami; Yamashita, Michiru; Hattori, Tadashi

    We developed a method for fabricating a three-dimensional spiral micro-inductor with high inductance using the LIGA process. The spiral inductor created had a diameter of 0.5mm, and a length of 1mm. The width of the spiral line was 10µm, the pitch was 20µm, and the number of turns was 15. It was made of plated copper. The master was a brass round bar coated with PMMA resist. Deep X-ray lithography was employed to fabricate a master for a metallic mold at the NewSUBARU synchrotron radiation facility, University of Hyogo. The inductor core was made of resin by injection molding. It has a spiral micro flute on the surface. We chose the worm injection molding technique in order to avoid the parting line across the spiral line. The worm injection molding was the method─for demolding the work such as that used in loosening a screw.

  15. Temperature Dependent Electrical Properties of PZT Wafer

    NASA Astrophysics Data System (ADS)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  16. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  17. Low-loss LIGA-micromachined conductor-backed coplanar waveguide.

    SciTech Connect

    Forman, Michael A.

    2004-12-01

    A mesoscale low-loss LIGA-micromachined conductor-backed coplanar waveguide is presented. The 517 {micro}m lines are the tallest uniplanar LIGA-fabricated microwave transmission lines to date, as well as the first to be constructed of copper rather than nickel. The conductor-backed micromachined CPW on quartz achieves a measured attenuation of 0.064 dB/cm at 15.5 GHz.

  18. Wafer-bonded surface plasmon waveguides

    NASA Astrophysics Data System (ADS)

    Berini, Pierre; Mattiussi, Greg; Lahoud, Nancy; Charbonneau, Robert

    2007-02-01

    Direct wafer bonding and thinning were explored as an approach for constructing long-range surface plasmon waveguides. The structures consist of a thin metal stripe deposited into a shallow trench etched into one of the claddings, to which another cladding of the same material is directly bonded. The approach was developed first using Pyrex wafers in order to assess feasibility and then using lithium niobate wafers. Optical and electro-optical measurements validate the approach.

  19. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  20. Micro cycloid-gear system fabricated by multiexposure LIGA technique

    NASA Astrophysics Data System (ADS)

    Hirata, Toru; Chung, Song-Jo; Hein, Herbert; Akashi, Tomoyuki; Mohr, Juergen

    1999-09-01

    In this paper, a prototype of 2 mm-diameter micro-cycloid gear system fabricated by the multi-exposure LIGA technique is presented. The entire gear system consists of a casing and three vertically stacked disks and gears. Each part is composed of three different levels. The first level, 40 micrometers high, was fabricated by UV-lithography, and the second as well as the third level, 195 micrometers and 250 micrometers high respectively, were processed by aligned deep X-ray lithography (DXL). The alignment error between two DXL- processed layers was measured, and the results have turned out to be within +/- 5 micrometers range. As a result of the height control process by the mechanical surface machining, the deviation of structural height has been maintained within +/- 3 micrometers range for the UV-lithography-processed structures, and +/- 10 micrometers for the DXL-processed structures. Further the tests of gear assembly were implemented with 125 micrometers -diameter glass fiber, by using a die-bonding machine with vacuum gripper under stereo- microscope. Finally the dynamic tests of the gear system were successfully conducted with the mechanical torque input by an electrical motor. A proper rotational speed reduction was observed in the operational input range of 3 to 1500 rpm with the designed gear ratio of 18.

  1. An aluminum resist substrate for microfabrication by LIGA.

    SciTech Connect

    Kelly, James J.; Boehme, Dale R.; Hauck, Cheryl A.; Yang, Chu-Yeu Peter; Hunter, Luke L.; Griffiths, Stewart K.; McLean, Dorrance E.; Aigeldinger, Georg; Hekmaty, Michelle A.; Hachman, John T.; Losey, Matthew W.; Skala, Dawn M.; Korellis, John S.; Friedmann, Thomas Aquinas; Yang, Nancy Y. C.; Lu, Wei-Yang

    2005-04-01

    Resist substrates used in the LIGA process must provide high initial bond strength between the substrate and resist, little degradation of the bond strength during x-ray exposure, acceptable undercut rates during development, and a surface enabling good electrodeposition of metals. Additionally, they should produce little fluorescence radiation and give small secondary doses in bright regions of the resist at the substrate interface. To develop a new substrate satisfying all these requirements, we have investigated secondary resist doses due to electrons and fluorescence, resist adhesion before exposure, loss of fine features during extended development, and the nucleation and adhesion of electrodeposits for various substrate materials. The result of these studies is a new anodized aluminum substrate and accompanying methods for resist bonding and electrodeposition. We demonstrate successful use of this substrate through all process steps and establish its capabilities via the fabrication of isolated resist features down to 6 {micro}m, feature aspect ratios up to 280 and electroformed nickel structures at heights of 190 to 1400 {micro}m. The minimum mask absorber thickness required for this new substrate ranges from 7 to 15 {micro}m depending on the resist thickness.

  2. Stress Voiding During Wafer Processing

    SciTech Connect

    Yost, F.G.

    1999-03-01

    Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

  3. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    SciTech Connect

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  4. Wafer level reliability for high-performance VLSI design

    NASA Technical Reports Server (NTRS)

    Root, Bryan J.; Seefeldt, James D.

    1987-01-01

    As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

  5. Methane production using resin-wafer electrodeionization

    DOEpatents

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  6. Formation and combustion characteristics of elephantgrass and energycane wafers

    NASA Astrophysics Data System (ADS)

    Mofleh, Mohamad I.

    Elephantgrass (Pennisetum purpureum Schum.) and energycane (Saccharum Spp.) are two cane type grasses. These are tall-growing perennial bunchgrasses that produce long hardened stems and grow in the tropics and subtropics. Traditionally, they have been used for forage and, in some regions, have been randomly burned on fields or disposed of uselessly. However, these plants have high dry matter yield and, thus, are excellent candidates as energy crops. Elephantgrass and energycane have been used for direct combustion in their loose form in large-scale applications. Several problems, many of which were attributed to their low bulk density, were encountered with using the materials. Consequently, this project was initiated to investigate the formation and combustion characteristics of the two materials in the form of small compact units called wafers. A hydraulic press that applied axial stresses on the material in four different dies was used. A load cell and a displacement transducer were utilized to measure the stresses and material detection. Wafer quality was evaluated using a tumbler built according to the American Society of Agricultural Engineers standards. In addition, a small stove was built to test wafer combustion. Thermocouples were used to measure temperatures during combustion. All the data gathered was transferred to a computer using a data acquisition system. It was found that the stress-deformation and stress-density relationships of elephantgrass and energycane were of exponential nature. Compaction energy required, which was calculated from the area under the force-deformation curves, ranged from 0.1 to 0.3% of their energy content. It was also found that wafer quality (durability) was mainly a function of wafer size and its final (relaxed) density in addition to material stem-to-leaf ratio and its crude protein content. Wafers possessed poor ignition quality but once ignited, they burned satisfactorily. The results indicated that sufficient and

  7. A model for reaction-assisted polymer dissolution in LIGA.

    SciTech Connect

    Larson, Richard S.

    2004-05-01

    A new chemically-oriented mathematical model for the development step of the LIGA process is presented. The key assumption is that the developer can react with the polymeric resist material in order to increase the solubility of the latter, thereby partially overcoming the need to reduce the polymer size. The ease with which this reaction takes place is assumed to be determined by the number of side chain scissions that occur during the x-ray exposure phase of the process. The dynamics of the dissolution process are simulated by solving the reaction-diffusion equations for this three-component, two-phase system, the three species being the unreacted and reacted polymers and the solvent. The mass fluxes are described by the multicomponent diffusion (Stefan-Maxwell) equations, and the chemical potentials are assumed to be given by the Flory-Huggins theory. Sample calculations are used to determine the dependence of the dissolution rate on key system parameters such as the reaction rate constant, polymer size, solid-phase diffusivity, and Flory-Huggins interaction parameters. A simple photochemistry model is used to relate the reaction rate constant and the polymer size to the absorbed x-ray dose. The resulting formula for the dissolution rate as a function of dose and temperature is ?t to an extensive experimental data base in order to evaluate a set of unknown global parameters. The results suggest that reaction-assisted dissolution is very important at low doses and low temperatures, the solubility of the unreacted polymer being too small for it to be dissolved at an appreciable rate. However, at high doses or at higher temperatures, the solubility is such that the reaction is no longer needed, and dissolution can take place via the conventional route. These results provide an explanation for the observed dependences of both the dissolution rate and its activation energy on the absorbed dose.

  8. A MEMS-Based Micro Biopsy Actuator for the Capsular Endoscope Using LiGA Process

    NASA Astrophysics Data System (ADS)

    Park, Sunkil; Koo, Kyo-In; Kim, Gil-Sub; Bang, Seoung Min; Song, Si Young; Chu, Chong Nam; Jeon, Doyoung; Cho, Dongil ``Dan''

    2007-01-01

    This paper presents a LiGA (German acronym for LIthografie, Galvanoformung, Abformung) based micro biopsy actuator for the capsular endoscope. The proposed fabricated actuator aims to extract sample tissues inside small gastric intestines, that cannot be reached by conventional biopsy. The actuator size is 10 mm in diameter and 1.8 mm in length. The mechanism is of a slider-crank type. The actuator consists of trigger, rotational module, and micro biopsy tool. The core components are fabricated using the LiGA process, for overcoming the limitations in accuracy of conventional precision machining.

  9. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  10. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  11. Local indicators of geocoding accuracy (LIGA): theory and application

    PubMed Central

    Jacquez, Geoffrey M; Rommel, Robert

    2009-01-01

    Background Although sources of positional error in geographic locations (e.g. geocoding error) used for describing and modeling spatial patterns are widely acknowledged, research on how such error impacts the statistical results has been limited. In this paper we explore techniques for quantifying the perturbability of spatial weights to different specifications of positional error. Results We find that a family of curves describes the relationship between perturbability and positional error, and use these curves to evaluate sensitivity of alternative spatial weight specifications to positional error both globally (when all locations are considered simultaneously) and locally (to identify those locations that would benefit most from increased geocoding accuracy). We evaluate the approach in simulation studies, and demonstrate it using a case-control study of bladder cancer in south-eastern Michigan. Conclusion Three results are significant. First, the shape of the probability distributions of positional error (e.g. circular, elliptical, cross) has little impact on the perturbability of spatial weights, which instead depends on the mean positional error. Second, our methodology allows researchers to evaluate the sensitivity of spatial statistics to positional accuracy for specific geographies. This has substantial practical implications since it makes possible routine sensitivity analysis of spatial statistics to positional error arising in geocoded street addresses, global positioning systems, LIDAR and other geographic data. Third, those locations with high perturbability (most sensitive to positional error) and high leverage (that contribute the most to the spatial weight being considered) will benefit the most from increased positional accuracy. These are rapidly identified using a new visualization tool we call the LIGA scatterplot. Herein lies a paradox for spatial analysis: For a given level of positional error increasing sample density to more accurately

  12. Yield-driven multi-project reticle design and wafer dicing

    NASA Astrophysics Data System (ADS)

    Kahng, Andrew B.; Mandoiu, Ion; Xu, Xu; Zelikovsky, Alex

    2005-11-01

    The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies has lead to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such low volume designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle design and wafer dicing introduce complexities not encountered in typical, single-project wafers. Recent works on wafer dicing adopt some assumptions to reduce the problem complexity. Although using one or more assumptions makes the problem solvable, the feasibility or performance of the solutions may be degraded. Also, the delay cost associated with schedule alignment was ignored in all previous works. In this paper we propose a general MPW flow including four main steps: (1) schedule-aware project partitioning (2) multi-project reticle floorplanning, (3) wafer shot-map definition, and (4) wafer dicing plan definition. Our project partitioner provides the best trade-off between the mask cost and delay cost. Our reticle floorplaner can automatically clone a design to better fit given production volumes. The round wafer shot-map definition step allows extracting functional dies from partially printed reticle images. Finally, our dicing planner allows multiple side-to-side dicing plans for different wafers and image rows/columns within a wafer. Experiments on industry testcases show that our methods outperform significantly not only previous methods in the literature, but also reticle floorplans manually designed by experienced engineers.

  13. Adhesive wafer bonding using a molded thick benzocyclobutene layer for wafer-level integration of MEMS and LSI

    NASA Astrophysics Data System (ADS)

    Makihata, M.; Tanaka, S.; Muroyama, M.; Matsuzaki, S.; Yamada, H.; Nakayama, T.; Yamaguchi, U.; Mima, K.; Nonomura, Y.; Fujiyoshi, M.; Esashi, M.

    2011-08-01

    This paper describes a wafer bonding process using a 50 µm thick benzocyclobutene (BCB) layer which has vias and metal electrodes. The vias were fabricated by molding BCB using a glass mold. During the molding, worm-like voids grew between BCB and the mold due to the shrinkage of polymerizing BCB. They were completely removed by subsequent reflowing in N2. After patterning Al on the reflowed BCB for the electrodes and via connections, bonding with a glass substrate was performed. Voidless bonding without damage in the vias and electrodes was achieved. Through the process, the control of the polymerization degree of BCB is important, and thus the polymerization degree was evaluated by Fourier transform infrared spectroscopy. The developed process is useful for the wafer-bonding-based integration of different devices, e.g. micro electro mechanical systems and large-scale integrated circuits.

  14. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Rhee, S. S.

    1979-01-01

    Several aspects of silicon wafer surface texturizing were studied. A low cost cleaning method that utilizes recycled Freon in an ultrasonic vapor degreaser to remove organic and inorganic contaminants from the surface of silicon wafers as received from silicon suppliers was investigated. The use of clean dry air and high throughout wafer batch drying techniques was shown to lower the cost of wafer drying. A two stage texturizing process was examined for suitability in large scale production. Also, an in-depth gettering study with the two stage texturizing process was performed for the enhancement of solar cell efficiency, minimization of current versus voltage curve dispersion, and improvement in process reproducibility. The 10% efficiency improvement goal was exceeded for the near term implementation of flat plate photovoltaic cost reduction.

  15. Harmonic versus LigaSure hemostasis technique in thyroid surgery: A meta-analysis

    PubMed Central

    Upadhyaya, Arun; Hu, Tianpeng; Meng, Zhaowei; Li, Xue; He, Xianghui; Tian, Weijun; Jia, Qiang; Tan, Jian

    2016-01-01

    Harmonic scalpel and LigaSure vessel sealing systems have been suggested as options for saving surgical time and reducing postoperative complications. The aim of the present meta-analysis was to compare surgical time, postoperative complications and other parameters between them in for the open thyroidectomy procedure. Studies were retrieved from MEDLINE, Cochrane Library, EMBASE and ISI Web of Science until December 2015. All the randomized controlled trials (RCTs) comparing Harmonic scalpel and LigaSure during open thyroidectomy were selected. Following data extraction, statistical analyses were performed. Among the 24 studies that were evaluated for eligibility, 7 RCTs with 981 patients were included. The Harmonic scalpel significantly reduced surgical time compared with LigaSure techniques (8.79 min; 95% confidence interval, −15.91 to −1.67; P=0.02). However, no significant difference was observed for the intraoperative blood loss, postoperative blood loss, duration of hospital stay, thyroid weight and serum calcium level postoperatively in either group. The present meta-analysis indicated superiority of Harmonic Scalpel only in terms of surgical time compared with LigaSure hemostasis techniques in open thyroid surgery. PMID:27446546

  16. Adhesive wafer bonding for MEMS applications

    NASA Astrophysics Data System (ADS)

    Dragoi, Viorel; Glinsner, Thomas; Mittendorfer, Gerald; Wieder, Bernhard; Lindner, Paul

    2003-04-01

    Low temperature wafer bonding is a powerful technique for MEMS/MOEMS devices fabrication and packaging. Among the low temperature processes adhesive bonding focuses a high technological interest. Adhesive wafer bonding is a bonding approach using an intermediate layer for bonding (e.g. glass, polymers, resists, polyimides). The main advantages of this method are: surface planarization, encapsulation of structures on the wafer surface, particle compensation and decrease of annealing temperature after bonding. This paper presents results on adhesive bonding using spin-on glass and Benzocyclobutene (BCB) from Dow Chemicals. The advantages of using adhesive bonding for MEMS applications will be illustrated be presenting a technology of fabricating GaAs-on-Si substrates (up to 150 mm diameter) and results on BCB bonding of Si wafers (200 mm diameter).

  17. Modelling deformation and fracture in confectionery wafers

    SciTech Connect

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  18. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  19. Total x-ray power measurements in the Sandia LIGA program.

    SciTech Connect

    Malinowski, Michael E. (Sandia National Laboratories, Livermore, CA); Ting, Aili (Sandia National Laboratories, Livermore, CA)

    2005-08-01

    Total X-ray power measurements using aluminum block calorimetry and other techniques were made at LIGA X-ray scanner synchrotron beamlines located at both the Advanced Light Source (ALS) and the Advanced Photon Source (APS). This block calorimetry work was initially performed on the LIGA beamline 3.3.1 of the ALS to provide experimental checks of predictions of the LEX-D (LIGA Exposure- Development) code for LIGA X-ray exposures, version 7.56, the version of the code in use at the time calorimetry was done. These experiments showed that it was necessary to use bend magnet field strengths and electron storage ring energies different from the default values originally in the code in order to obtain good agreement between experiment and theory. The results indicated that agreement between LEX-D predictions and experiment could be as good as 5% only if (1) more accurate values of the ring energies, (2) local values of the magnet field at the beamline source point, and (3) the NIST database for X-ray/materials interactions were used as code inputs. These local magnetic field value and accurate ring energies, together with NIST database, are now defaults in the newest release of LEX-D, version 7.61. Three dimensional simulations of the temperature distributions in the aluminum calorimeter block for a typical ALS power measurement were made with the ABAQUS code and found to be in good agreement with the experimental temperature data. As an application of the block calorimetry technique, the X-ray power exiting the mirror in place at a LIGA scanner located at the APS beamline 10 BM was measured with a calorimeter similar to the one used at the ALS. The overall results at the APS demonstrated the utility of calorimetry in helping to characterize the total X-ray power in LIGA beamlines. In addition to the block calorimetry work at the ALS and APS, a preliminary comparison of the use of heat flux sensors, photodiodes and modified beam calorimeters as total X-ray power

  20. Temperature Sensitivity Conferred by ligA Alleles from Psychrophilic Bacteria upon Substitution in Mesophilic Bacteria and a Yeast Species

    PubMed Central

    Pankowski, Jarosław A.; Puckett, Stephanie M.

    2016-01-01

    We have assembled a collection of 13 psychrophilic ligA alleles that can serve as genetic elements for engineering mesophiles to a temperature-sensitive (TS) phenotype. When these ligA alleles were substituted into Francisella novicida, they conferred a TS phenotype with restrictive temperatures between 33 and 39°C. When the F. novicida ligA hybrid strains were plated above their restrictive temperatures, eight of them generated temperature-resistant variants. For two alleles, the mutations that led to temperature resistance clustered near the 5′ end of the gene, and the mutations increased the predicted strength of the ribosome binding site at least 3-fold. Four F. novicida ligA hybrid strains generated no temperature-resistant variants at a detectable level. These results suggest that multiple mutations are needed to create temperature-resistant variants of these ligA gene products. One ligA allele was isolated from a Colwellia species that has a maximal growth temperature of 12°C, and this allele supported growth of F. novicida only as a hybrid between the psychrophilic and the F. novicida ligA genes. However, the full psychrophilic gene alone supported the growth of Salmonella enterica, imparting a restrictive temperature of 27°C. We also tested two ligA alleles from two Pseudoalteromonas strains for their ability to support the viability of a Saccharomyces cerevisiae strain that lacked its essential gene, CDC9, encoding an ATP-dependent DNA ligase. In both cases, the psychrophilic bacterial alleles supported yeast viability and their expression generated TS phenotypes. This collection of ligA alleles should be useful in engineering bacteria, and possibly eukaryotic microbes, to predictable TS phenotypes. PMID:26773080

  1. Temperature Sensitivity Conferred by ligA Alleles from Psychrophilic Bacteria upon Substitution in Mesophilic Bacteria and a Yeast Species.

    PubMed

    Pankowski, Jarosław A; Puckett, Stephanie M; Nano, Francis E

    2016-01-01

    We have assembled a collection of 13 psychrophilic ligA alleles that can serve as genetic elements for engineering mesophiles to a temperature-sensitive (TS) phenotype. When these ligA alleles were substituted into Francisella novicida, they conferred a TS phenotype with restrictive temperatures between 33 and 39°C. When the F. novicida ligA hybrid strains were plated above their restrictive temperatures, eight of them generated temperature-resistant variants. For two alleles, the mutations that led to temperature resistance clustered near the 5' end of the gene, and the mutations increased the predicted strength of the ribosome binding site at least 3-fold. Four F. novicida ligA hybrid strains generated no temperature-resistant variants at a detectable level. These results suggest that multiple mutations are needed to create temperature-resistant variants of these ligA gene products. One ligA allele was isolated from a Colwellia species that has a maximal growth temperature of 12°C, and this allele supported growth of F. novicida only as a hybrid between the psychrophilic and the F. novicida ligA genes. However, the full psychrophilic gene alone supported the growth of Salmonella enterica, imparting a restrictive temperature of 27°C. We also tested two ligA alleles from two Pseudoalteromonas strains for their ability to support the viability of a Saccharomyces cerevisiae strain that lacked its essential gene, CDC9, encoding an ATP-dependent DNA ligase. In both cases, the psychrophilic bacterial alleles supported yeast viability and their expression generated TS phenotypes. This collection of ligA alleles should be useful in engineering bacteria, and possibly eukaryotic microbes, to predictable TS phenotypes. PMID:26773080

  2. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  3. Analyzes Data from Semiconductor Wafers

    Energy Science and Technology Software Center (ESTSC)

    2002-07-23

    This program analyzes reflectance data from semiconductor wafers taken during the deposition or evolution of a thin film, typically via chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). It is used to determine the growth rate and optical constants of the deposited thin films using a virtual interface concept. Growth rates and optical constants of multiple-layer structures is possible by selecting appropriate sections in the reflectance vs time waveform. No prior information or estimatesmore » of growth rates and materials properties is required if an absolute reflectance waveform is used. If the optical constants of a thin film are known, then the growth rate may be extracted from a relative reflectance data set. The analysis is valid for either s or p polarized light at any incidence angle and wavelength. The analysis package is contained within an easy-to-use graphical user interface. The program is based on the algorighm described in the following two publications: W.G. Breiland and K.P. Killen, J. Appl. Phys. 78 (1995) 6726, and W. G. Breiland, H.Q. Hou, B.E. Hammons, and J.F. Klem, Proc. XXVIII SOTAPOCS Symp. Electrochem. Soc. San Diego, May 3-8, 1998. It relies on the fact that any multiple-layer system has a reflectance spectrum that is mathematically equivalent to a single-layer thin film on a virtual substrate. The program fits the thin film reflectance with five adjustable parameters: 1) growth rate, 2) real part of complex refractive index, 3) imaginary part of refractive index, 4) amplitude of virtual interface reflectance, 5) phase of virtual interface reflectance.« less

  4. Process Control By Automated In-Process Wafer Inspection

    NASA Astrophysics Data System (ADS)

    Harris, K. L.; Sandland, P.; Singleton, R. M.

    1984-06-01

    This is the introduction of new technology developed specifically for the inprocess pattern inspection and measurement of very large scale integrated (VLSI) wafers. There is a current need for significant improvements in pattern inspection instrumentation in order to tighten process control and achieve more competitive yields and therefore die costs. For the tedious and detailed task of pattern inspection and measurement, automation is the indicated solution. The future of computerized manufacturing requires, most fundamentally, the automation of the instrumentation and control function. In this paper, a system, designated the KLA 2020 Wafer Inspector, is described which incorporates the basic functions required to measure variations in the patterning process: linear and area dimensional measurements, registration error measurement, comparison for defects down to submicron in size. It is capable of inspecting in-process wafers in order to gain the most immediate process feedback. The speed with which it does each of these tests, less than a second, allows significant increases in sample size and therefore statistical control. It is this technology which will make computer-controlled photo processing possible.

  5. The Imaging Properties of a Silicon Wafer X-Ray Telescope

    NASA Technical Reports Server (NTRS)

    Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

    1994-01-01

    Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

  6. Porous solid ion exchange wafer for immobilizing biomolecules

    DOEpatents

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  7. Improvement of focus accuracy on processed wafer

    NASA Astrophysics Data System (ADS)

    Higashibata, Satomi; Komine, Nobuhiro; Fukuhara, Kazuya; Koike, Takashi; Kato, Yoshimitsu; Hashimoto, Kohji

    2013-04-01

    As feature size shrinkage in semiconductor device progress, process fluctuation, especially focus strongly affects device performance. Because focus control is an ongoing challenge in optical lithography, various studies have sought for improving focus monitoring and control. Focus errors are due to wafers, exposure tools, reticles, QCs, and so on. Few studies are performed to minimize the measurement errors of auto focus (AF) sensors of exposure tool, especially when processed wafers are exposed. With current focus measurement techniques, the phase shift grating (PSG) focus monitor 1) has been already proposed and its basic principle is that the intensity of the diffraction light of the mask pattern is made asymmetric by arranging a π/2 phase shift area on a reticle. The resist pattern exposed at the defocus position is shifted on the wafer and shifted pattern can be easily measured using an overlay inspection tool. However, it is difficult to measure shifted pattern for the pattern on the processed wafer because of interruptions caused by other patterns in the underlayer. In this paper, we therefore propose "SEM-PSG" technique, where the shift of the PSG resist mark is measured by employing critical dimension-scanning electron microscope (CD-SEM) to measure the focus error on the processed wafer. First, we evaluate the accuracy of SEM-PSG technique. Second, by applying the SEM-PSG technique and feeding the results back to the exposure, we evaluate the focus accuracy on processed wafers. By applying SEM-PSG feedback, the focus accuracy on the processed wafer was improved from 40 to 29 nm in 3σ.

  8. Design and simulation of non-resonant 1-DOF drive mode and anchored 2-DOF sense mode gyroscope for implementation using UV-LIGA process

    NASA Astrophysics Data System (ADS)

    Verma, Payal; Gopal, Ram; Butt, M. A.; Khonina, Svetlana N.; Skidanov, Roman V.

    2016-03-01

    This paper presents the design and simulation of a 3-DOF (degree-of-freedom) MEMS gyroscope structure with 1-DOF drive mode and anchored 2-DOF sense mode, based on UV-LIGA technology. The 3-DOF system has the drive resonance located in the flat zone between the two sense resonances. It is an inherently robust structure and offers a high sense frequency band width and high gain without much scaling down the mass on which the sensing comb fingers are attached and it is also immune to process imperfections and environmental conditions. The design is optimized to be compatible with the UV-LIGA process, having 9 μm thick nickel as structural layer. The electrostatic gap between the drive comb fingers is 4 μm and sense comb fingers gap are 4 μm/12 μm. The damping effect is considered by assuming the flexures and the proof mass suspended about 6 μm over the substrate. Accordingly, mask is designed in L-Edit software.

  9. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

  10. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y.; James, Ralph B.

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  11. Wafer plane inspection evaluated for photomask production

    NASA Astrophysics Data System (ADS)

    Gallagher, Emily; Badger, Karen; Lawliss, Mark; Kodera, Yutaka; Azpiroz, Jaione Tirapu; Pang, Song; Zhang, Hongqin; Eugenieva, Eugenia; Clifford, Chris; Goonesekera, Arosha; Tian, Yibin

    2008-10-01

    Wafer Plane Inspection (WPI) is a novel approach to inspection, developed to enable high inspectability on fragmented mask features at the optimal defect sensitivity. It builds on well-established high resolution inspection capabilities to complement existing manufacturing methods. The production of defect-free photomasks is practical today only because of informed decisions on the impact of defects identified. The defect size, location and its measured printing impact can dictate that a mask is perfectly good for lithographic purposes. This inspection - verification - repair loop is timeconsuming and is predicated on the fact that detectable photomask defects do not always resolve or matter on wafer. This paper will introduce and evaluate an alternative approach that moves the mask inspection to the wafer plane. WPI uses a high NA inspection of the mask to construct a physical mask model. This mask model is used to create the mask image in the wafer plane. Finally, a threshold model is applied to enhance sensitivity to printing defects. WPI essentially eliminates the non-printing inspection stops and relaxes some of the pattern restrictions currently placed on incoming photomask designs. This paper outlines the WPI technology and explores its application to patterns and substrates representative of 32nm designs. The implications of deploying Wafer Plane Inspection will be discussed.

  12. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  13. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  14. Laser furnace and method for zone refining of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

    1988-01-01

    A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

  15. Diamond-like nanocomposite coatings for LIGA-fabricated nickel alloy parts.

    SciTech Connect

    Prasad, Somuri V.; Scharf, Thomas W.

    2005-03-01

    A commercial plasma enhanced chemical vapor deposition (PECVD) technique with planetary substrate rotation was used to apply a thin (200-400 nm thick) conformal diamond-like carbon (DLC) coating (known as a diamond-like nanocomposite (DLN)) on LIGA fabricated Ni-Mn alloy parts. The PECVD technique is known to overcome the drawbacks associated with the line-of-sight nature of physical vapor deposition (PVD) and substrate heating inherent with traditional chemical vapor deposition (CVD). The purpose of the present study is to characterize the coverage, adhesion, and tribological (friction and wear) behavior of DLN coatings applied to planar and sidewall surfaces of small featured LIGA Ni-Mn fabricated parts, e.g. 280 {micro}m thick sidewalls. Friction and wear tests were performed in dry nitrogen, dry air, and air with 50% RH at Hertzian contact pressures ranging from 0.3 to 0.6 GPa. The friction coefficient of bare Ni-Mn alloy was determined to be 0.9. In contrast, low friction coefficients ({approx}0.02 in dry nitrogen and {approx}0.2 in 50% RH air) and minimal amount of wear were exhibited for the DLN coated LIGA Ni-Mn alloy parts and test coupons. This behavior was due to the ability of the coating to transfer to the rubbing counterface providing low interfacial shear at the sliding contact; resultantly, coating one surface was adequate for low friction and wear. In addition, a 30 nm thick titanium bond layer was determined to be necessary for good adhesion of DLN coating to Ni-Mn alloy substrates. Raman spectroscopy and cross-sectional SEM with energy dispersive x-ray analysis revealed that the DLN coatings deposited by the PECVD with planetary substrate rotation covered both the planar and sidewall surfaces of LIGA fabricated parts, as well as narrow holes of 300 {micro}m (0.012 inch) diameter.

  16. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu

  17. Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

    NASA Astrophysics Data System (ADS)

    Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

    2001-11-01

    The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

  18. Effect of wafer geometry on lithography chucking processes

    NASA Astrophysics Data System (ADS)

    Turner, Kevin T.; Sinha, Jaydeep K.

    2015-03-01

    Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

  19. Apparatus for edge etching of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Casajus, A.

    1986-01-01

    A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

  20. Methanol Steam Reformer on a Silicon Wafer

    SciTech Connect

    Park, H; Malen, J; Piggott, T; Morse, J; Sopchak, D; Greif, R; Grigoropoulos, C; Havstad, M; Upadhye, R

    2004-04-15

    A study of the reforming rates, heat transfer and flow through a methanol reforming catalytic microreactor fabricated on a silicon wafer are presented. Comparison of computed and measured conversion efficiencies are shown to be favorable. Concepts for insulating the reactor while maintaining small overall size and starting operation from ambient temperature are analyzed.

  1. Wafer capping of MEMS with fab-friendly metals

    NASA Astrophysics Data System (ADS)

    Martin, Jack

    2007-01-01

    Inertial MEMS (Micro Electro Mechanical System) sensors are normally sealed in hermetic enclosures. Some are assembled in hermetic packages but wafer level packaging has become much more important in recent years. Anodic bonding can be used to achieve wafer level seals between silicon and glass but most suppliers of inertial sensors screen print glass frit onto silicon cap wafers. After removing the organic vehicle, these patterned cap wafers are sealed to device wafer prior to wafer singulation and plastic packaging. Anodic and glass frit bonding are both cost-effective. However, they impose size, quality and performance limitations. Wafer level sealing with a metal removes some of these limitations but introduces other concerns. This paper will review the current wafer level hermetic processes followed by a description of a thermocompression metal seal technology that is compatible with IC fabrication.

  2. Wafer plane inspection for advanced reticle defects

    NASA Astrophysics Data System (ADS)

    Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

    2008-05-01

    Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

  3. Innovative optical alignment technique for CMP wafers

    NASA Astrophysics Data System (ADS)

    Sugaya, Ayako; Kanaya, Yuho; Nakajima, Shinichi; Nagayama, Tadashi; Shiraishi, Naomasa

    2002-07-01

    Detecting position of the wafers such as after CMP process is critical theme of current and forthcoming IC manufacturing. The alignment system must be with high accuracy for any process. To satisfy such requirements, we have studied and analyzed factors that have made alignment difficult. From the result of the studies, we have developed new optical alignment techniques which improve the accuracy of FIA (alignment sensor of Nikon's NSR series) and examined them. The approaches are optimizing the focus position, developing an advanced algorithm for position detection, and selecting a suitable mark design. For experiment, we have developed the special wafers that make it possible to evaluate the influence of CMP processes. The experimental results show that the overlay errors decrease dramatically with the new alignment techniques. FIA with these new techniques will be much accurate and suitable alignment sensor for CMP and other processes of future generation ULSI production.

  4. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  5. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.; St. Martin, Edward; Arora, Michelle; de la Garza, Linda

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  6. TOPICAL REVIEW: Wafer level packaging of MEMS

    NASA Astrophysics Data System (ADS)

    Esashi, Masayoshi

    2008-07-01

    Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass-Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review.

  7. Heterostructurally integrated III-V semiconductors fabricated by wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Shi, Fang Frank

    Integrating advanced microelectronic, photonic, and micromechanical devices, including nanoscale devices, into a three-dimensional architecture has become a key issue to realizing the advanced microintegrated systems for both electronic and biotechnological applications. Wafer bonding (wafer fusion) has been considered as one of the most promising technologies to integrate mismatched materials and devices into a chip level. One of the primary concerns of on-chip integration of mismatched micro- or nanodevices would be of material compatibility and interface structures at different length scales (including nanoscale), and the structural relations with the device electronic, optical, and mechanical performances. Accordingly, in the first section of this thesis work, the interface microstructures of wafer-bonded semiconductors, such as GaAs, InP, and GaN, have been systematically studied. The relations among the interface morphologies, chemistry, dislocation structures, and the wafer bonding processes have been determined. The electronic transport behaviors of both n-typed and p-typed majority and minority carriers at different wafer-bonded interface junctions with emphasis on the temporal correlations of electrical properties and interface microstructures from varied annealing processes have also been analyzed. Furthermore, the effects of the wafer rotation alignments on electrical characteristics of both n-n and p-n junctions have been investigated. Quantitative relations of interface conductivity of n-n junctions and ideality factor of p-n junctions at different alignment with varied annealing conditions have also been reported. Secondly, the adhesion, mechanical reliability, and wafer bondability of directly bonded GaAs, InP, and GaN semiconductors, together with their interfacial microfailure model, have also been carefully analyzed through the correlations between the wafer annealing processes, interface fracture energy and shear strength, and microfailure

  8. Wafer plane inspection with soft resist thresholding

    NASA Astrophysics Data System (ADS)

    Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

    2008-10-01

    Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

  9. Precipitating Chromium Impurities in Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Salama, A. M.

    1982-01-01

    Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

  10. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.