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Sample records for 90-nm cmos adaptive

  1. Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node

    NASA Technical Reports Server (NTRS)

    Ladbury, Raymond L.; Gorelick, Jerry L.; Berg, M. D.; Kim, H.; LaBel, K.; Friendlich, M.; Koga, R.; George, J.; Crain, S.; Yu, P.; Reed, R. A.

    2006-01-01

    We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer.

  2. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    NASA Astrophysics Data System (ADS)

    Rivetti, A.; Battaglia, M.; Bisello, D.; Caselle, M.; Chalmet, P.; Costa, M.; Demaria, N.; Giubilato, P.; Ikemoto, Y.; Kloukinas, K.; Mansuy, C.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rousset, J.; Silvestrin, L.; Wyss, J.

    2013-12-01

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 Ω cm, which is at least one order of magnitude greater than the typical value (1 - 10 Ω cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported.

  3. A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

    NASA Astrophysics Data System (ADS)

    Wenwei, He; Qiao, Meng; Yi, Zhang; Kai, Tang

    2014-08-01

    A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is presented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold amplifier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a differential nonlinearity < ±0.3 LSB and an integral nonlinearity < ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm2 with the pad. It consumes 210 mW from a 1.2 V single supply.

  4. IC design of low power, wide tuning range VCO in 90 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Zhu, Li; Zhigong, Wang; Zhiqun, Li; Qin, Li; Faen, Liu

    2014-12-01

    A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET (IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27-32.5 GHz, exhibiting a frequency tuning range (FTR) of 18.4% and a phase noise of -101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of -185 dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 mA DC current.

  5. 10-bit segmented current steering DAC in 90nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Bringas, R., Jr.; Dy, F.; Gerasta, O. J.

    2015-06-01

    This special project presents a 10-Bit 1Gs/s 1.2V/3.3V Digital-to-Analog Converter using1 Poly 9 Metal SAED 90-nm CMOS Technology intended for mixed-signal and power IC applications. To achieve maximum performance with minimum area, the DAC has been implemented in 6+4 Segmentation. The simulation results show a static performance of ±0.56 LSB INL and ±0.79 LSB DNL with a total layout chip area of 0.683 mm2.The segmented architecture is implemented using two sub DAC's, which are the LSB and MSB section with certain number bits. The DAC is designed using 4-BitBinary Weighted DAC for the LSB section and 6-BitThermometer-coded DAC for the MSB section. The thermometer-coded architecture provides the most optimized results in terms of linearity through reducing the clock feed-through effect especially in hot switching between multiple transistors. The binary- weighted architecture gives better linearity output in higher frequencies with better saturation in current sources.

  6. Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90 nm CMOS process.

    PubMed

    Chen, Tung-Chien; Ma, Tsung-Chuan; Chen, Yun-Yu; Chen, Liang-Gee

    2012-01-01

    Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However for the long duration experiments on free-moving subjects, the miniaturized and wireless neural recording ICs are the current trend, and the compromise on sorting accuracy is usually made by a lower SR for the lower power consumption. In this paper, we implement an on-chip spike sorting processor with integrated interpolation hardware in order to improve the performance in terms of power versus accuracy. According to the fabrication results in 90nm process, if the interpolation is appropriately performed during the spike sorting, the system operated at the SR of 12.5 k samples per second (sps) can outperform the one not having interpolation at 25 ksps on both accuracy and power.

  7. Closed-loop adaptive optics using a CMOS image quality metric sensor

    NASA Astrophysics Data System (ADS)

    Ting, Chueh; Rayankula, Aditya; Giles, Michael K.; Furth, Paul M.

    2006-08-01

    When compared to a Shack-Hartmann sensor, a CMOS image sharpness sensor has the advantage of reduced complexity in a closed-loop adaptive optics system. It also has the potential to be implemented as a smart sensor using VLSI technology. In this paper, we present a novel adaptive optics testbed that uses a CMOS sharpness imager built in the New Mexico State University (NMSU) Electro-Optics Research Laboratory (EORL). The adaptive optics testbed, which includes a CMOS image quality metric sensor and a 37-channel deformable mirror, has the capability to rapidly compensate higher-order phase aberrations. An experimental performance comparison of the pinhole image sharpness feedback method and the CMOS imager is presented. The experimental data shows that the CMOS sharpness imager works well in a closed-loop adaptive optics system. Its overall performance is better than that of the pinhole method, and it has a fast response time.

  8. Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan A.; LaBel, Kenneth A.

    2010-01-01

    The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

  9. On numerical simulation of high-speed CCD/CMOS-based wavefront sensors in adaptive optics

    NASA Astrophysics Data System (ADS)

    Konnik, Mikhail V.; Welsh, James Stuart

    2011-10-01

    Wavefront sensors, which use solid-state CCD or CMOS photosensors, are sources of errors in adaptive optic systems. Inaccuracy in the detection of wavefront distortions introduces considerable errors into wavefront reconstruction and leads to overall performance degradation of the adaptive optics system. The accuracy of wavefront sensors is significantly affected by photosensor noise. Thus, it is crucial to formulate high-level photosensor models that enable adaptive optic engineers to simulate realistic effects of noise from wavefront sensors. However, the complexity of solid-state photosensors and multiple noise sources makes it difficult to formulate an adequate model of the photosensor. Moreover, the characterisation of the simulated sensor and comparison with real hardware is often incomplete due to lack of comprehensive standards and guidelines. Owe to these difficulties, engineers work with oversimplified models of the wavefront sensors and consequently have imprecise numerical simulation results. The paper presents an approach for the modelling of noise sources for CCD and CMOS sensors that are used for wavefront sensing in adaptive optics. Both dark and light noise such as fixed pattern noise, photon shot noise, and read noises, as well as, charge-to-voltage noises are described. Procedures for characterisation of both light and dark noises of the simulated photosensors are provided. Numerical simulation results of a photosensor for a high-frame rate Shack-Hartmann wavefront sensor are presented.

  10. Achieving CDU requirement for 90-nm technology node and beyond with advanced mask making process technology

    NASA Astrophysics Data System (ADS)

    Tzu, San-De; Chang, Chung-Hsing; Chen, Wen-Chi; Kliem, Karl-Heinz; Hudek, Peter; Beyer, Dirk

    2005-01-01

    For 90nm node and beyond technology generations, one of the most critical challenges is how to meet the local CD uniformity (proximity) and global CD uniformity (GCDU) requirements within the exposure field. Both of them must be well controlled in the mask making process: (1) proximity effect and, (2) exposure pattern loading effect, or the so-called e-beam "fogging effect". In this paper, we report a method to improve our global CDU by means of a long range fogging compensation together with the Leica SB350 MW. This exposure tool is operated at 50keV and 1nm design grid. The proximity correction is done by the software - package "PROXECCO" from PDF Solutions. We have developed a unique correction method to reduce the fogging effect in dependency of the pattern density of the mask. This allows us to meet our customers" CDU specifications for the 90nm node and beyond.

  11. Specifications and methodologies for benchmarking of advanced CD-SEMs at the 90-nm CMOS technology node and beyond

    NASA Astrophysics Data System (ADS)

    Bunday, Benjamin D.; Bishop, Michael

    2003-05-01

    In this work, an extremely flexible and simple dissolution rate monitor (DRM) based on inexpensive, commercially available, PC card spectrometers has been built that can be used quite robustly in both fab and laboratory environments for measuring the dissolution behavior of photoreist films. The hardware required in order to construct such a simple apparatus has been discussed along with various experimental configurations that are appropriate for different measurement tasks. A multiwavelength interferometric data analysis software (MIDAS) has been developed in this work that can robustly perform both single wavelength and multiwavelength DRM data analysis. The multiwavelength DRM and MIDAS software have been found to be very useful in analyzing a variety of resist film dissolution phenomena including monitoring films possessing dissolution rates exceeding 100 nm/s and studying resist film surface inhibition/acceleration. Another useful application has been to measure swelling in the processing of photoresists and other polymer thin films. The basic approaches and algorithms used for thin film thickness and dissolution rate determination in the MIDAS software are discussed in this paper. Results from the use of the MIDAS software in various applications are presented.

  12. Adaptive Threshold Neural Spike Detector Using Stationary Wavelet Transform in CMOS.

    PubMed

    Yang, Yuning; Boling, C Sam; Kamboh, Awais M; Mason, Andrew J

    2015-11-01

    Spike detection is an essential first step in the analysis of neural recordings. Detection at the frontend eases the bandwidth requirement for wireless data transfer of multichannel recordings to extra-cranial processing units. In this work, a low power digital integrated spike detector based on the lifting stationary wavelet transform is presented and developed. By monitoring the standard deviation of wavelet coefficients, the proposed detector can adaptively set a threshold value online for each channel independently without requiring user intervention. A prototype 16-channel spike detector was designed and tested in an FPGA. The method enables spike detection with nearly 90% accuracy even when the signal-to-noise ratio is as low as 2. The design was mapped to 130 nm CMOS technology and shown to occupy 0.014 mm(2) of area and dissipate 1.7 μW of power per channel, making it suitable for implantable multichannel neural recording systems. PMID:25955990

  13. Adaptive Threshold Neural Spike Detector Using Stationary Wavelet Transform in CMOS.

    PubMed

    Yang, Yuning; Boling, C Sam; Kamboh, Awais M; Mason, Andrew J

    2015-11-01

    Spike detection is an essential first step in the analysis of neural recordings. Detection at the frontend eases the bandwidth requirement for wireless data transfer of multichannel recordings to extra-cranial processing units. In this work, a low power digital integrated spike detector based on the lifting stationary wavelet transform is presented and developed. By monitoring the standard deviation of wavelet coefficients, the proposed detector can adaptively set a threshold value online for each channel independently without requiring user intervention. A prototype 16-channel spike detector was designed and tested in an FPGA. The method enables spike detection with nearly 90% accuracy even when the signal-to-noise ratio is as low as 2. The design was mapped to 130 nm CMOS technology and shown to occupy 0.014 mm(2) of area and dissipate 1.7 μW of power per channel, making it suitable for implantable multichannel neural recording systems.

  14. LGSD/NGSD: high speed optical CMOS imagers for E-ELT adaptive optics

    NASA Astrophysics Data System (ADS)

    Downing, Mark; Kolb, Johann; Balard, Philippe; Dierickx, Bart; Defernez, Arnaud; Feautrier, Philippe; Finger, Gert; Fryer, Martin; Gach, Jean-Luc; Guillaume, Christian; Hubin, Norbert; Jerram, Paul; Jorden, Paul; Meyer, Manfred; Payne, Andrew; Pike, Andrew; Reyes, Javier; Simpson, Robert; Stadler, Eric; Stent, Jeremy; Swift, Nick

    2014-07-01

    The success of the next generation of instruments for ELT class telescopes will depend upon improving the image quality by exploiting sophisticated Adaptive Optics (AO) systems. One of the critical components of the AO systems for the E-ELT has been identified as the optical Laser/Natural Guide Star WFS detector. The combination of large format, 1760×1680 pixels to finely sample the wavefront and the spot elongation of laser guide stars, fast frame rate of 700 frames per second (fps), low read noise (< 3e-), and high QE (> 90%) makes the development of this device extremely challenging. Design studies concluded that a highly integrated Backside Illuminated CMOS Imager built on High Resistivity silicon as the most likely technology to succeed. Two generations of the CMOS Imager are being developed: a) the already designed and manufactured NGSD (Natural Guide Star Detector), a quarter-sized pioneering device of 880×840 pixels capable of meeting first light needs of the E-ELT; b) the LGSD (Laser Guide Star Detector), the larger full size device. The detailed design is presented including the approach of using massive parallelism (70,400 ADCs) to achieve the low read noise at high pixel rates of ~3 Gpixel/s and the 88 channel LVDS 220Mbps serial interface to get the data off-chip. To enable read noise closer to the goal of 1e- to be achieved, a split wafer run has allowed the NGSD to be manufactured in the more speculative, but much lower read noise, Ultra Low Threshold Transistors in the unit cell. The NGSD has come out of production, it has been thinned to 12μm, backside processed and packaged in a custom 370pin Ceramic PGA (Pin Grid Array). First results of tests performed both at e2v and ESO are presented.

  15. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    NASA Astrophysics Data System (ADS)

    Yin, Lan; Bozler, Carl; Harburg, Daniel V.; Omenetto, Fiorenzo; Rogers, John A.

    2015-01-01

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  16. Non-chemical cleaning technology for sub-90nm design node photomask manufacturing

    NASA Astrophysics Data System (ADS)

    Hoyeh, Star; Chen, Richard; Kozuma, Makoto; Kuo, Joann; Huang, Torey; Chen, Frank F.

    2006-10-01

    Cleaning chemistry residue in photomask manufacturing is one of root causes to generate HAZE over surface of photomask for 193nm and shorter wavelength exposure tools. In order to reduce the residue, chemical free process is one of targets in photomask industry. In this paper novel clean technology without sulfuric acid and ammonia chemical are shown to manufacture sub-90nm node photomask. Photo and E-beam resist were removed by plasma and ozone water clean instead of sulfuric acid. SPM and APM in final clean sequence before defect inspection were substituted with ozone water and hydrogen water respectively. The clean performance was demonstrated in real production of 193nm phase shift mask. Sulfate and Ammonia residue after final clean were controlled same as blank material level without any clean process.

  17. ArF processing of 90-nm design rule lithography achieved through enhanced thermal processing

    NASA Astrophysics Data System (ADS)

    Kagerer, Markus; Miller, Daniel; Chang, Wayne; Williams, Daniel J.

    2006-03-01

    As the lithography community has moved to ArF processing on 300 mm wafers for 90 nm design rules the process characterization of the components of variance continues to highlight the thermal requirements for the post exposure bake (PEB) processing step. In particular as the thermal systems have become increasingly uniform, the transient behavior of the thermal processing system has received the focus of attention. This paper demonstrates how a newly designed and patented thermal processing system was optimized for delivering improved thermal uniformity during a typical 90 second PEB processing cycle, rather than being optimized for steady state performance. This was accomplished with the aid of a wireless temperature measurement wafer system for obtaining real time temperature data and by using a response surface model (RSM) experimental design for optimizing parameters of the temperature controller of the thermal processing system. The new units were field retrofitted seamlessly in <2 days at customer sites without disruption to process recipes or flows. After evaluating certain resist parameters such as PEB temperature sensitivity and post exposure delay (PED) - stability of the baseline process, the new units were benchmarked against the previous PEB plates by processing a split lot experiment. Additional hardware characterization included environmental factors such as air velocity in the vicinity of the PEB plates and transient time between PEB and chill plate. At the completion of the optimization process, the within wafer CD uniformity displayed a significant improvement when compared to the previous hardware. The demonstrated within wafer CD uniformity improved by 27% compared to the initial hardware and baseline process. ITRS requirements for the 90 nm node were exceeded.

  18. A low power CMOS 3.3 Gbps continuous-time adaptive equalizer for serial link

    NASA Astrophysics Data System (ADS)

    Hao, Ju; Yumei, Zhou; Jianzhong, Zhao

    2011-09-01

    This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface, which is compliant with many serial communication specifications such as USB2.0, PCI-E2.0 and Rapid IO. The low and high frequency loops are merged to decrease the effect of delay between the two paths, in addition, the infinite input impedance facilitates the cascade stages in order to improve the high frequency boosting gain. The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces, which brings as much as 25 dB loss. The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation. In addition, AC coupling is adopted to suppress the common input from the forward stage. A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology. The actual area is 0.6 × 0.57 mm2 and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss. The overall power dissipation is approximately 23.4 mW.

  19. Evaluation of IDEALSmile for 90-nm FLASH memory contact holes imaging with ArF scanner

    NASA Astrophysics Data System (ADS)

    Cantu, Pietro; Capetti, Gianfranco; Loi, Sara; Lupo, Marco; Pepe, Annalisa; Saitoh, Kenji; Yamazoe, Kenji; Hasegawa, Yasuo; Iwasa, Junji; Toublan, Olivier R.

    2004-05-01

    According to sizes dictated by ITRS road map, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. The development of 90[nm] technology FLASH memories requires a robust solution for printing contact holes down to 100[nm] on 200[nm] pitch. The delay of NGL development as well as open issues related to 157[nm] scanner introduction pushes the industry to find a solution for printing such tight features using existing ArF scanner. IDEALSmile technology from Canon was proven to be a good candidate for achieving such high resolution with sufficiently large through pitch process window using a binary mask, relatively simple to be manufactured, with a modified illumination and single exposure, with no impact on throughput and without any increase of cost of ownership. This paper analyses main issues related to the introduction of this new resolution enhancement technology on a real FLASH memory device, highlighting advantages as well as known problems still under investigation.

  20. Transport and noise in 90nm n-GaAs Epilayers

    NASA Astrophysics Data System (ADS)

    Gilbertson, A.; Moore, J. D.; Perkins, G.; Gallop, J.; Cohen, L. F.; Newaz, A. K. M.; Solin, S. A.

    2009-03-01

    Extraordinary Magnetoresistance (EMR) belongs to the family of EXX effects which form the basis for a number of devices that offer the potential for high sensitivity applications. Such devices would benefit from minimising the active volume of the sensor. To reduce that volume and minimize wafer fabrication complexity it is desirable to employ unltra-thin GaAs epilayers. Accordingly, we report here the transport and noise properties of 90nm Si-doped GaAs films grown by molecular beam epitaxy which have been fabricated into both microscopic EMR devices and macroscopic van der Pauw geometries. These films exhibit a room temperature electron mobility and density of 3225 cm^2V-1s-1 and1.45x10^17cm-3, respectively, and show only a 6% variation over the temperature range 2K

  1. In-line 90 nm Technology Gate Oxide Nitrogen Monitoring With Non-Contact Electrical Technique

    NASA Astrophysics Data System (ADS)

    Pic, Nicolas; Polisski, Gennadi; Paire, Emmanuel; Rizzo, Véronique; Grosjean, Catherine; Bortolotti, Benjamin; D'Amico, John; Cabuil, Nicolas

    2009-09-01

    The continuous race to reduce the dimensions of IC components has lead to the introduction of Nitrogen in the thin gate oxide layer in order to increase the dielectric constant and to improve the gate dielectric properties. It is mandatory to apply in-line monitoring to control the amount of Nitrogen to ensure that electrical behavior is correct over time. Historically, this monitoring was performed by measuring the delay to reoxidation (D2R) with an ellipsometer. But, this method is not suitable in production as it is depending on both initial oxidation and reoxidation reproducibility, which implies implementing dedicated Statistical Process Control (SPC) monitoring at these two specific processing steps. We are here presenting an alternative method to D2R for 90 nm Technology gate oxide grown by Rapid Thermal Process (RTP). Applying a non-contact Metrology technique, which couples Kelvin probe surface voltage measurement with surface Corona deposition, directly after the nitridation step, the interface trapped charge (QIT) is obtained by integration of the interface state density over the space charge region. In summary, this electrical non-contact monitoring is more sensitive to the Nitrogen content compared to ellipsometer measurement after nitridation or after D2R, less sensitive compared to D2R to any initial oxide variation, and it allows simplification of the qualification procedure at this process step by skipping the reoxidation.

  2. Asymmetric MQW semiconductor optical amplifier with low-polarization sensitivity of over 90-nm bandwidth

    NASA Astrophysics Data System (ADS)

    Nkanta, Julie E.; Maldonado-Basilio, Ramón; Abdul-Majid, Sawsan; Zhang, Jessica; Hall, Trevor J.

    2013-12-01

    An exhausted capacity of current Passive Optical Networks has been anticipated as bandwidth-hungry applications such as HDTV and 3D video become available to end-users. To enhance their performance, the next generation optical access networks have been proposed, using optical carriers allocated within the E-band (1360-1460 nm). It is partly motivated by the low-water peak fiber being manufactured by Corning. At these wavelengths, choices for low cost optical amplifiers, with compact size, low energy consumption and feasibility for integration with other optoelectronic components are limited, making the semiconductor optical amplifiers (SOA) a realistic solution. An experimental characterization of a broadband and low polarization sensitive asymmetric multi quantum well (MQW) SOA operating in the E-band is reported. The SOA device is composed of nine 6 nm In1-xGaxAsyP1-y 0.2% tensile strained asymmetric MQW layers sandwiched between nine latticed matched 6 nm InGaAsP barrier layers. The active region is grown on an n-doped InP substrate and buried by p-doped InGaAsP layers. The SOA devices have 7-degrees tilt anti-reflected coated facets, with 2 μm ridge width, and a cavity length of 900 μm. For input powers of -10 dBm and -20 dBm, a maximum gain of 20 dB at 1360 nm with a polarization insensitivity under 3 dB for over 90 nm bandwidth is measured. Polarization sensitivity of less than 0.5 dB is observed for some wavelengths. Obtained results indicate a promising SOA with broadband amplification, polarization insensitivity and high gain. These SOAs were designed and characterized at the Photonics Technology Laboratory, University of Ottawa, Canada.

  3. DOE experiment for scattering bars optimization at the 90nm node

    NASA Astrophysics Data System (ADS)

    Bouton, G.; Connolly, B.; Courboin, D.; Di Giacomo, A.; Gasnier, F.; Lallement, R.; Parker, D.; Pindo, M.; Richoilley, J. C.; Royere, F.; Rameau-Savio, A.; Tissier, M.

    2011-03-01

    Scattering bars (SB) are sub-resolution lines added to the original database during Resolution Enhancement Techniques (RET) treatments. Their goal is stabilizing the CD of the adjacent polygons (by suppressing or reducing secondary diffraction waves). SB increase the process window in the litho process by lowering the first derivative of the CD. Moreover, the detailed knowledge of SB behavior around the fab working point is a must for future shrinks and for preparing the next technology nodes. SB are inserted in the generation of critical levels for STMicroelectronics 90 nm technology embedded memories before invoking the Model for Optical Proximity Corrections (MBOPC). This allows the software to calculate their contribution to the intensity in the aerial image and integrate their effects in Edge Proximity Error (EPE) corrections. However the Rule-Based insertion of these assist features still leaves behind occurrences of conflicting priorities as in the image below. (See manuscript PDF)Detection of Hot Spots in 2D simulations for die treatment validation (done on BRION equipment on each critical level before mask making) is in most cases correlated with SB singularities, at least for CD non-uniformity, bridging issues and necking in correspondence with OPC fragmentation effects. Within the framework of the MaXSSIMM project, we established a joint STMicroelectronics and Toppan Photomasks team to explore the influence of assist features (CD, distance), convex and concave corner rounding and CD uniformity by means of specific test patterns. The proposed study concerns the algorithms used to define the mask shop input as well as the physical mask etching. A set of test cases, based on elementary test patterns, each one including a list of geometrical variations, has been defined. As the number of configurations becomes rapidly very large (tens of thousands) we had to apply Design of Experiments (DOE) algorithms in order to reduce the number of measurements to a

  4. Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

    NASA Astrophysics Data System (ADS)

    Nogami, T.; Lane, S.; Fukasawa, M.; Ida, K.; Angyal, M.; Chanda, K.; Chen, F.; Christiansen, C.; Cohen, S.; Cullinan, M.; Dziobkowski, C.; Fitzsimmons, J.; Flaitz, P.; Grill, A.; Gill, J.; Inoue, K.; Klymko, N.; Kumar, K.; Labelle, C.; Lane, M.; Li, B.; Liniger, E.; Madon, A.; Malone, K.; Martin, J.; McGahay, V.; McLaughlin, P.; Melville, I.; Minami, M.; Molis, S.; Nguyen, S.; Penny, C.; Restaino, D.; Sakamoto, A.; Sankar, M.; Sherwood, M.; Simonyi, E.; Shimooka, Y.; Tai, L.; Widodo, J.; Wildman, H.; Ono, M.; McHerron, D.; Nye, H.; Davis, C.; Sankaran, S.; Edelstein, D.; Ivers, T.

    2005-11-01

    This paper discusses low-k/copper integration schemes which has been in production in the 90 nm node, have been developed in the 65 nm node, and should be taken in the 45 nm node. While our baseline 65 nm BEOL process has been developed by extension and simple shrinkage of our PECVD SiCOH integration which has been in production in the 90 nm node with our SiCOH film having k=3.0, the 65 nm SiCOH integration has two other options to go to extend to lower capacitance. One is to add porosity to become ultra low-k (ULK). The other is to stay with low-k SiCOH, which is modified to have a "lower-k". The effective k- value attained with the lower-k (k=2.8) SiCOH processed in the "Direct CMP" scheme is very close to that with an ULK (k=2.5) SiCOH film built with the "Hard Mask Retention" scheme. This paper first describes consideration of these two damascene schemes, whose comparison leads to the conclusion that the lower-k SiCOH integration can have more advantages in terms of process simplicity and extendibility of our 90 nm scheme under certain assumptions. Then describing the k=2.8 SiCOH film development and its successful integration, damascene schemes for 45nm nodes are discussed based on our learning from development of the lower-k 65nm scheme. Capability of modern dry etchers to define the finer patterns, non-uniformity of CMP, and susceptibility to plasma and mechanical strength and adhesion of ULK are discussed as factors to hamper the applicability of ULK.

  5. Novel Circuitry Configuration with Paired-Cell Erase Operation for High-Density 90-nm Embedded Resistive Random Access Memory

    NASA Astrophysics Data System (ADS)

    Sato, Yoshihiro; Tsunoda, Koji; Aoki, Masaki; Sugiyama, Yoshihiro

    2009-04-01

    We propose a novel circuitry configuration for high-density 90-nm embedded resistive random access memory (ReRAM). The memory cells are operated at 2 V, and a small memory cell size of 6F2 consisting of a 1.2-V standard transistor and a resistive junction (1T-1R) is designed, where F is the feature size. The unique circuitry configuration is that each pair of source-lines connects to each source-line selective gate. Therefore, erasing is done by a pair of cells in turn in the whole sector, while the reading or programming is done by a random accessing operation. We simulated the ReRAM circuit for read and write operations with SPICE. As a result, we found that 5-ns high-speed read access was obtained in the 256-word lines (WLs) × 256-bit lines (BLs) and that the SET/RESET operation was stable.

  6. Ion traps fabricated in a CMOS foundry

    SciTech Connect

    Mehta, K. K.; Ram, R. J.; Eltony, A. M.; Chuang, I. L.; Bruzewicz, C. D.; Sage, J. M. Chiaverini, J.

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  7. Optimization of building blocks for multi-stage 17-44 dB 6.1-9.6 mW 90-nm K-band front-ends

    NASA Astrophysics Data System (ADS)

    Roy, Apratim; Harun Rashid, A.

    2013-12-01

    In this article, five two-stage ˜6-mW and four three-stage ˜9-mW matched amplifier architectures are proposed to establish optimization procedure and quantify relative merits of cascode (CC), common-gate (CG), and commonsource (CS) building blocks for low-voltage low-power multi-stage front-ends. The circuits are simulated with a 90-nm CMOS technology including modeling of layout parasites. Integrated bias trees and passive port matching networks are incorporated in the K-band designs. In the face of process mismatch, variability in noise and gain figures remains <0.39 dB and <7.1 dB from the design values. The five combinations of building blocks in twostage low-power (6.1-6.6 mW) amplifiers achieve linearity (IIP3) in the range of -5.2˜-13.5 dBm, good reverse isolation (better than -26 dB), 2.89-3.82 dB noise penalties, and 17.2-25.5 dB peak forward gain. In case of threestage front-ends built with CS, CC, and CG blocks (power rating 9.2-9.6 mW), forward gain and optimized noise figures are found as >33 dB and <3.26 dB, respectively. They achieve -2.5˜18.3 dBm IIP3, <-39 dB reverse isolation, and <-17 dB minimum IRL. The results are compared with reported simulated findings on CMOS multistage amplifiers to highlight their relative advantages in terms of power requirement and decibel(gain)-per-watt.

  8. Advanced mask technique to improve bit line CD uniformity of 90 nm node flash memory in low-k1 lithography

    NASA Astrophysics Data System (ADS)

    Kim, Jong-doo; Choi, Jae-young; Kim, Jea-hee; Han, Jae-won

    2008-10-01

    As devices size move toward 90nm technology node or below, defining uniform bit line CD of flash devices is one of the most challenging features to print in KrF lithography. There are two principal difficulties in defining bit line on wafer. One is insufficient process margin besides poor resolution compared with ArF lithography. The other is that asymmetric bit line should be made for OPC(Optical Proximity Correction) modeling. Therefore advanced ArF lithography scanner should be used for define bit line with RETs (Resolution Enhancement Techniques) such as immersion lithography, OPC, PSM(Phase Shift Mask), high NA(Numerical Aperture), OAI(Off-Axis Illumination), SRAF(Sub-resolution Assistant Feature), and mask biasing.. Like this, ArF lithography propose the method of enhancing resolution, however, we must spend an enormous amount of CoC(cost of ownership) to utilize ArF photolithography process than KrF. In this paper, we suggest method to improve of bit line CD uniformity, patterned by KrF lithographic process in 90nm sFlash(stand alone Flash) devices. We applied new scheme of mask manufacturing, which is able to realize 2 different types of mask, binary and phase-shift, into one plate. Finally, we could get the more uniform bit lines and we expect to get more stable properties then before applying this technique.

  9. Nano watt power rail-to-rail CMOS amplifier with adaptive biasing circuits for ultralow-power analog LSIs

    NASA Astrophysics Data System (ADS)

    Ozaki, Toshihiro; Hirose, Tetsuya; Tsubaki, Keishi; Kuroki, Nobutaka; Numa, Masahiro

    2015-04-01

    In this paper, we present a rail-to-rail folded-cascode amplifier (AMP) with adaptive biasing circuits (ABCs). The circuit uses a nano ampere current reference circuit to achieve ultralow-power and ABCs to achieve high-speed operation. The ABCs are based on conventional circuits and modified to be suitable for rail-to-rail operation. The measurement results demonstrated that the AMP with the proposed ABCs can operate with an ultralow-power of 384 nA when the input voltage was 0.9 V and achieve high speeds of 0.162 V/µs at the rise time and 0.233 V/µs at the fall time when the input pulse frequency and the amplitude were 10 kHz and 1.5 Vpp, respectively.

  10. A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems.

    PubMed

    Zheng, Xuezhe; Liu, Frankie; Patil, Dinesh; Thacker, Hiren; Luo, Ying; Pinguet, Thierry; Mekis, Attila; Yao, Jin; Li, Guoliang; Shi, Jing; Raj, Kannan; Lexau, Jon; Alon, Elad; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

    2010-01-01

    We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible.

  11. A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems.

    PubMed

    Zheng, Xuezhe; Liu, Frankie; Patil, Dinesh; Thacker, Hiren; Luo, Ying; Pinguet, Thierry; Mekis, Attila; Yao, Jin; Li, Guoliang; Shi, Jing; Raj, Kannan; Lexau, Jon; Alon, Elad; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

    2010-01-01

    We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible. PMID:20173840

  12. 324GHz CMOS VCO Using Linear Superimposition Technique

    NASA Technical Reports Server (NTRS)

    Daquan, Huang; LaRocca, Tim R.; Samoska, Lorene A; Fung, Andy; Chang, Frank

    2007-01-01

    Terahertz (frequencies ranged from 300GHz to 3THz) imaging and spectroscopic systems have drawn increasing attention recently due to their unique capabilities in detecting and possibly analyzing concealed objects. The generation of terahertz signals is nonetheless nontrivial and traditionally accomplished by using either free-electron radiation, optical lasers, Gunn diodes or fundamental oscillation by using III-V based HBT/HEMT technology[1-3]... We have substantially extended the operation range of deep-scaled CMOS by using a linear superimposition method, in which we have realized a 324GHz VCO in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage. This may also pave the way for ultra-high data rate wireless communications beyond that of IEEE 802.15.3c and reach data rates comparable to that of fiber optical communications, such as OC768 (40Gbps) and beyond.

  13. Integrated CMOS amplifier for ENG signal recording.

    PubMed

    Uranga, A; Navarro, X; Barniol, N

    2004-12-01

    The development and in vivo test of a fully integrated differential CMOS amplifier, implemented with standard 0.7-microm CMOS technology (one poly, two metals, self aligned twin-well CMOS process) intended to record extracellular neural signals is described. In order to minimize the flicker noise generated by the CMOS circuitry, a chopper technique has been chosen. The fabricated amplifier has a gain of 74 dB, a bandwidth of 3 kHz, an input noise of 6.6 nV/(Hz)0.5, a power dissipation of 1.3 mW, and the active area is 2.7 mm2. An ac coupling has been used to adapt the electrode to the amplifier circuitry for the in vivo testing. Compound muscle action potentials, motor unit action potentials, and compound nerve action potentials have been recorded in acute experiments with rats, in order to validate the amplifier. PMID:15605867

  14. CMOS Detector Technology

    NASA Astrophysics Data System (ADS)

    Hoffman, Alan; Loose, Markus; Suntharalingam, Vyshnavi

    2005-01-01

    An entry level overview of state-of-the-art CMOS detector technology is presented. Operating principles and system architecture are explained in comparison to the well-established CCD technology, followed by a discussion of important benefits of modern CMOS-based detector arrays. A number of unique CMOS features including different shutter modes and scanning concepts are described. In addition, sub-field stitching is presented as a technique for producing very large imagers. After a brief introduction to the concept of monolithic CMOS sensors, hybrid detectors technology is introduced. A comparison of noise reduction methods for CMOS hybrids is presented. The final sections review CMOS fabrication processes for monolithic and vertically integrated image sensors.

  15. A scalable neural chip with synaptic electronics using CMOS integrated memristors.

    PubMed

    Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

    2013-09-27

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

  16. CAOS-CMOS camera.

    PubMed

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

  17. CAOS-CMOS camera.

    PubMed

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems. PMID:27410361

  18. DFM in practice: results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90-nm FPGA chip

    NASA Astrophysics Data System (ADS)

    Yu, Chun-Chi; Shieh, Ming-Feng; Liu, Erick; Lin, Benjamin; Lin, Henry; Chacko, Manoj; Li, Xiaoyang; Lei, Wen-Kang; Ho, Jonathan; Wu, Xin

    2005-05-01

    At the sub 90nm nodes, resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential steps in the post-physical verification 'Mask Synthesis' process and a key component of design for manufacturing (DFM). Several studies have been conducted and the results have been published on the implication and application of the different types of RETs on mask printability and costs. More specifically, double-exposure-based, dark-field, alternating PSM (Alt-PSM) technology has received lot of attention with respect to the mask manufacturing challenges and its implementation into a production flow, despite its yield and critical dimension (CD) control superiority. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a matured, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. What follows is an in-depth review of the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

  19. Hematite nanoparticles larger than 90 nm show no sign of toxicity in terms of lactate dehydrogenase release, nitric oxide generation, apoptosis, and comet assay in murine alveolar macrophages and human lung epithelial cells.

    PubMed

    Freyria, Francesca Stefania; Bonelli, Barbara; Tomatis, Maura; Ghiazza, Mara; Gazzano, Elena; Ghigo, Dario; Garrone, Edoardo; Fubini, Bice

    2012-04-16

    Three hematite samples were synthesized by precipitation from a FeCl₃ solution under controlled pH and temperature conditions in different morphology and dimensions: (i) microsized (average diameter 1.2 μm); (ii) submicrosized (250 nm); and (iii) nanosized (90 nm). To gain insight into reactions potentially occurring in vivo at the particle-lung interface following dust inhalation, several physicochemical features relevant to pathogenicity were measured (free radical generation in cell-free tests, metal release, and antioxidant depletion), and cellular toxicity assays on human lung epithelial cells (A549) and murine alveolar macrophages (MH-S) were carried out (LDH release, apoptosis detection, DNA damage, and nitric oxide synthesis). The decrease in particles size, from 1.2 μm to 90 nm, only caused a slight increase in structural defects (disorder of the hematite phase and the presence of surface ferrous ions) without enhancing surface reactivity or cellular responses in the concentration range between 20 and 100 μg cm⁻².

  20. Hematite nanoparticles larger than 90 nm show no sign of toxicity in terms of lactate dehydrogenase release, nitric oxide generation, apoptosis, and comet assay in murine alveolar macrophages and human lung epithelial cells.

    PubMed

    Freyria, Francesca Stefania; Bonelli, Barbara; Tomatis, Maura; Ghiazza, Mara; Gazzano, Elena; Ghigo, Dario; Garrone, Edoardo; Fubini, Bice

    2012-04-16

    Three hematite samples were synthesized by precipitation from a FeCl₃ solution under controlled pH and temperature conditions in different morphology and dimensions: (i) microsized (average diameter 1.2 μm); (ii) submicrosized (250 nm); and (iii) nanosized (90 nm). To gain insight into reactions potentially occurring in vivo at the particle-lung interface following dust inhalation, several physicochemical features relevant to pathogenicity were measured (free radical generation in cell-free tests, metal release, and antioxidant depletion), and cellular toxicity assays on human lung epithelial cells (A549) and murine alveolar macrophages (MH-S) were carried out (LDH release, apoptosis detection, DNA damage, and nitric oxide synthesis). The decrease in particles size, from 1.2 μm to 90 nm, only caused a slight increase in structural defects (disorder of the hematite phase and the presence of surface ferrous ions) without enhancing surface reactivity or cellular responses in the concentration range between 20 and 100 μg cm⁻². PMID:22324577

  1. A low voltage CMOS low drop-out voltage regulator

    NASA Astrophysics Data System (ADS)

    Bakr, Salma Ali; Abbasi, Tanvir Ahmad; Abbasi, Mohammas Suhaib; Aldessouky, Mohamed Samir; Abbasi, Mohammad Usaid

    2009-05-01

    A low voltage implementation of a CMOS Low Drop-Out voltage regulator (LDO) is presented. The requirement of low voltage devices is crucial for portable devices that require extensive computations in a low power environment. The LDO is implemented in 90nm generic CMOS technology. It generates a fixed 0.8V from a 2.5V supply which on discharging goes to 1V. The buffer stage used is unity gain configured unbuffered OpAmp with rail-to-rail swing input stage. The simulation result shows that the implemented circuit provides load regulation of 0.004%/mA and line regulation of -11.09mV/V. The LDO provides full load transient response with a settling time of 5.2μs. Further, the dropout voltage is 200mV and the quiescent current through the pass transistor (Iload=0) is 20μA. The total power consumption of this LDO (excluding bandgap reference) is only 80μW.

  2. Single photon detection and localization accuracy with an ebCMOS camera

    NASA Astrophysics Data System (ADS)

    Cajgfinger, T.; Dominjon, A.; Barbier, R.

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 μm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  3. Regenerative switching CMOS system

    DOEpatents

    Welch, James D.

    1998-01-01

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

  4. Regenerative switching CMOS system

    DOEpatents

    Welch, J.D.

    1998-06-02

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

  5. Reconfigurable RF CMOS Circuit for Cognitive Radio

    NASA Astrophysics Data System (ADS)

    Masu, Kazuya; Okada, Kenichi

    Cognitive radio and/or SDR (Software Defined Radio) inherently requires multi-band and multi standard wireless circuit. The circuit is implemented based on Si CMOS technology. In this article, the recent progress of Si RF CMOS is described and the reconfigurable RF CMOS circuit which was proposed by the authors is introduced. At the present and in the future, several kind of Si CMOS technology can be used for RF CMOS circuit implementation. The realistic RF CMOS circuit implementation toward cognitive and/or SDR is discussed.

  6. Large area CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; Guerrini, N.; Sedgwick, I.

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  7. CMOS Integrated Carbon Nanotube Sensor

    SciTech Connect

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-05-23

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  8. CMOS digital pixel sensors: technology and applications

    NASA Astrophysics Data System (ADS)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  9. Adapt

    NASA Astrophysics Data System (ADS)

    Bargatze, L. F.

    2015-12-01

    Active Data Archive Product Tracking (ADAPT) is a collection of software routines that permits one to generate XML metadata files to describe and register data products in support of the NASA Heliophysics Virtual Observatory VxO effort. ADAPT is also a philosophy. The ADAPT concept is to use any and all available metadata associated with scientific data to produce XML metadata descriptions in a consistent, uniform, and organized fashion to provide blanket access to the full complement of data stored on a targeted data server. In this poster, we present an application of ADAPT to describe all of the data products that are stored by using the Common Data File (CDF) format served out by the CDAWEB and SPDF data servers hosted at the NASA Goddard Space Flight Center. These data servers are the primary repositories for NASA Heliophysics data. For this purpose, the ADAPT routines have been used to generate data resource descriptions by using an XML schema named Space Physics Archive, Search, and Extract (SPASE). SPASE is the designated standard for documenting Heliophysics data products, as adopted by the Heliophysics Data and Model Consortium. The set of SPASE XML resource descriptions produced by ADAPT includes high-level descriptions of numerical data products, display data products, or catalogs and also includes low-level "Granule" descriptions. A SPASE Granule is effectively a universal access metadata resource; a Granule associates an individual data file (e.g. a CDF file) with a "parent" high-level data resource description, assigns a resource identifier to the file, and lists the corresponding assess URL(s). The CDAWEB and SPDF file systems were queried to provide the input required by the ADAPT software to create an initial set of SPASE metadata resource descriptions. Then, the CDAWEB and SPDF data repositories were queried subsequently on a nightly basis and the CDF file lists were checked for any changes such as the occurrence of new, modified, or deleted

  10. Development of CMOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  11. High-voltage CMOS detectors

    NASA Astrophysics Data System (ADS)

    Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

    2016-07-01

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented.

  12. CMOS output buffer wave shaper

    NASA Technical Reports Server (NTRS)

    Albertson, L.; Whitaker, S.; Merrell, R.

    1990-01-01

    As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. A design technique which aids in the reduction of switching noise is reported. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driver stage. A test circuit based on these techniques is being submitted to MOSIS for fabrication.

  13. Using CMOS image sensors to detect photons

    NASA Astrophysics Data System (ADS)

    Xu, Chenzhi; Tong, Xiaobo; Zhou, Xiang; Zheng, Xiaodong; Xu, Yunfei

    2010-05-01

    A research is carried out on the characteristics of CMOS (Complementary Metal-Oxide Semiconductor) image sensors. A CMOS image sensor is used to probe the fluorescence intensity of atoms or absorbed photons in order to measure the shape and atomicity density of Rb (Rubidium) cold-atom-cloud. A series of RGB data of images is obtained and the spectrum response curve of CMOS image sensor is deduced. After filtering out the noise of the pixel signals of CMOS image sensor, the number of photons received by every pixel of the CMOS image sensor is obtained. Compared with CCD camera, the CMOS image sensor has some advantages in measuring the properties of cold-atom-cloud,such as quick response, large sensory area, low cost, and so on.

  14. Fabrication of CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Malinovich, Yacov; Koltin, Ephie; Choen, David; Shkuri, Moshe; Ben-Simon, Meir

    1999-04-01

    In order to provide its customers with sub-micron CMOS fabrication solutions for imaging applications, Tower Semiconductor initiated a project to characterize the optical parameters of Tower's 0.5-micron process. A special characterization test chip was processed using the TS50 process. The results confirmed a high quality process for optical applications. Perhaps the most important result is the process' very low dark current, of 30-50 pA/cm2, using the entire window of process. This very low dark current characteristic was confirmed for a variety of pixel architectures. Additionally, we have succeeded to reduce and virtually eliminate the white spots on large sensor arrays. As a foundry Tower needs to support fabrication of many different imaging products. Therefore we have developed a fabrication methodology that is adjusted to the special needs of optical applications. In order to establish in-line process monitoring of the optical parameters, Tower places a scribe line optical test chip that enables wafer level measurements of the most important parameters, ensuring the optical quality and repeatability of the process. We have developed complementary capabilities like in house deposition of color filter and fabrication of very large are dice using sub-micron CMOS technologies. Shellcase and Tower are currently developing a new CMOS image sensor optical package.

  15. Nanosecond monolithic CMOS readout cell

    DOEpatents

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  16. CMOS foveal image sensor chip

    NASA Technical Reports Server (NTRS)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  17. Accelerated life testing effects on CMOS microcircuit characteristics

    NASA Technical Reports Server (NTRS)

    1977-01-01

    Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

  18. Spectrometry with consumer-quality CMOS cameras.

    PubMed

    Scheeline, Alexander

    2015-01-01

    Many modern spectrometric instruments use diode arrays, charge-coupled arrays, or CMOS cameras for detection and measurement. As portable or point-of-use instruments are desirable, one would expect that instruments using the cameras in cellular telephones and tablet computers would be the basis of numerous instruments. However, no mass market for such devices has yet developed. The difficulties in using megapixel CMOS cameras for scientific measurements are discussed, and promising avenues for instrument development reviewed. Inexpensive alternatives to use of the built-in camera are also mentioned, as the long-term question is whether it is better to overcome the constraints of CMOS cameras or to bypass them.

  19. Nuclear magnetic resonance imaging with 90-nm resolution.

    PubMed

    Mamin, H J; Poggio, M; Degen, C L; Rugar, D

    2007-05-01

    Magnetic resonance imaging (MRI) is a powerful imaging technique that typically operates on the scale of millimetres to micrometres. Conventional MRI is based on the manipulation of nuclear spins with radio-frequency fields, and the subsequent detection of spins with induction-based techniques. An alternative approach, magnetic resonance force microscopy (MRFM), uses force detection to overcome the sensitivity limitations of conventional MRI. Here, we show that the two-dimensional imaging of nuclear spins can be extended to a spatial resolution better than 100 nm using MRFM. The imaging of 19F nuclei in a patterned CaF(2) test object was enabled by a detection sensitivity of roughly 1,200 nuclear spins at a temperature of 600 mK. To achieve this sensitivity, we developed high-moment magnetic tips that produced field gradients up to 1.4 x 10(6) T m(-1), and implemented a measurement protocol based on force-gradient detection of naturally occurring spin fluctuations. The resulting detection volume was less than 650 zeptolitres. This is 60,000 times smaller than the previous smallest volume for nuclear magnetic resonance microscopy, and demonstrates the feasibility of pushing MRI into the nanoscale regime.

  20. Integration hybride de transistors a un electron sur un noeud technologique CMOS

    NASA Astrophysics Data System (ADS)

    Jouvet, Nicolas

    This study deals with the hybrid integration of single electron transistors (SET) on a CMOS technology nod. SET devices possess a high potential, especially regarding energy efficiency, but aren't fit to completely replace CMOS components in electrical circuits. However, this problem can be solved through hybrid combination of SETs and MOS, leading to very low operating power circuits, and high integration density. This thesis investigates the use of the nanodamascene process, developed by C. Dubuc, for back-end-of-line (BEOL) SET fabrication, meaning creation of SETs in the oxide encapsulating CMOS devices. The assets the nanodamascene process presents are quite interesting: fabrication of SETs with a large operation margin, high repeatability, and potential for BEOL fabrication. This last point, in particular, makes this process promising. Indeed, it opens the path to the fabrication of numerous layers of SETs, stacked one upon the other, and forming 3D circuits, created on top of 2D CMOS layer. Thus a high gain to existing CMOS wafers could be generated. Devices created through the use of the nanodamascene process, adapted for BEOL SET fabrication, are presented. Limits and improvement perspectives of the technique's transfer are discussed. Electrical characterizations of the devices are also presented. They have demonstrated the created devices functionality, thus validating the successful adaption of the nanodamascene process. They have also allowed for the identification of numerous traps located at the heart of fabricated devices. Fabricated SET devices potential for hybrid SET-CMOS circuits was studied through simulations. Possible architectures showing good potential for early hybrid circuits' realization were identified. Keywords: MOSFET, single electron transistor (SET), nanotechnology, microfabrication, nanodamascene, electrical characterization.

  1. Optical hybrid package with an 8-channel 18GT/s CMOS transceiver for chip-to-chip optical interconnect

    NASA Astrophysics Data System (ADS)

    Mohammed, E.; Liao, J.; Kern, A.; Lu, D.; Braunisch, H.; Thomas, T.; Hyvonen, S.; Palermo, S.; Young, I. A.

    2008-02-01

    We describe the design and development of a high-speed 8-channel hybrid integrated optical transceiver package with Clock and Data Recovery (CDR) circuits. The package concept has been developed to be compatible with microprocessor package technology and at the same time allow the integration of low cost, high-performance optical components. A 90nm CMOS optical transceiver chip, 850nm 10Gb/s GaAs based vertical cavity surface emitting laser (VCSEL) array and PIN photodiode array are flip-chip mounted on a standard microprocessor Land Grid Array (LGA) package substrate. The CMOS drivers and receivers on the transceiver chip and the optical components (VCSEL and Photodiode arrays) are electrically coupled using a short transmission line routed on the top surface of the package. VCSEL and photodiode arrays are optically coupled to on-package integrated polymer waveguide arrays with metallized 45° mirrors. The waveguides, which are terminated with multi-terminal (MT) fiber optic connectors, couple out/in high-speed optical signals to/from the chip. The CMOS transceiver chip fully integrates all analog optical circuits such as VCSEL drivers, transimpedance amplifiers and clock and data recovery (CDR) retiming circuit with a low jitter LC-PLL. Digital circuits for pseudorandom bit-pattern sequence generators (PRBS) and bit-error rate test (BERT) are fully integrated. 20Gb/s electrical and 18Gb/s optical eye diagrams for the transmitter were measured out of the package. A fully packaged transmitter and receiver including clock data recovery at 10Gb/s have also been measured.

  2. SOI CMOS Imager with Suppression of Cross-Talk

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

    2009-01-01

    A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

  3. Fundamental study on identification of CMOS cameras

    NASA Astrophysics Data System (ADS)

    Kurosawa, Kenji; Saitoh, Naoki

    2003-08-01

    In this study, we discussed individual camera identification of CMOS cameras, because CMOS (complementary-metal-oxide-semiconductor) imaging detectors have begun to make their move into the CCD (charge-coupled-device) fields for recent years. It can be identified whether or not the given images have been taken with the given CMOS camera by detecting the imager's intrinsic unique fixed pattern noise (FPN) just like the individual CCD camera identification method proposed by the authors. Both dark and bright pictures taken with the CMOS cameras can be identified by the method, because not only dark current in the photo detectors but also MOS-FET amplifiers incorporated in each pixel may produce pixel-to-pixel nonuniformity in sensitivity. Each pixel in CMOS detectors has the amplifier, which degrades image quality of bright images due to the nonuniformity of the amplifier gain. Two CMOS cameras were evaluated in our experiments. They were WebCamGoPlus (Creative), and EOS D30 (Canon). WebCamGoPlus is a low-priced web camera, whereas EOS D30 is for professional use. Image of a white plate were recorded with the cameras under the plate's luminance condition of 0cd/m2 and 150cd/m2. The recorded images were multiply integrated to reduce the random noise component. From the images of both cameras, characteristic dots patterns were observed. Some bright dots were observed in the dark images, whereas some dark dots were in the bright images. The results show that the camera identification method is also effective for CMOS cameras.

  4. New package for CMOS sensors

    NASA Astrophysics Data System (ADS)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  5. Future of nano CMOS technology

    NASA Astrophysics Data System (ADS)

    Iwai, Hiroshi

    2015-10-01

    Although Si MOS devices have dominated the integrated circuit applications over the four decades, it has been anticipated that the development of CMOS would reach its limits after the next decade because of the difficulties in the technologies for further downscaling and also because of some fundamental limits of MOSFETs. However, there have been no promising candidates yet, which can replace Si MOSFETs with better performance with low cost. Thus, for the moment, it seems that we have to stick to the Si MOSFET devices until their end. The downsizing is limited by the increase of off-leakage current between source and drain. In order to suppress the off-leakage current, multi-gate structures (FinFET, Tri-gate, and Si-nanowire MOSFETs) are replacing conventional planar MOSFETs, and continuous innovation of high-k/metal gate technologies has enabled EOT scaling down to 0.9 nm in production. However, it was found that the multi-gate structures have a future big problem of significant conduction reduction with decrease in fin width. Also it is not easy to further decrease EOT because of the mobility and reliability degradation. Furthermore, the development of EUV (Extremely Ultra-Violet) lithography, which is supposed to be essential for sub-10 nm lithography, delays significantly because of insufficient illumination intensity for production. Thus, it is now expected that the reduction rate of the gate length, which has a strong influence on the off-leakage current, will become slower in near future.

  6. CMOS prototype for retinal prosthesis applications with analog processing

    NASA Astrophysics Data System (ADS)

    Castillo-Cabrera, G.; García-Lamont, J.; Reyes-Barranca, M. A.; Matsumoto-Kuwabara, Y.; Moreno-Cadenas, J. A.; Flores-Nava, L. M.

    2014-12-01

    A core architecture for analog processing, which emulates a retina's receptive field, is presented in this work. A model was partially implemented and built on CMOS standard technology through MOSIS. It considers that the receptive field is the basic unit for image processing in the visual system. That is why the design is concerned on a partial solution of receptive field properties in order to be adapted in the future as an aid to people with retinal diseases. A receptive field is represented by an array of 3×3 pixels. Each pixel carries out a process based on four main operations. This means that image processing is developed at pixel level. Operations involved are: (1) photo-transduction by photocurrent integration, (2) signal averaging from eight neighbouring pixels executed by a neu-NMOS (ν-NMOS) neuron, (3) signal average gradient between central pixel and the average value from the eight neighbouring pixels (this gradient is performed by a comparator) and finally (4) a pulse generator. Each one of these operations gives place to circuital blocks which were built on 0.5 μm CMOS technology.

  7. Characterization and reliability of CMOS microstructures

    NASA Astrophysics Data System (ADS)

    Fedder, Gary K.; Blanton, Ronald D. S.

    1999-08-01

    This paper provides an overview of high-aspect-ratio CMOS micromachining, focusing on materials characterization, reliability, and fault analysis. Composite microstrutural beam widths and gaps down to 1.2 micrometers are etched out of conventional CMOS dielectric, aluminum, and gate-polysilicon thin films using post-CMOS dry etching for both structural sidewall definition and for release from the substrate. Differences in stress between the multiple metal and dielectric layers cause vertical stress gradients and curl, while misalignment between layers causes lateral stress gradients and curl. Cracking is induced in a resonant fatigue structures at 620 MPa of repetitive stress after over 50 million cycles. Beams have withstood over 1.3 billion cycles at 124 MPa stress levels induced by electrostatic actuation. Failures due to process defects are classified according to the geometrical features of the defective structures. Relative probability of occurrence of each defect type is extracted from the process simulation results.

  8. Nanopore-CMOS Interfaces for DNA Sequencing.

    PubMed

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-01-01

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces. PMID:27509529

  9. Nanopore-CMOS Interfaces for DNA Sequencing

    PubMed Central

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-01-01

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces. PMID:27509529

  10. High-temperature Complementary Metal Oxide Semiconductors (CMOS)

    NASA Technical Reports Server (NTRS)

    Mcbrayer, J. D.

    1981-01-01

    The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

  11. Low power, CMOS digital autocorrelator spectrometer for spaceborne applications

    NASA Technical Reports Server (NTRS)

    Chandra, Kumar; Wilson, William J.

    1992-01-01

    A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

  12. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    NASA Technical Reports Server (NTRS)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  13. End-of-fabrication CMOS process monitor

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

    1990-01-01

    A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

  14. Optical addressing technique for a CMOS RAM

    NASA Technical Reports Server (NTRS)

    Wu, W. H.; Bergman, L. A.; Allen, R. A.; Johnston, A. R.

    1988-01-01

    Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

  15. Radiation Tolerance of 65nm CMOS Transistors

    DOE PAGES

    Krohn, M.; Bentele, B.; Christian, D. C.; Cumalat, J. P.; Deptuch, G.; Fahim, F.; Hoff, J.; Shenai, A.; Wagner, S. R.

    2015-12-11

    We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately -20°C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  16. SEU hardening of CMOS memory circuit

    NASA Technical Reports Server (NTRS)

    Whitaker, S.; Canaris, J.; Liu, K.

    1990-01-01

    This paper reports a design technique to harden CMOS memory circuits against Single Event Upset (SEU) in the space environment. A RAM cell and Flip Flop design are presented to demonstrate the method. The Flip Flop was used in the control circuitry for a Reed Solomon encoder designed for the Space Station.

  17. Design and realization of CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Xu, Jian; Xiao, Zexin

    2008-02-01

    A project was presented that instrumental design of an economical CMOS microscope image sensor. A high performance, low price, black-white camera chip OV5116P was used as the core of the sensor circuit; Designing and realizing peripheral control circuit of sensor; Through the control on dial switch to realize different functions of the sensor chip in the system. For example: auto brightness level descending function on or off; gamma correction function on or off; auto and manual backlight compensation mode conversion and so on. The optical interface of sensor is designed for commercialization and standardization. The images of sample were respectively gathered with CCD and CMOS. Result of the experiment indicates that both performances were identical in several aspects as follows: image definition, contrast control, heating degree and the function can be adjusted according to the demand of user etc. The imperfection was that the CMOS with smaller field and higher noise than CCD; nevertheless, the maximal advantage of choosing the CMOS chip is its low cost. And its imaging quality conformed to requirement of the economical microscope image sensor.

  18. Fully CMOS-compatible titanium nitride nanoantennas

    NASA Astrophysics Data System (ADS)

    Briggs, Justin A.; Naik, Gururaj V.; Petach, Trevor A.; Baum, Brian K.; Goldhaber-Gordon, David; Dionne, Jennifer A.

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  19. Low energy CMOS for space applications

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Alkalaj, Leon

    1992-01-01

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  20. CMOS preamplifiers for detectors large and small

    SciTech Connect

    O`Connor, P.

    1997-12-31

    We describe four CMOS preamplifiers developed for multiwire proportional chambers (MWPC) and silicon drift detectors (SDD) covering a capacitance range from 150 pF to 0.15 pF. Circuit techniques to optimize noise performance, particularly in the low-capacitance regime, are discussed.

  1. Improving CMOS-compatible Germanium photodetectors.

    PubMed

    Li, Guoliang; Luo, Ying; Zheng, Xuezhe; Masini, Gianlorenzo; Mekis, Attila; Sahni, Subal; Thacker, Hiren; Yao, Jin; Shubin, Ivan; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

    2012-11-19

    We report design improvements for evanescently coupled Germanium photodetectors grown at low temperature. The resulting photodetectors with 10 μm Ge length manufactured in a commercial CMOS process achieve >0.8 A/W responsivity over the entire C-band, with a device capacitance of <7 fF based on measured data.

  2. A fail-safe CMOS logic gate

    NASA Technical Reports Server (NTRS)

    Bobin, V.; Whitaker, S.

    1990-01-01

    This paper reports a design technique to make Complex CMOS Gates fail-safe for a class of faults. Two classes of faults are defined. The fail-safe design presented has limited fault-tolerance capability. Multiple faults are also covered.

  3. Low-Power SOI CMOS Transceiver

    NASA Technical Reports Server (NTRS)

    Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

    2003-01-01

    The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS

  4. CMOS MEMS capacitive absolute pressure sensor

    NASA Astrophysics Data System (ADS)

    Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

    2013-05-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

  5. Development of a radiation hardened npn bipolar transistor for a 64K CMOS fusible-link PROM

    SciTech Connect

    Fuller, R.; Newman, W. )

    1994-12-01

    A 1.2 [mu]m CMOS production process was adapted to produce a 64K CMOS fusible-link Programmable Read-Only Memory (PROM) for space applications. The circuit requirement of less than 50 nS access time combined with the need for 9 volt single pulse programming of the fusible links and radiation tolerance to levels over 300 Krad(Si) made close collaboration between design engineering, reliability engineering, and device engineering essential for a successful project. A vertical NPN bipolar transistor was integrated into a standard CMOS process to be used for programming and reading the fuses. The device characteristics were carefully matched to the product speed and programmability requirements. The NPN device was optimized for radiation performances. Successful development required extensive use of process and device modeling, test structure design and measurement, and experimental design methods.

  6. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    PubMed Central

    Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

  7. Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

    PubMed

    Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

  8. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    PubMed

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-01

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

  9. A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT switch

    NASA Astrophysics Data System (ADS)

    Zonghua, Zheng; Lingling, Sun; Jun, Liu; Shengzhou, Zhang

    2016-01-01

    A novel loss compensation technique for a series-shunt single-pole double-throw (SPDT) switch is presented operating in the 60 GHz. The feed-forward compensation network which is composed of an NMOS, a couple capacitance and a shunt inductance can reduce the impact of the feed forward capacitance to reduce the insertion loss and improve the isolation of the SPDT switch. The measured insertion loss and isolation characteristics of the switch somewhat deviating from the 60 GHz are analyzed revealing that the inaccuracy of the MOS model can greatly degrade the performance of the switch. The switch is implemented in TSMC 90-nm CMOS process and exhibits an isolation of above 27 dB at transmitter mode, and the insertion loss of 1.8-3 dB at 30-65 GHz by layout simulation. The measured insertion loss is 2.45 dB at 52 GHz and keeps < 4 dB at 30-64 GHz. The measured isolation is better than 25 dB at 30-64 GHz and the measured return loss is better than 10 dB at 30-65 GHz. A measured input 1 dB gain compression point of the switch is 13 dBm at 52 GHz and 15 dBm at 60 GHz. The simulated switching speed with rise time and fall time are 720 and 520 ps, respectively. The active chip size of the proposed switch is 0.5 × 0.95 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61331006, 61372021).

  10. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    PubMed

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-30

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

  11. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

    PubMed Central

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-01

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

  12. PALM and STORM: Into large fields and high-throughput microscopy with sCMOS detectors.

    PubMed

    Almada, Pedro; Culley, Siân; Henriques, Ricardo

    2015-10-15

    Single Molecule Localization Microscopy (SMLM) techniques such as Photo-Activation Localization Microscopy (PALM) and Stochastic Optical Reconstruction Microscopy (STORM) enable fluorescence microscopy super-resolution: the overcoming of the resolution barrier imposed by the diffraction of light. These techniques are based on acquiring hundreds or thousands of images of single molecules, locating them and reconstructing a higher-resolution image from the high-precision localizations. These methods generally imply a considerable trade-off between imaging speed and resolution, limiting their applicability to high-throughput workflows. Recent advancements in scientific Complementary Metal-Oxide Semiconductor (sCMOS) camera sensors and localization algorithms reduce the temporal requirements for SMLM, pushing it toward high-throughput microscopy. Here we outline the decisions researchers face when considering how to adapt hardware on a new system for sCMOS sensors with high-throughput in mind. PMID:26079924

  13. Cmos spdt switch for wlan applications

    NASA Astrophysics Data System (ADS)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  14. Advanced CMOS Radiation Effects Testing Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  15. Advanced CMOS Radiation Effects Testing and Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  16. CMOS Camera Array With Onboard Memory

    NASA Technical Reports Server (NTRS)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  17. Radiation effects on scientific CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Yuanfu, Zhao; Liyan, Liu; Xiaohui, Liu; Xiaofeng, Jin; Xiang, Li

    2015-11-01

    A systemic solution for radiation hardened design is presented. Besides, a series of experiments have been carried out on the samples, and then the photoelectric response characteristic and spectral characteristic before and after the experiments have been comprehensively analyzed. The performance of the CMOS image sensor with the radiation hardened design technique realized total-dose resilience up to 300 krad(Si) and resilience to single-event latch up for LET up to 110 MeV·cm2/mg.

  18. CMOS-array design-automation techniques

    NASA Technical Reports Server (NTRS)

    Feller, A.; Lombardt, T.

    1979-01-01

    Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

  19. Radiation characteristics of scintillator coupled CMOS APS for radiography conditions

    NASA Astrophysics Data System (ADS)

    Kim, Kwang Hyun; Kim, Soongpyung; Kang, Dong-Won; Kim, Dong-Kie

    2006-11-01

    Under industrial radiography conditions, we analyzed short-term radiation characteristics of scintillator coupled CMOS APS (hereinafter SC CMOS APS). By means of experimentation, the contribution of the transmitted X-ray through the scintillator to the properties of the CMOS APS and the afterimage, generated in the acquired image even at low dose condition, were investigated. To see the transmitted X-ray effects on the CMOS APS, Fein focus™ X-ray machine, two scintillators of Lanex™ Fine and Regular, and two CMOS APS array of RadEye™ were used under the conditions of 50 kV p/1 mAs and 100 kV p/1 mAs. By measuring the transmitted X-ray on signal and Noise Power Spectrum, we analytically examined the generation mechanism of the afterimage, based on dark signal or dark current increase in the sensor, and explained the afterimage in the SC CMOS APS.

  20. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    PubMed

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-01-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

  1. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    PubMed

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-11-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

  2. Current-mode CMOS hybrid image sensor

    NASA Astrophysics Data System (ADS)

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several

  3. A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

    NASA Astrophysics Data System (ADS)

    Schmitz, A.; Tielert, R.

    2005-05-01

    Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

  4. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  5. Failures of CMOS Circuits Irradiated At Low Rates

    NASA Technical Reports Server (NTRS)

    Goben, Charles A.; Price, William E.

    1990-01-01

    Report describes experiments on irradiation of SGS 4007 complementary metal oxide/semiconductor (CMOS) integrated inverter circuits by 60Co and 137Cs radioactive sources. Purpose of experiments to supplement previous observations that minimum radiation doses at which failure occurred in more-complicated CMOS parts were lower at lower dose rates.

  6. Vertical Isolation for Photodiodes in CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2008-01-01

    In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

  7. Monolithic CMOS imaging x-ray spectrometers

    NASA Astrophysics Data System (ADS)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

  8. Design of high speed camera based on CMOS technology

    NASA Astrophysics Data System (ADS)

    Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

    2007-12-01

    The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

  9. Organic Field-Effect Transistors for CMOS Devices

    NASA Astrophysics Data System (ADS)

    Melzer, Christian; von Seggern, Heinz

    Organic field-effect transistors (OFETs) are the key elements of future low cost electronics such as radio frequency identification tags. In order to take full advantage of organic electronics, low power consumption is mandatory, requiring the use of a complementary metal oxide semiconductor (CMOS) like technique. To realize CMOS-devices p-type and n-type organic field-effect transistors on one substrate have to be provided. Here, the latest concepts to produce in a straightforward way complementary acting OFETs for CMOS-like elements are illustrated on basis of the inverter. Starting from a simple description of thin-film transistors, the basic design rules for the development of complementary OFETs are given and some realizations of CMOS-like inverters are discussed. A CMOS-like inverter based on two identical field-effect transistors disclosing almost unipolar p-type and n-type behavior is presented.

  10. A CMOS high speed imaging system design based on FPGA

    NASA Astrophysics Data System (ADS)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  11. Real-time reconfigurable subthreshold CMOS perceptron.

    PubMed

    Aunet, S; Oelmann, B; Norseng, P A; Berg, Y

    2008-04-01

    In this paper, a new, real-time reconfigurable perceptron circuit element is presented. A six-transistor version used as a threshold gate, having a fan-in of three, producing adequate outputs for threshold of T =1, 2 and 3 is demonstrated by chip measurements. Subthreshold operation for supply voltages in the range of 100-350 mV is shown. The circuit performs competitively with a standard static complimentary metal-oxide-semiconductor (CMOS) implementation when maximum speed and energy delay product are taken into account, when used in a ring oscillator. Functionality per transistor is, to our knowledge, the highest reported for a variety of comparable circuits not based on floating gate techniques. Statistical simulations predict probabilities for making working circuits under mismatch and process variations. The simulations, in 120-nm CMOS, also support discussions regarding lower limits to supply voltage and redundancy. A brief discussion on how the circuit may be exploited as a basic building block for future defect tolerant mixed signal circuits, as well as neural networks, exploiting redundancy, is included.

  12. Modulated CMOS camera for fluorescence lifetime microscopy.

    PubMed

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition. PMID:26500051

  13. Challenges of nickel silicidation in CMOS technologies

    SciTech Connect

    Breil, Nicolas; Lavoie, Christian; Ozcan, Ahmet; Baumann, Frieder; Klymko, Nancy; Nummy, Karen; Sun, Bing; Jordan-Sweet, Jean; Yu, Jian; Zhu, Frank; Narasimha, Shreesh; Chudzik, Michael

    2015-04-01

    In our paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g.SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of the nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. Furthermore, we investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (1 0 0) and (1 1 1) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni–Pt–Si–Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.

  14. The 1.2 micron CMOS technology

    NASA Technical Reports Server (NTRS)

    Pina, C. A.

    1985-01-01

    A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.

  15. Modulated CMOS camera for fluorescence lifetime microscopy.

    PubMed

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition.

  16. A built-in SRAM for radiation hard CMOS pixel sensors dedicated to high energy physics experiments

    NASA Astrophysics Data System (ADS)

    Wei, Xiaomin; Gao, Deyuan; Doziere, Guy; Hu, Yann

    2013-02-01

    CMOS pixel sensors (CPS) are attractive candidates for charged particle tracking in high energy physics experiments. However, CPS chips fabricated with standard CMOS processes, especially the built-in SRAM IP cores, are not radiation hard enough for this application. This paper presents a radiation hard SRAM for improving the CPS radiation tolerance. The SRAM cell is hardened by increasing the static noise margin (SNM) and adding P+ guard rings in layout. The peripheral circuitry is designed by building a radiation-hardened logic library. The SRAM internal timing control is hardened by a self-adaptive timing design. Finally, the SRAM design was implemented and tested in the Austriamicrosystems (AMS) 0.35 μm standard CMOS process. The prototype chips are adapted to work with frequencies up to 80 MHz, power supply voltages from 2.9 V to 3.3 V and temperatures from 0 °C to 60 °C. The single event latchup (SEL) tolerance is improved from 5.2 MeV cm2/mg to above 56 MeV cm2/mg. The total ionizing dose (TID) tolerance is enhanced by the P+ guard rings and the self-adaptive timing design. The single event upset (SEU) effects are also alleviated due to the high SNM SRAM cell and the P+ guard rings. In the near future, the presented SRAM will be integrated in the CPS chips for the STAR experiments.

  17. Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications

    PubMed Central

    Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

    2012-01-01

    One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

  18. All-CMOS night vision viewer with integrated microdisplay

    NASA Astrophysics Data System (ADS)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  19. Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

    2008-01-01

    Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

  20. A monolithically integrated torsional CMOS-MEMS relay

    NASA Astrophysics Data System (ADS)

    Riverola, M.; Sobreviela, G.; Torres, F.; Uranga, A.; Barniol, N.

    2016-11-01

    We report experimental demonstrations of a torsional microelectromechanical (MEM) relay fabricated using the CMOS-MEMS approach (or intra-CMOS) which exploits the full foundry inherent characteristics enabling drastic reduction of the fabrication costs and batch production. In particular, the relay is monolithically integrated in the back end of line of a commercial standard CMOS technology (AMS 0.35 μm) and released by means of a simple one-step mask-less wet etching. The fabricated torsional relay exhibits an extremely steep switching behaviour symmetrical about both contact sides with an on-state contact resistance in the k Ω -range throughout the on-off cycling test.

  1. 1984 Joint Congress: CGU and CMOS

    NASA Astrophysics Data System (ADS)

    Camfield, P. A.

    The Canadian Geophysical Union (CGU) had a very successful joint meeting with the Canadian Meteorological and Oceanographic Society (CMOS) at Dalhousie University in Halifax, Nova Scotia, May 29 to June 1, 1984. Thirty-five scientific sessions were held in the 4-day meeting period.The invited speaker for CGU at the plenary session, David Simpson of Lamont-Doherty Geological Observatory, spoke about the Halifax Explosion of 1917 in terms of a seismic event. The 2.6-kt explosion was the largest man-made explosion prior to the detonation of the first atomic bombs. The effective seismic magnitude of the event may have been m, = 2.5-3.0.

  2. Log polar image sensor in CMOS technology

    NASA Astrophysics Data System (ADS)

    Scheffer, Danny; Dierickx, Bart; Pardo, Fernando; Vlummens, Jan; Meynants, Guy; Hermans, Lou

    1996-08-01

    We report on the design, design issues, fabrication and performance of a log-polar CMOS image sensor. The sensor is developed for the use in a videophone system for deaf and hearing impaired people, who are not capable of communicating through a 'normal' telephone. The system allows 15 detailed images per second to be transmitted over existing telephone lines. This framerate is sufficient for conversations by means of sign language or lip reading. The pixel array of the sensor consists of 76 concentric circles with (up to) 128 pixels per circle, in total 8013 pixels. The interior pixels have a pitch of 14 micrometers, up to 250 micrometers at the border. The 8013-pixels image is mapped (log-polar transformation) in a X-Y addressable 76 by 128 array.

  3. CMOS imager for pointing and tracking applications

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

    2006-01-01

    Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

  4. Latchup in CMOS devices from heavy ions

    NASA Technical Reports Server (NTRS)

    Soliman, K.; Nichols, D. K.

    1983-01-01

    It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

  5. Depleted CMOS pixels for LHC proton-proton experiments

    NASA Astrophysics Data System (ADS)

    Wermes, N.

    2016-07-01

    While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

  6. Implementation of CMOS Millimeter-Wave Devices for Rotational Spectroscopy

    NASA Astrophysics Data System (ADS)

    Drouin, Brian; Tang, Adrian; Schlecht, Erich T.; Daly, Adam M.; Brageot, Emily; Gu, Qun Jane; Ye, Yu; Shu, Ran; Chang, M.-C. Frank; Kim, Rod M.

    2015-06-01

    The extension of radio-frequency CMOS circuitry into millimeter wavelengths promises the extension of spectroscopic techniques in compact, power efficient systems. We are now exploring the use of CMOS millimeter devices for low-mass, low-power instrumentation capable of remote or in-situ detection of gas composition during space missions. This effort focuses on the development of a semi-confocal Fabry-Perot cavity with mm-wavelength CMOS transmitter and receiver attached directly to a cavity coupler. Placement of the devices within the cavity structure bypasses problems encountered with signal injection and extraction in traditional cavity designs and simultaneously takes full advantage of the miniaturized form of the CMOS hardware. The presentation will provide an overview of the project and details of the accomplishments thus far, including the development and testing of a pulse modulated 83-98 GHz transmitter.

  7. Tests of commercial colour CMOS cameras for astronomical applications

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

    2013-12-01

    We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

  8. CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

    NASA Technical Reports Server (NTRS)

    Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

    2006-01-01

    This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

  9. A safety monitoring system for taxi based on CMOS imager

    NASA Astrophysics Data System (ADS)

    Liu, Zhi

    2005-01-01

    CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

  10. Improved CMOS field isolation using Germaniun/Boron implantation

    SciTech Connect

    Pfiester, J.R.; Alvis, J.R. )

    1988-08-01

    A novel germanium/boron implantation technique for improving the electrical field isolation for high-density CMOS circuits is demonstrated. Germanium implantation causes a reduction in dopant diffusion and segregation during field oxidation and is shown to increase the p-well field threshold voltage by as much as 40 percent with no significant degradation to junction or device performance. Selective germanium implantation with a blanket boron field implant can also improve the electrical field isolation behavior for CMOS circuits.

  11. CMOS front end electronics for the ATLAS muon detector

    SciTech Connect

    Huth, J.; Oliver, J.; Hazen, E.; Shank, J.

    1997-12-31

    An all-CMOS design for an integrated ASD (Amplifier-Shaper-Discriminator) chip for readout of the ATLAS Monitored Drift Tubes (MDTs) is presented. Eight channels of charge-sensitive preamp, two-stage pole/zero shaper, Wilkinson ADC and discriminator with programmable hysteresis are integrated on a single IC. Key elements have been prototyped in 1.2 and 0.5 micron CMOS operating at 5V and 3.3V respectively.

  12. Advancement of CMOS Doping Technology in an External Development Framework

    NASA Astrophysics Data System (ADS)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  13. Surface enhanced biodetection on a CMOS biosensor chip

    NASA Astrophysics Data System (ADS)

    Belloni, Federico; Sandeau, Laure; Contié, Sylvain; Vicaire, Florence; Owens, Roisin; Rigneault, Hervé

    2012-03-01

    We present a rigorous electromagnetic theory of the electromagnetic power emitted by a dipole located in the vicinity of a multilayer stack. We applied this formalism to a luminescent molecule attached to a CMOS photodiode surface and report light collection efficiency larger than 80% toward the CMOS silicon substrate. We applied this result to the development of a low-cost, simple, portable device based on CMOS photodiodes technology for the detection and quantification of biological targets through light detection, presenting high sensitivity, multiplex ability, and fast data processing. The key feature of our approach is to perform the analytical test directly on the CMOS sensor surface, improving dramatically the optical detection of the molecule emitted light into the high refractive index semiconductor CMOS material. Based on adequate surface chemistry modifications, probe spotting and micro-fluidics, we performed proof-of-concept bio-assays directed against typical immuno-markers (TNF-α and IFN-γ). We compared the developed CMOS chip with a commercial micro-plate reader and found similar intrinsic sensitivities in the pg/ml range.

  14. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    PubMed

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  15. Multiband CMOS sensor simplify FPA design

    NASA Astrophysics Data System (ADS)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  16. On noise in time-delay integration CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Levski, Deyan; Choubey, Bhaskar

    2016-05-01

    Time delay integration sensors are of increasing interest in CMOS processes owing to their low cost, power and ability to integrate with other circuit readout blocks. This paper presents an analysis of the noise contributors in current day CMOS Time-Delay-Integration image sensors with various readout architectures. An analysis of charge versus voltage domain readout modes is presented, followed by a noise classification of the existing Analog Accumulator Readout (AAR) and Digital Accumulator Readout (DAR) schemes for TDI imaging. The analysis and classification of existing readout schemes include, pipelined charge transfer, buffered direct injection, voltage as well as current-mode analog accumulators and all-digital accumulator techniques. Time-Delay-Integration imaging modes in CMOS processes typically use an N-number of readout steps, equivalent to the number of TDI pixel stages. In CMOS TDI sensors, where voltage domain readout is used, the requirements over speed and noise of the ADC readout chain are increased due to accumulation of the dominant voltage readout and ADC noise with every stage N. Until this day, the latter is the primary reason for a leap-back of CMOS TDI sensors as compared to their CCD counterparts. Moreover, most commercial CMOS TDI implementations are still based on a charge-domain readout, mimicking a CCD-like operation mode. Thus, having a good understanding of each noise contributor in the signal chain, as well as its magnitude in different readout architectures, is vital for the design of future generation low-noise CMOS TDI image sensors based on a voltage domain readout. This paper gives a quantitative classification of all major noise sources for all popular implementations in the literature.

  17. On noise in time-delay integration CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Levski, Deyan; Choubey, Bhaskar

    2016-05-01

    Time delay integration sensors are of increasing interest in CMOS processes owing to their low cost, power and ability to integrate with other circuit readout blocks. This paper presents an analysis of the noise contributors in current day CMOS Time-Delay-Integration image sensors with various readout architectures. An analysis of charge versus voltage domain readout modes is presented, followed by a noise classification of the existing Analog Accumulator Readout (AAR) and Digital Accumulator Readout (DAR) schemes for TDI imaging. The analysis and classification of existing readout schemes include, pipelined charge transfer, buffered direct injection, voltage as well as current-mode analog accumulators and all-digital accumulator techniques. Time-Delay-Integration imaging modes in CMOS processes typically use an N-number of readout steps, equivalent to the number of TDI pixel stages. In CMOS TDI sensors, where voltage domain readout is used, the requirements over speed and noise of the ADC readout chain are increased due to accumulation of the dominant voltage readout and ADC noise with every stage N. Until this day, the latter is the primary reason for a leap-back of CMOS TDI sensors as compared to their CCD counterparts. Moreover, most commercial CMOS TDI implementations are still based on a charge-domain readout, mimicking a CCD-like operation mode. Thus, having a good understanding of each noise contributor in the signal chain, as well as its magnitude in different readout architectures, is vital for the design of future generation low-noise CMOS TDI image sensors based on a voltage domain readout. This paper gives a quantitative classification of all major noise sources for all popular implementations in the literature.

  18. Simulation of SEU transients in CMOS ICs

    SciTech Connect

    Kaul, N.; Bhuva, B.L.; Kerns, S.E. )

    1991-12-01

    This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE.

  19. NSC 800, 8-bit CMOS microprocessor

    NASA Technical Reports Server (NTRS)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  20. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    NASA Astrophysics Data System (ADS)

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  1. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    PubMed Central

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  2. Development and characterization of CMOS avalanche photodiode arrays

    NASA Astrophysics Data System (ADS)

    Lawrence, William G.; Christian, James F.; Augustine, Frank L.; Squillante, Michael R.; Entine, Gerald

    2005-04-01

    Avalanche photodiode (APD) arrays fabricated by using complementary metal-oxide-semiconductor (CMOS) fabrication technology offer the possibility of combining these high sensitivity detectors with cost effective, on-board, complementary circuitry. Using CMOS techniques, Radiation Monitoring Devices has developed prototype pixels with active diameters ranging from 5 to 60 microns and with measured quantum efficiencies of up to 65%. The prototype CMOS APD pixel designs support both proportional and Geiger modes of photo-detection. When operating in Geiger mode, these APD"s act as single-optical-photon-counting detectors that can be used for time-resolved measurements under signal-starved conditions. We have also designed and fabricated CMOS chips that contain not only the APD pixels, but also associated circuitry for both actively and passively quenching the self-propagating Geiger avalanche. This report presents the noise and timing performance for the prototype CMOS APD pixels in both the proportional and Geiger modes of operation. It compares the quantum efficiency and dark-count rate of different pixel designs as a function of the applied bias and presents a discussion of the maximum count rates that is obtained with each of the two types of quenching circuits for operating the pixel in Geiger mode. Preliminary data on the application of the APD pixels to laser ranging and fluorescent lifetime measurement is also presented.

  3. Improved Space Object Observation Techniques Using CMOS Detectors

    NASA Astrophysics Data System (ADS)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  4. A CMOS pixel sensor prototype for the outer layers of linear collider vertex detector

    NASA Astrophysics Data System (ADS)

    Zhang, L.; Morel, F.; Hu-Guo, C.; Himmi, A.; Dorokhov, A.; Hu, Y.

    2015-01-01

    The International Linear Collider (ILC) expresses a stringent requirement for high precision vertex detectors (VXD). CMOS pixel sensors (CPS) have been considered as an option for the VXD of the International Large Detector (ILD), one of the detector concepts proposed for the ILC. MIMOSA-31 developed at IPHC-Strasbourg is the first CPS integrated with 4-bit column-level ADC for the outer layers of the VXD, adapted to an original concept minimizing the power consumption. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal noise and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with a self-triggered analog-to-digital converter (ADC). The ADC design was optimized for power saving at a sampling frequency of 6.25 MS/s. The prototype chip is fabricated in a 0.35 μm CMOS technology. This paper presents the details of the prototype chip and its test results.

  5. Multi-channel high-speed CMOS image acquisition and pre-processing system

    NASA Astrophysics Data System (ADS)

    Sun, Chun-feng; Yuan, Feng; Ding, Zhen-liang

    2008-10-01

    A new multi-channel high-speed CMOS image acquisition and pre-processing system is designed to realize the image acquisition, data transmission, time sequential control and simple image processing by high-speed CMOS image sensor. The modular structure design, LVDS and ping-pong cache techniques used during the designed image data acquisition sub-system design ensure the real-time data acquisition and transmission. Furthermore, a new histogram equalization algorithm of adaptive threshold value based on the reassignment of redundant gray level is incorporated in the image preprocessing module of FPGA. The iterative method is used in the course of setting threshold value, and a redundant graylevel is redistributed rationally according to the proportional gray level interval. The over-enhancement of background is restrained and the feasibility of mergence of foreground details is reduced. The experimental certificates show that the system can be used to realize the image acquisition, transmission, memory and pre-processing to 590MPixels/s data size, and make for the design and realization of the subsequent system.

  6. CMOS image sensor noise reduction method for image signal processor in digital cameras and camera phones

    NASA Astrophysics Data System (ADS)

    Yoo, Youngjin; Lee, SeongDeok; Choe, Wonhee; Kim, Chang-Yong

    2007-02-01

    Digital images captured from CMOS image sensors suffer Gaussian noise and impulsive noise. To efficiently reduce the noise in Image Signal Processor (ISP), we analyze noise feature for imaging pipeline of ISP where noise reduction algorithm is performed. The Gaussian noise reduction and impulsive noise reduction method are proposed for proper ISP implementation in Bayer domain. The proposed method takes advantage of the analyzed noise feature to calculate noise reduction filter coefficients. Thus, noise is adaptively reduced according to the scene environment. Since noise is amplified and characteristic of noise varies while the image sensor signal undergoes several image processing steps, it is better to remove noise in earlier stage on imaging pipeline of ISP. Thus, noise reduction is carried out in Bayer domain on imaging pipeline of ISP. The method is tested on imaging pipeline of ISP and images captured from Samsung 2M CMOS image sensor test module. The experimental results show that the proposed method removes noise while effectively preserves edges.

  7. CMOS preamplifier with high linearity and ultra low noise for x-ray spectroscopy

    SciTech Connect

    O`Connor, P.O.; Rehak, P.; Gramegna, G.; Corsi, F.; Marzocca, C.

    1996-12-31

    We present an ultra low noise charge preamplifier suitable for small capacitance (200M), low leakage current solid state detectors. A self adaptive bias circuit for the MOS feedback device establishes the static feedback resistance in the G{Omega} range while tracking the threshold variations and power supply and temperature fluctuations. The linearity of the gain versus input charge has been improved by means of a voltage divider between the output of the charge-sensitive amplifier and the source of the feedback transistor. With the preamplifier alone, we measure a room-temperature equivalent noise charge (ENC) of 9 e{sup -} rms at 12 usec shaping time. When coupled to a cooled detector a FWHM of 130 eV is obtained at 2.4 usec shaping, corresponding to an ENC of 16 e{sup -} rms. This is the best reported resolution obtained with a CMOS preamplifier. The circuit has good linearity (< 0.2%) up to 1.8 W. Since the preamplifier`s ENC is limited by flicker noise, we fabricated the circuit in two 1.2um CMOS technologies. Device measurements allow us to compare the 1/f noise behavior of each foundry. In addition to the preamplifiers, a 1 us shaper and a 50{Omega} output driver are included on the die.

  8. Towards a 10 μs, thin and high resolution pixelated CMOS sensor system for future vertex detectors

    NASA Astrophysics Data System (ADS)

    De Masi, R.; Amar-Youcef, S.; Baudot, J.; Bertolone, G.; Brogna, A.; Chon-Sen, N.; Claus, G.; Colledani, C.; Degerli, Y.; Deveaux, M.; Dorokhov, A.; Doziére, G.; Dulinski, W.; Gelin, M.; Goffe, M.; Fontaine, J. C.; Hu-Guo, Ch.; Himmi, A.; Jaaskelainen, K.; Koziel, M.; Morel, F.; Müntz, C.; Orsini, F.; Santos, C.; Schrader, C.; Specht, M.; Stroth, J.; Valin, I.; Voutsinas, G.; Wagner, F. M.; Winter, M.

    2011-02-01

    The physics goals of many high energy experiments require a precise determination of decay vertices, imposing severe constraints on vertex detectors (readout speed, granularity, material budget,…). The IPHC-IRFU collaboration developed a sensor architecture to comply with these requirements. The first full scale CMOS sensor was realised and equips the reference planes of the EUDET beam telescope. Its architecture is being adapted to the needs of the STAR (RHIC) and CBM (FAIR) experiments. It is a promising candidate for the ILC experiments and the ALICE detector upgrade (LHC). A substantial improvement to the CMOS sensor performances, especially in terms of radiation hardness, should come from a new fabrication technology with depleted sensitive volume. A prototype sensor was fabricated to explore the benefits of the technology. The crucial system integration issue is also currently being addressed. In 2009 the PLUME collaboration was set up to investigate the feasibility and performances of a light double sided ladder equipped with CMOS sensors, aimed primarily for the ILC vertex detector but also of interest for other applications such as the CBM vertex detector.

  9. Process, voltage and temperature compensation in a 1-MHz 130nm CMOS monolithic clock oscillator with 2.3% accuracy

    NASA Astrophysics Data System (ADS)

    Bian, Zhen-Peng; Yao, Ruo-He

    2015-10-01

    This paper presents an on-chip process, voltage and temperature (PVT) compensation technique for a 1-MHz monolithic clock oscillator in a CMOS process. The oscillator is based on carrier mobility and frequency-to-voltage converter (FVC), which is based on charge pump circuit. An adaptive charge current maintains a constant frequency without trimming. Furthermore, a reference voltage with a second-order temperature coefficient further compensates the variation of frequency with temperature. It improves the accuracy of existing carrier-mobility-based oscillator, from 4.5% to 2.3%. The circuit was designed in a 130 nm CMOS 3.3 V device process. The results show that the output frequency is within ?2.3% variation in the worst case. The variations of frequency with process, temperature (-40 to 125°C) and power supply are within ?1.8%, ?0.8% and ?0.2%/V, respectively. It achieves a CMOS monolithic clock oscillator insensitive to PVT.

  10. Radiation tolerant back biased CMOS VLSI

    NASA Technical Reports Server (NTRS)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  11. A CMOS humidity sensor for passive RFID sensing applications.

    PubMed

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  12. Design and characterization of avalanche photodiodes in submicron CMOS technologies

    NASA Astrophysics Data System (ADS)

    Pancheri, L.; Bendib, T.; Dalla Betta, G.-F.; Stoppa, D.

    2014-03-01

    The fabrication of Avalanche Photodiodes (APDs) in CMOS processes can be exploited in several application domains, including telecommunications, time-resolved optical detection and scintillation detection. CMOS integration allows the realization of systems with a high degree of parallelization which are competitive with hybrid solutions in terms of cost and complexity. In this work, we present a linear-mode APD fabricated in a 0.15μm process, and report its gain and noise characterization. The experimental observations can be accurately predicted using Hayat dead-space noise model. Device simulations based on dead-space model are then used to discuss the current status and the perspectives for the integration of high-performance low-noise devices in standard CMOS processes.

  13. Fabrication of the planar angular rotator using the CMOS process

    NASA Astrophysics Data System (ADS)

    Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

    2002-05-01

    In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

  14. Scaling CMOS photonics transceivers beyond 100 Gb/s

    NASA Astrophysics Data System (ADS)

    Mekis, Attila; Abdalla, Sherif; De Dobbelaere, Peter M.; Foltz, Dennis; Gloeckner, Steffen; Hovey, Steven; Jackson, Steven; Liang, Yi; Mack, Michael; Masini, Gianlorenzo; Novais, Rafaela; Peterson, Mark; Pinguet, Thierry; Sahni, Subal; Schramm, Jeff; Sharp, Michael; Song, Daniel; Welch, Brian P.; Yokoyama, Kosei; Yu, Shuhuan

    2012-01-01

    We report on the performance of an integrated four-channel parallel optical transceiver built in a CMOS photonics process, operating at 28 Gb/s per channel. The optical engine of the transceiver comprises a single silicon die and a hybrid integrated DFB laser. The silicon die contains the all functionalities needed for an optical transceiver: transmitter and receiver optics, electrical driver, receiver and control circuits. We also describe the CMOS photonics platform used to build such transceiver device, which consists of: an optically enabled CMOS process, a photonic device library, and a design infrastructure that is modeled after standard circuit design tools. We discuss how this platform can scale to higher speeds and channel counts.

  15. CMOS Monolithic Active Pixel Sensors (MAPS): Developments and future outlook

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; Fant, A.; Gasiorek, P.; Esbrand, C.; Griffiths, J. A.; Metaxas, M. G.; Royle, G. J.; Speller, R.; Venanzi, C.; van der Stelt, P. F.; Verheij, H.; Li, G.; Theodoridis, S.; Georgiou, H.; Cavouras, D.; Hall, G.; Noy, M.; Jones, J.; Leaver, J.; Machin, D.; Greenwood, S.; Khaleeq, M.; Schulerud, H.; Østby, J. M.; Triantis, F.; Asimidis, A.; Bolanakis, D.; Manthos, N.; Longo, R.; Bergamaschi, A.

    2007-12-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end applications, for example web-cams, and is slowly pervading the high-end applications, for example in prosumer digital cameras. Higher specifications are required for scientific applications: very low noise, high speed, high dynamic range, large format and radiation hardness are some of these requirements. This paper will present a brief overview of the CMOS Image Sensor technology and of the requirements for scientific applications. As an example, a sensor for X-ray imaging will be presented. This sensor was developed within a European FP6 Consortium, intelligent imaging sensors (I-ImaS).

  16. High-speed polysilicon CMOS photodetector for telecom and datacom

    NASA Astrophysics Data System (ADS)

    Atabaki, Amir H.; Meng, Huaiyu; Alloatti, Luca; Mehta, Karan K.; Ram, Rajeev J.

    2016-09-01

    Absorption by mid-bandgap states in polysilicon or heavily implanted silicon has been previously utilized to implement guided-wave infrared photodetectors in CMOS compatible photonic platforms. Here, we demonstrate a resonant guided-wave photodetector based on the polysilicon layer that is used for the transistor gate in a microelectronic SOI CMOS process without any change to the foundry process flow ("zero-change" CMOS). Through a combination of doping mask layers, a lateral pn junction diode in the polysilicon is demonstrated with a strong electric field to enable efficient photo-carrier extraction and high-speed operation. This photodetector has a responsivity of more than 0.14 A/W from 1300 to 1600 nm, a 10 GHz bandwidth, and 80 nA dark current at 15 V reverse bias.

  17. Operation and biasing for single device equivalent to CMOS

    DOEpatents

    Welch, James D.

    2001-01-01

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  18. A CMOS humidity sensor for passive RFID sensing applications.

    PubMed

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-05-16

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

  19. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  20. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as...

  1. Measuring trunk orientation with a CMOS camera: feasibility and accuracy.

    PubMed

    Gissot, A-S; Barbieri, G; Iacobelis, M; Paindavoine, M; Pérennou, D

    2007-10-01

    The purpose of this study was to develop and validate a new tool to objectively quantify trunk orientation at the bedside, especially dedicated to the measurement of the lateropulsion in acute and subacute stroke patients. We developed software to analyze 2D movement with a CMOS camera (Logitech Quickcam Pro 4000) and to calculate the orientation of a segment defined by two color markers. First, the accuracy, reproducibility and noise when measuring segment orientations were evaluated with the CMOS camera placed in different positions, and second trunk orientation was measured in static and in dynamic conditions both with a CMOS camera and with a gold standard 3D video system (BTS SMART-e). Results showed that the measurement was accurate (mean error=0.05+/-0.12 degrees), reproducible (S.D. over five measurements=0.005 degrees ) and steady (noise signal=0.02 degrees ). The data obtained with the CMOS camera were highly correlated with those obtained with the 3D video system both in static and in dynamic conditions. However, the CMOS camera must be relatively well centered on the measured segment to avoid error due to image distortion. The parallax error was negligible. In conclusion, this could be an important step in the postural assessment of acute and subacute stroke patients. The CMOS camera, a simple, portable, compact, low-cost, commercially available apparatus is the first tool to objectively quantify lateropulsion at the bedside. This method could also support the development of a rehabilitation program for trunk orientation based on biofeedback using the real-time signal provided by the device.

  2. Modifications in CMOS Dynamic Logic Style: A Review Paper

    NASA Astrophysics Data System (ADS)

    Meher, Preetisudha; Mahapatra, Kamalakanta

    2015-12-01

    Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper, an overview and classification of these techniques are first presented and then compared according to their performance.

  3. Statistical circuit design for yield improvement in CMOS circuits

    NASA Technical Reports Server (NTRS)

    Kamath, H. J.; Purviance, J. E.; Whitaker, S. R.

    1990-01-01

    This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

  4. CMOS Compatible Integrated Thermoelectric Sensors Using Novel Frontside Micromachining

    NASA Astrophysics Data System (ADS)

    Socher, E.; Bochobza-Degani, O.; Nemirovsky, Y.

    2000-12-01

    CMOS compatible integrated thermoelectric sensors were designed and realized using a standard CMOS process and frontside RIE micromachining. The suspended structures were designed to have a spiral structure that enhances the thermal resistance and isolation of the sensor. Using dry RIE frontside micromachining for the release of the sensors allows better yield in realization of sensitive and smaller sensor pixels. Measured results of sensors used for IR detection show NEP's down to 0.4 nW/√Hz and response times down to 3 msec in 70*70 μm2 pixels.

  5. New Multiple-Times Programmable CMOS ROM Cell

    NASA Astrophysics Data System (ADS)

    Chung, In-Young; Jeong, Seong Yeol; Seo, Sung Min; Lee, Myungjin; Jang, Taesu; Cha, Seon-Yong; Park, Young June

    New concept of CMOS nonvolatile memory is presented with demonstration of cell implementations. The memory cell, which is a comparator basically, makes use of comparator offset for storage quantity and the FN stress phenomena for cell programming. We also propose the stress-packet operation which is the relevant programming method to finely control the offset of the memory cell. The memory cell is multiple-time programmable while it is implemented in a standard CMOS process. We fabricated the memory cell arrays of the latch comparator and demonstrated that it is rewritten several times. We also investigated the reliability of cell data retention by monitoring programmed offsets for several months.

  6. CMOS-compatible photonic devices for single-photon generation

    NASA Astrophysics Data System (ADS)

    Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

    2016-09-01

    Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  7. A 0.5-GHz CMOS digital RF memory chip

    NASA Astrophysics Data System (ADS)

    Schnaitter, W. M.; Lewis, E. T.; Gordon, B. E.

    1986-10-01

    Digital RF memories (DRFM's) are key elements for modern radar jamming. An RF signal is sampled, stored in random access memory (RAM), and later recreated from the stored data. Here the first CMOS DRFM chip, integrating static RAM, control circuitry, and two channels of shift registers, on a single chip is described. The sample rate achieved was 0.5 GHz, VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.

  8. Study of built-in amplifier performance on HV-CMOS sensor for the ATLAS phase-II strip tracker upgrade

    NASA Astrophysics Data System (ADS)

    Liang, Z.; Affolder, A.; Arndt, K.; Bates, R.; Benoit, M.; Di Bello, F.; Blue, A.; Bortoletto, D.; Buckland, M.; Buttar, C.; Caragiulo, P.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hoeferkamp, M.; Hommels, L. B. A.; Huffman, B. T.; John, J.; Kanisauskas, K.; Kenney, C.; Kramberger, J.; Mandić, I.; Maneuski, D.; Martinez-Mckinney, F.; McMahon, S.; Meng, L.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Peric, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seidel, S.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zhang, J.; Zhu, H.

    2016-09-01

    This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip.

  9. Single Event Upset Behavior of CMOS Static RAM Cells

    NASA Technical Reports Server (NTRS)

    Lieneweg, Udo; Jeppson, Kjell O.; Buehler, Martin G.

    1993-01-01

    An improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.

  10. Integrated imaging sensor systems with CMOS active pixel sensor technology

    NASA Technical Reports Server (NTRS)

    Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

    2002-01-01

    This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

  11. CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.

    SciTech Connect

    RADEKA, V.

    2006-04-03

    Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

  12. CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics

    NASA Technical Reports Server (NTRS)

    Yeh, Penshu; Maki, Gary

    2007-01-01

    Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

  13. Effects Of Dose Rates On Radiation Damage In CMOS Parts

    NASA Technical Reports Server (NTRS)

    Goben, Charles A.; Coss, James R.; Price, William E.

    1990-01-01

    Report describes measurements of effects of ionizing-radiation dose rate on consequent damage to complementary metal oxide/semiconductor (CMOS) electronic devices. Depending on irradiation time and degree of annealing, survivability of devices in outer space, or after explosion of nuclear weapons, enhanced. Annealing involving recovery beyond pre-irradiation conditions (rebound) detrimental. Damage more severe at lower dose rates.

  14. Characterisation of a CMOS charge transfer device for TDI imaging

    NASA Astrophysics Data System (ADS)

    Rushton, J.; Holland, A.; Stefanov, K.; Mayer, F.

    2015-03-01

    The performance of a prototype true charge transfer imaging sensor in CMOS is investigated. The finished device is destined for use in TDI applications, especially Earth-observation, and to this end radiation tolerance must be investigated. Before this, complete characterisation is required. This work starts by looking at charge transfer inefficiency and then investigates responsivity using mean-variance techniques.

  15. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    PubMed Central

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

  16. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  17. CMOS-compatible LVOF-based visible microspectrometer

    NASA Astrophysics Data System (ADS)

    Emadi, Arvin; Wu, Huaiwen; de Graaf, Ger; Wolffenbuttel, Reinoud F.

    2010-04-01

    This paper reports on a CMOS-Compatible Linear Variable Optical Filter (LVOF) visible micro-spectrometer. The CMOS-compatible post process for fabrication of the LVOF has been used for integration of the LVOF with a CMOS chip containing a 128-element photodiode array and readout circuitry. Fabrication of LVOF involves a process for fabrication of very small taper angles, ranging from 0.001° to 0.1°, in SiO2. These layers can be fabricated flexibly in a resist layer by just one lithography step and a subsequent reflow process. The 3D pattern of the resist structures is subsequently transferred into SiO2 by appropriate etching. Complete LVOF fabrication involves CMOS-compatible deposition of a lower dielectric mirror using a stack of dielectrics on the wafer, tapered layer formation and deposition of the top dielectric mirror. The LVOF has been optimized for 580 nm - 720 nm spectral operating range and has also been mounted on a CCD camera for characterization. The design of LVOF micro-spectrometer, the fabrication and characterization results are presented.

  18. Optical and noise performance of CMOS solid-state photomultipliers

    NASA Astrophysics Data System (ADS)

    Chen, Xiao Jie; Johnson, Erik B.; Staples, Christopher J.; Chapman, Eric; Alberghini, Guy; Christian, James F.

    2010-08-01

    Solid-state photomultipliers (SSPM) are photodetectors composed of avalanche photodiode pixel arrays operating in Geiger mode (biased above diode breakdown voltage). They are built using CMOS technology and can be used in a variety of applications in high energy and nuclear physics, medical imaging and homeland security related areas. The high gain and low cost associated with the SSPM makes it an attractive alternative to existing photodetectors such as the photomultiplier tube (PMT). The capability of integrating CMOS on-chip readout circuitry on the same substrate as the SSPM also provides a compact and low-power-consumption solution to photodetector applications with stringent area and power requirements. The optical performance of the SSPM, specifically the detection and quantum efficiencies, can depend on the geometry and the doping profile associated with each photodiode pixel. The noise associated with the SSPM not only includes dark noise from each pixel, but also consists of excess noise terms due to after pulsing and inter-pixel cross talk. The magnitude of the excess noise terms can depend on biasing conditions, temperature, as well as pixel and inter-pixel dimensions. We present the optical and noise performance of SSPMs fabricated in a conventional CMOS process, and demonstrate the dependence of the SSPM performance on pixel/inter-pixel geometry, doping profile, temperature, as well as bias conditions. The continuing development of CMOS SSPM technology demonstrated here shows that low cost and high performance solid state photodetectors are viable solutions for many existing and future optical detection applications.

  19. Planar CMOS analog SiPMs: design, modeling, and characterization

    NASA Astrophysics Data System (ADS)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-11-01

    Silicon photomultipliers (SiPMs) are large area detectors consisting of an array of single-photon-sensitive microcells, which make SiPMs extremely attractive to substitute the photomultiplier tubes in many applications. We present the design, fabrication, and characterization of analog SiPMs in standard planar 0.35 μm CMOS technology, with about 1 mm × 1 mm total area and different kinds of microcells, based on single-photon avalanche diodes with 30 μm diameter reaching 21.0% fill-factor (FF), 50 μm diameter (FF = 58.3%) or 50 μm square active area with rounded corner of 5 μm radius (FF = 73.7%). We also developed the electrical SPICE model for CMOS SiPMs. Our CMOS SiPMs have 25 V breakdown voltage, in line with most commercial SiPMs and higher gain (8.8 × 106, 13.2 × 106, and 15.0 × 106, respectively). Although dark count rate density is slightly higher than state-of-the-art analog SiPMs, the proposed standard CMOS processing opens the feasibility of integration with active electronics, for switching hot pixels off, drastically reducing the overall dark count rate, or for further on-chip processing.

  20. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    NASA Astrophysics Data System (ADS)

    Rescigno, R.; Finck, Ch.; Juliani, D.; Baudot, J.; Dauvergne, D.; Dedes, G.; Krimmer, J.; Ray, C.; Reithinger, V.; Rousseau, M.; Testa, E.; Winter, M.

    2014-03-01

    Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  1. Attributes and drawbacks of submicron CMOS for IR FPA readouts

    NASA Astrophysics Data System (ADS)

    Kozlowski, L. J.

    1998-09-01

    The availability of submicron CMOS has enabled the development of shingle-chip IR cameras having performance capabilities and on-chip functions which were previously impossible. Sensor designers are, however, encoutering and overcoming several challanges including steadily decreasing operating voltage.

  2. Performance of CMOS ternary full adder at liquid nitrogen temperature

    NASA Astrophysics Data System (ADS)

    Srivastava, A.; Venkatapathy, K.

    We have designed, implemented and studied the performance at liquid nitrogen temperature (77 K) of a CMOS ternary full adder and its building blocks, the simple ternary inverter (STI), positive ternary inverter (PTI) and negative ternary inverter (NTI), and compared the corresponding performance at room temperature (300 K). The ternary full adder has been fabricated in 2 μm, n-well CMOS through MOSIS. In a ternary full adder, the basic building blocks, the PTI and NTI, have been developed using combinations of a CMOS inverter and transmission gate(s). There is close agreement between the simulated and measured voltage transfer characteristics and noise margins of ternary-valued devices. The measured transient times for the NTI, PTI and ternary full adder at 77 K show an improvement by a factor of ≈1.5-2.5 over the corresponding values at 300 K. The present design does not use linear resistors and depletion-mode MOSFETs to implement the ternary full adder and its building blocks, and is fully compatible with current CMOS technology.

  3. Research-grade CMOS image sensors for remote sensing applications

    NASA Astrophysics Data System (ADS)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

    2004-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

  4. Research-grade CMOS image sensors for demanding space applications

    NASA Astrophysics Data System (ADS)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2004-06-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  5. Direct readout of gaseous detectors with tiled CMOS circuits

    NASA Astrophysics Data System (ADS)

    Visschers, J. L.; Blanco Carballo, V.; Chefdeville, M.; Colas, P.; van der Graaf, H.; Schmitz, J.; Smits, S.; Timmermans, J.

    2007-03-01

    A coordinated design effort is underway, exploring the three-dimensional direct readout of gaseous detectors by an anode plate equipped with a tiled array of many CMOS pixel readout ASICs, having amplification grids integrated on their topsides and being contacted on their backside.

  6. Distinct development patterns of c-mos protooncogene expression in female and male mouse germ cells

    SciTech Connect

    Mutter, G.L.; Wolgemuth, D.J.

    1987-08-01

    The protooncogene c-mos is expressed in murine reproductive tissues, producing transcripts of 1.7 and 1.4 kilobases in testis and ovary, respectively. In situ hybridization analysis of c-mos expression in histological sections of mouse ovaries revealed that oocytes are the predominant if not exclusive source of c-mos transcripts. /sup 35/S- or /sup 32/P-labelled RNA probes were transcribed. c-mos transcripts accumulate in growing oocytes, increasing 40- to 90-fold during oocyte and follicular development. c-mos transcripts were also detected in male germ cells and are most abundant after the cells have entered the haploid stage of spermatogenesis. This developmentally regulated pattern of c-mos expression in oocytes and spermatogenic cells suggest that the c-mos gene product may have a function in normal germ-cell differentiation or early embryogenesis.

  7. Hybrid CMOS SiPIN detectors as astronomical imagers

    NASA Astrophysics Data System (ADS)

    Simms, Lance Michael

    Charge Coupled Devices (CCDs) have dominated optical and x-ray astronomy since their inception in 1969. Only recently, through improvements in design and fabrication methods, have imagers that use Complimentary Metal Oxide Semiconductor (CMOS) technology gained ground on CCDs in scientific imaging. We are now in the midst of an era where astronomers might begin to design optical telescope cameras that employ CMOS imagers. The first three chapters of this dissertation are primarily composed of introductory material. In them, we discuss the potential advantages that CMOS imagers offer over CCDs in astronomical applications. We compare the two technologies in terms of the standard metrics used to evaluate and compare scientific imagers: dark current, read noise, linearity, etc. We also discuss novel features of CMOS devices and the benefits they offer to astronomy. In particular, we focus on a specific kind of hybrid CMOS sensor that uses Silicon PIN photodiodes to detect optical light in order to overcome deficiencies of commercial CMOS sensors. The remaining four chapters focus on a specific type of hybrid CMOS Silicon PIN sensor: the Teledyne Hybrid Visible Silicon PIN Imager (HyViSI). In chapters four and five, results from testing HyViSI detectors in the laboratory and at the Kitt Peak 2.1m telescope are presented. We present our laboratory measurements of the standard detector metrics for a number of HyViSI devices, ranging from 1k×1k to 4k×4k format. We also include a description of the SIDECAR readout circuit that was used to control the detectors. We then show how they performed at the telescope in terms of photometry, astrometry, variability measurement, and telescope focusing and guiding. Lastly, in the final two chapters we present results on detector artifacts such as pixel crosstalk, electronic crosstalk, and image persistence. One form of pixel crosstalk that has not been discussed elsewhere in the literature, which we refer to as Interpixel Charge

  8. A novel multi-actuation CMOS RF MEMS switch

    NASA Astrophysics Data System (ADS)

    Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

    2008-12-01

    This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

  9. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; French, M.; Manolopoulos, S.; Tyndel, M.; Allport, P.; Bates, R.; O'Shea, V.; Hall, G.; Raymond, M.

    2003-03-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to tape. Because of the large number of pixels, data reduction is needed on the sensor itself or just outside. This brings in stringent requirements on the temporal noise as well as to the sensor uniformity, expressed as a Fixed Pattern Noise (FPN). A pixel architecture with an additional transistor is proposed. This architecture, coupled to correlated double sampling of the signal will allow cancellation of the two dominant noise sources, namely the reset or kTC noise and the FPN. A prototype has been designed in a standard 0.25 μm CMOS technology. It has also a structure for electrical calibration of the sensor. The prototype is functional and detailed tests are under way.

  10. Contact CMOS imaging of gaseous oxygen sensor array.

    PubMed

    Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-10-01

    We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3](2+)) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

  11. Contact CMOS imaging of gaseous oxygen sensor array

    PubMed Central

    Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

    2014-01-01

    We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

  12. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    PubMed

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

  13. Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

    NASA Astrophysics Data System (ADS)

    Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

    2013-07-01

    In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

  14. CMOS VLSI Active-Pixel Sensor for Tracking

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  15. High-Voltage-Input Level Translator Using Standard CMOS

    NASA Technical Reports Server (NTRS)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  16. Improved Space Object Orbit Determination Using CMOS Detectors

    NASA Astrophysics Data System (ADS)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  17. A 0.8-V Syllabic-Companding Log Domain Filter with 78-dB Dynamic Range in 0.35-μm CMOS

    NASA Astrophysics Data System (ADS)

    Akita, Ippei; Wada, Kazuyuki; Tadokoro, Yoshiaki

    A scheme for a low-voltage CMOS syllabic-companding log domain filter with wide dynamic range is proposed and its prototype is presented. A nodal voltage which is fixed in a conventional filter based on the dynamically adjustable biasing (DAB) technique is adapted for change of input envelope to achieve wide dynamic range. Externally linear and time invariant (ELTI) relation between an input and an output is guaranteed by a state variable correction (SVC) circuit which is also proposed for low-voltage operation. To demonstrate the proposed scheme, a fifth-order Chebychev low-pass filter with 100-kHz cutoff frequency is designed and fabricated in a standard 0.35-μm CMOS process. The filter has a 78-dB dynamic range and consumes 200-μW power from a 0.8-V power supply.

  18. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy.

    PubMed

    Valente, Virgilio; Demosthenous, Andreas

    2016-01-01

    This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm 2 , is capable of an operational bandwidth of 8 MHz and a linear gain in the range between -6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μ A. Each CR channel occupies an area of 0.21 mm 2 . The chip consumes between 530 μ A and 690 μ A per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis. PMID:27463721

  19. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

    PubMed Central

    Valente, Virgilio; Demosthenous, Andreas

    2016-01-01

    This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm2, is capable of an operational bandwidth of 8 MHz and a linear gain in the range between −6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μA. Each CR channel occupies an area of 0.21 mm2. The chip consumes between 530 μA and 690 μA per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis. PMID:27463721

  20. CMOS RAM cosmic-ray-induced-error-rate analysis

    NASA Technical Reports Server (NTRS)

    Pickel, J. C.; Blandford, J. T., Jr.

    1981-01-01

    A significant number of spacecraft operational anomalies are believed to be associated with cosmic-ray-induced soft errors in the LSI memories. Test programs using a cyclotron to simulate cosmic rays have established conclusively that many common commercial memory types are vulnerable to heavy-ion upset. A description is given of the methodology and the results of a detailed analysis for predicting the bit-error rate in an assumed space environment for CMOS memory devices. Results are presented for three types of commercially available CMOS 1,024-bit RAMs. It was found that the HM6508 is susceptible to single-ion induced latchup from argon and krypton ions. The HS6508 and HS6508RH and the CDP1821 apparently are not susceptible to single-ion induced latchup.

  1. Fundamental performance differences between CMOS and CCD imagers: Part II

    NASA Astrophysics Data System (ADS)

    Janesick, James; Andrews, James; Tower, John; Grygon, Mark; Elliott, Tom; Cheng, John; Lesser, Michael; Pinter, Jeff

    2007-09-01

    A new class of CMOS imagers that compete with scientific CCDs is presented. The sensors are based on deep depletion backside illuminated technology to achieve high near infrared quantum efficiency and low pixel cross-talk. The imagers deliver very low read noise suitable for single photon counting - Fano-noise limited soft x-ray applications. Digital correlated double sampling signal processing necessary to achieve low read noise performance is analyzed and demonstrated for CMOS use. Detailed experimental data products generated by different pixel architectures (notably 3TPPD, 5TPPD and 6TPG designs) are presented including read noise, charge capacity, dynamic range, quantum efficiency, charge collection and transfer efficiency and dark current generation. Radiation damage data taken for the imagers is also reported.

  2. CMOS Imaging Device for Optical Imaging of Biological Activities

    NASA Astrophysics Data System (ADS)

    Shishido, Sanshiro; Oguro, Yasuhiro; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Ohta, Jun

    In this paper, we propose a CMOS image sensor device placed on the brain surface or cerebral sulcus (Fig. 1). The device has a photo detector array where a single optical detector is usually used. The proposed imaging device enables the analysis which reflects a surface blood pattern in the observed area. It is also possible to improve effective sensitivity by image processing and to simplify the measurement system by the CMOS sensor device with on-chip light source. We describe the design details and characterization of proposed device. We also demonstrate detection of hemoglobin oxygenation level with external light source, imaging capability of biological activities, and image processing for sensitivity improvement is also realized.

  3. A CMOS integrated timing discriminator circuit for fast scintillation counters

    SciTech Connect

    Jochmann, M.W.

    1998-06-01

    Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t{sub r} {ge} 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal`s amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range.

  4. A back-illuminated megapixel CMOS image sensor

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

    2005-01-01

    In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

  5. Micromachined high-performance RF passives in CMOS substrate

    NASA Astrophysics Data System (ADS)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-11-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications.

  6. A CMOS image sensor dedicated to medical gamma camera application

    NASA Astrophysics Data System (ADS)

    Salahuddin, Nur S.; Paindavoine, Michel; Ginhac, Dominique; Parmentier, Michel; Tamda, Najia

    2005-03-01

    Generally, medical Gamma Camera are based on the Anger principle. These cameras use a scintillator block coupled to a bulky array of photomultiplier tube (PMT). To simplify this, we designed a new integrated CMOS image sensor in order to replace bulky PMT photodetetors. We studied several photodiodes sensors including current mirror amplifiers. These photodiodes have been fabricated using a CMOS 0.6 micrometers process from Austria Mikro Systeme (AMS). Each sensor pixel in the array occupies respectively, 1mm x 1mm area, 0.5mm x 0.5mm area and 0.2mm 0.2mm area with fill factor 98 % and total chip area is 2 square millimeters. The sensor pixels show a logarithmic response in illumination and are capable of detecting very low green light emitting diode (less than 0.5 lux) . These results allow to use our sensor in new Gamma Camera solid-state concept.

  7. CCD or CMOS camera calibration using point spread function

    NASA Astrophysics Data System (ADS)

    Abdelsalam, D. G.; Stanislas, M.; Coudert, S.

    2014-06-01

    We present a simple method based on the acquisition of a back-illuminated pinhole to estimate the point spread function (PSF) for CCD (or CMOS) sensor characterization. This method is used to measure the variations in sensitivity of the 2D-sensor array systems. The experimental results show that there is a variation in sensitivity for each position on the CCD of the calibrated camera and the pixel optical center error with respect to the geometrical center is in the range of 1/10th of a pixel. We claim that the pixel error comes most probably from the coherence of the laser light used, or eventually from possible defects in shape, surface quality, optical performance of micro-lenses, and the uniformity of the parameters across the wafer. This may have significant consequences for coherent light imaging using CCD (or CMOS) such as Particle Image Velocimetry.

  8. A Brief Discussion of Radiation Hardening of CMOS Microelectronics

    SciTech Connect

    Myers, D.R.

    1998-12-18

    Commercial microchips work well in their intended environments. However, generic microchips will not fimction correctly if exposed to sufficient amounts of ionizing radiation, the kind that satellites encounter in outer space. Modern CMOS circuits must overcome three specific concerns from ionizing radiation: total-dose, single-event, and dose-rate effects. Minority-carrier devices such as bipolar transistors, optical receivers, and solar cells must also deal with recombination-generation centers caused by displacement damage, which are not major concerns for majority-carrier CMOS devices. There are ways to make the chips themselves more resistant to radiation. This extra protection, called radiation hardening, has been called both a science and an art. Radiation hardening requires both changing the designs of the chips and altering the ways that the chips are manufactured.

  9. TID Simulation of Advanced CMOS Devices for Space Applications

    NASA Astrophysics Data System (ADS)

    Sajid, Muhammad

    2016-07-01

    This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

  10. Smart CMOS image sensor for lightning detection and imaging.

    PubMed

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-03-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach.

  11. Attenuation of single event induced pulses in CMOS combinational logic

    SciTech Connect

    Baze, M.P.; Buchner, S.P.

    1997-12-01

    Results are presented of a study of SEU generated transient pulse attenuation in combinational logic structures built using common digital CMOS design practices. SPICE circuit analysis, heavy ion tests, and pulsed, focused laser simulations were used to examine the response characteristics of transient pulse behavior in long logic strings. Results show that while there is an observable effect, it cannot be generally assumed that attenuation will significantly reduce observed circuit bit error rates.

  12. Hardening of commercial CMOS PROMs with polysilicon fusible links

    NASA Technical Reports Server (NTRS)

    Newman, W. H.; Rauchfuss, J. E.

    1985-01-01

    The method by which a commercial 4K CMOS PROM with polysilicon fuses was hardened and the feasibility of applying this method to a 16K PROM are presented. A description of the process and the necessary minor modifications to the original layout are given. The PROM circuit and discrete device characteristics over radiation to 1000K rad-Si are summarized. The dose rate sensitivity of the 4K PROMs is also presented.

  13. Linear dynamic range enhancement in a CMOS imager

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor)

    2008-01-01

    A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

  14. A BiCMOS integrated charge to amplitude converter

    SciTech Connect

    Gallin-Martel, L.; Pouxe, J.; Rossetto, O.

    1996-12-31

    This paper describes a fast two channel gated charge to amplitude converter (QAC) which has been designed with the 1.2 {mu}m BiCMOS technology from AMS (Austria Mikro Systeme). It can integrate fast negative impulse currents up to 100 mA. Associated with an audio 18 bit low cost ADC, it can easily be used to make a 12 to 13 bit QDC. The problems of current to current conversion, pedestal and offset stability are discussed.

  15. CMOS Alcohol Sensor Employing ZnO Nanowire Sensing Films

    NASA Astrophysics Data System (ADS)

    Santra, S.; Ali, S. Z.; Guha, P. K.; Hiralal, P.; Unalan, H. E.; Dalal, S. H.; Covington, J. A.; Milne, W. I.; Gardner, J. W.; Udrea, F.

    2009-05-01

    This paper reports on the utilization of zinc oxide nanowires (ZnO NWs) on a silicon on insulator (SOI) CMOS micro-hotplate for use as an alcohol sensor. The device was designed in Cadence and fabricated in a 1.0 μm SOI CMOS process at XFAB (Germany). The basic resistive gas sensor comprises of a metal micro-heater (made of aluminum) embedded in an ultra-thin membrane. Gold plated aluminum electrodes, formed of the top metal, are used for contacting with the sensing material. This design allows high operating temperatures with low power consumption. The membrane was formed by using deep reactive ion etching. ZnO NWs were grown on SOI CMOS substrates by a simple and low-cost hydrothermal method. A few nanometer of ZnO seed layer was first sputtered on the chips, using a metal mask, and then the chips were dipped in a zinc nitrate hexahydrate and hexamethylenetramine solution at 90° C to grow ZnO NWs. The chemical sensitivity of the on-chip NWs were studied in the presence of ethanol (C2H5OH) vapour (with 10% relative humidity) at two different temperatures: 200 and 250° C (the corresponding power consumptions are only 18 and 22 mW). The concentrations of ethanol vapour were varied from 175-1484 ppm (pers per million) and the maximum response was observed 40% (change in resistance in %) at 786 ppm at 250° C. These preliminary measurements showed that the on-chip deposited ZnO NWs could be a promising material for a CMOS based ethanol sensor.

  16. Accelerated life testing effects on CMOS microcircuit characteristics, phase 1

    NASA Technical Reports Server (NTRS)

    Maximow, B.

    1976-01-01

    An accelerated life test of sufficient duration to generate a minimum of 50% cumulative failures in lots of CMOS devices was conducted to provide a basis for determining the consistency of activation energy at 250 C. An investigation was made to determine whether any thresholds were exceeded during the high temperature testing, which could trigger failure mechanisms unique to that temperature. The usefulness of the 250 C temperature test as a predictor of long term reliability was evaluated.

  17. CMOS integration of inkjet-printed graphene for humidity sensing

    NASA Astrophysics Data System (ADS)

    Santra, S.; Hu, G.; Howe, R. C. T.; de Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-11-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  18. CMOS integration of inkjet-printed graphene for humidity sensing.

    PubMed

    Santra, S; Hu, G; Howe, R C T; De Luca, A; Ali, S Z; Udrea, F; Gardner, J W; Ray, S K; Guha, P K; Hasan, T

    2015-11-30

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  19. Development of CMOS Imager Block for Capsule Endoscope

    NASA Astrophysics Data System (ADS)

    Shafie, S.; Fodzi, F. A. M.; Tung, L. Q.; Lioe, D. X.; Halin, I. A.; Hasan, W. Z. W.; Jaafar, H.

    2014-04-01

    This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5V to 3.3V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5V to 3.3V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

  20. On-chip digital noise reduction for integrated CMOS Cameras

    NASA Astrophysics Data System (ADS)

    Rullmann, Markus; Schluessler, Jens-Uwe; Schueffny, Rene

    2003-06-01

    We propose an on-line noise reduction system especially designed for noisy CMOS image sensors. Image sequences from CMOS sensors in general are corrupted by two types of noise, temporal noise and fixed pattern noise (FPN). It is shown how the FPN component can be estimated from a sequence. We studied the theoretical performance of two different approaches called direct and indirect FPN estimation. We show that indirect estimation gives superior performance, both theoretically and by simulations. The FPN estimates can be used to improve the image quality by compensating it. We assess the quality of the estimates by the achievable SNR gains. Using those results a dedicated filtering scheme has been designed to accomplish both temporal noise reduction and FPN correction by applying a single noise filter. It allows signal gains of up to 12dB and provides a high visual quality of the results. We further analyzed and optimized the memory size and bandwidth requirements of our scheme and conclude that it is possible to implement it in hardware. The required memory size is 288kByte and the memory access rate is 70MHz. Our algorithm allows the integration of noisy CMOS sensors with digital noise reduction and other circuitry on a system-on-chip solution.

  1. CMOS Active Pixel Sensor (APS) Imager for Scientific Applications

    NASA Astrophysics Data System (ADS)

    Ay, Suat U.; Lesser, Michael P.; Fossum, Eric R.

    2002-12-01

    A 512×512 CMOS Active Pixel Sensor (APS) imager has been designed, fabricate, and tested for frontside illumination suitable for use in astronomy specifically in telescope guider systems as a replacement of CCD chips. The imager features a high-speed differential analog readout, 15 μm pixel pitch, 75 % fill factor (FF), 62 dB dynamic range, 315Ke- pixel capacity, less than 0.25% fixed pattern noise (FPN), 45 dB signal to noise ratio (SNR) and frame rate of up to 40 FPS. Design was implemented in a standard 0.5 μm CMOS process technology consuming less than 200mWatts on a single 5 Volt power supply. CMOS Active Pixel Sensor (APS) imager was developed with pixel structure suitable for both frontside and backside illumination holding large number of electron in relatively small pixel pitch of 15 μm. High-speed readout and signal processing circuits were designed to achieve low fixed pattern noise (FPN) and non-uniformity to provide CCD-like analog outputs. Target spectrum range of operation for the imager is in near ultraviolet (300-400 nm) with high quantum efficiency. This device is going to be used as a test vehicle to develop backside-thinning process.

  2. Transversal-readout CMOS active pixel image sensor

    NASA Astrophysics Data System (ADS)

    Miyatake, Shigehiro; Ishida, Kouichi; Morimoto, Takashi; Masaki, Yasuo; Tanabe, Hideki

    2001-05-01

    This paper presents a CMOS active pixel image sensor (APS) with a transversal readout architecture that eliminates the vertically striped fixed pattern noise (FPN). There are two kinds of FPNs for CMOS APSs. One originates form the pixel- to-pixel variation in dark current and source-follower threshold voltage, and the other from the column-to-column variation in column readout structures. The former may become invisible in the future due to process improvements. However, the latter, which result sin a vertically striped FPN, is and will be conspicuous without some subtraction because of the correlation in the vertical direction. The pixel consists of a photodiode, a row- and a column-reset transistor, a source follower input transistor, and a column-select transistor instead of the row-select transistor in conventional CMOS APSs. The column-select transistor is connected to a signal line, which runs horizontally instead of vertically. Every horizontal signal line is merged into a single vertical signal line via a row- select transistor, which can be made large enough to make its on-resistence variation negligible because of its low driving frequency. Therefore, the sensor has neither a vertical nor horizontal stripe FPN.

  3. Noise sources and noise suppression in CMOS imagers

    NASA Astrophysics Data System (ADS)

    Pain, Bedabrata; Cunningham, Thomas J.; Hancock, Bruce R.

    2004-01-01

    Mechanisms for noise coupling in CMOS imagers are complex, since unlike a CCD, a CMOS imager has to be considered as a full digital-system-on-a-chip, with a highly sensitive front-end. In this paper, we analyze the noise sources in a photodiode CMOS imager, and model their propagation through the signal chain to determine the nature and magnitude of noise coupling. We present methods for reduction of noise, and present measured data to show their viability. For temporal read noise reduction, we present pixel signal chain design techniques to achieve near 2 electrons read noise. We model the front-end reset noise both for conventional photodiode and CTIA type of pixels. For the suppression of reset noise, we present a column feedback-reset method to reduce reset noise below 6 electrons. For spatial noise reduction, we present the design of column signal chain that suppresses both spatial noise and power supply coupling noise. We conclude by identifying problems in low-noise design caused by dark current spatial distribution.

  4. An integrated CMOS detection system for optical short-pulse

    NASA Astrophysics Data System (ADS)

    Kim, Chang-Gun; Hong, Nam-Pyo; Choi, Young-Wan

    2014-03-01

    We present design of a front-end readout system consisting of charge sensitive amplifier (CSA) and pulse shaper for detection of stochastic and ultra-small semiconductor scintillator signal. The semiconductor scintillator is double sided silicon detector (DSSD) or avalanche photo detector (APD) for high resolution and peak signal reliability of γ-ray or X-ray spectroscopy. Such system commonly uses low noise multichannel CSA. Each CSA in multichannel includes continuous reset system based on tens of MΩ and charge-integrating capacitor in feedback loop. The high value feedback resistor requires large area and huge power consumption for integrated circuits. In this paper, we analyze these problems and propose a CMOS short pulse detection system with a novel CSA. The novel CSA is composed of continuous reset system with combination of diode connected PMOS and 100 fF. This structure has linearity with increased input charge quantity from tens of femto-coulomb to pico-coulomb. Also, the front-end readout system includes both slow and fast shapers for detecting CSA output and preventing pile-up distortion. Shaping times of fast and slow shapers are 150 ns and 1.4 μs, respectively. Simulation results of the CMOS detection system for optical short-pulse implemented in 0.18 μm CMOS technology are presented.

  5. Optimizing quantum efficiency in a stacked CMOS sensor

    NASA Astrophysics Data System (ADS)

    Hannebauer, Rob; Yoo, Sang Keun; Gilblom, David L.; Gilblom, Alexander D.

    2011-03-01

    Optimizing quantum efficiency of image sensors, whether CCD or CMOS, has usually required backside thinning to bring the photon receiving surface close to the charge generation elements. A new CMOS sensor architecture has been developed that permits high-fill-factor photodiodes to be placed at the silicon surface without the need for backside thinning. The photodiode access provided by this architecture permits application of highly-effective anti-reflection coatings on the input surface and construction of a mirror inside the silicon below the photodiodes to effectively double the optical thickness of the silicon charge generation volume. Secondary benefits of this architecture include prevention of light from reaching the CMOS circuitry under the photodiodes, improvement of near-infrared quantum efficiency, and reduction in optical artifacts caused by reflections from the sensor surface. Utilizing these techniques, a sensor is being constructed with 4096 x 4096 pixels 4.8 μm square with 95% fill factor backed by a mirror tuned to the 400-700 nm visible band and a front-surface anti-reflectance coating. The quantum efficiency is expected to exceed 80% through the visible and the global shutter extinction ratio should exceed 106:1. The sensors have been fabricated and first test data is due in February 2011.

  6. Optimization of precision localization microscopy using CMOS camera technology

    NASA Astrophysics Data System (ADS)

    Fullerton, Stephanie; Bennett, Keith; Toda, Eiji; Takahashi, Teruo

    2012-02-01

    Light microscopy imaging is being transformed by the application of computational methods that permit the detection of spatial features below the optical diffraction limit. Successful localization microscopy (STORM, dSTORM, PALM, PhILM, etc.) relies on the precise position detection of fluorescence emitted by single molecules using highly sensitive cameras with rapid acquisition speeds. Electron multiplying CCD (EM-CCD) cameras are the current standard detector for these applications. Here, we challenge the notion that EM-CCD cameras are the best choice for precision localization microscopy and demonstrate, through simulated and experimental data, that certain CMOS detector technology achieves better localization precision of single molecule fluorophores. It is well-established that localization precision is limited by system noise. Our findings show that the two overlooked noise sources relevant for precision localization microscopy are the shot noise of the background light in the sample and the excess noise from electron multiplication in EM-CCD cameras. At low light conditions (< 200 photons/fluorophore) with no optical background, EM-CCD cameras are the preferred detector. However, in practical applications, optical background noise is significant, creating conditions where CMOS performs better than EM-CCD. Furthermore, the excess noise of EM-CCD is equivalent to reducing the information content of each photon detected which, in localization microscopy, reduces the precision of the localization. Thus, new CMOS technology with 100fps, <1.3 e- read noise and high QE is the best detector choice for super resolution precision localization microscopy.

  7. CMOS integration of inkjet-printed graphene for humidity sensing

    PubMed Central

    Santra, S.; Hu, G.; Howe, R. C. T.; De Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10–80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

  8. Fully depleted, thick, monolithic CMOS pixels with high quantum efficiency

    NASA Astrophysics Data System (ADS)

    Clarke, A.; Stefanov, K.; Johnston, N.; Holland, A.

    2015-04-01

    The Centre for Electronic Imaging (CEI) has an active programme of evaluating and designing Complementary Metal-Oxide Semiconductor (CMOS) image sensors with high quantum efficiency, for applications in near-infrared and X-ray photon detection. This paper describes the performance characterisation of CMOS devices made on a high resistivity 50 μ m thick p-type substrate with a particular focus on determining the depletion depth and the quantum efficiency. The test devices contain 8 × 8 pixel arrays using CCD-style charge collection, which are manufactured in a low voltage CMOS process by ESPROS Photonics Corporation (EPC). Measurements include determining under which operating conditions the devices become fully depleted. By projecting a spot using a microscope optic and a LED and biasing the devices over a range of voltages, the depletion depth will change, causing the amount of charge collected in the projected spot to change. We determine if the device is fully depleted by measuring the signal collected from the projected spot. The analysis of spot size and shape is still under development.

  9. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

    SciTech Connect

    Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

    2008-08-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

  10. Increasing Linear Dynamic Range of a CMOS Image Sensor

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2007-01-01

    A generic design and a corresponding operating sequence have been developed for increasing the linear-response dynamic range of a complementary metal oxide/semiconductor (CMOS) image sensor. The design provides for linear calibrated dual-gain pixels that operate at high gain at a low signal level and at low gain at a signal level above a preset threshold. Unlike most prior designs for increasing dynamic range of an image sensor, this design does not entail any increase in noise (including fixed-pattern noise), decrease in responsivity or linearity, or degradation of photometric calibration. The figure is a simplified schematic diagram showing the circuit of one pixel and pertinent parts of its column readout circuitry. The conventional part of the pixel circuit includes a photodiode having a small capacitance, CD. The unconventional part includes an additional larger capacitance, CL, that can be connected to the photodiode via a transfer gate controlled in part by a latch. In the high-gain mode, the signal labeled TSR in the figure is held low through the latch, which also helps to adapt the gain on a pixel-by-pixel basis. Light must be coupled to the pixel through a microlens or by back illumination in order to obtain a high effective fill factor; this is necessary to ensure high quantum efficiency, a loss of which would minimize the efficacy of the dynamic- range-enhancement scheme. Once the level of illumination of the pixel exceeds the threshold, TSR is turned on, causing the transfer gate to conduct, thereby adding CL to the pixel capacitance. The added capacitance reduces the conversion gain, and increases the pixel electron-handling capacity, thereby providing an extension of the dynamic range. By use of an array of comparators also at the bottom of the column, photocharge voltages on sampling capacitors in each column are compared with a reference voltage to determine whether it is necessary to switch from the high-gain to the low-gain mode. Depending upon

  11. Investigation of CMOS photodiodes integrated on an ASIC by a 0.5-µm analog CMOS process

    NASA Astrophysics Data System (ADS)

    Luo, H.; Ricklefs, U.; Hillmer, H.

    2010-04-01

    The characteristics of photodiodes integrated on CMOS ASICs depend on wavelength of radiation, structure of the photodiode itself and the parameters of the process of production. In this paper, the influence of the structure of integrated CMOS photodiodes produced in a standard 0.5 μm mixed signal CMOS process on the sensitivity is described. These photodiodes are used as image sensor elements arranged in an array for noncontact optoelectronic measurements. Models of integrated photodiodes distinguish the lateral and the vertical region of the photodiodes. The standard 0.5 μm CMOS process offers three types of pn-junctions: n+/p-substrate, p+/n-well and n-well/p-substrate. Based on our previous research and on the results from other authors the p+/n-well is chosen due to its better sensitivity and isolation against other structures. The local sensitivity is measured with a scanning setup by applying a diffraction limited spot spot of light on the surface of the diodes. Independent of the wavelength of radiation the charge carriers are generated mainly in the lateral region and not - as expected - in the vertical region. The maximum value of the local sensitivity is found in photodiodes with subdivided p+ regions showing a distance of 1.5 μm between these regions in the space between these two adjacent p+ regions. This local sensitivity is three times smaller than that of a reference PIN photodiode. According to this result, the new photodiodes will be constructed with optimized geometries. All examined structures of this type of photodiodes show a maximal spectral sensitivity in the range of 650 nm - 700 nm.

  12. CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

    NASA Astrophysics Data System (ADS)

    Davidson, Bradley Darren

    This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different

  13. High gain CMOS image sensor design and fabrication on SOI and bulk technology

    NASA Astrophysics Data System (ADS)

    Zhang, Weiquan

    2000-12-01

    The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force in industry. Silicon on insulator (SOI) is considered as the coming mainstream technology. It challenges the current bulk CMOS technology because of its reduced power consumption, high speed, radiation hardness etc. Moving the CMOS imager from the bulk to the SOI substrate will benefit from these intrinsic advantages. In addition, the blooming and the cross-talk between the pixels of the sensor array can be ideally eliminated, unlike those on the bulk technology. Though there are many advantages to integrate CMOS imager on SOI, the problem is that the top silicon film is very thin, such as 2000Å. Many photons can just pass through this layer without being absorbed. A good photo-detector on SOI is critical to integrate SOI CMOS imagers. In this thesis, several methods to make photo-detectors on SOI substrate are investigated. A floating gate MOSFET on SOI substrate, operating in its lateral bipolar mode, is photon sensitive. One step further, the SOI MOSFET gate and body can be tied together. The positive feedback between the body and gate enables this device have a high responsivity. A similar device can be found on the bulk CMOS technology: the gate-well tied PMOSFET. A 32 x 32 CMOS imager is designed and characterized using such a device as the light-sensing element. I also proposed the idea of building hybrid active pixels on SOI substrate. Such devices are fabricated and characterized. The work here represents my contribution on the CMOS imager, especially moving the CMOS imager onto the SOI substrate.

  14. Adaptive oxide electronics: A review

    NASA Astrophysics Data System (ADS)

    Ha, Sieu D.; Ramanathan, Shriram

    2011-10-01

    Novel information processing techniques are being actively explored to overcome fundamental limitations associated with CMOS scaling. A new paradigm of adaptive electronic devices is emerging that may reshape the frontiers of electronics and enable new modalities. Creating systems that can learn and adapt to various inputs has generally been a complex algorithm problem in information science, albeit with wide-ranging and powerful applications from medical diagnosis to control systems. Recent work in oxide electronics suggests that it may be plausible to implement such systems at the device level, thereby drastically increasing computational density and power efficiency and expanding the potential for electronics beyond Boolean computation. Intriguing possibilities of adaptive electronics include fabrication of devices that mimic human brain functionality: the strengthening and weakening of synapses emulated by electrically, magnetically, thermally, or optically tunable properties of materials.In this review, we detail materials and device physics studies on functional metal oxides that may be utilized for adaptive electronics. It has been shown that properties, such as resistivity, polarization, and magnetization, of many oxides can be modified electrically in a non-volatile manner, suggesting that these materials respond to electrical stimulus similarly as a neural synapse. We discuss what device characteristics will likely be relevant for integration into adaptive platforms and then survey a variety of oxides with respect to these properties, such as, but not limited to, TaOx, SrTiO3, and Bi4-xLaxTi3O12. The physical mechanisms in each case are detailed and analyzed within the framework of adaptive electronics. We then review theoretically formulated and current experimentally realized adaptive devices with functional oxides, such as self-programmable logic and neuromorphic circuits. Finally, we speculate on what advances in materials physics and engineering may

  15. NV-CMOS HD camera for day/night imaging

    NASA Astrophysics Data System (ADS)

    Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

    2014-06-01

    SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE <90%), as well as projected low noise (<2h+) readout. Power consumption is minimized in the camera, which operates from a single 5V supply. The NVCMOS HD camera provides a substantial reduction in size, weight, and power (SWaP) , ideal for SWaP-constrained day/night imaging platforms such as UAVs, ground vehicles, fixed mount surveillance, and may be reconfigured for mobile soldier operations such as night vision goggles and weapon sights. In addition the camera with the NV-CMOS HD imager is suitable for high performance digital cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

  16. A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

    PubMed Central

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2012-01-01

    Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

  17. 77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-12-14

    ... (``CalTech''). 77 FR 33488 (June 6, 2012). The complaint alleged violations of section 337 of the Tariff... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations... importation, and the sale within the United States after importation of certain CMOS image sensors...

  18. 77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-06

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to... States after importation of certain CMOS image sensors and products containing same by reason of... image sensors and products containing same that infringe one or more of claims 1 and 2 of the...

  19. CMOS IC fault models, physical defect coverage, and I sub DDQ testing

    SciTech Connect

    Fritzemeier, R.R.; Soden, J.M. ); Hawkins, C.F. . Dept. of Electrical and Computer Engineering)

    1991-01-01

    The development of the stuck-at fault (SAF) model is reviewed with emphasis on its relationship to CMOS integrated circuit (IC) technologies. The ability of the SAF model to represent common physical defects in CMOS ICs is evaluated. A test strategy for defect detection, which includes I{sub DDQ} testing is presented. 16 refs., 4 figs.

  20. Silicide Nanowires for Low-Resistance CMOS Transistor Contacts.

    NASA Astrophysics Data System (ADS)

    Zollner, Stefan

    2007-03-01

    Transition metal (TM) silicide nanowires are used as contacts for modern CMOS transistors. (Our smallest wires are ˜20 nm thick and ˜50 nm wide.) While much research on thick TM silicides was conducted long ago, materials perform differently at the nanoscale. For example, the usual phase transformation sequences (e.g., Ni, Ni2Si, NiSi, NiSi2) for the reaction of thick metal films on Si no longer apply to nanostructures, because the surface and interface energies compete with the bulk energy of a given crystal structure. Therefore, a NiSi film will agglomerate into hemispherical droplets of NiSi by annealing before it reaches the lowest-energy (NiSi2) crystalline structure. These dynamics can be tuned by addition of impurities (such as Pt in Ni). The Si surface preparation is also a more important factor for nanowires than for silicidation of thick TM films. Ni nanowires formed on Si surfaces that were cleaned and amorphized by sputtering with Ar ions have a tendency to form NiSi2 pyramids (``spikes'') even at moderate temperatures (˜400^oC), while similar Ni films formed on atomically clean or hydrogen-terminated Si form uniform NiSi nanowires. Another issue affecting TM silicides is the barrier height between the silicide contact and the silicon transistor. For most TM silicides, the Fermi level of the silicide is aligned with the center of the Si band gap. Therefore, silicide contacts experience Schottky barrier heights of around 0.5 eV for both n-type and p-type Si. The resulting contact resistance becomes a significant term for the overall resistance of modern CMOS transistors. Lowering this contact resistance is an important goal in CMOS research. New materials are under investigation (for example PtSi, which has a barrier height of only 0.3 eV to p-type Si). This talk will describe recent results, with special emphasis on characterization techniques and electrical testing useful for the development of silicide nanowires for CMOS contacts. In collaboration

  1. A high speed CMOS A/D converter

    NASA Technical Reports Server (NTRS)

    Wiseman, Don R.; Whitaker, Sterling R.

    1992-01-01

    This paper presents a high speed analog-to-digital (A/D) converter. The converter is a 7 bit flash converter with one half LSB accuracy. Typical parts will function at approximately 200 MHz. The converter uses a novel comparator circuit that is shown to out perform more traditional comparators, and thus increases the speed of the converter. The comparator is a clocked, precharged circuit that offers very fast operation with a minimal offset voltage (2 mv). The converter was designed using a standard 1 micron digital CMOS process and is 2,244 microns by 3,972 microns.

  2. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    PubMed Central

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  3. Performance Analysis of Visible Light Communication Using CMOS Sensors

    PubMed Central

    Do, Trong-Hop; Yoo, Myungsik

    2016-01-01

    This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis. PMID:26938535

  4. Silicon nanowires integrated with CMOS circuits for biosensing application

    NASA Astrophysics Data System (ADS)

    Jayakumar, G.; Asadollahi, A.; Hellström, P.-E.; Garidis, K.; Östling, M.

    2014-08-01

    We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

  5. The DUV Stability of Superlattice-Doped CMOS Detector Arrays

    NASA Technical Reports Server (NTRS)

    Hoenk, M. E.; Carver, A. G.; Jones, T.; Dickie, M.; Cheng, P.; Greer, H. F.; Nikzad, S.; Sgro, J.; Tsur, S.

    2013-01-01

    JPL and Alacron have recently developed a high performance, DUV camera with a superlattice doped CMOS imaging detector. Supperlattice doped detectors achieve nearly 100% internal quantum efficiency in the deep and far ultraviolet, and a single layer, Al2O3 antireflection coating enables 64% external quantum efficiency at 263nm. In lifetime tests performed at Applied Materials using 263 nm pulsed, solid state and 193 nm pulsed excimer laser, the quantum efficiency and dark current of the JPL/Alacron camera remained stable to better than 1% precision during long-term exposure to several billion laser pulses, with no measurable degradation, no blooming and no image memory at 1000 fps.

  6. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    PubMed

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-07-10

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  7. 120-MHz BiCMOS superscalar RISC processor

    NASA Astrophysics Data System (ADS)

    Tanaka, Shigeya; Hotta, Takashi; Murabayashi, Fumio; Yamada, Hiromichi; Yoshida, Shoji; Shimamura, Kotaro; Katsura, Koyo; Bandoh, Tadaaki; Ikeda, Koichi; Matsubara, Kenji

    1994-04-01

    A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm x 16.5 mm, and utilizes 3.3 V/0.5 micron BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.

  8. Defect classes: An overdue paradigm for CMOS IC testing

    NASA Astrophysics Data System (ADS)

    Hawkins, C. F.; Soden, J. M.; Righter, A. W.; Ferguson, F. J.

    The IC test industry has struggled for more than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS IC's that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the test strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and test facilities and from public literature. We describe test pattern requirements for each defect class and propose a test paradigm.

  9. Design and optimization of BCCD in CMOS technology

    NASA Astrophysics Data System (ADS)

    Gao, Jing; Li, Yi; Gao, Zhi-yuan; Luo, Tao

    2016-09-01

    This paper optimizes the buried channel charge-coupled device (BCCD) structure fabricated by complementary metal oxide semiconductor (CMOS) technology. The optimized BCCD has advantages of low noise, high integration and high image quality. The charge transfer process shows that interface traps, weak fringing fields and potential well between adjacent gates all cause the decrease of charge transfer efficiency ( CTE). CTE and well capacity are simulated with different operating voltages and gap sizes. CTE can achieve 99.999% and the well capacity reaches up to 25 000 electrons for the gap size of 130 nm and the maximum operating voltage of 3 V.

  10. Extrinsic parameter extraction and RF modelling of CMOS

    NASA Astrophysics Data System (ADS)

    Alam, M. S.; Armstrong, G. A.

    2004-05-01

    An analytical approach for CMOS parameter extraction which includes the effect of parasitic resistance is presented. The method is based on small-signal equivalent circuit valid in all region of operation to uniquely extract extrinsic resistances, which can be used to extend the industry standard BSIM3v3 MOSFET model for radio frequency applications. The verification of the model was carried out through frequency domain measurements of S-parameters and direct time domain measurement at 2.4 GHz in a large signal non-linear mode of operation.

  11. Radiation-hard silicon gate bulk CMOS cell family

    SciTech Connect

    Gibbon, C. F.; Habing, D. H.; Flores, R. S.

    1980-01-01

    A radiation-hardened bulk silicon gate CMOS technology and a topologically simple, high-performance dual-port cell family utilizing this process have been demonstrated. Additional circuits, including a random logic circuit containing 4800 transistors on a 236 x 236 mil die, are presently being designed and processed. Finally, a joint design-process effort is underway to redesign the cell family in reduced design rules; this results in a factor of 2.5 cell size reduction and a factor of 3 decrease in chip interconnect area. Cell performance is correspondingly improved.

  12. Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

    PubMed

    Kazior, Thomas E

    2014-03-28

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  13. Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

    PubMed Central

    Kazior, Thomas E.

    2014-01-01

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  14. Damage effect on CMOS detector irradiated by single-pulse laser

    NASA Astrophysics Data System (ADS)

    Guo, Feng; Zhu, Rongzhen; Wang, Ang; Cheng, Xiang'ai

    2013-09-01

    Imaging systems are widespread observation tools used to fulfill various functions such as recognition, detection and identification. These devices such as CMOS and CCD can be damaged by laser. It is very important to study the damage mechanism of CMOS and CCD. Previous studies focused on the interference and damage of CCD. There were only a few researches on the interaction of CMOS and the laser. In this paper, using a 60ns, 1064 nm single-pulse laser to radiate the front illuminated CMOS detector, the typical experiment phenomena were observed and the corresponding energy density thresholds were measured. According to the experiment phenomena, hard damage process of CMOS can be divided into 3 stages. Based on the structure and working principle of CMOS, studying the damage mechanism of 3 stages by theoretical analysis, point damage was caused by the increase in leakage current due to structural defects resulting from thermal effects, half black line damage and black lines cross damage were caused by signal interruption due to that the device circuit fuses were cut. Enhancing the laser energy density, the damaged area expanded. Even if the laser energy density reached 1.95 J/cm2, black lines has covered most of the detector pixels, the detector still not completely lapsed, the undamaged area can imaging due to that pixels of CMOS were separated with each other. Experiments on CMOS by laser pulses at the wavelength of 1064 nm and the pulse duration in 25ps was carried out, then the thresholds with different pulse durations were measured and compared. Experiments on CMOS by fs pulsed laser at the frequency of 1 Hz, 10 Hz and 1000 Hz were carried out, respectively, the results showed that a high-repetition-rate laser was easier to damage CMOS compared to single-shot laser.

  15. Adaptive behaviour of silicon oxide memristive nanostructures

    NASA Astrophysics Data System (ADS)

    Korolev, D. S.; Mikhaylov, A. N.; Belov, A. I.; Sergeev, V. A.; Antonov, I. N.; Gorshkov, O. N.; Tetelbaum, D. I.

    2016-08-01

    The response to electrical pulses of various parameters has been studied for the CMOS-compatible memristive nanostructures on the basis of silicon oxide demonstrating reproducible resistive switching. It is established that an increase in the amplitude or width of a single programming pulse is followed by the gradual decrease in the device resistivity. By applying periodic pulse sequences of different polarity it is possible to obtain both lower and higher resistance states. This adaptive behavior is analogous to synaptic plasticity and considered as one of the main conditions for the application of memristive devices in neuromorphic systems and synaptic electronics.

  16. CMOS mm-wave transceivers for Gbps wireless communication

    NASA Astrophysics Data System (ADS)

    Baoyong, Chi; Zheng, Song; Lixue, Kuang; Haikun, Jia; Xiangyu, Meng; Zhihua, Wang

    2016-07-01

    The challenges in the design of CMOS millimeter-wave (mm-wave) transceiver for Gbps wireless communication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the bandwidth expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier (PA) and self-healing technique are introduced to improve the PA's average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers. Project supported in part by the National Natural Science Foundation of China (No. 61331003).

  17. Illumination robust change detection with CMOS imaging sensors

    NASA Astrophysics Data System (ADS)

    Rengarajan, Vijay; Gupta, Sheetal B.; Rajagopalan, A. N.; Seetharaman, Guna

    2015-05-01

    Change detection between two images in the presence of degradations is an important problem in the computer vision community, more so for the aerial scenario which is particularly challenging. Cameras mounted on moving platforms such as aircrafts or drones are subject to general six-dimensional motion as the motion is not restricted to a single plane. With CMOS cameras increasingly in vogue due to their low power consumption, the inevitability of rolling-shutter (RS) effect adds to the challenge. This is caused by sequential exposure of rows in CMOS cameras unlike conventional global shutter cameras where all pixels are exposed simultaneously. The RS effect is particularly pronounced in aerial imaging since each row of the imaging sensor is likely to experience a different motion. For fast-moving platforms, the problem is further compounded since the rows are also affected by motion blur. Moreover, since the two images are shot at different times, illumination differences are common. In this paper, we propose a unified computational framework that elegantly exploits the scarcity constraint to deal with the problem of change detection in images degraded by RS effect, motion blur as well as non-global illumination differences. We formulate an optimization problem where each row of the distorted image is approximated as a weighted sum of the corresponding rows in warped versions of the reference image due to camera motion within the exposure period to account for geometric as well as photometric differences. The method has been validated on both synthetic and real data.

  18. A CMOS smart temperature and humidity sensor with combined readout.

    PubMed

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA. PMID:25230305

  19. Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors

    PubMed Central

    Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5–200 mT. PMID:24172287

  20. A CMOS Smart Temperature and Humidity Sensor with Combined Readout

    PubMed Central

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 μA. PMID:25230305

  1. High-Q CMOS-integrated photonic crystal microcavity devices.

    PubMed

    Mehta, Karan K; Orcutt, Jason S; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J

    2014-01-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300-9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems.

  2. High-Q CMOS-integrated photonic crystal microcavity devices

    NASA Astrophysics Data System (ADS)

    Mehta, Karan K.; Orcutt, Jason S.; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J.

    2014-02-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300-9,300 one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems.

  3. CMOS: Efficient Clustered Data Monitoring in Sensor Networks

    PubMed Central

    2013-01-01

    Tiny and smart sensors enable applications that access a network of hundreds or thousands of sensors. Thus, recently, many researchers have paid attention to wireless sensor networks (WSNs). The limitation of energy is critical since most sensors are battery-powered and it is very difficult to replace batteries in cases that sensor networks are utilized outdoors. Data transmission between sensor nodes needs more energy than computation in a sensor node. In order to reduce the energy consumption of sensors, we present an approximate data gathering technique, called CMOS, based on the Kalman filter. The goal of CMOS is to efficiently obtain the sensor readings within a certain error bound. In our approach, spatially close sensors are grouped as a cluster. Since a cluster header generates approximate readings of member nodes, a user query can be answered efficiently using the cluster headers. In addition, we suggest an energy efficient clustering method to distribute the energy consumption of cluster headers. Our simulation results with synthetic data demonstrate the efficiency and accuracy of our proposed technique. PMID:24459444

  4. Fabrication of a miniature CMOS-based optical biosensor.

    PubMed

    Ho, Wei-Jen; Chen, Jung-Sheng; Ker, Ming-Dou; Wu, Tung-Kung; Wu, Chung-Yu; Yang, Yuh-Shyong; Li, Yaw-Kuen; Yuan, Chiun-Jye

    2007-06-15

    This work presents a novel, miniature optical biosensor by immobilizing horseradish peroxidase (HRP) or the HRP/glucose oxidase (GOx) coupled enzyme pair on a CMOS photosensing chip with a detection area of 0.5 mm x 0.5 mm. A highly transparent TEOS/PDMS Ormosil is used to encapsulate and immobilize enzymes on the surface of the photosensor. Interestingly, HRP-catalyzed luminol luminescence can be detected in real time on optical H(2)O(2) and glucose biosensors. The minimum reaction volume of the developed optical biosensors is 10 microL. Both optical H(2)O(2) and glucose biosensors have an optimal operation temperature and pH of 20-25 degrees C and pH 8.4, respectively. The linear dynamic range of optical H(2)O(2) and glucose biosensors is 0.05-20 mM H(2)O(2) and 0.5-20 mM glucose, respectively. The miniature optical glucose biosensor also exhibits good reproducibility with a relative standard deviation of 4.3%. Additionally, ascorbic acid and uric acid, two major interfering substances in the serum during electrochemical analysis, cause only slight interference with the fabricated optical glucose biosensor. In conclusion, the CMOS-photodiode-based optical biosensors proposed herein have many advantages, such as a short detection time, a small sample volume requirement, high reproducibility and wide dynamic range.

  5. BiCMOS-integrated photodiode exploiting drift enhancement

    NASA Astrophysics Data System (ADS)

    Swoboda, Robert; Schneider-Hornstein, Kerstin; Wille, Holger; Langguth, Gernot; Zimmermann, Horst

    2014-08-01

    A vertical pin photodiode with a thick intrinsic layer is integrated in a 0.5-μm BiCMOS process. The reverse bias of the photodiode can be increased far above the circuit supply voltage, enabling a high-drift velocity. Therefore, a highly efficient and very fast photodiode is achieved. Rise/fall times down to 94 ps/141 ps at a bias of 17 V were measured for a wavelength of 660 nm. The bandwidth was increased from 1.1 GHz at 3 V to 2.9 GHz at 17 V due to the drift enhancement. A quantum efficiency of 85% with a 660-nm light was verified. The technological measures to avoid negative effects on an NPN transistor due to the Kirk effect caused by the low-doped I-layer epitaxy are described. With a high-energy collector implant, the NPN transit frequency is held above 20 GHz. CMOS devices are unaffected. This photodiode is suitable for a wide variety of high-sensitivity optical sensor applications, for optical communications, for fiber-in-the-home applications, and for optical interconnects.

  6. IR CMOS: near infrared enhanced digital imaging (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Pralle, Martin U.; Carey, James E.; Joy, Thomas; Vineis, Chris J.; Palsule, Chintamani

    2015-08-01

    SiOnyx has demonstrated imaging at light levels below 1 mLux (moonless starlight) at video frame rates with a 720P CMOS image sensor in a compact, low latency camera. Low light imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancements are achieved by applying Black Silicon, SiOnyx's proprietary ultrafast laser semiconductor processing technology. In the near infrared, silicon's native indirect bandgap results in low absorption coefficients and long absorption lengths. The Black Silicon nanostructured layer fundamentally disrupts this paradigm by enhancing the absorption of light within a thin pixel layer making 5 microns of silicon equivalent to over 300 microns of standard silicon. This results in a demonstrate 10 fold improvements in near infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see spot. Imaging performance metrics will be discussed. Demonstrated performance characteristics: Pixel size : 5.6 and 10 um Array size: 720P/1.3Mpix Frame rate: 60 Hz Read noise: 2 ele/pixel Spectral sensitivity: 400 to 1200 nm (with 10x QE at 1064nm) Daytime imaging: color (Bayer pattern) Nighttime imaging: moonless starlight conditions 1064nm laser imaging: daytime imaging out to 2Km

  7. Single donor electronics and quantum functionalities with advanced CMOS technology

    NASA Astrophysics Data System (ADS)

    Jehl, Xavier; Niquet, Yann-Michel; Sanquer, Marc

    2016-03-01

    Recent progresses in quantum dots technology allow fundamental studies of single donors in various semiconductor nanostructures. For the prospect of applications figures of merits such as scalability, tunability, and operation at relatively large temperature are of prime importance. Beyond the case of actual dopant atoms in a host crystal, similar arguments hold for small enough quantum dots which behave as artificial atoms, for instance for single spin control and manipulation. In this context, this experimental review focuses on the silicon-on-insulator devices produced within microelectronics facilities with only very minor modifications to the current industrial CMOS process and tools. This is required for scalability and enabled by shallow trench or mesa isolation. It also paves the way for real integration with conventional circuits, as illustrated by a nanoscale device coupled to a CMOS circuit producing a radio-frequency drive on-chip. At the device level we emphasize the central role of electrostatics in etched silicon nanowire transistors, which allows to understand the characteristics in the full range from zero to room temperature.

  8. CMOS-TDI detector technology for reconnaissance application

    NASA Astrophysics Data System (ADS)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  9. A 50Mbit/Sec. CMOS Video Linestore System

    NASA Astrophysics Data System (ADS)

    Jeung, Yeun C.

    1988-10-01

    This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

  10. A CMOS Imager with Focal Plane Compression using Predictive Coding

    NASA Technical Reports Server (NTRS)

    Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

    2007-01-01

    This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

  11. Electronic-photonic integrated circuits on the CMOS platform

    NASA Astrophysics Data System (ADS)

    Kimerling, L. C.; Ahn, D.; Apsel, A. B.; Beals, M.; Carothers, D.; Chen, Y.-K.; Conway, T.; Gill, D. M.; Grove, M.; Hong, C.-Y.; Lipson, M.; Liu, J.; Michel, J.; Pan, D.; Patel, S. S.; Pomerene, A. T.; Rasras, M.; Sparacin, D. K.; Tu, K.-Y.; White, A. E.; Wong, C. W.

    2006-02-01

    The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

  12. Single phase dynamic CMOS PLA using charge sharing technique

    NASA Technical Reports Server (NTRS)

    Dhong, Y. B.; Tsang, C. P.

    1991-01-01

    A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

  13. A CMOS smart temperature and humidity sensor with combined readout.

    PubMed

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-09-16

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

  14. Improvement to the signaling interface for CMOS pixel sensors

    NASA Astrophysics Data System (ADS)

    Shi, Zhan; Tang, Zhenan; Feng, Chong; Cai, Hong

    2016-10-01

    The development of the readout speed of CMOS pixel sensors (CPS) is motivated by the demanding requirements of future high energy physics (HEP) experiments. As the interface between CPS and the data acquisition (DAQ) system, which inputs clock from the DAQ system and outputs data from CPS, the signaling interface should also be improved in terms of data rates. Meanwhile, the power consumption of the signaling interface should be maintained as low as possible. Consequently, a reduced swing differential signaling (RSDS) driver was adopted instead of a low-voltage differential signaling (LVDS) driver to transmit data from CPS to the DAQ system. In order to increase the capability of data rates, a serial source termination technique was employed. A LVDS/RSDS receiver was employed for transmitting clock from the DAQ system to CPS. A new method of generating hysteresis and a special current comparator were used to achieve a higher speed with lower power consumption. The signaling interface was designed and submitted for fabrication in a 0.18 μm CMOS image sensor (CIS) process. Measurement results indicate that the RSDS driver and the LVDS receiver can operate correctly at a data rate of 2 Gb/s with a power consumption of 19.1 mW.

  15. CMOS compatible fabrication of 3D photonic crystals by nanoimprint lithography

    NASA Astrophysics Data System (ADS)

    Eibelhuber, M.; Uhrmann, T.; Glinsner, T.

    2015-03-01

    Nanoimprinting techniques are an attractive solution for next generation lithography methods for several areas including photonic devices. A variety of potential applications have been demonstrated using nanoimprint lithography (NIL) (e.g. SAW devices, vias and contact layers with dual damascene imprinting process, Bragg structures, patterned media) [1,2]. Nanoimprint lithography is considered for bridging the gap from R and D to high volume manufacturing. In addition, it is capable to adapt to the needs of the fragmented and less standardized photonic market easily. In this work UV-NIL has been selected for the fabrication process of 3D-photonic crystals. It has been shown that UVNIL using a multiple layer approach is well suited to fabricate a 3D woodpile photonic crystal. The necessary alignment accuracies below 100nm were achieved using a simple optical method. In order to obtain sufficient alignment of the stacks to each other, a two stage alignment process is performed: at first proximity alignment is done followed by the Moiré alignment in soft contact with the substrate. Multiple steps of imprinting, etching, Si deposition and chemical mechanical polishing were implemented to create high quality 3D photonic crystals with up to 5 layers. This work has proven the applicability of nanoimprint lithography in a CMOS compatible process on 3D photonic crystals with alignment accuracy down to 100nm. Optimizing the processes will allow scaling up these structures on full wafers while still meeting the requirements of the designated devices.

  16. Next-generation CMOS active pixel sensors for satellite hybrid optical communications/imaging sensor systems

    NASA Astrophysics Data System (ADS)

    Stirbl, Robert C.; Pain, Bedabrata; Cunningham, Thomas J.; Hancock, Bruce R.; McCarty, Kenneth P.

    1998-12-01

    Given the current choices of (1) an ever increasing population of large numbers of satellites in low-earth orbit (LEO) constellations for commercial and military global coverage systems, or (2) the alternative of smaller count geosynchronous satellite system constellations in high-earth (HEO), of higher cost and complexity, a number of commercial communications and military operations satellite systems designers are investigating the potential advantages and issues of operating in the mid-earth orbit altitudes (MEO) (between LEO and HEO). At these MEO altitudes both total dose and displacement damage can be traded against the system advantages of fewer satellites required. With growing demand for higher bandwidth communication for real-time earth observing satellite sensor systems, and NASA's interplanetary and deep space virtual unmanned exploration missions in stressing radiation environments, JPL is developing the next generation of smart sensors to address these new requirements of: low-cost, high bandwidth, miniaturization, ultra low-power and mission environment ruggedness. Radiation hardened/tolerant Active Pixel Sensor CMOS imagers that can be adaptively windowed with low power, on-chip control, timing, digital output and provide data-channel efficient on-chip compression, high bandwidth optical communications links are being designed and investigated to reduce size, weight and cost for common optics/hybrid architectures.

  17. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    NASA Astrophysics Data System (ADS)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

    2016-09-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  18. Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

    NASA Technical Reports Server (NTRS)

    Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

    2009-01-01

    In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

  19. High-performance VGA-resolution digital color CMOS imager

    NASA Astrophysics Data System (ADS)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be

  20. Adaptive compressive sensing camera

    NASA Astrophysics Data System (ADS)

    Hsu, Charles; Hsu, Ming K.; Cha, Jae; Iwamura, Tomo; Landa, Joseph; Nguyen, Charles; Szu, Harold

    2013-05-01

    We have embedded Adaptive Compressive Sensing (ACS) algorithm on Charge-Coupled-Device (CCD) camera based on the simplest concept that each pixel is a charge bucket, and the charges comes from Einstein photoelectric conversion effect. Applying the manufactory design principle, we only allow altering each working component at a minimum one step. We then simulated what would be such a camera can do for real world persistent surveillance taking into account of diurnal, all weather, and seasonal variations. The data storage has saved immensely, and the order of magnitude of saving is inversely proportional to target angular speed. We did design two new components of CCD camera. Due to the matured CMOS (Complementary metal-oxide-semiconductor) technology, the on-chip Sample and Hold (SAH) circuitry can be designed for a dual Photon Detector (PD) analog circuitry for changedetection that predicts skipping or going forward at a sufficient sampling frame rate. For an admitted frame, there is a purely random sparse matrix [Φ] which is implemented at each bucket pixel level the charge transport bias voltage toward its neighborhood buckets or not, and if not, it goes to the ground drainage. Since the snapshot image is not a video, we could not apply the usual MPEG video compression and Hoffman entropy codec as well as powerful WaveNet Wrapper on sensor level. We shall compare (i) Pre-Processing FFT and a threshold of significant Fourier mode components and inverse FFT to check PSNR; (ii) Post-Processing image recovery will be selectively done by CDT&D adaptive version of linear programming at L1 minimization and L2 similarity. For (ii) we need to determine in new frames selection by SAH circuitry (i) the degree of information (d.o.i) K(t) dictates the purely random linear sparse combination of measurement data a la [Φ]M,N M(t) = K(t) Log N(t).

  1. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

    PubMed

    Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

    2012-01-11

    Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme.

  2. Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction

    PubMed Central

    Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

    2015-01-01

    A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology. PMID:26184222

  3. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    PubMed Central

    Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

    2014-01-01

    Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

  4. An Approach for Self-Timed Synchronous CMOS Circuit Design

    NASA Technical Reports Server (NTRS)

    Walker, Alvernon; Lala, Parag K.

    2001-01-01

    In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.

  5. Development of a radiation-hard CMOS process

    NASA Technical Reports Server (NTRS)

    Power, W. L.

    1983-01-01

    It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

  6. Micro-lens maker equation of a CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Wu, Yang

    2007-09-01

    The demand of a large resolution CMOS image sensor (CIS) in a small package drives the pixel pitch size down to the neighborhood of 2 μm. Double-micro-lens (ML) structure is a promising technology to obtain the high focusing capability required by such a small pixel. In this work, an optical model of a double-ML is derived from the well-known lens maker equation. This model predicts the critical back focal length (BFL) and the effective focal length (EFL) of the double-ML embedded in the Back-End-Of-The-Line (BEOL) stack. Explained by this model, a design guideline is provided to optimize the amount of light collected by the photo diode area for a good quantum efficiency (QE), which is crucial to the sensitivity of the sensor.

  7. Rapid Bacterial Detection via an All-Electronic CMOS Biosensor

    PubMed Central

    Nikkhoo, Nasim; Cumby, Nichole; Gulak, P. Glenn; Maxwell, Karen L.

    2016-01-01

    The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections. PMID:27618185

  8. A 20 MHz CMOS reorder buffer for a superscalar microprocessor

    NASA Technical Reports Server (NTRS)

    Lenell, John; Wallace, Steve; Bagherzadeh, Nader

    1992-01-01

    Superscalar processors can achieve increased performance by issuing instructions out-of-order from the original sequential instruction stream. Implementing an out-of-order instruction issue policy requires a hardware mechanism to prevent incorrectly executed instructions from updating register values. A reorder buffer can be used to allow a superscalar processor to issue instructions out-of-order and maintain program correctness. This paper describes the design and implementation of a 20MHz CMOS reorder buffer for superscalar processors. The reorder buffer is designed to accept and retire two instructions per cycle. A full-custom layout in 1.2 micron has been implemented, measuring 1.1058 mm by 1.3542 mm.

  9. Triple inverter pierce oscillator circuit suitable for CMOS

    DOEpatents

    Wessendorf; Kurt O.

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  10. An improved equivalent simulation model for CMOS integrated Hall plates.

    PubMed

    Xu, Yue; Pan, Hong-Bin

    2011-01-01

    An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model's simulation results are in good agreement with the classic experimental results reported in the literature.

  11. An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates

    PubMed Central

    Xu, Yue; Pan, Hong-Bin

    2011-01-01

    An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature. PMID:22163955

  12. Operational characteristics of a CMOS microprocessor system at cryogenic temperatures

    NASA Astrophysics Data System (ADS)

    Deen, M. J.; Chan, C. Y.; Fong, N.

    In this Paper, the variation of the maximum input clock frequency versus temperature of a CMOS microprocessor with a 'piggy-back' EPROM is described. The maximum input frequency for reliable operation increased from 19 to 33 MHz as the temperature was lowered from 300 to 77 K, and there was a corresponding increase in the power dissipated from 18 to 25 mW using a supply of 5 V. The measurements were repeatable even after thermal cycling more than 10 times and showed no hysteresis on cooling down to 77 K or warming up to 300 K. The results obtained can be qualitatively explained as due to a combination of effects including the increase in the carriers' mobilities, the decrease in junction capacitance, and the decrease in the interconnect resistance with decreasing temperature.

  13. Accelerated life testing effects on CMOS microcircuit characteristics

    NASA Technical Reports Server (NTRS)

    1980-01-01

    The 250 C, 200C and 125C accelerated tests are described. The wear-out distributions from the 250 and 200 C tests were used to estimate the activation energy between the two test temperatures. The duration of the 125 C test was not sufficient to bring the test devices into the wear-out region. It was estimated that, for the most complex of the three devices types, the activation energy between 200 C and 125 C should be at least as high as that between 250 C and 200 C. The practicality of the use of high temperature for the accelerated life tests from the point of view of durability of equipment is assessed. Guidlines for the development of accelerated life-test conditions are proposed. The use of the silicon nitride overcoat to improve the high temperature accelerated life-test characteristics of CMOS microcircuits is described.

  14. State assignment approach to asynchronous CMOS circuit design

    NASA Astrophysics Data System (ADS)

    Kantabutra, Vitit; Andreou, Andreas G.

    1994-04-01

    We present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching events is reduced and dynamic power dissipation may also be reduced. Our approach is suitable for asynchronous sequential circuits that are designed from flow tables or state transition diagrams. The proposed approach may also be useful for designing synchronous circuits, but explorations into the subject of clock power would be necessary to determine its usefulness.

  15. Failure analysis of a half-micron CMOS IC technology

    SciTech Connect

    Liang, A.Y.; Tangyunyong, P.; Bennett, R.S.; Flores, R.S.

    1996-08-01

    We present the results of recent failure analysis of an advanced, 0.5 {mu}m, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

  16. Variation in SEU sensitivity of dose-imprinted CMOS SRAMs

    NASA Technical Reports Server (NTRS)

    Stassinopoulos, E. G.; Brucker, G. J.; Van Gunten, O.; Kim, H. S.

    1989-01-01

    The authors report on an experimental study of dose-induced changes in SEU (single-event-upset) sensitivity of CMOS static RAMs. Two time regimes were investigated following exposure of memories to cobalt-60 gamma rays: the near term, within a few hours after exposure, and the long term, after many days. Samples were irradiated both at room and at liquid nitrogen temperatures. The latter procedure was used in order to freeze in the damage state until SEU measurements could be made prior to annealing. Results show that memories damaged by dose are more sensitive to upsets by heavy ions. The induced changes are substantial: threshold linear energy transfer (LET) values decreased by as much as 46 percent and asymptotic cross sections increased by factors of two to four (unannealed samples).

  17. Four channel CMOS codec filter circuit `SICOFIqq-4'

    NASA Astrophysics Data System (ADS)

    Tiefenbacher, M.; Caldera, P.; Dielacher, F.; Hauptmann, J.; Steiner, M.

    1994-08-01

    Cost reduction by integration of complex mixed analog-digital systems on a single chip and an excellent yield to area ratio is a major goal for IC design in the nineties. In this paper, a four-channel codec-filter chip for analog subscriber lines in ISDN-orientated networks is presented, giving an exceptional example for high level system implementation combined with parallel DSP integration and analog circuitry with high performance. The chip combines four analog frontends, digital signal processing realized by different approaches for a sophisticated filter concept in addition with test strategies including digital and analog BIST. The circuit is fabricated in a standard 1-mu CMOS technology, needs a single 5-V power supply, and can easily be programmed to world-wide different country specifications and applications.

  18. Rapid Bacterial Detection via an All-Electronic CMOS Biosensor.

    PubMed

    Nikkhoo, Nasim; Cumby, Nichole; Gulak, P Glenn; Maxwell, Karen L

    2016-01-01

    The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections. PMID:27618185

  19. Interferometric metrology of wafer nanotopography for advanced CMOS process integration

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Koliopoulos, Chris L.; Tang, Shouhong

    2001-12-01

    According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

  20. A CMOS Neural Interface for a Multichannel Vestibular Prosthesis

    PubMed Central

    Hageman, Kristin N.; Kalayjian, Zaven K.; Tejada, Francisco; Chiang, Bryce; Rahman, Mehdi A.; Fridman, Gene Y.; Dai, Chenkai; Pouliquen, Philippe O.; Georgiou, Julio; Della Santina, Charles C.; Andreou, Andreas G.

    2015-01-01

    We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45 ± 0.06 mA with durations as short as 10 µs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68–130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9–16.7°/s for the MVP2 and 2.0–14.2°/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference (t-test, p = 0.034), suggesting that the MVP2A achieves performance at least as good as the larger MVP2. PMID:25974945

  1. High-Q CMOS-integrated photonic crystal microcavity devices

    PubMed Central

    Mehta, Karan K.; Orcutt, Jason S.; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J.

    2014-01-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300–9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems. PMID:24518161

  2. Packaging commercial CMOS chips for lab on a chip integration.

    PubMed

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems. PMID:24682025

  3. Adaptive Management

    EPA Science Inventory

    Adaptive management is an approach to natural resource management that emphasizes learning through management where knowledge is incomplete, and when, despite inherent uncertainty, managers and policymakers must act. Unlike a traditional trial and error approach, adaptive managem...

  4. CMOS color image sensor with overlaid organic photoconductive layers having narrow absorption band

    NASA Astrophysics Data System (ADS)

    Takada, Shunji; Ihama, Mikio; Inuiya, Masafumi; Komatsu, Takashi; Saito, Takahiro

    2007-02-01

    At EI2006, we proposed the CMOS image sensor, which was overlaid with organic photoconductive layers in order to incorporate in it large light-capturing ability of a color film owing to its multiple-layer structure, and demonstrated the pictures taken by the trial product of the proposed CMOS image sensor overlaid with an organic layer having green sensitivity. In this study, we have tried to get the optimized spectral sensitivity for the proposed CMOS image sensor by means of the simulation to minimize the color difference between the original Macbeth chart and its reproduction with the spectral sensitivity of the sensor as a parameter. As a result, it has been confirmed that the proposed CMOS image sensor with multiple-layer structure possesses high potential capability in terms of imagecapturing efficiency when it is provided with the optimized spectral sensitivity.

  5. Design and coupled-effect simulations of CMOS micro gas sensors built on SOI thin membranes

    NASA Astrophysics Data System (ADS)

    Lu, Chih-Cheng; Udrea, Florin; Gardner, Julian W.; Setiadi, D.; Dogaru, T.; Tsai, T. H.; Covington, James A.

    2001-04-01

    This paper describes coupled-effect simulations of smart micro gas-sensors based on standard BiCMOS technology. The smart sensor features very low power consumption, high sensitivity and potential low fabrication cost achieved through full CMOS integration. For the first time the micro heaters are made of active CMOS elements (i.e. MOSFET transistors) and embedded in a thin SOI membrane consisting of Si and SiO2 thin layers. Micro gas-sensors such as chemoresistive, microcalorimeteric and Pd/polymer gate FET sensors can be made using this technology. Full numerical analyses including 3D electro- thermo-mechanical simulations, in particular stress and deflection studies on the SOI membranes are presented. The transducer circuit design and the post-CMOS fabrication process, which includes single sided back-etching, are also reported.

  6. Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

    NASA Technical Reports Server (NTRS)

    Duong, Tuan A. (Inventor)

    2015-01-01

    A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

  7. ''Normal'' tissues from humans exposed to radium contain an alteration in the c-mos locus

    SciTech Connect

    Huberman, E.; Schlenker, R.A.; Hardwick, J.P.

    1989-01-01

    The structures of a number of human proto-oncogenes from persons with internal systemic exposure to radium were analyzed by restriction enzyme digestion and southern blotting of their DNA. Two extra c-mos Eco R1 restriction-fragment-length bands of 5.0 kb and 5.5 kb were found in tissue DNA from six of seven individuals. The extra c-mos bands were detected in DNA from many, but not all, of the tissues of the individuals exposed to radium. Our results suggest that the c-mos restriction-fragment-length alterations (RFLA) found in individuals exposed to radium were induced rather than inherited, are epigenetic in origin, and most likely result from changes in the methylation of bases surrounding the single exon of the c-mos proto-oncogene. 7 refs., 3 figs., 2 tabs.

  8. Development of radiation hard CMOS active pixel sensors for HL-LHC

    NASA Astrophysics Data System (ADS)

    Pernegger, Heinz

    2016-07-01

    New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

  9. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    NASA Astrophysics Data System (ADS)

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  10. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    NASA Astrophysics Data System (ADS)

    Benoit, M.; Bilbao de Mendizabal, J.; Casse, G.; Chen, H.; Chen, K.; Di Bello, F. A.; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Lanni, F.; Liu, H.; Meloni, F.; Meng, L.; Miucci, A.; Muenstermann, D.; Nessi, M.; Perić, I.; Rimoldi, M.; Ristic, B.; Barrero Pinto, M. Vicente; Vossebeld, J.; Weber, M.; Wu, W.; Xu, L.

    2016-07-01

    Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  11. Fireplace adapters

    SciTech Connect

    Hunt, R.L.

    1983-12-27

    An adapter is disclosed for use with a fireplace. The stove pipe of a stove standing in a room to be heated may be connected to the flue of the chimney so that products of combustion from the stove may be safely exhausted through the flue and outwardly of the chimney. The adapter may be easily installed within the fireplace by removing the damper plate and fitting the adapter to the damper frame. Each of a pair of bolts has a portion which hooks over a portion of the damper frame and a threaded end depending from the hook portion and extending through a hole in the adapter. Nuts are threaded on the bolts and are adapted to force the adapter into a tight fit with the adapter frame.

  12. A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

    PubMed Central

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

  13. Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

    SciTech Connect

    Smith, J.H.; Ellis, J.R.; Montague, S.; Allen, J.J.

    1997-03-01

    One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.

  14. A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

    NASA Astrophysics Data System (ADS)

    Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

    2013-03-01

    Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

  15. Self-testable CMOS thermopile-based infrared imager

    NASA Astrophysics Data System (ADS)

    Charlot, Benoit; Parrain, F.; Mir, Salvador; Courtois, Bernard

    2001-04-01

    This paper describes a CMOS-compatible self-testable uncooled InfraRed (IR) imager that can be used in multiple applications such as overheating detection, night vision, and earth tracking for satellite positioning. The imager consists of an array of thermal pixels that sense an infrared radiation. Each pixel is implemented as a front-side bulk micromachined membrane suspended by four arms, each arm containing a thermopile made of Poly/Al thermocouples. The imager has a pixel self-test function that can be activated off-line in the field for validation and maintenance purposes, with an on-chip test signal generation that requires only slight modifications in the pixel design. The self-test of a pixel takes about 15 ms. The area overhead required by the test electronics does not imply any reduction of the pixel fill factor, since the electronics fits in the pixel silicon boundary. However, the additional self-test circuitry contributes to a small increase in the thermal conductance of a pixel due to the wiring of a heating resistor over the suspended arms. The self-test capability of the imager allows for a production test with a standard test equipment, without the need of special infrared sources and the associated optical equipment. A prototype with 8 X 8 pixels is currently in fabrication for validation of the self-test approach. In this prototype, each pixel occupies an area of 200 X 200 micrometer2, with a membrane size of 90 X 90 micrometer2 (fill factor of 0.2). Simulation results indicate a pixel thermal conductance of 22.6 (mu) W/K, giving a responsivity of 138 V/W, with a thermocouple Seebeck coefficient that has been measured at 248 (mu) V/K for the 0.6 micrometer CMOS technology used. The noise equivalent power (considering only Johnson noise in the thermopile) is calculated as 0.18 nW.H-1/2 with a detectivity of 5.03 X 107 cm.Hz1/2.W-1, in line with current state-of-the-art. Since the imager may need to measure irradiation intensities below 1(mu) W

  16. Adaptive SPECT

    PubMed Central

    Barrett, Harrison H.; Furenlid, Lars R.; Freed, Melanie; Hesterman, Jacob Y.; Kupinski, Matthew A.; Clarkson, Eric; Whitaker, Meredith K.

    2008-01-01

    Adaptive imaging systems alter their data-acquisition configuration or protocol in response to the image information received. An adaptive pinhole single-photon emission computed tomography (SPECT) system might acquire an initial scout image to obtain preliminary information about the radiotracer distribution and then adjust the configuration or sizes of the pinholes, the magnifications, or the projection angles in order to improve performance. This paper briefly describes two small-animal SPECT systems that allow this flexibility and then presents a framework for evaluating adaptive systems in general, and adaptive SPECT systems in particular. The evaluation is in terms of the performance of linear observers on detection or estimation tasks. Expressions are derived for the ideal linear (Hotelling) observer and the ideal linear (Wiener) estimator with adaptive imaging. Detailed expressions for the performance figures of merit are given, and possible adaptation rules are discussed. PMID:18541485

  17. Adaptive Computing.

    ERIC Educational Resources Information Center

    Harrell, William

    1999-01-01

    Provides information on various adaptive technology resources available to people with disabilities. (Contains 19 references, an annotated list of 129 websites, and 12 additional print resources.) (JOW)

  18. Contour adaptation.

    PubMed

    Anstis, Stuart

    2013-01-01

    It is known that adaptation to a disk that flickers between black and white at 3-8 Hz on a gray surround renders invisible a congruent gray test disk viewed afterwards. This is contrast adaptation. We now report that adapting simply to the flickering circular outline of the disk can have the same effect. We call this "contour adaptation." This adaptation does not transfer interocularly, and apparently applies only to luminance, not color. One can adapt selectively to only some of the contours in a display, making only these contours temporarily invisible. For instance, a plaid comprises a vertical grating superimposed on a horizontal grating. If one first adapts to appropriate flickering vertical lines, the vertical components of the plaid disappears and it looks like a horizontal grating. Also, we simulated a Cornsweet (1970) edge, and we selectively adapted out the subjective and objective contours of a Kanisza (1976) subjective square. By temporarily removing edges, contour adaptation offers a new technique to study the role of visual edges, and it demonstrates how brightness information is concentrated in edges and propagates from them as it fills in surfaces.

  19. An integrated low-voltage ultra-low-power reconfigurable hardware interface in 0.18-µm CMOS

    NASA Astrophysics Data System (ADS)

    Guo, Zhiyong; Li, Qiang; Liu, Haiqi; Yan, Bo; Li, Guangjun

    2011-06-01

    This article presents an interface application specific integrated circuit (ASIC) adaptable to a wide range of bio- and neuro-signal applications. The chip consists of a low-noise analogue front end (FE) and a successive-approximation analogue-to-digital converter (ADC). The entire analogue signal processing chain is fully differential for better immunity to common mode noise and interferences. To make the interface adaptable to different biopotential signals, the bandwidth and gain of the analogue FE are configurable. The ADC is designed for rail-to-rail operation and the input full-scale is adjustable so that the resolution requirement can be relaxed. Fabricated in 0.18-µm complementary metal oxide semiconductor (CMOS), ? input-referred noise density and more than 100-dB CMRR are obtained. Operating in a 10-bit mode, the ADC exhibits -1/+0.3-LSB DNL and -1.3/+0.8-LSB INL least significant bit integral nonlinearity for 1-V rail-to-rail input. The whole interface integrated circuit (IC) consumes 36 µW from a single 1-V supply, making it suitable for a wide range of low-voltage and low-power bio- and neuro-chip platforms.

  20. Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

    NASA Technical Reports Server (NTRS)

    White, Mark; Cooper, Mark; Johnston, Allan

    2011-01-01

    Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

  1. Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

    NASA Astrophysics Data System (ADS)

    Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

    2010-10-01

    Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

  2. Design and simulation of multi-color infrared CMOS metamaterial absorbers

    NASA Astrophysics Data System (ADS)

    Cheng, Zhengxi; Chen, Yongping; Ma, Bin

    2016-05-01

    Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.

  3. Dielectrophoretic lab-on-CMOS platform for trapping and manipulation of cells.

    PubMed

    Park, Kyoungchul; Kabiri, Shideh; Sonkusale, Sameer

    2016-02-01

    Trapping and manipulation of cells are essential operations in numerous studies in biology and life sciences. We discuss the realization of a Lab-on-a-Chip platform for dielectrophoretic trapping and repositioning of cells and microorganisms on a complementary metal oxide semiconductor (CMOS) technology, which we define here as Lab-on-CMOS (LoC). The LoC platform is based on dielectrophoresis (DEP) which is the force experienced by any dielectric particle including biological entities in non-uniform AC electrical field. DEP force depends on the permittivity of the cells, its size and shape and also on the permittivity of the medium and therefore it enables selective targeting of cells based on their phenotype. In this paper, we address an important matter that of electrode design for DEP for which we propose a three-dimensional (3D) octapole geometry to create highly confined electric fields for trapping and manipulation of cells. Conventional DEP-based platforms are implemented stand-alone on glass, silicon or polymers connected to external infrastructure for electronics and optics, making it bulky and expensive. In this paper, the use of CMOS as a platform provides a pathway to truly miniaturized lab-on-CMOS or LoC platform, where DEP electrodes are designed using built-in multiple metal layers of the CMOS process for effective trapping of cells, with built-in electronics for in-situ impedance monitoring of the cell position. We present electromagnetic simulation results of DEP force for this unique 3D octapole geometry on CMOS. Experimental results with yeast cells validate the design. These preliminary results indicate the promise of using CMOS technology for truly compact miniaturized lab-on-chip platform for cell biotechnology applications. PMID:26780441

  4. CMOS Image Sensor with a Built-in Lane Detector.

    PubMed

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%. PMID:22573983

  5. Tracking cancer cell proliferation on a CMOS capacitance sensor chip.

    PubMed

    Prakash, Somashekar Bangalore; Abshire, Pamela

    2008-05-15

    We report a novel technique for assessing cell proliferation that employs integrated capacitance sensors for monitoring the growth of anchorage-dependent living cells. The sensors measure substrate coupling capacitances of cells cultured on-chip in a standard in vitro environment. The biophysical phenomenon underlying the capacitive behavior of cells is the counterionic polarization around the insulating cell bodies when exposed to weak, low frequency electric fields. The sensors employ charge sharing for mapping sensed capacitance values in the fF range to output voltage signals. The sensor chip has been fabricated in a commercially available 0.5microm, 2-poly 3-metal CMOS technology. We report experimental results demonstrating sensor response to the adhesion of MDA-MB-231 breast cancer cells followed by their proliferation on the chip surface. On-chip capacitance sensing offers a non-invasive, label-free, easy-to-use, miniaturized technique with real-time monitoring capability for tracking cell proliferation in vitro. PMID:18281207

  6. A CMOS pressure sensor tag chip for passive wireless applications.

    PubMed

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

  7. Design of a CMOS Potentiostat Circuit for Electrochemical Detector Arrays

    PubMed Central

    Ayers, Sunitha; Gillis, Kevin D.; Lindau, Manfred; Minch, Bradley A.

    2010-01-01

    High-throughput electrode arrays are required for advancing devices for testing the effect of drugs on cellular function. In this paper, we present design criteria for a potentiostat circuit that is capable of measuring transient amperometric oxidation currents at the surface of an electrode with submillisecond time resolution and picoampere current resolution. The potentiostat is a regulated cascode stage in which a high-gain amplifier maintains the electrode voltage through a negative feedback loop. The potentiostat uses a new shared amplifier structure in which all of the amplifiers in a given row of detectors share a common half circuit permitting us to use fewer transistors per detector. We also present measurements from a test chip that was fabricated in a 0.5-μm, 5-V CMOS process through MOSIS. Each detector occupied a layout area of 35μm × 15μm and contained eight transistors and a 50-fF integrating capacitor. The rms current noise at 2kHz bandwidth is ≈ 110fA. The maximum charge storage capacity at 2kHz is 1.26 × 106 electrons. PMID:20514150

  8. Novel integrated CMOS pixel structures for vertex detectors

    SciTech Connect

    Kleinfelder, Stuart; Bieser, Fred; Chen, Yandong; Gareus, Robin; Matis, Howard S.; Oldenburg, Markus; Retiere, Fabrice; Ritter, Hans Georg; Wieman, Howard H.; Yamamoto, Eugene

    2003-10-29

    Novel CMOS active pixel structures for vertex detector applications have been designed and tested. The overriding goal of this work is to increase the signal to noise ratio of the sensors and readout circuits. A large-area native epitaxial silicon photogate was designed with the aim of increasing the charge collected per struck pixel and to reduce charge diffusion to neighboring pixels. The photogate then transfers the charge to a low capacitance readout node to maintain a high charge to voltage conversion gain. Two techniques for noise reduction are also presented. The first is a per-pixel kT/C noise reduction circuit that produces results similar to traditional correlated double sampling (CDS). It has the advantage of requiring only one read, as compared to two for CDS, and no external storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5, to 12.8 e{sup -}. Finally, a column-level active reset technique is explored that suppresses kT/C noise during pixel reset. In tests, noise was reduced by a factor of 7.6 times, to an estimated 5.1 e{sup -} input-referred noise. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21 in our tests. The latter feature may possibly reduce pixel-by-pixel pedestal differences to levels low enough to permit sparse data scan without per-pixel offset corrections.

  9. CMOS Image Sensor with a Built-in Lane Detector.

    PubMed

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

  10. A new architecture of current-mode CMOS TDI Sensor

    NASA Astrophysics Data System (ADS)

    Ji, Cheng; Chen, Yongping

    2015-10-01

    Nowadays, CMOS sensors still suffer from the problem of low SNR, especially in the stage of low illumination and high relative scanning velocity. Lots of methods have been develop to overcome this problem. Among these researches, TDI (Time Delay Integration) architecture is a more natural choice, which is natively supported by CCD sensors. In this paper a new kind of proposed current-mode sensor is used to achieve TDI operation in analog domain. The circuit is composed of three main parts. At first, a current-type pixel is proposed, in which the active MOSFET is operated in the triode region to ensure the output current is linearly dependent on the gate voltage and avoid the reduction of threshold voltage in the traditional voltage mode pixels, such as 3T, 4T which use the source followers as its active part. Then a discrete double sampling (DDS) unit, which is operated in the form of currents is used to efficiently reduce the fixed pattern noise (FPN) and make the output is independent of reset voltage of pixels. For accumulation, an improved current mirror adder under controlled of timing circuits is proposed to overcome the problem of saturation suffered in voltage domain. Some main noise sources, especially come from analog sample and holds capacitors and switches is analyzed. Finally, simulation results with CSMC 0.5um technology and Cadence IC show that the proposed method is reasonable and efficient to improve the SNR.

  11. Improved Signal Chains for Readout of CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Hancock, Bruce; Cunningham, Thomas

    2009-01-01

    An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

  12. Charge collection studies in irradiated HV-CMOS particle detectors

    NASA Astrophysics Data System (ADS)

    Affolder, A.; Andelković, M.; Arndt, K.; Bates, R.; Blue, A.; Bortoletto, D.; Buttar, C.; Caragiulo, P.; Cindro, V.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Gorišek, A.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hommels, L. B. A.; Huffman, T.; John, J.; Kanisauskas, K.; Kenney, C.; Kramberger, G.; Liang, Z.; Mandić, I.; Maneuski, D.; McMahon, S.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Perić, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zavrtanik, M.; Zhang, J.; Zhu, H.

    2016-04-01

    Charge collection properties of particle detectors made in HV-CMOS technology were investigated before and after irradiation with reactor neutrons. Two different sensor types were designed and processed in 180 and 350 nm technology by AMS. Edge-TCT and charge collection measurements with electrons from 90Sr source were employed. Diffusion of generated carriers from undepleted substrate contributes significantly to the charge collection before irradiation, while after irradiation the drift contribution prevails as shown by charge measurements at different shaping times. The depleted region at a given bias voltage was found to grow with irradiation in the fluence range of interest for strip detectors at the HL-LHC. This leads to large gains in the measured charge with respect to the one before irradiation. The increase of the depleted region was attributed to removal of effective acceptors. The evolution of depleted region with fluence was investigated and modeled. Initial studies show a small effect of short term annealing on charge collection.

  13. Passive radiation detection using optically active CMOS sensors

    NASA Astrophysics Data System (ADS)

    Dosiek, Luke; Schalk, Patrick D.

    2013-05-01

    Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and β particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

  14. Accelerated life testing effects on CMOS microcircuit characteristics

    NASA Technical Reports Server (NTRS)

    1980-01-01

    This report covers the time period from May 1976 to December 1979 and encompasses the three phases of accelerated testing: Phase 1, the 250 C testing; Phase 2, the 200 C testing; and Phase 3, the 125 C testing. The duration of the test in Phase 1 and Phase 2 was sufficient to take the devices into the wear out region. The wear out distributions were used to estimate the activation energy between the 250 C and the 200 C test temperatures. The duration of the 125 C test, 20,000 hours, was not sufficient to bring the test devices into the wear out region; consequently the third data point at 125 C for determining the consistency of activation energy could not be obtained. It was estimated that, for the most complex of the three device types, the activation energy between 200 C and 125 C should be at least as high as that between 250 C and 200 C. The practicality of the use of high temperature for the accelerated life tests from the point of view of durability of equipment was assessed. Guidelines for the development of accelerated life test conditions were proposed. The use of the silicon nitride overcoat to improve the high temperature accelerated life test characteristics of CMOS microcircuits was explored in Phase 4 of this study and is attached as an appendix to this report.

  15. A 16-channel CMOS preamplifier for laser ranging radar receivers

    NASA Astrophysics Data System (ADS)

    Liu, Ru-qing; Zhu, Jing-guo; Jiang, Yan; Li, Meng-lin; Li, Feng

    2015-10-01

    A 16-channal front-end preamplifier array has been design in a 0.18um CMOS process for pulse Laser ranging radar receiver. This front-end preamplifier array incorporates transimpedance amplifiers(TIAs) and differential voltage post-amplifier(PAMP),band gap reference and other interface circuits. In the circuit design, the regulated cascade (RGC) input stage, Cherry-Hooper and active inductor peaking were employed to enhance the bandwidth. And in the layout design, by applying the layout isolation structure combined with P+ guard-ring(PGR), N+ guard-ring(NGR),and deep-n-well(DNW) for amplifier array, the crosstalk and the substrate noise coupling was reduced effectively. The simulations show that a single channel receiver front-end preamplifier achieves 95 dBΩ transimpedance gain and 600MHz bandwidth for 3 PF photodiode capacitance. The total power of 16-channel front-end amplifier array is about 800mW for 1.8V supply.

  16. Smart CMOS sensor for wideband laser threat detection

    NASA Astrophysics Data System (ADS)

    Schwarze, Craig R.; Sonkusale, Sameer

    2015-09-01

    The proliferation of lasers has led to their widespread use in applications ranging from short range standoff chemical detection to long range Lidar sensing and target designation operating across the UV to LWIR spectrum. Recent advances in high energy lasers have renewed the development of laser weapons systems. The ability to measure and assess laser source information is important to both identify a potential threat as well as determine safety and nominal hazard zone (NHZ). Laser detection sensors are required that provide high dynamic range, wide spectral coverage, pulsed and continuous wave detection, and large field of view. OPTRA, Inc. and Tufts have developed a custom ROIC smart pixel imaging sensor architecture and wavelength encoding optics for measurement of source wavelength, pulse length, pulse repetition frequency (PRF), irradiance, and angle of arrival. The smart architecture provides dual linear and logarithmic operating modes to provide 8+ orders of signal dynamic range and nanosecond pulse measurement capability that can be hybridized with the appropriate detector array to provide UV through LWIR laser sensing. Recent advances in sputtering techniques provide the capability for post-processing CMOS dies from the foundry and patterning PbS and PbSe photoconductors directly on the chip to create a single monolithic sensor array architecture for measuring sources operating from 0.26 - 5.0 microns, 1 mW/cm2 - 2 kW/cm2.

  17. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    NASA Technical Reports Server (NTRS)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  18. Measurements of Si hybrid CMOS x-ray detector characteristics

    NASA Astrophysics Data System (ADS)

    Bongiorno, Stephen D.; Falcone, Abe D.; Burrows, David N.; Cook, Robert; Bai, Yibin; Farris, Mark

    2009-08-01

    The development of Hybrid CMOS Detectors (HCDs) for X-Ray telescope focal planes will place them in contention with CCDs on future satellite missions due to their faster frame rates, flexible readout scenarios, lower power consumption, and inherent radiation hardness. CCDs have been used with great success on the current generation of X-Ray telescopes (e.g. Chandra, XMM, Suzaku, and Swift). However their bucket-brigade readout architecture, which transfers charge across the chip with discrete component readout electronics, results in clockrate limited readout speeds that cause pileup (saturation) of bright sources and an inherent susceptibility to radiation induced displacement damage that limits mission lifetime. In contrast, HCDs read pixels with low power, on-chip multiplexer electronics in a random access fashion. Faster frame rates achieved with multi-output readout design will allow the next generation's larger effective area telescopes to observe bright sources free of pileup. Radiation damaged lattice sites effect a single pixel instead of an entire row. Random access, multi-output readout will allow for novel readout modes such as simultaneous bright-source-fast/whole-chip-slow readout. In order for HCDs to be useful as X-Ray detectors, they must show noise and energy resolution performance similar to CCDs while retaining advantages inherent to HCDs. We will report on readnoise, conversion gain, and energy resolution measurements of an X-Ray enhanced Teledyne HAWAII-1RG (H1RG) HCD and describe techniques of H1RG data reduction.

  19. A global shutter CMOS image sensor for hyperspectral imaging

    NASA Astrophysics Data System (ADS)

    Stefanov, Konstantin D.; Dryer, Ben J.; Hall, David J.; Holland, Andrew D.; Pratlong, Jérôme; Fryer, Martin; Pike, Andrew

    2015-09-01

    Hyperspectral imaging has been providing vital information on the Earth landscape in response to the changing environment, land use and natural phenomena. While conventional hyperspectral imaging instruments have typically used rows of linescan CCDs, CMOS image sensors (CIS) have been slowly penetrating space instrumentation for the past decade, and Earth observation (EO) is no exception. CIS provide distinct advantages over CCDs that are relevant to EO hyperspectral imaging. The lack of charge transfer through the array allows the reduction of cross talk usually present in CCDs due to imperfect charge transfer efficiency, and random pixel addressing makes variable integration time possible, and thus improves the camera sensitivity and dynamic range. We have developed a 10T pixel design that integrates a pinned photodiode with global shutter and in-pixel correlated double sampling (CDS) to increase the signal to noise ratio in less intense spectral regimes, allowing for both high resolution and low noise hyperspectral imaging for EO. This paper details the characterization of a test device, providing baseline performance measurements of the array such as noise, responsivity, dark current and global shutter efficiency, and also discussing benchmark hyperspectral imaging requirements such as dynamic range, pixel crosstalk, and image lag.

  20. Total dose hardness of three commercial CMOS microelectronics foundries

    SciTech Connect

    Osborn, J.V.; Lacoe, R.C.; Mayer, D.C.; Yabiku, G.

    1998-06-01

    The authors have measured the effects of total ionizing dose (TID) on CMOS FETs, ring oscillators and field-oxide transistor test structures fabricated at three different commercial foundries with four different processes. The foundries spanned a range of integration levels and included Hewlett-Packard (HP) 0.5 {micro}m and 0.8 {micro}m processes, an Orbit 1.2 {micro}m process, and an AMI 1.6 {micro}m process. They found that the highest tolerance to TID was for the HP 0.5 {micro}m process, where the shift in NMOS threshold voltage was less than 40 mV at 300 krad. An examination of the dependence of the threshold voltage shift on gate oxide thickness indicated that oxides of the different commercial processes were of similar quality, and that the improvement in the total dose tolerance of the HP 0.5 {micro}m technology is associated with the scaling of the gate oxide. Measurements on field-oxide transistors from the HP 0.5 {micro}m process were shown not to invert for signal voltages at 300 krad, maintaining the integrity of the LOCOS isolation.

  1. A CMOS pressure sensor tag chip for passive wireless applications.

    PubMed

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-03-23

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

  2. Label-free immunodetection with CMOS-compatible semiconducting nanowires.

    PubMed

    Stern, Eric; Klemic, James F; Routenberg, David A; Wyrembak, Pauline N; Turner-Evans, Daniel B; Hamilton, Andrew D; LaVan, David A; Fahmy, Tarek M; Reed, Mark A

    2007-02-01

    Semiconducting nanowires have the potential to function as highly sensitive and selective sensors for the label-free detection of low concentrations of pathogenic microorganisms. Successful solution-phase nanowire sensing has been demonstrated for ions, small molecules, proteins, DNA and viruses; however, 'bottom-up' nanowires (or similarly configured carbon nanotubes) used for these demonstrations require hybrid fabrication schemes, which result in severe integration issues that have hindered widespread application. Alternative 'top-down' fabrication methods of nanowire-like devices produce disappointing performance because of process-induced material and device degradation. Here we report an approach that uses complementary metal oxide semiconductor (CMOS) field effect transistor compatible technology and hence demonstrate the specific label-free detection of below 100 femtomolar concentrations of antibodies as well as real-time monitoring of the cellular immune response. This approach eliminates the need for hybrid methods and enables system-scale integration of these sensors with signal processing and information systems. Additionally, the ability to monitor antibody binding and sense the cellular immune response in real time with readily available technology should facilitate widespread diagnostic applications. PMID:17268465

  3. A CMOS Smart Thermal Sensor for Biomedical Application

    NASA Astrophysics Data System (ADS)

    Lee, Ho-Yin; Chen, Shih-Lun; Luo, Ching-Hsing

    This paper describes a smart thermal sensing chip with an integrated vertical bipolar transistor sensor, a Sigma Delta Modulator (SDM), a Micro-Control Unit (MCU), and a bandgap reference voltage generator for biomedical application by using 0.18μm CMOS process. The npn bipolar transistors with the Deep N-Well (DNW) instead of the pnp bipolar transistor is first adopted as the sensor for good isolation from substrate coupling noise. In addition to data compression, Micro-Control Unit (MCU) plays an important role for executing auto-calibration by digitally trimming the bipolar sensor in parallel to save power consumption and to reduce feedback complexity. It is different from the present analog feedback calibration technologies. Using one sensor, instead of two sensors, to create two differential signals in 180° phase difference input to SDM is also a novel design of this work. As a result, in the range of 0°C to 80°C or body temperature (37±5°C), the inaccuracy is less than ±0.1°C or ±0.05°C respectively with one-point calibration after packaging. The average power consumption is 268.4μW with 1.8V supply voltage.

  4. A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of −20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

  5. A hierarchical approach to test generation for CMOS VLSI circuits

    NASA Astrophysics Data System (ADS)

    Weening, Edward Christiaan

    A hierarchical approach to the automatic test pattern generation for large digital VLSI circuits, fabricated in CMOS technology, is developed and implemented. The use of information on the circuit's hierarchy, which is readily available from most modern CAD (Computer Aided Design) systems, speeds up the test generation process considerably and enhances the quality of the tests generated. The hierarchical test generation tool can also be integrated in future CAD systems making test generation and testability enhancement during circuit design feasible. The hierarchical approach is described at the switch, functional, and behavioral level. A test pattern generation algorithm at the switch level is presented. Test generation and fault simulation algorithms both using OBDD (Ordered Binary Decision Diagram) functional descriptions of the circuit modules are presented. A test plan generation method at the behavioral level is presented. Practical results show that the hierarchical approach to test generation is more efficient than a conventional, non-hierarchical approach, especially for switch level faults. The results also show that the use of Design For Testability (DFT) circuitry is supported at the behavioral level.

  6. CMOS Image Sensor with a Built-in Lane Detector

    PubMed Central

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%. PMID:22573983

  7. Climate adaptation

    NASA Astrophysics Data System (ADS)

    Kinzig, Ann P.

    2015-03-01

    This paper is intended as a brief introduction to climate adaptation in a conference devoted otherwise to the physics of sustainable energy. Whereas mitigation involves measures to reduce the probability of a potential event, such as climate change, adaptation refers to actions that lessen the impact of climate change. Mitigation and adaptation differ in other ways as well. Adaptation does not necessarily have to be implemented immediately to be effective; it only needs to be in place before the threat arrives. Also, adaptation does not necessarily require global, coordinated action; many effective adaptation actions can be local. Some urban communities, because of land-use change and the urban heat-island effect, currently face changes similar to some expected under climate change, such as changes in water availability, heat-related morbidity, or changes in disease patterns. Concern over those impacts might motivate the implementation of measures that would also help in climate adaptation, despite skepticism among some policy makers about anthropogenic global warming. Studies of ancient civilizations in the southwestern US lends some insight into factors that may or may not be important to successful adaptation.

  8. High-sensitivity chemiluminescence detection of cytokines using an antibody-immobilized CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Hong, Dong-Gu; Joung, Hyou-Arm; Kim, Sang-Hyo; Kim, Min-Gon

    2013-05-01

    In this study, we used a Complementary Metal Oxide Semiconductor (CMOS) image sensor with immobilizing antibodies on its surface to detect human cytokines, which are activators that mediate intercellular communication including expression and control of immune responses. The CMOS image sensor has many advantages over the Charge Couple Device, including lower power consumption, operation voltage, and cost. The photodiode, a unit pixel component in the CMOS image sensor, receives light from the detection area and generates digital image data. About a million pixels are embedded, and size of each pixel is 3 x 3 μm. The chemiluminescence reaction produces light from the chemical reaction of luminol and hydrogen peroxide. To detect cytokines, antibodies were immobilized on the surface of the CMOS image sensor, and a sandwich immunoassay using an HRP-labeled antibody was performed. An HRP-catalyzed chemiluminescence reaction was measured by each pixel of the CMOS image sensor. Pixels with stronger signals indicated higher cytokine concentrations; thus, we were able to measure human interleukin-5 (IL-5) at femtomolar concentrations.

  9. CMOS current-mode neural associative memory design with on-chip learning.

    PubMed

    Wu, C Y; Lan, J F

    1996-01-01

    Based on the Grossberg mathematical model called the outstar, a modular neural net with on-chip learning and memory is designed and analyzed. The outstar is the minimal anatomy that can interpret the classical conditioning or associative memory. It can also be served as a general-purpose pattern learning device. To realize the outstar, CMOS (complimentary metal-oxide semiconductor) current-mode analog dividers are developed to implement the special memory called the ratio-type memory. Furthermore, a CMOS current-mode analog multiplier is used to implement the correlation. The implemented CMOS outstar can on-chip store the relative ratio values of the trained weights for a long time. It can also be modularized to construct general neural nets. HSPICE (a circuit simulator of Meta Software, Inc.) simulation results of the CMOS outstar circuits as associative memory and pattern learner have successfully verified their functions. The measured results of the fabricated CMOS outstar circuits have also successfully confirmed the ratio memory and on-chip learning capability of the circuits. Furthermore, it has been shown that the storage time of the ratio memory can be as long as five minutes without refreshment. Also the outstar can enhance the contrast of the stored pattern within a long period. This makes the outstar circuits quite feasible in many applications.

  10. Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

    SciTech Connect

    Wang, Zujun Huang, Shaoyan; Liu, Minbo; Xiao, Zhigang; He, Baoping; Yao, Zhibin; Sheng, Jiangkun

    2014-07-15

    The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 10{sup 8} n/cm{sup 2}s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 10{sup 11}, 5 × 10{sup 11}, and 1 × 10{sup 12} n/cm{sup 2}, respectively. The mean dark signal (K{sub D}), dark signal spike, dark signal non-uniformity (DSNU), noise (V{sub N}), saturation output signal voltage (V{sub S}), and dynamic range (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike.

  11. Damage analysis of CMOS electro-optical imaging system by a continuous wave laser

    NASA Astrophysics Data System (ADS)

    Yoon, Sunghee; Jhang, Kyung-Young; Shin, Wan-Soon

    2016-08-01

    EOIS (electro-optical imaging system) is vulnerable to laser beam because EOIS focuses the incident laser beam onto the image sensor via lens module. Accordingly, the laser-induced damage of EOIS is necessary to be identified for the counter-measure against the laser attack. In this study, the damage of CMOS EOIS and image sensor induced by CW (continuous wave) NIR (near infrared) laser was experimentally investigated. When the laser was emitted to CMOS EOIS, a temporary damage was occurred first such as flickering or dazzling and then a permanent damage was followed as the increase of laser irradiance and irradiation time. If the EIOS is composed of the optical equipment made of heatresistant material, laser beam can penetrate the lens module of EOIS without melting the lens and lens guide. Thus, it is necessary to investigate the damage of CMOS image sensor by the CW laser and we performed experimentally investigation of damage on the CMOS image sensor similar with case of CMOS EOIS. And we analyzed the experiment results by using OM (optical microscopy) and check the image quality through tomography. As the increase of laser irradiance and irradiation time, the permanent damage such as discoloration and breakdown were sequentially appeared.

  12. Etch challenges for DSA implementation in CMOS via patterning

    NASA Astrophysics Data System (ADS)

    Pimenta Barros, P.; Barnola, S.; Gharbi, A.; Argoud, M.; Servin, I.; Tiron, R.; Chevalier, X.; Navarro, C.; Nicolet, C.; Lapeyre, C.; Monget, C.; Martinez, E.

    2014-03-01

    This paper reports on the etch challenges to overcome for the implementation of PS-b-PMMA block copolymer's Directed Self-Assembly (DSA) in CMOS via patterning level. Our process is based on a graphoepitaxy approach, employing an industrial PS-b-PMMA block copolymer (BCP) from Arkema with a cylindrical morphology. The process consists in the following steps: a) DSA of block copolymers inside guiding patterns, b) PMMA removal, c) brush layer opening and finally d) PS pattern transfer into typical MEOL or BEOL stacks. All results presented here have been performed on the DSA Leti's 300mm pilot line. The first etch challenge to overcome for BCP transfer involves in removing all PMMA selectively to PS block. In our process baseline, an acetic acid treatment is carried out to develop PMMA domains. However, this wet development has shown some limitations in terms of resists compatibility and will not be appropriated for lamellar BCPs. That is why we also investigate the possibility to remove PMMA by only dry etching. In this work the potential of a dry PMMA removal by using CO based chemistries is shown and compared to wet development. The advantages and limitations of each approach are reported. The second crucial step is the etching of brush layer (PS-r-PMMA) through a PS mask. We have optimized this step in order to preserve the PS patterns in terms of CD, holes features and film thickness. Several integrations flow with complex stacks are explored for contact shrinking by DSA. A study of CD uniformity has been addressed to evaluate the capabilities of DSA approach after graphoepitaxy and after etching.

  13. CMOS Hybrid Pixel Detectors for Scientific, Industrial and Medical Applications

    NASA Astrophysics Data System (ADS)

    Broennimann, Christian

    2009-03-01

    Crystallography is the principal technique for determining macromolecular structures at atomic resolution and uses advantageously the high intensity of 3rd generation synchrotron X-ray sources . Macromolecular crystallography experiments benefit from excellent beamline equipment, recent software advances and modern X-ray detectors. However, the latter do not take full advantage of the brightness of modern synchrotron sources. CMOS Hybrid pixel array detectors, originally developed for high energy physics experiments, meet these requirements. X-rays are recorded in single photon counting mode and data thus are stored digitally at the earliest possible stage. This architecture leads to several advantages over current detectors: No detector noise is added to the signal. Readout time is reduced to a few milliseconds. The counting rates are matched to beam intensities at protein crystallography beamlines at 3rd generation synchrotrons. The detector is not sensitive to X-rays during readout; therefore no mechanical shutter is required. The detector has a very sharp point spread function (PSF) of one pixel, which allows better resolution of adjacent reflections. Low energy X-rays can be suppressed by the comparator At the Paul Scherrer Institute (PSI) in Switzerland the first and largest array based on this technology was constructed: The Pilatus 6M detector. The detector covers an area of 43.1 x 44.8 cm2 , has 6 million pixels and is read out noise free in 3.7 ms. Since June 2007 the detector is in routine operation at the beamline 6S of the Swiss Light Source (SLS). The company DETCRIS Ltd, has licensed the technology from PSI and is commercially offering the PILATUS detectors. Examples of the wide application range of the detectors will be shown.

  14. sCMOS detector for imaging VNIR spectrometry

    NASA Astrophysics Data System (ADS)

    Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

    2013-09-01

    The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

  15. Advanced Simulation Technology to Design Etching Process on CMOS Devices

    NASA Astrophysics Data System (ADS)

    Kuboi, Nobuyuki

    2015-09-01

    Prediction and control of plasma-induced damage is needed to mass-produce high performance CMOS devices. In particular, side-wall (SW) etching with low damage is a key process for the next generation of MOSFETs and FinFETs. To predict and control the damage, we have developed a SiN etching simulation technique for CHxFy/Ar/O2 plasma processes using a three-dimensional (3D) voxel model. This model includes new concepts for the gas transportation in the pattern, detailed surface reactions on the SiN reactive layer divided into several thin slabs and C-F polymer layer dependent on the H/N ratio, and use of ``smart voxels''. We successfully predicted the etching properties such as the etch rate, polymer layer thickness, and selectivity for Si, SiO2, and SiN films along with process variations and demonstrated the 3D damage distribution time-dependently during SW etching on MOSFETs and FinFETs. We confirmed that a large amount of Si damage was caused in the source/drain region with the passage of time in spite of the existing SiO2 layer of 15 nm in the over etch step and the Si fin having been directly damaged by a large amount of high energy H during the removal step of the parasitic fin spacer leading to Si fin damage to a depth of 14 to 18 nm. By analyzing the results of these simulations and our previous simulations, we found that it is important to carefully control the dose of high energy H, incident energy of H, polymer layer thickness, and over-etch time considering the effects of the pattern structure, chamber-wall condition, and wafer open area ratio. In collaboration with Masanaga Fukasawa and Tetsuya Tatsumi, Sony Corporation. We thank Mr. T. Shigetoshi and Mr. T. Kinoshita of Sony Corporation for their assistance with the experiments.

  16. Photocurrent estimation from multiple nondestructive samples in CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Liu, Xinqiao; El Gamal, Abbas

    2001-05-01

    CMOS image sensors generally suffer form lower dynamic range than CCDs due to their higher readout noise. Their high speed readout capability and the potential of integrating memory and signal processing with the sensor on the same chip, open up many possibilities for enhancing their dynamic range. Earlier work have demonstrated the use of multiple non-destructive samples to enhance dynamic range, while achieving higher SNR than using other dynamic range enhancement schemes. The high dynamic range image is constructed by appropriately scaling each pixel's last sample before saturation. Conventional CDS is used to reduce offset FPN and reset noise. This simple high dynamic range image construction scheme, however, does not take full advantage of the multiple samples. Readout noise power, which doubles as a result of performing CDS, remain as high as in conventional sensor operation. As a result dynamic range is only extended at the high illumination end. The paper explores the use of linear mean-square-error estimation to more fully exploit the multiple pixel samples to reduce readout noise and thus extend dynamic range at the low illumination end. We present three estimation algorithms: (1) a recursive estimator when reset noise and offset FPN are ignored, (2) a non-recursive algorithm when reset noise and FPN are considered, and (3) a recursive estimation algorithm for case (2), which achieves mean square error close to the non-recursive algorithm without the need to store all the samples. The later recursive algorithm is attractive since it requires the storage of only a few pixel values per pixel, which makes its implementation in a single chip digital imaging system feasible.

  17. Integrated CMOS dew point sensors for relative humidity measurement

    NASA Astrophysics Data System (ADS)

    Savalli, Nicolo; Baglio, Salvatore; Castorina, Salvatore; Sacco, Vincenzo; Tringali, Cristina

    2004-07-01

    This work deals with the development of integrated relative humidity dew point sensors realized by adopting standard CMOS technology for applications in various fields. The proposed system is composed by a suspended plate that is cooled by exploiting integrated Peltier cells. The cold junctions of the cells have been spread over the plate surface to improve the homogeneity of the temperature distribution over its surface, where cooling will cause the water condensation. The temperature at which water drops occur, named dew point temperature, is a function of the air humidity. Measurement of such dew point temperature and the ambient temperature allows to know the relative humidity. The detection of water drops is achieved by adopting a capacitive sensing strategy realized by interdigited fixed combs, composed by the upper layer of the adopted process. Such a capacitive sensor, together with its conditioning circuit, drives a trigger that stops the cooling of the plate and enables the reading of the dew point temperature. Temperature measurements are achieved by means of suitably integrated thermocouples. The analytical model of the proposed system has been developed and has been used to design a prototype device and to estimate its performances. In such a prototype, the thermoelectric cooler is composed by 56 Peltier cells, made by metal 1/poly 1 junctions. The plate has a square shape with 200 μm side, and it is realized by exploiting the oxide layers. Starting from the ambient temperature a temperature variation of ΔT = 15 K can be reached in 10 ms thus allowing to measure a relative humidity greater than 40%.

  18. CMOS analog implementation of a simplified spinal cord neural model

    NASA Astrophysics Data System (ADS)

    Domenech-Asensi, Gines; Ruiz-Merino, Ramon; Hauer, Hans; Diaz-Madrid, Jose A.

    2003-04-01

    This paper presents an analog CMOS implementation of a neural network based on a spinal cord model. The network is comprised by three pairs of cells, Alpha motorneurons, Interneurons and Renshaw cells, which form the basic control motor system for a single limb movement. Behaviour of each neuron is described by a differential equation, which provides it with a dynamic performance. This network is useful to control limb movements based in an antagonist pair of actuators, i.e. muscles for a human limb or electric motors or SMA fibers for machine applications. This antagonist structure has the main advantage that allows independent control of limb position and stiffness, which makes it suitable for applications where inertial load compensation is a critical factor. For the implementation of the neurons we have developed individual analog operators, like multipliers and integrators, which have been then joined to obtain the cell. The whole circuit works in current mode, and exhibits good performance in power disipation and bandwidth. The implementation of the network has been done in a 0.35um process from AMS. The layout size is 870 × 480 μm and the power dissipation is 14 mW, using a reference voltage of 3.3 volts. The applications in which this network canbe used fall in two broad cathegories. Firstly, in the development of human-machine interfaces capable to be used both in industry and in handicaped people and secondly in the development o neural controller for industrial robots, providing them with a compliance performance.

  19. Toothbrush Adaptations.

    ERIC Educational Resources Information Center

    Exceptional Parent, 1987

    1987-01-01

    Suggestions are presented for helping disabled individuals learn to use or adapt toothbrushes for proper dental care. A directory lists dental health instructional materials available from various organizations. (CB)

  20. An approach to the optical interconnect made in standard CMOS process

    NASA Astrophysics Data System (ADS)

    Changliang, Yu; Luhong, Mao; Xindong, Xiao; Sheng, Xie; Shilin, Zhang

    2009-05-01

    A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide, metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P+/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.

  1. Prototyping of an HV-CMOS demonstrator for the High Luminosity-LHC upgrade

    NASA Astrophysics Data System (ADS)

    Vilella, E.; Benoit, M.; Casanova, R.; Casse, G.; Ferrere, D.; Iacobucci, G.; Peric, I.; Vossebeld, J.

    2016-01-01

    HV-CMOS sensors can offer important advantages in terms of material budget, granularity and cost for large area tracking systems in high energy physics experiments. This article presents the design and simulated results of an HV-CMOS pixel demonstrator for the High Luminosity-LHC. The pixel demonstrator has been designed in the 0.35 μm HV-CMOS process from ams AG and submitted for fabrication through an engineering run. To improve the response of the sensor, different wafers with moderate to high substrate resistivities are used to fabricate the design. The prototype consists of four large analog and standalone matrices with several pixel flavours, which are all compatible for readout with the FE-I4 ASIC. Details about the matrices and the pixel flavours are provided in this article.

  2. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    NASA Astrophysics Data System (ADS)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  3. A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System

    PubMed Central

    Rae, Bruce R.; Muir, Keith R.; Gong, Zheng; McKendry, Jonathan; Girkin, John M.; Gu, Erdan; Renshaw, David; Dawson, Martin D.; Henderson, Robert K.

    2009-01-01

    We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented. PMID:22291564

  4. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    NASA Astrophysics Data System (ADS)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×1012 1 MeV neq/cm2 and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  5. A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

    PubMed

    Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

    2016-08-01

    This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process. PMID:27337723

  6. 3D monolithically stacked CMOS Active Pixel Sensors for particle position and direction measurements

    NASA Astrophysics Data System (ADS)

    Servoli, L.; Passeri, D.; Morozzi, A.; Magalotti, D.; Piperku, L.

    2015-01-01

    In this work we propose a 3D monolithically stacked, multi-layer detectors based on CMOS Active Pixel Sensors (APS) layers which allows at the same time accurate estimation of the impact point and of the incidence angle an ionizing particle. The whole system features two fully-functional CMOS APS matrix detectors, including both sensing area and control/signal elaboration circuitry, stacked in a monolithic device by means of Through Silicon Via (TSV) connections thanks to the capabilities of the CMOS vertical scale integration (3D-IC) 130 nm Chartered/Tezzaron technology. In order to evaluate the suitability of the two layer monolithic active pixel sensor system to reconstruct particle tracks, tests with proton beams have been carried out at the INFN LABEC laboratories in Florence (Italy) with 3 MeV proton beam.

  7. Development of low read noise high conversion gain CMOS image sensor for photon counting level imaging

    NASA Astrophysics Data System (ADS)

    Seo, Min-Woong; Kawahito, Shoji; Kagawa, Keiichiro; Yasutomi, Keita

    2016-05-01

    A CMOS image sensor with deep sub-electron read noise and high pixel conversion gain has been developed. Its performance is recognized through image outputs from an area image sensor, confirming the capability of photoelectroncounting- level imaging. To achieve high conversion gain, the proposed pixel has special structures to reduce the parasitic capacitances around FD node. As a result, the pixel conversion gain is increased due to the optimized FD node capacitance, and the noise performance is also improved by removing two noise sources from power supply. For the first time, high contrast images from the reset-gate-less CMOS image sensor, with less than 0.3e- rms noise level, have been generated at an extremely low light level of a few electrons per pixel. In addition, the photon-counting capability of the developed CMOS imager is demonstrated by a measurement, photoelectron-counting histogram (PCH).

  8. A CMOS-compatible, surface-micromachined pressure sensor for aqueous ultrasonic application

    SciTech Connect

    Eaton, W.P.; Smith, J.H.

    1994-12-31

    A surface micromachined pressure sensor array is under development at the Integrated Micromechanics, Microsensors, and CMOS Technologies organization at Sandia National Laboratories. This array is designed to sense absolute pressures from ambient pressure to 650 psia with frequency responses from DC to 2 MHz. The sensor is based upon a sealed, deformable, circular LPCVD silicon nitride diaphragm. Absolute pressure is determined from diaphragm deflection, which is sensed with low-stress, micromechanical, LPCVD polysilicon piezoresistors. All materials and processes used for sensor fabrication are CMOS compatible, and are part of Sandia`s ongoing effort of CMOS integration with Micro-ElectroMechanical Systems (MEMS). Test results of individual sensors are presented along with process issues involving the release etch and metal step coverage.

  9. Investigation of III-V semiconductor heterostructures for post-Si-CMOS applications

    NASA Astrophysics Data System (ADS)

    Bhatnagar, Kunal

    Silicon complementary metal-oxide-semiconductor (CMOS) technology in the past few decades has been driven by aggressive device scaling to increase performance, reduce cost and lower power consumption. However, as devices are scaled below the 100 nm region, performance gain has become increasingly difficult to obtain by traditional scaling. As we move towards advanced technology nodes, materials innovation and physical architecture are becoming the primary enabler for performance enhancement in CMOS technology rather than scaling. One class of materials that can potentially result in improved electrical performance are III-V semiconductors, which are ideal candidates for replacing the channel in Si CMOS owing to their high electron mobilities and capabilities for band-engineering. This work is aimed towards the growth and characterization of III-V semiconductor heterostructures and their application in post-Si-CMOS devices. The two main components of this study include the integration of III-V compound semiconductors on silicon for tunnel-junction Esaki diodes, and the investigation of carrier transport properties in low-power III-V n-channel FETs under uniaxial strain for advanced III-V CMOS solutions. The integration of III-V compound semiconductors with Si can combine the cost advantage and maturity of the Si technology with the superior performance of III-V materials. We have demonstrated high quality epitaxial growth of GaAs and GaSb on Si (001) wafers through the use of various buffer layers including AlSb and crystalline SrTiO3. These GaSb/Si virtual substrates were used for the fabrication and characterization of InAs/GaSb broken-gap Esaki-tunnel diodes as a possible solution for heterojunction Tunnel-FETs. In addition, the carrier transport properties of InAs channels were evaluated under uniaxial strain for the potential use of strain solutions in III-V CMOS.

  10. CMOS technology: a critical enabler for free-form electronics-based killer applications

    NASA Astrophysics Data System (ADS)

    Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

    2016-05-01

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

  11. III-V/Ge channel MOS device technologies in nano CMOS era

    NASA Astrophysics Data System (ADS)

    Takagi, Shinichi; Zhang, Rui; Suh, Junkyo; Kim, Sang-Hyeon; Yokoyama, Masafumi; Nishi, Koichi; Takenaka, Mitsuru

    2015-06-01

    CMOS utilizing high-mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing III-V/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/III-V films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in III-V/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the III-V MOS device technologies, we mainly address the gate stack technology, III-V channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel III-V-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using III-V/Ge channels.

  12. Fabrication and characterization of a charge-biased CMOS-MEMS resonant gate field effect transistor

    NASA Astrophysics Data System (ADS)

    Chin, C. H.; Li, C. S.; Li, M. H.; Wang, Y. L.; Li, S. S.

    2014-09-01

    A high-frequency charge-biased CMOS-MEMS resonant gate field effect transistor (RGFET) composed of a metal-oxide composite resonant-gate structure and an FET transducer has been demonstrated utilizing the TSMC 0.35 μm CMOS technology with Q > 1700 and a signal-to-feedthrough ratio greater than 35 dB under a direct two-port measurement configuration. As compared to the conventional capacitive-type MEMS resonators, the proposed CMOS-MEMS RGFET features an inherent transconductance gain (gm) offered by the FET transduction capable of enhancing the motional signal of the resonator and relaxing the impedance mismatch issue to its succeeding electronics or 50 Ω-based test facilities. In this work, we design a clamped-clamped beam resonant-gate structure right above a floating gate FET transducer as a high-Q building block through a maskless post-CMOS process to combine merits from the large capacitive transduction areas of the large-width beam resonator and the high gain of the underneath FET. An analytical model is also provided to simulate the behavior of the charge-biased RGFET; the theoretical prediction is in good agreement with the experimental results. Thanks to the deep-submicrometer gap spacing enabled by the post-CMOS polysilicon release process, the proposed resonator under a purely capacitive transduction already attains motional impedance less than 10 kΩ, a record-low value among CMOS-MEMS capacitive resonators. To go one step further, the motional signal of the proposed RGFET is greatly enhanced through the FET transduction. Such a strong transmission and a sharp phase transition across 0° pave a way for future RGFET-type oscillators in RF and sensor applications. A time-elapsed characterization of the charge leakage rate for the floating gate is also carried out.

  13. Design and experimental demonstration of low-power CMOS magnetic cell manipulation platform using charge recycling technique

    NASA Astrophysics Data System (ADS)

    Niitsu, Kiichi; Yoshida, Kohei; Nakazato, Kazuo

    2016-03-01

    We present the world’s first charge-recycling-based low-power technique of complementary metal-oxide-semiconductor (CMOS) magnetic cell manipulation. CMOS magnetic cell manipulation associated with magnetic beads is a promissing tool for on-chip biomedical-analysis applications such as drug screening because CMOS can integrate control electronics and electro-chemical sensors. However, the conventional CMOS cell manipulation requires considerable power consumption. In this work, by concatenating multiple unit circuits and recycling electric charge among them, power consumption is reduced by a factor of the number of the concatenated unit circuits (1/N). For verifying the effectiveness, test chip was fabricated in a 0.6-µm CMOS. The chip successfully manipulates magnetic microbeads with achieving 49% power reduction (from 51 to 26.2 mW). Even considering the additional serial resistance of the concatenated inductors, nearly theoretical power reduction effect can be confirmed.

  14. Wireless power transmission for biomedical implants: The role of near-zero threshold CMOS rectifiers.

    PubMed

    Mohammadi, Ali; Redoute, Jean-Michel; Yuce, Mehmet R

    2015-01-01

    Biomedical implants require an electronic power conditioning circuitry to provide a stable electrical power supply. The efficiency of wireless power transmission is strongly dependent on the power conditioning circuitry specifically the rectifier. A cross-connected CMOS bridge rectifier is implemented to demonstrate the impact of thresholds of rectifiers on wireless power transfer. The performance of the proposed rectifier is experimentally compared with a conventional Schottky diode full wave rectifier over 9 cm distance of air and tissue medium between the transmitter and receiver. The output voltage generated by the CMOS rectifier across a 1 KΩ resistive load is around twice as much as the Schottky rectifier. PMID:26737525

  15. Use of CMOS imagers to measure high fluxes of charged particles

    NASA Astrophysics Data System (ADS)

    Servoli, L.; Tucceri, P.

    2016-03-01

    The measurement of high flux charged particle beams, specifically at medical accelerators and with small fields, poses several challenges. In this work we propose a single particle counting method based on CMOS imagers optimized for visible light collection, exploiting their very high spatial segmentation (> 3 106 pixels/cm2) and almost full efficiency detection capability. An algorithm to measure the charged particle flux with a precision of ~ 1% for fluxes up to 40 MHz/cm2 has been developed, using a non-linear calibration algorithm, and several CMOS imagers with different characteristics have been compared to find their limits on flux measurement.

  16. Prediction and measurement of radiation damage to CMOS devices on board spacecraft

    NASA Technical Reports Server (NTRS)

    Cliff, R. A.; Danchenko, V.; Stassinopoulos, E. G.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

    1976-01-01

    The initial results obtained from the Complementary Metal Oxide Semiconductors Radiation Effects Measurement experiment are presented. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on the ground simulation experiment with Co 60, indicated that the measured space damage is greater than predicted by a factor of two for shields thicker than 100 mils (2.54 mm), but agrees well with predictions for the thinner shields.

  17. 180 Degree Hybrid (Rat-Race) Junction on CMOS Grade Silicon with a Polyimide Interface Layer

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Papapolymerou, John

    2003-01-01

    180-degree hybrid junctions can be used to equally divide power between two output ports with either a 0 or 180-degree phase difference. Alternatively, they can be used to combine signals from two sources and output a sum and difference signal. The main limitation of implementing; these on CMOS grade silicon is the high loss associated with the substrate. In this paper, we present a low loss 180-degree hybrid junction on CMOS grade (15 omega-cm) silicon with a polyimide interface layer for the first time. The divider utilizes Finite Ground Coplanar (FGC) line technology, and operates at a center frequency of 15 GIIz.

  18. A novel CMOS sensor with in-pixel auto-zeroed discrimination for charged particle tracking

    NASA Astrophysics Data System (ADS)

    Degerli, Y.; Guilloux, F.; Orsini, F.

    2014-05-01

    With the aim of developing fast and granular Monolithic Active Pixels Sensors (MAPS) as new charged particle tracking detectors for high energy physics experiments, a new rolling shutter binary pixel architecture concept (RSBPix) with in-pixel correlated double sampling, amplification and discrimination is presented. The discriminator features auto-zeroing in order to compensate process-related transistor mismatches. In order to validate the pixel, a first monolithic CMOS sensor prototype, including a pixel array of 96 × 64 pixels, has been designed and fabricated in the Tower-Jazz 0.18 μm CMOS Image Sensor (CIS) process. Results of laboratory tests are presented.

  19. A standard CMOS high-voltage transmitter for ultrasound medical imaging applications

    NASA Astrophysics Data System (ADS)

    Cha, Hyouk-Kyu

    2014-03-01

    A high-voltage (HV) transmitter for ultrasound medical imaging applications is designed using 0.18-µm CMOS (complementary metal oxide semiconductor) technology. The proposed HV transmitter achieves high integration by employing standard CMOS transistors in a stacked configuration with dynamic gate biasing circuit while successfully driving the capacitive output load with an HV pulse without device breakdown reliability issues. The HV transmitter, which includes the output driver and voltage level-shifters, generates up to 30-Vp-p pulses at 1.25 MHz frequency and occupies 0.035 mm² of layout area.

  20. Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

    NASA Technical Reports Server (NTRS)

    Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

    2012-01-01

    Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

  1. Characterization of an x-ray hybrid CMOS detector with low interpixel capacitive crosstalk

    NASA Astrophysics Data System (ADS)

    Griffith, Christopher V.; Bongiorno, Stephen D.; Burrows, David N.; Falcone, Abraham D.; Prieskorn, Zachary R.

    2012-07-01

    We present the results of x-ray measurements on a hybrid CMOS detector that uses a H2RG ROIC and a unique bonding structure. The silicon absorber array has a 36μm pixel size, and the readout array has a pitch of 18μm but only one readout circuit line is bonded to each 36x36μm absorber pixel. This unique bonding structure gives the readout an effective pitch of 36μm. We find the increased pitch between readout bonds significantly reduces the interpixel capacitance of the CMOS detector reported by Bongiorno et al. 20101 and Kenter et al. 2005.2

  2. Compact all-CMOS spatiotemporal compressive sensing video camera with pixel-wise coded exposure.

    PubMed

    Zhang, Jie; Xiong, Tao; Tran, Trac; Chin, Sang; Etienne-Cummings, Ralph

    2016-04-18

    We present a low power all-CMOS implementation of temporal compressive sensing with pixel-wise coded exposure. This image sensor can increase video pixel resolution and frame rate simultaneously while reducing data readout speed. Compared to previous architectures, this system modulates pixel exposure at the individual photo-diode electronically without external optical components. Thus, the system provides reduction in size and power compare to previous optics based implementations. The prototype image sensor (127 × 90 pixels) can reconstruct 100 fps videos from coded images sampled at 5 fps. With 20× reduction in readout speed, our CMOS image sensor only consumes 14μW to provide 100 fps videos.

  3. Automatic Synthesis of CMOS Algorithmic Analog To-Digital Converter.

    NASA Astrophysics Data System (ADS)

    Jusuf, Gani

    The steady decrease in technological feature size is allowing increasing levels of integration in analog/digital interface functions. These functions consist of analog as well as digital circuits. While the turn around time for an all digital IC chip is very short due to the maturity of digital IC computer-aided design (CAD) tools over the last ten years, most analog circuits have to be designed manually due to the lack of analog IC CAD tools. As a result, analog circuit design becomes the bottleneck in the design of mixed signal processing chips. One common analog function in a mixed signal processing chip is an analog-to-digital conversion (ADC) function. This function recurs frequently but with varying performance requirements. The objective of this research is to study the design methodology of a compilation program capable of synthesizing ADC's with a broad range of sampling rates and resolution, and silicon area and performance comparable with the manual approach. The automatic compilation of the ADC function is a difficult problem mainly because ADC techniques span such a wide spectrum of performance, with radically different implementations being optimum for different ranges of conversion range, resolution, and power dissipation. We will show that a proper choice of the ADC architectures and the incorporation of many analog circuit design techniques will simplify the synthesis procedure tremendously. Moreover, in order to speed up the device sizing, hierarchical optimization procedure and behavioral simulation are implemented into the ADC module generation steps. As a result of this study, a new improved algorithmic ADC without the need of high precision comparators has been developed. This type of ADC lends itself to automatic generation due to its modularity, simplicity, small area consumption, moderate speed, low power dissipation, and single parameter trim capability that can be added at high resolution. Furthermore, a performance-driven CMOS ADC module

  4. Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

    PubMed Central

    Noack, Marko; Partzsch, Johannes; Mayr, Christian G.; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

    2015-01-01

    Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm2 and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling. PMID:25698914

  5. Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS.

    PubMed

    Noack, Marko; Partzsch, Johannes; Mayr, Christian G; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

    2015-01-01

    Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm(2) and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling. PMID:25698914

  6. Adaptive Development

    NASA Technical Reports Server (NTRS)

    2005-01-01

    The goal of this research is to develop and demonstrate innovative adaptive seal technologies that can lead to dramatic improvements in engine performance, life, range, and emissions, and enhance operability for next generation gas turbine engines. This work is concentrated on the development of self-adaptive clearance control systems for gas turbine engines. Researchers have targeted the high-pressure turbine (HPT) blade tip seal location for following reasons: Current active clearance control (ACC) systems (e.g., thermal case-cooling schemes) cannot respond to blade tip clearance changes due to mechanical, thermal, and aerodynamic loads. As such they are prone to wear due to the required tight running clearances during operation. Blade tip seal wear (increased clearances) reduces engine efficiency, performance, and service life. Adaptive sealing technology research has inherent impact on all envisioned 21st century propulsion systems (e.g. distributed vectored, hybrid and electric drive propulsion concepts).

  7. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    NASA Astrophysics Data System (ADS)

    Fiorini, M.; Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2014-12-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×1012 1 MeV neq /cm2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 1014 cm-2 and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  8. Adaptive management

    USGS Publications Warehouse

    Allen, Craig R.; Garmestani, Ahjond S.

    2015-01-01

    Adaptive management is an approach to natural resource management that emphasizes learning through management where knowledge is incomplete, and when, despite inherent uncertainty, managers and policymakers must act. Unlike a traditional trial and error approach, adaptive management has explicit structure, including a careful elucidation of goals, identification of alternative management objectives and hypotheses of causation, and procedures for the collection of data followed by evaluation and reiteration. The process is iterative, and serves to reduce uncertainty, build knowledge and improve management over time in a goal-oriented and structured process.

  9. Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

    PubMed

    Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

    2016-01-01

    In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices. PMID:27302586

  10. A CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) oscillator

    NASA Astrophysics Data System (ADS)

    Chin, Chi-Hang; Li, Ming-Huang; Chen, Chao-Yu; Wang, Yu-Lin; Li, Sheng-Shian

    2015-11-01

    A high-frequency CMOS-MEMS arrayed resonant-gate field effect transistor (RGFET) fabricated by a standard 0.35 μm 2-poly-4-metal CMOS-MEMS platform is implemented to enable a Pierce-type oscillator. The proposed arrayed RGFET exhibits low motional impedance of only 5 kΩ under a purely capacitive transduction and decent power handling capability. With such features, the implemented oscillator shows impressive phase noise of  -117 dBc Hz-1 at the far-from-carrier offset (1 MHz). In this work, we design a clamped-clamped beam (CCB) arrayed resonator utilizing a high-velocity mechanical coupling scheme to serve as the resonant-gate array. To achieve a functional arrayed RGFET, a corresponding FET array is directly placed underneath the resonant gate array to convert the motional current on the resonant-gate array into a voltage output with a tunable transconductance gain. To understand the behavior of the proposed device, an equivalent circuit model consisting of the resonant unit and FET is also provided. To verify the effects of the post-CMOS process on device performance, a conventional MOS I D current measurement is carried out. Finally, a CMOS-MEMS arrayed RGFET oscillator is realized by utilizing a Pierce oscillator architecture, showing decent phase noise performance that benefits from the array design to alleviate the nonlinear effect of the resonant gate.

  11. Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

    PubMed Central

    Kim, Jong-Wan; Takao, Hidekuni; Sawada, Kazuaki; Ishida, Makoto

    2007-01-01

    This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiral inductors for an LC resonator and an integrated antenna have been fabricated and evaluated experimentally. The fabricated RF transmitter and integrated antenna were packaged with subminiature series A (SMA) connectors, respectively. For the impedance (50 Ω) matching, a bonding wire type inductor was developed. In this paper, the design and fabrication of the bonding wire inductor for impedance matching is described. Integrated techniques for the RF transmitter by CMOS compatible processes have been successfully developed. After matching by inserting the bonding wire inductor between the on-chip integrated antenna and the VCO output, the measured emission power at distance of 5 m from RF transmitter was -37 dBm (0.2 μW).

  12. Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits

    SciTech Connect

    Velazco, R.; Bessot, D. ); Duzellier, S. ); Ecoffet, R. ); Koga, R. )

    1994-12-01

    Two new CMOS memory cells, called HIT cells, designed to be SEU-immune are presented. Compared to previously reported design hardened solutions, the HIT cells feature better electrical performances and consume less silicon area. SEU tests performed on a prototype chip prove the efficiency of the approach.

  13. A large-scale ceramic package of the CMOS image sensor chip for remote sensing application

    NASA Astrophysics Data System (ADS)

    Chang, Chia-Hung; Ling, Jer; Lo, Shih-Hung; Hsu, Wen-Chih; Liu, Cynthia

    2012-10-01

    A CMOS image sensor chip with the ceramic package technique for remote sensing application is presented in this paper. The chip is fabricated using the United Microelectronics Corporation (UMC) 0.18 um CMOS technology and occupies 25 mm x 120 mm of chip area, which is much larger than the conventional ones. Furthermore, a trade-off in sealing of the cover glass faces the gas leak and moisture sorption. The package of the CMOS image sensor chip in space may cause crack, leakage, and deformation. Consequently, a large-scale and specific package is required to meet remote sensing application. The proposed ceramic package comprises a ceramic substrate, a cover glass, a chip seal, a glass seal, and golden lines. The dimension with lead is approximately 155 mm x 60 mm x 7.87 mm, including 76 Pin Grid Array (PGA) at each side. To demonstrate the reliabilities, the sensor with large-scale ceramic package is also analyzed, manufactured, and tested by the thermal shock, vibration, and vacuum tests. Moreover, the Coordinate Measuring Machine (CMM) is employed to measure the common plane of the package. By testing 12 points on the top plane of the package, the measured relatively peak-to-peak variation can be lower than 10 um. A large-scale ceramic package of the CMOS image sensor chip is implemented in this work to achieve the specifications of the remote sensing application in space.

  14. The use of light emission in failure analysis of CMOS ICs

    SciTech Connect

    Hawkins, C.F. . Dept. of Electrical and Computer Engineering); Soden, J.M.; Cole, E.I. Jr.; Snyder, E.S. )

    1990-01-01

    The use of photon emission for analyzing failure mechanisms and defects in CMOS ICs is presented. Techniques are given for accurate identification and spatial localization of failure mechanisms and physical defects, including defects such as short and open circuits which do not themselves emit photons.

  15. Design and fabrication of a CMOS-compatible MHP gas sensor

    SciTech Connect

    Li, Ying; Yu, Jun Wu, Hao; Tang, Zhenan

    2014-03-15

    A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

  16. Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

    NASA Astrophysics Data System (ADS)

    Rizzo, G.; Comott, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.; Gannaway, F.; Cenci, R.; Bombelli, L.; Citterio, M.; Coelli, S.; Fiorini, C.; Liberali, V.; Monti, M.; Nasri, B.; Neri, N.; Palombo, F.; Stabile, A.; Balestri, G.; Batignani, G.; Bernardelli, A.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Forti, F.; Giorgi, M. A.; Lusiani, A.; Mammini, P.; Morsani, F.; Oberhof, B.; Paoloni, E.; Perez, A.; Petragnani, G.; Profeti, A.; Soldani, A.; Walsh, J.; Chrzaszcz, M.; Gaioni, L.; Manazza, A.; Quartieri, E.; Ratti, L.; Zucca, S.; Alampi, G.; Cotto, G.; Gamba, D.; Zambito, S.; Dalla Betta, G.-F.; Fontana, G.; Pancheri, L.; Povoli, M.; Verzellesi, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Lanceri, L.; Liberti, B.; Rashevskaya, I.; Stella, C.; Vitale, L.

    2013-08-01

    In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10 - 15 μm in both coordinates, low material budget < 1 %X0, and the ability to withstand a background hit rate of several tens of MHz /cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

  17. Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks

    NASA Technical Reports Server (NTRS)

    Dogan, Numan S.

    2003-01-01

    The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

  18. A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Ye, Han; Quanliang, Li; Cong, Shi; Nanjian, Wu

    2013-08-01

    This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm2 was implemented in a 0.13 μm CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

  19. Method for implementation of back-illuminated CMOS or CCD imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor)

    2008-01-01

    A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

  20. SEMICONDUCTOR DEVICES: A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors

    NASA Astrophysics Data System (ADS)

    Miin-Horng, Juang; Chia-Wei, Chang; Der-Chih, Shye; Chuan-Chou, Hwang; Jih-Liang, Wang; Sheng-Liang, Jang

    2010-06-01

    A process simplification scheme for fabricating CMOS poly-Si thin-film transistors (TFTs) has been proposed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer (LATITS). By this LATITS scheme, a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus (or boron) dopant through the spacer, and then the n+-source/drain (n+-S/D) (or p+-S/D) region is formed via using the same photo-mask layer during CMOS integration. For both n-TFT and p-TFT devices, as compared to the sample with conventional single n+-S/D (or p+-S/D) structure, the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field. In addition, the resultant on-state currents only show slight degradation for the LATITS scheme. As a result, by the LATITS scheme, CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.

  1. Ka-Band, RF MEMS Switches on CMOS Grade Silicon with a Polyimide Interface Layer

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Varaljay, Nicholas C.; Papapolymerou, John

    2003-01-01

    For the first time, RF MEMS switcbes on CMOS grade Si witb a polyimide interface layer are fabricated and characterized. At Ka-Band (36.6 GHz), an insertion loss of 0.52 dB and an isolation of 20 dB is obtained.

  2. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    PubMed

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  3. An image identification system of seal with fingerprint based on CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Xue, Xu-cheng; Zhang, Shu-yan; Guo, Yong-fei

    2006-01-01

    CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analog signal conditioning circuits, A/D converter and digital processing functions. Furthermore, CMOS sensors are the best choices for low-cost imaging systems. An image identification system based on CMOS image sensor is used to identify the seal images that include fingerprint, and then determine whether the seal is fake or not. The system consists of a color CMOS image sensor (OV2610), a buffer memory, a CPLD, a MCU (P89C61X2), a USB2.0 interface chip (ISP1581) and a personal computer. The CPLD implement the logic and timing of the system. The MCU and the USB2.0 interface chip deal with the communications between the images acquisition system and PC. Thus PC can send some parameters and commands to the images acquisition system and also read image data from it. The identification of the images of seal is processed by the PC. The structure and scheme of the system are discussed in detail in this paper. Several test images of seal taken by the system are also provided in the paper.

  4. CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

    PubMed

    Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

    2011-04-01

    In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

  5. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking

    PubMed Central

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-01-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

  6. High-speed binary CMOS image sensor using a high-responsivity MOSFET-type photodetector

    NASA Astrophysics Data System (ADS)

    Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Choi, Pyung; Shin, Jang-Kyoo

    2015-03-01

    In this paper, a complementary metal oxide semiconductor (CMOS) binary image sensor based on a gate/body-tied (GBT) MOSFET-type photodetector is proposed. The proposed CMOS binary image sensor was simulated and measured using a standard CMOS 0.18-μm process. The GBT MOSFET-type photodetector is composed of a floating gate (n+- polysilicon) tied to the body (n-well) of the p-type MOSFET. The size of the active pixel sensor (APS) using GBT photodetector is smaller than that of APS using the photodiode. This means that the resolution of the image can be increased. The high-gain GBT photodetector has a higher photosensitivity compared to the p-n junction photodiode that is used in a conventional APS. Because GBT has a high sensitivity, fast operation of the binary processing is possible. A CMOS image sensor with the binary processing can be designed with simple circuits composed of a comparator and a Dflip- flop while a complex analog to digital converter (ADC) is not required. In addition, the binary image sensor has low power consumption and high speed operation with the ability to switch back and forth between a binary mode and an analog mode.

  7. Defect-sensitivity analysis of an SEU immune CMOS logic family

    NASA Technical Reports Server (NTRS)

    Ingermann, Erik H.; Frenzel, James F.

    1992-01-01

    Fault testing of resistive manufacturing defects is done on a recently developed single event upset immune logic family. Resistive ranges and delay times are compared with those of traditional CMOS logic. Reaction of the logic to these defects is observed for a NOR gate, and an evaluation of its ability to cope with them is determined.

  8. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

    PubMed

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  9. Creating a parameterized model of a CMOS transistor with a gate of enclosed layout

    NASA Astrophysics Data System (ADS)

    Vinogradov, S. M.; Atkin, E. V.; Ivanov, P. Y.

    2016-02-01

    The method of creating a parameterized spice model of an N-channel transistor with a gate of enclosed layout is considered. Formulas and examples of engineering calculations for use of models in the computer-aided Design environment of Cadence Vitruoso are presented. Calculations are made for the CMOS technology with 180 nm design rules of the UMC.

  10. On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

    NASA Technical Reports Server (NTRS)

    Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

    2008-01-01

    The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

  11. High performance rf front end circuits using SiGe:C BiCMOS+copper technologies

    NASA Astrophysics Data System (ADS)

    Watanabe, Glenn; Ortiz, Jeff; Holbrook, Rick

    2004-03-01

    Using a first generation standard silicon germanium (SiGe):C HBT BiCMOS process, a personal digital cellular (PDC) LNA noice factor (NF) of 1.0 dB at 850 MHz and 1.2 dB at 1.5 GHz has been achieved. The LNA NF can be further reduced by using the second generation enhanced SiGe:C HBT BiCMOS process. The mixer performance is equally impressive. The NF of the downconversion mixer at 1.5 GHz is just 6.2 dB with a conversion gain of 12 dB. The mixer IIP3 is +9.9 dBm at a current drain of 5.6 mA. Design techniques are given on how to achieve high linearity with minimal current drain resulting in a 881 MHz LNA with an IIP3 of +12.4 dBm with just 6 mA of current and a NF of 1.4 dB using the first generation SiGe:C HBT BiCMOS process. The second generation enhanced SiGe:C HBT BiCMOS process should further reduce the noise figure.

  12. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    PubMed Central

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  13. CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

    PubMed

    Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

    2011-04-01

    In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply. PMID:23851206

  14. Overview of CMOS process and design options for image sensor dedicated to space applications

    NASA Astrophysics Data System (ADS)

    Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

    2005-10-01

    With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

  15. Adaptive Thresholds

    SciTech Connect

    Bremer, P. -T.

    2014-08-26

    ADAPT is a topological analysis code that allow to compute local threshold, in particular relevance based thresholds for features defined in scalar fields. The initial target application is vortex detection but the software is more generally applicable to all threshold based feature definitions.

  16. Microactuateur electrothermique bistable: Etude d'implementation avec une technologie standard CMOS

    NASA Astrophysics Data System (ADS)

    Ressejac, Isabelle

    The general objective of this Ph.D. thesis was to study the implementation of a new type of eletrothermal microactuator. This actuator presents the advantages to be bistable and fabricated in a standard CMOS process, allowing the integration of a microelectronics addressing circuit on the same substrate. Experimental research work, presented in this thesis, relate to the different steps carried out in order to implement this CMOS MEMS device: its theoretical conception, its fabrication with a standard CMOS technology, its micromachining as a post-process, its characterization and its electro-thermo-mechanical modeling. The device was designed and fabricated by using Mitel 1,5 mum CMOS technology and the Can-MEMS service which are both available via the Canadian Microelectronics Corporation. Fabricated monolithically within a standard CMOS process, our microactuator is suitable for large-scale integration due to its small dimensions (length ˜1000 mum and width ˜150 mum). It constitutes the basic component of a N by N matrix controlled by a microelectronic addressing system built on the same substrate. Initially, only one micromachining technique (involving TMAH) was used, and long etching times (>9 h) were requires} in order to release the microstructures. However, the passivation layer from the CMOS process could protect the underlying metal from the TMAH for a sufficient time (only ˜1--2 h). Consequently, we had to develop a micromachining strategy with shorter etching times to allow the complete release of the microstructures without damaging them. Post-processing begins with deposition (by sputtering) of a platinum layer intended to protect the abutment from subsequent etching. Our micromachining strategy is mainly based on the use of a hybrid etching process starting with a first anisotropic TMAH etching followed by a XeF2 isotropic etching. After micromachining, the released microactuator has a significant initial deflection with its tip reaching a height

  17. CMOS cassette for digital upgrade of film-based mammography systems

    NASA Astrophysics Data System (ADS)

    Baysal, Mehmet A.; Toker, Emre

    2006-03-01

    While full-field digital mammography (FFDM) technology is gaining clinical acceptance, the overwhelming majority (96%) of the installed base of mammography systems are conventional film-screen (FSM) systems. A high performance, and economical digital cassette based product to conveniently upgrade FSM systems to FFDM would accelerate the adoption of FFDM, and make the clinical and technical advantages of FFDM available to a larger population of women. The planned FFDM cassette is based on our commercial Digital Radiography (DR) cassette for 10 cm x 10 cm field-of-view spot imaging and specimen radiography, utilizing a 150 micron columnar CsI(Tl) scintillator and 48 micron active-pixel CMOS sensor modules. Unlike a Computer Radiography (CR) cassette, which requires an external digitizer, our DR cassette transfers acquired images to a display workstation within approximately 5 seconds of exposure, greatly enhancing patient flow. We will present the physical performance of our prototype system against other FFDM systems in clinical use today, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and subjective criteria, such as a contrast-detail (CD-MAM) observer performance study. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for FFDM today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. This study promises to take advantage of these unique features to develop the first CMOS based FFDM upgrade cassette.

  18. Precision of FLEET Velocimetry Using High-Speed CMOS Camera Systems

    NASA Technical Reports Server (NTRS)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 microseconds, precisions of 0.5 meters per second in air and 0.2 meters per second in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision HighSpeed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  19. Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

    NASA Technical Reports Server (NTRS)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  20. Design and Fabrication of High-Efficiency CMOS/CCD Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2007-01-01

    An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the

  1. Detection of pointing errors with CMOS-based camera in intersatellite optical communications

    NASA Astrophysics Data System (ADS)

    Yu, Si-yuan; Ma, Jing; Tan, Li-ying

    2005-01-01

    For very high data rates, intersatellite optical communications hold a potential performance edge over microwave communications. Acquisition and Tracking problem is critical because of the narrow transmit beam. A single array detector in some systems performs both spatial acquisition and tracking functions to detect pointing errors, so both wide field of view and high update rate is required. The past systems tend to employ CCD-based camera with complex readout arrangements, but the additional complexity reduces the applicability of the array based tracking concept. With the development of CMOS array, CMOS-based cameras can employ the single array detector concept. The area of interest feature of the CMOS-based camera allows a PAT system to specify portion of the array. The maximum allowed frame rate increases as the size of the area of interest decreases under certain conditions. A commercially available CMOS camera with 105 fps @ 640×480 is employed in our PAT simulation system, in which only part pixels are used in fact. Beams angle varying in the field of view can be detected after getting across a Cassegrain telescope and an optical focus system. Spot pixel values (8 bits per pixel) reading out from CMOS are transmitted to a DSP subsystem via IEEE 1394 bus, and pointing errors can be computed by the centroid equation. It was shown in test that: (1) 500 fps @ 100×100 is available in acquisition when the field of view is 1mrad; (2)3k fps @ 10×10 is available in tracking when the field of view is 0.1mrad.

  2. Region-of-interest cone beam computed tomography (ROI CBCT) with a high resolution CMOS detector

    NASA Astrophysics Data System (ADS)

    Jain, A.; Takemoto, H.; Silver, M. D.; Nagesh, S. V. S.; Ionita, C. N.; Bednarek, D. R.; Rudin, S.

    2015-03-01

    Cone beam computed tomography (CBCT) systems with rotational gantries that have standard flat panel detectors (FPD) are widely used for the 3D rendering of vascular structures using Feldkamp cone beam reconstruction algorithms. One of the inherent limitations of these systems is limited resolution (<3 lp/mm). There are systems available with higher resolution but their small FOV limits them to small animal imaging only. In this work, we report on region-of-interest (ROI) CBCT with a high resolution CMOS detector (75 μm pixels, 600 μm HR-CsI) mounted with motorized detector changer on a commercial FPD-based C-arm angiography gantry (194 μm pixels, 600 μm HL-CsI). A cylindrical CT phantom and neuro stents were imaged with both detectors. For each detector a total of 209 images were acquired in a rotational protocol. The technique parameters chosen for the FPD by the imaging system were used for the CMOS detector. The anti-scatter grid was removed and the incident scatter was kept the same for both detectors with identical collimator settings. The FPD images were reconstructed for the 10 cm x10 cm FOV and the CMOS images were reconstructed for a 3.84 cm x 3.84 cm FOV. Although the reconstructed images from the CMOS detector demonstrated comparable contrast to the FPD images, the reconstructed 3D images of the neuro stent clearly showed that the CMOS detector improved delineation of smaller objects such as the stent struts (~70 μm) compared to the FPD. Further development and the potential for substantial clinical impact are suggested.

  3. Connector adapter

    NASA Technical Reports Server (NTRS)

    Hacker, Scott C. (Inventor); Dean, Richard J. (Inventor); Burge, Scott W. (Inventor); Dartez, Toby W. (Inventor)

    2007-01-01

    An adapter for installing a connector to a terminal post, wherein the connector is attached to a cable, is presented. In an embodiment, the adapter is comprised of an elongated collet member having a longitudinal axis comprised of a first collet member end, a second collet member end, an outer collet member surface, and an inner collet member surface. The inner collet member surface at the first collet member end is used to engage the connector. The outer collet member surface at the first collet member end is tapered for a predetermined first length at a predetermined taper angle. The collet includes a longitudinal slot that extends along the longitudinal axis initiating at the first collet member end for a predetermined second length. The first collet member end is formed of a predetermined number of sections segregated by a predetermined number of channels and the longitudinal slot.

  4. Adaptive VFH

    NASA Astrophysics Data System (ADS)

    Odriozola, Iñigo; Lazkano, Elena; Sierra, Basi

    2011-10-01

    This paper investigates the improvement of the Vector Field Histogram (VFH) local planning algorithm for mobile robot systems. The Adaptive Vector Field Histogram (AVFH) algorithm has been developed to improve the effectiveness of the traditional VFH path planning algorithm overcoming the side effects of using static parameters. This new algorithm permits the adaptation of planning parameters for the different type of areas in an environment. Genetic Algorithms are used to fit the best VFH parameters to each type of sector and, afterwards, every section in the map is labelled with the sector-type which best represents it. The Player/Stage simulation platform has been chosen for making all sort of tests and to prove the new algorithm's adequateness. Even though there is still much work to be carried out, the developed algorithm showed good navigation properties and turned out to be softer and more effective than the traditional VFH algorithm.

  5. Adaptive sampler

    DOEpatents

    Watson, B.L.; Aeby, I.

    1980-08-26

    An adaptive data compression device for compressing data is described. The device has a frequency content, including a plurality of digital filters for analyzing the content of the data over a plurality of frequency regions, a memory, and a control logic circuit for generating a variable rate memory clock corresponding to the analyzed frequency content of the data in the frequency region and for clocking the data into the memory in response to the variable rate memory clock.

  6. Adaptive sampler

    DOEpatents

    Watson, Bobby L.; Aeby, Ian

    1982-01-01

    An adaptive data compression device for compressing data having variable frequency content, including a plurality of digital filters for analyzing the content of the data over a plurality of frequency regions, a memory, and a control logic circuit for generating a variable rate memory clock corresponding to the analyzed frequency content of the data in the frequency region and for clocking the data into the memory in response to the variable rate memory clock.

  7. Adaptive antennas

    NASA Astrophysics Data System (ADS)

    Barton, P.

    1987-04-01

    The basic principles of adaptive antennas are outlined in terms of the Wiener-Hopf expression for maximizing signal to noise ratio in an arbitrary noise environment; the analogy with generalized matched filter theory provides a useful aid to understanding. For many applications, there is insufficient information to achieve the above solution and thus non-optimum constrained null steering algorithms are also described, together with a summary of methods for preventing wanted signals being nulled by the adaptive system. The three generic approaches to adaptive weight control are discussed; correlation steepest descent, weight perturbation and direct solutions based on sample matrix conversion. The tradeoffs between hardware complexity and performance in terms of null depth and convergence rate are outlined. The sidelobe cancellor technique is described. Performance variation with jammer power and angular distribution is summarized and the key performance limitations identified. The configuration and performance characteristics of both multiple beam and phase scan array antennas are covered, with a brief discussion of performance factors.

  8. Adaptive optics wavefront sensors based on photon-counting detector arrays

    NASA Astrophysics Data System (ADS)

    Aull, Brian F.; Schuette, Daniel R.; Reich, Robert K.; Johnson, Robert L.

    2010-07-01

    For adaptive optics systems, there is a growing demand for wavefront sensors that operate at higher frame rates and with more pixels while maintaining low readout noise. Lincoln Laboratory has been investigating Geiger-mode avalanche photodiode arrays integrated with CMOS readout circuits as a potential solution. This type of sensor counts photons digitally within the pixel, enabling data to be read out at high rates without the penalty of readout noise. After a brief overview of adaptive optics sensor development at Lincoln Laboratory, we will present the status of silicon Geigermode- APD technology along with future plans to improve performance.

  9. Structural alterations of the c-mos locus in benign pleomorphic adenomas with chromosome abnormalities of 8q12.

    PubMed

    Stenman, G; Sahlin, P; Mark, J; Landys, D

    1991-07-01

    Recent mapping studies have assigned the human c-mos proto-oncogene to chromosome 8, bands q11-12. This region is frequently affected by chromosomal translocations in benign pleomorphic adenomas of the salivary glands. Using Southern blot analysis we report here that the c-mos gene and its flanking sequences are structurally altered in pleomorphic adenomas with chromosomal rearrangements of 8q12. Rearrangements were detected in two out of 23 tumors. Restriction fragment analysis indicated that the rearrangements were due to multiple, subtle mutations involving the c-mos open reading frame and its flanking sequences. There was no direct evidence of translocation of mos in any of the tumors. Control DNAs from the two patients showed a normal restriction pattern for all enzymes tested, indicating that the rearrangements are tumor specific. Collectively, our cytogenetic and molecular data suggest involvement of the c-mos gene in the pathogenesis of pleomorphic adenomas.

  10. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  11. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  12. Integration of solid-state nanopores in a 0.5 μm cmos foundry process

    PubMed Central

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-01-01

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

  13. Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

    PubMed

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-04-19

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

  14. Compact all-CMOS spatiotemporal compressive sensing video camera with pixel-wise coded exposure.

    PubMed

    Zhang, Jie; Xiong, Tao; Tran, Trac; Chin, Sang; Etienne-Cummings, Ralph

    2016-04-18

    We present a low power all-CMOS implementation of temporal compressive sensing with pixel-wise coded exposure. This image sensor can increase video pixel resolution and frame rate simultaneously while reducing data readout speed. Compared to previous architectures, this system modulates pixel exposure at the individual photo-diode electronically without external optical components. Thus, the system provides reduction in size and power compare to previous optics based implementations. The prototype image sensor (127 × 90 pixels) can reconstruct 100 fps videos from coded images sampled at 5 fps. With 20× reduction in readout speed, our CMOS image sensor only consumes 14μW to provide 100 fps videos. PMID:27137331

  15. Measuring the Temperature of the Ithaca College MOT Cloud using a CMOS Camera

    NASA Astrophysics Data System (ADS)

    Smucker, Jonathan; Thompson, Bruce

    2015-03-01

    We present our work on measuring the temperature of Rubidium atoms cooled using a magneto-optical trap (MOT). The MOT uses laser trapping methods and Doppler cooling to trap and cool Rubidium atoms to form a cloud that is visible to a CMOS Camera. The Rubidium atoms are cooled further using optical molasses cooling after they are released from the trap (by removing the magnetic field). In order to measure the temperature of the MOT we take pictures of the cloud using a CMOS camera as it expands and calculate the temperature based on the free expansion of the cloud. Results from the experiment will be presented along with a summary of the method used.

  16. IR CMOS: the digital nightvision solution to sub-1 mLux imaging

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Vineis, C.; Palsule, C.; Jiang, J.; Joy, T.

    2015-05-01

    SiOnyx has demonstrated imaging at light levels below 1 mLux at 60 FPS with a 720P CMOS image sensor in a compact, low latency camera. The camera contains a 1 inch (16 mm) optical format sensor and streams uncompressed video over CameraLink with row wise image latency below 1 msec. Sub mLux imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancement is achieved by utilizing SiOnyx's proprietary ultrafast laser semiconductor processing technology that enhances the absorption of light within a thin pixel layer. Our technology demonstrates a 10 fold improvement in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see-spot.

  17. Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique

    PubMed Central

    Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

    2015-01-01

    A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm. PMID:26512671

  18. A low-power, CMOS peak detect and hold circuit for nuclear pulse spectroscopy

    SciTech Connect

    Ericson, M.N.; Simpson, M.L.; Britton, C.L.; Allen, M.D.; Kroeger, R.A.; Inderhees, S.E.

    1994-12-31

    A low-power CMOS peak detecting track and hold circuit optimized for nuclear pulse spectroscopy is presented. The circuit topology eliminates the need for a rectifying diode, reducing the effect of charge injection into the hold capacitor, incorporates a linear gate at the input to prevent pulse pileup, and uses dynamic bias control that minimizes both pedestal and droop. Both positive-going and negative-going pulses are accommodated using a complementary set of track and hold circuits. Full characterization of the design fabricated in 1.2{mu}m CMOS including dynamic range, integral nonlinearity, droop rate, pedestal, and power measurements is presented. Additionally, analysis and design approaches for optimization of operational characteristics are discussed.

  19. A highly sensitive CMOS digital Hall sensor for low magnetic field applications.

    PubMed

    Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

    2012-01-01

    Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ± 2 mT magnetic field and output a digital Hall signal in a wide temperature range from -40 °C to 120 °C.

  20. A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications

    PubMed Central

    Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

    2012-01-01

    Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ±2 mT magnetic field and output a digital Hall signal in a wide temperature range from −40 °C to 120 °C. PMID:22438758

  1. A New Fully Differential CMOS Capacitance to Digital Converter for Lab-on-Chip Applications.

    PubMed

    Nabovati, Ghazal; Ghafar-Zadeh, Ebrahim; Mirzaei, Maryam; Ayala-Charca, Giancarlo; Awwad, Falah; Sawan, Mohamad

    2015-06-01

    In this paper, we present a new differential CMOS capacitive sensor for Lab-on-Chip applications. The proposed integrated sensor features a DC-input ΣΔ capacitance to digital converter (CDC) and two reference and sensing microelectrodes integrated on the top most metal layer in 0.35 μm CMOS process. Herein, we describe a readout circuitry with a programmable clocking strategy using a Charge Based Capacitance Measurement technique. The simulation and experimental results demonstrate a high capacitive dynamic range of 100 fF-110 fF, the sensitivity of 350 mV/fF and the minimum detectable capacitance variation of as low as 10 aF. We also demonstrate and discuss the use of this device for environmental applications through various chemical solvents.

  2. Temperature coefficient of frequency modeling for CMOS-MEMS bulk mode composite resonators.

    PubMed

    Wang, Siping; Chen, Wen-Chien; Bahr, Bichoy; Fang, Weileun; Li, Sheng-Shian; Weinstein, Dana

    2015-06-01

    CMOS-MEMS resonators, which are promising building blocks for achieving monolithic integration of MEMS structure, can be used for timing and filtering applications, and control circuitry. SiO2 has been used to make MEMS resonators with quality factor Q > 10(4), but temperature instability remains a major challenge. In this paper, a design that uses an embedded metal block for temperature compensation is proposed and shows sub-ppm temperature stability (-0.21 ppm/K). A comprehensive analytical model is derived and applied to analyze and optimize the temperature coefficient of frequency (TCF) of the CMOS-MEMS composite material resonator. Comparison with finite element method simulation demonstrates good accuracy. The model can also be applied to predict and analyze the TCF of MEMS resonators with arbitrary mode shape, and its integration with simulation packages enables interactive and efficient design process.

  3. Analog CMOS design for optical coherence tomography signal detection and processing.

    PubMed

    Xu, Wei; Mathine, David L; Barton, Jennifer K

    2008-02-01

    A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of -80 dB is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented. PMID:18269983

  4. Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique.

    PubMed

    Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

    2015-10-23

    A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm.

  5. A monolithic, standard CMOS, fully differential optical receiver with an integrated MSM photodetector

    NASA Astrophysics Data System (ADS)

    Changliang, Yu; Luhong, Mao; Xindong, Xiao; Sheng, Xie; Shilin, Zhang

    2009-10-01

    This paper presents a realization of a silicon-based standard CMOS, fully differential optoelectronic integrated receiver based on a metal-semiconductor-metal light detector (MSM photodetector). In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photogenerated currents. The optoelectronic integrated receiver was designed and implemented in a chartered 0.35 μm, 3.3 V standard CMOS process. For 850 nm wavelength, it achieves a 1 GHz 3 dB bandwidth due to the MSM photodetector's low capacitance and high intrinsic bandwidth. In addition, it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to -3 dB frequency.

  6. 3D integration of planar crossbar memristive devices with CMOS substrate.

    PubMed

    Lin, Peng; Pi, Shuang; Xia, Qiangfei

    2014-10-10

    Planar memristive devices with bottom electrodes embedded into the substrates were integrated on top of CMOS substrates using nanoimprint lithography to implement hybrid circuits with a CMOL-like architecture. The planar geometry eliminated the mechanically and electrically weak parts, such as kinks in the top electrodes in a traditional crossbar structure, and allowed the use of thicker and thus less resistive metal wires as the bottom electrodes. Planar memristive devices integrated with CMOS have demonstrated much lower programing voltages and excellent switching uniformity. With the inclusion of the Moiré pattern, the integration process has sub-20 nm alignment accuracy, opening opportunities for 3D hybrid circuits in applications in the next generation of memory and unconventional computing.

  7. Advanced simulation technology for etching process design for CMOS device applications

    NASA Astrophysics Data System (ADS)

    Kuboi, Nobuyuki; Fukasawa, Masanaga; Tatsumi, Tetsuya

    2016-07-01

    Plasma etching is a critical process for the realization of high performance in the next generation of CMOS devices. To predict and control fluctuations in the etching properties accurately during mass production, it is essential that etching process simulation technology considers fluctuations in the plasma chamber wall conditions, the effects of by-products on the critical dimensions, the Si recess dependence on the wafer open area ratio and local pattern structure, and the time-dependent plasma-induced damage distribution associated with the three-dimensional feature scale profile at the 100 nm level. This consideration can overcome the issues with conventional simulations performed under the assumed ideal conditions, which are not accurate enough for practical process design. In this article, these advanced process simulation technologies are reviewed, and, from the results of suitable process simulations, a new etching system that automatically controls the etching properties is proposed to enable stable CMOS device fabrication with high yields.

  8. The optimization of zero-spaced microlenses for 2.2um pixel CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Nam, Hyun hee; Park, Jeong Lyeol; Choi, Jea Sung; Lee, Jeong Gun

    2007-03-01

    In CMOS image sensor, microlens arrays are generally used as light propagation carrier onto photo diode to increase collection efficiency and reduce optical cross-talk. Today, the scaling trend of CMOS technology drives reduction of the pixel size for higher integration density and resolution improvement. Microlenses are typically formed by photo resist patterning and thermal reflowing, and the space between photo resist is necessary to avoid merging of microlenses during thermal reflow process. With the shrinking sizes, microlenses become more and more difficult to manufacture without their merging. Hence, the key of light loss free microlens fabrication is still zero-space between microlenses. In this paper, we report the selection of the optimum shape of microlens by the dead space and the curvature of radius. The improvements of critical dimension and thickness uniformities of microlens are also reported.

  9. Characterization of zeolite-trench-embedded microcantilevers with CMOS strain gauge for integrated gas sensor applications

    NASA Astrophysics Data System (ADS)

    Inoue, Shu; Denoual, Matthieu; Awala, Hussein; Grand, Julien; Mintova, Sveltana; Tixier-Mita, Agnès; Mita, Yoshio

    2016-04-01

    Custom-synthesized zeolite is coated and fixed into microcantilevers with microtrenches of 1 to 5 µm width. Zeolite is a porous material that absorbs chemical substances; thus, it is expected to work as a sensitive chemical-sensing head. The total mass increases with gas absorption, and the cantilever resonance frequency decreases accordingly. In this paper, a thick zeolite cantilever sensor array system for high sensitivity and selectivity is proposed. The system is composed of an array of microcantilevers with silicon deep trenches. The cantilevers are integrated with CMOS-made polysilicon strain gauges for frequency response electrical measurement. The post-process fabrication of such an integrated array out of a foundry-made CMOS chip is successful. On the cantilevers, three types of custom zeolite (FAU-X, LTL, and MFI) are integrated by dip and heating methods. The preliminary measurement has shown a clear shift of resonance frequency by the chemical absorbance of ethanol gas.

  10. 2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

    PubMed Central

    2014-01-01

    We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm2. PMID:25045755

  11. Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation

    PubMed Central

    Raič, Dušan

    2014-01-01

    A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell. PMID:25538951

  12. Heterogeneous CMOS/memristor hardware neural networks for real-time target classification

    NASA Astrophysics Data System (ADS)

    Merkel, Cory; Kudithipudi, Dhireesha; Ptucha, Ray

    2014-05-01

    The advent of nanoscale metal-insulator-metal (MIM) structures with memristive properties has given birth to a new generation of hardware neural networks based on CMOS/memristor integration (CMHNNs). The advantage of the CMHNN paradigm compared to a pure CMOS approach lies in the multi-faceted functionality of memristive devices: They can efficiently store neural network configurations (weights and activation function parameters) via non-volatile, quasi-analog resistance states. They also provide high-density interconnects between neurons when integrated into 2-D and 3-D crossbar architectures. In this work, we explore the combination of CMHNN classifiers with manifold learning to reduce the dimensionality of CMHNN inputs. This allows the size of the CMHNN to be reduced significantly (by ≍ 97%). We tested the proposed system using the Caltech101 database and were able to achieve classification accuracies within ≍ 1:5% of those produced by a traditional support vector machine.

  13. Readout circuit design of the retina-like CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Cao, Fengmei; Song, Shengyu; Bai, Tingzhu; Cao, Nan

    2015-02-01

    Readout circuit is designed for a special retina-like CMOS image sensor. To realize the pixels timing drive and readout of the sensor, the Altera's Cyclone II FPGA is used as a control chip. The voltage of the sensor is supported by a voltage chip initialized by SPI with AVR MCU system. The analog image signal outputted by the sensor is converted to digital image data by 12-bits A/D converter ADS807 and the digital data is memorized in the SRAM. Using the Camera-link image grabber, the data stored in SRAM is transformed to image shown on PC. Experimental results show the circuit works well on retina-like CMOS timing drive and image readout and images can be displayed properly on the PC.

  14. Photon counting system based on intensified CMOS-APS: PC-IAPS

    NASA Astrophysics Data System (ADS)

    Bonanno, Giovanni; Belluso, Massimiliano; Cali, Antonio; Timpanaro, Maria C.; Uslenghi, Michela C.; Fiorini, Mauro; Modica, Angelo

    2001-12-01

    A progress report on the work, started ten months ago, aimed to evaluate the use of a new type of position sensor (Complementary Metal Oxide Semiconductor Active Pixel Sensor or CMOS-APS) as readout system in MCP-based intensified photon counting systems, is presented in this paper. The main differences respect to the more classical Photon Counting Intensified CCDs (PC-ICCD), the advantages and the disadvantages of their use as image photon counters, the adopted solutions to acquire the images and compute the photon event center, are described. The adopted optics and the designed mechanical assembly are also shown. The selected CMOS-APS, heart of the system, is treated in detail, as well as the electronics designed to drive the detector, to compute the center of the luminous spot on the MCP phosphor screen, and to send and receive data from a host computer. Finally we present preliminary results and achieved performances.

  15. Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique.

    PubMed

    Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

    2015-01-01

    A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm. PMID:26512671

  16. Ambient and cryogenic temperature testing of a 32-channel CMOS multiplexer

    NASA Technical Reports Server (NTRS)

    Lee, J. H.

    1983-01-01

    A 32 channel CMOS multiplexer was tested at room temperature and at liquid helium temperature (4.9 K). Voltage gain of the FET input stage, leakage current, electrical crosstalk, and noise as a function of clock frequency were measured. The voltage gain measured at 4.9 K was slightly higher than that measured at 300 K and was independent of clock frequency at both operating temperatures. The off channel leakage current was 0.23 pA/channel at 4.9 K. Electrical crosstalk between adjacent channels (one on, one off) was quite low. The spot noise at 10 Hz, of the CMOS multiplexer operating in the static mode did not vary significantly with operating temperature. In the dynamic mode (3.2 kHz clock) at room temperature, the spot noise at 10 Hz was substantially higher than that measured in the static mode.

  17. A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

    PubMed Central

    Feruglio, Sylvain; Lu, Guo-Neng; Garda, Patrick; Vasilescu, Gabriel

    2008-01-01

    A CMOS Buried Double Junction PN (BDJ) photodetector consists of two vertically-stacked photodiodes. It can be operated as a photodiode with improved performance and wavelength-sensitive response. This paper presents a review of this device and its applications. The CMOS implementation and operating principle are firstly described. This includes the description of several key aspects directly related to the device performances, such as surface reflection, photon absorption and electron-hole pair generation, photocurrent and dark current generation, etc. SPICE modelling of the detector is then presented. Next, design and process considerations are proposed in order to improve the BDJ performance. Finally, several BDJ-detector-based image sensors provide a survey of their applications.

  18. A CMOS detection chip for amperometric sensors with chopper stabilized incremental ΔΣ ADC

    NASA Astrophysics Data System (ADS)

    Min, Chen; Yuntao, Liu; Jingbo, Xiao; Jie, Chen

    2016-06-01

    This paper presents a low noise complimentary metal-oxide-semiconductor (CMOS) detection chip for amperometric electrochemical sensors. In order to effectively remove the input offset of the cascaded integrators and the low frequency noise in the modulator, a novel offset cancellation chopping scheme was proposed in the Incremental ΔΣ analog to digital converter (IADC). A novel low power potentiostat was employed in this chip to provide the biasing voltage for the sensor while mirroring the sensor current out for detection. The chip communicates with FPGA through standard built in I2C interface and SPI bus. Fabricated in 0.18-μm CMOS process, this chip detects current signal with high accuracy and high linearity. A prototype microsystem was produced to verify the detection chip performance with current input as well as micro-sensors. Project supported by the State Key Development Program for Basic Research of China (No. 2015CB352100).

  19. A CMOS analog front-end chip for amperometric electrochemical sensors

    NASA Astrophysics Data System (ADS)

    Zhichao, Li; Yuntao, Liu; Min, Chen; Jingbo, Xiao; Jie, Chen

    2015-07-01

    This paper reports a complimentary metal-oxide-semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter (Σ-Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. Project supported by the National Key Basic Research and Development Project (No. 2015CB352103).

  20. Neural CMOS-integrated circuit and its application to data classification.

    PubMed

    Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

    2012-05-01

    Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

  1. Monolithic optical phased-array transceiver in a standard SOI CMOS process.

    PubMed

    Abediasl, Hooman; Hashemi, Hossein

    2015-03-01

    Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system.

  2. The coding region of the human c-mos pseudogene contains Alu repeat insertions.

    PubMed

    Zabarovsky, E R; Chumakov, I M; Prassolov, V S; Kisselev, L L

    1984-10-01

    We have determined the nucleotide sequence of an 841-bp fragment derived from a segment of the human genome previously cloned by Chumakov et al. [Gene 17 (1982) 19-26] and Zabarovsky et al. [Gene 23 (1983) 379-384] and containing regions homologous to the viral mos gene probe. This sequence displays homology with part of the coding region of the human and murine c-mos genes, contains several termination codons, and is interrupted by two Alu-family elements flanked by short direct repeats. Probably, the progenitor of the human c-mos gene was duplicated approximately at the time of mammalian divergence, was converted to a pseudogene, and acquired insertions of two Alu elements.

  3. Monolithic optical phased-array transceiver in a standard SOI CMOS process.

    PubMed

    Abediasl, Hooman; Hashemi, Hossein

    2015-03-01

    Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system. PMID:25836869

  4. Intrinsic signal imaging of brain function using a small implantable CMOS imaging device

    NASA Astrophysics Data System (ADS)

    Haruta, Makito; Sunaga, Yoshinori; Yamaguchi, Takahiro; Takehara, Hironari; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Ohta, Jun

    2015-04-01

    A brain functional imaging technique over a long period is important to understand brain functions related to animal behavior. We have developed a small implantable CMOS imaging device for measuring brain activity in freely moving animals. This device is composed of a CMOS image sensor chip and LEDs for illumination. In this study, we demonstrated intrinsic signal imaging of blood flow using the device with a green LED light source at a peak wavelength of 535 nm, which corresponds to one of the absorption spectral peaks of blood cells. Brain activity increases regional blood flow. The device light weight of about 0.02 g makes it possible to stably measure brain activity through blood flow over a long period. The device has successfully measured the intrinsic signal related to sensory stimulation on the primary somatosensory cortex.

  5. Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

    NASA Technical Reports Server (NTRS)

    Buchner, S.; McMorrow, D.; Sibley, M.; Eaton, P.; Mavis, D.; Dusseau, L.; Roche, N. J-H.; Bernard, M.

    2009-01-01

    This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

  6. CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics

    NASA Astrophysics Data System (ADS)

    Sawadsaringkarn, Y.; Kimura, H.; Maezawa, Y.; Nakajima, A.; Kobayashi, T.; Sasagawa, K.; Noda, T.; Tokuda, T.; Ohta, J.

    2012-03-01

    A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure and packaging process for LED integration. The prototype device produced an illumination intensity of approximately 1 mW with a driving current of 2.0 mA, which is expected to be sufficient to activate channelrhodopsin (ChR2). We also demonstrated the functions of light stimulation and on-chip imaging using a brain slice from a mouse as a target sample.

  7. A CMOS detection chip for amperometric sensors with chopper stabilized incremental ΔΣ ADC

    NASA Astrophysics Data System (ADS)

    Min, Chen; Yuntao, Liu; Jingbo, Xiao; Jie, Chen

    2016-06-01

    This paper presents a low noise complimentary metal–oxide-semiconductor (CMOS) detection chip for amperometric electrochemical sensors. In order to effectively remove the input offset of the cascaded integrators and the low frequency noise in the modulator, a novel offset cancellation chopping scheme was proposed in the Incremental ΔΣ analog to digital converter (IADC). A novel low power potentiostat was employed in this chip to provide the biasing voltage for the sensor while mirroring the sensor current out for detection. The chip communicates with FPGA through standard built in I2C interface and SPI bus. Fabricated in 0.18-μm CMOS process, this chip detects current signal with high accuracy and high linearity. A prototype microsystem was produced to verify the detection chip performance with current input as well as micro-sensors. Project supported by the State Key Development Program for Basic Research of China (No. 2015CB352100).

  8. Indium bump array fabrication on small CMOS circuit for flip-chip bonding

    NASA Astrophysics Data System (ADS)

    Yuyang, Huang; Yuxiang, Zhang; Zhizhen, Yin; Guoxin, Cui; C, Liu H.; Lifeng, Bian; Hui, Yang; Yaohui, Zhang

    2011-11-01

    We demonstrate a novel method for indium bump fabrication on a small CMOS circuit chip that is to be flip-chip bonded with a GaAs/AlGaAs multiple quantum well spatial light modulator. A chip holder with a via hole is used to coat the photoresist for indium bump lift-off. The 1000 μm-wide photoresist edge bead around the circuit chip can be reduced to less than 500 μm, which ensures the integrity of the indium bump array. 64 × 64 indium arrays with 20 μm-high, 30 μm-diameter bumps are successfully formed on a 5 × 6.5 mm2 CMOS chip.

  9. Respiration detection chip with integrated temperature-insensitive MEMS sensors and CMOS signal processing circuits.

    PubMed

    Wei, Chia-Ling; Lin, Yu-Chen; Chen, Tse-An; Lin, Ren-Yi; Liu, Tin-Hao

    2015-02-01

    An airflow sensing chip, which integrates MEMS sensors with their CMOS signal processing circuits into a single chip, is proposed for respiration detection. Three micro-cantilever-based airflow sensors were designed and fabricated using a 0.35 μm CMOS/MEMS 2P4M mixed-signal polycide process. Two main differences were present among these three designs: they were either metal-covered or metal-free structures, and had either bridge-type or fixed-type reference resistors. The performances of these sensors were measured and compared, including temperature sensitivity and airflow sensitivity. Based on the measured results, the metal-free structure with fixed-type reference resistors is recommended for use, because it has the highest airflow sensitivity and also can effectively reduce the output voltage drift caused by temperature change.

  10. Optical readout of a triple-GEM detector by means of a CMOS sensor

    NASA Astrophysics Data System (ADS)

    Marafini, M.; Patera, V.; Pinci, D.; Sarti, A.; Sciubba, A.; Spiriti, E.

    2016-07-01

    In last years, the development of optical sensors has produced objects able to provide very interesting performance. Large granularity is offered along with a very high sensitivity. CMOS sensors with millions of pixels able to detect as few as two or three photons per pixel are commercially available and can be used to read-out the optical signals provided by tracking particle detectors. In this work the results obtained by optically reading-out a triple-GEM detector by a commercial CMOS sensor will be presented. A standard detector was assembled with a transparent window below the third GEM allowing the light to get out. The detector is supplied with an Ar/CF4 based gas mixture producing 650 nm wavelength photons matching the maximum quantum efficiency of the sensor.

  11. A CMOS compatible Microbulk Micromegas-like detector using silicon oxide as spacer material

    NASA Astrophysics Data System (ADS)

    Blanco Carballo, V. M.; Fransen, M.; van der Graaf, H.; Lu, J.; Schmitz, J.

    2011-02-01

    We present a new Micro Pattern Gaseous Detector (MPGD) fabricated with nonpolymeric materials. The device structure is similar to a Microbulk Micromegas design, consisting of a punctured metal grid supported by a continuous perforated insulating structure. In this detector, the supporting structure is made out of silicon oxide. Devices were tested in He/ iC 4H 10 (80/20) and Ar/ iC 4H 10 (80/20) gas mixtures under 55Fe irradiation. Gas gain of 20,000 and energy resolution below 13% FWHM were achieved. The CMOS compatibility of the fabrication process has been studied in Timepix chips as well as individual 0.13-μm technology CMOS transistors. Complete detectors have been fabricated on top of Timepix chips. In an Ar/ iC 4H 10 (80/20) gas mixture 55Fe decay events were recorded operating the Timepix chip in 2D readout mode.

  12. A low power 3.125 Gbps CMOS analog equalizer for serial links

    NASA Astrophysics Data System (ADS)

    Hao, Ju; Yumei, Zhou; Yishu, Jiao

    2010-11-01

    A CMOS analog equalizer is designed to meet the different high speed communication specifications, such as USB 2.0, PCI-E and rapid IO. The proposed circuit architecture could facilitate the wide frequency scale ranging from 1 to 3.125 Gbps by adjusting the locations of pole and zero, so that the circuit can change its response accordingly as the channel characteristic alters. In order to balance the parasitic capacitors in the internal point, symmetric switches are addressed to generate the equal load for differential signals. A prototype chip was fabricated in 0.13-μm 1P8M mix-signal CMOS technology. The actual area is 0.49 × 0.5 mm2, and the analog equalizer operates up to 3.125 Gbps over 3 m RG-58 coaxial cable and 50 cm FR4-PCB trace. The overall power dissipation is approximately 14.4 mW.

  13. High-speed modulator with interleaved junctions in zero-change CMOS photonics

    NASA Astrophysics Data System (ADS)

    Alloatti, L.; Cheian, D.; Ram, R. J.

    2016-03-01

    A microring depletion modulator is demonstrated with T-shaped lateral p-n junctions used to realize efficient modulation while maximizing the RC limited bandwidth. The device having a 3 dB bandwidth of 13 GHz has been fabricated in a standard 45 nm microelectronics CMOS process. The cavity has a linewidth of 17 GHz and an average wavelength-shift of 9 pm/V in reverse-bias conditions.

  14. A compact picosecond pulsed laser source using a fully integrated CMOS driver circuit

    NASA Astrophysics Data System (ADS)

    He, Yuting; Li, Yuhua; Yadid-Pecht, Orly

    2016-03-01

    Picosecond pulsed laser source have applications in areas such as optical communications, biomedical imaging and supercontinuum generation. Direct modulation of a laser diode with ultrashort current pulses offers a compact and efficient approach to generate picosecond laser pulses. A fully integrated complementary metaloxide- semiconductor (CMOS) driver circuit is designed and applied to operate a 4 GHz distributed feedback laser (DFB). The CMOS driver circuit combines sub-circuits including a voltage-controlled ring oscillator, a voltagecontrolled delay line, an exclusive-or (XOR) circuit and a current source circuit. Ultrashort current pulses are generated by the XOR circuit when the delayed square wave is XOR'ed with the original square wave from the on-chip oscillator. Circuit post-layout simulation shows that output current pulses injected into an equivalent circuit load of the laser have a pulse full width at half maximum (FWHM) of 200 ps, a peak current of 80 mA and a repetition rate of 5.8 MHz. This driver circuit is designed in a 0.13 μm CMOS process and taped out on a 0.3 mm2 chip area. This CMOS chip is packaged and interconnected with the laser diode on a printed circuit board (PCB). The optical output waveform from the laser source is captured by a 5 GHz bandwidth photodiode and an 8 GHz bandwidth oscilloscope. Measured results show that the proposed laser source can output light pulses with a pulse FWHM of 151 ps, a peak power of 6.4 mW (55 mA laser peak forward current) and a repetition rate of 5.3 MHz.

  15. A 70-MHz 32-b microprocessor with 1. 0-. mu. m BiCMOS macrocell library

    SciTech Connect

    Hotta, T.; Bandoh, T. . Hitachi Research Lab.); Hotta, A.; Nakano, T. ); Iwamoto, S.; Adachi, S. )

    1990-06-01

    A custom 529K-transistor microprocessor with a five-stage pipeline has been implemented on a 12.98-mm{sup 2} die. Employing BiCMOS macrocells, a 32-b execution unit, extendible ROM, RAM a PLL clock generator with bipolar drivers, and sense circuits, a peak performance of 70 MIPS is achieved. Power consumption is 2.1 W at 40 MHz.

  16. Design and Experimental Evaluation of a 3rd Generation Addressable CMOS Piezoresistive Stress Sensing Test Chip

    SciTech Connect

    Sweet, J.N.; Peterson, D.W.; Hsia, A.H.

    1999-04-13

    Piezoresistive stress sensing chips have been used extensively for measurement of assembly related die surface stresses. Although many experiments can be performed with resistive structures which are directly bonded, for extensive stress mapping it is necessary to have a large number of sensor cells which can be addressed using CMOS logic circuitry. Our previous test chip, the ATC04, has 100 cells, each approximately 0.012 in. on a side, on a chip with a side dimension of 0.45 in. When a cell resistor is addressed, it is connected to a four terminal measurement bus through CMOS transmission gates. In theory, the gate resistances do not affect the measurement. In practice, there may be subtle effects which appear when very high accuracy is required. At high temperatures, gate leakage can increase to a point at which the resistor measurement becomes inaccurate. For ATC04 this occurred at or above 50 C. Here, we report on the first measurements obtained with a new prototype test chip, the ATC06. This prototype was fabricated in a 0.5 micron feature size silicided CMOS process using the MOSIS prototyping facility. The cell size was approximately 0.004 in. on a side. In order to achieve piezoresistive behavior for the implanted resistors it was necessary to employ a non-standard silicide ''blocking'' process. The stress sensitivity of both implanted and polysilicon blocked resistors is discussed. Using a new design strategy for the CMOS logic, it was possible to achieve a design in which only 5 signals had to be routed to a cell for addressing vs. 9 for ATC04. With our new design, the resistor under test is more effectively electrically isolated from other resistors on the chip, thereby improving high temperature performance. We present data showing operation up to 140 C.

  17. Structure for implementation of back-illuminated CMOS or CCD imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Cunningham, Thomas J. (Inventor)

    2009-01-01

    A structure for implementation of back-illuminated CMOS or CCD imagers. An epitaxial silicon layer is connected with a passivation layer, acting as a junction anode. The epitaxial silicon layer converts light passing through the passivation layer and collected by the imaging structure to photoelectrons. A semiconductor well is also provided, located opposite the passivation layer with respect to the epitaxial silicon layer, acting as a junction cathode. Prior to detection, light does not pass through a dielectric separating interconnection metal layers.

  18. Single event transient pulse width measurement of 65-nm bulk CMOS circuits

    NASA Astrophysics Data System (ADS)

    Suge, Yue; Xiaolin, Zhang; Xinyuan, Zhao

    2015-11-01

    Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device threshold voltage, temperature and well separation on pulse width are discussed. Experimental data implied that the low device threshold, high temperature and well speraration would contribute to wider SET. The multi-peak phenomenon in the distribution of SET pulse width was first observed and its dependence on various factors is also discussed.

  19. Low-noise CMOS SPAD arrays with in-pixel time-to-digital converters

    NASA Astrophysics Data System (ADS)

    Tosi, Alberto; Villa, Federica; Bronzi, Danilo; Zou, Yu; Lussana, Rudi; Tamborini, Davide; Tisa, Simone; Durini, Daniel; Weyers, Sascha; Pashen, Uwe; Brockherde, Werner; Zappa, Franco

    2014-05-01

    We present our latest results concerning CMOS Single-Photon Avalanche Diode (SPAD) arrays for high-throughput parallel single-photon counting. We exploited a high-voltage 0.35 μm CMOS technology in order to develop low-noise CMOS SPADs. The Dark Count Rate is 30 cps at room temperature for 30 μm devices, increases to 2 kcps for 100 μm SPADs and just to 100 kcps for 500 μm ones. Afterpulsing is less than 1% for hold-off time longer than 50 ns, thus allowing to reach high count rates. Photon Detection Efficiency is > 50% at 420 nm, > 40% below 500 nm and is still 5% at 850 nm. Timing jitter is less than 100 ps (FWHM) in SPADs with active area diameter up to 50 μm. We developed CMOS SPAD imagers with 150 μm pixel pitch and 30 μm SPADs. A 64×32 SPAD array is based on pixels including three 9-bit counters for smart phase-resolved photon counting up to 100 kfps. A 32x32 SPAD array includes 1024 10-bit Time-to-Digital Converters (TDC) with 300 ps resolution and 450 ps single-shot precision, for 3D ranging and FLIM. We developed also linear arrays with up to 60 pixels (with 100 μm SPAD, 150 μm pitch and in-pixel 250 ps TDC) for time-resolved parallel spectroscopy with high fill factor.

  20. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    NASA Astrophysics Data System (ADS)

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  1. Ultra-low crosstalk, CMOS compatible waveguide crossings for densely integrated photonic interconnection networks.

    PubMed

    Jones, Adam M; DeRose, Christopher T; Lentine, Anthony L; Trotter, Douglas C; Starbuck, Andrew L; Norwood, Robert A

    2013-05-20

    We explore the design space for optimizing CMOS compatible waveguide crossings on a silicon photonics platform. This paper presents simulated and experimental excess loss and crosstalk suppression data for vertically integrated silicon nitride over silicon-on-insulator waveguide crossings. Experimental results show crosstalk suppression exceeding -49/-44 dB with simulation results as low as -65/-60 dB for the TE/TM mode in a waveguide crossing with a 410 nm vertical gap. PMID:23736422

  2. A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

    NASA Technical Reports Server (NTRS)

    Timoc, C.; Tran, T.; Wongso, J.

    1992-01-01

    This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

  3. Ultra-low crosstalk, CMOS compatible waveguide crossings for densely integrated photonic interconnection networks.

    PubMed

    Jones, Adam M; DeRose, Christopher T; Lentine, Anthony L; Trotter, Douglas C; Starbuck, Andrew L; Norwood, Robert A

    2013-05-20

    We explore the design space for optimizing CMOS compatible waveguide crossings on a silicon photonics platform. This paper presents simulated and experimental excess loss and crosstalk suppression data for vertically integrated silicon nitride over silicon-on-insulator waveguide crossings. Experimental results show crosstalk suppression exceeding -49/-44 dB with simulation results as low as -65/-60 dB for the TE/TM mode in a waveguide crossing with a 410 nm vertical gap.

  4. Real time M2 and beam parameter product measurement using GigE CMOS sensors

    NASA Astrophysics Data System (ADS)

    Scaggs, Michael; Haas, Gil

    2016-03-01

    The ISO 11146-1 standard for measurement of a laser's M-square requires the minimum measurement of five (5) spatial profiles within the first Rayleigh range and an addition five (5) outside the second Rayleigh range. The first five spatial profiles within the first Rayleigh range establish the beam waist and its location; the second five beyond the second Rayleigh range establish the divergence or convergence from the focusing lens for the M-square computation. The majority of methods used to date are all time averaged and as such are incapable of a real time M-square measurement. We present an ISO 11146-1 compliant method for measuring single shot M-square or beam parameter product values or the measurement of continuous wave sources at rates greater than five frames per second utilizing a pair of GigE based CMOS sensors. One GigE CMOS sensor is setup to measure the minimum of five spots within the first Rayleigh range for the establishment of the beam waist and its location. A second GigE CMOS sensor is setup to measure the five spatial profiles beyond the second Rayleigh range for the determination of the beam divergence from the focusing lens. Both GigE cameras utilize optics that passively create multiple spatial time slices of the beam and superimpose these time slices on the CMOS sensor in real time resulting in the ability to make single pulse measurements or continuous wave measurements at speeds of greater than five frames per second with full ISO 11146-1 compliance.

  5. Resistive shorts characterization in CMOS standard cells for test pattern generation

    NASA Astrophysics Data System (ADS)

    Wielgus, Andrzej; Potrykus, Bartosz

    2013-07-01

    This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. Resistance of a short defect is taken into account while considering faulty behavior caused by this defect and finding the test vectors that detect this fault. Finally, all of found vectors are validated to check their effectiveness in fault covering and the optimal test sequence for all detectable faults is constructed. Experimental results for cells from industrial standard cell library are presented.

  6. Surprising patterns of CMOS susceptibility to ESD and implications on long-term reliability

    SciTech Connect

    Schwank, J.R.; Baker, R.P.; Armendariz, M.G.

    1980-01-01

    CMOS electrostatic discharge (ESD) failures in a product where, by design, the device input terminals are not accessible to ESD led to this study of device susceptibility and an analysis of the long-term reliability of devices in assemblies from that production line. Some surprising patterns of device susceptibility are established and it is shown that the probability of long-term failure in devices whose electrical characteristics have been degraded by electrostatic discharge is small.

  7. A low-temperature bridge-input CMOS circuit for low-impedance detector

    NASA Astrophysics Data System (ADS)

    Yuan, HongHui; Chen, YongPing

    2014-09-01

    Low-impedance long-wave infrared detectors (the wavelength longer than 10 microns) have very important applications in cryogenic aim detection, super-distance detection, anti-jamming target identify and so on. Therefore the research in the field of infrared detector technology is of importance. At present, no low-impedance photoconductive detectors are integrated with CMOS circuit. To design low-temperature CMOS circuit being fit for low impedance infrared photoconductive detector and realize high performance IR imaging, using differential amplifier with symmetrical positive and negative power is necessary, the low-resist detector is connected between an input and grounding, the corresponding low resistance is connected between another input and grounding, a larger feedback resistor is used between negative input and output, this structure can effectively solve the matching problem of low-impedance and high-impedance CMOS. In addition, the noise voltage from VBIAS terminal can be effectively reduced by increasing the ratio of the bias resistor and the detector resistance. The whole circuit is designed two grade. The first grade is adopted bridge input structure, this structure is fit for low impedance detector. The positive amplifying method is applied in second grade . The first grade feedback resistance is designed 1M ohm, the circuit is supplied by +/-1.5V. The testing showed that the circuit can work well when it connects with low-impedance infrared photoconductive detector at the liquid nitrogen low temperature. The magnification is up to 30000 times, 3dB bandwidth is more than 4kHz, the equivalent input noise is near 1.5 micron volts. This circuit has perfectly solved the matching problem between high impedance CMOS circuit and low impedance detector.

  8. CLARO-CMOS: a fast, low power and radiation-hard front-end ASIC for single-photon counting in 0.35 micron CMOS technology

    NASA Astrophysics Data System (ADS)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-01-01

    The CLARO-CMOS is a prototype ASIC designed for fast photon counting with multi-anode photomultiplier tubes (MaPMT). The CLARO features a 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. The chip was designed in 0.35 μm CMOS technology, and was tested for radiation hardness with neutrons up to 1014 1 MeV neq/cm2, X-rays up to 40 kGy and protons up to 76 kGy. Its capability to read out single photons at high rate from a Hamamatsu R11265 MaPMT, the baseline photon detector for the LHCb RICH upgrade, was demonstrated both with test bench measurements and with actual signals from a R11265 MaPMT. The presented results allowed CLARO to be chosen as the front-end readout chip in the upgraded LHCb RICH detector.

  9. Charge collection and non-ionizing radiation tolerance of CMOS pixel sensors using a 0.18 μm CMOS process

    NASA Astrophysics Data System (ADS)

    Zhang, Ying; Zhu, Hongbo; Zhang, Liang; Fu, Min

    2016-09-01

    The proposed Circular Electron Positron Collider (CEPC) will be primarily aimed for precision measurements of the discovered Higgs boson. Its innermost vertex detector, which will play a critical role in heavy-flavor tagging, must be constructed with fine-pitched silicon pixel sensors with low power consumption and fast readout. CMOS pixel sensor (CPS), as one of the most promising candidate technologies, has already demonstrated its excellent performance in several high energy physics experiments. Therefore it has been considered for R&D for the CEPC vertex detector. In this paper, we present the preliminary studies to improve the collected signal charge over the equivalent input capacitance ratio (Q / C), which will be crucial to reduce the analog power consumption. We have performed detailed 3D device simulation and evaluated potential impacts from diode geometry, epitaxial layer properties and non-ionizing radiation damage. We have proposed a new approach to improve the treatment of the boundary conditions in simulation. Along with the TCAD simulation, we have designed the exploratory prototype utilizing the TowerJazz 0.18 μm CMOS imaging sensor process and we will verify the simulation results with future measurements.

  10. Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

    PubMed Central

    López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

    2011-01-01

    We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

  11. A New Automated Design Method Based on Machine Learning for CMOS Analog Circuits

    NASA Astrophysics Data System (ADS)

    Moradi, Behzad; Mirzaei, Abdolreza

    2016-11-01

    A new simulation based automated CMOS analog circuit design method which applies a multi-objective non-Darwinian-type evolutionary algorithm based on Learnable Evolution Model (LEM) is proposed in this article. The multi-objective property of this automated design of CMOS analog circuits is governed by a modified Strength Pareto Evolutionary Algorithm (SPEA) incorporated in the LEM algorithm presented here. LEM includes a machine learning method such as the decision trees that makes a distinction between high- and low-fitness areas in the design space. The learning process can detect the right directions of the evolution and lead to high steps in the evolution of the individuals. The learning phase shortens the evolution process and makes remarkable reduction in the number of individual evaluations. The expert designer's knowledge on circuit is applied in the design process in order to reduce the design space as well as the design time. The circuit evaluation is made by HSPICE simulator. In order to improve the design accuracy, bsim3v3 CMOS transistor model is adopted in this proposed design method. This proposed design method is tested on three different operational amplifier circuits. The performance of this proposed design method is verified by comparing it with the evolutionary strategy algorithm and other similar methods.

  12. Implementation of the CMOS MEMS condenser microphone with corrugated metal diaphragm and silicon back-plate.

    PubMed

    Huang, Chien-Hsin; Lee, Chien-Hsing; Hsieh, Tsung-Min; Tsao, Li-Chi; Wu, Shaoyi; Liou, Jhyy-Cheng; Wang, Ming-Yi; Chen, Li-Che; Yip, Ming-Chuen; Fang, Weileun

    2011-01-01

    This study reports a CMOS-MEMS condenser microphone implemented using the standard thin film stacking of 0.35 μm UMC CMOS 3.3/5.0 V logic process, and followed by post-CMOS micromachining steps without introducing any special materials. The corrugated diaphragm for the microphone is designed and implemented using the metal layer to reduce the influence of thin film residual stresses. Moreover, a silicon substrate is employed to increase the stiffness of the back-plate. Measurements show the sensitivity of microphone is -42 ± 3 dBV/Pa at 1 kHz (the reference sound-level is 94 dB) under 6 V pumping voltage, the frequency response is 100 Hz-10 kHz, and the S/N ratio >55 dB. It also has low power consumption of less than 200 μA, and low distortion of less than 1% (referred to 100 dB). PMID:22163953

  13. Towards real-time VMAT verification using a prototype, high-speed CMOS active pixel sensor

    NASA Astrophysics Data System (ADS)

    Zin, Hafiz M.; Harris, Emma J.; Osmond, John P. F.; Allinson, Nigel M.; Evans, Philip M.

    2013-05-01

    This work investigates the feasibility of using a prototype complementary metal oxide semiconductor active pixel sensor (CMOS APS) for real-time verification of volumetric modulated arc therapy (VMAT) treatment. The prototype CMOS APS used region of interest read out on the chip to allow fast imaging of up to 403.6 frames per second (f/s). The sensor was made larger (5.4 cm × 5.4 cm) using recent advances in photolithographic technique but retains fast imaging speed with the sensor's regional read out. There is a paradigm shift in radiotherapy treatment verification with the advent of advanced treatment techniques such as VMAT. This work has demonstrated that the APS can track multi leaf collimator (MLC) leaves moving at 18 mm s-1 with an automatic edge tracking algorithm at accuracy better than 1.0 mm even at the fastest imaging speed. Evaluation of the measured fluence distribution for an example VMAT delivery sampled at 50.4 f/s was shown to agree well with the planned fluence distribution, with an average gamma pass rate of 96% at 3%/3 mm. The MLC leaves motion and linac pulse rate variation delivered throughout the VMAT treatment can also be measured. The results demonstrate the potential of CMOS APS technology as a real-time radiotherapy dosimeter for delivery of complex treatments such as VMAT.

  14. Superior performance with sCMOS over EMCCD in super-resolution optical fluctuation imaging

    NASA Astrophysics Data System (ADS)

    Chen, Xuanze; Zeng, Zhiping; Li, Rongqin; Xue, Boxin; Xi, Peng; Sun, Yujie

    2016-06-01

    Super-resolution optical fluctuation imaging (SOFI) is a fast and low-cost live-cell optical nanoscopy for extracting subdiffraction information from the statistics of fluorescence intensity fluctuation. As SOFI is based on the fluctuation statistics, rather than the detection of single molecules, it poses unique requirements for imaging detectors, which still lack a systematic evaluation. Here, we analyze the influences of pixel sizes, frame rates, noise levels, and different gains in SOFI with simulations and experimental tests. Our analysis shows that the smaller pixel size and faster readout speed of scientific-grade complementary metal oxide semiconductor (sCMOS) enables SOFI to achieve high spatiotemporal resolution with a large field-of-view, which is especially beneficial for live-cell super-resolution imaging. Overall, as the performance of SOFI is relatively insensitive to the signal-to-noise ratio (SNR), the gain in pixel size and readout speed exceeds the loss in SNR, indicating sCMOS is superior to electron multiplying charge coupled device in context to SOFI in many cases. Super-resolution imaging of cellular microtubule structures with high-order SOFI is experimentally demonstrated at large field-of-view, taking advantage of the large pixel number and fast frame rate of sCMOS cameras.

  15. Projection-reflection ultrasound images using PE-CMOS sensor: a preliminary bone fracture study

    NASA Astrophysics Data System (ADS)

    Lo, Shih-Chung B.; Liu, Chu-Chuan; Freedman, Matthew T.; Mun, Seong-Ki; Kula, John; Lasser, Marvin E.; Lasser, Bob; Wang, Yue Joseph

    2008-03-01

    In this study, we investigated the characteristics of the ultrasound reflective image obtained by a CMOS sensor array coated with piezoelectric material (PE-CMOS). The laboratory projection-reflection ultrasound prototype consists of five major components: an unfocused ultrasound transducer, an acoustic beam splitter, an acoustic compound lens, a PE-CMOS ultrasound sensing array (Model I400, Imperium Inc. Silver Spring, MD), and a readout circuit system. The prototype can image strong reflective materials such as bone and metal. We found this projection-reflection ultrasound prototype is able to reveal hairline bone fractures with and without intact skin and tissue. When compared, the image generated from a conventional B-scan ultrasound on the same bone fracture is less observable. When it is observable with the B-scan system, the fracture or crack on the surface only show one single spot of echo due to its scan geometry. The corresponding image produced from the projection-reflection ultrasound system shows a bright blooming strip on the image clearly indicating the fracture on the surface of the solid material. Speckles of the bone structure are also observed in the new ultrasound prototype. A theoretical analysis is provided to link the signals as well as speckles detected in both systems.

  16. Low-dose performance of wafer-scale CMOS-based X-ray detectors

    NASA Astrophysics Data System (ADS)

    Maes, Willem H.; Peters, Inge M.; Smit, Chiel; Kessener, Yves; Bosiers, Jan

    2015-03-01

    Compared to published amorphous-silicon (TFT) based X-ray detectors, crystalline silicon CMOS-based active-pixel detectors exploit the benefits of low noise, high speed, on-chip integration and featuring offered by CMOS technology. This presentation focuses on the specific advantage of high image quality at very low dose levels. The measurement of very low dose performance parameters like Detective Quantum Efficiency (DQE) and Noise Equivalent Dose (NED) is a challenge by itself. Second-order effects like defect pixel behavior, temporal and quantization noise effects, dose measurement accuracy and limitation of the x-ray source settings will influence the measurements at very low dose conditions. Using an analytical model to predict the low dose behavior of a detector from parameters extracted from shot-noise limited dose levels is presented. These models can also provide input for a simulation environment for optimizing the performance of future detectors. In this paper, models for predicting NED and the DQE at very low dose are compared to measurements on different CMOS detectors. Their validity for different sensor and optical stack combinations as well as for different x-ray beam conditions was validated.

  17. On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS.

    PubMed

    Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

    2016-01-01

    An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<-9 dB) with excellent transmission efficiency (averagely -1.9 dB) from 110 GHz-325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author's knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology.

  18. A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

    PubMed Central

    Zhang, Fan; Niu, Hanben

    2016-01-01

    In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena. PMID:27367699

  19. An investigation of medical radiation detection using CMOS image sensors in smartphones

    NASA Astrophysics Data System (ADS)

    Kang, Han Gyu; Song, Jae-Jun; Lee, Kwonhee; Nam, Ki Chang; Hong, Seong Jong; Kim, Ho Chul

    2016-07-01

    Medical radiation exposure to patients has increased with the development of diagnostic X-ray devices and multi-channel computed tomography (CT). Despite the fact that the low-dose CT technique can significantly reduce medical radiation exposure to patients, the increasing number of CT examinations has increased the total medical radiation exposure to patients. Therefore, medical radiation exposure to patients should be monitored to prevent cancers caused by diagnostic radiation. However, without using thermoluminescence or glass dosimeters, it is hardly measure doses received by patients during medical examinations accurately. Hence, it is necessary to develop radiation monitoring devices and algorithms that are reasonably priced and have superior radiation detection efficiencies. The aim of this study is to investigate the feasibility of medical dose measurement using complementary metal oxide semiconductor (CMOS) sensors in smartphone cameras with an algorithm to extract the X-ray interacted pixels. We characterized the responses of the CMOS sensors in a smartphone with respect to the X-rays generated by a general diagnostic X-ray system. The characteristics of the CMOS sensors in a smartphone camera, such as dose response linearity, dose rate dependence, energy dependence, angular dependence, and minimum detectable activity were evaluated. The high energy gamma-ray of 662 keV from Cs-137 can be detected using the smartphone camera. The smartphone cameras which employ the developed algorithm can detect medical radiations.

  20. Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects

    PubMed Central

    Suh, Sungho; Itoh, Shinya; Aoyama, Satoshi; Kawahito, Shoji

    2010-01-01

    For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e− for the simple integration CMS and 75 dB and 2.2 e− for the folding integration CMS, respectively, are obtained. PMID:22163400