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Sample records for 90nm cmos technology

  1. Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node

    NASA Technical Reports Server (NTRS)

    Ladbury, Raymond L.; Gorelick, Jerry L.; Berg, M. D.; Kim, H.; LaBel, K.; Friendlich, M.; Koga, R.; George, J.; Crain, S.; Yu, P.; Reed, R. A.

    2006-01-01

    We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer.

  2. IC design of low power, wide tuning range VCO in 90 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Zhu, Li; Zhigong, Wang; Zhiqun, Li; Qin, Li; Faen, Liu

    2014-12-01

    A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET (IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27-32.5 GHz, exhibiting a frequency tuning range (FTR) of 18.4% and a phase noise of -101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of -185 dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 mA DC current.

  3. 10-bit segmented current steering DAC in 90nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Bringas, R., Jr.; Dy, F.; Gerasta, O. J.

    2015-06-01

    This special project presents a 10-Bit 1Gs/s 1.2V/3.3V Digital-to-Analog Converter using1 Poly 9 Metal SAED 90-nm CMOS Technology intended for mixed-signal and power IC applications. To achieve maximum performance with minimum area, the DAC has been implemented in 6+4 Segmentation. The simulation results show a static performance of ±0.56 LSB INL and ±0.79 LSB DNL with a total layout chip area of 0.683 mm2.The segmented architecture is implemented using two sub DAC's, which are the LSB and MSB section with certain number bits. The DAC is designed using 4-BitBinary Weighted DAC for the LSB section and 6-BitThermometer-coded DAC for the MSB section. The thermometer-coded architecture provides the most optimized results in terms of linearity through reducing the clock feed-through effect especially in hot switching between multiple transistors. The binary- weighted architecture gives better linearity output in higher frequencies with better saturation in current sources.

  4. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    NASA Astrophysics Data System (ADS)

    Rivetti, A.; Battaglia, M.; Bisello, D.; Caselle, M.; Chalmet, P.; Costa, M.; Demaria, N.; Giubilato, P.; Ikemoto, Y.; Kloukinas, K.; Mansuy, C.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rousset, J.; Silvestrin, L.; Wyss, J.

    2013-12-01

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 Ω cm, which is at least one order of magnitude greater than the typical value (1 - 10 Ω cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported.

  5. A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

    NASA Astrophysics Data System (ADS)

    Wenwei, He; Qiao, Meng; Yi, Zhang; Kai, Tang

    2014-08-01

    A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is presented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold amplifier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a differential nonlinearity < ±0.3 LSB and an integral nonlinearity < ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm2 with the pad. It consumes 210 mW from a 1.2 V single supply.

  6. Achieving CDU requirement for 90-nm technology node and beyond with advanced mask making process technology

    NASA Astrophysics Data System (ADS)

    Tzu, San-De; Chang, Chung-Hsing; Chen, Wen-Chi; Kliem, Karl-Heinz; Hudek, Peter; Beyer, Dirk

    2005-01-01

    For 90nm node and beyond technology generations, one of the most critical challenges is how to meet the local CD uniformity (proximity) and global CD uniformity (GCDU) requirements within the exposure field. Both of them must be well controlled in the mask making process: (1) proximity effect and, (2) exposure pattern loading effect, or the so-called e-beam "fogging effect". In this paper, we report a method to improve our global CDU by means of a long range fogging compensation together with the Leica SB350 MW. This exposure tool is operated at 50keV and 1nm design grid. The proximity correction is done by the software - package "PROXECCO" from PDF Solutions. We have developed a unique correction method to reduce the fogging effect in dependency of the pattern density of the mask. This allows us to meet our customers" CDU specifications for the 90nm node and beyond.

  7. Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan A.; LaBel, Kenneth A.

    2010-01-01

    The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

  8. Non-chemical cleaning technology for sub-90nm design node photomask manufacturing

    NASA Astrophysics Data System (ADS)

    Hoyeh, Star; Chen, Richard; Kozuma, Makoto; Kuo, Joann; Huang, Torey; Chen, Frank F.

    2006-10-01

    Cleaning chemistry residue in photomask manufacturing is one of root causes to generate HAZE over surface of photomask for 193nm and shorter wavelength exposure tools. In order to reduce the residue, chemical free process is one of targets in photomask industry. In this paper novel clean technology without sulfuric acid and ammonia chemical are shown to manufacture sub-90nm node photomask. Photo and E-beam resist were removed by plasma and ozone water clean instead of sulfuric acid. SPM and APM in final clean sequence before defect inspection were substituted with ozone water and hydrogen water respectively. The clean performance was demonstrated in real production of 193nm phase shift mask. Sulfate and Ammonia residue after final clean were controlled same as blank material level without any clean process.

  9. In-line 90 nm Technology Gate Oxide Nitrogen Monitoring With Non-Contact Electrical Technique

    NASA Astrophysics Data System (ADS)

    Pic, Nicolas; Polisski, Gennadi; Paire, Emmanuel; Rizzo, Véronique; Grosjean, Catherine; Bortolotti, Benjamin; D'Amico, John; Cabuil, Nicolas

    2009-09-01

    The continuous race to reduce the dimensions of IC components has lead to the introduction of Nitrogen in the thin gate oxide layer in order to increase the dielectric constant and to improve the gate dielectric properties. It is mandatory to apply in-line monitoring to control the amount of Nitrogen to ensure that electrical behavior is correct over time. Historically, this monitoring was performed by measuring the delay to reoxidation (D2R) with an ellipsometer. But, this method is not suitable in production as it is depending on both initial oxidation and reoxidation reproducibility, which implies implementing dedicated Statistical Process Control (SPC) monitoring at these two specific processing steps. We are here presenting an alternative method to D2R for 90 nm Technology gate oxide grown by Rapid Thermal Process (RTP). Applying a non-contact Metrology technique, which couples Kelvin probe surface voltage measurement with surface Corona deposition, directly after the nitridation step, the interface trapped charge (QIT) is obtained by integration of the interface state density over the space charge region. In summary, this electrical non-contact monitoring is more sensitive to the Nitrogen content compared to ellipsometer measurement after nitridation or after D2R, less sensitive compared to D2R to any initial oxide variation, and it allows simplification of the qualification procedure at this process step by skipping the reoxidation.

  10. CMOS Detector Technology

    NASA Astrophysics Data System (ADS)

    Hoffman, Alan; Loose, Markus; Suntharalingam, Vyshnavi

    2005-01-01

    An entry level overview of state-of-the-art CMOS detector technology is presented. Operating principles and system architecture are explained in comparison to the well-established CCD technology, followed by a discussion of important benefits of modern CMOS-based detector arrays. A number of unique CMOS features including different shutter modes and scanning concepts are described. In addition, sub-field stitching is presented as a technique for producing very large imagers. After a brief introduction to the concept of monolithic CMOS sensors, hybrid detectors technology is introduced. A comparison of noise reduction methods for CMOS hybrids is presented. The final sections review CMOS fabrication processes for monolithic and vertically integrated image sensors.

  11. Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90 nm CMOS process.

    PubMed

    Chen, Tung-Chien; Ma, Tsung-Chuan; Chen, Yun-Yu; Chen, Liang-Gee

    2012-01-01

    Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However for the long duration experiments on free-moving subjects, the miniaturized and wireless neural recording ICs are the current trend, and the compromise on sorting accuracy is usually made by a lower SR for the lower power consumption. In this paper, we implement an on-chip spike sorting processor with integrated interpolation hardware in order to improve the performance in terms of power versus accuracy. According to the fabrication results in 90nm process, if the interpolation is appropriately performed during the spike sorting, the system operated at the SR of 12.5 k samples per second (sps) can outperform the one not having interpolation at 25 ksps on both accuracy and power.

  12. Specifications and methodologies for benchmarking of advanced CD-SEMs at the 90-nm CMOS technology node and beyond

    NASA Astrophysics Data System (ADS)

    Bunday, Benjamin D.; Bishop, Michael

    2003-05-01

    In this work, an extremely flexible and simple dissolution rate monitor (DRM) based on inexpensive, commercially available, PC card spectrometers has been built that can be used quite robustly in both fab and laboratory environments for measuring the dissolution behavior of photoreist films. The hardware required in order to construct such a simple apparatus has been discussed along with various experimental configurations that are appropriate for different measurement tasks. A multiwavelength interferometric data analysis software (MIDAS) has been developed in this work that can robustly perform both single wavelength and multiwavelength DRM data analysis. The multiwavelength DRM and MIDAS software have been found to be very useful in analyzing a variety of resist film dissolution phenomena including monitoring films possessing dissolution rates exceeding 100 nm/s and studying resist film surface inhibition/acceleration. Another useful application has been to measure swelling in the processing of photoresists and other polymer thin films. The basic approaches and algorithms used for thin film thickness and dissolution rate determination in the MIDAS software are discussed in this paper. Results from the use of the MIDAS software in various applications are presented.

  13. Future of nano CMOS technology

    NASA Astrophysics Data System (ADS)

    Iwai, Hiroshi

    2015-10-01

    Although Si MOS devices have dominated the integrated circuit applications over the four decades, it has been anticipated that the development of CMOS would reach its limits after the next decade because of the difficulties in the technologies for further downscaling and also because of some fundamental limits of MOSFETs. However, there have been no promising candidates yet, which can replace Si MOSFETs with better performance with low cost. Thus, for the moment, it seems that we have to stick to the Si MOSFET devices until their end. The downsizing is limited by the increase of off-leakage current between source and drain. In order to suppress the off-leakage current, multi-gate structures (FinFET, Tri-gate, and Si-nanowire MOSFETs) are replacing conventional planar MOSFETs, and continuous innovation of high-k/metal gate technologies has enabled EOT scaling down to 0.9 nm in production. However, it was found that the multi-gate structures have a future big problem of significant conduction reduction with decrease in fin width. Also it is not easy to further decrease EOT because of the mobility and reliability degradation. Furthermore, the development of EUV (Extremely Ultra-Violet) lithography, which is supposed to be essential for sub-10 nm lithography, delays significantly because of insufficient illumination intensity for production. Thus, it is now expected that the reduction rate of the gate length, which has a strong influence on the off-leakage current, will become slower in near future.

  14. Challenges of nickel silicidation in CMOS technologies

    SciTech Connect

    Breil, Nicolas; Lavoie, Christian; Ozcan, Ahmet; Baumann, Frieder; Klymko, Nancy; Nummy, Karen; Sun, Bing; Jordan-Sweet, Jean; Yu, Jian; Zhu, Frank; Narasimha, Shreesh; Chudzik, Michael

    2015-04-01

    In our paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g.SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of the nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. Furthermore, we investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (1 0 0) and (1 1 1) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni–Pt–Si–Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.

  15. The 1.2 micron CMOS technology

    NASA Technical Reports Server (NTRS)

    Pina, C. A.

    1985-01-01

    A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.

  16. CMOS digital pixel sensors: technology and applications

    NASA Astrophysics Data System (ADS)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  17. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  18. CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

    NASA Technical Reports Server (NTRS)

    Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

    2006-01-01

    This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

  19. Advancement of CMOS Doping Technology in an External Development Framework

    NASA Astrophysics Data System (ADS)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  20. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    NASA Astrophysics Data System (ADS)

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  1. Integrated imaging sensor systems with CMOS active pixel sensor technology

    NASA Technical Reports Server (NTRS)

    Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

    2002-01-01

    This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

  2. Log polar image sensor in CMOS technology

    NASA Astrophysics Data System (ADS)

    Scheffer, Danny; Dierickx, Bart; Pardo, Fernando; Vlummens, Jan; Meynants, Guy; Hermans, Lou

    1996-08-01

    We report on the design, design issues, fabrication and performance of a log-polar CMOS image sensor. The sensor is developed for the use in a videophone system for deaf and hearing impaired people, who are not capable of communicating through a 'normal' telephone. The system allows 15 detailed images per second to be transmitted over existing telephone lines. This framerate is sufficient for conversations by means of sign language or lip reading. The pixel array of the sensor consists of 76 concentric circles with (up to) 128 pixels per circle, in total 8013 pixels. The interior pixels have a pitch of 14 micrometers, up to 250 micrometers at the border. The 8013-pixels image is mapped (log-polar transformation) in a X-Y addressable 76 by 128 array.

  3. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; French, M.; Manolopoulos, S.; Tyndel, M.; Allport, P.; Bates, R.; O'Shea, V.; Hall, G.; Raymond, M.

    2003-03-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to tape. Because of the large number of pixels, data reduction is needed on the sensor itself or just outside. This brings in stringent requirements on the temporal noise as well as to the sensor uniformity, expressed as a Fixed Pattern Noise (FPN). A pixel architecture with an additional transistor is proposed. This architecture, coupled to correlated double sampling of the signal will allow cancellation of the two dominant noise sources, namely the reset or kTC noise and the FPN. A prototype has been designed in a standard 0.25 μm CMOS technology. It has also a structure for electrical calibration of the sensor. The prototype is functional and detailed tests are under way.

  4. Optimization of precision localization microscopy using CMOS camera technology

    NASA Astrophysics Data System (ADS)

    Fullerton, Stephanie; Bennett, Keith; Toda, Eiji; Takahashi, Teruo

    2012-02-01

    Light microscopy imaging is being transformed by the application of computational methods that permit the detection of spatial features below the optical diffraction limit. Successful localization microscopy (STORM, dSTORM, PALM, PhILM, etc.) relies on the precise position detection of fluorescence emitted by single molecules using highly sensitive cameras with rapid acquisition speeds. Electron multiplying CCD (EM-CCD) cameras are the current standard detector for these applications. Here, we challenge the notion that EM-CCD cameras are the best choice for precision localization microscopy and demonstrate, through simulated and experimental data, that certain CMOS detector technology achieves better localization precision of single molecule fluorophores. It is well-established that localization precision is limited by system noise. Our findings show that the two overlooked noise sources relevant for precision localization microscopy are the shot noise of the background light in the sample and the excess noise from electron multiplication in EM-CCD cameras. At low light conditions (< 200 photons/fluorophore) with no optical background, EM-CCD cameras are the preferred detector. However, in practical applications, optical background noise is significant, creating conditions where CMOS performs better than EM-CCD. Furthermore, the excess noise of EM-CCD is equivalent to reducing the information content of each photon detected which, in localization microscopy, reduces the precision of the localization. Thus, new CMOS technology with 100fps, <1.3 e- read noise and high QE is the best detector choice for super resolution precision localization microscopy.

  5. Scaled CMOS Technology Reliability Users Guide

    NASA Technical Reports Server (NTRS)

    White, Mark

    2010-01-01

    The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is

  6. Design and optimization of BCCD in CMOS technology

    NASA Astrophysics Data System (ADS)

    Gao, Jing; Li, Yi; Gao, Zhi-yuan; Luo, Tao

    2016-09-01

    This paper optimizes the buried channel charge-coupled device (BCCD) structure fabricated by complementary metal oxide semiconductor (CMOS) technology. The optimized BCCD has advantages of low noise, high integration and high image quality. The charge transfer process shows that interface traps, weak fringing fields and potential well between adjacent gates all cause the decrease of charge transfer efficiency ( CTE). CTE and well capacity are simulated with different operating voltages and gap sizes. CTE can achieve 99.999% and the well capacity reaches up to 25 000 electrons for the gap size of 130 nm and the maximum operating voltage of 3 V.

  7. CMOS-TDI detector technology for reconnaissance application

    NASA Astrophysics Data System (ADS)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  8. Single donor electronics and quantum functionalities with advanced CMOS technology

    NASA Astrophysics Data System (ADS)

    Jehl, Xavier; Niquet, Yann-Michel; Sanquer, Marc

    2016-03-01

    Recent progresses in quantum dots technology allow fundamental studies of single donors in various semiconductor nanostructures. For the prospect of applications figures of merits such as scalability, tunability, and operation at relatively large temperature are of prime importance. Beyond the case of actual dopant atoms in a host crystal, similar arguments hold for small enough quantum dots which behave as artificial atoms, for instance for single spin control and manipulation. In this context, this experimental review focuses on the silicon-on-insulator devices produced within microelectronics facilities with only very minor modifications to the current industrial CMOS process and tools. This is required for scalability and enabled by shallow trench or mesa isolation. It also paves the way for real integration with conventional circuits, as illustrated by a nanoscale device coupled to a CMOS circuit producing a radio-frequency drive on-chip. At the device level we emphasize the central role of electrostatics in etched silicon nanowire transistors, which allows to understand the characteristics in the full range from zero to room temperature.

  9. High gain CMOS image sensor design and fabrication on SOI and bulk technology

    NASA Astrophysics Data System (ADS)

    Zhang, Weiquan

    2000-12-01

    The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force in industry. Silicon on insulator (SOI) is considered as the coming mainstream technology. It challenges the current bulk CMOS technology because of its reduced power consumption, high speed, radiation hardness etc. Moving the CMOS imager from the bulk to the SOI substrate will benefit from these intrinsic advantages. In addition, the blooming and the cross-talk between the pixels of the sensor array can be ideally eliminated, unlike those on the bulk technology. Though there are many advantages to integrate CMOS imager on SOI, the problem is that the top silicon film is very thin, such as 2000Å. Many photons can just pass through this layer without being absorbed. A good photo-detector on SOI is critical to integrate SOI CMOS imagers. In this thesis, several methods to make photo-detectors on SOI substrate are investigated. A floating gate MOSFET on SOI substrate, operating in its lateral bipolar mode, is photon sensitive. One step further, the SOI MOSFET gate and body can be tied together. The positive feedback between the body and gate enables this device have a high responsivity. A similar device can be found on the bulk CMOS technology: the gate-well tied PMOSFET. A 32 x 32 CMOS imager is designed and characterized using such a device as the light-sensing element. I also proposed the idea of building hybrid active pixels on SOI substrate. Such devices are fabricated and characterized. The work here represents my contribution on the CMOS imager, especially moving the CMOS imager onto the SOI substrate.

  10. Failure analysis of a half-micron CMOS IC technology

    SciTech Connect

    Liang, A.Y.; Tangyunyong, P.; Bennett, R.S.; Flores, R.S.

    1996-08-01

    We present the results of recent failure analysis of an advanced, 0.5 {mu}m, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

  11. Design of high speed camera based on CMOS technology

    NASA Astrophysics Data System (ADS)

    Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

    2007-12-01

    The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

  12. Evaluation of IDEALSmile for 90-nm FLASH memory contact holes imaging with ArF scanner

    NASA Astrophysics Data System (ADS)

    Cantu, Pietro; Capetti, Gianfranco; Loi, Sara; Lupo, Marco; Pepe, Annalisa; Saitoh, Kenji; Yamazoe, Kenji; Hasegawa, Yasuo; Iwasa, Junji; Toublan, Olivier R.

    2004-05-01

    According to sizes dictated by ITRS road map, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. The development of 90[nm] technology FLASH memories requires a robust solution for printing contact holes down to 100[nm] on 200[nm] pitch. The delay of NGL development as well as open issues related to 157[nm] scanner introduction pushes the industry to find a solution for printing such tight features using existing ArF scanner. IDEALSmile technology from Canon was proven to be a good candidate for achieving such high resolution with sufficiently large through pitch process window using a binary mask, relatively simple to be manufactured, with a modified illumination and single exposure, with no impact on throughput and without any increase of cost of ownership. This paper analyses main issues related to the introduction of this new resolution enhancement technology on a real FLASH memory device, highlighting advantages as well as known problems still under investigation.

  13. Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

    SciTech Connect

    Smith, J.H.; Ellis, J.R.; Montague, S.; Allen, J.J.

    1997-03-01

    One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.

  14. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    NASA Astrophysics Data System (ADS)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

    2016-09-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  15. Design and characterization of avalanche photodiodes in submicron CMOS technologies

    NASA Astrophysics Data System (ADS)

    Pancheri, L.; Bendib, T.; Dalla Betta, G.-F.; Stoppa, D.

    2014-03-01

    The fabrication of Avalanche Photodiodes (APDs) in CMOS processes can be exploited in several application domains, including telecommunications, time-resolved optical detection and scintillation detection. CMOS integration allows the realization of systems with a high degree of parallelization which are competitive with hybrid solutions in terms of cost and complexity. In this work, we present a linear-mode APD fabricated in a 0.15μm process, and report its gain and noise characterization. The experimental observations can be accurately predicted using Hayat dead-space noise model. Device simulations based on dead-space model are then used to discuss the current status and the perspectives for the integration of high-performance low-noise devices in standard CMOS processes.

  16. III-V/Ge channel MOS device technologies in nano CMOS era

    NASA Astrophysics Data System (ADS)

    Takagi, Shinichi; Zhang, Rui; Suh, Junkyo; Kim, Sang-Hyeon; Yokoyama, Masafumi; Nishi, Koichi; Takenaka, Mitsuru

    2015-06-01

    CMOS utilizing high-mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing III-V/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/III-V films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in III-V/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the III-V MOS device technologies, we mainly address the gate stack technology, III-V channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel III-V-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using III-V/Ge channels.

  17. Asymmetric MQW semiconductor optical amplifier with low-polarization sensitivity of over 90-nm bandwidth

    NASA Astrophysics Data System (ADS)

    Nkanta, Julie E.; Maldonado-Basilio, Ramón; Abdul-Majid, Sawsan; Zhang, Jessica; Hall, Trevor J.

    2013-12-01

    An exhausted capacity of current Passive Optical Networks has been anticipated as bandwidth-hungry applications such as HDTV and 3D video become available to end-users. To enhance their performance, the next generation optical access networks have been proposed, using optical carriers allocated within the E-band (1360-1460 nm). It is partly motivated by the low-water peak fiber being manufactured by Corning. At these wavelengths, choices for low cost optical amplifiers, with compact size, low energy consumption and feasibility for integration with other optoelectronic components are limited, making the semiconductor optical amplifiers (SOA) a realistic solution. An experimental characterization of a broadband and low polarization sensitive asymmetric multi quantum well (MQW) SOA operating in the E-band is reported. The SOA device is composed of nine 6 nm In1-xGaxAsyP1-y 0.2% tensile strained asymmetric MQW layers sandwiched between nine latticed matched 6 nm InGaAsP barrier layers. The active region is grown on an n-doped InP substrate and buried by p-doped InGaAsP layers. The SOA devices have 7-degrees tilt anti-reflected coated facets, with 2 μm ridge width, and a cavity length of 900 μm. For input powers of -10 dBm and -20 dBm, a maximum gain of 20 dB at 1360 nm with a polarization insensitivity under 3 dB for over 90 nm bandwidth is measured. Polarization sensitivity of less than 0.5 dB is observed for some wavelengths. Obtained results indicate a promising SOA with broadband amplification, polarization insensitivity and high gain. These SOAs were designed and characterized at the Photonics Technology Laboratory, University of Ottawa, Canada.

  18. CMOS technology: a critical enabler for free-form electronics-based killer applications

    NASA Astrophysics Data System (ADS)

    Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

    2016-05-01

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

  19. Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks

    NASA Technical Reports Server (NTRS)

    Dogan, Numan S.

    2003-01-01

    The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

  20. DOE experiment for scattering bars optimization at the 90nm node

    NASA Astrophysics Data System (ADS)

    Bouton, G.; Connolly, B.; Courboin, D.; Di Giacomo, A.; Gasnier, F.; Lallement, R.; Parker, D.; Pindo, M.; Richoilley, J. C.; Royere, F.; Rameau-Savio, A.; Tissier, M.

    2011-03-01

    Scattering bars (SB) are sub-resolution lines added to the original database during Resolution Enhancement Techniques (RET) treatments. Their goal is stabilizing the CD of the adjacent polygons (by suppressing or reducing secondary diffraction waves). SB increase the process window in the litho process by lowering the first derivative of the CD. Moreover, the detailed knowledge of SB behavior around the fab working point is a must for future shrinks and for preparing the next technology nodes. SB are inserted in the generation of critical levels for STMicroelectronics 90 nm technology embedded memories before invoking the Model for Optical Proximity Corrections (MBOPC). This allows the software to calculate their contribution to the intensity in the aerial image and integrate their effects in Edge Proximity Error (EPE) corrections. However the Rule-Based insertion of these assist features still leaves behind occurrences of conflicting priorities as in the image below. (See manuscript PDF)Detection of Hot Spots in 2D simulations for die treatment validation (done on BRION equipment on each critical level before mask making) is in most cases correlated with SB singularities, at least for CD non-uniformity, bridging issues and necking in correspondence with OPC fragmentation effects. Within the framework of the MaXSSIMM project, we established a joint STMicroelectronics and Toppan Photomasks team to explore the influence of assist features (CD, distance), convex and concave corner rounding and CD uniformity by means of specific test patterns. The proposed study concerns the algorithms used to define the mask shop input as well as the physical mask etching. A set of test cases, based on elementary test patterns, each one including a list of geometrical variations, has been defined. As the number of configurations becomes rapidly very large (tens of thousands) we had to apply Design of Experiments (DOE) algorithms in order to reduce the number of measurements to a

  1. Optimization of building blocks for multi-stage 17-44 dB 6.1-9.6 mW 90-nm K-band front-ends

    NASA Astrophysics Data System (ADS)

    Roy, Apratim; Harun Rashid, A.

    2013-12-01

    In this article, five two-stage ˜6-mW and four three-stage ˜9-mW matched amplifier architectures are proposed to establish optimization procedure and quantify relative merits of cascode (CC), common-gate (CG), and commonsource (CS) building blocks for low-voltage low-power multi-stage front-ends. The circuits are simulated with a 90-nm CMOS technology including modeling of layout parasites. Integrated bias trees and passive port matching networks are incorporated in the K-band designs. In the face of process mismatch, variability in noise and gain figures remains <0.39 dB and <7.1 dB from the design values. The five combinations of building blocks in twostage low-power (6.1-6.6 mW) amplifiers achieve linearity (IIP3) in the range of -5.2˜-13.5 dBm, good reverse isolation (better than -26 dB), 2.89-3.82 dB noise penalties, and 17.2-25.5 dB peak forward gain. In case of threestage front-ends built with CS, CC, and CG blocks (power rating 9.2-9.6 mW), forward gain and optimized noise figures are found as >33 dB and <3.26 dB, respectively. They achieve -2.5˜18.3 dBm IIP3, <-39 dB reverse isolation, and <-17 dB minimum IRL. The results are compared with reported simulated findings on CMOS multistage amplifiers to highlight their relative advantages in terms of power requirement and decibel(gain)-per-watt.

  2. Advanced Simulation Technology to Design Etching Process on CMOS Devices

    NASA Astrophysics Data System (ADS)

    Kuboi, Nobuyuki

    2015-09-01

    Prediction and control of plasma-induced damage is needed to mass-produce high performance CMOS devices. In particular, side-wall (SW) etching with low damage is a key process for the next generation of MOSFETs and FinFETs. To predict and control the damage, we have developed a SiN etching simulation technique for CHxFy/Ar/O2 plasma processes using a three-dimensional (3D) voxel model. This model includes new concepts for the gas transportation in the pattern, detailed surface reactions on the SiN reactive layer divided into several thin slabs and C-F polymer layer dependent on the H/N ratio, and use of ``smart voxels''. We successfully predicted the etching properties such as the etch rate, polymer layer thickness, and selectivity for Si, SiO2, and SiN films along with process variations and demonstrated the 3D damage distribution time-dependently during SW etching on MOSFETs and FinFETs. We confirmed that a large amount of Si damage was caused in the source/drain region with the passage of time in spite of the existing SiO2 layer of 15 nm in the over etch step and the Si fin having been directly damaged by a large amount of high energy H during the removal step of the parasitic fin spacer leading to Si fin damage to a depth of 14 to 18 nm. By analyzing the results of these simulations and our previous simulations, we found that it is important to carefully control the dose of high energy H, incident energy of H, polymer layer thickness, and over-etch time considering the effects of the pattern structure, chamber-wall condition, and wafer open area ratio. In collaboration with Masanaga Fukasawa and Tetsuya Tatsumi, Sony Corporation. We thank Mr. T. Shigetoshi and Mr. T. Kinoshita of Sony Corporation for their assistance with the experiments.

  3. Advanced simulation technology for etching process design for CMOS device applications

    NASA Astrophysics Data System (ADS)

    Kuboi, Nobuyuki; Fukasawa, Masanaga; Tatsumi, Tetsuya

    2016-07-01

    Plasma etching is a critical process for the realization of high performance in the next generation of CMOS devices. To predict and control fluctuations in the etching properties accurately during mass production, it is essential that etching process simulation technology considers fluctuations in the plasma chamber wall conditions, the effects of by-products on the critical dimensions, the Si recess dependence on the wafer open area ratio and local pattern structure, and the time-dependent plasma-induced damage distribution associated with the three-dimensional feature scale profile at the 100 nm level. This consideration can overcome the issues with conventional simulations performed under the assumed ideal conditions, which are not accurate enough for practical process design. In this article, these advanced process simulation technologies are reviewed, and, from the results of suitable process simulations, a new etching system that automatically controls the etching properties is proposed to enable stable CMOS device fabrication with high yields.

  4. Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

    NASA Astrophysics Data System (ADS)

    Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

    2010-10-01

    Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

  5. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    NASA Astrophysics Data System (ADS)

    Yin, Lan; Bozler, Carl; Harburg, Daniel V.; Omenetto, Fiorenzo; Rogers, John A.

    2015-01-01

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  6. ArF processing of 90-nm design rule lithography achieved through enhanced thermal processing

    NASA Astrophysics Data System (ADS)

    Kagerer, Markus; Miller, Daniel; Chang, Wayne; Williams, Daniel J.

    2006-03-01

    As the lithography community has moved to ArF processing on 300 mm wafers for 90 nm design rules the process characterization of the components of variance continues to highlight the thermal requirements for the post exposure bake (PEB) processing step. In particular as the thermal systems have become increasingly uniform, the transient behavior of the thermal processing system has received the focus of attention. This paper demonstrates how a newly designed and patented thermal processing system was optimized for delivering improved thermal uniformity during a typical 90 second PEB processing cycle, rather than being optimized for steady state performance. This was accomplished with the aid of a wireless temperature measurement wafer system for obtaining real time temperature data and by using a response surface model (RSM) experimental design for optimizing parameters of the temperature controller of the thermal processing system. The new units were field retrofitted seamlessly in <2 days at customer sites without disruption to process recipes or flows. After evaluating certain resist parameters such as PEB temperature sensitivity and post exposure delay (PED) - stability of the baseline process, the new units were benchmarked against the previous PEB plates by processing a split lot experiment. Additional hardware characterization included environmental factors such as air velocity in the vicinity of the PEB plates and transient time between PEB and chill plate. At the completion of the optimization process, the within wafer CD uniformity displayed a significant improvement when compared to the previous hardware. The demonstrated within wafer CD uniformity improved by 27% compared to the initial hardware and baseline process. ITRS requirements for the 90 nm node were exceeded.

  7. 324GHz CMOS VCO Using Linear Superimposition Technique

    NASA Technical Reports Server (NTRS)

    Daquan, Huang; LaRocca, Tim R.; Samoska, Lorene A; Fung, Andy; Chang, Frank

    2007-01-01

    Terahertz (frequencies ranged from 300GHz to 3THz) imaging and spectroscopic systems have drawn increasing attention recently due to their unique capabilities in detecting and possibly analyzing concealed objects. The generation of terahertz signals is nonetheless nontrivial and traditionally accomplished by using either free-electron radiation, optical lasers, Gunn diodes or fundamental oscillation by using III-V based HBT/HEMT technology[1-3]... We have substantially extended the operation range of deep-scaled CMOS by using a linear superimposition method, in which we have realized a 324GHz VCO in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage. This may also pave the way for ultra-high data rate wireless communications beyond that of IEEE 802.15.3c and reach data rates comparable to that of fiber optical communications, such as OC768 (40Gbps) and beyond.

  8. CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications.

    PubMed

    Hussain, Aftab M; Hussain, Muhammad M

    2016-06-01

    Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. PMID:26607553

  9. Integrated pressure-sensing microsystem by CMOS IC technology for barometal applications

    NASA Astrophysics Data System (ADS)

    Zhou, Minxin; Huang, Qing-An

    2001-10-01

    Most currently integrated silicon microsystems available for pressure sensing are based on preprocessing before CMOS IC technology. These microsystems are generally very sensitive to parasitism effect and not available for IC-compatible process. This limits the accuracy of the microsystem and batch-fabrication. Calibration cost is also increased. To overcome these problems, a new generation of pressure microsystems without preprocessing CMOS IC technology has been proposed. This pressure-sensing system consists of a miniature silicon capacitive sensor, fabricated with silicon-silicon bonding technique, and a detection integrated circuit. Only the standard layers of CMOS process are used to build the system and only several photolithography steps are necessary to achieve the micromachined structure in postprocessing, so a high long-term stability could be assured. The entire system converts absolute pressure changes, in the pressure range useful for barometal applications, to frequency changes. A reference capacitor is used in the system and a (delta) C model is applied to cancel out temperature dependence and to compensate non-linearity. The pressure range of the sensor is from 0.5 bar to 1.5bar and the temperature varies between -25 degree(s)C and -60 degree(s)C. A sensitivity of 50Hz/Torr could be achieved.

  10. CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications.

    PubMed

    Hussain, Aftab M; Hussain, Muhammad M

    2016-06-01

    Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered.

  11. Transport and noise in 90nm n-GaAs Epilayers

    NASA Astrophysics Data System (ADS)

    Gilbertson, A.; Moore, J. D.; Perkins, G.; Gallop, J.; Cohen, L. F.; Newaz, A. K. M.; Solin, S. A.

    2009-03-01

    Extraordinary Magnetoresistance (EMR) belongs to the family of EXX effects which form the basis for a number of devices that offer the potential for high sensitivity applications. Such devices would benefit from minimising the active volume of the sensor. To reduce that volume and minimize wafer fabrication complexity it is desirable to employ unltra-thin GaAs epilayers. Accordingly, we report here the transport and noise properties of 90nm Si-doped GaAs films grown by molecular beam epitaxy which have been fabricated into both microscopic EMR devices and macroscopic van der Pauw geometries. These films exhibit a room temperature electron mobility and density of 3225 cm^2V-1s-1 and1.45x10^17cm-3, respectively, and show only a 6% variation over the temperature range 2K

  12. Deep submicron CMOS technologies for the LHC experiments

    NASA Astrophysics Data System (ADS)

    Jarron, P.; Anelli, G.; Calin, T.; Cosculluela, J.; Campbell, M.; Delmastro, M.; Faccio, F.; Giraldo, A.; Heijne, E.; Kloukinas, K.; Letheren, M.; Nicolaidis, M.; Moreira, P.; Paccagnella, A.; Marchioro, A.; Snoeys, W.; Velazco, R.

    1999-08-01

    The harsh radiation environment at the Large Hadron Collider (LHC) requires radiation hard ASICs. This paper presents how a high tolerance for total ionizing dose can be obtained in commercial deep submicron technologies by using enclosed NMOS devices and guard rings. The method is explained, demonstrated on transistor and circuit level, and design implications are discussed. A model for the effective W/L of an enclosed transistor is given, a radiation-tolerant standard cell library is presented, and single event effects are discussed.

  13. A low-power asynchronous ECG acquisition system in CMOS technology.

    PubMed

    Hwang, Sungkil; Trakimas, Michael; Sonkusale, Sameer

    2010-01-01

    An asynchronous electrocardiogram (ECG) acquisition system is presented for wearable ambulatory monitoring. The proposed system consists of a low noise front-end amplifier (AFE) with tunable bandwidth, an asynchronous analog-to-digital converter (ADC), and digital signal processing (DSP). Data compression is achieved by the inherent signal dependent sampling rate of the asynchronous architecture. This makes the system attractive for compact wearable ECG monitoring applications. The AFE and ADC were fabricated in a 0.18 microm CMOS technology and consume a total of 79 microW. Measured results demonstrating ECG monitoring are presented. PMID:21096052

  14. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    NASA Astrophysics Data System (ADS)

    Fiorini, M.; Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2014-12-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×1012 1 MeV neq /cm2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 1014 cm-2 and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  15. Proton-counting radiography for proton therapy: a proof of principle using CMOS APS technology.

    PubMed

    Poludniowski, G; Allinson, N M; Anaxagoras, T; Esposito, M; Green, S; Manolopoulos, S; Nieto-Camero, J; Parker, D J; Price, T; Evans, P M

    2014-06-01

    Despite the early recognition of the potential of proton imaging to assist proton therapy (Cormack 1963 J. Appl. Phys. 34 2722), the modality is still removed from clinical practice, with various approaches in development. For proton-counting radiography applications such as computed tomography (CT), the water-equivalent-path-length that each proton has travelled through an imaged object must be inferred. Typically, scintillator-based technology has been used in various energy/range telescope designs. Here we propose a very different alternative of using radiation-hard CMOS active pixel sensor technology. The ability of such a sensor to resolve the passage of individual protons in a therapy beam has not been previously shown. Here, such capability is demonstrated using a 36 MeV cyclotron beam (University of Birmingham Cyclotron, Birmingham, UK) and a 200 MeV clinical radiotherapy beam (iThemba LABS, Cape Town, SA). The feasibility of tracking individual protons through multiple CMOS layers is also demonstrated using a two-layer stack of sensors. The chief advantages of this solution are the spatial discrimination of events intrinsic to pixelated sensors, combined with the potential provision of information on both the range and residual energy of a proton. The challenges in developing a practical system are discussed.

  16. Depleted Monolithic Active Pixel Sensors (DMAPS) implemented in LF-150 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Kishishita, T.; Hemperek, T.; Krüger, H.; Wermes, N.

    2015-03-01

    We present the recent development of Depleted Monolithic Active Pixel Sensors (DMAPS), implemented with an LFoundry (LF) 150 nm CMOS process. MAPS detectors based on an epi-layer have been matured in recent years and have attractive features in terms of reducing material budget and handling cost compared to conventional hybrid pixel detectors. However, the obtained signal is relatively small (~1000 e-) due to the thin epi-layer, and charge collection time is relatively slow, e.g., in the order of 100 ns, because charges are mainly collected by diffusion. Modern commercial CMOS technology, however, offers advanced process options to overcome such difficulties and enable truly monolithic devices as an alternative to hybrid pixel sensors and charge coupled devices. Unlike in the case of the standard MAPS technologies with epi-layers, the LF process provides a high-resistivity substrate that enables large signal and fast charge collection by drift in a ~50 μm thick depleted layer. Since this process also enables the use of deep n- and p-wells to isolate the collection electrode from the thin active device layer, PMOS and NMOS transistors are available for the readout electronics in each pixel cell. In order to evaluate the sensor and transistor characteristics, several collection electrodes variants and readout architectures have been implemented. In this report, we focus on its design aspect of the LF-DMAPS prototype chip.

  17. Proton-counting radiography for proton therapy: a proof of principle using CMOS APS technology

    PubMed Central

    Poludniowski, G; Allinson, N M; Anaxagoras, T; Esposito, M; Green, S; Manolopoulos, S; Nieto-Camero, J; Parker, D J; Price, T; Evans, P M

    2014-01-01

    Despite the early recognition of the potential of proton imaging to assist proton therapy the modality is still removed from clinical practice, with various approaches in development. For proton-counting radiography applications such as Computed Tomography (CT), the Water-Equivalent-Path-Length (WEPL) that each proton has travelled through an imaged object must be inferred. Typically, scintillator-based technology has been used in various energy/range telescope designs. Here we propose a very different alternative of using radiation-hard CMOS Active Pixel Sensor (APS) technology. The ability of such a sensor to resolve the passage of individual protons in a therapy beam has not been previously shown. Here, such capability is demonstrated using a 36 MeV cyclotron beam (University of Birmingham Cyclotron, Birmingham, UK) and a 200 MeV clinical radiotherapy beam (iThemba LABS, Cape Town, SA). The feasibility of tracking individual protons through multiple CMOS layers is also demonstrated using a two-layer stack of sensors. The chief advantages of this solution are the spatial discrimination of events intrinsic to pixelated sensors, combined with the potential provision of information on both the range and residual energy of a proton. The challenges in developing a practical system are discussed. PMID:24785680

  18. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    PubMed Central

    Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

  19. Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

    PubMed

    Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

    2011-01-01

    The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

  20. High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches

    NASA Astrophysics Data System (ADS)

    Heinemann, B.; Barth, R.; Knoll, D.; Rücker, H.; Tillack, B.; Winkler, W.

    2007-01-01

    A 0.25 µm SiGe:C BiCMOS technology family (SG25H) with high-speed npn and pnp transistors for different performance requirements is presented. A CMOS-friendly integration scheme is realized by using collector wells, implanted after shallow trench formation, and avoiding deep trenches and extra collector sinkers. Three process variants are offered. The key bipolar transistor of the SG25H1 process is a 200 GHz npn device. The SG25H3 process offers three different types of npn HBTs. The performance ranges from fT/fmax /BVCEo values of 110 GHz/180 GHz/2.3 V for the high-speed (HS) device to 50 GHz/140 GHz/4.5 V for the medium voltage (MV) device and 30 GHz/80 GHz/6.5 V for the high-voltage (HV) transistor. The SG25H2 process provides in addition to npn transistors similar to those of SG25H1 and H3 a very high-speed SiGe:C pnp HBT with fT/fmax/BVCEo values of 90 GHz/120 GHz/2.8 V.

  1. Radiation tolerance study of a commercial 65 nm CMOS technology for high energy physics applications

    NASA Astrophysics Data System (ADS)

    Ding, Lili; Gerardin, Simone; Bagatin, Marta; Bisello, Dario; Mattiazzo, Serena; Paccagnella, Alessandro

    2016-09-01

    This paper reports the radiation tolerance study of a commercial 65 nm technology, which is a strong candidate for the Large Hadron Collider applications. After exposure to 3 MeV protons till 1 Grad dose, the 65 nm CMOS transistors, especially the pMOSFETs, showed severe long-term degradation mainly in the saturation drain currents. There were some differences between the degradation levels in the nMOSFETs and the pMOSFETs, which were likely attributed to the positive charges trapped in the gate spacers. After exposure to heavy ions till multiple strikes, the pMOSFETs did not show any sudden loss of drain currents, the degradations in the characteristics were negligible.

  2. Development of scalable frequency and power Phase-Locked Loop in 130 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moroń, J.; Świentek, K.

    2014-02-01

    The design and measurements results of a prototype very low power Phase-Locked Loop (PLL) ASIC for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in 130 nm CMOS technology. It was designed and simulated for frequency range 10 MHz-3.5 GHz. Four division factors i.e. 6, 8, 10 and 16 were implemented in the PLL feedback loop. The main PLL block-voltage controlled oscillator (VCO) should work in 16 frequency ranges/modes, switched either manually or automatically. Preliminary measurements done in frequency range 20 MHz-1.6 GHz showed that the ASIC is functional and generates proper clock signal. The automatic VCO mode switching, one of the main design goals, was positively verified. Power consumption of around 0.6 mW was measured at 1 GHz for a division factor equal to 10.

  3. BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

    NASA Astrophysics Data System (ADS)

    Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

    2016-01-01

    We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

  4. Advanced mask technique to improve bit line CD uniformity of 90 nm node flash memory in low-k1 lithography

    NASA Astrophysics Data System (ADS)

    Kim, Jong-doo; Choi, Jae-young; Kim, Jea-hee; Han, Jae-won

    2008-10-01

    As devices size move toward 90nm technology node or below, defining uniform bit line CD of flash devices is one of the most challenging features to print in KrF lithography. There are two principal difficulties in defining bit line on wafer. One is insufficient process margin besides poor resolution compared with ArF lithography. The other is that asymmetric bit line should be made for OPC(Optical Proximity Correction) modeling. Therefore advanced ArF lithography scanner should be used for define bit line with RETs (Resolution Enhancement Techniques) such as immersion lithography, OPC, PSM(Phase Shift Mask), high NA(Numerical Aperture), OAI(Off-Axis Illumination), SRAF(Sub-resolution Assistant Feature), and mask biasing.. Like this, ArF lithography propose the method of enhancing resolution, however, we must spend an enormous amount of CoC(cost of ownership) to utilize ArF photolithography process than KrF. In this paper, we suggest method to improve of bit line CD uniformity, patterned by KrF lithographic process in 90nm sFlash(stand alone Flash) devices. We applied new scheme of mask manufacturing, which is able to realize 2 different types of mask, binary and phase-shift, into one plate. Finally, we could get the more uniform bit lines and we expect to get more stable properties then before applying this technique.

  5. CLARO-CMOS: a fast, low power and radiation-hard front-end ASIC for single-photon counting in 0.35 micron CMOS technology

    NASA Astrophysics Data System (ADS)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-01-01

    The CLARO-CMOS is a prototype ASIC designed for fast photon counting with multi-anode photomultiplier tubes (MaPMT). The CLARO features a 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. The chip was designed in 0.35 μm CMOS technology, and was tested for radiation hardness with neutrons up to 1014 1 MeV neq/cm2, X-rays up to 40 kGy and protons up to 76 kGy. Its capability to read out single photons at high rate from a Hamamatsu R11265 MaPMT, the baseline photon detector for the LHCb RICH upgrade, was demonstrated both with test bench measurements and with actual signals from a R11265 MaPMT. The presented results allowed CLARO to be chosen as the front-end readout chip in the upgraded LHCb RICH detector.

  6. 1/f noise in deep-submicron CMOS technology for RF and analog applications

    NASA Astrophysics Data System (ADS)

    Mercha, Abdelkarim; Simoen, Eddy; Decoutere, Stefaan; Claeys, Cor

    2004-05-01

    As further enhanced functionalities of mobile equipment are predicted, the development of a CMOS technology that provides low-power, high-speed, and low-noise performance has become an urgent and hot issue. For these application driven technologies the complexity must be tackled at different levels to insure the optimisation of the area, the power consumption, the speed and the reliability. Therefore this paper present a review of the solutions implemented at different levels from system down to technology in order to reduce the contribution of the low frequency noise. These achievements are illustrated by experimental results from literature and are inserted in the general context of system design strategies for reducing the 1/f noise contribution. In a first part dedicated to high-level system and circuit design, we introduce the noise reduction by switching techniques and the methodology for including the noise dispersion in scaled devices for the early design of analogue/RF circuits. In the second part, the 1/f noise is tackled at its origins i.e. the choice of the gate oxide and other critical process steps.

  7. Active pixel sensors in AMS H18/H35 HV-CMOS technology for the ATLAS HL-LHC upgrade

    NASA Astrophysics Data System (ADS)

    Ristic, Branislav

    2016-09-01

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement signal processing electronics in deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150 V leading to a depletion depth of several 10 μm. Prototype sensors in the AMS H18 180 nm and H35 350 nm HV-CMOS processes were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiations with X-rays and protons revealed a tolerance to ionizing doses of 1 Grad while Edge-TCT studies assessed the effects of radiation on the charge collection. The sensors showed high detection efficiencies after neutron irradiation to 1015neq cm-2 in testbeam experiments. A full reticle size demonstrator chip, implemented in the H35 process is being submitted to prove the large scale feasibility of the HV-CMOS concept.

  8. Characterization of Depleted Monolithic Active Pixel detectors implemented with a high-resistive CMOS technology

    NASA Astrophysics Data System (ADS)

    Kishishita, T.; Hemperek, T.; Rymaszewski, P.; Hirono, T.; Krüger, H.; Wermes, N.

    2016-07-01

    We present the recent development of DMAPS (Depleted Monolithic Active Pixel Sensor), implemented with a Toshiba 130 nm CMOS process. Unlike in the case of standard MAPS technologies which are based on an epi-layer, this process provides a high-resistive substrate that enables larger signal and faster charge collection by drift in a 50 - 300 μm thick depleted layer. Since this process also enables the use of deep n-wells to isolate the collection electrodes from the thin active device layer, NMOS and PMOS transistors are available for the readout electronics in each pixel cell. In order to characterize the technology, we implemented a simple three transistor readout with a variety of pixel pitches and input FET sizes. This layout variety gives us a clue on sensor characteristics for future optimization, such as the input detector capacitance or leakage current. In the initial measurement, the radiation spectra were obtained from 55Fe with an energy resolution of 770 eV (FWHM) and 90Sr with the MVP of 4165 e-.

  9. Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

    NASA Astrophysics Data System (ADS)

    Nogami, T.; Lane, S.; Fukasawa, M.; Ida, K.; Angyal, M.; Chanda, K.; Chen, F.; Christiansen, C.; Cohen, S.; Cullinan, M.; Dziobkowski, C.; Fitzsimmons, J.; Flaitz, P.; Grill, A.; Gill, J.; Inoue, K.; Klymko, N.; Kumar, K.; Labelle, C.; Lane, M.; Li, B.; Liniger, E.; Madon, A.; Malone, K.; Martin, J.; McGahay, V.; McLaughlin, P.; Melville, I.; Minami, M.; Molis, S.; Nguyen, S.; Penny, C.; Restaino, D.; Sakamoto, A.; Sankar, M.; Sherwood, M.; Simonyi, E.; Shimooka, Y.; Tai, L.; Widodo, J.; Wildman, H.; Ono, M.; McHerron, D.; Nye, H.; Davis, C.; Sankaran, S.; Edelstein, D.; Ivers, T.

    2005-11-01

    This paper discusses low-k/copper integration schemes which has been in production in the 90 nm node, have been developed in the 65 nm node, and should be taken in the 45 nm node. While our baseline 65 nm BEOL process has been developed by extension and simple shrinkage of our PECVD SiCOH integration which has been in production in the 90 nm node with our SiCOH film having k=3.0, the 65 nm SiCOH integration has two other options to go to extend to lower capacitance. One is to add porosity to become ultra low-k (ULK). The other is to stay with low-k SiCOH, which is modified to have a "lower-k". The effective k- value attained with the lower-k (k=2.8) SiCOH processed in the "Direct CMP" scheme is very close to that with an ULK (k=2.5) SiCOH film built with the "Hard Mask Retention" scheme. This paper first describes consideration of these two damascene schemes, whose comparison leads to the conclusion that the lower-k SiCOH integration can have more advantages in terms of process simplicity and extendibility of our 90 nm scheme under certain assumptions. Then describing the k=2.8 SiCOH film development and its successful integration, damascene schemes for 45nm nodes are discussed based on our learning from development of the lower-k 65nm scheme. Capability of modern dry etchers to define the finer patterns, non-uniformity of CMP, and susceptibility to plasma and mechanical strength and adhesion of ULK are discussed as factors to hamper the applicability of ULK.

  10. Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

    NASA Astrophysics Data System (ADS)

    Singh, Anil; Agarwal, Alpana

    2016-10-01

    A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

  11. High mobility CMOS technologies using III-V/Ge channels on Si platform

    NASA Astrophysics Data System (ADS)

    Takagi, S.; Kim, S.-H.; Yokoyama, M.; Zhang, R.; Taoka, N.; Urabe, Y.; Yasuda, T.; Yamada, H.; Ichikawa, O.; Fukuhara, N.; Hata, M.; Takenaka, M.

    2013-10-01

    MOSFETs using channel materials with high mobility and low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to Ge and III-V channels. In this paper, possible solutions for realizing III-V/Ge MOSFETs on the Si platform are presented. The high quality III-V channel formation on Si substrates can be realized through direct wafer bonding. The gate stack formation is constructed on a basis of atomic layer deposition (ALD) Al2O3 gate insulators for both InGaAs and Ge MOSFETs. As the source/drain (S/D) formation, Ni-based metal S/D is implemented for both InGaAs and Ge MOSFETs. By combining these technologies, we demonstrate successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.

  12. 15158A SP6T RF switch based on IBM SOI CMOS technology

    NASA Astrophysics Data System (ADS)

    Zhiqun, Cheng; Guoguo, Yan; Wayne, Ni; Dandan, Zhu; Hannah, Ni; Jin, Li; Shuai, Chen; Guohua, Liu

    2016-05-01

    This paper presents the design of single-pole six-throw (SP6T) RF switch with IBM 0.18 μm SOI CMOS technology, which can be widely used in a wireless communication system with its high performance and low cost. The circuit is designed and simulated by using an idea that the total load is divided into six branches and SOI special structures. The insertion loss is less than 0.6 dB, isolation is more than 30 dB, the input power P0.1dB for 0.1 dB compression point is more than 37.5 dBm, IIP3 is more than 70 dBm, the 2nd and the 3rd harmonic compressions are more than 96 dBc, and the control voltage is (+2.46 V, 0, -2.46 V) in the frequency from 0.1 to 2.7 GHz. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LZ16F010001).

  13. A Low-Voltage Silicon Light Emitting Device in Standard Salicide CMOS Technology

    NASA Astrophysics Data System (ADS)

    Wang, Wei; Huang, Bei-Ju; Dong, Zan; Liu, Hai-Jun; Zhang, Xu; Guan, Ning; Chen, Jin; Guo, Wei-Lian; Niu, Ping-Juan; Chen, Hong-Da

    2010-04-01

    A silicon-based field emission light emitting diode for low-voltage operation is fabricated in the standard 0.35 μm 2P4M salicide complementary metal-oxide-semiconductor (CMOS) technology. Partially overlapping p+ and n+ regions with a salicide block layer are employed in this device to constitute a heavily doped p+-n+ junction which has soft “knee" Zener breakdown characteristics, thus its working voltage can be reduced preferably below 5 V, and at the same time the power efficiency is improved. The spectra of this device are spread over 500 nm to 1000 nm with the main peak at about 722 nm and an obvious red shift of the spectra peak is observed with the increasing current through the device. During the emission process, field emission rather than avalanche process plays a major role. Differences between low-voltage Zener breakdown emission and high-voltage avalanche breakdown emission performance are observed and compared.

  14. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology

    PubMed Central

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-01-01

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode’s current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm2 of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA. PMID:26205275

  15. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

    PubMed

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-07-22

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA.

  16. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

    PubMed

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-01-01

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA. PMID:26205275

  17. 15158A SP6T RF switch based on IBM SOI CMOS technology

    NASA Astrophysics Data System (ADS)

    Zhiqun, Cheng; Guoguo, Yan; Wayne, Ni; Dandan, Zhu; Hannah, Ni; Jin, Li; Shuai, Chen; Guohua, Liu

    2016-05-01

    This paper presents the design of single-pole six-throw (SP6T) RF switch with IBM 0.18 μm SOI CMOS technology, which can be widely used in a wireless communication system with its high performance and low cost. The circuit is designed and simulated by using an idea that the total load is divided into six branches and SOI special structures. The insertion loss is less than 0.6 dB, isolation is more than 30 dB, the input power P0.1dB for 0.1 dB compression point is more than 37.5 dBm, IIP3 is more than 70 dBm, the 2nd and the 3rd harmonic compressions are more than 96 dBc, and the control voltage is (+2.46 V, 0, ‑2.46 V) in the frequency from 0.1 to 2.7 GHz. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LZ16F010001).

  18. Study of silicon-germanium junction formation for SOI based CMOS technology

    NASA Astrophysics Data System (ADS)

    Du, Yan

    Si1-xGex source/drain technology has been sucessfully applied to bulk metal oxide semiconductor field effect transistors (MOSFETs). Both channel mobility and source/drain contact resistivity are substantially improved with this technology. In this dissertation, Si1-xGex junction formation for silicon on insulator (SOI) based CMOS technology was investigated. Strain in epitaxially grown films on SOI films and silicon nanowires is studied using Raman spectroscopy and transmission electron microscope (TEM). For epitaxially grown Si1-xGe x film on SOI, there is lower degree of strain development in the SOI layer due to the rigid interface between the SOI and the burried oxide as compared to bulk. However, for silicon nanowires on oxide, the situation is different since nanowires serve as compliant substrates. Part of the strain energy is transferred to silicon nanowires. The consistency between synthesized Raman peak shifts and the experimental measurements verified the strain sharing between the epitaxially grown Si1-xGe x films and the silicon nanowires. Splittings of high order Laue zone line (HOLZ) from a convergent beam electron diffraction (CBED) pattern was quantified to study the strain distribution in epitaxial Si1- xGex films grown on silicon nanowires. It was found out in this study that elastic deformation of epitaxial Si 1-xGex at free surfaces leads to strain relaxation at these surfaces. This phenomenon is detrimental to strain engineering in a nanowire MOSFET and provides new challenges to develop smart designs for constraining strain in the nano-structures. Moreover, atomic layer deposition (ALD) Platinum is proposed for metal deposition on 3D epitaxial Si1-xGex source/drain. The uniform deposition around 3D Si1- xGex films effectively increases the contact surface area which is highly desired in the FinFET application.

  19. Performance of a-Si:H photodiode technology-based advanced CMOS active pixel sensor imagers

    NASA Astrophysics Data System (ADS)

    Theil, Jeremy A.; Haddad, Homayoon; Snyder, Rick D.; Zelman, Mike; Hula, David; Lindahl, Kirk A.

    2001-12-01

    Amorphous silicon photodiode technology is a very attractive option for image array integrated circuits because it enables large die-size reduction and higher light collection efficiency than c-Si arrays. The concept behind the technology is to place the photosensing element directly above the rest of the circuit, thus eliminating the need to make areal tradeoffs between photodiode and pixel circuit. We have developed an photodiode array technology that is fully compatible with a 0.35 um CMOS process to produce image sensors arrays with 10-bit dynamic range that are 30% smaller than comparable c-Si photodiode arrays. The work presented here will discuss performance issues and solutions to lend itself to cost-effective high-volume manufacturing. The various methods of interconnection of the diode to the array and their advantages will be presented. The effect of doped layer thickness and concentration on quantum efficiency, and the effect of a-Si:H defect concentration on diode performance will be discussed. The photodiode dark leakage current density is about 80 pA/cm2, and its absolute quantum efficiency peaks about 85% at 550 nm. These sensors have 50% higher sensitivity, and 2x lower dark current when compared to bulk silicon sensors of the same design. The cell utilizes a 3 FET design, but allows for 100% photodiode area due to the elevated nature of the design. The VGA (640 X 480), array demonstrated here uses common intrinsic and p-type contact layers, and makes reliable contact to those layers by use of a monolithic transparent conductor strap tied to vias in the interconnect.

  20. First measurement of the in-pixel electron multiplying with a standard imaging CMOS technology: Study of the EMCMOS concept

    NASA Astrophysics Data System (ADS)

    Brugière, Timothée; Mayer, Fréderic; Fereyre, Pierre; Guérin, Cyrille; Dominjon, Agnés; Barbier, Rémi

    2015-07-01

    Scientific low light imaging devices benefit today from designs for pushing the mean noise to the single electron level. When readout noise reduction reaches its limit, signal-to-noise ratio improvement can be driven by an electron multiplication process, driven by impact ionization, before adding the readout noises. This concept already implemented in CCD structures using extra-pixel shift registers can today be integrated inside each pixel in CMOS technology. The EBCMOS group at IPNL is in charge of the characterization of new prototypes developed by E2V using this concept: the electron multiplying CMOS (EMCMOS). The CMOS technology enables electron multiplication inside the photodiode itself, and thus, an overlap of the charge integration and multiplication. A new modeling has been developed to describe the output signal mean and variance after the impact ionization process in such a case. In this paper the feasibility of impact ionization process inside a 8 μm-pitch pixel is demonstrated. The new modeling is also validated by data and a value of 0.32% is obtained for the impact ionization parameter α with an electric field intensity of 24 V / μm.

  1. Study of dc micro-discharge arrays made in silicon using CMOS compatible technology

    NASA Astrophysics Data System (ADS)

    Kulsreshath, M. K.; Schwaederle, L.; Overzet, L. J.; Lefaucheux, P.; Ladroue, J.; Tillocher, T.; Aubry, O.; Woytasik, M.; Schelcher, G.; Dussart, R.

    2012-07-01

    In this paper we present the fabrication technology used to make micro-discharge ‘reactors’ on a silicon (Si) substrate. For the fabrication of these reactors we have used Si wafers with 4 inch diameter and standard cleanroom facilities. The fabrication technology used is compatible with standard CMOS device fabrication and the fabricated micro-discharge reactors can be used to produce dc discharges. These micro-discharges operate at near atmospheric pressure. They were given ring-shaped anodes separated from the cathode by a SiO2 dielectric with a thickness of approximately 5-6 µm rather than the much more common ˜100 µm. The micro-discharge reactors can consist of either a single hole or multiple holes and we have built devices with holes from 25 to 150 µm in diameter. The micro-discharge measurements were obtained for helium and argon dc plasmas between 100 and 1000 Torr. We used a single ballast resistor to produce micro-discharges in multi-hole array. This resistor also acted to limit the discharge power. An average current density of 0.8 A cm-2 was calculated for the 1024 holes array with 100 µm diameter holes. In addition, we will report on stability of micro-discharges depending on the cavity configuration of the micro-reactors and the ignition trends for the micro-discharge arrays. Finally, we discuss the life time of micro-discharge arrays as well as the factors affecting them (cathode sputtering, thermally affected zones, etc).

  2. Novel Circuitry Configuration with Paired-Cell Erase Operation for High-Density 90-nm Embedded Resistive Random Access Memory

    NASA Astrophysics Data System (ADS)

    Sato, Yoshihiro; Tsunoda, Koji; Aoki, Masaki; Sugiyama, Yoshihiro

    2009-04-01

    We propose a novel circuitry configuration for high-density 90-nm embedded resistive random access memory (ReRAM). The memory cells are operated at 2 V, and a small memory cell size of 6F2 consisting of a 1.2-V standard transistor and a resistive junction (1T-1R) is designed, where F is the feature size. The unique circuitry configuration is that each pair of source-lines connects to each source-line selective gate. Therefore, erasing is done by a pair of cells in turn in the whole sector, while the reading or programming is done by a random accessing operation. We simulated the ReRAM circuit for read and write operations with SPICE. As a result, we found that 5-ns high-speed read access was obtained in the 256-word lines (WLs) × 256-bit lines (BLs) and that the SET/RESET operation was stable.

  3. Development of III-Sb based technologies for p-channel MOSFET in CMOS applications

    NASA Astrophysics Data System (ADS)

    Madisetti, Shailesh Kumar

    The continuous scaling of silicon CMOS predicts the end of roadmap due to the difficulties such as that arise from electrostatic integrity, design complexities, and power dissipation. These fundamental and practical limitations bring the need for innovative design architectures or alternate materials with higher carrier transport than current Si based materials. New device designs such as multigate/gate-all-around architectures improve electrostatics while alternate materials like III-Vs such as III-As for electrons and III-Sbs for holes increase operational speed, lower power dissipation and thereby improve performance of the transistors due to their low effective mass and faster transport properties. Further, application of compressive strain on InxGa1-xSb modifies band structure enhancing hole mobility on par with its rival Germanium. This band structure modification lowers in plane hole meff* improving carrier transport thereby lowering power dissipation and increasing operational speed of future CMOS technology. This work studies optimization of thick GaSb layers grown on GaAs with the goal of improvement of growth, surface quality and achieve high hole mobility. Quality of growth is evaluated using atomic force microscopy (AFM) and electrically assessed using Van der Pauw (VdP) Hall method and capacitance-voltage measurements. After optimizing, the best top surface with average roughness (Ra) of ˜0.37 nm and spiral type ''step-flow'' growth mode in MBE was observed on the GaSb structure where initial 0.5 mum grown at 410°C and the top 0.5 mum grown at 485°C obtaining hole mobility of 737 cm2/V-s and 3.2 kO/sq at 2.7x1016 cm-3. N- and p-type GaSb MOSCaps with reasonable capacitance--voltage (C--V) characteristics at room temperature (RT) were demonstrated using all in-situ 0.5 nm a-Si interface passivation layer (IPL) and 10 nm Al2O3/HfO2 or Al 2O3. Amorphous-Si IPL was found essential for n-MOSCaps but not in the case of p-MOSCaps where comparable C

  4. High performance rf front end circuits using SiGe:C BiCMOS+copper technologies

    NASA Astrophysics Data System (ADS)

    Watanabe, Glenn; Ortiz, Jeff; Holbrook, Rick

    2004-03-01

    Using a first generation standard silicon germanium (SiGe):C HBT BiCMOS process, a personal digital cellular (PDC) LNA noice factor (NF) of 1.0 dB at 850 MHz and 1.2 dB at 1.5 GHz has been achieved. The LNA NF can be further reduced by using the second generation enhanced SiGe:C HBT BiCMOS process. The mixer performance is equally impressive. The NF of the downconversion mixer at 1.5 GHz is just 6.2 dB with a conversion gain of 12 dB. The mixer IIP3 is +9.9 dBm at a current drain of 5.6 mA. Design techniques are given on how to achieve high linearity with minimal current drain resulting in a 881 MHz LNA with an IIP3 of +12.4 dBm with just 6 mA of current and a NF of 1.4 dB using the first generation SiGe:C HBT BiCMOS process. The second generation enhanced SiGe:C HBT BiCMOS process should further reduce the noise figure.

  5. Reconfigurable RF CMOS Circuit for Cognitive Radio

    NASA Astrophysics Data System (ADS)

    Masu, Kazuya; Okada, Kenichi

    Cognitive radio and/or SDR (Software Defined Radio) inherently requires multi-band and multi standard wireless circuit. The circuit is implemented based on Si CMOS technology. In this article, the recent progress of Si RF CMOS is described and the reconfigurable RF CMOS circuit which was proposed by the authors is introduced. At the present and in the future, several kind of Si CMOS technology can be used for RF CMOS circuit implementation. The realistic RF CMOS circuit implementation toward cognitive and/or SDR is discussed.

  6. A low voltage CMOS low drop-out voltage regulator

    NASA Astrophysics Data System (ADS)

    Bakr, Salma Ali; Abbasi, Tanvir Ahmad; Abbasi, Mohammas Suhaib; Aldessouky, Mohamed Samir; Abbasi, Mohammad Usaid

    2009-05-01

    A low voltage implementation of a CMOS Low Drop-Out voltage regulator (LDO) is presented. The requirement of low voltage devices is crucial for portable devices that require extensive computations in a low power environment. The LDO is implemented in 90nm generic CMOS technology. It generates a fixed 0.8V from a 2.5V supply which on discharging goes to 1V. The buffer stage used is unity gain configured unbuffered OpAmp with rail-to-rail swing input stage. The simulation result shows that the implemented circuit provides load regulation of 0.004%/mA and line regulation of -11.09mV/V. The LDO provides full load transient response with a settling time of 5.2μs. Further, the dropout voltage is 200mV and the quiescent current through the pass transistor (Iload=0) is 20μA. The total power consumption of this LDO (excluding bandgap reference) is only 80μW.

  7. Ion traps fabricated in a CMOS foundry

    SciTech Connect

    Mehta, K. K.; Ram, R. J.; Eltony, A. M.; Chuang, I. L.; Bruzewicz, C. D.; Sage, J. M. Chiaverini, J.

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  8. A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

    NASA Astrophysics Data System (ADS)

    Schmitz, A.; Tielert, R.

    2005-05-01

    Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

  9. Spin blockade in a triple silicon quantum dot in CMOS technology

    NASA Astrophysics Data System (ADS)

    Prati, E.; Petretto, G.; Belli, M.; Mazzeo, G.; Cocco, S.; de Michielis, M.; Fanciulli, M.; Guagliardo, F.; Vinet, M.; Wacquez, R.

    2012-02-01

    We study the spin blockade (SB) phenomenon by quantum transport in a triple quantum dot made of two single electron transistors (SET) on a CMOS platform separated by an implanted multiple donor quantum dot [1]. Spin blockade condition [2] has been used in the past to realize single spin localization and manipulation in GaAs quantum dots [3]. Here, we reproduce the same physics in a CMOS preindustrial silicon quantum device. Single electron quantum dots are connected via an implanted quantum dot and exhibit SB in one current direction. We break the spin blockade by applying a magnetic field of few tesla. Our experimental results are explained by a theoretical microscopic scheme supported by simulations in which only some of the possible processes through the triple quantum dot are spin blocked, according to the asymmetry of the coupling capacitances with the control gates and the central dot. Depending on the spin state, the SB may be both lifted and induced. Spin control in CMOS quantum dots is a necessary condition to realize large fabrication of spin qubits in some solid state silicon quantum device architectures.[0pt] [1] Pierre et al., Appl. Phys. Lett., 95, 24, 242107 (2009); [2] Liu et al., Phys. Rev. B 77, 073310 (2008); [3] Koppens et al., Nature 442, 766-771 (2006)

  10. System-in Package of Integrated Humidity Sensor Using CMOS-MEMS Technology.

    PubMed

    Lee, Sung Pil

    2015-10-01

    Temperature/humidity microchips with micropump were fabricated using a CMOS-MEMS process and combined with ZigBee modules to implement a sensor system in package (SIP) for a ubiquitous sensor network (USN) and/or a wireless communication system. The current of a diode temperature sensor to temperature and a normalized current of FET humidity sensor to relative humidity showed linear characteristics, respectively, and the use of the micropump has enabled a faster response. A wireless reception module using the same protocol as that in transmission systems processed the received data within 10 m and showed temperature and humidity values in the display.

  11. DFM in practice: results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90-nm FPGA chip

    NASA Astrophysics Data System (ADS)

    Yu, Chun-Chi; Shieh, Ming-Feng; Liu, Erick; Lin, Benjamin; Lin, Henry; Chacko, Manoj; Li, Xiaoyang; Lei, Wen-Kang; Ho, Jonathan; Wu, Xin

    2005-05-01

    At the sub 90nm nodes, resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential steps in the post-physical verification 'Mask Synthesis' process and a key component of design for manufacturing (DFM). Several studies have been conducted and the results have been published on the implication and application of the different types of RETs on mask printability and costs. More specifically, double-exposure-based, dark-field, alternating PSM (Alt-PSM) technology has received lot of attention with respect to the mask manufacturing challenges and its implementation into a production flow, despite its yield and critical dimension (CD) control superiority. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a matured, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. What follows is an in-depth review of the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

  12. Cross-talk characterization of dense single-photon avalanche diode arrays in CMOS 150-nm technology

    NASA Astrophysics Data System (ADS)

    Xu, Hesong; Pancheri, Lucio; C. Braga, Leo H.; Betta, Gian-Franco Dalla; Stoppa, David

    2016-06-01

    Cross-talk characterization results of high-fill-factor single-photon avalanche diode (SPAD) arrays in CMOS 150-nm technology are reported and discussed. Three different SPAD structures were designed with two different sizes (15.6 and 25.6 μm pitch) and three guard ring widths (0.6, 1.1, and 1.6 μm). Each SPAD was implemented in an array, composed of 25 (5×5) devices, which can be separately activated. Measurement results show that the average cross-talk probability is well below 1% for the shallow-junction SPAD structure with 15.6 μm pitch and 39.9% fill factor, and 1.45% for the structure with 25.6 μm pitch and 60.6% fill factor. An increase of cross-talk probability with the excess bias voltage is observed.

  13. A novel diode string triggered gated-PiN junction device for electrostatic discharge protection in 65-nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Zhang, Li-Zhong; Wang, Yuan; Lu, Guang-Yi; Cao, Jian; Zhang, Xing

    2015-10-01

    A novel diode string-triggered gated-PiN junction device, which is fabricated in a standard 65-nm complementary metal-oxide semiconductor (CMOS) technology, is proposed in this paper. An embedded gated-PiN junction structure is employed to reduce the diode string leakage current to 13 nA/μm in a temperature range from 25 °C to 85 °C. To provide the effective electrostatic discharge (ESD) protection in multi-voltage power supply, the triggering voltage of the novel device can be adjusted through redistributing parasitic resistance instead of changing the stacked diode number. Project supported by the National Basic Research Program of China (Grant No. 2011CBA00606).

  14. Comprehensive procedural approach for transferring or comparative analysis of analogue IP building blocks towards different CMOS technologies

    NASA Astrophysics Data System (ADS)

    Gevaert, Dorine M.

    2009-05-01

    The challenges for the next generation of integrated circuit design of analogue and mixed-signal building blocks in standard CMOS technologies for signal conversion demand research progress in the emerging scientific fields of device physics and modelling, converter architectures, design automation, quality assurance and cost factor analysis. Estimation of mismatch for analogue building blocks at the conceptual level and the impact on active area is not a straightforward calculation. The proposed design concepts reduce the over-sizing of transistors, compared with the existing methods, with 15 to 20% for the same quality specification. Besides the reduction of the silicon cost also the design time cost for new topologies is reduced considerably. Comparison has been done for current mode converters (ADC and DAC) and focussing on downscaling technologies. The developed method offers an integrated approach on the estimation of architecture performances, yield and IP-reuse. Matching energy remains constant over process generations and will be the limiting factor for current signal processing. The comprehensive understanding of all sources of mismatches and the use of physical based mismatch modelling in the prediction of mismatch errors, more adequate and realistic sizing of all transistors will result in an overall area reduction of analogue IP blocks. For each technology the following design curves are automatically developed: noise curves for a specified signal bandwidth, choice of overdrive voltage versus lambda and output resistance, physical mismatch error modelling on target current levels. The procedural approach shares knowledge of several design curves and speeds up the design time.

  15. A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

    PubMed Central

    Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A.; Wu, Wen-Jung; Lin, Chih-Ting

    2014-01-01

    A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems. PMID:24859027

  16. A Retinal Prosthesis Technology Based on CMOS Microelectronics and Microwire Glass Electrodes.

    PubMed

    Scribner, D; Johnson, L; Skeath, P; Klein, R; Ilg, D; Wasserman, L; Fernandez, N; Freeman, W; Peele, J; Perkins, F K; Friebele, E J; Bassett, W E; Howard, J G; Krebs, W

    2007-03-01

    A very large format neural stimulator device, to be used in future retinal prosthesis experiments, has been designed, fabricated, and tested. The device was designed to be positioned against a human retina for short periods in an operating room environment. Demonstrating a very large format, parallel interface between a 2-D microelectronic stimulator array and neural tissue would be an important step in proving the feasibility of high resolution retinal prosthesis for the blind. The architecture of the test device combines several novel components, including microwire glass, a microelectronic multiplexer, and a microcable connector. The array format is 80 times 40 array pixels with approximately 20 microwire electrodes per pixel. The custom assembly techniques involve indium bump bonding, ribbon bonding, and encapsulation. The design, fabrication, and testing of the device has resolved several important issues regarding the feasibility of high-resolution retinal prosthesis, namely, that the combination of conventional CMOS electronics and microwire glass provides a viable approach for a high resolution retinal prosthesis device. Temperature change from power dissipation within the device and maximum electrical output current levels suggest that the device is acceptable for acute human tests. PMID:23851523

  17. Design of the low area monotonic trim DAC in 40 nm CMOS technology for pixel readout chips

    NASA Astrophysics Data System (ADS)

    Drozd, A.; Szczygiel, R.; Maj, P.; Satlawa, T.; Grybos, P.

    2014-12-01

    The recent research in hybrid pixel detectors working in single photon counting mode focuses on nanometer or 3D technologies which allow making pixels smaller and implementing more complex solutions in each of the pixels. Usually single pixel in readout electronics for X-ray detection comprises of charge amplifier, shaper and discriminator that allow classification of events occurring at the detector as true or false hits by comparing amplitude of the signal obtained with threshold voltage, which minimizes the influence of noise effects. However, making the pixel size smaller often causes problems with pixel to pixel uniformity and additional effects like charge sharing become more visible. To improve channel-to-channel uniformity or implement an algorithm for charge sharing effect minimization, small area trimming DACs working in each pixel independently are necessary. However, meeting the requirement of small area often results in poor linearity and even non-monotonicity. In this paper we present a novel low-area thermometer coded 6-bit DAC implemented in 40 nm CMOS technology. Monte Carlo simulations were performed on the described design proving that under all conditions designed DAC is inherently monotonic. Presented DAC was implemented in the prototype readout chip with 432 pixels working in single photon counting mode, with two trimming DACs in each pixel. Each DAC occupies the area of 8 μm × 18.5 μm. Measurements and chips' tests were performed to obtain reliable statistical results.

  18. A novel HBT trigger SCR in 0.35 μm SiGe BiCMOS technology

    NASA Astrophysics Data System (ADS)

    Changjun, Liao; Jizhi, Liu; Zhiwei, Liu

    2016-09-01

    The silicon-controlled rectifier (SCR) device is known as an efficient electrostatic discharge (ESD) protection device due to the highest ESD robustness in the smallest layout area. However, SCR has some drawbacks, such as high trigger voltage and low holding voltage. In order to reduce the trigger voltage of the SCR device for ESD protection, a new heterojunction bipolar transistor (HBT) trigger silicon controlled rectifier (HTSCR) device in 0.35 μm SiGe BiCMOS technology are proposed. The underlying physical mechanisms critical to the trigger voltage are demonstrated based on transmission line pulsing (TLP) measurement and physics-based simulation results. The simulation results prove that the trigger voltage of the HTSCR is decided by the collector-to-emitter breakdown voltage of the HBT structure in floating base configuration. The ESD experiment test results demonstrate the HTSCR can offer superior performance with a small trigger voltage, an adjustable holding voltage and a high ESD robustness. In comparison to the conventional MLSCR, the trigger voltage of the fabricated HTSCR can reduce to less than 50% of that of the MLSCR, and the I t2 of the HBT trigger SCR is 80% more than that of the MLSCR. Project supported by the Central Universities Fundamental Research Project (No. ZYGX2015J035) and the Sichuan Science and Technology Support Project (No. 2016GZ0115).

  19. Design of a MEMS-Based Oscillator Using 180nm CMOS Technology

    PubMed Central

    Roy, Sukanta; Ramiah, Harikrishnan; Reza, Ahmed Wasif; Lim, Chee Cheow; Ferrer, Eloi Marigo

    2016-01-01

    Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator’s high motion losses due to the possibility of their ‘system-on-chip’ integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design’s applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications. PMID:27391136

  20. Design of a MEMS-Based Oscillator Using 180nm CMOS Technology.

    PubMed

    Roy, Sukanta; Ramiah, Harikrishnan; Reza, Ahmed Wasif; Lim, Chee Cheow; Ferrer, Eloi Marigo

    2016-01-01

    Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator's high motion losses due to the possibility of their 'system-on-chip' integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design's applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications. PMID:27391136

  1. Design of a MEMS-Based Oscillator Using 180nm CMOS Technology.

    PubMed

    Roy, Sukanta; Ramiah, Harikrishnan; Reza, Ahmed Wasif; Lim, Chee Cheow; Ferrer, Eloi Marigo

    2016-01-01

    Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator's high motion losses due to the possibility of their 'system-on-chip' integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design's applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications.

  2. 3D integration approaches for MEMS and CMOS sensors based on a Cu through-silicon-via technology and wafer level bonding

    NASA Astrophysics Data System (ADS)

    Hofmann, L.; Dempwolf, S.; Reuter, D.; Ecke, R.; Gottfried, K.; Schulz, S. E.; Knechtel, R.; Geßner, T.

    2015-05-01

    Technologies for the 3D integration are described within this paper with respect to devices that have to retain a specific minimum wafer thickness for handling purposes (CMOS) and integrity of mechanical elements (MEMS). This implies Through-Silicon Vias (TSVs) with large dimensions and high aspect ratios (HAR). Moreover, as a main objective, the aspired TSV technology had to be universal and scalable with the designated utilization in a MEMS/CMOS foundry. Two TSV approaches are investigated and discussed, in which the TSVs were fabricated either before or after wafer thinning. One distinctive feature is an incomplete TSV Cu-filling, which avoids long processing and complex process control, while minimizing the thermomechanical stress between Cu and Si and related adverse effects in the device. However, the incomplete filling also includes various challenges regarding process integration. A method based on pattern plating is described, in which TSVs are metalized at the same time as the redistribution layer and which eliminates the need for additional planarization and patterning steps. For MEMS, the realization of a protective hermetically sealed capping is crucial, which is addressed in this paper by glass frit wafer level bonding and is discussed for hermetic sealing of MEMS inertial sensors. The TSV based 3D integration technologies are demonstrated on CMOS like test vehicle and on a MEMS device fabricated in Air Gap Insulated Microstructure (AIM) technology.

  3. Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

    2015-06-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

  4. A methodology for the characterization of arithmetic circuits on CMOS deep submicron technologies

    NASA Astrophysics Data System (ADS)

    Estrada, Adrian; Jimenez, Carlos J.; Valencia, Manuel

    2005-06-01

    Integration technologies have favored the design and implementation of more complex circuits. Thanks to this increased complexity, these circuits are capable of implementing algorithms which a few years ago were too expensive in both area and computational resources. However, they now offer interesting choices which should be considered. This new generation of integrated circuits nevertheless presents other kinds of restrictions that the designer should bear in mind. Parameters such as frequency of operation or power consumption are new restrictions that the designer has to deal with in order to fulfill the conditions established by the circuit functionality. Finally, the shrinking integration scale of current technologies makes the timing behavior of the design differ from previous technologies. Thus, a review of the timing behavior of the digital circuit should be done. So far, arithmetic circuits have been used as a benchmark for the analysis and design procedures of digital circuits. Therefore, it is our goal now to analyze both conventional and modern arithmetic circuits structures for different deep-submicron technologies. To achieve this goal, a good solution is to characterize a set of algorithmic circuits for several deep submicron processes, so that the designer can select the most suitable one depending upon the intended application and existing restrictions. In this paper, the first steps to attain such selection are presented. In particular, we propose a design and VHDL characterization methodology based on an RTL description of each component, on the utilization of an automated synthesis tool, and on the generation of logic characteristics from the logic level. This methodology is applied to a set of adders structures, the results of which are also presented.

  5. Design of complementary LDMOS in 0.35 μm BiCMOS technology for smart integration

    NASA Astrophysics Data System (ADS)

    Abouelatta-Ebrahim, M.; Gontrand, C.; Zekry, A.

    2012-01-01

    In this paper, an nLDMOS and a pLDMOS are developed by slight modifications of the base process steps of 0.35 μm BiCMOS technology. Extra two masks are used for the formation of the body region and the drift region with slightly added thermal budget and without resorting to high-tilt implants. The specific ON-resistance (RON,SP) and the OFF-state breakdown voltage (BV) are 1.5 mΩ cm2 and 60 V, for the nLDMOS and 3.0 mΩ cm2 and 160 V, for the pLDMOS, so the devices can typically be operated around 42 V supply voltage, which is suitable for the new automotive applications. An isolation mechanism between the power devices is suggested using a deep trench filled with silicon dioxide and undoped polysilicon. The polysilicon has a nearly perfect conformal deposition, that is, both step coverage and bottom coverage are 100%. A simple subcircuit model is built using a two module approach, one for the intrinsic MOS area and the other for the drift region. The Spice model parameters of the intrinsic MOS part are extracted using a system that links the ICCAP extraction tool with the results of the ISE-TCAD tools. The simulation results using the Spice model are compared to the results provided by ISE-TCAD tools, and the accuracy at room temperature is less than 5% for the whole voltage domain. An interface circuit, to convert 0/3.3 V to 0/42 V, suitable for automotive applications, is proposed.

  6. Low-loss and low-crosstalk 8 × 8 silicon nanowire AWG routers fabricated with CMOS technology.

    PubMed

    Wang, Jing; Sheng, Zhen; Li, Le; Pang, Albert; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Qi, Minghao; Gan, Fuwan

    2014-04-21

    Low-loss and low-crosstalk 8 × 8 arrayed waveguide grating (AWG) routers based on silicon nanowire waveguides are reported. A comparative study of the measurement results of the 3.2 nm-channel-spacing AWGs with three different designs is performed to evaluate the effect of each optimal technique, showing that a comprehensive optimization technique is more effective to improve the device performance than a single optimization. Based on the comprehensive optimal design, we further design and experimentally demonstrate a new 8-channel 0.8 nm-channel-spacing silicon AWG router for dense wavelength division multiplexing (DWDM) application with 130 nm CMOS technology. The AWG router with a channel spacing of 3.2 nm (resp. 0.8 nm) exhibits low insertion loss of 2.32 dB (resp. 2.92 dB) and low crosstalk of -20.5~-24.5 dB (resp. -16.9~-17.8 dB). In addition, sophisticated measurements are presented including all-input transmission testing and high-speed WDM system demonstrations for these routers. The functionality of the Si nanowire AWG as a router is characterized and a good cyclic rotation property is demonstrated. Moreover, we test the optical eye diagrams and bit-error-rates (BER) of the de-multiplexed signal when the multi-wavelength high-speed signals are launched into the AWG routers in a system experiment. Clear optical eye diagrams and low power penalty from the system point of view are achieved thanks to the low crosstalk of the AWG devices. PMID:24787827

  7. A low-power 20 GSps track-and-hold amplifier in 0.18 μm SiGe BiCMOS technology

    NASA Astrophysics Data System (ADS)

    Kai, Tang; Qiao, Meng; Zhigong, Wang; Yi, Zhang; Kuai, Yin; Ting, Guo

    2013-09-01

    An open-loop 20 GSps track-and-hold amplifier (THA) using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to achieve high speed and good linearity. A cross-coupled pair is used in the input buffer to suppress the charge injection and clock feedthrough. Both the input and output buffers use an active inductor load to achieve high signal bandwidth. The THA is realized with 0.18 μm SiGe BiCMOS technology using only CMOS devices at a 1.8 V voltage supply and with a core area of 0.024 mm2. The measurement results show that the SFDR is 32.4 dB with a 4 GHz sine wave input at a 20 GSps sampling rate, and the third harmonic distortion is -48 dBc. The effective resolution bandwidth of the THA is 12 GHz and the figure of merit is only 0.028 mW/GHz.

  8. Temperature behavior of spiral inductors on high resistivity substrate in SOI CMOS technology

    NASA Astrophysics Data System (ADS)

    El Kaamouchi, M.; Delatte, P.; Si Moussa, M.; Raskin, J.-P.; Vanhoenacker-Janvier, D.

    2008-12-01

    This paper reviews and analyzes a compact model for integrated planar spiral inductors on standard and high resistivity substrates in silicon-on-insulator (SOI) technology. The inductors have been characterized over a temperature range from 25 to 200 °C. The temperature variation of each model parameter has been investigated. It demonstrates that only the variations of the metallic losses versus temperature have to be taken into account to model properly the high frequency behavior over a wide temperature range of a spiral inductor integrated on silicon high resistivity substrate. Based on these experimental and characterization results, guidelines for practical inductor designs in RFICs for high-temperature applications are drawn.

  9. DC-DC converters in 0.35μm CMOS technology

    NASA Astrophysics Data System (ADS)

    Michelis, S.; Allongue, B.; Blanchot, G.; Faccio, F.; Fuentes, C.; Orlandi, S.; Saggini, S.; Cengarle, S.; Ongaro, F.

    2012-01-01

    In view of the upgrade of the LHC experiments, we are developing custom DC/DC converters for a more efficient power distribution scheme. A new prototype have been integrated in ASICs in the selected 0.35μm commercial high voltage technology that has been successfully tested for all radiation effects: TID, displacement damage and Single Event Burnout. This converter has been optimized for high efficiency and improved radiation tolerance. Amongst the new features the most relevant are the presence of internal linear regulators, protection circuits with a state-machine and a new pinout for a modified assembly in package in order to reduce conductive losses. This paper illustrates the design of the prototype followed by functional and radiation tests.

  10. CCD and APS/CMOS technology for smart pixels and image sensors

    NASA Astrophysics Data System (ADS)

    Seitz, Peter; Blanc, Nicolas

    2004-02-01

    The relentless progress of semiconductor technology makes it possible to provide image sensors and pixels with additional analog and digital functionality. Growing experience with such photosensor functionality leads to the development of modular building blocks that can be employed for smart pixels, single-chip digital cameras and functional image sensors. Examples given include a non-linear pixel response circuit for high-dynamic range imaging offering a dynamic range of more than 180 dB, low-noise amplifiers and avalanche-effect pixels for high-sensitivity detection performance that approaches single-photoelectron resolution, lock-in pixels for optical time-of-flight range cameras with sub-centimeter distance resolution and in-pixel demodulation circuits for optical coherence tomography imaging. The future is seen in even higher levels of integration, such as system-on-a-chip machine vision cameras ("seeing chips"), post-processing with non-silicon materials for the extension of the detection range to the X-ray, ultraviolet and infrared spectrum, the exploitation of all properties of the incident light and imaging of fields other than electromagnetic radiation

  11. Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology.

    PubMed

    Talaśka, Tomasz; Kolasa, Marta; Długosz, Rafał; Pedrycz, Witold

    2016-03-01

    This paper presents a programmable analog current-mode circuit used to calculate the distance between two vectors of currents, following two distance measures. The Euclidean (L2) distance is commonly used. However, in many situations, it can be replaced with the Manhattan (L1) one, which is computationally less intensive, whose realization comes with less power dissipation and lower hardware complexity. The presented circuit can be easily reprogrammed to operate with one of these distances. The circuit is one of the components of an analog winner takes all neural network (NN) implemented in the complementary metal-oxide-semiconductor 0.18- [Formula: see text] technology. The learning process of the realized NN has been successfully verified by the laboratory tests of the fabricated chip. The proposed distance calculation circuit (DCC) features a simple structure, which makes it suitable for networks with a relatively large number of neurons realized in hardware and operating in parallel. For example, the network with three inputs occupies a relatively small area of 3900 μm(2). When operating in the L2 mode, the circuit dissipates 85 [Formula: see text] of power from the 1.5 V voltage supply, at maximum data rate of 10 MHz. In the L1 mode, an average dissipated power is reduced to 55 [Formula: see text] from 1.2 V voltage supply, while data rate is 12 MHz in this case. The given data rates are provided for the worst case scenario, where input currents differ by 1%-2% only. In this case, the settling time of the comparators used in the DCC is quite long. However, that kind of situation is very rare in the overall learning process.

  12. High-temperature Complementary Metal Oxide Semiconductors (CMOS)

    NASA Technical Reports Server (NTRS)

    Mcbrayer, J. D.

    1981-01-01

    The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

  13. Design of millimeter-wave MEMS-based reconfigurable front-end circuits using the standard CMOS technology

    NASA Astrophysics Data System (ADS)

    Chang, Chia-Chan; Hsieh, Sheng-Chi; Chen, Chien-Hsun; Huang, Chin-Yen; Yao, Chun-Han; Lin, Chun-Chi

    2011-12-01

    This paper describes the designs of three reconfigurable CMOS-MEMS front-end components for V-/W-band applications. The suspended MEMS structure is released through post-CMOS micromachining. To achieve circuit reconfigurability, dual-state and multi-state fishbone-beam-drive actuators are proposed herein. The reconfigurable bandstop is fabricated in a 0.35 µm CMOS process with the chip size of 0.765 × 0.98 mm2, showing that the stop-band frequency can be switched from 60 to 50 GHz with 40 V actuation voltage. The measured isolation is better than 38 dB at 60 GHz and 34 dB at 50 GHz, respectively. The bandpass filter-integrated single-pole single-throw switch, using the 0.18 µm CMOS process, demonstrates that insertion loss and return loss are better than 6.2 and 15 dB from 88 to 100 GHz in the on-state, and isolation is better than 21 dB in the off-state with an actuation voltage of 51 V. The chip size is 0.7 × 1.04 mm2. The third component is a reconfigurable slot antenna fabricated in a 0.18 µm CMOS process with the chip size of 1.2 × 1.2 mm2. By utilizing the multi-state actuators, the frequencies of this antenna can be switched to 43, 47, 50.5, 54, 57.5 GHz with return loss better than 20 dB. Those circuits demonstrate good RF performance and are relatively compact by employing several size miniaturizing techniques, thereby enabling a great potential for the future single-chip transceiver.

  14. A 2x2 W-Band Reference Time-Shifted Phase-Locked Transmitter Array in 65nm CMOS Technology

    NASA Technical Reports Server (NTRS)

    Tang, Adrian; Virbila, Gabriel; Hsiao, Frank; Wu, Hao; Murphy, David; Mehdi, Imran; Siegel, P. H.; Chang, M-C. Frank

    2013-01-01

    This paper presents a complete 2x2 phased array transmitter system operating at W-band (90-95 GHz) which employs a PLL reference time-shifting approach instead of using traditional mm-wave phase shifters. PLL reference shifting enables a phased array to be distributed over multiple chips without the need for coherent mm-wave signal distribution between chips. The proposed phased array transmitter system consumes 248 mW per array element when implemented in a 65 nm CMOS technology.

  15. A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems.

    PubMed

    Zheng, Xuezhe; Liu, Frankie; Patil, Dinesh; Thacker, Hiren; Luo, Ying; Pinguet, Thierry; Mekis, Attila; Yao, Jin; Li, Guoliang; Shi, Jing; Raj, Kannan; Lexau, Jon; Alon, Elad; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

    2010-01-01

    We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible.

  16. A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems.

    PubMed

    Zheng, Xuezhe; Liu, Frankie; Patil, Dinesh; Thacker, Hiren; Luo, Ying; Pinguet, Thierry; Mekis, Attila; Yao, Jin; Li, Guoliang; Shi, Jing; Raj, Kannan; Lexau, Jon; Alon, Elad; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

    2010-01-01

    We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible. PMID:20173840

  17. An integrated 12.5-Gb/s optoelectronic receiver with a silicon avalanche photodetector in standard SiGe BiCMOS technology.

    PubMed

    Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

    2012-12-17

    An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom bit sequence optical data with the bit-error rate less than 10(-12) at incident optical power of -7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

  18. Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

    PubMed

    Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

    2012-07-01

    In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

  19. Gun muzzle flash detection using a single photon avalanche diode array in 0.18µm CMOS technology

    NASA Astrophysics Data System (ADS)

    Savuskan, Vitali; Jakobson, Claudio; Merhav, Tomer; Shoham, Avi; Brouk, Igor; Nemirovsky, Yael

    2015-05-01

    In this study, a CMOS Single Photon Avalanche Diode (SPAD) 2D array is used to record and sample muzzle flash events in the visible spectrum, from representative weapons. SPADs detect the emission peaks of alkali salts, potassium or sodium, with spectral emission lines around 769nm and 589nm, respectively. The alkali salts are included in the gunpowder to suppress secondary flashes ignited during the muzzle flash event. The SPADs possess two crucial properties for muzzle flash imaging: (i) very high photon detection sensitivity, (ii) a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. The sole noise sources are the ones prior to the readout circuitry (optical signal distribution, avalanche initiation distribution and nonphotonic generation). This enables high sampling frequencies in the kilohertz range without significant SNR degradation, in contrast to regular CMOS image sensors. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength, in the presence of sunlight. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics and signal processing, which will be reported. The frame rate of ~16 KHz was chosen as an optimum between SNR degradation and temporal profile recognition accuracy. In contrast to a single SPAD, the 2D array allows for multiple events to be processed simultaneously. Moreover, a significant field of view is covered, enabling comprehensive surveillance and imaging.

  20. A wide range ultra-low power Phase-Locked Loop with automatic frequency setting in 130 nm CMOS technology for data serialisation

    NASA Astrophysics Data System (ADS)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moroń, J.; Świentek, K.

    2015-12-01

    The design and measurements results of a wide frequency range ultra-low power Phase-Locked Loop (PLL) for applications in readout systems of particle physics detectors are presented. The PLL was fabricated in a 130 nm CMOS technology. To allow the implementation of different data serialisation schemes multiple division factors (6, 8, 10, 16) were implemented in the PLL feedback loop. The main PLL block—VCO works in 16 frequency ranges/modes, switched either manually or automatically. A dedicated automatic frequency mode switching circuit was developed to allow simple frequency tuning. Although the PLL was designed and simulated for a frequency range of 30 MHz-3 GHz, due to the SLVS interface limits, the measurements were done only up to 1.3 GHz. The full PLL functionality was experimentally verified, confirming a very low and frequency scalable power consumption (0.7 mW at 1 GHz).

  1. A 1.36μW 312-315MHz synchronized-OOK receiver for wireless sensor networks using 65nm SOTB CMOS technology

    NASA Astrophysics Data System (ADS)

    Hoang, Minh-Thien; Sugii, Nobuyuki; Ishibashi, Koichiro

    2016-03-01

    The paper presents a receiver design operating at 312-315 MHz frequency band for wireless sensor networks. The proposed architecture uses synchronized on-off-keying (S-OOK) modulation scheme, which includes clock information together with data, providing self-synchronization ability for the receiver without a separate clock and data recovery circuit. In addition, a new technique is also proposed to reduce active time of the RF font-end for better energy efficiency. The receiver architecture is verified by using discrete RF modules and FPGAs, then VLSI design is carried out on 65 nm Silicon-On-Thin-Buried-Oxide (SOTB) CMOS technology and simulated using SPICE models to illustrate effectiveness of the proposed architecture. Post-layout simulation shows -58.5 dBm sensitivity with 1.36 μW and 8.39 μW power consumption corresponding to 10 kbps and 100 kbps data rate, respectively.

  2. A fully integrated folded mixer in CMOS 0.35 µm technology for 802.11a WIFI applications

    NASA Astrophysics Data System (ADS)

    del Pino, J.; Díaz, R.; Afonso, M.; Cabrera, F.; Iturri, A.; Khemchandani, S. L.

    2007-05-01

    In the last years, Wireless market has shown an incredible growth, exceeding expectations. This paper presents a fully integrated folded mixer in a BiCMOS 0.35 μm technology for the 5 GHz band, according to the IEEE 802.11a WIFI standard. To make possible a comparison, two designs are presented: a folded mixer, and a classical Gilbert cell. In both designs all passives devices are on chip, including integrated inductors which have been designed by electromagnetic simulations. This work demonstrates the improvement in gain and linearity of a folded mixer comparing to a classical Gilbert topology, at expense of a little increase in power consumption. This implies that, unlike the Gilbert mixer, in a low voltage application, the folded topology would present still good performance.

  3. Optical hybrid package with an 8-channel 18GT/s CMOS transceiver for chip-to-chip optical interconnect

    NASA Astrophysics Data System (ADS)

    Mohammed, E.; Liao, J.; Kern, A.; Lu, D.; Braunisch, H.; Thomas, T.; Hyvonen, S.; Palermo, S.; Young, I. A.

    2008-02-01

    We describe the design and development of a high-speed 8-channel hybrid integrated optical transceiver package with Clock and Data Recovery (CDR) circuits. The package concept has been developed to be compatible with microprocessor package technology and at the same time allow the integration of low cost, high-performance optical components. A 90nm CMOS optical transceiver chip, 850nm 10Gb/s GaAs based vertical cavity surface emitting laser (VCSEL) array and PIN photodiode array are flip-chip mounted on a standard microprocessor Land Grid Array (LGA) package substrate. The CMOS drivers and receivers on the transceiver chip and the optical components (VCSEL and Photodiode arrays) are electrically coupled using a short transmission line routed on the top surface of the package. VCSEL and photodiode arrays are optically coupled to on-package integrated polymer waveguide arrays with metallized 45° mirrors. The waveguides, which are terminated with multi-terminal (MT) fiber optic connectors, couple out/in high-speed optical signals to/from the chip. The CMOS transceiver chip fully integrates all analog optical circuits such as VCSEL drivers, transimpedance amplifiers and clock and data recovery (CDR) retiming circuit with a low jitter LC-PLL. Digital circuits for pseudorandom bit-pattern sequence generators (PRBS) and bit-error rate test (BERT) are fully integrated. 20Gb/s electrical and 18Gb/s optical eye diagrams for the transmitter were measured out of the package. A fully packaged transmitter and receiver including clock data recovery at 10Gb/s have also been measured.

  4. A 64 single photon avalanche diode array in 0.18 µm CMOS standard technology with versatile quenching circuit for quick prototyping

    NASA Astrophysics Data System (ADS)

    Uhring, Wilfried; Le Normand, Jean-Pierre; Zint, Virginie; Dumas, Norbert; Dadouche, Foudil; Malasse, Imane; Scholz, Jeremy

    2012-04-01

    Several works have demonstrated the successfully integration of Single-photon avalanche photodiodes (SPADs) operating in Geiger mode in a standard CMOS circuit for the last 10 years. These devices offer an exceptional temporal resolution as well as a very good optical sensitivity. Nevertheless, it is difficult to predict the expected performances of such a device. Indeed, for a similar structure of SPAD, some parameter values can differ by two orders of magnitude from a technology to another. We proposed here a procedure to identify in just one or two runs the optimal structure of SPAD available for a given technology. A circuit with an array of 64 SPAD has been realized in the Tower-Jazz 0.18 μm CMOS image sensor process. It encompasses an array of 8 different structures of SPAD reproduced in 8 diameters in the range from 5 μm up to 40 μm. According to the SPAD structures, efficient shallow trench insulator and/or P-Well guard ring are used for preventing edge breakdown. Low dark count rate of about 100 Hz are expected thanks to the use of buried n-well layer and a high resistivity substrate. Each photodiode is embedded in a pixel which includes a versatile quenching circuitry and an analog output of its cathode voltage. The quenching system is configurable in four operation modes; the SPAD is disabled, the quenching is completely passive, the reset of the photodiode is active and the quenching is fully active. The architecture of the array makes possible the characterization of every single photodiode individually. The parameters to be measured for a SPAD are the breakdown avalanche voltage, the dark count rate, the dead time, the timing jitter, the photon detection probability and the after-pulsing rate.

  5. A 180-Vpp Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology

    PubMed Central

    Sun, Kexu; Gao, Zheng; Gui, Ping; Wang, Rui; Oguzman, Ismail; Xu, Xiaochen; Vasanth, Karthik; Zhou, Qifa; Shung, K. Kirk

    2015-01-01

    This brief presents a monolithically integrated fully differential linear HV amplifier as the driver of an ultrasonic transducer. The linear amplifier is capable of transmitting HV arbitrary signals with a very low harmonic distortion, which is suitable for tissue harmonic imaging and other ultrasonic modes for enhanced imaging quality. The amplifier is designed and implemented using the 0.7-μm CMOS silicon-on-insulator process with 120-V devices. The amplifier, when driving a load of 300 pF in parallel with 100 Ω, is capable of transmitting a sine-wave signal with a frequency of up to 4.4 MHz, a maximum signal swing of 180 Vpp, and a second-order harmonic distortion (HD2) of −56 dBc but only dissipating an average power of 62 mW with a 0.1% duty cycle. PMID:25914609

  6. Single event effects in static and dynamic registers in a 0.25{micro}m CMOS technology

    SciTech Connect

    Faccio, F.; Kloukinas, K.; Marchioro, A.; Calin, T.; Cosculluela, J.; Nicolaidis, M.; Velazco, R.

    1999-12-01

    The authors have studied Single Event Effects in static and dynamic registers designed in a quarter micron CMOS process. In the design, they systematically used guard rings and enclosed (edgeless) transistor geometry to improve the total dose tolerance. This design technique improved both the SEL and SEU sensitivity of the circuits. Using SPICE simulations, the measured smooth transition of the cross-section curve between LET threshold and saturation has been traced to the presence of four different upset modes, each corresponding to a different critical charge and sensitive area. A new architecture to protect the content of storage cells has been developed, and a threshold LET around 89 MeVcm{sup 2}mg{sup {minus}1} has been measured for this cell at a power supply voltage of 2 V.

  7. A 900 MHz fractional-N synthesizer for UHF transceiver in 0.18 μm CMOS technology

    NASA Astrophysics Data System (ADS)

    Xurui, Mao; Beiju, Huang; Hongda, Chen

    2014-12-01

    A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823-1061 MHz that implements 16 (24) sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip—flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 kHz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma—delta modulator is applied. When its relative frequency resolution is settled to 10-6, the testing results show that the phase noises are -120.6 dBc/Hz at 1 MHz and -95.0 dBc/Hz at 100 kHz. The chip is 2.1 mm2 in UMC 0.18 μm CMOS. The power is 36 mW at a 1.8 V supply.

  8. Integrated CMOS amplifier for ENG signal recording.

    PubMed

    Uranga, A; Navarro, X; Barniol, N

    2004-12-01

    The development and in vivo test of a fully integrated differential CMOS amplifier, implemented with standard 0.7-microm CMOS technology (one poly, two metals, self aligned twin-well CMOS process) intended to record extracellular neural signals is described. In order to minimize the flicker noise generated by the CMOS circuitry, a chopper technique has been chosen. The fabricated amplifier has a gain of 74 dB, a bandwidth of 3 kHz, an input noise of 6.6 nV/(Hz)0.5, a power dissipation of 1.3 mW, and the active area is 2.7 mm2. An ac coupling has been used to adapt the electrode to the amplifier circuitry for the in vivo testing. Compound muscle action potentials, motor unit action potentials, and compound nerve action potentials have been recorded in acute experiments with rats, in order to validate the amplifier. PMID:15605867

  9. A scalable neural chip with synaptic electronics using CMOS integrated memristors.

    PubMed

    Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

    2013-09-27

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

  10. A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

    NASA Astrophysics Data System (ADS)

    Weidong, Yang; Jiandong, Zang; Tiehu, Li; Pu, Luo; Jie, Pu; Ruitao, Zhang; Chao, Chen

    2015-10-01

    This paper presents a 16-bit 2 GSPS digital-to-analog converter (DAC) in 0.18 μm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB & INL less than ±4.3 LSB after the chip is calibrated.

  11. Search strategy for relevant parasitic elements and reduction of their influence on the operation of SC FIR filters realized in CMOS technology

    NASA Astrophysics Data System (ADS)

    Dlugosz, Rafal

    2005-06-01

    Parasitic capacities pose a serious problem in switched capacitor finite impulse response (SC FIR) filters realized as VLSI systems in CMOS submicron technologies. The influence of these parasitic elements is especially visible in the stopband of the filter frequency response. To design mixed digital-analog SC FIR filters is a difficult task. Filters of this class have to be designed using full-custom method. SC FIR filters of high orders N are very complex systems with thousands of transistors, capacitors, which, in turn, make the basis for many active elements, switches, delay elements, memories and other circuitry. One of the most important stages during the design process is post-layout HSPICE verification. However, the simulation of separated blocks does not suffice to have enough knowledge of the operation of the whole system. Optimization requires netlist simulations of the entire system, with presence of typically between 5000-30000 of parasitic capacities, where only about hundred of them are critical ones. Analysis which aims at finding these elements, in practice, is not possible because of the complexity of the entire system. The heuristic method of searching for relevant parasitic elements presented in this paper is based on the assumption that all parasitic elements create a set. The main task is to divide this set into subareas. In order to do this particular groups of nets in the layout must be labeled using unique names. Then particular groups of parasitic elements are filtered out from the netlist. Each filtering stage generates two netlists with separate areas of parasitic elements. After the analysis of the simulation results has been done there remains to make the decision concerning subsequent filtering operations. The iteration method is very quick, convenient, efficient and does not require deep knowledge of the simulated system. Many stages of this method can be easy implemented with CAD tools. In realized projects, after no more than 15

  12. CAOS-CMOS camera.

    PubMed

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

  13. CAOS-CMOS camera.

    PubMed

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems. PMID:27410361

  14. A deep-submicron single gate CMOS technology using in-situ boron-doped polycrystalline silicon-germanium gates formed by rapid thermal chemical vapor deposition

    NASA Astrophysics Data System (ADS)

    Li, Vivian Zhi-Qi

    This thesis presents a comprehensive study of in-situ boron doped polycrystalline-Sisb{1-x}Gesb{x} films deposited in a rapid thermal chemical vapor deposition system and used as the gate electrode in the deep submicron bulk CMOS technology. This work includes an investigation of the nucleation behavior of poly-Sisb{1-x}Gesb{x} films on the oxide surface, development of a deposition process using Sisb2Hsb6,\\ GeHsb4 and Bsb2Hsb6 gases in addition to using common gas mixture of SiHsb4,\\ GeHsb4 and Bsb2Hsb6 in a RTCVD system, characterization of the deposited film structure and its properties, examination of the electrical properties, extraction of the workfunction as a function of the Ge content in the film, development of the NMOS, PMOS and CMOS processes for in-situ boron doped poly-Sisb{1-x}Gesb{x} gate technology, assessment of the impact of poly-Sisb{1-x}Gesb{x} gate on the device performance through computer simulations. The process integration issues such as boron penetration, poly-depletion and gate oxide reliability, and characterization of deep submicron CMOS devices are also studied. One critical concern with the use of poly-Sisb{1-x}Gesb{x} gate materials is its partially selective deposition process on the SiOsb2. In this work, we demonstrated non-selective deposition processes for poly-Sisb{1-x}Gesb{x} without conventional Si pre-deposition onto oxide. One approach is by using in-situ boron doping method and another is by using Sisb2Hsb6 as the Si source gas. Also, it was found that the density of the nucleation sites at the initial stage of deposition increases with the increase of the Bsb2Hsb6 gas flow rate. The resulting continuous poly-Sisb{1-x}Gesb{x} films were attributed to the preferential adsorption of boron atoms onto the oxide surface providing the necessary nucleation sites for the subsequent Sisb{1-x}Gesb{x} film growth. For undoped poly-Sisb{1-x}Gesb{x} films, continuous films can be formed on the oxide using Sisb2Hsb6 and GeHsb4 gases

  15. Nanopore-CMOS Interfaces for DNA Sequencing.

    PubMed

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-01-01

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces. PMID:27509529

  16. Nanopore-CMOS Interfaces for DNA Sequencing

    PubMed Central

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-01-01

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces. PMID:27509529

  17. TOT01, a time-over-threshold based readout chip in 180nm CMOS technology for silicon strip detectors

    NASA Astrophysics Data System (ADS)

    Kasinski, K.; Szczygiel, R.; Gryboś, P.

    2011-01-01

    This work is focused on the development of the TOT01 prototype front-end ASIC for the readout of long silicon strip detectors in the STS (Silicon Tracking System) of the CBM experiment at FAIR - GSI. The deposited charge measurement is based on the Time-over-Threshold method which allows integration of a low-power ADC into each channel. The TOT01 chip comprises 30 identical channels and 1 test channel which is supplied with additional test pads. The major blocks of each channel are the CSA (charge sensitive amplifier) with two switchable constant-current discharge circuits and additional test features. The architecture of the CSA core is based on the folded cascode. The input p-channel MOSFET device, biased at a drain current 500 μA, was optimized for 30 pF detector capacitance while keeping in mind the area constraints — W/L = 1800 μm / 0.180 μm. The main advantage of this solution is high gain (GBW = 1.2 GHz) and low power consumption at the same time. The amplifier is followed by the discriminator circuit. The discriminator allows for a global (multi-channel) differential threshold setting and independent compensation for the CSA output DC-level deviations in each channel by means of a 6-bit digital to analog converter (DAC). The output pulse of this processing chain is fed through a 31:1 multiplexer structure to the output of the chip for further processing. The TOT01 chip has been fabricated in the UMC 0.18 μm CMOS process (Europractice mini@sic). It has 78 pads, measures approximately 1.5x3.2 mm2 and dissipates 33 mW. The channels have 50 μm pitch and each consumes 1.05 mW of power. The chip has been successfully tested. Charge sensitivity parameters, noise performance and first X-ray acquisitions are presented.

  18. ALDO: A radiation-tolerant, low-noise, adjustable low drop-out linear regulator in 0.35 μm CMOS technology

    NASA Astrophysics Data System (ADS)

    Carniti, P.; Cassina, L.; Gotti, C.; Maino, M.; Pessina, G.

    2016-07-01

    In this work we present ALDO, an adjustable low drop-out linear regulator designed in AMS 0.35 μm CMOS technology. It is specifically tailored for use in the upgraded LHCb RICH detector in order to improve the power supply noise for the front end readout chip (CLARO). ALDO is designed with radiation-tolerant solutions such as an all-MOS band-gap voltage reference and layout techniques aiming to make it able to operate in harsh environments like High Energy Physics accelerators. It is capable of driving up to 200 mA while keeping an adequate power supply filtering capability in a very wide frequency range from 10 Hz up to 100 MHz. This property allows us to suppress the noise and high frequency spikes that could be generated by a DC/DC regulator, for example. ALDO also shows a very low noise of 11.6 μV RMS in the same frequency range. Its output is protected with over-current and short detection circuits for a safe integration in tightly packed environments. Design solutions and measurements of the first prototype are presented.

  19. Experimental research of heavy ion and proton induced single event effects for a Bi-CMOS technology DC/DC converter

    NASA Astrophysics Data System (ADS)

    Anlin, He; Gang, Guo; Shuting, Shi; Dongjun, Shen; Jiancheng, Liu; Li, Cai; Hui, Fan

    2015-11-01

    This paper tested and analyzed heavy ion and proton induced single event effects (SEE) of a commercial DC/DC converter based on a 600 nm Bi-CMOS technology. Heavy ion induced single event transients (SET) testing has been carried out by using the Beijing HI-13 tandem accelerator at China Institute of Atomic Energy. Proton test has been carried out by using the Canadian TRIUMF proton accelerator. Both SET cross section versus linear energy transfer (LET) and proton energy has been measured. The main study conclusions are: (1) the DC/DC is both sensitive to heavy ion and proton radiations although at a pretty large feature size (600 nm), and threshold LET is about 0.06 MeV·mg/cm2 (2) heavy ion SET saturation cross section is about 5 magnitudes order larger than proton SET saturation cross section, which is consistent with the theory calculation result deduced by the RPP model and the proton nuclear reaction model; (3) on-orbit soft error rate (SER) prediction showed, on GEO orbit, proton induced SERs calculated by the heavy ion derived model are 4-5 times larger than those calculated by proton test data.

  20. Fabrication of CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Malinovich, Yacov; Koltin, Ephie; Choen, David; Shkuri, Moshe; Ben-Simon, Meir

    1999-04-01

    In order to provide its customers with sub-micron CMOS fabrication solutions for imaging applications, Tower Semiconductor initiated a project to characterize the optical parameters of Tower's 0.5-micron process. A special characterization test chip was processed using the TS50 process. The results confirmed a high quality process for optical applications. Perhaps the most important result is the process' very low dark current, of 30-50 pA/cm2, using the entire window of process. This very low dark current characteristic was confirmed for a variety of pixel architectures. Additionally, we have succeeded to reduce and virtually eliminate the white spots on large sensor arrays. As a foundry Tower needs to support fabrication of many different imaging products. Therefore we have developed a fabrication methodology that is adjusted to the special needs of optical applications. In order to establish in-line process monitoring of the optical parameters, Tower places a scribe line optical test chip that enables wafer level measurements of the most important parameters, ensuring the optical quality and repeatability of the process. We have developed complementary capabilities like in house deposition of color filter and fabrication of very large are dice using sub-micron CMOS technologies. Shellcase and Tower are currently developing a new CMOS image sensor optical package.

  1. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

    SciTech Connect

    MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

  2. New GeSi doping strategies based on P(SiH3)3 for next-generation CMOS technologies

    NASA Astrophysics Data System (ADS)

    Chizmeshya, Andrew; Xu, Chi; Gallagher, James; Sims, Patrick; Smith, David; Menendez, Jose; Kouvetakis, John

    2015-03-01

    GeSi n-type films are synthesized using the specially designed hydrides P(SiH3)3 , Ge3H8andGe4H10 for applications in next-generation CMOS technologies. The films are grown on Ge-buffered Si(100) at 340 °C using two methods. The first employs a gas-source molecular epitaxy approach and Ge4H10 to yield films with P doping densities up to 3.5 x 1019/cm3. The amount of Si incorporated equals or exceeds the 3:1 ratio in the P(SiH3)3 compound. The second approach applies an ultra-high vacuum chemical vapor deposition technique and Ge3H8 in place of Ge4H10 to achieve higher carrier concentrations up to 6 x 1019/cm3. The Si:P ratio in this case is well below the 3:1 value expected from the precursor. The electron mobilities for both types of samples are significantly higher than state-of-the-art prototypes, probably due to superior microstructure and dearth of inactive donors. The relative stability of Si-P and Ge-P bonds in a Ge matrix is studied with ab initio methods. P - I - N diodes fabricated using P(SiH3)3 show excellent I- V characteristics that are virtually undistinguishable from similar diodes doped with the P(GeH3)3 precursor. These results confirm P(SiH3)3 as a viable doping source that is practical from a process standpoint and therefore attractive for industrial scale-up. Work supported by NSF-SusChEM Award DMR-1309090.

  3. Advanced microlens and color filter process technology for the high-efficiency CMOS and CCD image sensors

    NASA Astrophysics Data System (ADS)

    Fan, Yang-Tung; Peng, Chiou-Shian; Chu, Cheng-Yu

    2000-12-01

    New markets are emerging for digital electronic image device, especially in visual communications, PC camera, mobile/cell phone, security system, toys, vehicle image system and computer peripherals for document capture. To enable one-chip image system that image sensor is with a full digital interface, can make image capture devices in our daily lives. Adding a color filter to such image sensor in a pattern of mosaics pixel or wide stripes can make image more real and colorful. We can say 'color filter makes the life more colorful color filter is? Color filter means can filter image light source except the color with specific wavelength and transmittance that is same as color filter itself. Color filter process is coating and patterning green, red and blue (or cyan, magenta and yellow) mosaic resists onto matched pixel in image sensing array pixels. According to the signal caught from each pixel, we can figure out the environment image picture. Widely use of digital electronic camera and multimedia applications today makes the feature of color filter becoming bright. Although it has challenge but it is very worthy to develop the process of color filter. We provide the best service on shorter cycle time, excellent color quality, high and stable yield. The key issues of advanced color process have to be solved and implemented are planarization and micro-lens technology. Lost of key points of color filter process technology have to consider will also be described in this paper.

  4. Cryogenic Lifetime Studies of 130 nm and 65 nm CMOS Technologies for High-Energy Physics Experiments

    SciTech Connect

    Hoff, James R.; Deptuch, G. W.; Wu, Guoying; Gui, Ping

    2015-06-04

    The Long Baseline Neutrino Facility intends to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. Research is under way to place the electronics inside the cryostat. For reasons of efficiency and economics, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This, then, requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130 nm and 65 nm nMOS transistors operating at cryogenic temperatures are investigated. Our results show that both technologies achieve the lifetimes required by the experiment. Minimal design changes are necessary in the case of the 130 nm process and no changes whatsoever are necessary for the 65 nm process.

  5. In-line charge-trapping characterization of dielectrics for sub-0.5-um CMOS technologies

    NASA Astrophysics Data System (ADS)

    Roy, Pradip K.; Chacon, Carlos M.; Ma, Yi; Horner, Gregory

    1997-09-01

    The advent of ultra-large and giga-scale-integration (ULSI/GSI) has placed considerable emphasis on the development of new gate oxides and interlevel dielectrics capable of meeting strict performance and reliability requirements. The costs and demands associated with ULSI fabrication have in turn fueled the need for cost-effective, rapid and accurate in-line characterization techniques for evaluating dielectric quality. The use of non-contact surface photovoltage characterization techniques provides cost-effective rapid feedback on dielectric quality, reducing costs through the reutilization of control wafers and the elimination of processing time. This technology has been applied to characterize most of the relevant C-V parameters, including flatband voltage (Vfb), density of interface traps (Dit), mobile charge density (Qm), oxide thickness (Tox), oxide resistivity (pox) and total charge (Qtot) for gate and interlevel (ILO) oxides. A novel method of measuring tunneling voltage by this technique on various gate oxides is discussed. For ILO, PECVD and high density plasma dielectrics, surface voltage maps are also presented. Measurements of near-surface silicon quality are described, including minority carrier generation lifetime, and examples of their application in diagnosing manufacturing problems.

  6. Fundamentals and technology for monolithically integrated RF MEMS switches with ultra-nanocrystaline diamond dielectric/CMOS devices.

    SciTech Connect

    Auciello, O.; Sumant, A.; Goldsmith, C.; O'Brien, S.; Sampath, S.; Gudeman, C; Wang, W.; Hwang, J.; Swonger, J.; Carlisle, J.; Balachandran, S.; MEMtronics Corp.; Innovative Micro Technology; Lehigh Univ.; Peregrine Semiconductor; Advanced Diamond Technologies

    2010-01-01

    Most current capacitive RF-MEMS switch technology is based on conventional dielectric materials such as SiO{sub 2} and Si{sub 3}N{sub 4}. However, they suffer not only from charging problems but also stiction problems leading to premature failure of an RF-MEMS switch. Ultrananocrystalline diamond (UNCD{sup (R)}) (2-5 nm grains) and nanocrystalline diamond (NCD) (10-100 nm grains) films exhibit one of the highest Young's modulus ({approx} 980-1100 GPa) and demonstrated MEMS resonators with the highest quality factor (Q {ge} 10,000 in air for NCD) today, they also exhibit the lowest force of adhesion among MEMS/NEMS materials ({approx}10 mJ/m{sup 2}-close to van der Waals attractive force for UNCD) demonstrated today. Finally, UNCD exhibits dielectric properties (fast discharge) superior to those of Si and SiO{sub 2}, as shown in this paper. Thus, UNCD and NCD films provide promising platform materials beyond Si for a new generation of important classes of high-performance MEMS/NEMS devices.

  7. Low energy CMOS for space applications

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Alkalaj, Leon

    1992-01-01

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  8. All-CMOS night vision viewer with integrated microdisplay

    NASA Astrophysics Data System (ADS)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  9. Design of a 10-bit segmented current-steering digital-to-analog converter in CMOS 65 nm technology for the bias of new generation readout chips in high radiation environment

    NASA Astrophysics Data System (ADS)

    De Robertis, G.; Loddo, F.; Mattiazzo, S.; Pacher, L.; Pantano, D.; Tamma, C.

    2016-01-01

    A new pixel front end chip for HL-LHC experiments in CMOS 65nm technology is under development by the CERN RD53 collaboration together with the Chipix65 INFN project. This work describes the design of a 10-bit segmented current-steering Digital-to-Analog Converter (DAC) to provide a programmable bias current to the analog blocks of the circuit. The main requirements are monotonicity, good linearity, limited area consumption and radiation hardness up to 10 MGy. The DAC was prototyped and electrically tested, while irradiation tests will be performed in Autumn 2015.

  10. Hematite nanoparticles larger than 90 nm show no sign of toxicity in terms of lactate dehydrogenase release, nitric oxide generation, apoptosis, and comet assay in murine alveolar macrophages and human lung epithelial cells.

    PubMed

    Freyria, Francesca Stefania; Bonelli, Barbara; Tomatis, Maura; Ghiazza, Mara; Gazzano, Elena; Ghigo, Dario; Garrone, Edoardo; Fubini, Bice

    2012-04-16

    Three hematite samples were synthesized by precipitation from a FeCl₃ solution under controlled pH and temperature conditions in different morphology and dimensions: (i) microsized (average diameter 1.2 μm); (ii) submicrosized (250 nm); and (iii) nanosized (90 nm). To gain insight into reactions potentially occurring in vivo at the particle-lung interface following dust inhalation, several physicochemical features relevant to pathogenicity were measured (free radical generation in cell-free tests, metal release, and antioxidant depletion), and cellular toxicity assays on human lung epithelial cells (A549) and murine alveolar macrophages (MH-S) were carried out (LDH release, apoptosis detection, DNA damage, and nitric oxide synthesis). The decrease in particles size, from 1.2 μm to 90 nm, only caused a slight increase in structural defects (disorder of the hematite phase and the presence of surface ferrous ions) without enhancing surface reactivity or cellular responses in the concentration range between 20 and 100 μg cm⁻².

  11. Hematite nanoparticles larger than 90 nm show no sign of toxicity in terms of lactate dehydrogenase release, nitric oxide generation, apoptosis, and comet assay in murine alveolar macrophages and human lung epithelial cells.

    PubMed

    Freyria, Francesca Stefania; Bonelli, Barbara; Tomatis, Maura; Ghiazza, Mara; Gazzano, Elena; Ghigo, Dario; Garrone, Edoardo; Fubini, Bice

    2012-04-16

    Three hematite samples were synthesized by precipitation from a FeCl₃ solution under controlled pH and temperature conditions in different morphology and dimensions: (i) microsized (average diameter 1.2 μm); (ii) submicrosized (250 nm); and (iii) nanosized (90 nm). To gain insight into reactions potentially occurring in vivo at the particle-lung interface following dust inhalation, several physicochemical features relevant to pathogenicity were measured (free radical generation in cell-free tests, metal release, and antioxidant depletion), and cellular toxicity assays on human lung epithelial cells (A549) and murine alveolar macrophages (MH-S) were carried out (LDH release, apoptosis detection, DNA damage, and nitric oxide synthesis). The decrease in particles size, from 1.2 μm to 90 nm, only caused a slight increase in structural defects (disorder of the hematite phase and the presence of surface ferrous ions) without enhancing surface reactivity or cellular responses in the concentration range between 20 and 100 μg cm⁻². PMID:22324577

  12. Ultra low power CMOS technology

    NASA Technical Reports Server (NTRS)

    Burr, J.; Peterson, A.

    1991-01-01

    This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very large neural networks, energy optimization metrics and their impact on system design, modeling problems, circuit design constraints, possible fabrication process modifications to improve performance, and barriers to practical implementation.

  13. A monolithically integrated torsional CMOS-MEMS relay

    NASA Astrophysics Data System (ADS)

    Riverola, M.; Sobreviela, G.; Torres, F.; Uranga, A.; Barniol, N.

    2016-11-01

    We report experimental demonstrations of a torsional microelectromechanical (MEM) relay fabricated using the CMOS-MEMS approach (or intra-CMOS) which exploits the full foundry inherent characteristics enabling drastic reduction of the fabrication costs and batch production. In particular, the relay is monolithically integrated in the back end of line of a commercial standard CMOS technology (AMS 0.35 μm) and released by means of a simple one-step mask-less wet etching. The fabricated torsional relay exhibits an extremely steep switching behaviour symmetrical about both contact sides with an on-state contact resistance in the k Ω -range throughout the on-off cycling test.

  14. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    PubMed

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  15. Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications

    PubMed Central

    Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

    2012-01-01

    One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

  16. Cmos spdt switch for wlan applications

    NASA Astrophysics Data System (ADS)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  17. Advanced CMOS Radiation Effects Testing Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  18. Advanced CMOS Radiation Effects Testing and Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  19. A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Siyuan, He; Changhong, Zhang; Liang, Tao; Weifeng, Zhang; Longyue, Zeng; Wei, Lü; Haijun, Wu

    2013-03-01

    A CMOS long-term evolution (LTE) direct convert receiver that eliminates the interstage SAW filter is presented. The receiver consists of a low noise variable gain transconductance amplifier (TCA), a quadrature passive current commutating mixer with a 25% duty-cycle LO, a trans-impedance amplifier (TIA), a 7th-order Chebyshev filter and programmable gain amplifiers (PGAs). A wide dynamic gain range is allocated in the RF and analog parts. A current commutating passive mixer with a 25% duty-cycle LO improves gain, noise, and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference. Fabricated in a 0.13 μm CMOS process, the receiver chain achieves a 107 dB maximum voltage gain, 2.7 dB DSB NF (from PAD port), -11 dBm IIP3, and > +65 dBm IIP2 after calibration, 96 dB dynamic control range with 1 dB steps, less than 2% error vector magnitude (EVM) from 2.3 to 2.7 GHz. The total receiver (total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

  20. Performance of capacitively coupled active pixel sensors in 180 nm HV-CMOS technology after irradiation to HL-LHC fluences

    NASA Astrophysics Data System (ADS)

    Feigl, S.

    2014-03-01

    In this ATLAS upgrade R&D project, we explore the concept of using a deep-submicron HV-CMOS process to produce a drop-in replacement for traditional radiation-hard silicon sensors. Such active sensors contain simple circuits, e.g. amplifiers and discriminators, but still require a traditional (pixel or strip) readout chip. This approach yields most advantages of MAPS (improved resolution, reduced cost and material budget, etc.), without the complication of full integration on a single chip. After outlining the basic design of the HV2FEI4 test ASIC, results after irradiation with X-rays to 862 Mrad and neutrons up to 1016(1 MeV neq)/cm2 will be presented. Finally, a brief outlook on further development plans is given.

  1. Design of embedded SCR device to improve ESD robustness of stacked-device output driver in low-voltage CMOS technology

    NASA Astrophysics Data System (ADS)

    Lin, Chun-Yu; Chiu, Yan-Lian

    2016-10-01

    This study proposes a novel design for an embedded silicon-controlled rectifier (SCR) device to improve the electrostatic discharge (ESD) robustness of a stacked-device output driver. A 3 × VDD-tolerant stacked-device output driver with embedded SCR is demonstrated using a 0.18 μm CMOS process with VDD of 3.3 V. This design is verified in a silicon chip, and it is shown that the proposed output driver with embedded SCR can deliver an output voltage of 3 × VDD. The ESD robustness can be improved without the use of any additional ESD protection device or layout area. Furthermore, the proposed design can also be used for an n × VDD-tolerant stacked-device output driver to improve its ESD robustness.

  2. Surface enhanced biodetection on a CMOS biosensor chip

    NASA Astrophysics Data System (ADS)

    Belloni, Federico; Sandeau, Laure; Contié, Sylvain; Vicaire, Florence; Owens, Roisin; Rigneault, Hervé

    2012-03-01

    We present a rigorous electromagnetic theory of the electromagnetic power emitted by a dipole located in the vicinity of a multilayer stack. We applied this formalism to a luminescent molecule attached to a CMOS photodiode surface and report light collection efficiency larger than 80% toward the CMOS silicon substrate. We applied this result to the development of a low-cost, simple, portable device based on CMOS photodiodes technology for the detection and quantification of biological targets through light detection, presenting high sensitivity, multiplex ability, and fast data processing. The key feature of our approach is to perform the analytical test directly on the CMOS sensor surface, improving dramatically the optical detection of the molecule emitted light into the high refractive index semiconductor CMOS material. Based on adequate surface chemistry modifications, probe spotting and micro-fluidics, we performed proof-of-concept bio-assays directed against typical immuno-markers (TNF-α and IFN-γ). We compared the developed CMOS chip with a commercial micro-plate reader and found similar intrinsic sensitivities in the pg/ml range.

  3. CMOS Monolithic Active Pixel Sensors (MAPS): Developments and future outlook

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; Fant, A.; Gasiorek, P.; Esbrand, C.; Griffiths, J. A.; Metaxas, M. G.; Royle, G. J.; Speller, R.; Venanzi, C.; van der Stelt, P. F.; Verheij, H.; Li, G.; Theodoridis, S.; Georgiou, H.; Cavouras, D.; Hall, G.; Noy, M.; Jones, J.; Leaver, J.; Machin, D.; Greenwood, S.; Khaleeq, M.; Schulerud, H.; Østby, J. M.; Triantis, F.; Asimidis, A.; Bolanakis, D.; Manthos, N.; Longo, R.; Bergamaschi, A.

    2007-12-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end applications, for example web-cams, and is slowly pervading the high-end applications, for example in prosumer digital cameras. Higher specifications are required for scientific applications: very low noise, high speed, high dynamic range, large format and radiation hardness are some of these requirements. This paper will present a brief overview of the CMOS Image Sensor technology and of the requirements for scientific applications. As an example, a sensor for X-ray imaging will be presented. This sensor was developed within a European FP6 Consortium, intelligent imaging sensors (I-ImaS).

  4. Regenerative switching CMOS system

    DOEpatents

    Welch, James D.

    1998-01-01

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

  5. Regenerative switching CMOS system

    DOEpatents

    Welch, J.D.

    1998-06-02

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

  6. CMOS IC fault models, physical defect coverage, and I sub DDQ testing

    SciTech Connect

    Fritzemeier, R.R.; Soden, J.M. ); Hawkins, C.F. . Dept. of Electrical and Computer Engineering)

    1991-01-01

    The development of the stuck-at fault (SAF) model is reviewed with emphasis on its relationship to CMOS integrated circuit (IC) technologies. The ability of the SAF model to represent common physical defects in CMOS ICs is evaluated. A test strategy for defect detection, which includes I{sub DDQ} testing is presented. 16 refs., 4 figs.

  7. CMOS-compatible photonic devices for single-photon generation

    NASA Astrophysics Data System (ADS)

    Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

    2016-09-01

    Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  8. Single photon detection and localization accuracy with an ebCMOS camera

    NASA Astrophysics Data System (ADS)

    Cajgfinger, T.; Dominjon, A.; Barbier, R.

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 μm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  9. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    PubMed Central

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  10. Improved Space Object Observation Techniques Using CMOS Detectors

    NASA Astrophysics Data System (ADS)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  11. Development and characterization of CMOS avalanche photodiode arrays

    NASA Astrophysics Data System (ADS)

    Lawrence, William G.; Christian, James F.; Augustine, Frank L.; Squillante, Michael R.; Entine, Gerald

    2005-04-01

    Avalanche photodiode (APD) arrays fabricated by using complementary metal-oxide-semiconductor (CMOS) fabrication technology offer the possibility of combining these high sensitivity detectors with cost effective, on-board, complementary circuitry. Using CMOS techniques, Radiation Monitoring Devices has developed prototype pixels with active diameters ranging from 5 to 60 microns and with measured quantum efficiencies of up to 65%. The prototype CMOS APD pixel designs support both proportional and Geiger modes of photo-detection. When operating in Geiger mode, these APD"s act as single-optical-photon-counting detectors that can be used for time-resolved measurements under signal-starved conditions. We have also designed and fabricated CMOS chips that contain not only the APD pixels, but also associated circuitry for both actively and passively quenching the self-propagating Geiger avalanche. This report presents the noise and timing performance for the prototype CMOS APD pixels in both the proportional and Geiger modes of operation. It compares the quantum efficiency and dark-count rate of different pixel designs as a function of the applied bias and presents a discussion of the maximum count rates that is obtained with each of the two types of quenching circuits for operating the pixel in Geiger mode. Preliminary data on the application of the APD pixels to laser ranging and fluorescent lifetime measurement is also presented.

  12. A CMOS humidity sensor for passive RFID sensing applications.

    PubMed

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  13. A CMOS humidity sensor for passive RFID sensing applications.

    PubMed

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-05-16

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

  14. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  15. Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction

    PubMed Central

    Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

    2015-01-01

    A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology. PMID:26184222

  16. Closed-loop adaptive optics using a CMOS image quality metric sensor

    NASA Astrophysics Data System (ADS)

    Ting, Chueh; Rayankula, Aditya; Giles, Michael K.; Furth, Paul M.

    2006-08-01

    When compared to a Shack-Hartmann sensor, a CMOS image sharpness sensor has the advantage of reduced complexity in a closed-loop adaptive optics system. It also has the potential to be implemented as a smart sensor using VLSI technology. In this paper, we present a novel adaptive optics testbed that uses a CMOS sharpness imager built in the New Mexico State University (NMSU) Electro-Optics Research Laboratory (EORL). The adaptive optics testbed, which includes a CMOS image quality metric sensor and a 37-channel deformable mirror, has the capability to rapidly compensate higher-order phase aberrations. An experimental performance comparison of the pinhole image sharpness feedback method and the CMOS imager is presented. The experimental data shows that the CMOS sharpness imager works well in a closed-loop adaptive optics system. Its overall performance is better than that of the pinhole method, and it has a fast response time.

  17. Large area CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; Guerrini, N.; Sedgwick, I.

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  18. Research-grade CMOS image sensors for remote sensing applications

    NASA Astrophysics Data System (ADS)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

    2004-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

  19. Research-grade CMOS image sensors for demanding space applications

    NASA Astrophysics Data System (ADS)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2004-06-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  20. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    NASA Astrophysics Data System (ADS)

    Benoit, M.; Bilbao de Mendizabal, J.; Casse, G.; Chen, H.; Chen, K.; Di Bello, F. A.; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Lanni, F.; Liu, H.; Meloni, F.; Meng, L.; Miucci, A.; Muenstermann, D.; Nessi, M.; Perić, I.; Rimoldi, M.; Ristic, B.; Barrero Pinto, M. Vicente; Vossebeld, J.; Weber, M.; Wu, W.; Xu, L.

    2016-07-01

    Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  1. CMOS Integrated Carbon Nanotube Sensor

    SciTech Connect

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-05-23

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  2. Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

    NASA Technical Reports Server (NTRS)

    White, Mark; Cooper, Mark; Johnston, Allan

    2011-01-01

    Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

  3. TID Simulation of Advanced CMOS Devices for Space Applications

    NASA Astrophysics Data System (ADS)

    Sajid, Muhammad

    2016-07-01

    This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

  4. Optical and noise performance of CMOS solid-state photomultipliers

    NASA Astrophysics Data System (ADS)

    Chen, Xiao Jie; Johnson, Erik B.; Staples, Christopher J.; Chapman, Eric; Alberghini, Guy; Christian, James F.

    2010-08-01

    Solid-state photomultipliers (SSPM) are photodetectors composed of avalanche photodiode pixel arrays operating in Geiger mode (biased above diode breakdown voltage). They are built using CMOS technology and can be used in a variety of applications in high energy and nuclear physics, medical imaging and homeland security related areas. The high gain and low cost associated with the SSPM makes it an attractive alternative to existing photodetectors such as the photomultiplier tube (PMT). The capability of integrating CMOS on-chip readout circuitry on the same substrate as the SSPM also provides a compact and low-power-consumption solution to photodetector applications with stringent area and power requirements. The optical performance of the SSPM, specifically the detection and quantum efficiencies, can depend on the geometry and the doping profile associated with each photodiode pixel. The noise associated with the SSPM not only includes dark noise from each pixel, but also consists of excess noise terms due to after pulsing and inter-pixel cross talk. The magnitude of the excess noise terms can depend on biasing conditions, temperature, as well as pixel and inter-pixel dimensions. We present the optical and noise performance of SSPMs fabricated in a conventional CMOS process, and demonstrate the dependence of the SSPM performance on pixel/inter-pixel geometry, doping profile, temperature, as well as bias conditions. The continuing development of CMOS SSPM technology demonstrated here shows that low cost and high performance solid state photodetectors are viable solutions for many existing and future optical detection applications.

  5. Monolithic CMOS imaging x-ray spectrometers

    NASA Astrophysics Data System (ADS)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

  6. Development of CMOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  7. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    PubMed

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

  8. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    PubMed Central

    Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

    2014-01-01

    Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

  9. Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

    PubMed

    Kazior, Thomas E

    2014-03-28

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  10. Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

    PubMed Central

    Kazior, Thomas E.

    2014-01-01

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  11. Design and coupled-effect simulations of CMOS micro gas sensors built on SOI thin membranes

    NASA Astrophysics Data System (ADS)

    Lu, Chih-Cheng; Udrea, Florin; Gardner, Julian W.; Setiadi, D.; Dogaru, T.; Tsai, T. H.; Covington, James A.

    2001-04-01

    This paper describes coupled-effect simulations of smart micro gas-sensors based on standard BiCMOS technology. The smart sensor features very low power consumption, high sensitivity and potential low fabrication cost achieved through full CMOS integration. For the first time the micro heaters are made of active CMOS elements (i.e. MOSFET transistors) and embedded in a thin SOI membrane consisting of Si and SiO2 thin layers. Micro gas-sensors such as chemoresistive, microcalorimeteric and Pd/polymer gate FET sensors can be made using this technology. Full numerical analyses including 3D electro- thermo-mechanical simulations, in particular stress and deflection studies on the SOI membranes are presented. The transducer circuit design and the post-CMOS fabrication process, which includes single sided back-etching, are also reported.

  12. Planar CMOS analog SiPMs: design, modeling, and characterization

    NASA Astrophysics Data System (ADS)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-11-01

    Silicon photomultipliers (SiPMs) are large area detectors consisting of an array of single-photon-sensitive microcells, which make SiPMs extremely attractive to substitute the photomultiplier tubes in many applications. We present the design, fabrication, and characterization of analog SiPMs in standard planar 0.35 μm CMOS technology, with about 1 mm × 1 mm total area and different kinds of microcells, based on single-photon avalanche diodes with 30 μm diameter reaching 21.0% fill-factor (FF), 50 μm diameter (FF = 58.3%) or 50 μm square active area with rounded corner of 5 μm radius (FF = 73.7%). We also developed the electrical SPICE model for CMOS SiPMs. Our CMOS SiPMs have 25 V breakdown voltage, in line with most commercial SiPMs and higher gain (8.8 × 106, 13.2 × 106, and 15.0 × 106, respectively). Although dark count rate density is slightly higher than state-of-the-art analog SiPMs, the proposed standard CMOS processing opens the feasibility of integration with active electronics, for switching hot pixels off, drastically reducing the overall dark count rate, or for further on-chip processing.

  13. Performance of CMOS ternary full adder at liquid nitrogen temperature

    NASA Astrophysics Data System (ADS)

    Srivastava, A.; Venkatapathy, K.

    We have designed, implemented and studied the performance at liquid nitrogen temperature (77 K) of a CMOS ternary full adder and its building blocks, the simple ternary inverter (STI), positive ternary inverter (PTI) and negative ternary inverter (NTI), and compared the corresponding performance at room temperature (300 K). The ternary full adder has been fabricated in 2 μm, n-well CMOS through MOSIS. In a ternary full adder, the basic building blocks, the PTI and NTI, have been developed using combinations of a CMOS inverter and transmission gate(s). There is close agreement between the simulated and measured voltage transfer characteristics and noise margins of ternary-valued devices. The measured transient times for the NTI, PTI and ternary full adder at 77 K show an improvement by a factor of ≈1.5-2.5 over the corresponding values at 300 K. The present design does not use linear resistors and depletion-mode MOSFETs to implement the ternary full adder and its building blocks, and is fully compatible with current CMOS technology.

  14. Hybrid CMOS SiPIN detectors as astronomical imagers

    NASA Astrophysics Data System (ADS)

    Simms, Lance Michael

    Charge Coupled Devices (CCDs) have dominated optical and x-ray astronomy since their inception in 1969. Only recently, through improvements in design and fabrication methods, have imagers that use Complimentary Metal Oxide Semiconductor (CMOS) technology gained ground on CCDs in scientific imaging. We are now in the midst of an era where astronomers might begin to design optical telescope cameras that employ CMOS imagers. The first three chapters of this dissertation are primarily composed of introductory material. In them, we discuss the potential advantages that CMOS imagers offer over CCDs in astronomical applications. We compare the two technologies in terms of the standard metrics used to evaluate and compare scientific imagers: dark current, read noise, linearity, etc. We also discuss novel features of CMOS devices and the benefits they offer to astronomy. In particular, we focus on a specific kind of hybrid CMOS sensor that uses Silicon PIN photodiodes to detect optical light in order to overcome deficiencies of commercial CMOS sensors. The remaining four chapters focus on a specific type of hybrid CMOS Silicon PIN sensor: the Teledyne Hybrid Visible Silicon PIN Imager (HyViSI). In chapters four and five, results from testing HyViSI detectors in the laboratory and at the Kitt Peak 2.1m telescope are presented. We present our laboratory measurements of the standard detector metrics for a number of HyViSI devices, ranging from 1k×1k to 4k×4k format. We also include a description of the SIDECAR readout circuit that was used to control the detectors. We then show how they performed at the telescope in terms of photometry, astrometry, variability measurement, and telescope focusing and guiding. Lastly, in the final two chapters we present results on detector artifacts such as pixel crosstalk, electronic crosstalk, and image persistence. One form of pixel crosstalk that has not been discussed elsewhere in the literature, which we refer to as Interpixel Charge

  15. Multi-physics modelling contributions to investigate the atmospheric cosmic rays on the single event upset sensitivity along the scaling trend of CMOS technologies.

    PubMed

    Hubert, G; Regis, D; Cheminet, A; Gatti, M; Lacoste, V

    2014-10-01

    Particles originating from primary cosmic radiation, which hit the Earth's atmosphere give rise to a complex field of secondary particles. These particles include neutrons, protons, muons, pions, etc. Since the 1980s it has been known that terrestrial cosmic rays can penetrate the natural shielding of buildings, equipment and circuit package and induce soft errors in integrated circuits. Recently, research has shown that commercial static random access memories are now so small and sufficiently sensitive that single event upsets (SEUs) may be induced from the electronic stopping of a proton. With continued advancements in process size, this downward trend in sensitivity is expected to continue. Then, muon soft errors have been predicted for nano-electronics. This paper describes the effects in the specific cases such as neutron-, proton- and muon-induced SEU observed in complementary metal-oxide semiconductor. The results will allow investigating the technology node sensitivity along the scaling trend.

  16. Multi-physics modelling contributions to investigate the atmospheric cosmic rays on the single event upset sensitivity along the scaling trend of CMOS technologies.

    PubMed

    Hubert, G; Regis, D; Cheminet, A; Gatti, M; Lacoste, V

    2014-10-01

    Particles originating from primary cosmic radiation, which hit the Earth's atmosphere give rise to a complex field of secondary particles. These particles include neutrons, protons, muons, pions, etc. Since the 1980s it has been known that terrestrial cosmic rays can penetrate the natural shielding of buildings, equipment and circuit package and induce soft errors in integrated circuits. Recently, research has shown that commercial static random access memories are now so small and sufficiently sensitive that single event upsets (SEUs) may be induced from the electronic stopping of a proton. With continued advancements in process size, this downward trend in sensitivity is expected to continue. Then, muon soft errors have been predicted for nano-electronics. This paper describes the effects in the specific cases such as neutron-, proton- and muon-induced SEU observed in complementary metal-oxide semiconductor. The results will allow investigating the technology node sensitivity along the scaling trend. PMID:24500239

  17. A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

    NASA Astrophysics Data System (ADS)

    Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

    2013-03-01

    Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

  18. High-voltage CMOS detectors

    NASA Astrophysics Data System (ADS)

    Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

    2016-07-01

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented.

  19. CMOS output buffer wave shaper

    NASA Technical Reports Server (NTRS)

    Albertson, L.; Whitaker, S.; Merrell, R.

    1990-01-01

    As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. A design technique which aids in the reduction of switching noise is reported. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driver stage. A test circuit based on these techniques is being submitted to MOSIS for fabrication.

  20. Using CMOS image sensors to detect photons

    NASA Astrophysics Data System (ADS)

    Xu, Chenzhi; Tong, Xiaobo; Zhou, Xiang; Zheng, Xiaodong; Xu, Yunfei

    2010-05-01

    A research is carried out on the characteristics of CMOS (Complementary Metal-Oxide Semiconductor) image sensors. A CMOS image sensor is used to probe the fluorescence intensity of atoms or absorbed photons in order to measure the shape and atomicity density of Rb (Rubidium) cold-atom-cloud. A series of RGB data of images is obtained and the spectrum response curve of CMOS image sensor is deduced. After filtering out the noise of the pixel signals of CMOS image sensor, the number of photons received by every pixel of the CMOS image sensor is obtained. Compared with CCD camera, the CMOS image sensor has some advantages in measuring the properties of cold-atom-cloud,such as quick response, large sensory area, low cost, and so on.

  1. A BiCMOS integrated charge to amplitude converter

    SciTech Connect

    Gallin-Martel, L.; Pouxe, J.; Rossetto, O.

    1996-12-31

    This paper describes a fast two channel gated charge to amplitude converter (QAC) which has been designed with the 1.2 {mu}m BiCMOS technology from AMS (Austria Mikro Systeme). It can integrate fast negative impulse currents up to 100 mA. Associated with an audio 18 bit low cost ADC, it can easily be used to make a 12 to 13 bit QDC. The problems of current to current conversion, pedestal and offset stability are discussed.

  2. A novel multi-actuation CMOS RF MEMS switch

    NASA Astrophysics Data System (ADS)

    Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

    2008-12-01

    This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

  3. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

    SciTech Connect

    Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

    2008-08-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

  4. A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

    PubMed Central

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

  5. Improved Space Object Orbit Determination Using CMOS Detectors

    NASA Astrophysics Data System (ADS)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  6. Multiband CMOS sensor simplify FPA design

    NASA Astrophysics Data System (ADS)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  7. Fundamental performance differences between CMOS and CCD imagers: Part II

    NASA Astrophysics Data System (ADS)

    Janesick, James; Andrews, James; Tower, John; Grygon, Mark; Elliott, Tom; Cheng, John; Lesser, Michael; Pinter, Jeff

    2007-09-01

    A new class of CMOS imagers that compete with scientific CCDs is presented. The sensors are based on deep depletion backside illuminated technology to achieve high near infrared quantum efficiency and low pixel cross-talk. The imagers deliver very low read noise suitable for single photon counting - Fano-noise limited soft x-ray applications. Digital correlated double sampling signal processing necessary to achieve low read noise performance is analyzed and demonstrated for CMOS use. Detailed experimental data products generated by different pixel architectures (notably 3TPPD, 5TPPD and 6TPG designs) are presented including read noise, charge capacity, dynamic range, quantum efficiency, charge collection and transfer efficiency and dark current generation. Radiation damage data taken for the imagers is also reported.

  8. Micromachined high-performance RF passives in CMOS substrate

    NASA Astrophysics Data System (ADS)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-11-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications.

  9. Smart CMOS image sensor for lightning detection and imaging.

    PubMed

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-03-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach.

  10. Nanosecond monolithic CMOS readout cell

    DOEpatents

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  11. CMOS foveal image sensor chip

    NASA Technical Reports Server (NTRS)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  12. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    NASA Astrophysics Data System (ADS)

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  13. Accelerated life testing effects on CMOS microcircuit characteristics

    NASA Technical Reports Server (NTRS)

    1977-01-01

    Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

  14. CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

    NASA Astrophysics Data System (ADS)

    Davidson, Bradley Darren

    This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different

  15. CMOS Active Pixel Sensor (APS) Imager for Scientific Applications

    NASA Astrophysics Data System (ADS)

    Ay, Suat U.; Lesser, Michael P.; Fossum, Eric R.

    2002-12-01

    A 512×512 CMOS Active Pixel Sensor (APS) imager has been designed, fabricate, and tested for frontside illumination suitable for use in astronomy specifically in telescope guider systems as a replacement of CCD chips. The imager features a high-speed differential analog readout, 15 μm pixel pitch, 75 % fill factor (FF), 62 dB dynamic range, 315Ke- pixel capacity, less than 0.25% fixed pattern noise (FPN), 45 dB signal to noise ratio (SNR) and frame rate of up to 40 FPS. Design was implemented in a standard 0.5 μm CMOS process technology consuming less than 200mWatts on a single 5 Volt power supply. CMOS Active Pixel Sensor (APS) imager was developed with pixel structure suitable for both frontside and backside illumination holding large number of electron in relatively small pixel pitch of 15 μm. High-speed readout and signal processing circuits were designed to achieve low fixed pattern noise (FPN) and non-uniformity to provide CCD-like analog outputs. Target spectrum range of operation for the imager is in near ultraviolet (300-400 nm) with high quantum efficiency. This device is going to be used as a test vehicle to develop backside-thinning process.

  16. An integrated CMOS detection system for optical short-pulse

    NASA Astrophysics Data System (ADS)

    Kim, Chang-Gun; Hong, Nam-Pyo; Choi, Young-Wan

    2014-03-01

    We present design of a front-end readout system consisting of charge sensitive amplifier (CSA) and pulse shaper for detection of stochastic and ultra-small semiconductor scintillator signal. The semiconductor scintillator is double sided silicon detector (DSSD) or avalanche photo detector (APD) for high resolution and peak signal reliability of γ-ray or X-ray spectroscopy. Such system commonly uses low noise multichannel CSA. Each CSA in multichannel includes continuous reset system based on tens of MΩ and charge-integrating capacitor in feedback loop. The high value feedback resistor requires large area and huge power consumption for integrated circuits. In this paper, we analyze these problems and propose a CMOS short pulse detection system with a novel CSA. The novel CSA is composed of continuous reset system with combination of diode connected PMOS and 100 fF. This structure has linearity with increased input charge quantity from tens of femto-coulomb to pico-coulomb. Also, the front-end readout system includes both slow and fast shapers for detecting CSA output and preventing pile-up distortion. Shaping times of fast and slow shapers are 150 ns and 1.4 μs, respectively. Simulation results of the CMOS detection system for optical short-pulse implemented in 0.18 μm CMOS technology are presented.

  17. Spectrometry with consumer-quality CMOS cameras.

    PubMed

    Scheeline, Alexander

    2015-01-01

    Many modern spectrometric instruments use diode arrays, charge-coupled arrays, or CMOS cameras for detection and measurement. As portable or point-of-use instruments are desirable, one would expect that instruments using the cameras in cellular telephones and tablet computers would be the basis of numerous instruments. However, no mass market for such devices has yet developed. The difficulties in using megapixel CMOS cameras for scientific measurements are discussed, and promising avenues for instrument development reviewed. Inexpensive alternatives to use of the built-in camera are also mentioned, as the long-term question is whether it is better to overcome the constraints of CMOS cameras or to bypass them.

  18. Design and simulation of multi-color infrared CMOS metamaterial absorbers

    NASA Astrophysics Data System (ADS)

    Cheng, Zhengxi; Chen, Yongping; Ma, Bin

    2016-05-01

    Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.

  19. Dielectrophoretic lab-on-CMOS platform for trapping and manipulation of cells.

    PubMed

    Park, Kyoungchul; Kabiri, Shideh; Sonkusale, Sameer

    2016-02-01

    Trapping and manipulation of cells are essential operations in numerous studies in biology and life sciences. We discuss the realization of a Lab-on-a-Chip platform for dielectrophoretic trapping and repositioning of cells and microorganisms on a complementary metal oxide semiconductor (CMOS) technology, which we define here as Lab-on-CMOS (LoC). The LoC platform is based on dielectrophoresis (DEP) which is the force experienced by any dielectric particle including biological entities in non-uniform AC electrical field. DEP force depends on the permittivity of the cells, its size and shape and also on the permittivity of the medium and therefore it enables selective targeting of cells based on their phenotype. In this paper, we address an important matter that of electrode design for DEP for which we propose a three-dimensional (3D) octapole geometry to create highly confined electric fields for trapping and manipulation of cells. Conventional DEP-based platforms are implemented stand-alone on glass, silicon or polymers connected to external infrastructure for electronics and optics, making it bulky and expensive. In this paper, the use of CMOS as a platform provides a pathway to truly miniaturized lab-on-CMOS or LoC platform, where DEP electrodes are designed using built-in multiple metal layers of the CMOS process for effective trapping of cells, with built-in electronics for in-situ impedance monitoring of the cell position. We present electromagnetic simulation results of DEP force for this unique 3D octapole geometry on CMOS. Experimental results with yeast cells validate the design. These preliminary results indicate the promise of using CMOS technology for truly compact miniaturized lab-on-chip platform for cell biotechnology applications. PMID:26780441

  20. Electronic-photonic integrated circuits on the CMOS platform

    NASA Astrophysics Data System (ADS)

    Kimerling, L. C.; Ahn, D.; Apsel, A. B.; Beals, M.; Carothers, D.; Chen, Y.-K.; Conway, T.; Gill, D. M.; Grove, M.; Hong, C.-Y.; Lipson, M.; Liu, J.; Michel, J.; Pan, D.; Patel, S. S.; Pomerene, A. T.; Rasras, M.; Sparacin, D. K.; Tu, K.-Y.; White, A. E.; Wong, C. W.

    2006-02-01

    The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

  1. Nuclear magnetic resonance imaging with 90-nm resolution.

    PubMed

    Mamin, H J; Poggio, M; Degen, C L; Rugar, D

    2007-05-01

    Magnetic resonance imaging (MRI) is a powerful imaging technique that typically operates on the scale of millimetres to micrometres. Conventional MRI is based on the manipulation of nuclear spins with radio-frequency fields, and the subsequent detection of spins with induction-based techniques. An alternative approach, magnetic resonance force microscopy (MRFM), uses force detection to overcome the sensitivity limitations of conventional MRI. Here, we show that the two-dimensional imaging of nuclear spins can be extended to a spatial resolution better than 100 nm using MRFM. The imaging of 19F nuclei in a patterned CaF(2) test object was enabled by a detection sensitivity of roughly 1,200 nuclear spins at a temperature of 600 mK. To achieve this sensitivity, we developed high-moment magnetic tips that produced field gradients up to 1.4 x 10(6) T m(-1), and implemented a measurement protocol based on force-gradient detection of naturally occurring spin fluctuations. The resulting detection volume was less than 650 zeptolitres. This is 60,000 times smaller than the previous smallest volume for nuclear magnetic resonance microscopy, and demonstrates the feasibility of pushing MRI into the nanoscale regime.

  2. A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System

    PubMed Central

    Rae, Bruce R.; Muir, Keith R.; Gong, Zheng; McKendry, Jonathan; Girkin, John M.; Gu, Erdan; Renshaw, David; Dawson, Martin D.; Henderson, Robert K.

    2009-01-01

    We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented. PMID:22291564

  3. Investigation of III-V semiconductor heterostructures for post-Si-CMOS applications

    NASA Astrophysics Data System (ADS)

    Bhatnagar, Kunal

    Silicon complementary metal-oxide-semiconductor (CMOS) technology in the past few decades has been driven by aggressive device scaling to increase performance, reduce cost and lower power consumption. However, as devices are scaled below the 100 nm region, performance gain has become increasingly difficult to obtain by traditional scaling. As we move towards advanced technology nodes, materials innovation and physical architecture are becoming the primary enabler for performance enhancement in CMOS technology rather than scaling. One class of materials that can potentially result in improved electrical performance are III-V semiconductors, which are ideal candidates for replacing the channel in Si CMOS owing to their high electron mobilities and capabilities for band-engineering. This work is aimed towards the growth and characterization of III-V semiconductor heterostructures and their application in post-Si-CMOS devices. The two main components of this study include the integration of III-V compound semiconductors on silicon for tunnel-junction Esaki diodes, and the investigation of carrier transport properties in low-power III-V n-channel FETs under uniaxial strain for advanced III-V CMOS solutions. The integration of III-V compound semiconductors with Si can combine the cost advantage and maturity of the Si technology with the superior performance of III-V materials. We have demonstrated high quality epitaxial growth of GaAs and GaSb on Si (001) wafers through the use of various buffer layers including AlSb and crystalline SrTiO3. These GaSb/Si virtual substrates were used for the fabrication and characterization of InAs/GaSb broken-gap Esaki-tunnel diodes as a possible solution for heterojunction Tunnel-FETs. In addition, the carrier transport properties of InAs channels were evaluated under uniaxial strain for the potential use of strain solutions in III-V CMOS.

  4. NSC 800, 8-bit CMOS microprocessor

    NASA Technical Reports Server (NTRS)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  5. 120-MHz BiCMOS superscalar RISC processor

    NASA Astrophysics Data System (ADS)

    Tanaka, Shigeya; Hotta, Takashi; Murabayashi, Fumio; Yamada, Hiromichi; Yoshida, Shoji; Shimamura, Kotaro; Katsura, Koyo; Bandoh, Tadaaki; Ikeda, Koichi; Matsubara, Kenji

    1994-04-01

    A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm x 16.5 mm, and utilizes 3.3 V/0.5 micron BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.

  6. Radiation-hard silicon gate bulk CMOS cell family

    SciTech Connect

    Gibbon, C. F.; Habing, D. H.; Flores, R. S.

    1980-01-01

    A radiation-hardened bulk silicon gate CMOS technology and a topologically simple, high-performance dual-port cell family utilizing this process have been demonstrated. Additional circuits, including a random logic circuit containing 4800 transistors on a 236 x 236 mil die, are presently being designed and processed. Finally, a joint design-process effort is underway to redesign the cell family in reduced design rules; this results in a factor of 2.5 cell size reduction and a factor of 3 decrease in chip interconnect area. Cell performance is correspondingly improved.

  7. 180 Degree Hybrid (Rat-Race) Junction on CMOS Grade Silicon with a Polyimide Interface Layer

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Papapolymerou, John

    2003-01-01

    180-degree hybrid junctions can be used to equally divide power between two output ports with either a 0 or 180-degree phase difference. Alternatively, they can be used to combine signals from two sources and output a sum and difference signal. The main limitation of implementing; these on CMOS grade silicon is the high loss associated with the substrate. In this paper, we present a low loss 180-degree hybrid junction on CMOS grade (15 omega-cm) silicon with a polyimide interface layer for the first time. The divider utilizes Finite Ground Coplanar (FGC) line technology, and operates at a center frequency of 15 GIIz.

  8. A standard CMOS high-voltage transmitter for ultrasound medical imaging applications

    NASA Astrophysics Data System (ADS)

    Cha, Hyouk-Kyu

    2014-03-01

    A high-voltage (HV) transmitter for ultrasound medical imaging applications is designed using 0.18-µm CMOS (complementary metal oxide semiconductor) technology. The proposed HV transmitter achieves high integration by employing standard CMOS transistors in a stacked configuration with dynamic gate biasing circuit while successfully driving the capacitive output load with an HV pulse without device breakdown reliability issues. The HV transmitter, which includes the output driver and voltage level-shifters, generates up to 30-Vp-p pulses at 1.25 MHz frequency and occupies 0.035 mm² of layout area.

  9. Creating a parameterized model of a CMOS transistor with a gate of enclosed layout

    NASA Astrophysics Data System (ADS)

    Vinogradov, S. M.; Atkin, E. V.; Ivanov, P. Y.

    2016-02-01

    The method of creating a parameterized spice model of an N-channel transistor with a gate of enclosed layout is considered. Formulas and examples of engineering calculations for use of models in the computer-aided Design environment of Cadence Vitruoso are presented. Calculations are made for the CMOS technology with 180 nm design rules of the UMC.

  10. Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

    SciTech Connect

    Wang, Zujun Huang, Shaoyan; Liu, Minbo; Xiao, Zhigang; He, Baoping; Yao, Zhibin; Sheng, Jiangkun

    2014-07-15

    The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 10{sup 8} n/cm{sup 2}s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 10{sup 11}, 5 × 10{sup 11}, and 1 × 10{sup 12} n/cm{sup 2}, respectively. The mean dark signal (K{sub D}), dark signal spike, dark signal non-uniformity (DSNU), noise (V{sub N}), saturation output signal voltage (V{sub S}), and dynamic range (DR) versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike.

  11. Fundamental study on identification of CMOS cameras

    NASA Astrophysics Data System (ADS)

    Kurosawa, Kenji; Saitoh, Naoki

    2003-08-01

    In this study, we discussed individual camera identification of CMOS cameras, because CMOS (complementary-metal-oxide-semiconductor) imaging detectors have begun to make their move into the CCD (charge-coupled-device) fields for recent years. It can be identified whether or not the given images have been taken with the given CMOS camera by detecting the imager's intrinsic unique fixed pattern noise (FPN) just like the individual CCD camera identification method proposed by the authors. Both dark and bright pictures taken with the CMOS cameras can be identified by the method, because not only dark current in the photo detectors but also MOS-FET amplifiers incorporated in each pixel may produce pixel-to-pixel nonuniformity in sensitivity. Each pixel in CMOS detectors has the amplifier, which degrades image quality of bright images due to the nonuniformity of the amplifier gain. Two CMOS cameras were evaluated in our experiments. They were WebCamGoPlus (Creative), and EOS D30 (Canon). WebCamGoPlus is a low-priced web camera, whereas EOS D30 is for professional use. Image of a white plate were recorded with the cameras under the plate's luminance condition of 0cd/m2 and 150cd/m2. The recorded images were multiply integrated to reduce the random noise component. From the images of both cameras, characteristic dots patterns were observed. Some bright dots were observed in the dark images, whereas some dark dots were in the bright images. The results show that the camera identification method is also effective for CMOS cameras.

  12. New package for CMOS sensors

    NASA Astrophysics Data System (ADS)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  13. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    NASA Astrophysics Data System (ADS)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×1012 1 MeV neq/cm2 and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  14. 3D monolithically stacked CMOS Active Pixel Sensors for particle position and direction measurements

    NASA Astrophysics Data System (ADS)

    Servoli, L.; Passeri, D.; Morozzi, A.; Magalotti, D.; Piperku, L.

    2015-01-01

    In this work we propose a 3D monolithically stacked, multi-layer detectors based on CMOS Active Pixel Sensors (APS) layers which allows at the same time accurate estimation of the impact point and of the incidence angle an ionizing particle. The whole system features two fully-functional CMOS APS matrix detectors, including both sensing area and control/signal elaboration circuitry, stacked in a monolithic device by means of Through Silicon Via (TSV) connections thanks to the capabilities of the CMOS vertical scale integration (3D-IC) 130 nm Chartered/Tezzaron technology. In order to evaluate the suitability of the two layer monolithic active pixel sensor system to reconstruct particle tracks, tests with proton beams have been carried out at the INFN LABEC laboratories in Florence (Italy) with 3 MeV proton beam.

  15. A CMOS-compatible, surface-micromachined pressure sensor for aqueous ultrasonic application

    SciTech Connect

    Eaton, W.P.; Smith, J.H.

    1994-12-31

    A surface micromachined pressure sensor array is under development at the Integrated Micromechanics, Microsensors, and CMOS Technologies organization at Sandia National Laboratories. This array is designed to sense absolute pressures from ambient pressure to 650 psia with frequency responses from DC to 2 MHz. The sensor is based upon a sealed, deformable, circular LPCVD silicon nitride diaphragm. Absolute pressure is determined from diaphragm deflection, which is sensed with low-stress, micromechanical, LPCVD polysilicon piezoresistors. All materials and processes used for sensor fabrication are CMOS compatible, and are part of Sandia`s ongoing effort of CMOS integration with Micro-ElectroMechanical Systems (MEMS). Test results of individual sensors are presented along with process issues involving the release etch and metal step coverage.

  16. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

    PubMed

    Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

    2014-02-10

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

  17. Rapid Bacterial Detection via an All-Electronic CMOS Biosensor

    PubMed Central

    Nikkhoo, Nasim; Cumby, Nichole; Gulak, P. Glenn; Maxwell, Karen L.

    2016-01-01

    The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections. PMID:27618185

  18. Rapid Bacterial Detection via an All-Electronic CMOS Biosensor.

    PubMed

    Nikkhoo, Nasim; Cumby, Nichole; Gulak, P Glenn; Maxwell, Karen L

    2016-01-01

    The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections. PMID:27618185

  19. Overview of CMOS process and design options for image sensor dedicated to space applications

    NASA Astrophysics Data System (ADS)

    Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

    2005-10-01

    With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

  20. IR CMOS: near infrared enhanced digital imaging (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Pralle, Martin U.; Carey, James E.; Joy, Thomas; Vineis, Chris J.; Palsule, Chintamani

    2015-08-01

    SiOnyx has demonstrated imaging at light levels below 1 mLux (moonless starlight) at video frame rates with a 720P CMOS image sensor in a compact, low latency camera. Low light imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancements are achieved by applying Black Silicon, SiOnyx's proprietary ultrafast laser semiconductor processing technology. In the near infrared, silicon's native indirect bandgap results in low absorption coefficients and long absorption lengths. The Black Silicon nanostructured layer fundamentally disrupts this paradigm by enhancing the absorption of light within a thin pixel layer making 5 microns of silicon equivalent to over 300 microns of standard silicon. This results in a demonstrate 10 fold improvements in near infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see spot. Imaging performance metrics will be discussed. Demonstrated performance characteristics: Pixel size : 5.6 and 10 um Array size: 720P/1.3Mpix Frame rate: 60 Hz Read noise: 2 ele/pixel Spectral sensitivity: 400 to 1200 nm (with 10x QE at 1064nm) Daytime imaging: color (Bayer pattern) Nighttime imaging: moonless starlight conditions 1064nm laser imaging: daytime imaging out to 2Km

  1. CMOS prototype for retinal prosthesis applications with analog processing

    NASA Astrophysics Data System (ADS)

    Castillo-Cabrera, G.; García-Lamont, J.; Reyes-Barranca, M. A.; Matsumoto-Kuwabara, Y.; Moreno-Cadenas, J. A.; Flores-Nava, L. M.

    2014-12-01

    A core architecture for analog processing, which emulates a retina's receptive field, is presented in this work. A model was partially implemented and built on CMOS standard technology through MOSIS. It considers that the receptive field is the basic unit for image processing in the visual system. That is why the design is concerned on a partial solution of receptive field properties in order to be adapted in the future as an aid to people with retinal diseases. A receptive field is represented by an array of 3×3 pixels. Each pixel carries out a process based on four main operations. This means that image processing is developed at pixel level. Operations involved are: (1) photo-transduction by photocurrent integration, (2) signal averaging from eight neighbouring pixels executed by a neu-NMOS (ν-NMOS) neuron, (3) signal average gradient between central pixel and the average value from the eight neighbouring pixels (this gradient is performed by a comparator) and finally (4) a pulse generator. Each one of these operations gives place to circuital blocks which were built on 0.5 μm CMOS technology.

  2. Characterization and reliability of CMOS microstructures

    NASA Astrophysics Data System (ADS)

    Fedder, Gary K.; Blanton, Ronald D. S.

    1999-08-01

    This paper provides an overview of high-aspect-ratio CMOS micromachining, focusing on materials characterization, reliability, and fault analysis. Composite microstrutural beam widths and gaps down to 1.2 micrometers are etched out of conventional CMOS dielectric, aluminum, and gate-polysilicon thin films using post-CMOS dry etching for both structural sidewall definition and for release from the substrate. Differences in stress between the multiple metal and dielectric layers cause vertical stress gradients and curl, while misalignment between layers causes lateral stress gradients and curl. Cracking is induced in a resonant fatigue structures at 620 MPa of repetitive stress after over 50 million cycles. Beams have withstood over 1.3 billion cycles at 124 MPa stress levels induced by electrostatic actuation. Failures due to process defects are classified according to the geometrical features of the defective structures. Relative probability of occurrence of each defect type is extracted from the process simulation results.

  3. Low power, CMOS digital autocorrelator spectrometer for spaceborne applications

    NASA Technical Reports Server (NTRS)

    Chandra, Kumar; Wilson, William J.

    1992-01-01

    A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

  4. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    NASA Technical Reports Server (NTRS)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  5. End-of-fabrication CMOS process monitor

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

    1990-01-01

    A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

  6. Optical addressing technique for a CMOS RAM

    NASA Technical Reports Server (NTRS)

    Wu, W. H.; Bergman, L. A.; Allen, R. A.; Johnston, A. R.

    1988-01-01

    Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

  7. Integration of solid-state nanopores in a 0.5 μm cmos foundry process

    PubMed Central

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-01-01

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

  8. Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

    PubMed

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-04-19

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

  9. Integration hybride de transistors a un electron sur un noeud technologique CMOS

    NASA Astrophysics Data System (ADS)

    Jouvet, Nicolas

    This study deals with the hybrid integration of single electron transistors (SET) on a CMOS technology nod. SET devices possess a high potential, especially regarding energy efficiency, but aren't fit to completely replace CMOS components in electrical circuits. However, this problem can be solved through hybrid combination of SETs and MOS, leading to very low operating power circuits, and high integration density. This thesis investigates the use of the nanodamascene process, developed by C. Dubuc, for back-end-of-line (BEOL) SET fabrication, meaning creation of SETs in the oxide encapsulating CMOS devices. The assets the nanodamascene process presents are quite interesting: fabrication of SETs with a large operation margin, high repeatability, and potential for BEOL fabrication. This last point, in particular, makes this process promising. Indeed, it opens the path to the fabrication of numerous layers of SETs, stacked one upon the other, and forming 3D circuits, created on top of 2D CMOS layer. Thus a high gain to existing CMOS wafers could be generated. Devices created through the use of the nanodamascene process, adapted for BEOL SET fabrication, are presented. Limits and improvement perspectives of the technique's transfer are discussed. Electrical characterizations of the devices are also presented. They have demonstrated the created devices functionality, thus validating the successful adaption of the nanodamascene process. They have also allowed for the identification of numerous traps located at the heart of fabricated devices. Fabricated SET devices potential for hybrid SET-CMOS circuits was studied through simulations. Possible architectures showing good potential for early hybrid circuits' realization were identified. Keywords: MOSFET, single electron transistor (SET), nanotechnology, microfabrication, nanodamascene, electrical characterization.

  10. Fabrication and characterization of a charge-biased CMOS-MEMS resonant gate field effect transistor

    NASA Astrophysics Data System (ADS)

    Chin, C. H.; Li, C. S.; Li, M. H.; Wang, Y. L.; Li, S. S.

    2014-09-01

    A high-frequency charge-biased CMOS-MEMS resonant gate field effect transistor (RGFET) composed of a metal-oxide composite resonant-gate structure and an FET transducer has been demonstrated utilizing the TSMC 0.35 μm CMOS technology with Q > 1700 and a signal-to-feedthrough ratio greater than 35 dB under a direct two-port measurement configuration. As compared to the conventional capacitive-type MEMS resonators, the proposed CMOS-MEMS RGFET features an inherent transconductance gain (gm) offered by the FET transduction capable of enhancing the motional signal of the resonator and relaxing the impedance mismatch issue to its succeeding electronics or 50 Ω-based test facilities. In this work, we design a clamped-clamped beam resonant-gate structure right above a floating gate FET transducer as a high-Q building block through a maskless post-CMOS process to combine merits from the large capacitive transduction areas of the large-width beam resonator and the high gain of the underneath FET. An analytical model is also provided to simulate the behavior of the charge-biased RGFET; the theoretical prediction is in good agreement with the experimental results. Thanks to the deep-submicrometer gap spacing enabled by the post-CMOS polysilicon release process, the proposed resonator under a purely capacitive transduction already attains motional impedance less than 10 kΩ, a record-low value among CMOS-MEMS capacitive resonators. To go one step further, the motional signal of the proposed RGFET is greatly enhanced through the FET transduction. Such a strong transmission and a sharp phase transition across 0° pave a way for future RGFET-type oscillators in RF and sensor applications. A time-elapsed characterization of the charge leakage rate for the floating gate is also carried out.

  11. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking

    PubMed Central

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-01-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

  12. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    PubMed Central

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  13. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    PubMed

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-07-10

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  14. CMOS cassette for digital upgrade of film-based mammography systems

    NASA Astrophysics Data System (ADS)

    Baysal, Mehmet A.; Toker, Emre

    2006-03-01

    While full-field digital mammography (FFDM) technology is gaining clinical acceptance, the overwhelming majority (96%) of the installed base of mammography systems are conventional film-screen (FSM) systems. A high performance, and economical digital cassette based product to conveniently upgrade FSM systems to FFDM would accelerate the adoption of FFDM, and make the clinical and technical advantages of FFDM available to a larger population of women. The planned FFDM cassette is based on our commercial Digital Radiography (DR) cassette for 10 cm x 10 cm field-of-view spot imaging and specimen radiography, utilizing a 150 micron columnar CsI(Tl) scintillator and 48 micron active-pixel CMOS sensor modules. Unlike a Computer Radiography (CR) cassette, which requires an external digitizer, our DR cassette transfers acquired images to a display workstation within approximately 5 seconds of exposure, greatly enhancing patient flow. We will present the physical performance of our prototype system against other FFDM systems in clinical use today, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and subjective criteria, such as a contrast-detail (CD-MAM) observer performance study. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for FFDM today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. This study promises to take advantage of these unique features to develop the first CMOS based FFDM upgrade cassette.

  15. Radiation Tolerance of 65nm CMOS Transistors

    DOE PAGES

    Krohn, M.; Bentele, B.; Christian, D. C.; Cumalat, J. P.; Deptuch, G.; Fahim, F.; Hoff, J.; Shenai, A.; Wagner, S. R.

    2015-12-11

    We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately -20°C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  16. SEU hardening of CMOS memory circuit

    NASA Technical Reports Server (NTRS)

    Whitaker, S.; Canaris, J.; Liu, K.

    1990-01-01

    This paper reports a design technique to harden CMOS memory circuits against Single Event Upset (SEU) in the space environment. A RAM cell and Flip Flop design are presented to demonstrate the method. The Flip Flop was used in the control circuitry for a Reed Solomon encoder designed for the Space Station.

  17. Design and realization of CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Xu, Jian; Xiao, Zexin

    2008-02-01

    A project was presented that instrumental design of an economical CMOS microscope image sensor. A high performance, low price, black-white camera chip OV5116P was used as the core of the sensor circuit; Designing and realizing peripheral control circuit of sensor; Through the control on dial switch to realize different functions of the sensor chip in the system. For example: auto brightness level descending function on or off; gamma correction function on or off; auto and manual backlight compensation mode conversion and so on. The optical interface of sensor is designed for commercialization and standardization. The images of sample were respectively gathered with CCD and CMOS. Result of the experiment indicates that both performances were identical in several aspects as follows: image definition, contrast control, heating degree and the function can be adjusted according to the demand of user etc. The imperfection was that the CMOS with smaller field and higher noise than CCD; nevertheless, the maximal advantage of choosing the CMOS chip is its low cost. And its imaging quality conformed to requirement of the economical microscope image sensor.

  18. Fully CMOS-compatible titanium nitride nanoantennas

    NASA Astrophysics Data System (ADS)

    Briggs, Justin A.; Naik, Gururaj V.; Petach, Trevor A.; Baum, Brian K.; Goldhaber-Gordon, David; Dionne, Jennifer A.

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  19. CMOS preamplifiers for detectors large and small

    SciTech Connect

    O`Connor, P.

    1997-12-31

    We describe four CMOS preamplifiers developed for multiwire proportional chambers (MWPC) and silicon drift detectors (SDD) covering a capacitance range from 150 pF to 0.15 pF. Circuit techniques to optimize noise performance, particularly in the low-capacitance regime, are discussed.

  20. Improving CMOS-compatible Germanium photodetectors.

    PubMed

    Li, Guoliang; Luo, Ying; Zheng, Xuezhe; Masini, Gianlorenzo; Mekis, Attila; Sahni, Subal; Thacker, Hiren; Yao, Jin; Shubin, Ivan; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

    2012-11-19

    We report design improvements for evanescently coupled Germanium photodetectors grown at low temperature. The resulting photodetectors with 10 μm Ge length manufactured in a commercial CMOS process achieve >0.8 A/W responsivity over the entire C-band, with a device capacitance of <7 fF based on measured data.

  1. A fail-safe CMOS logic gate

    NASA Technical Reports Server (NTRS)

    Bobin, V.; Whitaker, S.

    1990-01-01

    This paper reports a design technique to make Complex CMOS Gates fail-safe for a class of faults. Two classes of faults are defined. The fail-safe design presented has limited fault-tolerance capability. Multiple faults are also covered.

  2. High-Q CMOS-integrated photonic crystal microcavity devices.

    PubMed

    Mehta, Karan K; Orcutt, Jason S; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J

    2014-01-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300-9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems.

  3. High-Q CMOS-integrated photonic crystal microcavity devices

    NASA Astrophysics Data System (ADS)

    Mehta, Karan K.; Orcutt, Jason S.; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J.

    2014-02-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300-9,300 one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems.

  4. BiCMOS-integrated photodiode exploiting drift enhancement

    NASA Astrophysics Data System (ADS)

    Swoboda, Robert; Schneider-Hornstein, Kerstin; Wille, Holger; Langguth, Gernot; Zimmermann, Horst

    2014-08-01

    A vertical pin photodiode with a thick intrinsic layer is integrated in a 0.5-μm BiCMOS process. The reverse bias of the photodiode can be increased far above the circuit supply voltage, enabling a high-drift velocity. Therefore, a highly efficient and very fast photodiode is achieved. Rise/fall times down to 94 ps/141 ps at a bias of 17 V were measured for a wavelength of 660 nm. The bandwidth was increased from 1.1 GHz at 3 V to 2.9 GHz at 17 V due to the drift enhancement. A quantum efficiency of 85% with a 660-nm light was verified. The technological measures to avoid negative effects on an NPN transistor due to the Kirk effect caused by the low-doped I-layer epitaxy are described. With a high-energy collector implant, the NPN transit frequency is held above 20 GHz. CMOS devices are unaffected. This photodiode is suitable for a wide variety of high-sensitivity optical sensor applications, for optical communications, for fiber-in-the-home applications, and for optical interconnects.

  5. A 50Mbit/Sec. CMOS Video Linestore System

    NASA Astrophysics Data System (ADS)

    Jeung, Yeun C.

    1988-10-01

    This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

  6. Low-Power SOI CMOS Transceiver

    NASA Technical Reports Server (NTRS)

    Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

    2003-01-01

    The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS

  7. CMOS MEMS capacitive absolute pressure sensor

    NASA Astrophysics Data System (ADS)

    Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

    2013-05-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

  8. IR CMOS: the digital nightvision solution to sub-1 mLux imaging

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Vineis, C.; Palsule, C.; Jiang, J.; Joy, T.

    2015-05-01

    SiOnyx has demonstrated imaging at light levels below 1 mLux at 60 FPS with a 720P CMOS image sensor in a compact, low latency camera. The camera contains a 1 inch (16 mm) optical format sensor and streams uncompressed video over CameraLink with row wise image latency below 1 msec. Sub mLux imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancement is achieved by utilizing SiOnyx's proprietary ultrafast laser semiconductor processing technology that enhances the absorption of light within a thin pixel layer. Our technology demonstrates a 10 fold improvement in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see-spot.

  9. Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

    PubMed Central

    Kim, Jong-Wan; Takao, Hidekuni; Sawada, Kazuaki; Ishida, Makoto

    2007-01-01

    This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiral inductors for an LC resonator and an integrated antenna have been fabricated and evaluated experimentally. The fabricated RF transmitter and integrated antenna were packaged with subminiature series A (SMA) connectors, respectively. For the impedance (50 Ω) matching, a bonding wire type inductor was developed. In this paper, the design and fabrication of the bonding wire inductor for impedance matching is described. Integrated techniques for the RF transmitter by CMOS compatible processes have been successfully developed. After matching by inserting the bonding wire inductor between the on-chip integrated antenna and the VCO output, the measured emission power at distance of 5 m from RF transmitter was -37 dBm (0.2 μW).

  10. A large-scale ceramic package of the CMOS image sensor chip for remote sensing application

    NASA Astrophysics Data System (ADS)

    Chang, Chia-Hung; Ling, Jer; Lo, Shih-Hung; Hsu, Wen-Chih; Liu, Cynthia

    2012-10-01

    A CMOS image sensor chip with the ceramic package technique for remote sensing application is presented in this paper. The chip is fabricated using the United Microelectronics Corporation (UMC) 0.18 um CMOS technology and occupies 25 mm x 120 mm of chip area, which is much larger than the conventional ones. Furthermore, a trade-off in sealing of the cover glass faces the gas leak and moisture sorption. The package of the CMOS image sensor chip in space may cause crack, leakage, and deformation. Consequently, a large-scale and specific package is required to meet remote sensing application. The proposed ceramic package comprises a ceramic substrate, a cover glass, a chip seal, a glass seal, and golden lines. The dimension with lead is approximately 155 mm x 60 mm x 7.87 mm, including 76 Pin Grid Array (PGA) at each side. To demonstrate the reliabilities, the sensor with large-scale ceramic package is also analyzed, manufactured, and tested by the thermal shock, vibration, and vacuum tests. Moreover, the Coordinate Measuring Machine (CMM) is employed to measure the common plane of the package. By testing 12 points on the top plane of the package, the measured relatively peak-to-peak variation can be lower than 10 um. A large-scale ceramic package of the CMOS image sensor chip is implemented in this work to achieve the specifications of the remote sensing application in space.

  11. Design and fabrication of a CMOS-compatible MHP gas sensor

    SciTech Connect

    Li, Ying; Yu, Jun Wu, Hao; Tang, Zhenan

    2014-03-15

    A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

  12. Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker

    NASA Astrophysics Data System (ADS)

    Rizzo, G.; Comott, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Giorgi, F.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.; Gannaway, F.; Cenci, R.; Bombelli, L.; Citterio, M.; Coelli, S.; Fiorini, C.; Liberali, V.; Monti, M.; Nasri, B.; Neri, N.; Palombo, F.; Stabile, A.; Balestri, G.; Batignani, G.; Bernardelli, A.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Forti, F.; Giorgi, M. A.; Lusiani, A.; Mammini, P.; Morsani, F.; Oberhof, B.; Paoloni, E.; Perez, A.; Petragnani, G.; Profeti, A.; Soldani, A.; Walsh, J.; Chrzaszcz, M.; Gaioni, L.; Manazza, A.; Quartieri, E.; Ratti, L.; Zucca, S.; Alampi, G.; Cotto, G.; Gamba, D.; Zambito, S.; Dalla Betta, G.-F.; Fontana, G.; Pancheri, L.; Povoli, M.; Verzellesi, G.; Bomben, M.; Bosisio, L.; Cristaudo, P.; Lanceri, L.; Liberti, B.; Rashevskaya, I.; Stella, C.; Vitale, L.

    2013-08-01

    In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10 - 15 μm in both coordinates, low material budget < 1 %X0, and the ability to withstand a background hit rate of several tens of MHz /cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.

  13. Microactuateur electrothermique bistable: Etude d'implementation avec une technologie standard CMOS

    NASA Astrophysics Data System (ADS)

    Ressejac, Isabelle

    The general objective of this Ph.D. thesis was to study the implementation of a new type of eletrothermal microactuator. This actuator presents the advantages to be bistable and fabricated in a standard CMOS process, allowing the integration of a microelectronics addressing circuit on the same substrate. Experimental research work, presented in this thesis, relate to the different steps carried out in order to implement this CMOS MEMS device: its theoretical conception, its fabrication with a standard CMOS technology, its micromachining as a post-process, its characterization and its electro-thermo-mechanical modeling. The device was designed and fabricated by using Mitel 1,5 mum CMOS technology and the Can-MEMS service which are both available via the Canadian Microelectronics Corporation. Fabricated monolithically within a standard CMOS process, our microactuator is suitable for large-scale integration due to its small dimensions (length ˜1000 mum and width ˜150 mum). It constitutes the basic component of a N by N matrix controlled by a microelectronic addressing system built on the same substrate. Initially, only one micromachining technique (involving TMAH) was used, and long etching times (>9 h) were requires} in order to release the microstructures. However, the passivation layer from the CMOS process could protect the underlying metal from the TMAH for a sufficient time (only ˜1--2 h). Consequently, we had to develop a micromachining strategy with shorter etching times to allow the complete release of the microstructures without damaging them. Post-processing begins with deposition (by sputtering) of a platinum layer intended to protect the abutment from subsequent etching. Our micromachining strategy is mainly based on the use of a hybrid etching process starting with a first anisotropic TMAH etching followed by a XeF2 isotropic etching. After micromachining, the released microactuator has a significant initial deflection with its tip reaching a height

  14. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    PubMed

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-01

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

  15. A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT switch

    NASA Astrophysics Data System (ADS)

    Zonghua, Zheng; Lingling, Sun; Jun, Liu; Shengzhou, Zhang

    2016-01-01

    A novel loss compensation technique for a series-shunt single-pole double-throw (SPDT) switch is presented operating in the 60 GHz. The feed-forward compensation network which is composed of an NMOS, a couple capacitance and a shunt inductance can reduce the impact of the feed forward capacitance to reduce the insertion loss and improve the isolation of the SPDT switch. The measured insertion loss and isolation characteristics of the switch somewhat deviating from the 60 GHz are analyzed revealing that the inaccuracy of the MOS model can greatly degrade the performance of the switch. The switch is implemented in TSMC 90-nm CMOS process and exhibits an isolation of above 27 dB at transmitter mode, and the insertion loss of 1.8-3 dB at 30-65 GHz by layout simulation. The measured insertion loss is 2.45 dB at 52 GHz and keeps < 4 dB at 30-64 GHz. The measured isolation is better than 25 dB at 30-64 GHz and the measured return loss is better than 10 dB at 30-65 GHz. A measured input 1 dB gain compression point of the switch is 13 dBm at 52 GHz and 15 dBm at 60 GHz. The simulated switching speed with rise time and fall time are 720 and 520 ps, respectively. The active chip size of the proposed switch is 0.5 × 0.95 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61331006, 61372021).

  16. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    PubMed

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-30

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

  17. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

    PubMed Central

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-01

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

  18. Micro-lens maker equation of a CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Wu, Yang

    2007-09-01

    The demand of a large resolution CMOS image sensor (CIS) in a small package drives the pixel pitch size down to the neighborhood of 2 μm. Double-micro-lens (ML) structure is a promising technology to obtain the high focusing capability required by such a small pixel. In this work, an optical model of a double-ML is derived from the well-known lens maker equation. This model predicts the critical back focal length (BFL) and the effective focal length (EFL) of the double-ML embedded in the Back-End-Of-The-Line (BEOL) stack. Explained by this model, a design guideline is provided to optimize the amount of light collected by the photo diode area for a good quantum efficiency (QE), which is crucial to the sensitivity of the sensor.

  19. An improved equivalent simulation model for CMOS integrated Hall plates.

    PubMed

    Xu, Yue; Pan, Hong-Bin

    2011-01-01

    An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model's simulation results are in good agreement with the classic experimental results reported in the literature.

  20. An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates

    PubMed Central

    Xu, Yue; Pan, Hong-Bin

    2011-01-01

    An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature. PMID:22163955

  1. Four channel CMOS codec filter circuit `SICOFIqq-4'

    NASA Astrophysics Data System (ADS)

    Tiefenbacher, M.; Caldera, P.; Dielacher, F.; Hauptmann, J.; Steiner, M.

    1994-08-01

    Cost reduction by integration of complex mixed analog-digital systems on a single chip and an excellent yield to area ratio is a major goal for IC design in the nineties. In this paper, a four-channel codec-filter chip for analog subscriber lines in ISDN-orientated networks is presented, giving an exceptional example for high level system implementation combined with parallel DSP integration and analog circuitry with high performance. The chip combines four analog frontends, digital signal processing realized by different approaches for a sophisticated filter concept in addition with test strategies including digital and analog BIST. The circuit is fabricated in a standard 1-mu CMOS technology, needs a single 5-V power supply, and can easily be programmed to world-wide different country specifications and applications.

  2. Interferometric metrology of wafer nanotopography for advanced CMOS process integration

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Koliopoulos, Chris L.; Tang, Shouhong

    2001-12-01

    According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

  3. CMOS Camera Array With Onboard Memory

    NASA Technical Reports Server (NTRS)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  4. Radiation effects on scientific CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Yuanfu, Zhao; Liyan, Liu; Xiaohui, Liu; Xiaofeng, Jin; Xiang, Li

    2015-11-01

    A systemic solution for radiation hardened design is presented. Besides, a series of experiments have been carried out on the samples, and then the photoelectric response characteristic and spectral characteristic before and after the experiments have been comprehensively analyzed. The performance of the CMOS image sensor with the radiation hardened design technique realized total-dose resilience up to 300 krad(Si) and resilience to single-event latch up for LET up to 110 MeV·cm2/mg.

  5. CMOS-array design-automation techniques

    NASA Technical Reports Server (NTRS)

    Feller, A.; Lombardt, T.

    1979-01-01

    Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

  6. Radiation characteristics of scintillator coupled CMOS APS for radiography conditions

    NASA Astrophysics Data System (ADS)

    Kim, Kwang Hyun; Kim, Soongpyung; Kang, Dong-Won; Kim, Dong-Kie

    2006-11-01

    Under industrial radiography conditions, we analyzed short-term radiation characteristics of scintillator coupled CMOS APS (hereinafter SC CMOS APS). By means of experimentation, the contribution of the transmitted X-ray through the scintillator to the properties of the CMOS APS and the afterimage, generated in the acquired image even at low dose condition, were investigated. To see the transmitted X-ray effects on the CMOS APS, Fein focus™ X-ray machine, two scintillators of Lanex™ Fine and Regular, and two CMOS APS array of RadEye™ were used under the conditions of 50 kV p/1 mAs and 100 kV p/1 mAs. By measuring the transmitted X-ray on signal and Noise Power Spectrum, we analytically examined the generation mechanism of the afterimage, based on dark signal or dark current increase in the sensor, and explained the afterimage in the SC CMOS APS.

  7. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    PubMed

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-01-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

  8. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    PubMed

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-11-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

  9. Design of Low Power CMOS Read-Out with TDI Function for Infrared Linear Photodiode Array Detectors

    NASA Technical Reports Server (NTRS)

    Vizcaino, Paul; Ramirez-Angulo, Jaime; Patel, Umesh D.

    2007-01-01

    A new low voltage CMOS infrared readout circuit using the buffer-direct injection method is presented. It uses a single supply voltage of 1.8 volts and a bias current of 1uA. The time-delay integration technique is used to increase the signal to noise ratio. A current memory circuit with faulty diode detection is used to remove dark current for background compensation and to disable a photodiode in a cell if detected as faulty. Simulations are shown that verify the circuit that is currently in fabrication in 0.5ym CMOS technology.

  10. Current-mode CMOS hybrid image sensor

    NASA Astrophysics Data System (ADS)

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several

  11. The Intersection of CMOS Microsystems and Upconversion Nanoparticles for Luminescence Bioimaging and Bioassays

    PubMed Central

    Wei, Liping.; Doughan, Samer.; Han, Yi.; DaCosta, Matthew V.; Krull, Ulrich J.; Ho, Derek.

    2014-01-01

    Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs) offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR) wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV) wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS) technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies. PMID:25211198

  12. The intersection of CMOS microsystems and upconversion nanoparticles for luminescence bioimaging and bioassays.

    PubMed

    Wei, Liping; Doughan, Samer; Han, Yi; DaCosta, Matthew V; Krull, Ulrich J; Ho, Derek

    2014-09-10

    Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs) offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR) wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV) wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS) technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies.

  13. High-Q CMOS-integrated photonic crystal microcavity devices

    PubMed Central

    Mehta, Karan K.; Orcutt, Jason S.; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J.

    2014-01-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300–9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems. PMID:24518161

  14. CMOS-Compatible Room-Temperature Rectifier Toward Terahertz Radiation Detection

    NASA Astrophysics Data System (ADS)

    Varlamava, Volha; De Amicis, Giovanni; Del Monte, Andrea; Perticaroli, Stefano; Rao, Rosario; Palma, Fabrizio

    2016-08-01

    In this paper, we present a new rectifying device, compatible with the technology of CMOS image sensors, suitable for implementing a direct-conversion detector operating at room temperature for operation at up to terahertz frequencies. The rectifying device can be obtained by introducing some simple modifications of the charge-storage well in conventional CMOS integrated circuits, making the proposed solution easy to integrate with the existing imaging systems. The rectifying device is combined with the different elements of the detector, composed of a 3D high-performance antenna and a charge-storage well. In particular, its position just below the edge of the 3D antenna takes maximum advantage of the high electric field concentrated by the antenna itself. In addition, the proposed structure ensures the integrity of the charge-storage well of the detector. In the structure, it is not necessary to use very scaled and costly technological nodes, since the CMOS transistor only provides the necessary integrated readout electronics. On-wafer measurements of RF characteristics of the designed junction are reported and discussed. The overall performances of the entire detector in terms of noise equivalent power (NEP) are evaluated by combining low-frequency measurements of the rectifier with numerical simulations of the 3D antenna and the semiconductor structure at 1 THz, allowing prediction of the achievable NEP.

  15. SiGe BiCMOS manufacturing platform for mmWave applications

    NASA Astrophysics Data System (ADS)

    Kar-Roy, Arjun; Howard, David; Preisler, Edward; Racanelli, Marco; Chaudhry, Samir; Blaschke, Volker

    2010-10-01

    TowerJazz offers high volume manufacturable commercial SiGe BiCMOS technology platforms to address the mmWave market. In this paper, first, the SiGe BiCMOS process technology platforms such as SBC18 and SBC13 are described. These manufacturing platforms integrate 200 GHz fT/fMAX SiGe NPN with deep trench isolation into 0.18μm and 0.13μm node CMOS processes along with high density 5.6fF/μm2 stacked MIM capacitors, high value polysilicon resistors, high-Q metal resistors, lateral PNP transistors, and triple well isolation using deep n-well for mixed-signal integration, and, multiple varactors and compact high-Q inductors for RF needs. Second, design enablement tools that maximize performance and lowers costs and time to market such as scalable PSP and HICUM models, statistical and Xsigma models, reliability modeling tools, process control model tools, inductor toolbox and transmission line models are described. Finally, demonstrations in silicon for mmWave applications in the areas of optical networking, mobile broadband, phased array radar, collision avoidance radar and W-band imaging are listed.

  16. Failures of CMOS Circuits Irradiated At Low Rates

    NASA Technical Reports Server (NTRS)

    Goben, Charles A.; Price, William E.

    1990-01-01

    Report describes experiments on irradiation of SGS 4007 complementary metal oxide/semiconductor (CMOS) integrated inverter circuits by 60Co and 137Cs radioactive sources. Purpose of experiments to supplement previous observations that minimum radiation doses at which failure occurred in more-complicated CMOS parts were lower at lower dose rates.

  17. A highly sensitive CMOS digital Hall sensor for low magnetic field applications.

    PubMed

    Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

    2012-01-01

    Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ± 2 mT magnetic field and output a digital Hall signal in a wide temperature range from -40 °C to 120 °C.

  18. A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications

    PubMed Central

    Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

    2012-01-01

    Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ±2 mT magnetic field and output a digital Hall signal in a wide temperature range from −40 °C to 120 °C. PMID:22438758

  19. The optimization of zero-spaced microlenses for 2.2um pixel CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Nam, Hyun hee; Park, Jeong Lyeol; Choi, Jea Sung; Lee, Jeong Gun

    2007-03-01

    In CMOS image sensor, microlens arrays are generally used as light propagation carrier onto photo diode to increase collection efficiency and reduce optical cross-talk. Today, the scaling trend of CMOS technology drives reduction of the pixel size for higher integration density and resolution improvement. Microlenses are typically formed by photo resist patterning and thermal reflowing, and the space between photo resist is necessary to avoid merging of microlenses during thermal reflow process. With the shrinking sizes, microlenses become more and more difficult to manufacture without their merging. Hence, the key of light loss free microlens fabrication is still zero-space between microlenses. In this paper, we report the selection of the optimum shape of microlens by the dead space and the curvature of radius. The improvements of critical dimension and thickness uniformities of microlens are also reported.

  20. Neural CMOS-integrated circuit and its application to data classification.

    PubMed

    Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

    2012-05-01

    Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

  1. Monolithic optical phased-array transceiver in a standard SOI CMOS process.

    PubMed

    Abediasl, Hooman; Hashemi, Hossein

    2015-03-01

    Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system.

  2. Monolithic optical phased-array transceiver in a standard SOI CMOS process.

    PubMed

    Abediasl, Hooman; Hashemi, Hossein

    2015-03-01

    Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system. PMID:25836869

  3. A CMOS compatible Microbulk Micromegas-like detector using silicon oxide as spacer material

    NASA Astrophysics Data System (ADS)

    Blanco Carballo, V. M.; Fransen, M.; van der Graaf, H.; Lu, J.; Schmitz, J.

    2011-02-01

    We present a new Micro Pattern Gaseous Detector (MPGD) fabricated with nonpolymeric materials. The device structure is similar to a Microbulk Micromegas design, consisting of a punctured metal grid supported by a continuous perforated insulating structure. In this detector, the supporting structure is made out of silicon oxide. Devices were tested in He/ iC 4H 10 (80/20) and Ar/ iC 4H 10 (80/20) gas mixtures under 55Fe irradiation. Gas gain of 20,000 and energy resolution below 13% FWHM were achieved. The CMOS compatibility of the fabrication process has been studied in Timepix chips as well as individual 0.13-μm technology CMOS transistors. Complete detectors have been fabricated on top of Timepix chips. In an Ar/ iC 4H 10 (80/20) gas mixture 55Fe decay events were recorded operating the Timepix chip in 2D readout mode.

  4. A low power 3.125 Gbps CMOS analog equalizer for serial links

    NASA Astrophysics Data System (ADS)

    Hao, Ju; Yumei, Zhou; Yishu, Jiao

    2010-11-01

    A CMOS analog equalizer is designed to meet the different high speed communication specifications, such as USB 2.0, PCI-E and rapid IO. The proposed circuit architecture could facilitate the wide frequency scale ranging from 1 to 3.125 Gbps by adjusting the locations of pole and zero, so that the circuit can change its response accordingly as the channel characteristic alters. In order to balance the parasitic capacitors in the internal point, symmetric switches are addressed to generate the equal load for differential signals. A prototype chip was fabricated in 0.13-μm 1P8M mix-signal CMOS technology. The actual area is 0.49 × 0.5 mm2, and the analog equalizer operates up to 3.125 Gbps over 3 m RG-58 coaxial cable and 50 cm FR4-PCB trace. The overall power dissipation is approximately 14.4 mW.

  5. Vertical Isolation for Photodiodes in CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2008-01-01

    In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

  6. Organic Field-Effect Transistors for CMOS Devices

    NASA Astrophysics Data System (ADS)

    Melzer, Christian; von Seggern, Heinz

    Organic field-effect transistors (OFETs) are the key elements of future low cost electronics such as radio frequency identification tags. In order to take full advantage of organic electronics, low power consumption is mandatory, requiring the use of a complementary metal oxide semiconductor (CMOS) like technique. To realize CMOS-devices p-type and n-type organic field-effect transistors on one substrate have to be provided. Here, the latest concepts to produce in a straightforward way complementary acting OFETs for CMOS-like elements are illustrated on basis of the inverter. Starting from a simple description of thin-film transistors, the basic design rules for the development of complementary OFETs are given and some realizations of CMOS-like inverters are discussed. A CMOS-like inverter based on two identical field-effect transistors disclosing almost unipolar p-type and n-type behavior is presented.

  7. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    NASA Astrophysics Data System (ADS)

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  8. A CMOS high speed imaging system design based on FPGA

    NASA Astrophysics Data System (ADS)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  9. Real-time reconfigurable subthreshold CMOS perceptron.

    PubMed

    Aunet, S; Oelmann, B; Norseng, P A; Berg, Y

    2008-04-01

    In this paper, a new, real-time reconfigurable perceptron circuit element is presented. A six-transistor version used as a threshold gate, having a fan-in of three, producing adequate outputs for threshold of T =1, 2 and 3 is demonstrated by chip measurements. Subthreshold operation for supply voltages in the range of 100-350 mV is shown. The circuit performs competitively with a standard static complimentary metal-oxide-semiconductor (CMOS) implementation when maximum speed and energy delay product are taken into account, when used in a ring oscillator. Functionality per transistor is, to our knowledge, the highest reported for a variety of comparable circuits not based on floating gate techniques. Statistical simulations predict probabilities for making working circuits under mismatch and process variations. The simulations, in 120-nm CMOS, also support discussions regarding lower limits to supply voltage and redundancy. A brief discussion on how the circuit may be exploited as a basic building block for future defect tolerant mixed signal circuits, as well as neural networks, exploiting redundancy, is included.

  10. Modulated CMOS camera for fluorescence lifetime microscopy.

    PubMed

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition. PMID:26500051

  11. Modulated CMOS camera for fluorescence lifetime microscopy.

    PubMed

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition.

  12. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  13. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  14. Pick-and-place process for sensitivity improvement of the capacitive type CMOS MEMS 2-axis tilt sensor

    NASA Astrophysics Data System (ADS)

    Chang, Chun-I.; Tsai, Ming-Han; Liu, Yu-Chia; Sun, Chih-Ming; Fang, Weileun

    2013-09-01

    This study exploits the foundry available complimentary metal-oxide-semiconductor (CMOS) process and the packaging house available pick-and-place technology to implement a capacitive type micromachined 2-axis tilt sensor. The suspended micro mechanical structures such as the spring, stage and sensing electrodes are fabricated using the CMOS microelectromechanical systems (MEMS) processes. A bulk block is assembled onto the suspended stage by pick-and-place technology to increase the proof-mass of the tilt sensor. The low temperature UV-glue dispensing and curing processes are employed to bond the block onto the stage. Thus, the sensitivity of the CMOS MEMS capacitive type 2-axis tilt sensor is significantly improved. In application, this study successfully demonstrates the bonding of a bulk solder ball of 100 µm in diameter with a 2-axis tilt sensor fabricated using the standard TSMC 0.35 µm 2P4M CMOS process. Measurements show the sensitivities of the 2-axis tilt sensor are increased for 2.06-fold (x-axis) and 1.78-fold (y-axis) after adding the solder ball. Note that the sensitivity can be further improved by reducing the parasitic capacitance and the mismatch of sensing electrodes caused by the solder ball.

  15. SPICE analysis of the SEU sensitivity of a fully depleted SOI CMOS SRAM cell

    SciTech Connect

    Alles, M.L. )

    1994-12-01

    Fully depleted silicon-on-insulator (SOI) technologies are of interest for commercial applications as well as for use in harsh (radiation-intensive) environments. In both types of application, effects of charged particles (single-event effects) are of concern. Here, SPICE analysis of SEU sensitivity of a 6-T SRAM cell using commercially-representative fully depleted SOI CMOS technology parameters indicates that reduction of the minority carrier lifetime (parasitic bipolar gain) and use of thinner silicon can significantly reduce SEU sensitivity.

  16. Charge collection studies in irradiated HV-CMOS particle detectors

    NASA Astrophysics Data System (ADS)

    Affolder, A.; Andelković, M.; Arndt, K.; Bates, R.; Blue, A.; Bortoletto, D.; Buttar, C.; Caragiulo, P.; Cindro, V.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Gorišek, A.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hommels, L. B. A.; Huffman, T.; John, J.; Kanisauskas, K.; Kenney, C.; Kramberger, G.; Liang, Z.; Mandić, I.; Maneuski, D.; McMahon, S.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Perić, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zavrtanik, M.; Zhang, J.; Zhu, H.

    2016-04-01

    Charge collection properties of particle detectors made in HV-CMOS technology were investigated before and after irradiation with reactor neutrons. Two different sensor types were designed and processed in 180 and 350 nm technology by AMS. Edge-TCT and charge collection measurements with electrons from 90Sr source were employed. Diffusion of generated carriers from undepleted substrate contributes significantly to the charge collection before irradiation, while after irradiation the drift contribution prevails as shown by charge measurements at different shaping times. The depleted region at a given bias voltage was found to grow with irradiation in the fluence range of interest for strip detectors at the HL-LHC. This leads to large gains in the measured charge with respect to the one before irradiation. The increase of the depleted region was attributed to removal of effective acceptors. The evolution of depleted region with fluence was investigated and modeled. Initial studies show a small effect of short term annealing on charge collection.

  17. Label-free immunodetection with CMOS-compatible semiconducting nanowires.

    PubMed

    Stern, Eric; Klemic, James F; Routenberg, David A; Wyrembak, Pauline N; Turner-Evans, Daniel B; Hamilton, Andrew D; LaVan, David A; Fahmy, Tarek M; Reed, Mark A

    2007-02-01

    Semiconducting nanowires have the potential to function as highly sensitive and selective sensors for the label-free detection of low concentrations of pathogenic microorganisms. Successful solution-phase nanowire sensing has been demonstrated for ions, small molecules, proteins, DNA and viruses; however, 'bottom-up' nanowires (or similarly configured carbon nanotubes) used for these demonstrations require hybrid fabrication schemes, which result in severe integration issues that have hindered widespread application. Alternative 'top-down' fabrication methods of nanowire-like devices produce disappointing performance because of process-induced material and device degradation. Here we report an approach that uses complementary metal oxide semiconductor (CMOS) field effect transistor compatible technology and hence demonstrate the specific label-free detection of below 100 femtomolar concentrations of antibodies as well as real-time monitoring of the cellular immune response. This approach eliminates the need for hybrid methods and enables system-scale integration of these sensors with signal processing and information systems. Additionally, the ability to monitor antibody binding and sense the cellular immune response in real time with readily available technology should facilitate widespread diagnostic applications. PMID:17268465

  18. Towards real-time VMAT verification using a prototype, high-speed CMOS active pixel sensor

    NASA Astrophysics Data System (ADS)

    Zin, Hafiz M.; Harris, Emma J.; Osmond, John P. F.; Allinson, Nigel M.; Evans, Philip M.

    2013-05-01

    This work investigates the feasibility of using a prototype complementary metal oxide semiconductor active pixel sensor (CMOS APS) for real-time verification of volumetric modulated arc therapy (VMAT) treatment. The prototype CMOS APS used region of interest read out on the chip to allow fast imaging of up to 403.6 frames per second (f/s). The sensor was made larger (5.4 cm × 5.4 cm) using recent advances in photolithographic technique but retains fast imaging speed with the sensor's regional read out. There is a paradigm shift in radiotherapy treatment verification with the advent of advanced treatment techniques such as VMAT. This work has demonstrated that the APS can track multi leaf collimator (MLC) leaves moving at 18 mm s-1 with an automatic edge tracking algorithm at accuracy better than 1.0 mm even at the fastest imaging speed. Evaluation of the measured fluence distribution for an example VMAT delivery sampled at 50.4 f/s was shown to agree well with the planned fluence distribution, with an average gamma pass rate of 96% at 3%/3 mm. The MLC leaves motion and linac pulse rate variation delivered throughout the VMAT treatment can also be measured. The results demonstrate the potential of CMOS APS technology as a real-time radiotherapy dosimeter for delivery of complex treatments such as VMAT.

  19. Low-dose performance of wafer-scale CMOS-based X-ray detectors

    NASA Astrophysics Data System (ADS)

    Maes, Willem H.; Peters, Inge M.; Smit, Chiel; Kessener, Yves; Bosiers, Jan

    2015-03-01

    Compared to published amorphous-silicon (TFT) based X-ray detectors, crystalline silicon CMOS-based active-pixel detectors exploit the benefits of low noise, high speed, on-chip integration and featuring offered by CMOS technology. This presentation focuses on the specific advantage of high image quality at very low dose levels. The measurement of very low dose performance parameters like Detective Quantum Efficiency (DQE) and Noise Equivalent Dose (NED) is a challenge by itself. Second-order effects like defect pixel behavior, temporal and quantization noise effects, dose measurement accuracy and limitation of the x-ray source settings will influence the measurements at very low dose conditions. Using an analytical model to predict the low dose behavior of a detector from parameters extracted from shot-noise limited dose levels is presented. These models can also provide input for a simulation environment for optimizing the performance of future detectors. In this paper, models for predicting NED and the DQE at very low dose are compared to measurements on different CMOS detectors. Their validity for different sensor and optical stack combinations as well as for different x-ray beam conditions was validated.

  20. On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS.

    PubMed

    Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

    2016-01-01

    An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<-9 dB) with excellent transmission efficiency (averagely -1.9 dB) from 110 GHz-325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author's knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology.

  1. On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS.

    PubMed

    Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

    2016-01-01

    An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<-9 dB) with excellent transmission efficiency (averagely -1.9 dB) from 110 GHz-325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author's knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology. PMID:27444782

  2. On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS

    NASA Astrophysics Data System (ADS)

    Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

    2016-07-01

    An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<-9 dB) with excellent transmission efficiency (averagely -1.9 dB) from 110 GHz-325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology.

  3. High-performance CMOS image sensors at BAE SYSTEMS Imaging Solutions

    NASA Astrophysics Data System (ADS)

    Vu, Paul; Fowler, Boyd; Liu, Chiao; Mims, Steve; Balicki, Janusz; Bartkovjak, Peter; Do, Hung; Li, Wang

    2012-07-01

    In this paper, we present an overview of high-performance CMOS image sensor products developed at BAE SYSTEMS Imaging Solutions designed to satisfy the increasingly challenging technical requirements for image sensors used in advanced scientific, industrial, and low light imaging applications. We discuss the design and present the test results of a family of image sensors tailored for high imaging performance and capable of delivering sub-electron readout noise, high dynamic range, low power, high frame rates, and high sensitivity. We briefly review the performance of the CIS2051, a 5.5-Mpixel image sensor, which represents our first commercial CMOS image sensor product that demonstrates the potential of our technology, then we present the performance characteristics of the CIS1021, a full HD format CMOS image sensor capable of delivering sub-electron read noise performance at 50 fps frame rate at full HD resolution. We also review the performance of the CIS1042, a 4-Mpixel image sensor which offers better than 70% QE @ 600nm combined with better than 91dB intra scene dynamic range and about 1 e- read noise at 100 fps frame rate at full resolution.

  4. A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Kaiming, Nie; Suying, Yao; Jiangtao, Xu; Zhaorui, Jiang

    2014-03-01

    A 10-bit ratio-independent switch-capacitor (SC) cyclic analog-to-digital converter (ADC) with offset canceling for a CMOS image sensor is presented. The proposed ADC completes an N-bit conversion in 1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversion characteristic of the proposed cyclic ADC is inherently insensitive both to capacitor ratio and to amplifier offset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18-μm one-poly four-metal CMOS technology. The measured results indicate that the ADC has a signal-to-noise and distortion ratio (SNDR) of 53.6 dB and a DNL of +0:12/-0:14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 μW with a 1.8 V supply, and its area is 0.03 × 0.8 mm2.

  5. Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

    NASA Technical Reports Server (NTRS)

    Feller, A.; Lombardi, T.

    1978-01-01

    Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

  6. Star sensor image acquisition and preprocessing hardware system based on CMOS image sensor and FGPA

    NASA Astrophysics Data System (ADS)

    Hao, Xuetao; Jiang, Jie; Zhang, Guangjun

    2003-09-01

    Star Sensor is an avionics instrument used to provide the absolute 3-axis attitude of a spacecraft utilizing star observations. It consists of an electronic camera and associated processing electronics. As outcome of advancing state-of-the-art, new generation star sensor features faster, lower cost, power dissipation and size than the first generation star sensor. This paper describes a star sensor anterior image acquisition and pre-processing hardware system based on CMOS image-sensor and FPGA technology. Practically, star images are produced by a simple simulator on PC, acquired by CMOS image sensor, pre-processed by FPGA, saved in SRAM, read out by EPP protocol and validated by an image process software on PC. The hardware part of system acquires images thought CMOS image-sensor controlled by FPGA, then processes image data by a circuit module of FPGA, and save images to SRAM for test. Basic image data for star recognition and attitude determination of spacecrafts are provided by it. As an important reference for developing star sensor prototype, the system validates the performance advantages of new generation star sensor.

  7. CMOS Active Pixel Sensors as energy-range detectors for proton Computed Tomography

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Evans, P. M.; Green, S.; Manolopoulos, S.; Nieto-Camero, J.; Parker, D. J.; Poludniowski, G.; Price, T.; Waltham, C.; Allinson, N. M.

    2015-06-01

    Since the first proof of concept in the early 70s, a number of technologies has been proposed to perform proton CT (pCT), as a means of mapping tissue stopping power for accurate treatment planning in proton therapy. Previous prototypes of energy-range detectors for pCT have been mainly based on the use of scintillator-based calorimeters, to measure proton residual energy after passing through the patient. However, such an approach is limited by the need for only a single proton passing through the energy-range detector in a read-out cycle. A novel approach to this problem could be the use of pixelated detectors, where the independent read-out of each pixel allows to measure simultaneously the residual energy of a number of protons in the same read-out cycle, facilitating a faster and more efficient pCT scan. This paper investigates the suitability of CMOS Active Pixel Sensors (APSs) to track individual protons as they go through a number of CMOS layers, forming an energy-range telescope. Measurements performed at the iThemba Laboratories will be presented and analysed in terms of correlation, to confirm capability of proton tracking for CMOS APSs.

  8. On-chip sub-terahertz surface plasmon polariton transmission lines in CMOS

    PubMed Central

    Liang, Yuan; Yu, Hao; Zhang, Hao Chi; Yang, Chang; Cui, Tie Jun

    2015-01-01

    A low-loss and low-crosstalk surface-wave transmission line (T-line) is demonstrated at sub-THz in CMOS. By introducing periodical sub-wavelength structures onto the metal transmission line, surface plasmon polaritons (SPP) are excited and propagate signals via a strongly localized surface wave. Two coupled SPP T-lines and two quasi-TEM T-lines are both fabricated on-chip, each with a separation distance of 2.4 μm using standard 65 nm CMOS technology. Measurement results show that the SPP T-lines achieve wideband reflection coefficient lower than −14 dB and crosstalk ratio better than −24 dB, which is 19 dB lower on average than the traditional T-lines from 220 GHz to 325 GHz. The demonstrated compact and wideband SPP T-lines have shown great potential for future realization of highly dense on-chip sub-THz communications in CMOS. PMID:26445889

  9. Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter

    SciTech Connect

    Zhang, Y.; Hu-Guo, C.; Husson, D.; Hu, Y.

    2011-07-01

    Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial points of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)

  10. A generalized CMOS-MEMS platform for micromechanical resonators monolithically integrated with circuits

    NASA Astrophysics Data System (ADS)

    Chen, Wen-Chien; Fang, Weileun; Li, Sheng-Shian

    2011-06-01

    A generalized foundry-oriented CMOS-MEMS platform well suited for integrated micromechanical resonators alongside IC amplifiers has been developed for commercial multi-user purpose and demonstrated with a fast turnaround time of only 3 months and a variety of design flexibilities for resonator applications. With this platform, different configurations of capacitively-transduced resonators monolithically integrated with their amplifier circuits, spanning frequencies from 500 kHz to 14.5 MHz, have been realized with resonator Q's ranging between 700 and 3500. This platform, specifically featured with various configurations of structural materials, multi-dimensional displacements, different arrangements of mechanical boundary conditions, tiny supports of resonators, large transduction areas, well-defined anchors and performance enhancement scaling with IC fabrication technology, offers a variety of flexible design options targeted for sensor, timing reference, and RF applications. In addition, resonators consisting of metal-oxide composite structures fabricated by this platform offer an effective temperature compensation scheme for the first time in CMOS-MEMS resonators, showing TCf six times better than that of resonators merely made by CMOS metals.

  11. Low-noise CMOS SPAD arrays with in-pixel time-to-digital converters

    NASA Astrophysics Data System (ADS)

    Tosi, Alberto; Villa, Federica; Bronzi, Danilo; Zou, Yu; Lussana, Rudi; Tamborini, Davide; Tisa, Simone; Durini, Daniel; Weyers, Sascha; Pashen, Uwe; Brockherde, Werner; Zappa, Franco

    2014-05-01

    We present our latest results concerning CMOS Single-Photon Avalanche Diode (SPAD) arrays for high-throughput parallel single-photon counting. We exploited a high-voltage 0.35 μm CMOS technology in order to develop low-noise CMOS SPADs. The Dark Count Rate is 30 cps at room temperature for 30 μm devices, increases to 2 kcps for 100 μm SPADs and just to 100 kcps for 500 μm ones. Afterpulsing is less than 1% for hold-off time longer than 50 ns, thus allowing to reach high count rates. Photon Detection Efficiency is > 50% at 420 nm, > 40% below 500 nm and is still 5% at 850 nm. Timing jitter is less than 100 ps (FWHM) in SPADs with active area diameter up to 50 μm. We developed CMOS SPAD imagers with 150 μm pixel pitch and 30 μm SPADs. A 64×32 SPAD array is based on pixels including three 9-bit counters for smart phase-resolved photon counting up to 100 kfps. A 32x32 SPAD array includes 1024 10-bit Time-to-Digital Converters (TDC) with 300 ps resolution and 450 ps single-shot precision, for 3D ranging and FLIM. We developed also linear arrays with up to 60 pixels (with 100 μm SPAD, 150 μm pitch and in-pixel 250 ps TDC) for time-resolved parallel spectroscopy with high fill factor.

  12. A low-temperature bridge-input CMOS circuit for low-impedance detector

    NASA Astrophysics Data System (ADS)

    Yuan, HongHui; Chen, YongPing

    2014-09-01

    Low-impedance long-wave infrared detectors (the wavelength longer than 10 microns) have very important applications in cryogenic aim detection, super-distance detection, anti-jamming target identify and so on. Therefore the research in the field of infrared detector technology is of importance. At present, no low-impedance photoconductive detectors are integrated with CMOS circuit. To design low-temperature CMOS circuit being fit for low impedance infrared photoconductive detector and realize high performance IR imaging, using differential amplifier with symmetrical positive and negative power is necessary, the low-resist detector is connected between an input and grounding, the corresponding low resistance is connected between another input and grounding, a larger feedback resistor is used between negative input and output, this structure can effectively solve the matching problem of low-impedance and high-impedance CMOS. In addition, the noise voltage from VBIAS terminal can be effectively reduced by increasing the ratio of the bias resistor and the detector resistance. The whole circuit is designed two grade. The first grade is adopted bridge input structure, this structure is fit for low impedance detector. The positive amplifying method is applied in second grade . The first grade feedback resistance is designed 1M ohm, the circuit is supplied by +/-1.5V. The testing showed that the circuit can work well when it connects with low-impedance infrared photoconductive detector at the liquid nitrogen low temperature. The magnification is up to 30000 times, 3dB bandwidth is more than 4kHz, the equivalent input noise is near 1.5 micron volts. This circuit has perfectly solved the matching problem between high impedance CMOS circuit and low impedance detector.

  13. Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

    2008-01-01

    Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

  14. 1984 Joint Congress: CGU and CMOS

    NASA Astrophysics Data System (ADS)

    Camfield, P. A.

    The Canadian Geophysical Union (CGU) had a very successful joint meeting with the Canadian Meteorological and Oceanographic Society (CMOS) at Dalhousie University in Halifax, Nova Scotia, May 29 to June 1, 1984. Thirty-five scientific sessions were held in the 4-day meeting period.The invited speaker for CGU at the plenary session, David Simpson of Lamont-Doherty Geological Observatory, spoke about the Halifax Explosion of 1917 in terms of a seismic event. The 2.6-kt explosion was the largest man-made explosion prior to the detonation of the first atomic bombs. The effective seismic magnitude of the event may have been m, = 2.5-3.0.

  15. CMOS imager for pointing and tracking applications

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

    2006-01-01

    Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

  16. Latchup in CMOS devices from heavy ions

    NASA Technical Reports Server (NTRS)

    Soliman, K.; Nichols, D. K.

    1983-01-01

    It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

  17. Integrated on-chip 0.35 μm BiCMOS current-mode DC-DC buck converter

    NASA Astrophysics Data System (ADS)

    Lee, Chan-Soo; Kim, Nam-Soo; Gendensuren, Munkhsuld; Choi, Jae-Ho; Choi, Joong-Ho

    2012-12-01

    A current-mode DC-DC buck converter with a fully integrated power module is presented in this article. The converter is implemented using BiCMOS technology in amplifier and power MOSFET in a current sensor. The current sensor is realised by the power lateral double-diffused MOSFET with the aspect ratio much larger than that of a matched p-MOSFET. In addition, BiCMOS technology is applied in the error amplifier for an accurate current sensing and a fast transient response. The DC-DC converter is fabricated with 0.35 µm BiCMOS process. Experimental results show that the fully integrated converter operates at 1.3 MHz switching frequency with a supply voltage of 5 V. The output DC voltage is obtained as expected and the output ripple is controlled to be within 2% with a 30 µH off-chip inductor and 100 µF off-chip capacitor.

  18. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    NASA Astrophysics Data System (ADS)

    Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  19. Depleted CMOS pixels for LHC proton-proton experiments

    NASA Astrophysics Data System (ADS)

    Wermes, N.

    2016-07-01

    While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

  20. Implementation of CMOS Millimeter-Wave Devices for Rotational Spectroscopy

    NASA Astrophysics Data System (ADS)

    Drouin, Brian; Tang, Adrian; Schlecht, Erich T.; Daly, Adam M.; Brageot, Emily; Gu, Qun Jane; Ye, Yu; Shu, Ran; Chang, M.-C. Frank; Kim, Rod M.

    2015-06-01

    The extension of radio-frequency CMOS circuitry into millimeter wavelengths promises the extension of spectroscopic techniques in compact, power efficient systems. We are now exploring the use of CMOS millimeter devices for low-mass, low-power instrumentation capable of remote or in-situ detection of gas composition during space missions. This effort focuses on the development of a semi-confocal Fabry-Perot cavity with mm-wavelength CMOS transmitter and receiver attached directly to a cavity coupler. Placement of the devices within the cavity structure bypasses problems encountered with signal injection and extraction in traditional cavity designs and simultaneously takes full advantage of the miniaturized form of the CMOS hardware. The presentation will provide an overview of the project and details of the accomplishments thus far, including the development and testing of a pulse modulated 83-98 GHz transmitter.

  1. Tests of commercial colour CMOS cameras for astronomical applications

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

    2013-12-01

    We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

  2. A safety monitoring system for taxi based on CMOS imager

    NASA Astrophysics Data System (ADS)

    Liu, Zhi

    2005-01-01

    CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

  3. Self-testable CMOS thermopile-based infrared imager

    NASA Astrophysics Data System (ADS)

    Charlot, Benoit; Parrain, F.; Mir, Salvador; Courtois, Bernard

    2001-04-01

    This paper describes a CMOS-compatible self-testable uncooled InfraRed (IR) imager that can be used in multiple applications such as overheating detection, night vision, and earth tracking for satellite positioning. The imager consists of an array of thermal pixels that sense an infrared radiation. Each pixel is implemented as a front-side bulk micromachined membrane suspended by four arms, each arm containing a thermopile made of Poly/Al thermocouples. The imager has a pixel self-test function that can be activated off-line in the field for validation and maintenance purposes, with an on-chip test signal generation that requires only slight modifications in the pixel design. The self-test of a pixel takes about 15 ms. The area overhead required by the test electronics does not imply any reduction of the pixel fill factor, since the electronics fits in the pixel silicon boundary. However, the additional self-test circuitry contributes to a small increase in the thermal conductance of a pixel due to the wiring of a heating resistor over the suspended arms. The self-test capability of the imager allows for a production test with a standard test equipment, without the need of special infrared sources and the associated optical equipment. A prototype with 8 X 8 pixels is currently in fabrication for validation of the self-test approach. In this prototype, each pixel occupies an area of 200 X 200 micrometer2, with a membrane size of 90 X 90 micrometer2 (fill factor of 0.2). Simulation results indicate a pixel thermal conductance of 22.6 (mu) W/K, giving a responsivity of 138 V/W, with a thermocouple Seebeck coefficient that has been measured at 248 (mu) V/K for the 0.6 micrometer CMOS technology used. The noise equivalent power (considering only Johnson noise in the thermopile) is calculated as 0.18 nW.H-1/2 with a detectivity of 5.03 X 107 cm.Hz1/2.W-1, in line with current state-of-the-art. Since the imager may need to measure irradiation intensities below 1(mu) W

  4. Tracking cancer cell proliferation on a CMOS capacitance sensor chip.

    PubMed

    Prakash, Somashekar Bangalore; Abshire, Pamela

    2008-05-15

    We report a novel technique for assessing cell proliferation that employs integrated capacitance sensors for monitoring the growth of anchorage-dependent living cells. The sensors measure substrate coupling capacitances of cells cultured on-chip in a standard in vitro environment. The biophysical phenomenon underlying the capacitive behavior of cells is the counterionic polarization around the insulating cell bodies when exposed to weak, low frequency electric fields. The sensors employ charge sharing for mapping sensed capacitance values in the fF range to output voltage signals. The sensor chip has been fabricated in a commercially available 0.5microm, 2-poly 3-metal CMOS technology. We report experimental results demonstrating sensor response to the adhesion of MDA-MB-231 breast cancer cells followed by their proliferation on the chip surface. On-chip capacitance sensing offers a non-invasive, label-free, easy-to-use, miniaturized technique with real-time monitoring capability for tracking cell proliferation in vitro. PMID:18281207

  5. A new architecture of current-mode CMOS TDI Sensor

    NASA Astrophysics Data System (ADS)

    Ji, Cheng; Chen, Yongping

    2015-10-01

    Nowadays, CMOS sensors still suffer from the problem of low SNR, especially in the stage of low illumination and high relative scanning velocity. Lots of methods have been develop to overcome this problem. Among these researches, TDI (Time Delay Integration) architecture is a more natural choice, which is natively supported by CCD sensors. In this paper a new kind of proposed current-mode sensor is used to achieve TDI operation in analog domain. The circuit is composed of three main parts. At first, a current-type pixel is proposed, in which the active MOSFET is operated in the triode region to ensure the output current is linearly dependent on the gate voltage and avoid the reduction of threshold voltage in the traditional voltage mode pixels, such as 3T, 4T which use the source followers as its active part. Then a discrete double sampling (DDS) unit, which is operated in the form of currents is used to efficiently reduce the fixed pattern noise (FPN) and make the output is independent of reset voltage of pixels. For accumulation, an improved current mirror adder under controlled of timing circuits is proposed to overcome the problem of saturation suffered in voltage domain. Some main noise sources, especially come from analog sample and holds capacitors and switches is analyzed. Finally, simulation results with CSMC 0.5um technology and Cadence IC show that the proposed method is reasonable and efficient to improve the SNR.

  6. Total dose hardness of three commercial CMOS microelectronics foundries

    SciTech Connect

    Osborn, J.V.; Lacoe, R.C.; Mayer, D.C.; Yabiku, G.

    1998-06-01

    The authors have measured the effects of total ionizing dose (TID) on CMOS FETs, ring oscillators and field-oxide transistor test structures fabricated at three different commercial foundries with four different processes. The foundries spanned a range of integration levels and included Hewlett-Packard (HP) 0.5 {micro}m and 0.8 {micro}m processes, an Orbit 1.2 {micro}m process, and an AMI 1.6 {micro}m process. They found that the highest tolerance to TID was for the HP 0.5 {micro}m process, where the shift in NMOS threshold voltage was less than 40 mV at 300 krad. An examination of the dependence of the threshold voltage shift on gate oxide thickness indicated that oxides of the different commercial processes were of similar quality, and that the improvement in the total dose tolerance of the HP 0.5 {micro}m technology is associated with the scaling of the gate oxide. Measurements on field-oxide transistors from the HP 0.5 {micro}m process were shown not to invert for signal voltages at 300 krad, maintaining the integrity of the LOCOS isolation.

  7. A CMOS Smart Thermal Sensor for Biomedical Application

    NASA Astrophysics Data System (ADS)

    Lee, Ho-Yin; Chen, Shih-Lun; Luo, Ching-Hsing

    This paper describes a smart thermal sensing chip with an integrated vertical bipolar transistor sensor, a Sigma Delta Modulator (SDM), a Micro-Control Unit (MCU), and a bandgap reference voltage generator for biomedical application by using 0.18μm CMOS process. The npn bipolar transistors with the Deep N-Well (DNW) instead of the pnp bipolar transistor is first adopted as the sensor for good isolation from substrate coupling noise. In addition to data compression, Micro-Control Unit (MCU) plays an important role for executing auto-calibration by digitally trimming the bipolar sensor in parallel to save power consumption and to reduce feedback complexity. It is different from the present analog feedback calibration technologies. Using one sensor, instead of two sensors, to create two differential signals in 180° phase difference input to SDM is also a novel design of this work. As a result, in the range of 0°C to 80°C or body temperature (37±5°C), the inaccuracy is less than ±0.1°C or ±0.05°C respectively with one-point calibration after packaging. The average power consumption is 268.4μW with 1.8V supply voltage.

  8. A hierarchical approach to test generation for CMOS VLSI circuits

    NASA Astrophysics Data System (ADS)

    Weening, Edward Christiaan

    A hierarchical approach to the automatic test pattern generation for large digital VLSI circuits, fabricated in CMOS technology, is developed and implemented. The use of information on the circuit's hierarchy, which is readily available from most modern CAD (Computer Aided Design) systems, speeds up the test generation process considerably and enhances the quality of the tests generated. The hierarchical test generation tool can also be integrated in future CAD systems making test generation and testability enhancement during circuit design feasible. The hierarchical approach is described at the switch, functional, and behavioral level. A test pattern generation algorithm at the switch level is presented. Test generation and fault simulation algorithms both using OBDD (Ordered Binary Decision Diagram) functional descriptions of the circuit modules are presented. A test plan generation method at the behavioral level is presented. Practical results show that the hierarchical approach to test generation is more efficient than a conventional, non-hierarchical approach, especially for switch level faults. The results also show that the use of Design For Testability (DFT) circuitry is supported at the behavioral level.

  9. sCMOS detector for imaging VNIR spectrometry

    NASA Astrophysics Data System (ADS)

    Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

    2013-09-01

    The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

  10. Improved CMOS field isolation using Germaniun/Boron implantation

    SciTech Connect

    Pfiester, J.R.; Alvis, J.R. )

    1988-08-01

    A novel germanium/boron implantation technique for improving the electrical field isolation for high-density CMOS circuits is demonstrated. Germanium implantation causes a reduction in dopant diffusion and segregation during field oxidation and is shown to increase the p-well field threshold voltage by as much as 40 percent with no significant degradation to junction or device performance. Selective germanium implantation with a blanket boron field implant can also improve the electrical field isolation behavior for CMOS circuits.

  11. CMOS front end electronics for the ATLAS muon detector

    SciTech Connect

    Huth, J.; Oliver, J.; Hazen, E.; Shank, J.

    1997-12-31

    An all-CMOS design for an integrated ASD (Amplifier-Shaper-Discriminator) chip for readout of the ATLAS Monitored Drift Tubes (MDTs) is presented. Eight channels of charge-sensitive preamp, two-stage pole/zero shaper, Wilkinson ADC and discriminator with programmable hysteresis are integrated on a single IC. Key elements have been prototyped in 1.2 and 0.5 micron CMOS operating at 5V and 3.3V respectively.

  12. Development of a novel pixel-level signal processing chain for fast readout 3D integrated CMOS pixel sensors

    NASA Astrophysics Data System (ADS)

    Fu, Y.; Torheim, O.; Hu-Guo, C.; Degerli, Y.; Hu, Y.

    2013-03-01

    In order to resolve the inherent readout speed limitation of traditional 2D CMOS pixel sensors, operated in rolling shutter readout, a parallel readout architecture has been developed by taking advantage of 3D integration technologies. Since the rows of the pixel array are zero-suppressed simultaneously instead of sequentially, a frame readout time of a few microseconds is expected for coping with high hit rates foreseen in future collider experiments. In order to demonstrate the pixel readout functionality of such a pixel sensor, a 2D proof-of-concept chip including a novel pixel-level signal processing chain was designed and fabricated in a 0.13 μm CMOS technology. The functionalities of this chip have been verified through experimental characterization.

  13. CMOS pixel sensors on high resistive substrate for high-rate, high-radiation environments

    NASA Astrophysics Data System (ADS)

    Hirono, Toko; Barbero, Marlon; Breugnon, Patrick; Godiot, Stephanie; Gonella, Laura; Hemperek, Tomasz; Hügging, Fabian; Krüger, Hans; Liu, Jian; Pangaud, Patrick; Peric, Ivan; Pohl, David-Leon; Rozanov, Alexandre; Rymaszewski, Piotr; Wang, Anqing; Wermes, Norbert

    2016-09-01

    A depleted CMOS active pixel sensor (DMAPS) has been developed on a substrate with high resistivity in a high voltage process. High radiation tolerance and high time resolution can be expected because of the charge collection by drift. A prototype of DMAPS was fabricated in a 150 nm process by LFoundry. Two variants of the pixel layout were tested, and the measured depletion depths of the variants are 166 μm and 80 μm. We report the results obtained with the prototype fabricated in this technology.

  14. Design and implementation of IEEE 802.11ac MAC controller in 65 nm CMOS process

    NASA Astrophysics Data System (ADS)

    Peng, Cheng; Bin, Wu; Yong, Hei

    2016-02-01

    An IEEE-802.11ac-1*1 wireless LAN system-on-a-chip (SoC) that integrates an analog front end, a digital base-band processor and a media access controller has been implemented in 65 nm CMOS technology. It can provide significantly increased throughput, high efficiency rate selection, and fully backward compatibility with the existing 802.11a/n WLAN protocols. Especially the measured maximum throughput of UDP traffic can be up to 267 Mbps. Project supported by the National Great Specific Project of China (No. 2012ZX03004004_001).

  15. A 12 GHz low-jitter LC-VCO PLL in 130 nm CMOS

    NASA Astrophysics Data System (ADS)

    You, Y.; Chen, J.; Feng, Y.; Tang, Y.; Huang, D.; Rui, W.; Gong, D.; Liu, T.; Ye, J.

    2015-03-01

    We present a wideband low-jitter LC-VCO phase-locked loop in 130 nm CMOS technology for high speed serial link applications. The PLL covers a 5.6 GHz to 13.4 GHz frequency range by using two LC-VCO cores with an RMS jitter of 370 fs. The single event effects testing is performed with a neutron beam at Los Alamos National Laboratory and no frequency disturbance is found over the test period. The PLL consumes 50.88 mW of power under a 1.2 V power supply.

  16. Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

    NASA Technical Reports Server (NTRS)

    Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.; Ackland, B.; Dickinson, A.; Eid, E.; Inglis, D.

    1994-01-01

    This paper describes ongoing research and development of CMOS active pixel image sensors for low cost commercial applications. A number of sensor designs have been fabricated and tested in both p-well and n-well technologies. Major elements in the development of the sensor include on-chip analog signal processing circuits for the reduction of fixed pattern noise, on-chip timing and control circuits and on-chip analog-to-digital conversion (ADC). Recent results and continuing efforts in these areas will be presented.

  17. Development of a 750×750 pixels CMOS imager sensor for tracking applications

    NASA Astrophysics Data System (ADS)

    Larnaudie, Franck; Guardiola, Nicolas; Saint-Pé, Olivier; Vignon, Bruno; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Estribeau, Magali

    2004-06-01

    Solid-state optical sensors are now commonly used in space applications (navigation cameras, astronomy imagers, tracking sensors...). Although the charge-coupled devices are still widely used, the CMOS image sensor (CIS), which performances are continuously improving, is a strong challenger for Guidance, Navigation and Control (GNC) systems. This paper describes a 750×750 pixels CMOS image sensor that has been specially designed and developed for star tracker and tracking sensor applications. Such detector, that is featuring smart architecture enabling very simple and powerful operations, is built using the AMIS 0.5μm CMOS technology. It contains 750×750 rectangular pixels with 20μm pitch. The geometry of the pixel sensitive zone is optimized for applications based on centroiding measurements. The main feature of this device is the on-chip control and timing function that makes the device operation easier by drastically reducing the number of clocks to be applied. This powerful function allows the user to operate the sensor with high flexibility: measurement of dark level from masked lines, direct access to the windows of interest... A temperature probe is also integrated within the CMOS chip allowing a very precise measurement through the video stream. A complete electro-optical characterization of the sensor has been performed. The major parameters have been evaluated: dark current and its uniformity, read-out noise, conversion gain, Fixed Pattern Noise, Photo Response Non Uniformity, quantum efficiency, Modulation Transfer Function, intra-pixel scanning. The characterization tests are detailed in the paper. Co60 and protons irradiation tests have been also carried out on the image sensor and the results are presented. The specific features of the 750×750 image sensor such as low power CMOS design (3.3V, power consumption <100mW), natural windowing (that allows efficient and robust tracking algorithms), simple proximity electronics (because of the on

  18. Analysis on the positive dependence of channel length on ESD failure current of a GGNMOS in a 5 V CMOS

    NASA Astrophysics Data System (ADS)

    Daoxun, Wu; Lingli, Jiang; Hang, Fan; Jian, Fang; Bo, Zhang

    2013-02-01

    Contrary to general understanding, a test result shows that devices with a shorter channel length have a degraded ESD performance in the advanced silicided CMOS process. Such a phenomenon in a gate-grounded NMOSFET (GGNMOS) was investigated, and the current spreading effect was verified as the predominant factor. Due to transmission line pulse (TLP) measurements and Sentaurus technology computer aided design (TCAD) 2-D numerical simulations, parameters such as current gain, on-resistance and power density were discussed in detail.

  19. New interpretation of photonic yield processes (450-750nm) in multi-junction Si CMOS LEDs: simulation and analyses

    NASA Astrophysics Data System (ADS)

    Snyman, Lukas W.; Bellotti, Enrico

    2010-02-01

    Emission levels in the 450-750nm range of about 80-100 fold higher than that emitted by single junction avalanche LEDs, has been obtained. CMOS Si LED p+-i-np+ structures were modeled in order to investigate the effect of various depletion layer profiles and defect engineering on the photonic transitions in the 1.4 to 2.8 eV, 450-750nnm regime. Modeling and device simulation results showed that by utilizing a short lowly doped layer in between a highly doped p+ layer and n layer can enhance the photonic yields by orders of magnitude through an increase in the dynamic carrier densities in the device and favoring enhanced lateral multiplication processes. The electric field profile should be of the order of 5 x 105 V.cm-1 and about 0.5 micron long. Injecting of carriers of opposite charge type from an opposing forward bias junction further enhance the photonic yield. These models and interpretations is confirmed by analyses of device designs as realized in 1.2 μm and 0.35 CMOS technology. The device design involved normal CMOS design and processing procedures with no excessive micro-dimensioning. The current devices operated in the 8-10V, 1uA - 2mA regime and yield emission intensities of up to 100 nW.μm-2. The current emission levels are about three orders higher than the low frequency detectability limit of Si CMOS p-n detectors of corresponding area. The particular design favors higher emission levels towards the 750nm wavelength region. This makes diverse electro-optical applications possible such as optical communication on chip, diverse optical signal processing and wave-guiding. It also enables realization of on chip Micro-Optical-Electro-Mechanical Sensors (MOEMS), which could lead to the development of so-called "smart chips" utilizing standard CMOS integrated circuitry.

  20. Characterization of the embedded micromechanical device approach to the monolithic integration of MEMS with CMOS

    SciTech Connect

    Smith, J.H.; Montague, S.; Sniegowski, J.J.; Murray, J.R.

    1996-10-01

    Recently, a great deal of interest has developed in manufacturing processes that allow the monolithic integration of MicroElectroMechanical Systems (MEMS) with driving, controlling, and signal processing electronics. This integration promises to improve the performance of micromechanical devices as well as lower the cost of manufacturing, packaging, and instrumenting these devices by combining the micromechanical devices with a electronic devices in the same manufacturing and packaging process. In order to maintain modularity and overcome some of the manufacturing challenges of the CMOS-first approach to integration, we have developed a MEMS-first process. This process places the micromechanical devices in a shallow trench, planarizes the wafer, and seals the micromechanical devices in the trench. Then, a high-temperature anneal is performed after the devices are embedded in the trench prior to microelectronics processing. This anneal stress-relieves the micromechanical polysilicon and ensures that the subsequent thermal processing associated with fabrication of the microelectronic processing does not adversely affect the mechanical properties of the polysilicon structures. These wafers with the completed, planarized micromechanical devices are then used as starting material for conventional CMOS processes. The circuit yield for the process has exceeded 98%. A description of the integration technology, the refinements to the technology, and wafer-scale parametric measurements of device characteristics is presented. Additionally, the performance of integrated sensing devices built using this technology is presented.

  1. CMOS Hybrid Pixel Detectors for Scientific, Industrial and Medical Applications

    NASA Astrophysics Data System (ADS)

    Broennimann, Christian

    2009-03-01

    Crystallography is the principal technique for determining macromolecular structures at atomic resolution and uses advantageously the high intensity of 3rd generation synchrotron X-ray sources . Macromolecular crystallography experiments benefit from excellent beamline equipment, recent software advances and modern X-ray detectors. However, the latter do not take full advantage of the brightness of modern synchrotron sources. CMOS Hybrid pixel array detectors, originally developed for high energy physics experiments, meet these requirements. X-rays are recorded in single photon counting mode and data thus are stored digitally at the earliest possible stage. This architecture leads to several advantages over current detectors: No detector noise is added to the signal. Readout time is reduced to a few milliseconds. The counting rates are matched to beam intensities at protein crystallography beamlines at 3rd generation synchrotrons. The detector is not sensitive to X-rays during readout; therefore no mechanical shutter is required. The detector has a very sharp point spread function (PSF) of one pixel, which allows better resolution of adjacent reflections. Low energy X-rays can be suppressed by the comparator At the Paul Scherrer Institute (PSI) in Switzerland the first and largest array based on this technology was constructed: The Pilatus 6M detector. The detector covers an area of 43.1 x 44.8 cm2 , has 6 million pixels and is read out noise free in 3.7 ms. Since June 2007 the detector is in routine operation at the beamline 6S of the Swiss Light Source (SLS). The company DETCRIS Ltd, has licensed the technology from PSI and is commercially offering the PILATUS detectors. Examples of the wide application range of the detectors will be shown.

  2. On noise in time-delay integration CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Levski, Deyan; Choubey, Bhaskar

    2016-05-01

    Time delay integration sensors are of increasing interest in CMOS processes owing to their low cost, power and ability to integrate with other circuit readout blocks. This paper presents an analysis of the noise contributors in current day CMOS Time-Delay-Integration image sensors with various readout architectures. An analysis of charge versus voltage domain readout modes is presented, followed by a noise classification of the existing Analog Accumulator Readout (AAR) and Digital Accumulator Readout (DAR) schemes for TDI imaging. The analysis and classification of existing readout schemes include, pipelined charge transfer, buffered direct injection, voltage as well as current-mode analog accumulators and all-digital accumulator techniques. Time-Delay-Integration imaging modes in CMOS processes typically use an N-number of readout steps, equivalent to the number of TDI pixel stages. In CMOS TDI sensors, where voltage domain readout is used, the requirements over speed and noise of the ADC readout chain are increased due to accumulation of the dominant voltage readout and ADC noise with every stage N. Until this day, the latter is the primary reason for a leap-back of CMOS TDI sensors as compared to their CCD counterparts. Moreover, most commercial CMOS TDI implementations are still based on a charge-domain readout, mimicking a CCD-like operation mode. Thus, having a good understanding of each noise contributor in the signal chain, as well as its magnitude in different readout architectures, is vital for the design of future generation low-noise CMOS TDI image sensors based on a voltage domain readout. This paper gives a quantitative classification of all major noise sources for all popular implementations in the literature.

  3. On noise in time-delay integration CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Levski, Deyan; Choubey, Bhaskar

    2016-05-01

    Time delay integration sensors are of increasing interest in CMOS processes owing to their low cost, power and ability to integrate with other circuit readout blocks. This paper presents an analysis of the noise contributors in current day CMOS Time-Delay-Integration image sensors with various readout architectures. An analysis of charge versus voltage domain readout modes is presented, followed by a noise classification of the existing Analog Accumulator Readout (AAR) and Digital Accumulator Readout (DAR) schemes for TDI imaging. The analysis and classification of existing readout schemes include, pipelined charge transfer, buffered direct injection, voltage as well as current-mode analog accumulators and all-digital accumulator techniques. Time-Delay-Integration imaging modes in CMOS processes typically use an N-number of readout steps, equivalent to the number of TDI pixel stages. In CMOS TDI sensors, where voltage domain readout is used, the requirements over speed and noise of the ADC readout chain are increased due to accumulation of the dominant voltage readout and ADC noise with every stage N. Until this day, the latter is the primary reason for a leap-back of CMOS TDI sensors as compared to their CCD counterparts. Moreover, most commercial CMOS TDI implementations are still based on a charge-domain readout, mimicking a CCD-like operation mode. Thus, having a good understanding of each noise contributor in the signal chain, as well as its magnitude in different readout architectures, is vital for the design of future generation low-noise CMOS TDI image sensors based on a voltage domain readout. This paper gives a quantitative classification of all major noise sources for all popular implementations in the literature.

  4. Simulation of SEU transients in CMOS ICs

    SciTech Connect

    Kaul, N.; Bhuva, B.L.; Kerns, S.E. )

    1991-12-01

    This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE.

  5. Charge collection and non-ionizing radiation tolerance of CMOS pixel sensors using a 0.18 μm CMOS process

    NASA Astrophysics Data System (ADS)

    Zhang, Ying; Zhu, Hongbo; Zhang, Liang; Fu, Min

    2016-09-01

    The proposed Circular Electron Positron Collider (CEPC) will be primarily aimed for precision measurements of the discovered Higgs boson. Its innermost vertex detector, which will play a critical role in heavy-flavor tagging, must be constructed with fine-pitched silicon pixel sensors with low power consumption and fast readout. CMOS pixel sensor (CPS), as one of the most promising candidate technologies, has already demonstrated its excellent performance in several high energy physics experiments. Therefore it has been considered for R&D for the CEPC vertex detector. In this paper, we present the preliminary studies to improve the collected signal charge over the equivalent input capacitance ratio (Q / C), which will be crucial to reduce the analog power consumption. We have performed detailed 3D device simulation and evaluated potential impacts from diode geometry, epitaxial layer properties and non-ionizing radiation damage. We have proposed a new approach to improve the treatment of the boundary conditions in simulation. Along with the TCAD simulation, we have designed the exploratory prototype utilizing the TowerJazz 0.18 μm CMOS imaging sensor process and we will verify the simulation results with future measurements.

  6. Radiation tolerant back biased CMOS VLSI

    NASA Technical Reports Server (NTRS)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  7. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications

    NASA Astrophysics Data System (ADS)

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-05-01

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V‑1 sec‑1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

  8. Towards a 10 μs, thin and high resolution pixelated CMOS sensor system for future vertex detectors

    NASA Astrophysics Data System (ADS)

    De Masi, R.; Amar-Youcef, S.; Baudot, J.; Bertolone, G.; Brogna, A.; Chon-Sen, N.; Claus, G.; Colledani, C.; Degerli, Y.; Deveaux, M.; Dorokhov, A.; Doziére, G.; Dulinski, W.; Gelin, M.; Goffe, M.; Fontaine, J. C.; Hu-Guo, Ch.; Himmi, A.; Jaaskelainen, K.; Koziel, M.; Morel, F.; Müntz, C.; Orsini, F.; Santos, C.; Schrader, C.; Specht, M.; Stroth, J.; Valin, I.; Voutsinas, G.; Wagner, F. M.; Winter, M.

    2011-02-01

    The physics goals of many high energy experiments require a precise determination of decay vertices, imposing severe constraints on vertex detectors (readout speed, granularity, material budget,…). The IPHC-IRFU collaboration developed a sensor architecture to comply with these requirements. The first full scale CMOS sensor was realised and equips the reference planes of the EUDET beam telescope. Its architecture is being adapted to the needs of the STAR (RHIC) and CBM (FAIR) experiments. It is a promising candidate for the ILC experiments and the ALICE detector upgrade (LHC). A substantial improvement to the CMOS sensor performances, especially in terms of radiation hardness, should come from a new fabrication technology with depleted sensitive volume. A prototype sensor was fabricated to explore the benefits of the technology. The crucial system integration issue is also currently being addressed. In 2009 the PLUME collaboration was set up to investigate the feasibility and performances of a light double sided ladder equipped with CMOS sensors, aimed primarily for the ILC vertex detector but also of interest for other applications such as the CBM vertex detector.

  9. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

    PubMed

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-05-09

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

  10. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

    PubMed

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-01-01

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. PMID:27157914

  11. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications

    PubMed Central

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-01-01

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V−1 sec−1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. PMID:27157914

  12. Novel CMOS time-delay integration using single-photon counting for high-speed industrial and aerospace applications

    NASA Astrophysics Data System (ADS)

    El-Desouki, Munir M.; Al-Azem, Badeea

    2014-03-01

    Time-delay integration (TDI) is a popular imaging technique that is used in many applications such as machine vision, dental scanning and satellite earth observation. One of the main advantages of using TDI imagers is the increased effective integration time that is achieved while maintaining high frame-rates. Another use for TDI imagers is with moving objects, such as the earth's surface or industrial machine vision applications, where integration time is limited in order to avoid motion blurs. Such technique may even find its way in mobile and consumer based imaging applications where the reduction in pixel size can limit the performance during low-light and high speed applications. Until recently, TDI was only used with charge-coupled devices (CCDs) mainly due to their charge transfer characteristics. CCDs however, are power consuming and slow when compared to CMOS technology and are no longer favorable for mobile applications. In this work, we report on novel single-photon counting based TDI technique that is implemented in standard CMOS technology allowing for complete camera-on-a-chip solution. The imager was fabricated in a standard CMOS 150 nm 5-metal digital process from LFoundry.

  13. Integrated CMOS dew point sensors for relative humidity measurement

    NASA Astrophysics Data System (ADS)

    Savalli, Nicolo; Baglio, Salvatore; Castorina, Salvatore; Sacco, Vincenzo; Tringali, Cristina

    2004-07-01

    This work deals with the development of integrated relative humidity dew point sensors realized by adopting standard CMOS technology for applications in various fields. The proposed system is composed by a suspended plate that is cooled by exploiting integrated Peltier cells. The cold junctions of the cells have been spread over the plate surface to improve the homogeneity of the temperature distribution over its surface, where cooling will cause the water condensation. The temperature at which water drops occur, named dew point temperature, is a function of the air humidity. Measurement of such dew point temperature and the ambient temperature allows to know the relative humidity. The detection of water drops is achieved by adopting a capacitive sensing strategy realized by interdigited fixed combs, composed by the upper layer of the adopted process. Such a capacitive sensor, together with its conditioning circuit, drives a trigger that stops the cooling of the plate and enables the reading of the dew point temperature. Temperature measurements are achieved by means of suitably integrated thermocouples. The analytical model of the proposed system has been developed and has been used to design a prototype device and to estimate its performances. In such a prototype, the thermoelectric cooler is composed by 56 Peltier cells, made by metal 1/poly 1 junctions. The plate has a square shape with 200 μm side, and it is realized by exploiting the oxide layers. Starting from the ambient temperature a temperature variation of ΔT = 15 K can be reached in 10 ms thus allowing to measure a relative humidity greater than 40%.

  14. A 0.18μm CMOS low-power radiation sensor for UWB wireless transmission

    NASA Astrophysics Data System (ADS)

    Crepaldi, M.; Demarchi, D.; Gabrielli, A.; Khan, A.; Pikhay, E.; Roizin, Y.; Villani, G.; Zhang, Z.

    2012-12-01

    The paper describes the design of a floating gate MOS sensor embedded in a readout CMOS element, used as a radiation monitor. A maximum sensitivity of 1 mV/rad is estimated within an absorbed dose range from 1 to 10 krad. The paper shows in particular the design of a microelectronic circuit that includes the floating gate sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype of the circuit has recently been simulated, fabricated and tested exploiting a commercial 180 nm, 4 metal CMOS technology. Some simulation results are presented along with a measurement of the readout circuit response to an input voltage swing. Given the small estimated area of the complete chip prototype, that is less than 1 mm2, the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements or radiation level in High-Energy Physics experiments.

  15. CLARO-CMOS, an ASIC for single photon counting with Ma-PMTs, MCPs and SiPMs

    NASA Astrophysics Data System (ADS)

    Carniti, P.; Cibinetto, G.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Maino, M.; Malaguti, R.; Pessina, G.

    2013-01-01

    An ASIC named CLARO-CMOS was designed for fast photon counting with MaPMTs, MCPs and SiPMs. The prototype was realized in a .35 μm CMOS technology and has four channels, each with a fast amplifier and a discriminator. The main features of the design are the high speed of operation and the low power dissipation, below 1 mW per channel. This paper focuses on the use of the CLARO for SiPM readout. The ASIC was tested with several SiPMs of various sizes, connected to the input of the chip both directly and through a coaxial cable about one meter long. In the latter case the ASIC is still fully functional although the speed of response is affected by the cable capacitance. The threshold could be set just above the single photoelectron level, and with 1 ×1 mm2 SiPMs the discrete photoelectron peaks could be well resolved.

  16. CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

    NASA Astrophysics Data System (ADS)

    Li, Zhuo; Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

    2016-04-01

    This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

  17. A 75 ps rms time resolution BiCMOS time to digital converter optimized for high rate imaging detectors

    NASA Astrophysics Data System (ADS)

    Hervé, C.; Torki, K.

    2002-04-01

    This paper presents an integrated time to digital converter (TDC) with a bin size adjustable in the range of 125 to 175 ps and a differential nonlinearity of ±0.3%. The TDC has four channels. Its architecture has been optimized for the readout of imaging detectors in use at Synchrotron Radiation facilities. In particular, a built-in logic flags piled-up events. Multi-hit patterns are also supported for other applications. Time measurements are extracted off chip at the maximum throughput of 40 MHz. The dynamic range is 14 bits. It has been fabricated in 0.8 μm BiCMOS technology. Time critical inputs are PECL compatible whereas other signals are CMOS compatible. A second application specific integrated circuit (ASIC) has been developed which translates NIM electrical levels to PECL ones. Both circuits are used to assemble board level TDCs complying with industry standards like VME, NIM and PCI.

  18. Fabrication of the planar angular rotator using the CMOS process

    NASA Astrophysics Data System (ADS)

    Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

    2002-05-01

    In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

  19. Scaling CMOS photonics transceivers beyond 100 Gb/s

    NASA Astrophysics Data System (ADS)

    Mekis, Attila; Abdalla, Sherif; De Dobbelaere, Peter M.; Foltz, Dennis; Gloeckner, Steffen; Hovey, Steven; Jackson, Steven; Liang, Yi; Mack, Michael; Masini, Gianlorenzo; Novais, Rafaela; Peterson, Mark; Pinguet, Thierry; Sahni, Subal; Schramm, Jeff; Sharp, Michael; Song, Daniel; Welch, Brian P.; Yokoyama, Kosei; Yu, Shuhuan

    2012-01-01

    We report on the performance of an integrated four-channel parallel optical transceiver built in a CMOS photonics process, operating at 28 Gb/s per channel. The optical engine of the transceiver comprises a single silicon die and a hybrid integrated DFB laser. The silicon die contains the all functionalities needed for an optical transceiver: transmitter and receiver optics, electrical driver, receiver and control circuits. We also describe the CMOS photonics platform used to build such transceiver device, which consists of: an optically enabled CMOS process, a photonic device library, and a design infrastructure that is modeled after standard circuit design tools. We discuss how this platform can scale to higher speeds and channel counts.

  20. High-speed polysilicon CMOS photodetector for telecom and datacom

    NASA Astrophysics Data System (ADS)

    Atabaki, Amir H.; Meng, Huaiyu; Alloatti, Luca; Mehta, Karan K.; Ram, Rajeev J.

    2016-09-01

    Absorption by mid-bandgap states in polysilicon or heavily implanted silicon has been previously utilized to implement guided-wave infrared photodetectors in CMOS compatible photonic platforms. Here, we demonstrate a resonant guided-wave photodetector based on the polysilicon layer that is used for the transistor gate in a microelectronic SOI CMOS process without any change to the foundry process flow ("zero-change" CMOS). Through a combination of doping mask layers, a lateral pn junction diode in the polysilicon is demonstrated with a strong electric field to enable efficient photo-carrier extraction and high-speed operation. This photodetector has a responsivity of more than 0.14 A/W from 1300 to 1600 nm, a 10 GHz bandwidth, and 80 nA dark current at 15 V reverse bias.

  1. Operation and biasing for single device equivalent to CMOS

    DOEpatents

    Welch, James D.

    2001-01-01

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  2. Memory technology survey

    NASA Technical Reports Server (NTRS)

    1981-01-01

    The current status of semiconductor, magnetic, and optical memory technologies is described. Projections based on these research activities planned for the shot term are presented. Conceptual designs of specific memory buffer pplications employing bipola, CMOS, GaAs, and Magnetic Bubble devices are discussed.

  3. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as...

  4. Measuring trunk orientation with a CMOS camera: feasibility and accuracy.

    PubMed

    Gissot, A-S; Barbieri, G; Iacobelis, M; Paindavoine, M; Pérennou, D

    2007-10-01

    The purpose of this study was to develop and validate a new tool to objectively quantify trunk orientation at the bedside, especially dedicated to the measurement of the lateropulsion in acute and subacute stroke patients. We developed software to analyze 2D movement with a CMOS camera (Logitech Quickcam Pro 4000) and to calculate the orientation of a segment defined by two color markers. First, the accuracy, reproducibility and noise when measuring segment orientations were evaluated with the CMOS camera placed in different positions, and second trunk orientation was measured in static and in dynamic conditions both with a CMOS camera and with a gold standard 3D video system (BTS SMART-e). Results showed that the measurement was accurate (mean error=0.05+/-0.12 degrees), reproducible (S.D. over five measurements=0.005 degrees ) and steady (noise signal=0.02 degrees ). The data obtained with the CMOS camera were highly correlated with those obtained with the 3D video system both in static and in dynamic conditions. However, the CMOS camera must be relatively well centered on the measured segment to avoid error due to image distortion. The parallax error was negligible. In conclusion, this could be an important step in the postural assessment of acute and subacute stroke patients. The CMOS camera, a simple, portable, compact, low-cost, commercially available apparatus is the first tool to objectively quantify lateropulsion at the bedside. This method could also support the development of a rehabilitation program for trunk orientation based on biofeedback using the real-time signal provided by the device.

  5. Characterization of CMOS image sensors with Nyquist rate pixel-level ADC

    NASA Astrophysics Data System (ADS)

    Yang, David X. D.; Tian, Hui; Fowler, Boyd A.; Liu, Xinqiao; El Gamal, Abbas

    1999-03-01

    Techniques for characterizing CCD imagers have been developed over many years. These techniques have been recently modified and extended to CMOS PPS and APS imagers. With the scaling of CMOS technology, an increasing number of transistors can be added to each pixel. A promising direction to utilize these transistors is to perform pixel level ADC. The authors have designed and prototyped two imagers with pixel level Nyquist rate ADC. The ADCs operate in parallel and output data one bit at a time. The data is read out of the imager array one bit plane at a time in a manner similar to a digital memory. Existing characterization techniques could not be directly used for these imagers, however, since there is no facility to read out the analog pixel values before ADC, and the ADC resolution is limited to only 8 bits. Fortunately, the ADCs are fully testable electrically without the need for any light or optics. This makes it possible obtain the ADC transfer curve, which greatly simplifies characterization. In this paper we describe how we characterize our pixel level ADC imagers. To estimate QE, we measure the imager photon to DN transfer curve and the ADC transfer curve. We find that both curves are quite linear.Using an estimate of the sense node capacitance we then estimate sensitivity, and QE. To estimate FPN we model it as an outcome of the sum of two uncorrelated random processes, one representing the ADC FPN, and the other representing the photodetector FPN, and develop estimators for the model parameters form imager data under uniform illumination. We report characterization result for a 640 by 512 imager, which was fabricated in a 0.35 micrometers standard digital CMOS process.

  6. On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS

    PubMed Central

    Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

    2016-01-01

    An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<−9 dB) with excellent transmission efficiency (averagely −1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology. PMID:27444782

  7. On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS

    NASA Astrophysics Data System (ADS)

    Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

    2016-07-01

    An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<‑9 dB) with excellent transmission efficiency (averagely ‑1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology.

  8. Modifications in CMOS Dynamic Logic Style: A Review Paper

    NASA Astrophysics Data System (ADS)

    Meher, Preetisudha; Mahapatra, Kamalakanta

    2015-12-01

    Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper, an overview and classification of these techniques are first presented and then compared according to their performance.

  9. Statistical circuit design for yield improvement in CMOS circuits

    NASA Technical Reports Server (NTRS)

    Kamath, H. J.; Purviance, J. E.; Whitaker, S. R.

    1990-01-01

    This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

  10. CMOS Compatible Integrated Thermoelectric Sensors Using Novel Frontside Micromachining

    NASA Astrophysics Data System (ADS)

    Socher, E.; Bochobza-Degani, O.; Nemirovsky, Y.

    2000-12-01

    CMOS compatible integrated thermoelectric sensors were designed and realized using a standard CMOS process and frontside RIE micromachining. The suspended structures were designed to have a spiral structure that enhances the thermal resistance and isolation of the sensor. Using dry RIE frontside micromachining for the release of the sensors allows better yield in realization of sensitive and smaller sensor pixels. Measured results of sensors used for IR detection show NEP's down to 0.4 nW/√Hz and response times down to 3 msec in 70*70 μm2 pixels.

  11. New Multiple-Times Programmable CMOS ROM Cell

    NASA Astrophysics Data System (ADS)

    Chung, In-Young; Jeong, Seong Yeol; Seo, Sung Min; Lee, Myungjin; Jang, Taesu; Cha, Seon-Yong; Park, Young June

    New concept of CMOS nonvolatile memory is presented with demonstration of cell implementations. The memory cell, which is a comparator basically, makes use of comparator offset for storage quantity and the FN stress phenomena for cell programming. We also propose the stress-packet operation which is the relevant programming method to finely control the offset of the memory cell. The memory cell is multiple-time programmable while it is implemented in a standard CMOS process. We fabricated the memory cell arrays of the latch comparator and demonstrated that it is rewritten several times. We also investigated the reliability of cell data retention by monitoring programmed offsets for several months.

  12. A 0.5-GHz CMOS digital RF memory chip

    NASA Astrophysics Data System (ADS)

    Schnaitter, W. M.; Lewis, E. T.; Gordon, B. E.

    1986-10-01

    Digital RF memories (DRFM's) are key elements for modern radar jamming. An RF signal is sampled, stored in random access memory (RAM), and later recreated from the stored data. Here the first CMOS DRFM chip, integrating static RAM, control circuitry, and two channels of shift registers, on a single chip is described. The sample rate achieved was 0.5 GHz, VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.

  13. Increasing the efficiency of p +np + injection-avalanche Si CMOS LEDs (450nm - 750nm) by means of depletion layer profiling and reach-through techniques

    NASA Astrophysics Data System (ADS)

    Snyman, Lukas W.; du Plessis, Monuko

    2008-02-01

    Modeling of p +np + CMOS Si LED structures show that by utilizing a short linear increasing E-field in the p +n reverse biased junction with a gradient of approximately 5 × 10 5 V.cm -1. μm -1, and facing an injecting p +n junction, has the potential to enhance photonic emissions in the 2.2 and 2.8 eV (450-750nm ) regime. Latest new designs utilize reach-through techniques in p +np + avalanche-injection control structures and p +np + poly-Si gated structures and show positive realizations of this model. Areas in the devices show marked increases in emission efficiency of factors of up to 50 - 100 as compared to previous realizations utilizing no reach-through and injection techniques. The current devices operated in the 6-8V, 1uA - 2mA regime and emit at levels of up to ~10nW /μm2. The developed devices have been realized using standard 0.35 μm CMOS design rules and fabrication technology, and have particular technological significance for future all-silicon CMOS opto-elctronic circuits and systems. The current emission levels are about three orders higher than the low frequency detectability limit of CMOS p-i-n detectors of corresponding area.

  14. Technology.

    ERIC Educational Resources Information Center

    Callison, Daniel

    2002-01-01

    Discussion of technology focuses on instructional technology. Topics include inquiry and technology; curriculum development; reflection and curriculum evaluation; criteria for technological innovations that will increase student motivation; standards; impact of new technologies on library media centers; software; and future trends. (LRW)

  15. A low-power CMOS WIA-PA transceiver with a high sensitivity GFSK demodulator

    NASA Astrophysics Data System (ADS)

    Tao, Yang; Yu, Jiang; Shengyou, Liu; Guiliang, Guo; Yuepeng, Yan

    2015-06-01

    This paper presents a low power, high sensitivity Gaussian frequency shift keying (GFSK) demodulator with a flexible frequency offset canceling method for wireless networks for industrial automation process automation (WIA-PA) transceiver fabricated in 0.18 μm CMOS technology. The receiver uses a low-IF (1.5 MHz) architecture, and the transmitter uses a sigma delta PLL based modulation with Gaussian low-pass filter for low power consumption. The active area of the demodulator is 0.14 mm2. Measurement results show that the proposed demodulator operates without harmonic distortion, deals with ± 180 kHz frequency offset, needs SNR only 18.5 dB at 0.1% bit-error rate (BER), and consumes no more than 0.26 mA from a 1.8 V power supply. Project supported by the National High Technology Research and Development Program of China (No. 2011AA040102).

  16. Integrating conjugated polymer microactuators with CMOS sensing circuitry for studying living cells

    NASA Astrophysics Data System (ADS)

    Urdaneta, Mario; Liu, Yingkai; Christophersen, Marc; Prakash, Somashekar; Abshire, Pamela; Smela, Elisabeth

    2005-05-01

    We present the use of electroactive polymer actuators as components of a biolab-on-a-chip, which has potential applications in cell-based sensing. This technology takes full advantage of the properties of polypyrrole actuators as well as the wide range of CMOS sensors that can be created. System integration becomes an important issue when developing real applications of EAP technologies. The requirements of the application and the constraints imposed by the various components must be considered in the context of the whole system, along with any opportunities that present themselves. In this paper, we discuss some of these challenges, including actuator design, the use of complementary actuation techniques, miniaturization, and packaging.

  17. Flip-chip packaged CMOS chemical microsystem for detection of volatile organic compounds

    NASA Astrophysics Data System (ADS)

    Koll, Andreas; Kawahito, Shoji; Mayer, Felix; Hagleitner, Christoph; Scheiwiller, D.; Brand, Oliver; Baltes, Henry

    1998-07-01

    We present a packaged single-chip microsystem for the detection of organic vapors. The sensor is fabricated using a 0.8 micrometers CMOS IC process provided by AMS Austria Mikro Systeme. Volatile organic compounds are detected by measuring the capacitance change of three polymer coated interdigitated capacitors due to analyte absorption. To protect the read-out circuitry from the organic vapors, the device is packaged using flip-chip technology. This technology allows for openings in the ceramic substrate for the sensing capacitors while hermetically sealing the remaining chip area. Measurements for different volatile organic compounds and chemically sensitive polymer layers are presented. The packaged microsensor array is a first step towards the realization of a small, low cost electronic nose on a single chip.

  18. Single Event Upset Behavior of CMOS Static RAM Cells

    NASA Technical Reports Server (NTRS)

    Lieneweg, Udo; Jeppson, Kjell O.; Buehler, Martin G.

    1993-01-01

    An improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.

  19. CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.

    SciTech Connect

    RADEKA, V.

    2006-04-03

    Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

  20. CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics

    NASA Technical Reports Server (NTRS)

    Yeh, Penshu; Maki, Gary

    2007-01-01

    Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

  1. Effects Of Dose Rates On Radiation Damage In CMOS Parts

    NASA Technical Reports Server (NTRS)

    Goben, Charles A.; Coss, James R.; Price, William E.

    1990-01-01

    Report describes measurements of effects of ionizing-radiation dose rate on consequent damage to complementary metal oxide/semiconductor (CMOS) electronic devices. Depending on irradiation time and degree of annealing, survivability of devices in outer space, or after explosion of nuclear weapons, enhanced. Annealing involving recovery beyond pre-irradiation conditions (rebound) detrimental. Damage more severe at lower dose rates.

  2. Characterisation of a CMOS charge transfer device for TDI imaging

    NASA Astrophysics Data System (ADS)

    Rushton, J.; Holland, A.; Stefanov, K.; Mayer, F.

    2015-03-01

    The performance of a prototype true charge transfer imaging sensor in CMOS is investigated. The finished device is destined for use in TDI applications, especially Earth-observation, and to this end radiation tolerance must be investigated. Before this, complete characterisation is required. This work starts by looking at charge transfer inefficiency and then investigates responsivity using mean-variance techniques.

  3. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    PubMed Central

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

  4. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  5. CMOS-compatible LVOF-based visible microspectrometer

    NASA Astrophysics Data System (ADS)

    Emadi, Arvin; Wu, Huaiwen; de Graaf, Ger; Wolffenbuttel, Reinoud F.

    2010-04-01

    This paper reports on a CMOS-Compatible Linear Variable Optical Filter (LVOF) visible micro-spectrometer. The CMOS-compatible post process for fabrication of the LVOF has been used for integration of the LVOF with a CMOS chip containing a 128-element photodiode array and readout circuitry. Fabrication of LVOF involves a process for fabrication of very small taper angles, ranging from 0.001° to 0.1°, in SiO2. These layers can be fabricated flexibly in a resist layer by just one lithography step and a subsequent reflow process. The 3D pattern of the resist structures is subsequently transferred into SiO2 by appropriate etching. Complete LVOF fabrication involves CMOS-compatible deposition of a lower dielectric mirror using a stack of dielectrics on the wafer, tapered layer formation and deposition of the top dielectric mirror. The LVOF has been optimized for 580 nm - 720 nm spectral operating range and has also been mounted on a CCD camera for characterization. The design of LVOF micro-spectrometer, the fabrication and characterization results are presented.

  6. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    NASA Astrophysics Data System (ADS)

    Rescigno, R.; Finck, Ch.; Juliani, D.; Baudot, J.; Dauvergne, D.; Dedes, G.; Krimmer, J.; Ray, C.; Reithinger, V.; Rousseau, M.; Testa, E.; Winter, M.

    2014-03-01

    Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  7. Attributes and drawbacks of submicron CMOS for IR FPA readouts

    NASA Astrophysics Data System (ADS)

    Kozlowski, L. J.

    1998-09-01

    The availability of submicron CMOS has enabled the development of shingle-chip IR cameras having performance capabilities and on-chip functions which were previously impossible. Sensor designers are, however, encoutering and overcoming several challanges including steadily decreasing operating voltage.

  8. Direct readout of gaseous detectors with tiled CMOS circuits

    NASA Astrophysics Data System (ADS)

    Visschers, J. L.; Blanco Carballo, V.; Chefdeville, M.; Colas, P.; van der Graaf, H.; Schmitz, J.; Smits, S.; Timmermans, J.

    2007-03-01

    A coordinated design effort is underway, exploring the three-dimensional direct readout of gaseous detectors by an anode plate equipped with a tiled array of many CMOS pixel readout ASICs, having amplification grids integrated on their topsides and being contacted on their backside.

  9. A robust color signal processing with wide dynamic range WRGB CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Kawada, Shun; Kuroda, Rihito; Sugawa, Shigetoshi

    2011-01-01

    We have developed a robust color reproduction methodology by a simple calculation with a new color matrix using the formerly developed wide dynamic range WRGB lateral overflow integration capacitor (LOFIC) CMOS image sensor. The image sensor was fabricated through a 0.18 μm CMOS technology and has a 45 degrees oblique pixel array, the 4.2 μm effective pixel pitch and the W pixels. A W pixel was formed by replacing one of the two G pixels in the Bayer RGB color filter. The W pixel has a high sensitivity through the visible light waveband. An emerald green and yellow (EGY) signal is generated from the difference between the W signal and the sum of RGB signals. This EGY signal mainly includes emerald green and yellow lights. These colors are difficult to be reproduced accurately by the conventional simple linear matrix because their wave lengths are in the valleys of the spectral sensitivity characteristics of the RGB pixels. A new linear matrix based on the EGY-RGB signal was developed. Using this simple matrix, a highly accurate color processing with a large margin to the sensitivity fluctuation and noise has been achieved.

  10. Design and Implementation of A CMOS Light Pulse Receiver Cell Array for Spatial Optical Communications

    PubMed Central

    Sarker, Md. Shakowat Zaman; Itoh, Shinya; Hamai, Moeta; Takai, Isamu; Andoh, Michinori; Yasutomi, Keita; Kawahito, Shoji

    2011-01-01

    A CMOS light pulse receiver (LPR) cell for spatial optical communications is designed and evaluated by device simulations and a prototype chip implementation. The LPR cell consists of a pinned photodiode and four transistors. It works under sub-threshold region of a MOS transistor and the source terminal voltage which responds to the logarithm of the photo current are read out with a source follower circuit. For finding the position of the light spot on the focal plane, an image pixel array is embedded on the same plane of the LPR cell array. A prototype chip with 640 × 240 image pixels and 640 × 240 LPR cells is implemented with 0.18 μm CMOS technology. A proposed model of the transient response of the LPR cell agrees with the result of the device simulations and measurements. Both imaging at 60 fps and optical communication at the carrier frequency of 1 MHz are successfully performed. The measured signal amplitude and the calculation results of photocurrents show that the spatial optical communication up to 100 m is feasible using a 10 × 10 LED array. PMID:22319398

  11. A Differential CMOS Common-Gate LNA Linearized by Cross-Coupled Post Distortion Technique

    NASA Astrophysics Data System (ADS)

    Guo, Benqing; Yang, Guomin; Bin, Xiexian

    2014-05-01

    A linearized differential common-gate CMOS low noise amplifier is proposed. The linearity is improved by a cross-coupled post distortion technique, employing auxiliary PMOS transistors in weak inversion region to cancel the third-order nonlinear currents of common-gate LNA and impair the second-order nonlinear currents of that. The negative conductance characteristic of cross-coupled auxiliary PMOS transistors improves the gain while the resulted NF is little affected. Furthermore, noise contribution and linearity deterioration from the cascode stage is eliminated by an inductor resonating with the parasitic capacitance observed at the source net of the cascode transistor. The LNA implemented in a 0.18 μm CMOS technology demonstrates that IIP3 and gain have about 8.2 dB and 1.4 dB improvements in the designed frequency band, respectively. The noise figure of 3.4 dB is obtained with a power dissipation of 6.8 mW under a 1.8 V power supply.

  12. Design and implementation of a CMOS light pulse receiver cell array for spatial optical communications.

    PubMed

    Sarker, Md Shakowat Zaman; Itoh, Shinya; Hamai, Moeta; Takai, Isamu; Andoh, Michinori; Yasutomi, Keita; Kawahito, Shoji

    2011-01-01

    A CMOS light pulse receiver (LPR) cell for spatial optical communications is designed and evaluated by device simulations and a prototype chip implementation. The LPR cell consists of a pinned photodiode and four transistors. It works under sub-threshold region of a MOS transistor and the source terminal voltage which responds to the logarithm of the photo current are read out with a source follower circuit. For finding the position of the light spot on the focal plane, an image pixel array is embedded on the same plane of the LPR cell array. A prototype chip with 640 × 240 image pixels and 640 × 240 LPR cells is implemented with 0.18 μm CMOS technology. A proposed model of the transient response of the LPR cell agrees with the result of the device simulations and measurements. Both imaging at 60 fps and optical communication at the carrier frequency of 1 MHz are successfully performed. The measured signal amplitude and the calculation results of photocurrents show that the spatial optical communication up to 100 m is feasible using a 10 × 10 LED array.

  13. A low-power CMOS smart temperature sensor for RFID application

    NASA Astrophysics Data System (ADS)

    Liangbo, Xie; Jiaxin, Liu; Yao, Wang; Guangjun, Wen

    2014-11-01

    This paper presents the design and implement of a CMOS smart temperature sensor, which consists of a low power analog front-end and a 12-bit low-power successive approximation register (SAR) analog-to-digital converter (ADC). The analog front-end generates a proportional-to-absolute-temperature (PTAT) voltage with MOSFET circuits operating in the sub-threshold region. A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage. Using 0.18 μm CMOS technology, measurement results show that the temperature error is -0.69/+0.85 °C after one-point calibration over a temperature range of -40 to 100 °C. Under a conversion speed of 1K samples/s, the power consumption is only 2.02 μW while the chip area is 230 × 225 μm2, and it is suitable for RFID application.

  14. (Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

    DOE PAGES

    Gao, X.; Mamaluy, D.; Cyr, E. C.; Marinella, M. J.

    2016-05-10

    As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

  15. A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

    NASA Astrophysics Data System (ADS)

    Sharma, Vijay Kumar; Pattanaik, Manisha

    2015-11-01

    Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

  16. Mass-producible and efficient optical antennas with CMOS-fabricated nanometer-scale gap.

    PubMed

    Seok, Tae Joon; Jamshidi, Arash; Eggleston, Michael; Wu, Ming C

    2013-07-15

    Optical antennas have been widely used for sensitive photodetection, efficient light emission, high resolution imaging, and biochemical sensing because of their ability to capture and focus light energy beyond the diffraction limit. However, widespread application of optical antennas has been limited due to lack of appropriate methods for uniform and large area fabrication of antennas as well as difficulty in achieving an efficient design with small mode volume (gap spacing < 10nm). Here, we present a novel optical antenna design, arch-dipole antenna, with optimal radiation efficiency and small mode volume, 5 nm gap spacing, fabricated by CMOS-compatible deep-UV spacer lithography. We demonstrate strong surface-enhanced Raman spectroscopy (SERS) signal with an enhancement factor exceeding 108 from the arch-dipole antenna array, which is two orders of magnitude stronger than that from the standard dipole antenna array fabricated by e-beam lithography. Since the antenna gap spacing, the critical dimension of the antenna, can be defined by deep-UV lithography, efficient optical antenna arrays with nanometer-scale gap can be mass-produced using current CMOS technology.

  17. An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications

    NASA Astrophysics Data System (ADS)

    Chen, Po-Hung; Chen, Min-Chiao; Ko, Chun-Lin; Wu, Chung-Yu

    A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SFT) for V-band applications is designed, fabricated and measured using 0.13-µm CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SFT. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20GHz. The fabricated receiver has a maximum conversion gain of 19.4dB, a minimum single-side band noise figure of 10.2dB, the input-referred 1-dB compression point of -20dBm and the input third order inter-modulation intercept point of -8.3dB. It draws only 15.8mA from a 1.2-V power supply with a total chip area of 0.794mm × 0.794mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.

  18. A CMOS pixel sensor prototype for the outer layers of linear collider vertex detector

    NASA Astrophysics Data System (ADS)

    Zhang, L.; Morel, F.; Hu-Guo, C.; Himmi, A.; Dorokhov, A.; Hu, Y.

    2015-01-01

    The International Linear Collider (ILC) expresses a stringent requirement for high precision vertex detectors (VXD). CMOS pixel sensors (CPS) have been considered as an option for the VXD of the International Large Detector (ILD), one of the detector concepts proposed for the ILC. MIMOSA-31 developed at IPHC-Strasbourg is the first CPS integrated with 4-bit column-level ADC for the outer layers of the VXD, adapted to an original concept minimizing the power consumption. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal noise and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with a self-triggered analog-to-digital converter (ADC). The ADC design was optimized for power saving at a sampling frequency of 6.25 MS/s. The prototype chip is fabricated in a 0.35 μm CMOS technology. This paper presents the details of the prototype chip and its test results.

  19. CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

    NASA Astrophysics Data System (ADS)

    Carniti, P.; De Matteis, M.; Giachero, A.; Gotti, C.; Maino, M.; Pessina, G.

    2012-11-01

    The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 μm CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke- (1.2 fC) with an input capacitance of 3.3 pF. With this value of input capacitance a timing resolution down to 10 ps RMS was measured for pulser signals of a few million electrons, corresponding to the single photon response for these detectors.

  20. Towards monolithically integrated CMOS cameras for active imaging with 600 GHz radiation

    NASA Astrophysics Data System (ADS)

    Boppel, Sebastian; Lisauskas, Alvydas; Krozer, Viktor; Roskos, Hartmut G.

    2012-02-01

    We explore terahertz imaging with CMOS field-effect transistors exploiting their plasmonic detection capability and the advantages of CMOS technology for the fabrication of THz cameras with respect to process stability, array uniformity, ease of integration of additional functionality, scalability and cost-effectiveness. A 100×100-pixel camera with an active area of 20×20 mm² is physically simulated by scanning single detectors and groups of a few detectors in the image plane. Using detectors with a noise-equivalent power of 43 pW/√Hz, a distributed illumination of 432 μW at 591.4 GHz, and an integration time of 20 ms (for a possible frame rate of 17 fps), this virtual camera allows to obtain images with a dynamic range of at least 20 dB and a resolution approaching the diffraction limit. Imaging examples acquired in direct and heterodyne detection mode, and in transmission and reflection geometry, show the potential for real-time operation. It is demonstrated that heterodyning (i) improves the dynamic range substantially even if the radiation from the local oscillator is distributed over the camera area, and (ii) allows sensitive determination of object-induced phase changes, which promises the realization of coherent imaging systems.

  1. Capacitive micropressure sensors with underneath readout circuit using a standard CMOS process

    NASA Astrophysics Data System (ADS)

    Chang, Shihchen; Dai, Chingliang; Chiou, Jinghung; Chang, Peizen

    2001-08-01

    A capacitive micropressure sensor with readout circuits on a single chip is fabricated using commercial 0.35micrometers CMOS process technology and post-processing. The main break through feature of the chip is the positioning of its readout circuits under the pressure sensor, allowing the chip to be smaller. Post-processing included anisotropic dry etching and wet etching to remove the sacrificial layer, and the use of PECVD nitride to seal the etching holes of the pressure sensor. The sacrificial layer was the metal 3 layer of the standard 0.35 micrometers CMOS process. In addition, the readout circuit is divided into analog and digital parts, with the digital part being an alternate coupled RS flip- flop with four inverters that sharpened the output wave. Moreover, the analog part is employed switched capacitor methodology. The pressure sensor contained an 8 X 8 sensing cells array, and the total area of the pressure sensor chip is 2mmx2 mm. In addition to illustrating the design and fabrication of the capacitive pressure sensor, this investigation demonstrates the simulation and testing results of the readout circuit.

  2. Mass-producible and efficient optical antennas with CMOS-fabricated nanometer-scale gap.

    PubMed

    Seok, Tae Joon; Jamshidi, Arash; Eggleston, Michael; Wu, Ming C

    2013-07-15

    Optical antennas have been widely used for sensitive photodetection, efficient light emission, high resolution imaging, and biochemical sensing because of their ability to capture and focus light energy beyond the diffraction limit. However, widespread application of optical antennas has been limited due to lack of appropriate methods for uniform and large area fabrication of antennas as well as difficulty in achieving an efficient design with small mode volume (gap spacing < 10nm). Here, we present a novel optical antenna design, arch-dipole antenna, with optimal radiation efficiency and small mode volume, 5 nm gap spacing, fabricated by CMOS-compatible deep-UV spacer lithography. We demonstrate strong surface-enhanced Raman spectroscopy (SERS) signal with an enhancement factor exceeding 108 from the arch-dipole antenna array, which is two orders of magnitude stronger than that from the standard dipole antenna array fabricated by e-beam lithography. Since the antenna gap spacing, the critical dimension of the antenna, can be defined by deep-UV lithography, efficient optical antenna arrays with nanometer-scale gap can be mass-produced using current CMOS technology. PMID:23938507

  3. A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE

    NASA Astrophysics Data System (ADS)

    Xuemin, Li; Mao, Ye; Gongyuan, Zhao; Yun, Zhang; Yiqiang, Zhao

    2016-05-01

    A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage |VGS|p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages |VGS|n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages ΔVBE of bipolar junction transistors (BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/°C without trimming, over a temperature range from -40 to 120 °C, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio (PSRR) is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2. Project supported by the National Natural Science Foundation of China (No. 61376032).

  4. CMOS preamplifier with high linearity and ultra low noise for x-ray spectroscopy

    SciTech Connect

    O`Connor, P.O.; Rehak, P.; Gramegna, G.; Corsi, F.; Marzocca, C.

    1996-12-31

    We present an ultra low noise charge preamplifier suitable for small capacitance (200M), low leakage current solid state detectors. A self adaptive bias circuit for the MOS feedback device establishes the static feedback resistance in the G{Omega} range while tracking the threshold variations and power supply and temperature fluctuations. The linearity of the gain versus input charge has been improved by means of a voltage divider between the output of the charge-sensitive amplifier and the source of the feedback transistor. With the preamplifier alone, we measure a room-temperature equivalent noise charge (ENC) of 9 e{sup -} rms at 12 usec shaping time. When coupled to a cooled detector a FWHM of 130 eV is obtained at 2.4 usec shaping, corresponding to an ENC of 16 e{sup -} rms. This is the best reported resolution obtained with a CMOS preamplifier. The circuit has good linearity (< 0.2%) up to 1.8 W. Since the preamplifier`s ENC is limited by flicker noise, we fabricated the circuit in two 1.2um CMOS technologies. Device measurements allow us to compare the 1/f noise behavior of each foundry. In addition to the preamplifiers, a 1 us shaper and a 50{Omega} output driver are included on the die.

  5. Distinct development patterns of c-mos protooncogene expression in female and male mouse germ cells

    SciTech Connect

    Mutter, G.L.; Wolgemuth, D.J.

    1987-08-01

    The protooncogene c-mos is expressed in murine reproductive tissues, producing transcripts of 1.7 and 1.4 kilobases in testis and ovary, respectively. In situ hybridization analysis of c-mos expression in histological sections of mouse ovaries revealed that oocytes are the predominant if not exclusive source of c-mos transcripts. /sup 35/S- or /sup 32/P-labelled RNA probes were transcribed. c-mos transcripts accumulate in growing oocytes, increasing 40- to 90-fold during oocyte and follicular development. c-mos transcripts were also detected in male germ cells and are most abundant after the cells have entered the haploid stage of spermatogenesis. This developmentally regulated pattern of c-mos expression in oocytes and spermatogenic cells suggest that the c-mos gene product may have a function in normal germ-cell differentiation or early embryogenesis.

  6. Combined reactor neutron beam and {sup 60}Co γ-ray radiation effects on CMOS APS image sensors

    SciTech Connect

    Wang, Zujun Chen, Wei; Sheng, Jiangkun; Liu, Yan; Xiao, Zhigang; Huang, Shaoyan; Liu, Minbo

    2015-02-15

    The combined reactor neutron beam and {sup 60}Co γ-ray radiation effects on complementary metal-oxide semiconductor (CMOS) active pixel sensors (APS) have been discussed and some new experimental phenomena are presented. The samples are manufactured in the standard 0.35-μm CMOS technology. Two samples were first exposed to {sup 60}Co γ-rays up to the total ionizing dose (TID) level of 200 krad(Si) at the dose rates of 50.0 and 0.2 rad(Si)/s, and then exposed to neutron fluence up to 1 × 10{sup 11} n/cm{sup 2} (1-MeV equivalent neutron fluence). One sample was first exposed to neutron fluence up to 1 × 10{sup 11} n/cm{sup 2} (1-MeV equivalent neutron fluence), and then exposed to {sup 60}Co γ-rays up to the TID level of 200 krad(Si) at the dose rate of 0.2 rad(Si)/s. The mean dark signal (K{sub D}), the dark signal non-uniformity (DSNU), and the noise (V{sub N}) versus the total dose and neutron fluence has been investigated. The degradation mechanisms of CMOS APS image sensors have been analyzed, especially for the interaction induced by neutron displacement damage and TID damage.

  7. Performance analysis of a large photoactive area CMOS line sensor for fast, time-resolved spectroscopy applications

    NASA Astrophysics Data System (ADS)

    Poklonskaya, Elena A.; Durini, Daniel; Jung, Melanie; Schrey, Olaf; Driewer, Adrian; Brockherde, Werner; Hosticka, Bedrich; Vogt, Holger

    2014-05-01

    The performance of a fabricated CMOS line sensor based on the lateral drift-field photodiode (LDPD)1 concept is described. A new pixel structure was designed to decrease the charge transfer time across the photoactive area. Synopsys TCAD simulations were performed to design a proper intrinsic lateral drift-field within the pixel. The line sensor was fabricated in the 0.35 μm CMOS technology, and further characterized using a tailored photon-transfer method2 and the EMVA 1288 standard3. The basic parameters such as spectral responsivity, photo-response non-uniformity and dark current were measured at fabricated sensor samples. A special attention was paid to charge transfer time characterization4 and the evaluation of crosstalk between neighboring pixels - two major concerns attained during the development. It is shown that the electro-optical characteristics of the developed line sensor are comparable to those delivered by CCD line sensors available on the market, which are normally superior in performance compared to their CMOS based counterparts, but offering additional features such as the possibility of time gating, non-destructive readout, and charge accumulation over several cycles: approaches used to enhance the signal-to-noise ratio (SNR) of the sensor output.

  8. Contact CMOS imaging of gaseous oxygen sensor array.

    PubMed

    Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-10-01

    We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3](2+)) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

  9. Contact CMOS imaging of gaseous oxygen sensor array

    PubMed Central

    Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

    2014-01-01

    We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

  10. Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

    NASA Astrophysics Data System (ADS)

    Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

    2013-07-01

    In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

  11. Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization

    SciTech Connect

    Zhao, Chumin; Kanicki, Jerzy; Konstantinidis, Anastasios C.; Patel, Tushita

    2015-11-15

    Purpose: Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50–300 e{sup −}) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). Methods: In this study, imaging performance of a large area (29 × 23 cm{sup 2}) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165–400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. Results: The LFW mode shows better DQE at low air kerma (K{sub a} < 10 μGy) and should be used for DBT. At current DBT applications, air kerma (K{sub a} ∼ 10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165–400 μm in size can be resolved using a MGD range of 0.3–1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at

  12. Automatic Synthesis of CMOS Algorithmic Analog To-Digital Converter.

    NASA Astrophysics Data System (ADS)

    Jusuf, Gani

    The steady decrease in technological feature size is allowing increasing levels of integration in analog/digital interface functions. These functions consist of analog as well as digital circuits. While the turn around time for an all digital IC chip is very short due to the maturity of digital IC computer-aided design (CAD) tools over the last ten years, most analog circuits have to be designed manually due to the lack of analog IC CAD tools. As a result, analog circuit design becomes the bottleneck in the design of mixed signal processing chips. One common analog function in a mixed signal processing chip is an analog-to-digital conversion (ADC) function. This function recurs frequently but with varying performance requirements. The objective of this research is to study the design methodology of a compilation program capable of synthesizing ADC's with a broad range of sampling rates and resolution, and silicon area and performance comparable with the manual approach. The automatic compilation of the ADC function is a difficult problem mainly because ADC techniques span such a wide spectrum of performance, with radically different implementations being optimum for different ranges of conversion range, resolution, and power dissipation. We will show that a proper choice of the ADC architectures and the incorporation of many analog circuit design techniques will simplify the synthesis procedure tremendously. Moreover, in order to speed up the device sizing, hierarchical optimization procedure and behavioral simulation are implemented into the ADC module generation steps. As a result of this study, a new improved algorithmic ADC without the need of high precision comparators has been developed. This type of ADC lends itself to automatic generation due to its modularity, simplicity, small area consumption, moderate speed, low power dissipation, and single parameter trim capability that can be added at high resolution. Furthermore, a performance-driven CMOS ADC module

  13. Study of built-in amplifier performance on HV-CMOS sensor for the ATLAS phase-II strip tracker upgrade

    NASA Astrophysics Data System (ADS)

    Liang, Z.; Affolder, A.; Arndt, K.; Bates, R.; Benoit, M.; Di Bello, F.; Blue, A.; Bortoletto, D.; Buckland, M.; Buttar, C.; Caragiulo, P.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hoeferkamp, M.; Hommels, L. B. A.; Huffman, B. T.; John, J.; Kanisauskas, K.; Kenney, C.; Kramberger, J.; Mandić, I.; Maneuski, D.; Martinez-Mckinney, F.; McMahon, S.; Meng, L.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Peric, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seidel, S.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zhang, J.; Zhu, H.

    2016-09-01

    This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip.

  14. Single-photon sensitive fast ebCMOS camera system for multiple-target tracking of single fluorophores: application to nano-biophotonics

    NASA Astrophysics Data System (ADS)

    Cajgfinger, Thomas; Chabanat, Eric; Dominjon, Agnes; Doan, Quang T.; Guerin, Cyrille; Houles, Julien; Barbier, Remi

    2011-03-01

    Nano-biophotonics applications will benefit from new fluorescent microscopy methods based essentially on super-resolution techniques (beyond the diffraction limit) on large biological structures (membranes) with fast frame rate (1000 Hz). This trend tends to push the photon detectors to the single-photon counting regime and the camera acquisition system to real time dynamic multiple-target tracing. The LUSIPHER prototype presented in this paper aims to give a different approach than those of Electron Multiplied CCD (EMCCD) technology and try to answer to the stringent demands of the new nano-biophotonics imaging techniques. The electron bombarded CMOS (ebCMOS) device has the potential to respond to this challenge, thanks to the linear gain of the accelerating high voltage of the photo-cathode, to the possible ultra fast frame rate of CMOS sensors and to the single-photon sensitivity. We produced a camera system based on a 640 kPixels ebCMOS with its acquisition system. The proof of concept for single-photon based tracking for multiple single-emitters is the main result of this paper.

  15. CMOS VLSI Active-Pixel Sensor for Tracking

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  16. High-Voltage-Input Level Translator Using Standard CMOS

    NASA Technical Reports Server (NTRS)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  17. SPICE Level 3 and BSIM3v3.1 characterization of monolithic integrated CMOS-MEMS devices

    SciTech Connect

    Staple, B.D.; Watts, H.A.; Dyck, C.; Griego, A.P.; Hewlett, F.W.; Smith, J.H.

    1998-08-01

    The monolithic integration of MicroElectroMechanical Systems (MEMS) with the driving, controlling, and signal processing electronics promises to improve the performance of micromechanical devices as well as lower their manufacturing, packaging, and instrumentation costs. Key to this integration is the proper interleaving, combining, and customizing of the manufacturing processes to produce functional integrated micromechanical devices with electronics. The authors have developed a MEMS-first monolithic integrated process that first seals the micromechanical devices in a planarized trench and then builds the electronics in a conventional CMOS process. To date, most of the research published on this technology has focused on the performance characteristics of the mechanical portion of the devices, with little information on the attributes of the accompanying electronics. This work attempts to reduce this information void by presenting the results of SPICE Level 3 and BSIM3v3.1 model parameters extracted for the CMOS portion of the MEMS-first process. Transistor-level simulations of MOSFET current, capacitance, output resistance, and transconductance versus voltage using the extracted model parameters closely match the measured data. Moreover, in model validation efforts, circuit-level simulation values for the average gate propagation delay in a 101-stage ring oscillator are within 13--18% of the measured data. In general, the BSIM3v3.1 models provide improved accuracy over the SPICE Level 3 models. These results establish the following: (1) the MEMS-first approach produces functional CMOS devices integrated on a single chip with MEMS devices and (2) the devices manufactured in the approach have excellent transistor characteristics. Thus, the MEMS-first approach renders a solid technology foundation for customers designing in the technology.

  18. SPICE Level 3 and BSIM3v3.1 characterization of monolithic integrated CMOS-MEMS devices

    NASA Astrophysics Data System (ADS)

    Staple, Bevan D.; Watts, Herman A.; Dyck, Christopher W.; Griego, A. P.; Hewlett, F. W.; Smith, James H.

    1998-09-01

    Thy monolithic integration of MicroElectroMechanical Systems (MEMS) with the driving, controlling, and signal processing electronics promises to improve the performance of micromechanical devices as well as lower their manufacturing, packaging, and instrumentation costs. Key to this integration is the proper interleaving, combining, and customizing of the manufacturing processes to produce functional integrated micromechanical devices with electronics. We have developed a MEMS-first monolithic integrated process that first seals the micromechanical devices in a planarized trench and then builds the electronics in a conventional CMOS process. To date, most of the research published on this technology has focused on the performance characteristics of the mechanical portion of the devices, with little information on the attributes of the accompanying electronics. This work attempts to reduce this information void by presenting the results of SPICE Level 3 and BSIM3v3.1 model parameters extracted for the CMOS portion of the MEMS-first process. Transistor-level simulations of MOSFET current, capacitance, output resistance, and transconductance versus voltage using the extracted model parameters closely match the measured data. Moreover, in model validation efforts, circuit-level simulation values for the average gate propagation delay in a 101-stage ring oscillator are within 13 - 18% of the measured data. These results establish the following: (1) the MEMS-first approach produces functional CMOS devices integrated on a single chip with MEMS devices and (2) the devices manufactured in the approach have excellent transistor characteristics. Thus, the MEMS-first approach renders a solid technology foundation for customers designing in the technology.

  19. Maximum density of quantum information in a scalable CMOS implementation of the hybrid qubit architecture

    NASA Astrophysics Data System (ADS)

    Rotta, Davide; De Michielis, Marco; Ferraro, Elena; Fanciulli, Marco; Prati, Enrico

    2016-06-01

    Scalability from single-qubit operations to multi-qubit circuits for quantum information processing requires architecture-specific implementations. Semiconductor hybrid qubit architecture is a suitable candidate to realize large-scale quantum information processing, as it combines a universal set of logic gates with fast and all-electrical manipulation of qubits. We propose an implementation of hybrid qubits, based on Si metal-oxide-semiconductor (MOS) quantum dots, compatible with the CMOS industrial technological standards. We discuss the realization of multi-qubit circuits capable of fault-tolerant computation and quantum error correction, by evaluating the time and space resources needed for their implementation. As a result, the maximum density of quantum information is extracted from a circuit including eight logical qubits encoded by the [[7, 1, 3

  20. Adaptive Threshold Neural Spike Detector Using Stationary Wavelet Transform in CMOS.

    PubMed

    Yang, Yuning; Boling, C Sam; Kamboh, Awais M; Mason, Andrew J

    2015-11-01

    Spike detection is an essential first step in the analysis of neural recordings. Detection at the frontend eases the bandwidth requirement for wireless data transfer of multichannel recordings to extra-cranial processing units. In this work, a low power digital integrated spike detector based on the lifting stationary wavelet transform is presented and developed. By monitoring the standard deviation of wavelet coefficients, the proposed detector can adaptively set a threshold value online for each channel independently without requiring user intervention. A prototype 16-channel spike detector was designed and tested in an FPGA. The method enables spike detection with nearly 90% accuracy even when the signal-to-noise ratio is as low as 2. The design was mapped to 130 nm CMOS technology and shown to occupy 0.014 mm(2) of area and dissipate 1.7 μW of power per channel, making it suitable for implantable multichannel neural recording systems. PMID:25955990

  1. Optimization of CMOS pixel sensors for high performance vertexing and tracking

    NASA Astrophysics Data System (ADS)

    Baudot, Jérôme; Besson, Auguste; Claus, Gilles; Dulinski, Wojciech; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Molnar, Levente; Sanchez-Castro, Xitzel; Senyukov, Serhiy; Winter, Marc

    2013-12-01

    CMOS Pixel Sensors tend to become relevant for a growing spectrum of charged particle detection instruments. This comes mainly from their high granularity and low material budget. However, several potential applications require a higher read-out speed and radiation tolerance than those achieved with the available devices based on a 0.35 μm feature size technology. This paper shows preliminary test results of new prototype sensors manufactured in a 0.18 μm process based on a high resistivity epitaxial layer of sizeable thickness. Grounded on these observed performances, we discuss a development strategy over the coming years to reach a full scale sensor matching the specifications of the upgraded version of the Inner Tracking System (ITS) of the ALICE experiment at CERN, for which a sensitive area of up to ∼10 m2 may be equipped with pixel sensors.

  2. CMOS Humidity Sensor System Using Carbon Nitride Film as Sensing Materials

    PubMed Central

    Lee, Sung Pil; Lee, Ji Gong; Chowdhury, Shaestagir

    2008-01-01

    An integrated humidity sensor system with nano-structured carbon nitride film as humidity sensing material is fabricated by a 0.8 μm analog mixed CMOS process. The integrated sensor system consists of differential humidity sensitive field effect transistors (HUSFET), temperature sensor, and operational amplifier. The process contains two poly, two metal and twin well technology. To form CNx film on Si3N4/Si substrate, plasma etching is performed to the gate area as well as trenches. CNx film is deposited by reactive RF magnetron sputtering method and patterned by the lift-off technique. The drain current is proportional to the dielectric constant, and the sensitivity is 2.8 μA/%RH.

  3. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

    PubMed

    Huang, Haiyun; Wang, Dejun; Xu, Yue

    2015-10-27

    This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

  4. Design Considerations for CMOS-Integrated Hall-Effect Magnetic Bead Detectors for Biosensor Applications.

    PubMed

    Skucha, K; Gambini, S; Liu, P; Megens, M; Kim, J; Boser, Be

    2013-06-01

    We describe a design methodology for on-chip magnetic bead label detectors based on Hall-effect sensors. Signal errors caused by the label-binding process and other factors that limit the minimum detection area are quantified and adjusted to meet typical assay accuracy standards. The methodology is demonstrated by designing an 8192 element Hall sensor array, implemented in a commercial 0.18 μm CMOS process with single-mask postprocessing. The array can quantify a 1% surface coverage of 2.8 μm beads in 30 seconds with a coefficient of variation of 7.4%. This combination of accuracy and speed makes this technology a suitable detection platform for biological assays based on magnetic bead labels.

  5. Investigations on CMOS photodiodes using scanning electron microscopy with electron beam induced current measurements

    NASA Astrophysics Data System (ADS)

    Kraxner, A.; Roger, F.; Loeffler, B.; Faccinelli, M.; Kirnstoetter, S.; Minixhofer, R.; Hadley, P.

    2014-09-01

    In this work the characterization of CMOS diodes with Electron Beam Induced Current (EBIC) measurements in a Scanning Electron Microscope (SEM) are presented. Three-dimensional Technology Computer Aided Design (TCAD) simulations of the EBIC measurement were performed for the first time to help interpret the experimental results. The TCAD simulations provide direct access to the spatial distribution of physical quantities (like mobility, lifetime etc.) which are very difficult to obtain experimentally. For the calibration of the simulation to the experiments, special designs of vertical p-n diodes were fabricated. These structures were investigated with respect to doping concentration, beam energy, and biasing. A strong influence of the surface preparation on the measurements and the extracted diffusion lengths are shown.

  6. Scaled CMOS Reliability and Considerations for Spacecraft Systems: Bottom-Up and Top-Down Perspective

    NASA Technical Reports Server (NTRS)

    White, Mark

    2012-01-01

    New space missions will increasingly rely on more advanced technologies because of system requirements for higher performance, particularly in instruments and high-speed processing. Component-level reliability challenges with scaled CMOS in spacecraft systems from a bottom-up perspective have been presented. Fundamental Front-end and Back-end processing reliability issues with more aggressively scaled parts have been discussed. Effective thermal management from system-level to the componentlevel (top-down) is a key element in overall design of reliable systems. Thermal management in space systems must consider a wide range of issues, including thermal loading of many different components, and frequent temperature cycling of some systems. Both perspectives (top-down and bottom-up) play a large role in robust, reliable spacecraft system design.

  7. Transmission of wireless neural signals through a 0.18 µm CMOS low-power amplifier.

    PubMed

    Gazziro, M; Braga, C F R; Moreira, D A; Carvalho, A C P L F; Rodrigues, J F; Navarro, J S; Ardila, J C M; Mioni, D P; Pessatti, M; Fabbro, P; Freewin, C; Saddow, S E

    2015-01-01

    In the field of Brain Machine Interfaces (BMI) researchers still are not able to produce clinically viable solutions that meet the requirements of long-term operation without the use of wires or batteries. Another problem is neural compatibility with the electrode probes. One of the possible ways of approaching these problems is the use of semiconductor biocompatible materials (silicon carbide) combined with an integrated circuit designed to operate with low power consumption. This paper describes a low-power neural signal amplifier chip, named Cortex, fabricated using 0.18 μm CMOS process technology with all electronics integrated in an area of 0.40 mm(2). The chip has 4 channels, total power consumption of only 144 μW, and is impedance matched to silicon carbide biocompatible electrodes. PMID:26737437

  8. Adaptive Threshold Neural Spike Detector Using Stationary Wavelet Transform in CMOS.

    PubMed

    Yang, Yuning; Boling, C Sam; Kamboh, Awais M; Mason, Andrew J

    2015-11-01

    Spike detection is an essential first step in the analysis of neural recordings. Detection at the frontend eases the bandwidth requirement for wireless data transfer of multichannel recordings to extra-cranial processing units. In this work, a low power digital integrated spike detector based on the lifting stationary wavelet transform is presented and developed. By monitoring the standard deviation of wavelet coefficients, the proposed detector can adaptively set a threshold value online for each channel independently without requiring user intervention. A prototype 16-channel spike detector was designed and tested in an FPGA. The method enables spike detection with nearly 90% accuracy even when the signal-to-noise ratio is as low as 2. The design was mapped to 130 nm CMOS technology and shown to occupy 0.014 mm(2) of area and dissipate 1.7 μW of power per channel, making it suitable for implantable multichannel neural recording systems.

  9. SEE Sensitivity Analysis of 180 nm NAND CMOS Logic Cell for Space Applications

    NASA Astrophysics Data System (ADS)

    Sajid, Muhammad

    2016-07-01

    This paper focus on Single Event Effects caused by energetic particle strike on sensitive locations in CMOS NAND logic cell designed in 180nm technology node to be operated in space radiation environment. The generation of SE transients as well as upsets as function of LET of incident particle has been determined for logic devices onboard LEO and GEO satellites. The minimum magnitude pulse and pulse-width for threshold LET was determined to estimate the vulnerability /susceptibility of device for heavy ion strike. The impact of temperature, strike location and logic state of NAND circuit on total SEU/SET rate was estimated with physical mechanism simulations using Visual TCAD, Genius, runSEU program and Crad computer codes.

  10. CMOS RAM cosmic-ray-induced-error-rate analysis

    NASA Technical Reports Server (NTRS)

    Pickel, J. C.; Blandford, J. T., Jr.

    1981-01-01

    A significant number of spacecraft operational anomalies are believed to be associated with cosmic-ray-induced soft errors in the LSI memories. Test programs using a cyclotron to simulate cosmic rays have established conclusively that many common commercial memory types are vulnerable to heavy-ion upset. A description is given of the methodology and the results of a detailed analysis for predicting the bit-error rate in an assumed space environment for CMOS memory devices. Results are presented for three types of commercially available CMOS 1,024-bit RAMs. It was found that the HM6508 is susceptible to single-ion induced latchup from argon and krypton ions. The HS6508 and HS6508RH and the CDP1821 apparently are not susceptible to single-ion induced latchup.

  11. CMOS Imaging Device for Optical Imaging of Biological Activities

    NASA Astrophysics Data System (ADS)

    Shishido, Sanshiro; Oguro, Yasuhiro; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Ohta, Jun

    In this paper, we propose a CMOS image sensor device placed on the brain surface or cerebral sulcus (Fig. 1). The device has a photo detector array where a single optical detector is usually used. The proposed imaging device enables the analysis which reflects a surface blood pattern in the observed area. It is also possible to improve effective sensitivity by image processing and to simplify the measurement system by the CMOS sensor device with on-chip light source. We describe the design details and characterization of proposed device. We also demonstrate detection of hemoglobin oxygenation level with external light source, imaging capability of biological activities, and image processing for sensitivity improvement is also realized.

  12. A CMOS integrated timing discriminator circuit for fast scintillation counters

    SciTech Connect

    Jochmann, M.W.

    1998-06-01

    Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t{sub r} {ge} 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal`s amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range.

  13. A back-illuminated megapixel CMOS image sensor

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

    2005-01-01

    In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

  14. A CMOS image sensor dedicated to medical gamma camera application

    NASA Astrophysics Data System (ADS)

    Salahuddin, Nur S.; Paindavoine, Michel; Ginhac, Dominique; Parmentier, Michel; Tamda, Najia

    2005-03-01

    Generally, medical Gamma Camera are based on the Anger principle. These cameras use a scintillator block coupled to a bulky array of photomultiplier tube (PMT). To simplify this, we designed a new integrated CMOS image sensor in order to replace bulky PMT photodetetors. We studied several photodiodes sensors including current mirror amplifiers. These photodiodes have been fabricated using a CMOS 0.6 micrometers process from Austria Mikro Systeme (AMS). Each sensor pixel in the array occupies respectively, 1mm x 1mm area, 0.5mm x 0.5mm area and 0.2mm 0.2mm area with fill factor 98 % and total chip area is 2 square millimeters. The sensor pixels show a logarithmic response in illumination and are capable of detecting very low green light emitting diode (less than 0.5 lux) . These results allow to use our sensor in new Gamma Camera solid-state concept.

  15. CCD or CMOS camera calibration using point spread function

    NASA Astrophysics Data System (ADS)

    Abdelsalam, D. G.; Stanislas, M.; Coudert, S.

    2014-06-01

    We present a simple method based on the acquisition of a back-illuminated pinhole to estimate the point spread function (PSF) for CCD (or CMOS) sensor characterization. This method is used to measure the variations in sensitivity of the 2D-sensor array systems. The experimental results show that there is a variation in sensitivity for each position on the CCD of the calibrated camera and the pixel optical center error with respect to the geometrical center is in the range of 1/10th of a pixel. We claim that the pixel error comes most probably from the coherence of the laser light used, or eventually from possible defects in shape, surface quality, optical performance of micro-lenses, and the uniformity of the parameters across the wafer. This may have significant consequences for coherent light imaging using CCD (or CMOS) such as Particle Image Velocimetry.

  16. A Brief Discussion of Radiation Hardening of CMOS Microelectronics

    SciTech Connect

    Myers, D.R.

    1998-12-18

    Commercial microchips work well in their intended environments. However, generic microchips will not fimction correctly if exposed to sufficient amounts of ionizing radiation, the kind that satellites encounter in outer space. Modern CMOS circuits must overcome three specific concerns from ionizing radiation: total-dose, single-event, and dose-rate effects. Minority-carrier devices such as bipolar transistors, optical receivers, and solar cells must also deal with recombination-generation centers caused by displacement damage, which are not major concerns for majority-carrier CMOS devices. There are ways to make the chips themselves more resistant to radiation. This extra protection, called radiation hardening, has been called both a science and an art. Radiation hardening requires both changing the designs of the chips and altering the ways that the chips are manufactured.

  17. Graphene-based lateral heterostructure transistors exhibit better intrinsic performance than graphene-based vertical transistors as post-CMOS devices

    NASA Astrophysics Data System (ADS)

    Logoteta, Demetrio; Fiori, Gianluca; Iannaccone, Giuseppe

    2014-10-01

    We investigate the intrinsic performance of vertical and lateral graphene-based heterostructure field-effect transistors, currently considered the most promising options to exploit graphene properties in post-CMOS electronics. We focus on three recently proposed graphene-based transistors, that in experiments have exhibited large current modulation. Our analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the Non-Equilibrium Green's Function formalism. We show that the lateral heterostructure transistor has the potential to outperform CMOS technology and to meet the requirements of the International Technology Roadmap for Semiconductors for the next generation of semiconductor integrated circuits. On the other hand, we find that vertical heterostructure transistors miss these performance targets by several orders of magnitude, both in terms of switching frequency and delay time, due to large intrinsic capacitances, and unavoidable current/capacitance tradeoffs.

  18. Systematic analysis of CMOS-micromachined inductors with application to mixer matching circuits

    NASA Astrophysics Data System (ADS)

    Wu, Jerry Chun-Li

    The growing demand for consumer voice and data communication systems and military communication applications has created a need for low-power, low-cost, high-performance radio-frequency (RF) front-end. To achieve this goal, bringing passive components, especially inductors, to silicon is imperative. On-chip passive components such as inductors and capacitors generally enhance the reliability and efficiency of silicon-integrated RF cells. They can provide circuit solutions with superior performance and contribute to a higher level of integration. With passive components on chip, there is a great opportunity to have transformers, filters, and matching networks on chip. However, inductors on silicon have a low quality factor (Q) due to both substrate and metal loss. This dissertation demonstrates the systematic analysis of inductors fabricated using standard complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) system technologies. We report system-on-chip inductor modeling, simulation, and measurements of effective inductance and quality factors. In this analysis methodology, a number of systematic simulations are performed on regular and micromachined inductors with different parameters such as spiral topology, number of turns, outer diameter, thickness, and percentage of substrate removed by using micromachining technologies. Three different novel support structures of the micromachined spiral inductor are proposed, analyzed, and implemented for larger size suspended inductors. The sensitivity of the structure support and different degree of substrate etching by post-processing is illustrated. The results provide guidelines for the selection of inductor parameters, post-processing methodologies, and its spiral supports to meet the RF design specifications and the stability requirements for mobile communication. The proposed CMOS-micromachined inductor is used in a low cost-effective double-balanced Gilbert mixer with on-chip matching

  19. Low-loss CMOS copper plasmonic waveguides at the nanoscale (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Fedyanin, Dmitry Y.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.; Volkov, Valentyn S.

    2016-05-01

    Implementation of optical components in microprocessors can increase their performance by orders of magnitude. However, the size of optical elements is fundamentally limited by diffraction, while miniaturization is one of the essential concepts in the development of high-speed and energy-efficient electronic chips. Surface plasmon polaritons (SPPs) are widely considered to be promising candidates for the next generation of chip-scale technology thanks to the ability to break down the fundamental diffraction limit and manipulate optical signals at the truly nometer scale. In the past years, a variety of deep-subwavelength plasmonic structures have been proposed and investigated, including dielectric-loaded SPP waveguides, V-groove waveguides, hybrid plasmonic waveguides and metal nanowires. At the same time, for practical application, such waveguide structures must be integrated on a silicon chip and be fabricated using CMOS fabrication process. However, to date, acceptable characteristics have been demonstrated only with noble metals (gold and silver), which are not compatible with industry-standard manufacturing technologies. On the other hand, alternative materials introduce enormous propagation losses due absorption in the metal. This prevents plasmonic components from implementation in on-chip nanophotonic circuits. In this work, we experimentally demonstrate for the first time that copper plasmonic waveguides fabricated in a CMOS compatible process can outperform gold waveguides showing the same level of mode confinement and lower propagation losses. At telecommunication wavelengths, the fabricated ultralow-loss deep-subwavelength hybrid plasmonic waveguides ensure a relatively long propagation length of more than 50 um along with strong mode confinement with the mode size down to lambda^2/70, which is confirmed by direct scanning near-field optical microscopy (SNOM) measurements. These results create the backbone for design and development of high

  20. Large-area CMOS solid-state photomultipliers and recent developments

    NASA Astrophysics Data System (ADS)

    Johnson, Erik B.; Stapels, Christopher J.; Jie Chen, Xiao; Augustine, Frank L.; Christian, James F.

    2011-10-01

    The CMOS solid-state photomultiplier (SSPM) is an array of Geiger avalanche photodiodes (GPD) read out in parallel. These devices are not susceptible to magnetic fields, less expensive to fabricate than many other photodetector technologies, compact, and allow for on-chip integration of signal processing circuits. A number of nuclear detection applications require detector sizes on the order of 1 cm. Standard silicon fabrication technology limits the size of the SSPM die, and tiling of the silicon die can result in large-area devices but results in dead space between die for bonding purposes. Radiation Monitoring Devices (RMD) has fabricated 1×1 cm SSPM arrays on a single die. The size of these devices is large enough to provide an alternative detector for scintillation detector applications compared to photomultiplier tubes. Although the size increases the dark noise, we will demonstrate that the large-area SSPM can provide a PMT-like response for 22Na gamma rays using an LYSO crystal. Each of the noise terms associated with the large-area SSPM is discussed, quantifying the cross talk and after pulse multipliers, which are scaling factors to the gain to account for the additional output charge from the SSPM. The excess noise factor associated with cross talk and after pulsing has a linear dependence on the multiplier term. The signal and noise terms have been compiled to provide the best operating voltage of roughly 6 V above breakdown for a 1×1 cm CMOS SSPM to be operated with a short integration time (<10 ns) and at 0 °C.

  1. Microfluidic-optical integrated CMOS compatible devices for label-free biochemical sensing

    NASA Astrophysics Data System (ADS)

    Blanco, F. J.; Agirregabiria, M.; Berganzo, J.; Mayora, K.; Elizalde, J.; Calle, A.; Dominguez, C.; Lechuga, L. M.

    2006-05-01

    The fabrication, characterization and packaging of novel microfluidic-optical integrated biosensors for label-free biochemical detection is presented in this paper. The integrated device consists of a three-dimensional embedded microchannel network fabricated using enhanced CMOS compatible SU-8 multilevel polymer technology on top of a wafer containing Mach-Zehnder Interferometer (MZI) nanophotonic biosensor devices. PMMA housing provides connection to the macro-world and ensures robust leakage-free flow operation of the devices. This macro-microfluidic module can operate at pressure drops up to 1000 kPa. Fluid flow experiments have been performed in order to demonstrate the robustness of our microfluidic devices. The devices have been designed to operate under continuous flow. Steady-state flow rates ranging from 1 to 100 µl min-1 at pressure drops ranging from 10 to 500 kPa were measured in the laminar flow regime. Experimental results are in good agreement with laminar flow theory. The first interferometric sensing measurements are presented in order to demonstrate the functionality of these novel integrated devices for lab-on-a-chip and label-free biosensing applications. A bulk refractive index detection limit of 3.8 × 10-6 was obtained, close to the minimum detected up to now by label-free biosensor devices without microfluidic integration. As far as we know, this is the first time that a label-free biosensor device is integrated within a microfluidic network using a wafer-level CMOS compatible process technology.

  2. Flexible ultrathin-body single-photon avalanche diode sensors and CMOS integration.

    PubMed

    Sun, Pengfei; Ishihara, Ryoichi; Charbon, Edoardo

    2016-02-22

    We proposed the world's first flexible ultrathin-body single-photon avalanche diode (SPAD) as photon counting device providing a suitable solution to advanced implantable bio-compatible chronic medical monitoring, diagnostics and other applications. In this paper, we investigate the Geiger-mode performance of this flexible ultrathin-body SPAD comprehensively and we extend this work to the first flexible SPAD image sensor with in-pixel and off-pixel electronics integrated in CMOS. Experimental results show that dark count rate (DCR) by band-to-band tunneling can be reduced by optimizing multiplication doping. DCR by trap-assisted avalanche, which is believed to be originated from the trench etching process, could be further reduced, resulting in a DCR density of tens to hundreds of Hertz per micrometer square at cryogenic temperature. The influence of the trench etching process onto DCR is also proved by comparison with planar ultrathin-body SPAD structures without trench. Photon detection probability (PDP) can be achieved by wider depletion and drift regions and by carefully optimizing body thickness. PDP in frontside- (FSI) and backside-illumination (BSI) are comparable, thus making this technology suitable for both modes of illumination. Afterpulsing and crosstalk are negligible at 2µs dead time, while it has been proved, for the first time, that a CMOS SPAD pixel of this kind could work in a cryogenic environment. By appropriate choice of substrate, this technology is amenable to implantation for biocompatible photon-counting applications and wherever bended imaging sensors are essential. PMID:26907030

  3. Prototype CMOS SSPM solar particle dosimeter with tissue-equivalent sensor

    NASA Astrophysics Data System (ADS)

    Stapels, C. J.; Johnson, E. B.; Mukhopadhyay, S.; Chapman, E. C.; Christian, J. F.; Benton, Eric

    2009-08-01

    A dosimeter-on-a-chip (DoseChip) comprised of a tissue-equivalent scintillator coupled to a solid-state photomultiplier (SSPM) built using CMOS (complementary metal-oxide semiconductor) technology represents an ideal technology for a space-worthy, real-time solar-particle monitor for astronauts. It provides a tissue-equivalent response to the relevant energies and types of radiation for Low-Earth Orbit (LEO) and interplanetary space flight to the moon or Mars. The DoseChip will complement the existing Crew Passive Dosimeters by providing real-time dosimetry and as an alarming monitor for solar particle events (SPEs).[1] A prototype of the DoseChip, comprised of a 3 x 3 x 3 mm3 cube of BC-430 plastic scintillator coupled to a 2000-pixel SSPM, has successfully demonstrated response to protons at the NASA Space Radiation Laboratory (NSRL) at Brookhaven National Laboratory and at the HIMAC facility in Japan. The dynamic range of the dose has been verified over four orders of magnitude for particles with LET ranging from 0.2 keV/μm to 200 keV/μm, which includes 1-GeV protons to 420-MeV/n Fe nuclei. To exploit the benefits of the CMOS SSPM, we have developed our first autonomous prototype using the DoseChip. An analog circuit is used to process the signals from the SSPM, and an on-board microprocessor is used to digitize and store the pulse height information. Power is distributed over the device from a single dual voltage supply through various regulators and boost converters to appropriate supply voltages to each of the components.

  4. Potentials and challenges of integration for complex metal oxides in CMOS devices and beyond

    NASA Astrophysics Data System (ADS)

    Kim, Y.; Pham, C.; Chang, J. P.

    2015-02-01

    This review focuses on recent accomplishments on complex metal oxide based multifunctional materials and the potential they hold in advancing integrated circuits. It begins with metal oxide based high-κ materials to highlight the success of their integration since 45 nm complementary metal-oxide-semiconductor (CMOS) devices. By simultaneously offering a higher dielectric constant for improved capacitance as well as providing a thicker physical layer to prevent the quantum mechanical tunnelling of electrons, high-κ materials have enabled the continued down-scaling of CMOS based devices. The most recent technology driver has been the demand to lower device power consumption, which requires the design and synthesis of novel materials, such as complex metal oxides that exhibit remarkable tunability in their ferromagnetic, ferroelectric and multiferroic properties. These properties make them suitable for a wide variety of applications such as magnetoelectric random access memory, radio frequency band pass filters, antennae and magnetic sensors. Single-phase multiferroics, while rare, offer unique functionalities which have motivated much scientific and technological research to ascertain the origins of their multiferroicity and their applicability to potential devices. However, due to the weak magnetoelectric coupling for single-phase multiferroics, engineered multiferroic composites based on magnetostrictive ferromagnets interfacing piezoelectrics or ferroelectrics have shown enhanced multiferroic behaviour from effective strain coupling at the interface. In addition, nanostructuring of the ferroic phases has demonstrated further improvement in the coupling effect. Therefore, single-phase and engineered composite multiferroics consisting of complex metal oxides are reviewed in terms of magnetoelectric coupling effects and voltage controlled ferromagnetic properties, followed by a review on the integration challenges that need to be overcome to realize the

  5. SEMICONDUCTOR INTEGRATED CIRCUITS: A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

    NASA Astrophysics Data System (ADS)

    Xindong, Xiao; Luhong, Mao; Changliang, Yu; Shilin, Zhang; Sheng, Xie

    2009-12-01

    A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10-9. The chip dissipates 60 mW under a single 3.3 V supply.

  6. SEMICONDUCTOR DEVICES: RF CMOS modeling: a novel empirical large-signal model for an RF-MOSFET

    NASA Astrophysics Data System (ADS)

    Lingling, Sun; Binyi, Lü; Jun, Liu; Lei, Chen

    2010-04-01

    A novel empirical model for large-signal modeling of an RF-MOSFET is proposed. The proposed model is validated in the DC, AC, small-signal and large-signal characteristics of a 32-finger nMOSFET fabricated in SMIC's 0.18 μm RF CMOS technology. The power dissipation caused by self-heating is described. Excellent agreement is achieved between simulation and measurement for DC, S-parameters (50 MHz-40 GHz), and power characteristics, which shows that our model is accurate and reliable.

  7. A single shot TDC with 4.8 ps resolution in 40 nm CMOS for high energy physics applications

    NASA Astrophysics Data System (ADS)

    Prinzie, J.; Steyaert, M.; Leroux, P.

    2015-01-01

    A robust TDC with 4.8 ps bin width has been designed for harsh environments and high energy physics applications. The circuit uses resistive interpolation DLL with a novel dual phase detector architecture. This architecture improves startup- and recovery speed from single event strikes without control voltage ripple trade-off and requires no off-line calibrations. A 0.43 LSB DNL has been measured at a power consumption of 4.2 mW with an extended frequency range from 0.8 GHz to 2.4 GHz. The TDC has been processed in 40 nm CMOS technology.

  8. A MedRadio-band low-energy-per-bit 4-Mbps CMOS OOK receiver for implantable medical devices.

    PubMed

    Chou, Chia-Wei; Liu, Li-Chen; Wu, Chung-Yu

    2013-01-01

    A 4-Mbps 400-MHz On-Off Keying (OOK) receiver implemented in 0.18-um CMOS technology for implantable epilepsy sense-and-stimulation devices is presented. The proposed receiver is composed of a new current-mode full-wave envelope detector and differential cascaded gain amplifiers which is operated at MedRadio band. The fabricated receiver has power consumption of 0.27 mW and energy consumption of 0.07 nJ per bit at 4-Mbps. The sensitivity of receiver is -45.67 dBm.

  9. Characterization of a three side abuttable CMOS pixel sensor with digital pixel and data compression for charged particle tracking

    NASA Astrophysics Data System (ADS)

    Guilloux, F.; Değerli, Y.; Flouzat, C.; Lachkar, M.; Monmarthe, E.; Orsini, F.; Venault, P.

    2016-02-01

    CMOS monolithic pixel sensor technology has been chosen to equip the new ALICE trackers for HL-LHC . PIXAM is the final prototype from an R&D program specific to the Muon Forward Tracker which intends to push significantly forward the performances of the mature rolling shutter architecture. By implementing a digital pixel allowing to readout of a group of rows in parallel, the PIXAM sensor increases the rolling shutter readout speed while keeping the same power consumption as that of analogue pixel sensors. This paper will describe shortly the ASIC architecture and will focus on the analogue and digital performances of the sensor, obtained from laboratory measurements.

  10. Attenuation of single event induced pulses in CMOS combinational logic

    SciTech Connect

    Baze, M.P.; Buchner, S.P.

    1997-12-01

    Results are presented of a study of SEU generated transient pulse attenuation in combinational logic structures built using common digital CMOS design practices. SPICE circuit analysis, heavy ion tests, and pulsed, focused laser simulations were used to examine the response characteristics of transient pulse behavior in long logic strings. Results show that while there is an observable effect, it cannot be generally assumed that attenuation will significantly reduce observed circuit bit error rates.

  11. Hardening of commercial CMOS PROMs with polysilicon fusible links

    NASA Technical Reports Server (NTRS)

    Newman, W. H.; Rauchfuss, J. E.

    1985-01-01

    The method by which a commercial 4K CMOS PROM with polysilicon fuses was hardened and the feasibility of applying this method to a 16K PROM are presented. A description of the process and the necessary minor modifications to the original layout are given. The PROM circuit and discrete device characteristics over radiation to 1000K rad-Si are summarized. The dose rate sensitivity of the 4K PROMs is also presented.

  12. Linear dynamic range enhancement in a CMOS imager

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor)

    2008-01-01

    A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

  13. CMOS Alcohol Sensor Employing ZnO Nanowire Sensing Films

    NASA Astrophysics Data System (ADS)

    Santra, S.; Ali, S. Z.; Guha, P. K.; Hiralal, P.; Unalan, H. E.; Dalal, S. H.; Covington, J. A.; Milne, W. I.; Gardner, J. W.; Udrea, F.

    2009-05-01

    This paper reports on the utilization of zinc oxide nanowires (ZnO NWs) on a silicon on insulator (SOI) CMOS micro-hotplate for use as an alcohol sensor. The device was designed in Cadence and fabricated in a 1.0 μm SOI CMOS process at XFAB (Germany). The basic resistive gas sensor comprises of a metal micro-heater (made of aluminum) embedded in an ultra-thin membrane. Gold plated aluminum electrodes, formed of the top metal, are used for contacting with the sensing material. This design allows high operating temperatures with low power consumption. The membrane was formed by using deep reactive ion etching. ZnO NWs were grown on SOI CMOS substrates by a simple and low-cost hydrothermal method. A few nanometer of ZnO seed layer was first sputtered on the chips, using a metal mask, and then the chips were dipped in a zinc nitrate hexahydrate and hexamethylenetramine solution at 90° C to grow ZnO NWs. The chemical sensitivity of the on-chip NWs were studied in the presence of ethanol (C2H5OH) vapour (with 10% relative humidity) at two different temperatures: 200 and 250° C (the corresponding power consumptions are only 18 and 22 mW). The concentrations of ethanol vapour were varied from 175-1484 ppm (pers per million) and the maximum response was observed 40% (change in resistance in %) at 786 ppm at 250° C. These preliminary measurements showed that the on-chip deposited ZnO NWs could be a promising material for a CMOS based ethanol sensor.

  14. Accelerated life testing effects on CMOS microcircuit characteristics, phase 1

    NASA Technical Reports Server (NTRS)

    Maximow, B.

    1976-01-01

    An accelerated life test of sufficient duration to generate a minimum of 50% cumulative failures in lots of CMOS devices was conducted to provide a basis for determining the consistency of activation energy at 250 C. An investigation was made to determine whether any thresholds were exceeded during the high temperature testing, which could trigger failure mechanisms unique to that temperature. The usefulness of the 250 C temperature test as a predictor of long term reliability was evaluated.

  15. CMOS integration of inkjet-printed graphene for humidity sensing

    NASA Astrophysics Data System (ADS)

    Santra, S.; Hu, G.; Howe, R. C. T.; de Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-11-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  16. CMOS integration of inkjet-printed graphene for humidity sensing.

    PubMed

    Santra, S; Hu, G; Howe, R C T; De Luca, A; Ali, S Z; Udrea, F; Gardner, J W; Ray, S K; Guha, P K; Hasan, T

    2015-11-30

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  17. Development of CMOS Imager Block for Capsule Endoscope

    NASA Astrophysics Data System (ADS)

    Shafie, S.; Fodzi, F. A. M.; Tung, L. Q.; Lioe, D. X.; Halin, I. A.; Hasan, W. Z. W.; Jaafar, H.

    2014-04-01

    This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5V to 3.3V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5V to 3.3V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

  18. On-chip digital noise reduction for integrated CMOS Cameras

    NASA Astrophysics Data System (ADS)

    Rullmann, Markus; Schluessler, Jens-Uwe; Schueffny, Rene

    2003-06-01

    We propose an on-line noise reduction system especially designed for noisy CMOS image sensors. Image sequences from CMOS sensors in general are corrupted by two types of noise, temporal noise and fixed pattern noise (FPN). It is shown how the FPN component can be estimated from a sequence. We studied the theoretical performance of two different approaches called direct and indirect FPN estimation. We show that indirect estimation gives superior performance, both theoretically and by simulations. The FPN estimates can be used to improve the image quality by compensating it. We assess the quality of the estimates by the achievable SNR gains. Using those results a dedicated filtering scheme has been designed to accomplish both temporal noise reduction and FPN correction by applying a single noise filter. It allows signal gains of up to 12dB and provides a high visual quality of the results. We further analyzed and optimized the memory size and bandwidth requirements of our scheme and conclude that it is possible to implement it in hardware. The required memory size is 288kByte and the memory access rate is 70MHz. Our algorithm allows the integration of noisy CMOS sensors with digital noise reduction and other circuitry on a system-on-chip solution.

  19. Transversal-readout CMOS active pixel image sensor

    NASA Astrophysics Data System (ADS)

    Miyatake, Shigehiro; Ishida, Kouichi; Morimoto, Takashi; Masaki, Yasuo; Tanabe, Hideki

    2001-05-01

    This paper presents a CMOS active pixel image sensor (APS) with a transversal readout architecture that eliminates the vertically striped fixed pattern noise (FPN). There are two kinds of FPNs for CMOS APSs. One originates form the pixel- to-pixel variation in dark current and source-follower threshold voltage, and the other from the column-to-column variation in column readout structures. The former may become invisible in the future due to process improvements. However, the latter, which result sin a vertically striped FPN, is and will be conspicuous without some subtraction because of the correlation in the vertical direction. The pixel consists of a photodiode, a row- and a column-reset transistor, a source follower input transistor, and a column-select transistor instead of the row-select transistor in conventional CMOS APSs. The column-select transistor is connected to a signal line, which runs horizontally instead of vertically. Every horizontal signal line is merged into a single vertical signal line via a row- select transistor, which can be made large enough to make its on-resistence variation negligible because of its low driving frequency. Therefore, the sensor has neither a vertical nor horizontal stripe FPN.

  20. Noise sources and noise suppression in CMOS imagers

    NASA Astrophysics Data System (ADS)

    Pain, Bedabrata; Cunningham, Thomas J.; Hancock, Bruce R.

    2004-01-01

    Mechanisms for noise coupling in CMOS imagers are complex, since unlike a CCD, a CMOS imager has to be considered as a full digital-system-on-a-chip, with a highly sensitive front-end. In this paper, we analyze the noise sources in a photodiode CMOS imager, and model their propagation through the signal chain to determine the nature and magnitude of noise coupling. We present methods for reduction of noise, and present measured data to show their viability. For temporal read noise reduction, we present pixel signal chain design techniques to achieve near 2 electrons read noise. We model the front-end reset noise both for conventional photodiode and CTIA type of pixels. For the suppression of reset noise, we present a column feedback-reset method to reduce reset noise below 6 electrons. For spatial noise reduction, we present the design of column signal chain that suppresses both spatial noise and power supply coupling noise. We conclude by identifying problems in low-noise design caused by dark current spatial distribution.

  1. Optimizing quantum efficiency in a stacked CMOS sensor

    NASA Astrophysics Data System (ADS)

    Hannebauer, Rob; Yoo, Sang Keun; Gilblom, David L.; Gilblom, Alexander D.

    2011-03-01

    Optimizing quantum efficiency of image sensors, whether CCD or CMOS, has usually required backside thinning to bring the photon receiving surface close to the charge generation elements. A new CMOS sensor architecture has been developed that permits high-fill-factor photodiodes to be placed at the silicon surface without the need for backside thinning. The photodiode access provided by this architecture permits application of highly-effective anti-reflection coatings on the input surface and construction of a mirror inside the silicon below the photodiodes to effectively double the optical thickness of the silicon charge generation volume. Secondary benefits of this architecture include prevention of light from reaching the CMOS circuitry under the photodiodes, improvement of near-infrared quantum efficiency, and reduction in optical artifacts caused by reflections from the sensor surface. Utilizing these techniques, a sensor is being constructed with 4096 x 4096 pixels 4.8 μm square with 95% fill factor backed by a mirror tuned to the 400-700 nm visible band and a front-surface anti-reflectance coating. The quantum efficiency is expected to exceed 80% through the visible and the global shutter extinction ratio should exceed 106:1. The sensors have been fabricated and first test data is due in February 2011.

  2. CMOS integration of inkjet-printed graphene for humidity sensing

    PubMed Central

    Santra, S.; Hu, G.; Howe, R. C. T.; De Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10–80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

  3. Fully depleted, thick, monolithic CMOS pixels with high quantum efficiency

    NASA Astrophysics Data System (ADS)

    Clarke, A.; Stefanov, K.; Johnston, N.; Holland, A.

    2015-04-01

    The Centre for Electronic Imaging (CEI) has an active programme of evaluating and designing Complementary Metal-Oxide Semiconductor (CMOS) image sensors with high quantum efficiency, for applications in near-infrared and X-ray photon detection. This paper describes the performance characterisation of CMOS devices made on a high resistivity 50 μ m thick p-type substrate with a particular focus on determining the depletion depth and the quantum efficiency. The test devices contain 8 × 8 pixel arrays using CCD-style charge collection, which are manufactured in a low voltage CMOS process by ESPROS Photonics Corporation (EPC). Measurements include determining under which operating conditions the devices become fully depleted. By projecting a spot using a microscope optic and a LED and biasing the devices over a range of voltages, the depletion depth will change, causing the amount of charge collected in the projected spot to change. We determine if the device is fully depleted by measuring the signal collected from the projected spot. The analysis of spot size and shape is still under development.

  4. Image Sensors Enhance Camera Technologies

    NASA Technical Reports Server (NTRS)

    2010-01-01

    In the 1990s, a Jet Propulsion Laboratory team led by Eric Fossum researched ways of improving complementary metal-oxide semiconductor (CMOS) image sensors in order to miniaturize cameras on spacecraft while maintaining scientific image quality. Fossum s team founded a company to commercialize the resulting CMOS active pixel sensor. Now called the Aptina Imaging Corporation, based in San Jose, California, the company has shipped over 1 billion sensors for use in applications such as digital cameras, camera phones, Web cameras, and automotive cameras. Today, one of every three cell phone cameras on the planet feature Aptina s sensor technology.

  5. Investigation of CMOS photodiodes integrated on an ASIC by a 0.5-µm analog CMOS process

    NASA Astrophysics Data System (ADS)

    Luo, H.; Ricklefs, U.; Hillmer, H.

    2010-04-01

    The characteristics of photodiodes integrated on CMOS ASICs depend on wavelength of radiation, structure of the photodiode itself and the parameters of the process of production. In this paper, the influence of the structure of integrated CMOS photodiodes produced in a standard 0.5 μm mixed signal CMOS process on the sensitivity is described. These photodiodes are used as image sensor elements arranged in an array for noncontact optoelectronic measurements. Models of integrated photodiodes distinguish the lateral and the vertical region of the photodiodes. The standard 0.5 μm CMOS process offers three types of pn-junctions: n+/p-substrate, p+/n-well and n-well/p-substrate. Based on our previous research and on the results from other authors the p+/n-well is chosen due to its better sensitivity and isolation against other structures. The local sensitivity is measured with a scanning setup by applying a diffraction limited spot spot of light on the surface of the diodes. Independent of the wavelength of radiation the charge carriers are generated mainly in the lateral region and not - as expected - in the vertical region. The maximum value of the local sensitivity is found in photodiodes with subdivided p+ regions showing a distance of 1.5 μm between these regions in the space between these two adjacent p+ regions. This local sensitivity is three times smaller than that of a reference PIN photodiode. According to this result, the new photodiodes will be constructed with optimized geometries. All examined structures of this type of photodiodes show a maximal spectral sensitivity in the range of 650 nm - 700 nm.

  6. Development of a CMOS SOI Pixel Detector

    SciTech Connect

    Arai, Y.; Hazumi, M.; Ikegami, Y.; Kohriki, T.; Tajima, O.; Terada, S.; Tsuboyama, T.; Unno, Y.; Ushiroda, Y.; Ikeda, H.; Hara, K.; Ishino, H.; Kawasaki, T.; Miyake, H.; Martin, E.; Varner, G.; Tajima, H.; Ohno, M.; Fukuda, K.; Komatsubara, H.; Ida, J.; /NONE - OKI ELECTR INDUST TOKYO

    2008-08-19

    We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 {micro}m fully-depleted-SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 x 2.5 mm{sup 2} consisting of 20 x 20 {micro}m{sup 2} pixels have been designed and manufactured. Performance tests with a laser light illumination and a {beta} ray radioactive source indicate successful operation of the detector. We also briefly discuss the back gate effect as well as the simulation study.

  7. High-Voltage CMOS Controller for Microfluidics.

    PubMed

    Khorasani, M; Behnam, M; van den Berg, L; Backhouse, C J; Elliott, D G

    2009-04-01

    A high-voltage microfluidic controller designed using DALSA semiconductor's 0.8-mum low-voltage/high-voltage complementary metal-oxide semiconductor/double diffused metal-oxide semiconductor process is presented. The chip's four high-voltage output drivers can switch 300 V, and the dc-dc boost converter can generate up to 68 V using external passive components. This integrated circuit represents an advancement in microfluidic technology when used in conjunction with a charge coupling device (CCD)-based optical system and a glass microfluidic channel, enabling a portable and cost-efficient platform for genetic analysis.

  8. CMOS BDJ photodiode for trichromatic sensing

    NASA Astrophysics Data System (ADS)

    Tu, Lien; Setlur Nagesh, S. V.; Fu, ZhenHong; Titus, Albert H.

    2012-03-01

    A novel method for achieving trichromatic color detection using a single photodetector with less than three p-n junctions is presented. This new method removes the constraints of color sensing in buried-double-junction (BDJ) photodiode, eliminates the need for a priori light source knowledge or for changing color intensity. After using a single visible light optical filter to block irradiance external of visible spectrum, the color detection is achieved by taking the difference in depletion region photocurrent generated by different reverse bias voltages. This "difference output" effectively forms the "third" optical wavelength specific depletion region required for trichromatic color sensing. This method is based on exploiting the relationship between photon absorption and photon penetration depth of silicon, and the basic property of p-n junction photodiode which states that only photons absorbed within depletion region generate current. The theory is validated experimentally using BDJ photodiodes fabricated through MOSIS Inc. in the AMI-ABN 1.5um technology and ON-SEMI 0.5um technology. A commercial p-i-n photodiode is also being investigated for contrast and comparison.

  9. Technology.

    ERIC Educational Resources Information Center

    Giorgis, Cyndi; Johnson, Nancy J.

    2002-01-01

    Presents annotations of 30 works of children's literature that support the topic of technology and its influences on readers' daily lives. Notes some stories tell about a time when simple tools enabled individuals to accomplish tasks, and others feature visionaries who used technology to create buildings, bridges, roads, and inventions. Considers…

  10. Portable optical epidural needle-a CMOS-based system solution and its circuit design.

    PubMed

    Gong, Cihun-Siyong Alex; Lin, Shih-Pin; Mandell, M Susan; Tsou, Mei-Yung; Chang, Yin; Ting, Chien-Kun

    2014-01-01

    Epidural anesthesia is a common anesthesia method yet up to 10% of procedures fail to provide adequate analgesia. This is usually due to misinterpreting the tactile information derived from the advancing needle through the complex tissue planes. Incorrect placement also can cause dural puncture and neural injury. We developed an optic system capable of reliably identifying tissue planes surrounding the epidural space. However the new technology was too large and cumbersome for practical clinical use. We present a miniaturized version of our optic system using chip technology (first generation CMOS-based system) for logic functions. The new system was connected to an alarm that was triggered once the optic properties of the epidural were identified. The aims of this study were to test our miniaturized system in a porcine model and describe the technology to build this new clinical tool. Our system was tested in a porcine model and identified the epidural space in the lumbar, low and high thoracic regions of the spine. The new technology identified the epidural space in all but 1 of 46 attempts. Experimental results from our fabricated integrated circuit and animal study show the new tool has future clinical potential.

  11. The research on binocular stereo video imaging and display system based on low-light CMOS

    NASA Astrophysics Data System (ADS)

    Xie, Ruobing; Li, Li; Jin, Weiqi; Guo, Hong

    2015-10-01

    It is prevalent for the low-light night-vision helmet to equip the binocular viewer with image intensifiers. Such equipment can not only acquire night vision ability, but also obtain the sense of stereo vision to achieve better perception and understanding of the visual field. However, since the image intensifier is for direct-observation, it is difficult to apply the modern image processing technology. As a result, developing digital video technology in night vision is of great significance. In this paper, we design a low-light night-vision helmet with digital imaging device. It consists of three parts: a set of two low-illumination CMOS cameras, a binocular OLED micro display and an image processing PCB. Stereopsis is achieved through the binocular OLED micro display. We choose Speed-Up Robust Feature (SURF) algorithm for image registration. Based on the image matching information and the cameras' calibration parameters, disparity can be calculated in real-time. We then elaborately derive the constraints of binocular stereo display. The sense of stereo vision can be obtained by dynamically adjusting the content of the binocular OLED micro display. There is sufficient space for function extensions in our system. The performance of this low-light night-vision helmet can be further enhanced in combination with The HDR technology and image fusion technology, etc.

  12. Portable Optical Epidural Needle-A CMOS-Based System Solution and Its Circuit Design

    PubMed Central

    Gong, Cihun-Siyong Alex; Lin, Shih-Pin; Mandell, M. Susan; Tsou, Mei-Yung; Chang, Yin; Ting, Chien-Kun

    2014-01-01

    Epidural anesthesia is a common anesthesia method yet up to 10% of procedures fail to provide adequate analgesia. This is usually due to misinterpreting the tactile information derived from the advancing needle through the complex tissue planes. Incorrect placement also can cause dural puncture and neural injury. We developed an optic system capable of reliably identifying tissue planes surrounding the epidural space. However the new technology was too large and cumbersome for practical clinical use. We present a miniaturized version of our optic system using chip technology (first generation CMOS-based system) for logic functions. The new system was connected to an alarm that was triggered once the optic properties of the epidural were identified. The aims of this study were to test our miniaturized system in a porcine model and describe the technology to build this new clinical tool. Our system was tested in a porcine model and identified the epidural space in the lumbar, low and high thoracic regions of the spine. The new technology identified the epidural space in all but 1 of 46 attempts. Experimental results from our fabricated integrated circuit and animal study show the new tool has future clinical potential. PMID:25162150

  13. CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

    NASA Astrophysics Data System (ADS)

    Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

    2015-12-01

    Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard

  14. LGSD/NGSD: high speed optical CMOS imagers for E-ELT adaptive optics

    NASA Astrophysics Data System (ADS)

    Downing, Mark; Kolb, Johann; Balard, Philippe; Dierickx, Bart; Defernez, Arnaud; Feautrier, Philippe; Finger, Gert; Fryer, Martin; Gach, Jean-Luc; Guillaume, Christian; Hubin, Norbert; Jerram, Paul; Jorden, Paul; Meyer, Manfred; Payne, Andrew; Pike, Andrew; Reyes, Javier; Simpson, Robert; Stadler, Eric; Stent, Jeremy; Swift, Nick

    2014-07-01

    The success of the next generation of instruments for ELT class telescopes will depend upon improving the image quality by exploiting sophisticated Adaptive Optics (AO) systems. One of the critical components of the AO systems for the E-ELT has been identified as the optical Laser/Natural Guide Star WFS detector. The combination of large format, 1760×1680 pixels to finely sample the wavefront and the spot elongation of laser guide stars, fast frame rate of 700 frames per second (fps), low read noise (< 3e-), and high QE (> 90%) makes the development of this device extremely challenging. Design studies concluded that a highly integrated Backside Illuminated CMOS Imager built on High Resistivity silicon as the most likely technology to succeed. Two generations of the CMOS Imager are being developed: a) the already designed and manufactured NGSD (Natural Guide Star Detector), a quarter-sized pioneering device of 880×840 pixels capable of meeting first light needs of the E-ELT; b) the LGSD (Laser Guide Star Detector), the larger full size device. The detailed design is presented including the approach of using massive parallelism (70,400 ADCs) to achieve the low read noise at high pixel rates of ~3 Gpixel/s and the 88 channel LVDS 220Mbps serial interface to get the data off-chip. To enable read noise closer to the goal of 1e- to be achieved, a split wafer run has allowed the NGSD to be manufactured in the more speculative, but much lower read noise, Ultra Low Threshold Transistors in the unit cell. The NGSD has come out of production, it has been thinned to 12μm, backside processed and packaged in a custom 370pin Ceramic PGA (Pin Grid Array). First results of tests performed both at e2v and ESO are presented.

  15. Improved Design of Active Pixel CMOS Sensors for Charged Particle Detection

    SciTech Connect

    Deptuch, Grzegorz

    2007-11-12

    The Department of Energy (DOE) nuclear physics program requires developments in detector instrumentation electronics with improved energy, position and timing resolution, sensitivity, rate capability, stability, dynamic range, and background suppression. The current Phase-I project was focused on analysis of standard-CMOS photogate Active Pixel Sensors (APS) as an efficient solution to this challenge. The advantages of the CMOS APS over traditional hybrid approaches (i.e., separate detection regions bump-bonded to readout circuits) include greatly reduced cost, low power and the potential for vastly larger pixel counts and densities. However, challenges remain in terms of the signal-to-noise ratio (SNR) and readout speed (currently on the order of milliseconds), which is the major problem for this technology. Recent work has shown that the long readout time for photogate APS is due to the presence of (interface) traps at the semiconductor-oxide interface. This Phase-I work yielded useful results in two areas: (a) Advanced three-dimensional (3D) physics-based simulation models and simulation-based analysis of the impact of interface trap density on the transient charge collection characteristics of existing APS structures; and (b) Preliminary analysis of the feasibility of an improved photogate pixel structure (i.e., new APS design) with an induced electric field under the charge collecting electrode to enhance charge collection. Significant effort was dedicated in Phase-I to the critical task of implementing accurate interface trap models in CFDRC's NanoTCAD 3D semiconductor device-physics simulator. This resulted in validation of the new NanoTCAD models and simulation results against experimental (published) data, within the margin of uncertainty associated with obtaining device geometry, material properties, and experimentation details. Analyses of the new, proposed photogate APS design demonstrated several promising trends.

  16. Low Light CMOS Contact Imager with an Integrated Poly-Acrylic Emission Filter for Fluorescence Detection

    PubMed Central

    Dattner, Yonathan; Yadid-Pecht, Orly

    2010-01-01

    This study presents the fabrication of a low cost poly-acrylic acid (PAA) based emission filter integrated with a low light CMOS contact imager for fluorescence detection. The process involves the use of PAA as an adhesive for the emission filter. The poly-acrylic solution was chosen due its optical transparent properties, adhesive properties, miscibility with polar protic solvents and most importantly its bio-compatibility with a biological environment. The emission filter, also known as an absorption filter, involves dissolving an absorbing specimen in a polar protic solvent and mixing it with the PAA to uniformly bond the absorbing specimen and harden the filter. The PAA is optically transparent in solid form and therefore does not contribute to the absorbance of light in the visible spectrum. Many combinations of absorbing specimen and polar protic solvents can be derived, yielding different filter characteristics in different parts of the spectrum. We report a specific combination as a first example of implementation of our technology. The filter reported has excitation in the green spectrum and emission in the red spectrum, utilizing the increased quantum efficiency of the photo sensitive sensor array. The thickness of the filter (20 μm) was chosen by calculating the desired SNR using Beer-Lambert’s law for liquids, Quantum Yield of the fluorophore and the Quantum Efficiency of the sensor array. The filters promising characteristics make it suitable for low light fluorescence detection. The filter was integrated with a fully functional low noise, low light CMOS contact imager and experimental results using fluorescence polystyrene micro-spheres are presented. PMID:22399920

  17. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy.

    PubMed

    Valente, Virgilio; Demosthenous, Andreas

    2016-01-01

    This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm 2 , is capable of an operational bandwidth of 8 MHz and a linear gain in the range between -6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μ A. Each CR channel occupies an area of 0.21 mm 2 . The chip consumes between 530 μ A and 690 μ A per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis. PMID:27463721

  18. Multi-channel measurement for hetero-core optical fiber sensor by using CMOS camera

    NASA Astrophysics Data System (ADS)

    Koyama, Yuya; Nishiyama, Michiko; Watanabe, Kazuhiro

    2015-07-01

    Fiber optic smart structures have been developed over several decades by the recent fiber optic sensor technology. Optical intensity-based sensors, which use LD or LEDs, can be suitable for the monitor system to be simple and cost effective. In this paper, a novel fiber optic smart structure with human-like perception has been demonstrated by using intensity-based hetero-core optical fiber sensors system with the CMOS detector. The optical intensity from the hetero-core optical fiber bend sensor is obtained as luminance spots indicated by the optical power distributions. A number of optical intensity spots are simultaneously readout by taking a picture of luminance pattern. To recognize the state of fiber optic smart structure with the hetero-core optical fibers, the template matching process is employed with Sum of Absolute Differences (SAD). A fiber optic smart glove having five optic fiber nerves have been employed to monitor hand postures. Three kinds of hand postures have been recognized by means of the template matching process. A body posture monitoring has also been developed by placing the wearable hetero-core optical fiber bend sensors on the body segments. In order for the CMOS system to be a human brain-like, the luminescent spots in the obtained picture were arranged to make the pattern corresponding to the position of body segments. As a result, it was successfully demonstrated that the proposed fiber optic smart structure could recognize eight kinds of body postures. The developed system will give a capability of human brain-like processing to the existing fiber optic smart structures.

  19. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

    PubMed Central

    Valente, Virgilio; Demosthenous, Andreas

    2016-01-01

    This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm2, is capable of an operational bandwidth of 8 MHz and a linear gain in the range between −6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μA. Each CR channel occupies an area of 0.21 mm2. The chip consumes between 530 μA and 690 μA per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis. PMID:27463721

  20. Product assurance technology for custom LSI/VLSI electronics

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Blaes, B. R.; Jennings, G. A.; Moore, B. T.; Nixon, R. H.; Pina, C. A.; Sayah, H. R.; Sievers, M. W.; Stahlberg, N. F.

    1985-01-01

    The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.