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Sample records for 90nm digital cmos

  1. Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node

    NASA Technical Reports Server (NTRS)

    Ladbury, Raymond L.; Gorelick, Jerry L.; Berg, M. D.; Kim, H.; LaBel, K.; Friendlich, M.; Koga, R.; George, J.; Crain, S.; Yu, P.; Reed, R. A.

    2006-01-01

    We present Single Event Effect (SEE) and Total Ionizing Dose (TID) data for 1 Gbit DDR SDRAMs (90 nm CMOS technology) as well as comparing this data with earlier technology nodes from the same manufacturer.

  2. A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

    NASA Astrophysics Data System (ADS)

    Wenwei, He; Qiao, Meng; Yi, Zhang; Kai, Tang

    2014-08-01

    A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is presented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold amplifier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a differential nonlinearity < ±0.3 LSB and an integral nonlinearity < ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm2 with the pad. It consumes 210 mW from a 1.2 V single supply.

  3. 10-bit segmented current steering DAC in 90nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Bringas, R., Jr.; Dy, F.; Gerasta, O. J.

    2015-06-01

    This special project presents a 10-Bit 1Gs/s 1.2V/3.3V Digital-to-Analog Converter using1 Poly 9 Metal SAED 90-nm CMOS Technology intended for mixed-signal and power IC applications. To achieve maximum performance with minimum area, the DAC has been implemented in 6+4 Segmentation. The simulation results show a static performance of ±0.56 LSB INL and ±0.79 LSB DNL with a total layout chip area of 0.683 mm2.The segmented architecture is implemented using two sub DAC's, which are the LSB and MSB section with certain number bits. The DAC is designed using 4-BitBinary Weighted DAC for the LSB section and 6-BitThermometer-coded DAC for the MSB section. The thermometer-coded architecture provides the most optimized results in terms of linearity through reducing the clock feed-through effect especially in hot switching between multiple transistors. The binary- weighted architecture gives better linearity output in higher frequencies with better saturation in current sources.

  4. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    NASA Astrophysics Data System (ADS)

    Rivetti, A.; Battaglia, M.; Bisello, D.; Caselle, M.; Chalmet, P.; Costa, M.; Demaria, N.; Giubilato, P.; Ikemoto, Y.; Kloukinas, K.; Mansuy, C.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rousset, J.; Silvestrin, L.; Wyss, J.

    2013-12-01

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 Ω cm, which is at least one order of magnitude greater than the typical value (1 - 10 Ω cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported.

  5. IC design of low power, wide tuning range VCO in 90 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Zhu, Li; Zhigong, Wang; Zhiqun, Li; Qin, Li; Faen, Liu

    2014-12-01

    A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET (IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27-32.5 GHz, exhibiting a frequency tuning range (FTR) of 18.4% and a phase noise of -101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of -185 dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 mA DC current.

  6. Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90 nm CMOS process.

    PubMed

    Chen, Tung-Chien; Ma, Tsung-Chuan; Chen, Yun-Yu; Chen, Liang-Gee

    2012-01-01

    Accurate spike sorting is an important issue for neuroscientific and neuroprosthetic applications. The sorting of spikes depends on the features extracted from the neural waveforms, and a better sorting performance usually comes with a higher sampling rate (SR). However for the long duration experiments on free-moving subjects, the miniaturized and wireless neural recording ICs are the current trend, and the compromise on sorting accuracy is usually made by a lower SR for the lower power consumption. In this paper, we implement an on-chip spike sorting processor with integrated interpolation hardware in order to improve the performance in terms of power versus accuracy. According to the fabrication results in 90nm process, if the interpolation is appropriately performed during the spike sorting, the system operated at the SR of 12.5 k samples per second (sps) can outperform the one not having interpolation at 25 ksps on both accuracy and power.

  7. Low power, CMOS digital autocorrelator spectrometer for spaceborne applications

    NASA Technical Reports Server (NTRS)

    Chandra, Kumar; Wilson, William J.

    1992-01-01

    A 128-channel digital autocorrelator spectrometer using four 32 channel low power CMOS correlator chips was built and tested. The CMOS correlator chip uses a 2-bit multiplication algorithm and a full-custom CMOS VLSI design to achieve low DC power consumption. The digital autocorrelator spectrometer has a 20 MHz band width, and the total DC power requirement is 6 Watts.

  8. CMOS digital pixel sensors: technology and applications

    NASA Astrophysics Data System (ADS)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  9. A 0.5-GHz CMOS digital RF memory chip

    NASA Astrophysics Data System (ADS)

    Schnaitter, W. M.; Lewis, E. T.; Gordon, B. E.

    1986-10-01

    Digital RF memories (DRFM's) are key elements for modern radar jamming. An RF signal is sampled, stored in random access memory (RAM), and later recreated from the stored data. Here the first CMOS DRFM chip, integrating static RAM, control circuitry, and two channels of shift registers, on a single chip is described. The sample rate achieved was 0.5 GHz, VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.

  10. On-chip digital noise reduction for integrated CMOS Cameras

    NASA Astrophysics Data System (ADS)

    Rullmann, Markus; Schluessler, Jens-Uwe; Schueffny, Rene

    2003-06-01

    We propose an on-line noise reduction system especially designed for noisy CMOS image sensors. Image sequences from CMOS sensors in general are corrupted by two types of noise, temporal noise and fixed pattern noise (FPN). It is shown how the FPN component can be estimated from a sequence. We studied the theoretical performance of two different approaches called direct and indirect FPN estimation. We show that indirect estimation gives superior performance, both theoretically and by simulations. The FPN estimates can be used to improve the image quality by compensating it. We assess the quality of the estimates by the achievable SNR gains. Using those results a dedicated filtering scheme has been designed to accomplish both temporal noise reduction and FPN correction by applying a single noise filter. It allows signal gains of up to 12dB and provides a high visual quality of the results. We further analyzed and optimized the memory size and bandwidth requirements of our scheme and conclude that it is possible to implement it in hardware. The required memory size is 288kByte and the memory access rate is 70MHz. Our algorithm allows the integration of noisy CMOS sensors with digital noise reduction and other circuitry on a system-on-chip solution.

  11. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    PubMed

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-01

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

  12. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    PubMed

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-30

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

  13. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

    PubMed Central

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-01

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

  14. High-performance VGA-resolution digital color CMOS imager

    NASA Astrophysics Data System (ADS)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be

  15. A Low Power Digital Accumulation Technique for Digital-Domain CMOS TDI Image Sensor.

    PubMed

    Yu, Changwei; Nie, Kaiming; Xu, Jiangtao; Gao, Jing

    2016-01-01

    In this paper, an accumulation technique suitable for digital domain CMOS time delay integration (TDI) image sensors is proposed to reduce power consumption without degrading the rate of imaging. In terms of the slight variations of quantization codes among different pixel exposures towards the same object, the pixel array is divided into two groups: one is for coarse quantization of high bits only, and the other one is for fine quantization of low bits. Then, the complete quantization codes are composed of both results from the coarse-and-fine quantization. The equivalent operation comparably reduces the total required bit numbers of the quantization. In the 0.18 µm CMOS process, two versions of 16-stage digital domain CMOS TDI image sensor chains based on a 10-bit successive approximate register (SAR) analog-to-digital converter (ADC), with and without the proposed technique, are designed. The simulation results show that the average power consumption of slices of the two versions are 6 . 47 × 10 - 8 J/line and 7 . 4 × 10 - 8 J/line, respectively. Meanwhile, the linearity of the two versions are 99.74% and 99.99%, respectively. PMID:27669256

  16. Automatic Synthesis of CMOS Algorithmic Analog To-Digital Converter.

    NASA Astrophysics Data System (ADS)

    Jusuf, Gani

    The steady decrease in technological feature size is allowing increasing levels of integration in analog/digital interface functions. These functions consist of analog as well as digital circuits. While the turn around time for an all digital IC chip is very short due to the maturity of digital IC computer-aided design (CAD) tools over the last ten years, most analog circuits have to be designed manually due to the lack of analog IC CAD tools. As a result, analog circuit design becomes the bottleneck in the design of mixed signal processing chips. One common analog function in a mixed signal processing chip is an analog-to-digital conversion (ADC) function. This function recurs frequently but with varying performance requirements. The objective of this research is to study the design methodology of a compilation program capable of synthesizing ADC's with a broad range of sampling rates and resolution, and silicon area and performance comparable with the manual approach. The automatic compilation of the ADC function is a difficult problem mainly because ADC techniques span such a wide spectrum of performance, with radically different implementations being optimum for different ranges of conversion range, resolution, and power dissipation. We will show that a proper choice of the ADC architectures and the incorporation of many analog circuit design techniques will simplify the synthesis procedure tremendously. Moreover, in order to speed up the device sizing, hierarchical optimization procedure and behavioral simulation are implemented into the ADC module generation steps. As a result of this study, a new improved algorithmic ADC without the need of high precision comparators has been developed. This type of ADC lends itself to automatic generation due to its modularity, simplicity, small area consumption, moderate speed, low power dissipation, and single parameter trim capability that can be added at high resolution. Furthermore, a performance-driven CMOS ADC module

  17. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

    PubMed

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  18. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    PubMed Central

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  19. Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan A.; LaBel, Kenneth A.

    2010-01-01

    The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

  20. A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

    NASA Technical Reports Server (NTRS)

    Timoc, C.; Tran, T.; Wongso, J.

    1992-01-01

    This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

  1. CMOS cassette for digital upgrade of film-based mammography systems

    NASA Astrophysics Data System (ADS)

    Baysal, Mehmet A.; Toker, Emre

    2006-03-01

    While full-field digital mammography (FFDM) technology is gaining clinical acceptance, the overwhelming majority (96%) of the installed base of mammography systems are conventional film-screen (FSM) systems. A high performance, and economical digital cassette based product to conveniently upgrade FSM systems to FFDM would accelerate the adoption of FFDM, and make the clinical and technical advantages of FFDM available to a larger population of women. The planned FFDM cassette is based on our commercial Digital Radiography (DR) cassette for 10 cm x 10 cm field-of-view spot imaging and specimen radiography, utilizing a 150 micron columnar CsI(Tl) scintillator and 48 micron active-pixel CMOS sensor modules. Unlike a Computer Radiography (CR) cassette, which requires an external digitizer, our DR cassette transfers acquired images to a display workstation within approximately 5 seconds of exposure, greatly enhancing patient flow. We will present the physical performance of our prototype system against other FFDM systems in clinical use today, using established objective criteria such as the Modulation Transfer Function (MTF), Detective Quantum Efficiency (DQE), and subjective criteria, such as a contrast-detail (CD-MAM) observer performance study. Driven by the strong demand from the computer industry, CMOS technology is one of the lowest cost, and the most readily accessible technologies available for FFDM today. Recent popular use of CMOS imagers in high-end consumer cameras have also resulted in significant advances in the imaging performance of CMOS sensors against rivaling CCD sensors. This study promises to take advantage of these unique features to develop the first CMOS based FFDM upgrade cassette.

  2. IR CMOS: near infrared enhanced digital imaging (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Pralle, Martin U.; Carey, James E.; Joy, Thomas; Vineis, Chris J.; Palsule, Chintamani

    2015-08-01

    SiOnyx has demonstrated imaging at light levels below 1 mLux (moonless starlight) at video frame rates with a 720P CMOS image sensor in a compact, low latency camera. Low light imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancements are achieved by applying Black Silicon, SiOnyx's proprietary ultrafast laser semiconductor processing technology. In the near infrared, silicon's native indirect bandgap results in low absorption coefficients and long absorption lengths. The Black Silicon nanostructured layer fundamentally disrupts this paradigm by enhancing the absorption of light within a thin pixel layer making 5 microns of silicon equivalent to over 300 microns of standard silicon. This results in a demonstrate 10 fold improvements in near infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see spot. Imaging performance metrics will be discussed. Demonstrated performance characteristics: Pixel size : 5.6 and 10 um Array size: 720P/1.3Mpix Frame rate: 60 Hz Read noise: 2 ele/pixel Spectral sensitivity: 400 to 1200 nm (with 10x QE at 1064nm) Daytime imaging: color (Bayer pattern) Nighttime imaging: moonless starlight conditions 1064nm laser imaging: daytime imaging out to 2Km

  3. Note: All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters

    NASA Astrophysics Data System (ADS)

    Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, You-Ting; Liu, Keng-Chih

    2015-12-01

    This paper presents an all-digital CMOS pulse-shrinking mechanism suitable for time-to-digital converters (TDCs). A simple MOS capacitor is used as a pulse-shrinking cell to perform time attenuation for time resolving. Compared with a previous pulse-shrinking mechanism, the proposed mechanism provides an appreciably improved temporal resolution with high linearity. Furthermore, the use of a binary-weighted pulse-shrinking unit with scaled MOS capacitors is proposed for achieving a programmable resolution. A TDC involving the proposed mechanism was fabricated using a TSMC (Taiwan Semiconductor Manufacturing Company) 0.18-μm CMOS process, and it has a small area of nearly 0.02 mm2 and an integral nonlinearity error of ±0.8 LSB for a resolution of 24 ps.

  4. Note: All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters.

    PubMed

    Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, You-Ting; Liu, Keng-Chih

    2015-12-01

    This paper presents an all-digital CMOS pulse-shrinking mechanism suitable for time-to-digital converters (TDCs). A simple MOS capacitor is used as a pulse-shrinking cell to perform time attenuation for time resolving. Compared with a previous pulse-shrinking mechanism, the proposed mechanism provides an appreciably improved temporal resolution with high linearity. Furthermore, the use of a binary-weighted pulse-shrinking unit with scaled MOS capacitors is proposed for achieving a programmable resolution. A TDC involving the proposed mechanism was fabricated using a TSMC (Taiwan Semiconductor Manufacturing Company) 0.18-μm CMOS process, and it has a small area of nearly 0.02 mm(2) and an integral nonlinearity error of ±0.8 LSB for a resolution of 24 ps.

  5. Note: All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters.

    PubMed

    Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, You-Ting; Liu, Keng-Chih

    2015-12-01

    This paper presents an all-digital CMOS pulse-shrinking mechanism suitable for time-to-digital converters (TDCs). A simple MOS capacitor is used as a pulse-shrinking cell to perform time attenuation for time resolving. Compared with a previous pulse-shrinking mechanism, the proposed mechanism provides an appreciably improved temporal resolution with high linearity. Furthermore, the use of a binary-weighted pulse-shrinking unit with scaled MOS capacitors is proposed for achieving a programmable resolution. A TDC involving the proposed mechanism was fabricated using a TSMC (Taiwan Semiconductor Manufacturing Company) 0.18-μm CMOS process, and it has a small area of nearly 0.02 mm(2) and an integral nonlinearity error of ±0.8 LSB for a resolution of 24 ps. PMID:26724094

  6. A highly sensitive CMOS digital Hall sensor for low magnetic field applications.

    PubMed

    Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

    2012-01-01

    Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ± 2 mT magnetic field and output a digital Hall signal in a wide temperature range from -40 °C to 120 °C.

  7. A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications

    PubMed Central

    Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

    2012-01-01

    Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ±2 mT magnetic field and output a digital Hall signal in a wide temperature range from −40 °C to 120 °C. PMID:22438758

  8. Realization of the FPGA based TDI algorithm in digital domain for CMOS cameras

    NASA Astrophysics Data System (ADS)

    Tao, Shuping; Jin, Guang; Zhang, Xuyan; Qu, Hongsong

    2012-10-01

    In order to make the CMOS image sensors suitable for space high resolution imaging applications, a new method realizing TDI in digital domain by FPGA is proposed in this paper, which improves the imaging mode for area array CMOS sensors. The TDI algorithm accumulates the corresponding pixels of adjoining frames in digital domain, so the gray values increase by M times, where M is for the integration number, and the image's quality in signal-to-noise ratio can be improved. In addition, the TDI optimization algorithm is discussed. Firstly, the signal storage is optimized by 2 slices of external RAM, where memory depth expanding and the table tennis operation mechanism are used. Secondly, the FIFO operation mechanism reduces the reading and writing operation on memory by M×(M-1) times, It saves so much signal transfer time as is proportional to the square of integration number M2, that the frame frequency is able to increase greatly. At last, the CMOS camera based on TDI in digital domain is developed, and the algorithm is validated by experiments on it.

  9. A New Fully Differential CMOS Capacitance to Digital Converter for Lab-on-Chip Applications.

    PubMed

    Nabovati, Ghazal; Ghafar-Zadeh, Ebrahim; Mirzaei, Maryam; Ayala-Charca, Giancarlo; Awwad, Falah; Sawan, Mohamad

    2015-06-01

    In this paper, we present a new differential CMOS capacitive sensor for Lab-on-Chip applications. The proposed integrated sensor features a DC-input ΣΔ capacitance to digital converter (CDC) and two reference and sensing microelectrodes integrated on the top most metal layer in 0.35 μm CMOS process. Herein, we describe a readout circuitry with a programmable clocking strategy using a Charge Based Capacitance Measurement technique. The simulation and experimental results demonstrate a high capacitive dynamic range of 100 fF-110 fF, the sensitivity of 350 mV/fF and the minimum detectable capacitance variation of as low as 10 aF. We also demonstrate and discuss the use of this device for environmental applications through various chemical solvents.

  10. Low-noise CMOS SPAD arrays with in-pixel time-to-digital converters

    NASA Astrophysics Data System (ADS)

    Tosi, Alberto; Villa, Federica; Bronzi, Danilo; Zou, Yu; Lussana, Rudi; Tamborini, Davide; Tisa, Simone; Durini, Daniel; Weyers, Sascha; Pashen, Uwe; Brockherde, Werner; Zappa, Franco

    2014-05-01

    We present our latest results concerning CMOS Single-Photon Avalanche Diode (SPAD) arrays for high-throughput parallel single-photon counting. We exploited a high-voltage 0.35 μm CMOS technology in order to develop low-noise CMOS SPADs. The Dark Count Rate is 30 cps at room temperature for 30 μm devices, increases to 2 kcps for 100 μm SPADs and just to 100 kcps for 500 μm ones. Afterpulsing is less than 1% for hold-off time longer than 50 ns, thus allowing to reach high count rates. Photon Detection Efficiency is > 50% at 420 nm, > 40% below 500 nm and is still 5% at 850 nm. Timing jitter is less than 100 ps (FWHM) in SPADs with active area diameter up to 50 μm. We developed CMOS SPAD imagers with 150 μm pixel pitch and 30 μm SPADs. A 64×32 SPAD array is based on pixels including three 9-bit counters for smart phase-resolved photon counting up to 100 kfps. A 32x32 SPAD array includes 1024 10-bit Time-to-Digital Converters (TDC) with 300 ps resolution and 450 ps single-shot precision, for 3D ranging and FLIM. We developed also linear arrays with up to 60 pixels (with 100 μm SPAD, 150 μm pitch and in-pixel 250 ps TDC) for time-resolved parallel spectroscopy with high fill factor.

  11. CMOS-compatible InP/InGaAs digital photoreceiver

    DOEpatents

    Lovejoy, Michael L.; Rose, Benny H.; Craft, David C.; Enquist, Paul M.; Slater, Jr., David B.

    1997-01-01

    A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1000 Mb/s or more.

  12. CMOS-compatible InP/InGaAs digital photoreceiver

    DOEpatents

    Lovejoy, M.L.; Rose, B.H.; Craft, D.C.; Enquist, P.M.; Slater, D.B. Jr.

    1997-11-04

    A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1,000 Mb/s or more. 4 figs.

  13. A time-domain CMOS oscillator-based thermostat with digital set-point programming.

    PubMed

    Chen, Chun-Chi; Lin, Shih-Hao

    2013-01-29

    This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC) or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs) was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-mm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 µW at a sample rate of 10 samples/s.

  14. Development of CMOS Pixel Sensors with digital pixel dedicated to future particle physics experiments

    NASA Astrophysics Data System (ADS)

    Zhao, W.; Wang, T.; Pham, H.; Hu-Guo, C.; Dorokhov, A.; Hu, Y.

    2014-02-01

    Two prototypes of CMOS pixel sensor with in-pixel analog to digital conversion have been developed in a 0.18 μm CIS process. The first design integrates a discriminator into each pixel within an area of 22 × 33 μm2 in order to meet the requirements of the ALICE inner tracking system (ALICE-ITS) upgrade. The second design features 3-bit charge encoding inside a 35 × 35 μm2 pixel which is motivated by the specifications of the outer layers of the ILD vertex detector (ILD-VXD). This work aims to validate the concept of in-pixel digitization which offers higher readout speed, lower power consumption and less dead zone compared with the column-level charge encoding.

  15. A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems.

    PubMed

    Zheng, Xuezhe; Liu, Frankie; Patil, Dinesh; Thacker, Hiren; Luo, Ying; Pinguet, Thierry; Mekis, Attila; Yao, Jin; Li, Guoliang; Shi, Jing; Raj, Kannan; Lexau, Jon; Alon, Elad; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

    2010-01-01

    We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible.

  16. A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems.

    PubMed

    Zheng, Xuezhe; Liu, Frankie; Patil, Dinesh; Thacker, Hiren; Luo, Ying; Pinguet, Thierry; Mekis, Attila; Yao, Jin; Li, Guoliang; Shi, Jing; Raj, Kannan; Lexau, Jon; Alon, Elad; Ho, Ron; Cunningham, John E; Krishnamoorthy, Ashok V

    2010-01-01

    We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible. PMID:20173840

  17. Multiplexed Oversampling Digitizer in 65 nm CMOS for Column-Parallel CCD Readout

    SciTech Connect

    Grace, Carl; Walder, Jean-Pierre; von der Lippe, Henrik

    2012-04-10

    A digitizer designed to read out column-parallel charge-coupled devices (CCDs) used for high-speed X-ray imaging is presented. The digitizer is included as part of the High-Speed Image Preprocessor with Oversampling (HIPPO) integrated circuit. The digitizer module comprises a multiplexed, oversampling, 12-bit, 80 MS/s pipelined Analog-to-Digital Converter (ADC) and a bank of four fast-settling sample-and-hold amplifiers to instrument four analog channels. The ADC multiplexes and oversamples to reduce its area to allow integration that is pitch-matched to the columns of the CCD. Novel design techniques are used to enable oversampling and multiplexing with a reduced power penalty. The ADC exhibits 188 ?V-rms noise which is less than 1 LSB at a 12-bit level. The prototype is implemented in a commercially available 65 nm CMOS process. The digitizer will lead to a proof-of-principle 2D 10 Gigapixel/s X-ray detector.

  18. CMOS image sensor noise reduction method for image signal processor in digital cameras and camera phones

    NASA Astrophysics Data System (ADS)

    Yoo, Youngjin; Lee, SeongDeok; Choe, Wonhee; Kim, Chang-Yong

    2007-02-01

    Digital images captured from CMOS image sensors suffer Gaussian noise and impulsive noise. To efficiently reduce the noise in Image Signal Processor (ISP), we analyze noise feature for imaging pipeline of ISP where noise reduction algorithm is performed. The Gaussian noise reduction and impulsive noise reduction method are proposed for proper ISP implementation in Bayer domain. The proposed method takes advantage of the analyzed noise feature to calculate noise reduction filter coefficients. Thus, noise is adaptively reduced according to the scene environment. Since noise is amplified and characteristic of noise varies while the image sensor signal undergoes several image processing steps, it is better to remove noise in earlier stage on imaging pipeline of ISP. Thus, noise reduction is carried out in Bayer domain on imaging pipeline of ISP. The method is tested on imaging pipeline of ISP and images captured from Samsung 2M CMOS image sensor test module. The experimental results show that the proposed method removes noise while effectively preserves edges.

  19. A novel CMOS digital pixel sensor for 1D barcode scanning

    NASA Astrophysics Data System (ADS)

    Yan, Mei; DeGeronimo, Gianluigi; O'Connor, Paul; Carlson, Bradley S.

    2004-06-01

    A 1-D CMOS digital pixel image sensor system architecture is presented. Each pixel contains a photodiode, a low-power charge-sensitive amplifier, low noise sample/hold circuit, an 8-bit single-slope ADC, a 12-bit shift register and timing & control logic. The pixel is laid out on a 4μm pitch to enable a cost efficient implementation of high-resolution pixel arrays. Fixed pattern noise (FPN) is reduced by a charge-sensitive feedback amplifier, and the reset noise is cancelled by correlated double sampling read out. A prototype chip containing 512 pixels has been fabricated in the TSMC .25um logic process. A 40μV/e- conversion gain is measured with 100 e- rms read noise.

  20. A BiCMOS time interval digitizer based on fully-differential, current-steering circuits

    SciTech Connect

    Loinaz, M.J.; Wooley, B.A. . Center for Integrated Systems)

    1994-06-01

    A time interval digitizer cell with a 0--16 ns input range and a nominal LSB width of 1.0 ns has been integrated in a 2-[mu]m BiCMOS technology. The circuit exhibits both integral and differential nonlinearity below 0.15 LSB and a timing error of 0.32 ns RMS. Logic gate propagation delays are used as time measurement units, and the nominal value of the delays is set by an on-chip phase-locked loop (PLL). Fully-differential, current-steering circuits with low voltage swings are used to implement the time interval digitizer so as to generate minimal switching noise. The cell is to be used in the monolithic, multi-channel realization of a high-sensitivity, mixed-signal data acquisition front-end. By virtue of the time digitization architecture used, the average power dissipation of the cell is only 19.8 mW, despite the use of circuits that dissipate static power, and the layout area is a compact 448 [mu]m x 634 [mu]m.

  1. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology

    PubMed Central

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-01-01

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode’s current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm2 of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA. PMID:26205275

  2. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

    PubMed

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-07-22

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA.

  3. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

    PubMed

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-01-01

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA. PMID:26205275

  4. Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

    NASA Astrophysics Data System (ADS)

    Singh, Anil; Agarwal, Alpana

    2016-10-01

    A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

  5. Modeling and Experimental Demonstration of a Hopfield Network Analog-to-Digital Converter with Hybrid CMOS/Memristor Circuits

    PubMed Central

    Guo, Xinjie; Merrikh-Bayat, Farnood; Gao, Ligang; Hoskins, Brian D.; Alibart, Fabien; Linares-Barranco, Bernabe; Theogarajan, Luke; Teuscher, Christof; Strukov, Dmitri B.

    2015-01-01

    The purpose of this work was to demonstrate the feasibility of building recurrent artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS)/memristor circuits. To do so, we modeled a Hopfield network implementing an analog-to-digital converter (ADC) with up to 8 bits of precision. Major shortcomings affecting the ADC's precision, such as the non-ideal behavior of CMOS circuitry and the specific limitations of memristors, were investigated and an effective solution was proposed, capitalizing on the in-field programmability of memristors. The theoretical work was validated experimentally by demonstrating the successful operation of a 4-bit ADC circuit implemented with discrete Pt/TiO2−x/Pt memristors and CMOS integrated circuit components. PMID:26732664

  6. Modeling and Experimental Demonstration of a Hopfield Network Analog-to-Digital Converter with Hybrid CMOS/Memristor Circuits.

    PubMed

    Guo, Xinjie; Merrikh-Bayat, Farnood; Gao, Ligang; Hoskins, Brian D; Alibart, Fabien; Linares-Barranco, Bernabe; Theogarajan, Luke; Teuscher, Christof; Strukov, Dmitri B

    2015-01-01

    The purpose of this work was to demonstrate the feasibility of building recurrent artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS)/memristor circuits. To do so, we modeled a Hopfield network implementing an analog-to-digital converter (ADC) with up to 8 bits of precision. Major shortcomings affecting the ADC's precision, such as the non-ideal behavior of CMOS circuitry and the specific limitations of memristors, were investigated and an effective solution was proposed, capitalizing on the in-field programmability of memristors. The theoretical work was validated experimentally by demonstrating the successful operation of a 4-bit ADC circuit implemented with discrete Pt/TiO2- x /Pt memristors and CMOS integrated circuit components.

  7. A time digitizer CMOS gate-array with a 250 ps time resolution

    SciTech Connect

    Arai, Yasuo

    1996-02-01

    Recent high-energy physics experiments are demanding a pipeline (deadtime-less) time-to-digital converter (TDC) with a time resolution of better than 500 ps and a double-pulse resolution of less than 30 ns. The TDC must keep all of the timing history until a trigger signal arrives about 3 {micro}s later. In large experiments, since the number of channels used is more than 100 k, the device must have a low power dissipation, a high circuit density and a low cost. A pipelined time digitizer CMOS gate-array has been developed using 0.5 {micro}m Sea-of-Gate technology. Precise timing signals which are used to sample input signals are generated from 32 taps of an asymmetric ring oscillator. The frequency of the oscillator is controlled by a phase-locked loop (PLL) circuit which runs in the 10--50 MHz frequency range. A test chip has been developed and tested; a time resolution of 250 ps rms at 40 MHz clock was measured. The chip has 4 channels and encoding circuits for both the rising and the falling edges of the input signals. The chip has 128-word dual-port memories, allowing the histories of the input signals to be stored and causing no deadtime for the conversion.

  8. Achieving CDU requirement for 90-nm technology node and beyond with advanced mask making process technology

    NASA Astrophysics Data System (ADS)

    Tzu, San-De; Chang, Chung-Hsing; Chen, Wen-Chi; Kliem, Karl-Heinz; Hudek, Peter; Beyer, Dirk

    2005-01-01

    For 90nm node and beyond technology generations, one of the most critical challenges is how to meet the local CD uniformity (proximity) and global CD uniformity (GCDU) requirements within the exposure field. Both of them must be well controlled in the mask making process: (1) proximity effect and, (2) exposure pattern loading effect, or the so-called e-beam "fogging effect". In this paper, we report a method to improve our global CDU by means of a long range fogging compensation together with the Leica SB350 MW. This exposure tool is operated at 50keV and 1nm design grid. The proximity correction is done by the software - package "PROXECCO" from PDF Solutions. We have developed a unique correction method to reduce the fogging effect in dependency of the pattern density of the mask. This allows us to meet our customers" CDU specifications for the 90nm node and beyond.

  9. Design and image-quality performance of high resolution CMOS-based X-ray imaging detectors for digital mammography

    NASA Astrophysics Data System (ADS)

    Cha, B. K.; Kim, J. Y.; Kim, Y. J.; Yun, S.; Cho, G.; Kim, H. K.; Seo, C.-W.; Jeon, S.; Huh, Y.

    2012-04-01

    In digital X-ray imaging systems, X-ray imaging detectors based on scintillating screens with electronic devices such as charge-coupled devices (CCDs), thin-film transistors (TFT), complementary metal oxide semiconductor (CMOS) flat panel imagers have been introduced for general radiography, dental, mammography and non-destructive testing (NDT) applications. Recently, a large-area CMOS active-pixel sensor (APS) in combination with scintillation films has been widely used in a variety of digital X-ray imaging applications. We employed a scintillator-based CMOS APS image sensor for high-resolution mammography. In this work, both powder-type Gd2O2S:Tb and a columnar structured CsI:Tl scintillation screens with various thicknesses were fabricated and used as materials to convert X-ray into visible light. These scintillating screens were directly coupled to a CMOS flat panel imager with a 25 × 50 mm2 active area and a 48 μm pixel pitch for high spatial resolution acquisition. We used a W/Al mammographic X-ray source with a 30 kVp energy condition. The imaging characterization of the X-ray detector was measured and analyzed in terms of linearity in incident X-ray dose, modulation transfer function (MTF), noise-power spectrum (NPS) and detective quantum efficiency (DQE).

  10. 324GHz CMOS VCO Using Linear Superimposition Technique

    NASA Technical Reports Server (NTRS)

    Daquan, Huang; LaRocca, Tim R.; Samoska, Lorene A; Fung, Andy; Chang, Frank

    2007-01-01

    Terahertz (frequencies ranged from 300GHz to 3THz) imaging and spectroscopic systems have drawn increasing attention recently due to their unique capabilities in detecting and possibly analyzing concealed objects. The generation of terahertz signals is nonetheless nontrivial and traditionally accomplished by using either free-electron radiation, optical lasers, Gunn diodes or fundamental oscillation by using III-V based HBT/HEMT technology[1-3]... We have substantially extended the operation range of deep-scaled CMOS by using a linear superimposition method, in which we have realized a 324GHz VCO in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage. This may also pave the way for ultra-high data rate wireless communications beyond that of IEEE 802.15.3c and reach data rates comparable to that of fiber optical communications, such as OC768 (40Gbps) and beyond.

  11. Specifications and methodologies for benchmarking of advanced CD-SEMs at the 90-nm CMOS technology node and beyond

    NASA Astrophysics Data System (ADS)

    Bunday, Benjamin D.; Bishop, Michael

    2003-05-01

    In this work, an extremely flexible and simple dissolution rate monitor (DRM) based on inexpensive, commercially available, PC card spectrometers has been built that can be used quite robustly in both fab and laboratory environments for measuring the dissolution behavior of photoreist films. The hardware required in order to construct such a simple apparatus has been discussed along with various experimental configurations that are appropriate for different measurement tasks. A multiwavelength interferometric data analysis software (MIDAS) has been developed in this work that can robustly perform both single wavelength and multiwavelength DRM data analysis. The multiwavelength DRM and MIDAS software have been found to be very useful in analyzing a variety of resist film dissolution phenomena including monitoring films possessing dissolution rates exceeding 100 nm/s and studying resist film surface inhibition/acceleration. Another useful application has been to measure swelling in the processing of photoresists and other polymer thin films. The basic approaches and algorithms used for thin film thickness and dissolution rate determination in the MIDAS software are discussed in this paper. Results from the use of the MIDAS software in various applications are presented.

  12. Characterization of a three side abuttable CMOS pixel sensor with digital pixel and data compression for charged particle tracking

    NASA Astrophysics Data System (ADS)

    Guilloux, F.; Değerli, Y.; Flouzat, C.; Lachkar, M.; Monmarthe, E.; Orsini, F.; Venault, P.

    2016-02-01

    CMOS monolithic pixel sensor technology has been chosen to equip the new ALICE trackers for HL-LHC . PIXAM is the final prototype from an R&D program specific to the Muon Forward Tracker which intends to push significantly forward the performances of the mature rolling shutter architecture. By implementing a digital pixel allowing to readout of a group of rows in parallel, the PIXAM sensor increases the rolling shutter readout speed while keeping the same power consumption as that of analogue pixel sensors. This paper will describe shortly the ASIC architecture and will focus on the analogue and digital performances of the sensor, obtained from laboratory measurements.

  13. Micropower CMOS Integrated Low-Noise Amplification, Filtering, and Digitization of Multimodal Neuropotentials.

    PubMed

    Mollazadeh, M; Murari, K; Cauwenberghs, G; Thakor, N

    2009-02-01

    Electrical activity in the brain spans a wide range of spatial and temporal scales, requiring simultaneous recording of multiple modalities of neurophysiological signals in order to capture various aspects of brain state dynamics. Here, we present a 16-channel neural interface integrated circuit fabricated in a 0.5 mum 3M2P CMOS process for selective digital acquisition of biopotentials across the spectrum of neural signal modalities in the brain, ranging from single spike action potentials to local field potentials (LFP), electrocorticograms (ECoG), and electroencephalograms (EEG). Each channel is composed of a tunable bandwidth, fixed gain front-end amplifier and a programmable gain/resolution continuous-time incremental DeltaSigma analog-to-digital converter (ADC). A two-stage topology for the front-end voltage amplifier with capacitive feedback offers independent tuning of the amplifier bandpass frequency corners, and attains a noise efficiency factor (NEF) of 2.9 at 8.2 kHz bandwidth for spike recording, and a NEF of 3.2 at 140 Hz bandwidth for EEG recording. The amplifier has a measured midband gain of 39.6 dB, frequency response from 0.2 Hz to 8.2 kHz, and an input-referred noise of 1.94 muV rms while drawing 12.2 muA of current from a 3.3 V supply. The lower and higher cutoff frequencies of the bandpass filter are adjustable from 0.2 to 94 Hz and 140 Hz to 8.2 kHz, respectively. At 10-bit resolution, the ADC has an SNDR of 56 dB while consuming 76 muW power. Time-modulation feedback in the ADC offers programmable digital gain (1-4096) for auto-ranging, further improving the dynamic range and linearity of the ADC. Experimental recordings with the system show spike signals in rat somatosensory cortex as well as alpha EEG activity in a human subject. PMID:20046962

  14. A 75 ps rms time resolution BiCMOS time to digital converter optimized for high rate imaging detectors

    NASA Astrophysics Data System (ADS)

    Hervé, C.; Torki, K.

    2002-04-01

    This paper presents an integrated time to digital converter (TDC) with a bin size adjustable in the range of 125 to 175 ps and a differential nonlinearity of ±0.3%. The TDC has four channels. Its architecture has been optimized for the readout of imaging detectors in use at Synchrotron Radiation facilities. In particular, a built-in logic flags piled-up events. Multi-hit patterns are also supported for other applications. Time measurements are extracted off chip at the maximum throughput of 40 MHz. The dynamic range is 14 bits. It has been fabricated in 0.8 μm BiCMOS technology. Time critical inputs are PECL compatible whereas other signals are CMOS compatible. A second application specific integrated circuit (ASIC) has been developed which translates NIM electrical levels to PECL ones. Both circuits are used to assemble board level TDCs complying with industry standards like VME, NIM and PCI.

  15. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    NASA Astrophysics Data System (ADS)

    Yin, Lan; Bozler, Carl; Harburg, Daniel V.; Omenetto, Fiorenzo; Rogers, John A.

    2015-01-01

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  16. Non-chemical cleaning technology for sub-90nm design node photomask manufacturing

    NASA Astrophysics Data System (ADS)

    Hoyeh, Star; Chen, Richard; Kozuma, Makoto; Kuo, Joann; Huang, Torey; Chen, Frank F.

    2006-10-01

    Cleaning chemistry residue in photomask manufacturing is one of root causes to generate HAZE over surface of photomask for 193nm and shorter wavelength exposure tools. In order to reduce the residue, chemical free process is one of targets in photomask industry. In this paper novel clean technology without sulfuric acid and ammonia chemical are shown to manufacture sub-90nm node photomask. Photo and E-beam resist were removed by plasma and ozone water clean instead of sulfuric acid. SPM and APM in final clean sequence before defect inspection were substituted with ozone water and hydrogen water respectively. The clean performance was demonstrated in real production of 193nm phase shift mask. Sulfate and Ammonia residue after final clean were controlled same as blank material level without any clean process.

  17. ArF processing of 90-nm design rule lithography achieved through enhanced thermal processing

    NASA Astrophysics Data System (ADS)

    Kagerer, Markus; Miller, Daniel; Chang, Wayne; Williams, Daniel J.

    2006-03-01

    As the lithography community has moved to ArF processing on 300 mm wafers for 90 nm design rules the process characterization of the components of variance continues to highlight the thermal requirements for the post exposure bake (PEB) processing step. In particular as the thermal systems have become increasingly uniform, the transient behavior of the thermal processing system has received the focus of attention. This paper demonstrates how a newly designed and patented thermal processing system was optimized for delivering improved thermal uniformity during a typical 90 second PEB processing cycle, rather than being optimized for steady state performance. This was accomplished with the aid of a wireless temperature measurement wafer system for obtaining real time temperature data and by using a response surface model (RSM) experimental design for optimizing parameters of the temperature controller of the thermal processing system. The new units were field retrofitted seamlessly in <2 days at customer sites without disruption to process recipes or flows. After evaluating certain resist parameters such as PEB temperature sensitivity and post exposure delay (PED) - stability of the baseline process, the new units were benchmarked against the previous PEB plates by processing a split lot experiment. Additional hardware characterization included environmental factors such as air velocity in the vicinity of the PEB plates and transient time between PEB and chill plate. At the completion of the optimization process, the within wafer CD uniformity displayed a significant improvement when compared to the previous hardware. The demonstrated within wafer CD uniformity improved by 27% compared to the initial hardware and baseline process. ITRS requirements for the 90 nm node were exceeded.

  18. Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

    NASA Astrophysics Data System (ADS)

    Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

    2015-06-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

  19. Evaluation of IDEALSmile for 90-nm FLASH memory contact holes imaging with ArF scanner

    NASA Astrophysics Data System (ADS)

    Cantu, Pietro; Capetti, Gianfranco; Loi, Sara; Lupo, Marco; Pepe, Annalisa; Saitoh, Kenji; Yamazoe, Kenji; Hasegawa, Yasuo; Iwasa, Junji; Toublan, Olivier R.

    2004-05-01

    According to sizes dictated by ITRS road map, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. The development of 90[nm] technology FLASH memories requires a robust solution for printing contact holes down to 100[nm] on 200[nm] pitch. The delay of NGL development as well as open issues related to 157[nm] scanner introduction pushes the industry to find a solution for printing such tight features using existing ArF scanner. IDEALSmile technology from Canon was proven to be a good candidate for achieving such high resolution with sufficiently large through pitch process window using a binary mask, relatively simple to be manufactured, with a modified illumination and single exposure, with no impact on throughput and without any increase of cost of ownership. This paper analyses main issues related to the introduction of this new resolution enhancement technology on a real FLASH memory device, highlighting advantages as well as known problems still under investigation.

  20. Transport and noise in 90nm n-GaAs Epilayers

    NASA Astrophysics Data System (ADS)

    Gilbertson, A.; Moore, J. D.; Perkins, G.; Gallop, J.; Cohen, L. F.; Newaz, A. K. M.; Solin, S. A.

    2009-03-01

    Extraordinary Magnetoresistance (EMR) belongs to the family of EXX effects which form the basis for a number of devices that offer the potential for high sensitivity applications. Such devices would benefit from minimising the active volume of the sensor. To reduce that volume and minimize wafer fabrication complexity it is desirable to employ unltra-thin GaAs epilayers. Accordingly, we report here the transport and noise properties of 90nm Si-doped GaAs films grown by molecular beam epitaxy which have been fabricated into both microscopic EMR devices and macroscopic van der Pauw geometries. These films exhibit a room temperature electron mobility and density of 3225 cm^2V-1s-1 and1.45x10^17cm-3, respectively, and show only a 6% variation over the temperature range 2K

  1. In-line 90 nm Technology Gate Oxide Nitrogen Monitoring With Non-Contact Electrical Technique

    NASA Astrophysics Data System (ADS)

    Pic, Nicolas; Polisski, Gennadi; Paire, Emmanuel; Rizzo, Véronique; Grosjean, Catherine; Bortolotti, Benjamin; D'Amico, John; Cabuil, Nicolas

    2009-09-01

    The continuous race to reduce the dimensions of IC components has lead to the introduction of Nitrogen in the thin gate oxide layer in order to increase the dielectric constant and to improve the gate dielectric properties. It is mandatory to apply in-line monitoring to control the amount of Nitrogen to ensure that electrical behavior is correct over time. Historically, this monitoring was performed by measuring the delay to reoxidation (D2R) with an ellipsometer. But, this method is not suitable in production as it is depending on both initial oxidation and reoxidation reproducibility, which implies implementing dedicated Statistical Process Control (SPC) monitoring at these two specific processing steps. We are here presenting an alternative method to D2R for 90 nm Technology gate oxide grown by Rapid Thermal Process (RTP). Applying a non-contact Metrology technique, which couples Kelvin probe surface voltage measurement with surface Corona deposition, directly after the nitridation step, the interface trapped charge (QIT) is obtained by integration of the interface state density over the space charge region. In summary, this electrical non-contact monitoring is more sensitive to the Nitrogen content compared to ellipsometer measurement after nitridation or after D2R, less sensitive compared to D2R to any initial oxide variation, and it allows simplification of the qualification procedure at this process step by skipping the reoxidation.

  2. A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics

    SciTech Connect

    Lemkin, M.; Boser, B.E.

    1999-04-01

    This paper describes a three-axis accelerometer implemented in a surface-micromachining technology with integrated CMOS. The accelerometer measures changes in a capacitive half-bridge to detect deflections of a proof mass, which result from acceleration input. The half-bridge is connected to a fully differential position-sense interface, the output of which is used for one-bit force feedback. By enclosing the proof mass in a one-bit feedback loop, simultaneous force balancing and analog-to-digital conversion are achieved. On-chip digital offset-trim electronics enable compensation of random offset in the electronic interface. Analytical performance calculations are shown to accurately model device behavior. The fabricated single-chip accelerometer measures 4 {times} 4 mm{sup 2}, draws 27 mA from a 5-V supply, and has a dynamic range of 84, 81, and 70 dB along the x-, y-, and z-axes, respectively.

  3. Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization

    SciTech Connect

    Zhao, Chumin; Kanicki, Jerzy; Konstantinidis, Anastasios C.; Patel, Tushita

    2015-11-15

    Purpose: Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50–300 e{sup −}) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). Methods: In this study, imaging performance of a large area (29 × 23 cm{sup 2}) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165–400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. Results: The LFW mode shows better DQE at low air kerma (K{sub a} < 10 μGy) and should be used for DBT. At current DBT applications, air kerma (K{sub a} ∼ 10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165–400 μm in size can be resolved using a MGD range of 0.3–1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at

  4. Asymmetric MQW semiconductor optical amplifier with low-polarization sensitivity of over 90-nm bandwidth

    NASA Astrophysics Data System (ADS)

    Nkanta, Julie E.; Maldonado-Basilio, Ramón; Abdul-Majid, Sawsan; Zhang, Jessica; Hall, Trevor J.

    2013-12-01

    An exhausted capacity of current Passive Optical Networks has been anticipated as bandwidth-hungry applications such as HDTV and 3D video become available to end-users. To enhance their performance, the next generation optical access networks have been proposed, using optical carriers allocated within the E-band (1360-1460 nm). It is partly motivated by the low-water peak fiber being manufactured by Corning. At these wavelengths, choices for low cost optical amplifiers, with compact size, low energy consumption and feasibility for integration with other optoelectronic components are limited, making the semiconductor optical amplifiers (SOA) a realistic solution. An experimental characterization of a broadband and low polarization sensitive asymmetric multi quantum well (MQW) SOA operating in the E-band is reported. The SOA device is composed of nine 6 nm In1-xGaxAsyP1-y 0.2% tensile strained asymmetric MQW layers sandwiched between nine latticed matched 6 nm InGaAsP barrier layers. The active region is grown on an n-doped InP substrate and buried by p-doped InGaAsP layers. The SOA devices have 7-degrees tilt anti-reflected coated facets, with 2 μm ridge width, and a cavity length of 900 μm. For input powers of -10 dBm and -20 dBm, a maximum gain of 20 dB at 1360 nm with a polarization insensitivity under 3 dB for over 90 nm bandwidth is measured. Polarization sensitivity of less than 0.5 dB is observed for some wavelengths. Obtained results indicate a promising SOA with broadband amplification, polarization insensitivity and high gain. These SOAs were designed and characterized at the Photonics Technology Laboratory, University of Ottawa, Canada.

  5. A 70μm × 70μm CMOS digital active pixel sensor for digital mammography and X-ray imaging

    NASA Astrophysics Data System (ADS)

    Sabadell, J.; Figueras, R.; Margarit, J. M.; Martín, E.; Terès, L.; Serra-Graells, F.

    2011-03-01

    This work presents an architecture for CMOS active pixel sensors (APS) based on a novel lossless charge integration method, proposed for X-ray imagers in general but specifically optimized for full-field digital mammography. The objective is to provide all the required functionality inside the pixel, so to use full digital control and read-out signals only, therefore avoiding crosstalk between analog lines over large pixel arrays. It includes a novel lossless A/D conversion scheme besides a self-calibrating dark current cancellation circuit, a self-biasing circuitry, biphasic current sensing for the collection of electrons (e-) or holes (h+) and built-in test. Furthermore, FPN compensation is available by individually addressing the pixel's internal DAC controlling the gain. Implemented in a 0.18μm 1P6M CMOS technology with MiM capacitors, everything fits into a 70μm by 70μm due to the extensive reuse of available blocks and aggressive layout techniques. Also, thanks to the MOSFET subthreshold operation, the average power consumption is as low as 8μW/pixel.

  6. IR CMOS: the digital nightvision solution to sub-1 mLux imaging

    NASA Astrophysics Data System (ADS)

    Pralle, M. U.; Carey, J. E.; Vineis, C.; Palsule, C.; Jiang, J.; Joy, T.

    2015-05-01

    SiOnyx has demonstrated imaging at light levels below 1 mLux at 60 FPS with a 720P CMOS image sensor in a compact, low latency camera. The camera contains a 1 inch (16 mm) optical format sensor and streams uncompressed video over CameraLink with row wise image latency below 1 msec. Sub mLux imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancement is achieved by utilizing SiOnyx's proprietary ultrafast laser semiconductor processing technology that enhances the absorption of light within a thin pixel layer. Our technology demonstrates a 10 fold improvement in infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see-spot.

  7. Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

    NASA Technical Reports Server (NTRS)

    Buchner, S.; McMorrow, D.; Sibley, M.; Eaton, P.; Mavis, D.; Dusseau, L.; Roche, N. J-H.; Bernard, M.

    2009-01-01

    This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

  8. A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

    NASA Astrophysics Data System (ADS)

    Weidong, Yang; Jiandong, Zang; Tiehu, Li; Pu, Luo; Jie, Pu; Ruitao, Zhang; Chao, Chen

    2015-10-01

    This paper presents a 16-bit 2 GSPS digital-to-analog converter (DAC) in 0.18 μm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB & INL less than ±4.3 LSB after the chip is calibrated.

  9. DOE experiment for scattering bars optimization at the 90nm node

    NASA Astrophysics Data System (ADS)

    Bouton, G.; Connolly, B.; Courboin, D.; Di Giacomo, A.; Gasnier, F.; Lallement, R.; Parker, D.; Pindo, M.; Richoilley, J. C.; Royere, F.; Rameau-Savio, A.; Tissier, M.

    2011-03-01

    Scattering bars (SB) are sub-resolution lines added to the original database during Resolution Enhancement Techniques (RET) treatments. Their goal is stabilizing the CD of the adjacent polygons (by suppressing or reducing secondary diffraction waves). SB increase the process window in the litho process by lowering the first derivative of the CD. Moreover, the detailed knowledge of SB behavior around the fab working point is a must for future shrinks and for preparing the next technology nodes. SB are inserted in the generation of critical levels for STMicroelectronics 90 nm technology embedded memories before invoking the Model for Optical Proximity Corrections (MBOPC). This allows the software to calculate their contribution to the intensity in the aerial image and integrate their effects in Edge Proximity Error (EPE) corrections. However the Rule-Based insertion of these assist features still leaves behind occurrences of conflicting priorities as in the image below. (See manuscript PDF)Detection of Hot Spots in 2D simulations for die treatment validation (done on BRION equipment on each critical level before mask making) is in most cases correlated with SB singularities, at least for CD non-uniformity, bridging issues and necking in correspondence with OPC fragmentation effects. Within the framework of the MaXSSIMM project, we established a joint STMicroelectronics and Toppan Photomasks team to explore the influence of assist features (CD, distance), convex and concave corner rounding and CD uniformity by means of specific test patterns. The proposed study concerns the algorithms used to define the mask shop input as well as the physical mask etching. A set of test cases, based on elementary test patterns, each one including a list of geometrical variations, has been defined. As the number of configurations becomes rapidly very large (tens of thousands) we had to apply Design of Experiments (DOE) algorithms in order to reduce the number of measurements to a

  10. A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

    PubMed

    Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

    2014-01-01

    A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

  11. CAOS-CMOS camera.

    PubMed

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

  12. CAOS-CMOS camera.

    PubMed

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems. PMID:27410361

  13. Multipoint laser Doppler vibrometry using holographic optical elements and a CMOS digital camera.

    PubMed

    Connelly, Michael J; Szecówka, Przemyslaw M; Jallapuram, Raghavendra; Martin, Suzanne; Toal, Vincent; Whelan, Maurice P

    2008-02-15

    A laser Doppler vibrometer (LDV) is described in which holographic optical elements are used to provide the interferometer reference and object illumination beams. A complementary metal-oxide semiconductor camera, incorporating a digital signal processor, is used to carry out real-time signal processing of the interferometer output to allow multipoint LDV to be implemented.

  14. Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

    NASA Astrophysics Data System (ADS)

    Nogami, T.; Lane, S.; Fukasawa, M.; Ida, K.; Angyal, M.; Chanda, K.; Chen, F.; Christiansen, C.; Cohen, S.; Cullinan, M.; Dziobkowski, C.; Fitzsimmons, J.; Flaitz, P.; Grill, A.; Gill, J.; Inoue, K.; Klymko, N.; Kumar, K.; Labelle, C.; Lane, M.; Li, B.; Liniger, E.; Madon, A.; Malone, K.; Martin, J.; McGahay, V.; McLaughlin, P.; Melville, I.; Minami, M.; Molis, S.; Nguyen, S.; Penny, C.; Restaino, D.; Sakamoto, A.; Sankar, M.; Sherwood, M.; Simonyi, E.; Shimooka, Y.; Tai, L.; Widodo, J.; Wildman, H.; Ono, M.; McHerron, D.; Nye, H.; Davis, C.; Sankaran, S.; Edelstein, D.; Ivers, T.

    2005-11-01

    This paper discusses low-k/copper integration schemes which has been in production in the 90 nm node, have been developed in the 65 nm node, and should be taken in the 45 nm node. While our baseline 65 nm BEOL process has been developed by extension and simple shrinkage of our PECVD SiCOH integration which has been in production in the 90 nm node with our SiCOH film having k=3.0, the 65 nm SiCOH integration has two other options to go to extend to lower capacitance. One is to add porosity to become ultra low-k (ULK). The other is to stay with low-k SiCOH, which is modified to have a "lower-k". The effective k- value attained with the lower-k (k=2.8) SiCOH processed in the "Direct CMP" scheme is very close to that with an ULK (k=2.5) SiCOH film built with the "Hard Mask Retention" scheme. This paper first describes consideration of these two damascene schemes, whose comparison leads to the conclusion that the lower-k SiCOH integration can have more advantages in terms of process simplicity and extendibility of our 90 nm scheme under certain assumptions. Then describing the k=2.8 SiCOH film development and its successful integration, damascene schemes for 45nm nodes are discussed based on our learning from development of the lower-k 65nm scheme. Capability of modern dry etchers to define the finer patterns, non-uniformity of CMP, and susceptibility to plasma and mechanical strength and adhesion of ULK are discussed as factors to hamper the applicability of ULK.

  15. Experimental characterization of a 10 μW 55 μm-pitch FPN-compensated CMOS digital pixel sensor for X-ray imagers

    NASA Astrophysics Data System (ADS)

    Figueras, Roger; Martínez, Ricardo; Terés, Lluís; Serra-Graells, Francisco

    2014-10-01

    This paper presents experimental results obtained from both electrical and radiation tests of a new room-temperature digital pixel sensor (DPS) circuit specifically optimized for digital direct X-ray imaging. The 10 μW 55 μm-pitch CMOS active pixel circuit under test includes self-bias capability, built-in test, selectable e-/h+ collection, 10-bit charge-integration A/D conversion, individual gain tuning for fixed pattern noise (FPN) cancellation, and digital-only I/O interface, which make it suitable for 2D modular chip assemblies in large and seamless sensing areas. Experimental results for this DPS architecture in 0.18 μm 1P6M CMOS technology are reported, returning good performance in terms of linearity, 2 kerms- of ENC, inter-pixel crosstalk below 0.5 LSB, 50 Mbps of I/O speed, and good radiation response for its use in digital X-ray imaging.

  16. Novel Circuitry Configuration with Paired-Cell Erase Operation for High-Density 90-nm Embedded Resistive Random Access Memory

    NASA Astrophysics Data System (ADS)

    Sato, Yoshihiro; Tsunoda, Koji; Aoki, Masaki; Sugiyama, Yoshihiro

    2009-04-01

    We propose a novel circuitry configuration for high-density 90-nm embedded resistive random access memory (ReRAM). The memory cells are operated at 2 V, and a small memory cell size of 6F2 consisting of a 1.2-V standard transistor and a resistive junction (1T-1R) is designed, where F is the feature size. The unique circuitry configuration is that each pair of source-lines connects to each source-line selective gate. Therefore, erasing is done by a pair of cells in turn in the whole sector, while the reading or programming is done by a random accessing operation. We simulated the ReRAM circuit for read and write operations with SPICE. As a result, we found that 5-ns high-speed read access was obtained in the 256-word lines (WLs) × 256-bit lines (BLs) and that the SET/RESET operation was stable.

  17. Performance evaluation of a digital intraoral imaging device based on the CMOS photosensor array coupled with an integrated X-ray conversion fiber-optic faceplate

    NASA Astrophysics Data System (ADS)

    Cho, Hyosung; Choi, Sungil; Kim, Jongguk; Koo, Yangseo; Kim, Taewoo; Ro, Changjoon; Lee, Bongsoo; Kim, Sin; Kim, Hokyung

    2007-08-01

    As a continuation of our digital X-ray imaging sensor R&D, we have developed a cost-effective, intraoral imaging device based on the complementary-metal-oxide semiconductor (CMOS) photosensor array coupled with an integrated X-ray conversion fiber-optic faceplate. It consists of a commercially available CMOS photosensor of a 35×35 μm 2 pixel size and a 688×910 pixel array dimension, and a high-efficiency columnar CsI(Tl) scintillator of a 90 μm thickness directly deposited on a fiber-optic faceplate of a 6 μm core size and an 1.46 mm thickness with 85/15 core-cladding ratio (NA˜1.0 in air). The fiber-optic faceplate is a highly X-ray attenuating material that minimizes X-ray absorption on the end CMOS photosensor array, thus, minimizing X-ray induced noise at the photosensor array. It uses a high light-output columnar CsI(Tl) scintillator with a peak spectral emission at 545 nm, giving better spatial resolution, but attenuates some of this light due to interfacial and optical attenuation factors. In this paper, we presented the performance analysis of the intraoral imaging device with experimental measurements and acquired X-ray images in terms of modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE).

  18. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis

    NASA Astrophysics Data System (ADS)

    Zhao, C.; Konstantinidis, A. C.; Zheng, Y.; Anaxagoras, T.; Speller, R. D.; Kanicki, J.

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm-1 and a DQE of around 0.5 at spatial frequencies  <1 mm-1. In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered.

  19. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    PubMed

    Zhao, C; Konstantinidis, A C; Zheng, Y; Anaxagoras, T; Speller, R D; Kanicki, J

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm(-1) and a DQE of around 0.5 at spatial frequencies  <1 mm(-1). In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered. PMID:26540090

  20. Ion traps fabricated in a CMOS foundry

    SciTech Connect

    Mehta, K. K.; Ram, R. J.; Eltony, A. M.; Chuang, I. L.; Bruzewicz, C. D.; Sage, J. M. Chiaverini, J.

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  1. Digital pixel readout integrated circuit architectures for LWIR

    NASA Astrophysics Data System (ADS)

    Shafique, Atia; Yazici, Melik; Kayahan, Huseyin; Ceylan, Omer; Gurbuz, Yasar

    2015-06-01

    This paper presents and discusses digital pixel readout integrated circuit architectures for long wavelength infrared (LWIR) in CMOS technology. Presented architectures are designed for scanning and staring arrays type detectors respectively. For scanning arrays, digital time delay integration (TDI) is implemented on 8 pixels with sampling rate up to 3 using CMOS 180nm technology. Input referred noise of ROIC is below 750 rms electron meanwhile power dissipation is appreciably under 30mW. ROIC design is optimized to perform at room as well as cryogenic temperatures. For staring type arrays, a digital pixel architecture relying on coarse quantization with pulse frequency modulation (PFM) and novel approach of extended integration is presented. It can achieve extreme charge handling capacity of 2.04Ge- with 20 bit output resolution and power dissipation below 350 nW in CMOS 90nm technology. Efficient mechanism of measuring the time to estimate the remaining charge on integration capacitor in order to achieve low SNR has employed.

  2. Optimization of building blocks for multi-stage 17-44 dB 6.1-9.6 mW 90-nm K-band front-ends

    NASA Astrophysics Data System (ADS)

    Roy, Apratim; Harun Rashid, A.

    2013-12-01

    In this article, five two-stage ˜6-mW and four three-stage ˜9-mW matched amplifier architectures are proposed to establish optimization procedure and quantify relative merits of cascode (CC), common-gate (CG), and commonsource (CS) building blocks for low-voltage low-power multi-stage front-ends. The circuits are simulated with a 90-nm CMOS technology including modeling of layout parasites. Integrated bias trees and passive port matching networks are incorporated in the K-band designs. In the face of process mismatch, variability in noise and gain figures remains <0.39 dB and <7.1 dB from the design values. The five combinations of building blocks in twostage low-power (6.1-6.6 mW) amplifiers achieve linearity (IIP3) in the range of -5.2˜-13.5 dBm, good reverse isolation (better than -26 dB), 2.89-3.82 dB noise penalties, and 17.2-25.5 dB peak forward gain. In case of threestage front-ends built with CS, CC, and CG blocks (power rating 9.2-9.6 mW), forward gain and optimized noise figures are found as >33 dB and <3.26 dB, respectively. They achieve -2.5˜18.3 dBm IIP3, <-39 dB reverse isolation, and <-17 dB minimum IRL. The results are compared with reported simulated findings on CMOS multistage amplifiers to highlight their relative advantages in terms of power requirement and decibel(gain)-per-watt.

  3. A data parallel digitizer for a time-based simulation of CMOS Monolithic Active Pixel Sensors with FairRoot

    NASA Astrophysics Data System (ADS)

    Sitzmann, P.; Amar-Youcef, S.; Doering, D.; Deveaux, M.; Fröhlich, I.; Koziel, M.; Krebs, E.; Linnik, B.; Michel, J.; Milanovic, B.; Müntz, C.; Li, Q.; Stroth, J.; Tischler, T.

    2014-06-01

    CMOS Monolithic Active Pixel Sensors (MAPS) demonstrated excellent performances in the field of charged particle tracking. They feature an excellent single point resolution of few μm, a light material budget of 0.05% Xo in combination with a good radiation tolerance and time resolution. This makes the sensors a valuable technology for micro vertex detectors (MVD) of various experiments in heavy ion and particle physics like STAR and CBM. State of the art MAPS are equipped with a rolling shutter readout. Therefore, the data of one individual event is typically found in more than one data train generated by the sensor. This paper presents a concept to introduce this feature in both simulation and data analysis, taking profit of the sensor topology of the MVD. This topology allows to use for massive parallel data streaming and handling strategies within the FairRoot framework.

  4. Synchrotron based planar imaging and digital tomosynthesis of breast and biopsy phantoms using a CMOS active pixel sensor.

    PubMed

    Szafraniec, Magdalena B; Konstantinidis, Anastasios C; Tromba, Giuliana; Dreossi, Diego; Vecchio, Sara; Rigon, Luigi; Sodini, Nicola; Naday, Steve; Gunn, Spencer; McArthur, Alan; Olivo, Alessandro

    2015-03-01

    The SYRMEP (SYnchrotron Radiation for MEdical Physics) beamline at Elettra is performing the first mammography study on human patients using free-space propagation phase contrast imaging. The stricter spatial resolution requirements of this method currently force the use of conventional films or specialized computed radiography (CR) systems. This also prevents the implementation of three-dimensional (3D) approaches. This paper explores the use of an X-ray detector based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology as a possible alternative, for acquisitions both in planar and tomosynthesis geometry. Results indicate higher quality of the images acquired with the synchrotron set-up in both geometries. This improvement can be partly ascribed to the use of parallel, collimated and monochromatic synchrotron radiation (resulting in scatter rejection, no penumbra-induced blurring and optimized X-ray energy), and partly to phase contrast effects. Even though the pixel size of the used detector is still too large - and thus suboptimal - for free-space propagation phase contrast imaging, a degree of phase-induced edge enhancement can clearly be observed in the images. PMID:25498332

  5. Low Temperature Testing of a Radiation Hardened CMOS 8-Bit Flash Analog-to-Digital (A/D) Converter

    NASA Technical Reports Server (NTRS)

    Gerber, Scott S.; Hammond, Ahmad; Elbuluk, Malik E.; Patterson, Richard L.; Overton, Eric; Ghaffarian, Reza; Ramesham, Rajeshuni; Agarwal, Shri G.

    2001-01-01

    Power processing electronic systems, data acquiring probes, and signal conditioning circuits are required to operate reliably under harsh environments in many of NASA:s missions. The environment of the space mission as well as the operational requirements of some of the electronic systems, such as infrared-based satellite or telescopic observation stations where cryogenics are involved, dictate the utilization of electronics that can operate efficiently and reliably at low temperatures. In this work, radiation-hard CMOS 8-bit flash A/D converters were characterized in terms of voltage conversion and offset in the temperature range of +25 to -190 C. Static and dynamic supply currents, ladder resistance, and gain and offset errors were also obtained in the temperature range of +125 to -190 C. The effect of thermal cycling on these properties for a total of ten cycles between +80 and - 150 C was also determined. The experimental procedure along with the data obtained are reported and discussed in this paper.

  6. Digital-pixel focal plane array development

    NASA Astrophysics Data System (ADS)

    Brown, Matthew G.; Baker, Justin; Colonero, Curtis; Costa, Joe; Gardner, Tom; Kelly, Mike; Schultz, Ken; Tyrrell, Brian; Wey, Jim

    2010-01-01

    Since 2006, MIT Lincoln Laboratory has been developing Digital-pixel Focal Plane Array (DFPA) readout integrated circuits (ROICs). To date, four 256 × 256 30 μm pitch DFPA designs with in-pixel analog to digital conversion have been fabricated using IBM 90 nm CMOS processes. The DFPA ROICs are compatible with a wide range of detector materials and cutoff wavelengths; HgCdTe, QWIP, and InGaAs photo-detectors with cutoff wavelengths ranging from 1.6 to 14.5 μm have been hybridized to the same digital-pixel readout. The digital-pixel readout architecture offers high dynamic range, A/C or D/C coupled integration, and on-chip image processing with low power orthogonal transfer operations. The newest ROIC designs support two-color operation with a single Indium bump connection. Development and characterization of the two-color DFPA designs is presented along with applications for this new digital readout technology.

  7. Advanced mask technique to improve bit line CD uniformity of 90 nm node flash memory in low-k1 lithography

    NASA Astrophysics Data System (ADS)

    Kim, Jong-doo; Choi, Jae-young; Kim, Jea-hee; Han, Jae-won

    2008-10-01

    As devices size move toward 90nm technology node or below, defining uniform bit line CD of flash devices is one of the most challenging features to print in KrF lithography. There are two principal difficulties in defining bit line on wafer. One is insufficient process margin besides poor resolution compared with ArF lithography. The other is that asymmetric bit line should be made for OPC(Optical Proximity Correction) modeling. Therefore advanced ArF lithography scanner should be used for define bit line with RETs (Resolution Enhancement Techniques) such as immersion lithography, OPC, PSM(Phase Shift Mask), high NA(Numerical Aperture), OAI(Off-Axis Illumination), SRAF(Sub-resolution Assistant Feature), and mask biasing.. Like this, ArF lithography propose the method of enhancing resolution, however, we must spend an enormous amount of CoC(cost of ownership) to utilize ArF photolithography process than KrF. In this paper, we suggest method to improve of bit line CD uniformity, patterned by KrF lithographic process in 90nm sFlash(stand alone Flash) devices. We applied new scheme of mask manufacturing, which is able to realize 2 different types of mask, binary and phase-shift, into one plate. Finally, we could get the more uniform bit lines and we expect to get more stable properties then before applying this technique.

  8. Large area CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; Guerrini, N.; Sedgwick, I.

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  9. Design of a 10-bit segmented current-steering digital-to-analog converter in CMOS 65 nm technology for the bias of new generation readout chips in high radiation environment

    NASA Astrophysics Data System (ADS)

    De Robertis, G.; Loddo, F.; Mattiazzo, S.; Pacher, L.; Pantano, D.; Tamma, C.

    2016-01-01

    A new pixel front end chip for HL-LHC experiments in CMOS 65nm technology is under development by the CERN RD53 collaboration together with the Chipix65 INFN project. This work describes the design of a 10-bit segmented current-steering Digital-to-Analog Converter (DAC) to provide a programmable bias current to the analog blocks of the circuit. The main requirements are monotonicity, good linearity, limited area consumption and radiation hardness up to 10 MGy. The DAC was prototyped and electrically tested, while irradiation tests will be performed in Autumn 2015.

  10. Optical hybrid package with an 8-channel 18GT/s CMOS transceiver for chip-to-chip optical interconnect

    NASA Astrophysics Data System (ADS)

    Mohammed, E.; Liao, J.; Kern, A.; Lu, D.; Braunisch, H.; Thomas, T.; Hyvonen, S.; Palermo, S.; Young, I. A.

    2008-02-01

    We describe the design and development of a high-speed 8-channel hybrid integrated optical transceiver package with Clock and Data Recovery (CDR) circuits. The package concept has been developed to be compatible with microprocessor package technology and at the same time allow the integration of low cost, high-performance optical components. A 90nm CMOS optical transceiver chip, 850nm 10Gb/s GaAs based vertical cavity surface emitting laser (VCSEL) array and PIN photodiode array are flip-chip mounted on a standard microprocessor Land Grid Array (LGA) package substrate. The CMOS drivers and receivers on the transceiver chip and the optical components (VCSEL and Photodiode arrays) are electrically coupled using a short transmission line routed on the top surface of the package. VCSEL and photodiode arrays are optically coupled to on-package integrated polymer waveguide arrays with metallized 45° mirrors. The waveguides, which are terminated with multi-terminal (MT) fiber optic connectors, couple out/in high-speed optical signals to/from the chip. The CMOS transceiver chip fully integrates all analog optical circuits such as VCSEL drivers, transimpedance amplifiers and clock and data recovery (CDR) retiming circuit with a low jitter LC-PLL. Digital circuits for pseudorandom bit-pattern sequence generators (PRBS) and bit-error rate test (BERT) are fully integrated. 20Gb/s electrical and 18Gb/s optical eye diagrams for the transmitter were measured out of the package. A fully packaged transmitter and receiver including clock data recovery at 10Gb/s have also been measured.

  11. CMOS output buffer wave shaper

    NASA Technical Reports Server (NTRS)

    Albertson, L.; Whitaker, S.; Merrell, R.

    1990-01-01

    As the switching speeds and densities of Digital CMOS integrated circuits continue to increase, output switching noise becomes more of a problem. A design technique which aids in the reduction of switching noise is reported. The output driver stage is analyzed through the use of an equivalent RLC circuit. The results of the analysis are used in the design of an output driver stage. A test circuit based on these techniques is being submitted to MOSIS for fabrication.

  12. High responsivity CMOS imager pixel implemented in SOI technology

    NASA Technical Reports Server (NTRS)

    Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

    2000-01-01

    Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

  13. Cryogenic measurements of a digital pixel readout integrated circuit for LWIR

    NASA Astrophysics Data System (ADS)

    Shafique, Atia; Yazici, Melik; Kayahan, Huseyin; Ceylan, Omer; Gurbuz, Yasar

    2015-06-01

    This paper presents and discusses the cryogenic temperature (77K) measurement results of a digital readout integrated circuit (DROIC) for a 32x32 long wavelength infrared pixel sensor array designed in 90nm CMOS process. The chip achieves a signal-to-noise ratio (SNR) of 58dB with a charge handling capacity of 2.03Ge- at cryogenic temperature with 1.3mW of power dissipation. The performance of the readout is discussed in terms of power dissipation, charge handling capacity and SNR considering the fact that the process library models are not optimized for cryogenic temperature operation of the Metal-Oxide-Semiconductor (MOS) devices. These results provide an insight to foresee the design confrontations due to non-optimized device models for cryogenic temperatures particularly for short channel devices

  14. CMOS Detector Technology

    NASA Astrophysics Data System (ADS)

    Hoffman, Alan; Loose, Markus; Suntharalingam, Vyshnavi

    2005-01-01

    An entry level overview of state-of-the-art CMOS detector technology is presented. Operating principles and system architecture are explained in comparison to the well-established CCD technology, followed by a discussion of important benefits of modern CMOS-based detector arrays. A number of unique CMOS features including different shutter modes and scanning concepts are described. In addition, sub-field stitching is presented as a technique for producing very large imagers. After a brief introduction to the concept of monolithic CMOS sensors, hybrid detectors technology is introduced. A comparison of noise reduction methods for CMOS hybrids is presented. The final sections review CMOS fabrication processes for monolithic and vertically integrated image sensors.

  15. A scalable neural chip with synaptic electronics using CMOS integrated memristors.

    PubMed

    Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

    2013-09-27

    The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

  16. Low area 4-bit 5 MS/s flash-type digitizer for hybrid-pixel detectors - Design study in 180 nm and 40 nm CMOS

    NASA Astrophysics Data System (ADS)

    Otfinowski, Piotr; Grybos, Pawel

    2015-11-01

    We report on the design of a 4-bit flash ADC with dynamic offset correction dedicated to measurement systems based on a pixel architecture. The presented converter was manufactured in two CMOS technologies: widespread and economical 180 nm and modern 40 nm process. The designs are optimized for the lowest area occupancy resulting in chip areas of 160×55 μm2 and 35×25 μm2. The experimental results indicate integral nonlinearity of +0.35/-0.21 LSB and +0.28/-0.25 LSB and power consumption of 52 μW and 17 μW at 5 MS/s for the prototypes in 180 nm and 40 nm technologies respectively.

  17. A safety monitoring system for taxi based on CMOS imager

    NASA Astrophysics Data System (ADS)

    Liu, Zhi

    2005-01-01

    CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

  18. A CMOS high speed imaging system design based on FPGA

    NASA Astrophysics Data System (ADS)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  19. All-CMOS night vision viewer with integrated microdisplay

    NASA Astrophysics Data System (ADS)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  20. A low-power inverter-based CMOS level-crossing analog-to-digital converter for low-frequency biosignal sensing

    NASA Astrophysics Data System (ADS)

    Tanaka, Suiki; Niitsu, Kiichi; Nakazato, Kazuo

    2016-03-01

    Low-power analog-to-digital conversion is a key technique for power-limited biomedical applications such as power-limited continuous glucose monitoring. However, a conventional uniform-sampling analog-to-digital converter (ADC) is not suitable for nonuniform biosignals. A level-crossing ADC (LC-ADC) is a promising candidate for low-power biosignal processing because of its event-driven properties. The LC-ADC acquires data by level-crossing sampling. When an input signal crosses the threshold level, the LC-ADC samples the signal. The conventional LC-ADC employs a power-hungry comparator. In this paper, we present a low-power inverter-based LC-ADC. By adjusting the threshold level of the inverter, it can be used as a threshold-fixed window comparator. By using the inverter as an alternative to a comparator, power consumption can be markedly reduced. As a result, the total power consumption is successfully reduced by 90% of that of previous LC-ADC. The inverter-based LC-ADC was found to be very suitable for use in power-limited biomedical devices.

  1. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    NASA Astrophysics Data System (ADS)

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  2. Tests of commercial colour CMOS cameras for astronomical applications

    NASA Astrophysics Data System (ADS)

    Pokhvala, S. M.; Reshetnyk, V. M.; Zhilyaev, B. E.

    2013-12-01

    We present some results of testing commercial colour CMOS cameras for astronomical applications. Colour CMOS sensors allow to perform photometry in three filters simultaneously that gives a great advantage compared with monochrome CCD detectors. The Bayer BGR colour system realized in colour CMOS sensors is close to the astronomical Johnson BVR system. The basic camera characteristics: read noise (e^{-}/pix), thermal noise (e^{-}/pix/sec) and electronic gain (e^{-}/ADU) for the commercial digital camera Canon 5D MarkIII are presented. We give the same characteristics for the scientific high performance cooled CCD camera system ALTA E47. Comparing results for tests of Canon 5D MarkIII and CCD ALTA E47 show that present-day commercial colour CMOS cameras can seriously compete with the scientific CCD cameras in deep astronomical imaging.

  3. DFM in practice: results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90-nm FPGA chip

    NASA Astrophysics Data System (ADS)

    Yu, Chun-Chi; Shieh, Ming-Feng; Liu, Erick; Lin, Benjamin; Lin, Henry; Chacko, Manoj; Li, Xiaoyang; Lei, Wen-Kang; Ho, Jonathan; Wu, Xin

    2005-05-01

    At the sub 90nm nodes, resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential steps in the post-physical verification 'Mask Synthesis' process and a key component of design for manufacturing (DFM). Several studies have been conducted and the results have been published on the implication and application of the different types of RETs on mask printability and costs. More specifically, double-exposure-based, dark-field, alternating PSM (Alt-PSM) technology has received lot of attention with respect to the mask manufacturing challenges and its implementation into a production flow, despite its yield and critical dimension (CD) control superiority. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a matured, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. What follows is an in-depth review of the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

  4. Hematite nanoparticles larger than 90 nm show no sign of toxicity in terms of lactate dehydrogenase release, nitric oxide generation, apoptosis, and comet assay in murine alveolar macrophages and human lung epithelial cells.

    PubMed

    Freyria, Francesca Stefania; Bonelli, Barbara; Tomatis, Maura; Ghiazza, Mara; Gazzano, Elena; Ghigo, Dario; Garrone, Edoardo; Fubini, Bice

    2012-04-16

    Three hematite samples were synthesized by precipitation from a FeCl₃ solution under controlled pH and temperature conditions in different morphology and dimensions: (i) microsized (average diameter 1.2 μm); (ii) submicrosized (250 nm); and (iii) nanosized (90 nm). To gain insight into reactions potentially occurring in vivo at the particle-lung interface following dust inhalation, several physicochemical features relevant to pathogenicity were measured (free radical generation in cell-free tests, metal release, and antioxidant depletion), and cellular toxicity assays on human lung epithelial cells (A549) and murine alveolar macrophages (MH-S) were carried out (LDH release, apoptosis detection, DNA damage, and nitric oxide synthesis). The decrease in particles size, from 1.2 μm to 90 nm, only caused a slight increase in structural defects (disorder of the hematite phase and the presence of surface ferrous ions) without enhancing surface reactivity or cellular responses in the concentration range between 20 and 100 μg cm⁻².

  5. Hematite nanoparticles larger than 90 nm show no sign of toxicity in terms of lactate dehydrogenase release, nitric oxide generation, apoptosis, and comet assay in murine alveolar macrophages and human lung epithelial cells.

    PubMed

    Freyria, Francesca Stefania; Bonelli, Barbara; Tomatis, Maura; Ghiazza, Mara; Gazzano, Elena; Ghigo, Dario; Garrone, Edoardo; Fubini, Bice

    2012-04-16

    Three hematite samples were synthesized by precipitation from a FeCl₃ solution under controlled pH and temperature conditions in different morphology and dimensions: (i) microsized (average diameter 1.2 μm); (ii) submicrosized (250 nm); and (iii) nanosized (90 nm). To gain insight into reactions potentially occurring in vivo at the particle-lung interface following dust inhalation, several physicochemical features relevant to pathogenicity were measured (free radical generation in cell-free tests, metal release, and antioxidant depletion), and cellular toxicity assays on human lung epithelial cells (A549) and murine alveolar macrophages (MH-S) were carried out (LDH release, apoptosis detection, DNA damage, and nitric oxide synthesis). The decrease in particles size, from 1.2 μm to 90 nm, only caused a slight increase in structural defects (disorder of the hematite phase and the presence of surface ferrous ions) without enhancing surface reactivity or cellular responses in the concentration range between 20 and 100 μg cm⁻². PMID:22324577

  6. A low voltage CMOS low drop-out voltage regulator

    NASA Astrophysics Data System (ADS)

    Bakr, Salma Ali; Abbasi, Tanvir Ahmad; Abbasi, Mohammas Suhaib; Aldessouky, Mohamed Samir; Abbasi, Mohammad Usaid

    2009-05-01

    A low voltage implementation of a CMOS Low Drop-Out voltage regulator (LDO) is presented. The requirement of low voltage devices is crucial for portable devices that require extensive computations in a low power environment. The LDO is implemented in 90nm generic CMOS technology. It generates a fixed 0.8V from a 2.5V supply which on discharging goes to 1V. The buffer stage used is unity gain configured unbuffered OpAmp with rail-to-rail swing input stage. The simulation result shows that the implemented circuit provides load regulation of 0.004%/mA and line regulation of -11.09mV/V. The LDO provides full load transient response with a settling time of 5.2μs. Further, the dropout voltage is 200mV and the quiescent current through the pass transistor (Iload=0) is 20μA. The total power consumption of this LDO (excluding bandgap reference) is only 80μW.

  7. A PFM based digital pixel with off-pixel residue measurement for 15μm pitch MWIR FPAs

    NASA Astrophysics Data System (ADS)

    Abbasi, Shahbaz; Shafique, Atia; Galioglu, Arman; Ceylan, Omer; Yazici, Melik; Gurbuz, Yasar

    2016-05-01

    Digital pixels based on pulse frequency modulation (PFM) employ counting techniques to achieve very high charge handling capability compared to their analog counterparts. Moreover, extended counting methods making use of leftover charge (residue) on the integration capacitor help improve the noise performance of these pixels. However, medium wave infrared (MWIR) focal plane arrays (FPAs) having smaller pixel pitch are constrained in terms of pixel area which makes it difficult to add extended counting circuitry to the pixel. Thus, this paper investigates the performance of digital pixels employing off-pixel residue measurement. A circuit prototype of such a pixel has been designed for 15μm pixel pitch and fabricated in 90nm CMOS. The prototype is composed of a pixel front-end based on a PFM loop. The frontend is a modified version of conventional design providing a means for buffering the signal that needs to be converted to a digital value by an off-pixel ADC. The pixel has an integration phase and a residue measurement phase. Measured integration performance of the pixel has been reported in this paper for various detector currents and integration times.

  8. Integrated imaging sensor systems with CMOS active pixel sensor technology

    NASA Technical Reports Server (NTRS)

    Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

    2002-01-01

    This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

  9. A fully digital readout employing extended counting method to achieve very low quantization noise

    NASA Astrophysics Data System (ADS)

    Kayahan, Huseyin; Ceylan, Ömer; Yazici, Melik; Gurbuz, Yasar

    2013-06-01

    This paper presents a digital ROIC for staring type arrays with extending counting method to realize very low quantization noise while achieving a very high charge handling capacity. Current state of the art has shown that digital readouts with pulse frequency method can achieve charge handling capacities higher than 3Ge- with quantization noise higher than 1000e-. Even if the integration capacitance is reduced, it cannot be lower than 1-3 fF due to the parasitic capacitance of the comparator. For achieving a very low quantization noise of 200 electrons in a power efficient way, a new method based on measuring the time to measure the remaining charge on the integration capacitor is proposed. With this approach SNR of low flux pixels are significantly increased while large flux pixels can store electrons as high as 2.33Ge-. A prototype array of 32x32 pixels with 30μm pitch is implemented in 90nm CMOS process technology for verification. Simulation results are given for complete readout.

  10. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    NASA Astrophysics Data System (ADS)

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  11. On noise in time-delay integration CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Levski, Deyan; Choubey, Bhaskar

    2016-05-01

    Time delay integration sensors are of increasing interest in CMOS processes owing to their low cost, power and ability to integrate with other circuit readout blocks. This paper presents an analysis of the noise contributors in current day CMOS Time-Delay-Integration image sensors with various readout architectures. An analysis of charge versus voltage domain readout modes is presented, followed by a noise classification of the existing Analog Accumulator Readout (AAR) and Digital Accumulator Readout (DAR) schemes for TDI imaging. The analysis and classification of existing readout schemes include, pipelined charge transfer, buffered direct injection, voltage as well as current-mode analog accumulators and all-digital accumulator techniques. Time-Delay-Integration imaging modes in CMOS processes typically use an N-number of readout steps, equivalent to the number of TDI pixel stages. In CMOS TDI sensors, where voltage domain readout is used, the requirements over speed and noise of the ADC readout chain are increased due to accumulation of the dominant voltage readout and ADC noise with every stage N. Until this day, the latter is the primary reason for a leap-back of CMOS TDI sensors as compared to their CCD counterparts. Moreover, most commercial CMOS TDI implementations are still based on a charge-domain readout, mimicking a CCD-like operation mode. Thus, having a good understanding of each noise contributor in the signal chain, as well as its magnitude in different readout architectures, is vital for the design of future generation low-noise CMOS TDI image sensors based on a voltage domain readout. This paper gives a quantitative classification of all major noise sources for all popular implementations in the literature.

  12. On noise in time-delay integration CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Levski, Deyan; Choubey, Bhaskar

    2016-05-01

    Time delay integration sensors are of increasing interest in CMOS processes owing to their low cost, power and ability to integrate with other circuit readout blocks. This paper presents an analysis of the noise contributors in current day CMOS Time-Delay-Integration image sensors with various readout architectures. An analysis of charge versus voltage domain readout modes is presented, followed by a noise classification of the existing Analog Accumulator Readout (AAR) and Digital Accumulator Readout (DAR) schemes for TDI imaging. The analysis and classification of existing readout schemes include, pipelined charge transfer, buffered direct injection, voltage as well as current-mode analog accumulators and all-digital accumulator techniques. Time-Delay-Integration imaging modes in CMOS processes typically use an N-number of readout steps, equivalent to the number of TDI pixel stages. In CMOS TDI sensors, where voltage domain readout is used, the requirements over speed and noise of the ADC readout chain are increased due to accumulation of the dominant voltage readout and ADC noise with every stage N. Until this day, the latter is the primary reason for a leap-back of CMOS TDI sensors as compared to their CCD counterparts. Moreover, most commercial CMOS TDI implementations are still based on a charge-domain readout, mimicking a CCD-like operation mode. Thus, having a good understanding of each noise contributor in the signal chain, as well as its magnitude in different readout architectures, is vital for the design of future generation low-noise CMOS TDI image sensors based on a voltage domain readout. This paper gives a quantitative classification of all major noise sources for all popular implementations in the literature.

  13. Statistical circuit design for yield improvement in CMOS circuits

    NASA Technical Reports Server (NTRS)

    Kamath, H. J.; Purviance, J. E.; Whitaker, S. R.

    1990-01-01

    This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

  14. A CMOS humidity sensor for passive RFID sensing applications.

    PubMed

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  15. CMOS Monolithic Active Pixel Sensors (MAPS): Developments and future outlook

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; Fant, A.; Gasiorek, P.; Esbrand, C.; Griffiths, J. A.; Metaxas, M. G.; Royle, G. J.; Speller, R.; Venanzi, C.; van der Stelt, P. F.; Verheij, H.; Li, G.; Theodoridis, S.; Georgiou, H.; Cavouras, D.; Hall, G.; Noy, M.; Jones, J.; Leaver, J.; Machin, D.; Greenwood, S.; Khaleeq, M.; Schulerud, H.; Østby, J. M.; Triantis, F.; Asimidis, A.; Bolanakis, D.; Manthos, N.; Longo, R.; Bergamaschi, A.

    2007-12-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end applications, for example web-cams, and is slowly pervading the high-end applications, for example in prosumer digital cameras. Higher specifications are required for scientific applications: very low noise, high speed, high dynamic range, large format and radiation hardness are some of these requirements. This paper will present a brief overview of the CMOS Image Sensor technology and of the requirements for scientific applications. As an example, a sensor for X-ray imaging will be presented. This sensor was developed within a European FP6 Consortium, intelligent imaging sensors (I-ImaS).

  16. A CMOS humidity sensor for passive RFID sensing applications.

    PubMed

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-05-16

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 µW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs.

  17. A CMOS Humidity Sensor for Passive RFID Sensing Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Zhang, Chaolong; Feng, Wei

    2014-01-01

    This paper presents a low-cost low-power CMOS humidity sensor for passive RFID sensing applications. The humidity sensing element is implemented in standard CMOS technology without any further post-processing, which results in low fabrication costs. The interface of this humidity sensor employs a PLL-based architecture transferring sensor signal processing from the voltage domain to the frequency domain. Therefore this architecture allows the use of a fully digital circuit, which can operate on ultra-low supply voltage and thus achieves low-power consumption. The proposed humidity sensor has been fabricated in the TSMC 0.18 μm CMOS process. The measurements show this humidity sensor exhibits excellent linearity and stability within the relative humidity range. The sensor interface circuit consumes only 1.05 μW at 0.5 V supply voltage and reduces it at least by an order of magnitude compared to previous designs. PMID:24841250

  18. A new digital readout integrated circuit (DROIC) with pixel parallel A/D conversion with reduced quantization noise

    NASA Astrophysics Data System (ADS)

    Kayahan, Huseyin; Ceylan, Ömer; Yazici, Melik; Gurbuz, Yasar

    2014-06-01

    This paper presents a digital ROIC for staring type arrays with extending counting method to realize very low quantization noise while achieving a very high charge handling capacity. Current state of the art has shown that digital readouts with pulse frequency method can achieve charge handling capacities higher than 3Ge- with quantization noise higher than 1000e-. Even if the integration capacitance is reduced, it cannot be lower than 1-3 fF due to the parasitic capacitance of the comparator. For achieving a very low quantization noise of 161 electrons in a power efficient way, a new method based on measuring the time to measure the remaining charge on the integration capacitor is proposed. With this approach SNR of low flux pixels are significantly increased while large flux pixels can store electrons as high as 2.33Ge-. A prototype array of 32×32 pixels with 30μm pitch is implemented in 90nm CMOS process technology for verification. Measurement results are given for complete readout.

  19. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    PubMed Central

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  20. Regenerative switching CMOS system

    DOEpatents

    Welch, James D.

    1998-01-01

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

  1. Regenerative switching CMOS system

    DOEpatents

    Welch, J.D.

    1998-06-02

    Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

  2. Current-mode CMOS hybrid image sensor

    NASA Astrophysics Data System (ADS)

    Benyhesan, Mohammad Kassim

    Digital imaging is growing rapidly making Complimentary Metal-Oxide-Semi conductor (CMOS) image sensor-based cameras indispensable in many modern life devices like cell phones, surveillance devices, personal computers, and tablets. For various purposes wireless portable image systems are widely deployed in many indoor and outdoor places such as hospitals, urban areas, streets, highways, forests, mountains, and towers. However, the increased demand on high-resolution image sensors and improved processing features is expected to increase the power consumption of the CMOS sensor-based camera systems. Increased power consumption translates into a reduced battery life-time. The increased power consumption might not be a problem if there is access to a nearby charging station. On the other hand, the problem arises if the image sensor is located in widely spread areas, unfavorable to human intervention, and difficult to reach. Given the limitation of energy sources available for wireless CMOS image sensor, an energy harvesting technique presents a viable solution to extend the sensor life-time. Energy can be harvested from the sun light or the artificial light surrounding the sensor itself. In this thesis, we propose a current-mode CMOS hybrid image sensor capable of energy harvesting and image capture. The proposed sensor is based on a hybrid pixel that can be programmed to perform the task of an image sensor and the task of a solar cell to harvest energy. The basic idea is to design a pixel that can be configured to exploit its internal photodiode to perform two functions: image sensing and energy harvesting. As a proof of concept a 40 x 40 array of hybrid pixels has been designed and fabricated in a standard 0.5 microm CMOS process. Measurement results show that up to 39 microW of power can be harvested from the array under 130 Klux condition with an energy efficiency of 220 nJ /pixel /frame. The proposed image sensor is a current-mode image sensor which has several

  3. High gain CMOS image sensor design and fabrication on SOI and bulk technology

    NASA Astrophysics Data System (ADS)

    Zhang, Weiquan

    2000-12-01

    The CMOS imager is now competing with the CCD imager, which still dominates the electronic imaging market. By taking advantage of the mature CMOS technology, the CMOS imager can integrate AID converters, digital signal processing (DSP) and timing control circuits on the same chip. This low cost and high-density integration solution to the image capture is the strong driving force in industry. Silicon on insulator (SOI) is considered as the coming mainstream technology. It challenges the current bulk CMOS technology because of its reduced power consumption, high speed, radiation hardness etc. Moving the CMOS imager from the bulk to the SOI substrate will benefit from these intrinsic advantages. In addition, the blooming and the cross-talk between the pixels of the sensor array can be ideally eliminated, unlike those on the bulk technology. Though there are many advantages to integrate CMOS imager on SOI, the problem is that the top silicon film is very thin, such as 2000Å. Many photons can just pass through this layer without being absorbed. A good photo-detector on SOI is critical to integrate SOI CMOS imagers. In this thesis, several methods to make photo-detectors on SOI substrate are investigated. A floating gate MOSFET on SOI substrate, operating in its lateral bipolar mode, is photon sensitive. One step further, the SOI MOSFET gate and body can be tied together. The positive feedback between the body and gate enables this device have a high responsivity. A similar device can be found on the bulk CMOS technology: the gate-well tied PMOSFET. A 32 x 32 CMOS imager is designed and characterized using such a device as the light-sensing element. I also proposed the idea of building hybrid active pixels on SOI substrate. Such devices are fabricated and characterized. The work here represents my contribution on the CMOS imager, especially moving the CMOS imager onto the SOI substrate.

  4. Design of low-power hybrid digital pulse width modulator with piecewise calibration scheme

    NASA Astrophysics Data System (ADS)

    Zhen, Shaowei; Hou, Sijian; Gan, Wubing; Chen, Jingbo; Luo, Ping; Zhang, Bo

    2015-12-01

    A low-power hybrid digital pulse width modulator (DPWM) is proposed in the paper. Owing to the piecewise calibration scheme, the delay time of delay line is locked to target frequency. The delay line consists of two piecewise lines with different control codes. The delay time of each cell in one sub-delay-line is longer than the last significant bit (LSB) of DPWM, while the delay time of each cell in the other sub-delay-line is shorter than LSB. Optimum linearity is realised with minimum standard cells. Simulation results show that the differential nonlinearity and integral nonlinearity are improved from 5.1 to 0.4 and from 5 to 1.3, respectively. The DPWM is fully synthesised and fabricated in a 90-nm CMOS process. The proposed DPWM occupies a silicon area of 0.01 mm2, with 31.5 μw core power consumption. Experimental results are shown to demonstrate the 2-MHz, 10-bit resolution implementation. Pulse width histogram is firstly introduced to characterise the linearity of the DPWM.

  5. Attenuation of single event induced pulses in CMOS combinational logic

    SciTech Connect

    Baze, M.P.; Buchner, S.P.

    1997-12-01

    Results are presented of a study of SEU generated transient pulse attenuation in combinational logic structures built using common digital CMOS design practices. SPICE circuit analysis, heavy ion tests, and pulsed, focused laser simulations were used to examine the response characteristics of transient pulse behavior in long logic strings. Results show that while there is an observable effect, it cannot be generally assumed that attenuation will significantly reduce observed circuit bit error rates.

  6. Reconfigurable RF CMOS Circuit for Cognitive Radio

    NASA Astrophysics Data System (ADS)

    Masu, Kazuya; Okada, Kenichi

    Cognitive radio and/or SDR (Software Defined Radio) inherently requires multi-band and multi standard wireless circuit. The circuit is implemented based on Si CMOS technology. In this article, the recent progress of Si RF CMOS is described and the reconfigurable RF CMOS circuit which was proposed by the authors is introduced. At the present and in the future, several kind of Si CMOS technology can be used for RF CMOS circuit implementation. The realistic RF CMOS circuit implementation toward cognitive and/or SDR is discussed.

  7. A high speed CMOS A/D converter

    NASA Technical Reports Server (NTRS)

    Wiseman, Don R.; Whitaker, Sterling R.

    1992-01-01

    This paper presents a high speed analog-to-digital (A/D) converter. The converter is a 7 bit flash converter with one half LSB accuracy. Typical parts will function at approximately 200 MHz. The converter uses a novel comparator circuit that is shown to out perform more traditional comparators, and thus increases the speed of the converter. The comparator is a clocked, precharged circuit that offers very fast operation with a minimal offset voltage (2 mv). The converter was designed using a standard 1 micron digital CMOS process and is 2,244 microns by 3,972 microns.

  8. Research-grade CMOS image sensors for remote sensing applications

    NASA Astrophysics Data System (ADS)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

    2004-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

  9. Research-grade CMOS image sensors for demanding space applications

    NASA Astrophysics Data System (ADS)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2004-06-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  10. Light microscopy digital imaging.

    PubMed

    Joubert, James; Sharma, Deepak

    2011-10-01

    This unit presents an overview of digital imaging hardware used in light microscopy. CMOS, CCD, and EMCCDs are the primary sensors used. The strengths and weaknesses of each define the primary applications for these sensors. Sensor architecture and formats are also reviewed. Color camera design strategies and sensor window cleaning are also described in the unit.

  11. Design and characterization of high precision in-pixel discriminators for rolling shutter CMOS pixel sensors with full CMOS capability

    NASA Astrophysics Data System (ADS)

    Fu, Y.; Hu-Guo, C.; Dorokhov, A.; Pham, H.; Hu, Y.

    2013-07-01

    In order to exploit the ability to integrate a charge collecting electrode with analog and digital processing circuitry down to the pixel level, a new type of CMOS pixel sensors with full CMOS capability is presented in this paper. The pixel array is read out based on a column-parallel read-out architecture, where each pixel incorporates a diode, a preamplifier with a double sampling circuitry and a discriminator to completely eliminate analog read-out bottlenecks. The sensor featuring a pixel array of 8 rows and 32 columns with a pixel pitch of 80 μm×16 μm was fabricated in a 0.18 μm CMOS process. The behavior of each pixel-level discriminator isolated from the diode and the preamplifier was studied. The experimental results indicate that all in-pixel discriminators which are fully operational can provide significant improvements in the read-out speed and the power consumption of CMOS pixel sensors.

  12. Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

    PubMed

    Kazior, Thomas E

    2014-03-28

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  13. Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

    PubMed Central

    Kazior, Thomas E.

    2014-01-01

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  14. CMOS Integrated Carbon Nanotube Sensor

    SciTech Connect

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-05-23

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  15. Contact CMOS imaging of gaseous oxygen sensor array.

    PubMed

    Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-10-01

    We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3](2+)) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

  16. Contact CMOS imaging of gaseous oxygen sensor array

    PubMed Central

    Daivasagaya, Daisy S.; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C.; Chodavarapu, Vamsy P.; Bright, Frank V.

    2014-01-01

    We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3]2+) encapsulated within sol–gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors. PMID:24493909

  17. Fundamental performance differences between CMOS and CCD imagers: Part II

    NASA Astrophysics Data System (ADS)

    Janesick, James; Andrews, James; Tower, John; Grygon, Mark; Elliott, Tom; Cheng, John; Lesser, Michael; Pinter, Jeff

    2007-09-01

    A new class of CMOS imagers that compete with scientific CCDs is presented. The sensors are based on deep depletion backside illuminated technology to achieve high near infrared quantum efficiency and low pixel cross-talk. The imagers deliver very low read noise suitable for single photon counting - Fano-noise limited soft x-ray applications. Digital correlated double sampling signal processing necessary to achieve low read noise performance is analyzed and demonstrated for CMOS use. Detailed experimental data products generated by different pixel architectures (notably 3TPPD, 5TPPD and 6TPG designs) are presented including read noise, charge capacity, dynamic range, quantum efficiency, charge collection and transfer efficiency and dark current generation. Radiation damage data taken for the imagers is also reported.

  18. Smart CMOS image sensor for lightning detection and imaging.

    PubMed

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-03-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel frame-to-frame difference comparison with an adjustable threshold and on-chip digital processing allowing an efficient localization of a faint lightning pulse on the entire large format array at a frequency of 1 kHz. A CMOS prototype sensor with a 256×256 pixel array and a 60 μm pixel pitch has been fabricated using a 0.35 μm 2P 5M technology and tested to validate the selected detection approach.

  19. Development of CMOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  20. Multiband CMOS sensor simplify FPA design

    NASA Astrophysics Data System (ADS)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  1. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

    SciTech Connect

    Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

    2008-08-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

  2. Four channel CMOS codec filter circuit `SICOFIqq-4'

    NASA Astrophysics Data System (ADS)

    Tiefenbacher, M.; Caldera, P.; Dielacher, F.; Hauptmann, J.; Steiner, M.

    1994-08-01

    Cost reduction by integration of complex mixed analog-digital systems on a single chip and an excellent yield to area ratio is a major goal for IC design in the nineties. In this paper, a four-channel codec-filter chip for analog subscriber lines in ISDN-orientated networks is presented, giving an exceptional example for high level system implementation combined with parallel DSP integration and analog circuitry with high performance. The chip combines four analog frontends, digital signal processing realized by different approaches for a sophisticated filter concept in addition with test strategies including digital and analog BIST. The circuit is fabricated in a standard 1-mu CMOS technology, needs a single 5-V power supply, and can easily be programmed to world-wide different country specifications and applications.

  3. Evaluation of a CMOS image detector for low-cost and power medical x-ray imaging applications

    NASA Astrophysics Data System (ADS)

    Smith, Scott T.; Bednarek, Daniel R.; Wobschall, Darold C.; Jeong, Myoungki; Kim, Hyunkeun; Rudin, Stephen

    1999-05-01

    Recent developments in CMOS image detectors are changing the way digital imaging is performed for many applications. The replacement of charge coupled devices (CCDs), with CMOS detectors is a desirable paradigm shift that will depend on the ability to match the high performance characteristics of CCDs. Digital X-ray imaging applications (chest X-ray, mammography) would benefit greatly from this shift because CMOS detectors have the following inherent characteristics: (1) Low operating power (5 - 10 times lower than CCD/processing electronics). (2) Standard CMOS manufacturing process (CCD requires special manufacturing). (3) On-chip integration of analog/digital processing functions (difficult with CCD). (4) Low Cost (5 - 10 times lower cost than CCD). The achievement of both low cost and low power is highly desirable for portable applications as well as situations where large, expensive X-ray imaging machines are not feasible (small hospitals and clinics, emergency medical vehicles, remote sites). Achieving this goal using commercially available components would allow rapid development of such digital X-ray systems as compared with the development difficulties incurred through specialized direct detectors and systems. The focus of this paper is to evaluate a CMOS image detector for medical X-ray applications and to demonstrate the results obtained from a prototype CMOS digital X-ray camera. Results from the images collected from this optically-coupled camera are presented for a particular lens, X-ray conversion screen, and demagnification factor. Further, an overview of the overall power consumption and cost of a multi-sensor CMOS mosaic compared to its CCD counterpart are also reported.

  4. NV-CMOS HD camera for day/night imaging

    NASA Astrophysics Data System (ADS)

    Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

    2014-06-01

    SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE <90%), as well as projected low noise (<2h+) readout. Power consumption is minimized in the camera, which operates from a single 5V supply. The NVCMOS HD camera provides a substantial reduction in size, weight, and power (SWaP) , ideal for SWaP-constrained day/night imaging platforms such as UAVs, ground vehicles, fixed mount surveillance, and may be reconfigured for mobile soldier operations such as night vision goggles and weapon sights. In addition the camera with the NV-CMOS HD imager is suitable for high performance digital cinematography/broadcast systems, biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

  5. High-voltage CMOS detectors

    NASA Astrophysics Data System (ADS)

    Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

    2016-07-01

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented.

  6. Noise sources and noise suppression in CMOS imagers

    NASA Astrophysics Data System (ADS)

    Pain, Bedabrata; Cunningham, Thomas J.; Hancock, Bruce R.

    2004-01-01

    Mechanisms for noise coupling in CMOS imagers are complex, since unlike a CCD, a CMOS imager has to be considered as a full digital-system-on-a-chip, with a highly sensitive front-end. In this paper, we analyze the noise sources in a photodiode CMOS imager, and model their propagation through the signal chain to determine the nature and magnitude of noise coupling. We present methods for reduction of noise, and present measured data to show their viability. For temporal read noise reduction, we present pixel signal chain design techniques to achieve near 2 electrons read noise. We model the front-end reset noise both for conventional photodiode and CTIA type of pixels. For the suppression of reset noise, we present a column feedback-reset method to reduce reset noise below 6 electrons. For spatial noise reduction, we present the design of column signal chain that suppresses both spatial noise and power supply coupling noise. We conclude by identifying problems in low-noise design caused by dark current spatial distribution.

  7. Using CMOS image sensors to detect photons

    NASA Astrophysics Data System (ADS)

    Xu, Chenzhi; Tong, Xiaobo; Zhou, Xiang; Zheng, Xiaodong; Xu, Yunfei

    2010-05-01

    A research is carried out on the characteristics of CMOS (Complementary Metal-Oxide Semiconductor) image sensors. A CMOS image sensor is used to probe the fluorescence intensity of atoms or absorbed photons in order to measure the shape and atomicity density of Rb (Rubidium) cold-atom-cloud. A series of RGB data of images is obtained and the spectrum response curve of CMOS image sensor is deduced. After filtering out the noise of the pixel signals of CMOS image sensor, the number of photons received by every pixel of the CMOS image sensor is obtained. Compared with CCD camera, the CMOS image sensor has some advantages in measuring the properties of cold-atom-cloud,such as quick response, large sensory area, low cost, and so on.

  8. Fabrication of CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Malinovich, Yacov; Koltin, Ephie; Choen, David; Shkuri, Moshe; Ben-Simon, Meir

    1999-04-01

    In order to provide its customers with sub-micron CMOS fabrication solutions for imaging applications, Tower Semiconductor initiated a project to characterize the optical parameters of Tower's 0.5-micron process. A special characterization test chip was processed using the TS50 process. The results confirmed a high quality process for optical applications. Perhaps the most important result is the process' very low dark current, of 30-50 pA/cm2, using the entire window of process. This very low dark current characteristic was confirmed for a variety of pixel architectures. Additionally, we have succeeded to reduce and virtually eliminate the white spots on large sensor arrays. As a foundry Tower needs to support fabrication of many different imaging products. Therefore we have developed a fabrication methodology that is adjusted to the special needs of optical applications. In order to establish in-line process monitoring of the optical parameters, Tower places a scribe line optical test chip that enables wafer level measurements of the most important parameters, ensuring the optical quality and repeatability of the process. We have developed complementary capabilities like in house deposition of color filter and fabrication of very large are dice using sub-micron CMOS technologies. Shellcase and Tower are currently developing a new CMOS image sensor optical package.

  9. High-Voltage-Input Level Translator Using Standard CMOS

    NASA Technical Reports Server (NTRS)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  10. A CMOS analog front-end chip for amperometric electrochemical sensors

    NASA Astrophysics Data System (ADS)

    Zhichao, Li; Yuntao, Liu; Min, Chen; Jingbo, Xiao; Jie, Chen

    2015-07-01

    This paper reports a complimentary metal-oxide-semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter (Σ-Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. Project supported by the National Key Basic Research and Development Project (No. 2015CB352103).

  11. Nanosecond monolithic CMOS readout cell

    DOEpatents

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  12. CMOS foveal image sensor chip

    NASA Technical Reports Server (NTRS)

    Bandera, Cesar (Inventor); Scott, Peter (Inventor); Sridhar, Ramalingam (Inventor); Xia, Shu (Inventor)

    2002-01-01

    A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

  13. High-sensitivity chemiluminescence detection of cytokines using an antibody-immobilized CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Hong, Dong-Gu; Joung, Hyou-Arm; Kim, Sang-Hyo; Kim, Min-Gon

    2013-05-01

    In this study, we used a Complementary Metal Oxide Semiconductor (CMOS) image sensor with immobilizing antibodies on its surface to detect human cytokines, which are activators that mediate intercellular communication including expression and control of immune responses. The CMOS image sensor has many advantages over the Charge Couple Device, including lower power consumption, operation voltage, and cost. The photodiode, a unit pixel component in the CMOS image sensor, receives light from the detection area and generates digital image data. About a million pixels are embedded, and size of each pixel is 3 x 3 μm. The chemiluminescence reaction produces light from the chemical reaction of luminol and hydrogen peroxide. To detect cytokines, antibodies were immobilized on the surface of the CMOS image sensor, and a sandwich immunoassay using an HRP-labeled antibody was performed. An HRP-catalyzed chemiluminescence reaction was measured by each pixel of the CMOS image sensor. Pixels with stronger signals indicated higher cytokine concentrations; thus, we were able to measure human interleukin-5 (IL-5) at femtomolar concentrations.

  14. Accelerated life testing effects on CMOS microcircuit characteristics

    NASA Technical Reports Server (NTRS)

    1977-01-01

    Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

  15. Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

    PubMed

    Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

    2016-01-01

    In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices. PMID:27302586

  16. Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

    NASA Astrophysics Data System (ADS)

    Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

    2010-10-01

    Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

  17. Spectrometry with consumer-quality CMOS cameras.

    PubMed

    Scheeline, Alexander

    2015-01-01

    Many modern spectrometric instruments use diode arrays, charge-coupled arrays, or CMOS cameras for detection and measurement. As portable or point-of-use instruments are desirable, one would expect that instruments using the cameras in cellular telephones and tablet computers would be the basis of numerous instruments. However, no mass market for such devices has yet developed. The difficulties in using megapixel CMOS cameras for scientific measurements are discussed, and promising avenues for instrument development reviewed. Inexpensive alternatives to use of the built-in camera are also mentioned, as the long-term question is whether it is better to overcome the constraints of CMOS cameras or to bypass them.

  18. Nuclear magnetic resonance imaging with 90-nm resolution.

    PubMed

    Mamin, H J; Poggio, M; Degen, C L; Rugar, D

    2007-05-01

    Magnetic resonance imaging (MRI) is a powerful imaging technique that typically operates on the scale of millimetres to micrometres. Conventional MRI is based on the manipulation of nuclear spins with radio-frequency fields, and the subsequent detection of spins with induction-based techniques. An alternative approach, magnetic resonance force microscopy (MRFM), uses force detection to overcome the sensitivity limitations of conventional MRI. Here, we show that the two-dimensional imaging of nuclear spins can be extended to a spatial resolution better than 100 nm using MRFM. The imaging of 19F nuclei in a patterned CaF(2) test object was enabled by a detection sensitivity of roughly 1,200 nuclear spins at a temperature of 600 mK. To achieve this sensitivity, we developed high-moment magnetic tips that produced field gradients up to 1.4 x 10(6) T m(-1), and implemented a measurement protocol based on force-gradient detection of naturally occurring spin fluctuations. The resulting detection volume was less than 650 zeptolitres. This is 60,000 times smaller than the previous smallest volume for nuclear magnetic resonance microscopy, and demonstrates the feasibility of pushing MRI into the nanoscale regime.

  19. Readout circuit design of the retina-like CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Cao, Fengmei; Song, Shengyu; Bai, Tingzhu; Cao, Nan

    2015-02-01

    Readout circuit is designed for a special retina-like CMOS image sensor. To realize the pixels timing drive and readout of the sensor, the Altera's Cyclone II FPGA is used as a control chip. The voltage of the sensor is supported by a voltage chip initialized by SPI with AVR MCU system. The analog image signal outputted by the sensor is converted to digital image data by 12-bits A/D converter ADS807 and the digital data is memorized in the SRAM. Using the Camera-link image grabber, the data stored in SRAM is transformed to image shown on PC. Experimental results show the circuit works well on retina-like CMOS timing drive and image readout and images can be displayed properly on the PC.

  20. Integrated CMOS amplifier for ENG signal recording.

    PubMed

    Uranga, A; Navarro, X; Barniol, N

    2004-12-01

    The development and in vivo test of a fully integrated differential CMOS amplifier, implemented with standard 0.7-microm CMOS technology (one poly, two metals, self aligned twin-well CMOS process) intended to record extracellular neural signals is described. In order to minimize the flicker noise generated by the CMOS circuitry, a chopper technique has been chosen. The fabricated amplifier has a gain of 74 dB, a bandwidth of 3 kHz, an input noise of 6.6 nV/(Hz)0.5, a power dissipation of 1.3 mW, and the active area is 2.7 mm2. An ac coupling has been used to adapt the electrode to the amplifier circuitry for the in vivo testing. Compound muscle action potentials, motor unit action potentials, and compound nerve action potentials have been recorded in acute experiments with rats, in order to validate the amplifier. PMID:15605867

  1. A CMOS smart temperature and humidity sensor with combined readout.

    PubMed

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA. PMID:25230305

  2. A CMOS Smart Temperature and Humidity Sensor with Combined Readout

    PubMed Central

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-01-01

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 μA. PMID:25230305

  3. CMOS-TDI detector technology for reconnaissance application

    NASA Astrophysics Data System (ADS)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  4. A 50Mbit/Sec. CMOS Video Linestore System

    NASA Astrophysics Data System (ADS)

    Jeung, Yeun C.

    1988-10-01

    This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

  5. A CMOS Imager with Focal Plane Compression using Predictive Coding

    NASA Technical Reports Server (NTRS)

    Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

    2007-01-01

    This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

  6. A CMOS smart temperature and humidity sensor with combined readout.

    PubMed

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-09-16

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

  7. Precision of FLEET Velocimetry Using High-Speed CMOS Camera Systems

    NASA Technical Reports Server (NTRS)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 microseconds, precisions of 0.5 meters per second in air and 0.2 meters per second in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision HighSpeed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  8. Precision of FLEET Velocimetry Using High-speed CMOS Camera Systems

    NASA Technical Reports Server (NTRS)

    Peters, Christopher J.; Danehy, Paul M.; Bathel, Brett F.; Jiang, Naibo; Calvert, Nathan D.; Miles, Richard B.

    2015-01-01

    Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 micro sec, precisions of 0.5 m/s in air and 0.2 m/s in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision High Speed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

  9. Fundamental study on identification of CMOS cameras

    NASA Astrophysics Data System (ADS)

    Kurosawa, Kenji; Saitoh, Naoki

    2003-08-01

    In this study, we discussed individual camera identification of CMOS cameras, because CMOS (complementary-metal-oxide-semiconductor) imaging detectors have begun to make their move into the CCD (charge-coupled-device) fields for recent years. It can be identified whether or not the given images have been taken with the given CMOS camera by detecting the imager's intrinsic unique fixed pattern noise (FPN) just like the individual CCD camera identification method proposed by the authors. Both dark and bright pictures taken with the CMOS cameras can be identified by the method, because not only dark current in the photo detectors but also MOS-FET amplifiers incorporated in each pixel may produce pixel-to-pixel nonuniformity in sensitivity. Each pixel in CMOS detectors has the amplifier, which degrades image quality of bright images due to the nonuniformity of the amplifier gain. Two CMOS cameras were evaluated in our experiments. They were WebCamGoPlus (Creative), and EOS D30 (Canon). WebCamGoPlus is a low-priced web camera, whereas EOS D30 is for professional use. Image of a white plate were recorded with the cameras under the plate's luminance condition of 0cd/m2 and 150cd/m2. The recorded images were multiply integrated to reduce the random noise component. From the images of both cameras, characteristic dots patterns were observed. Some bright dots were observed in the dark images, whereas some dark dots were in the bright images. The results show that the camera identification method is also effective for CMOS cameras.

  10. New package for CMOS sensors

    NASA Astrophysics Data System (ADS)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  11. Future of nano CMOS technology

    NASA Astrophysics Data System (ADS)

    Iwai, Hiroshi

    2015-10-01

    Although Si MOS devices have dominated the integrated circuit applications over the four decades, it has been anticipated that the development of CMOS would reach its limits after the next decade because of the difficulties in the technologies for further downscaling and also because of some fundamental limits of MOSFETs. However, there have been no promising candidates yet, which can replace Si MOSFETs with better performance with low cost. Thus, for the moment, it seems that we have to stick to the Si MOSFET devices until their end. The downsizing is limited by the increase of off-leakage current between source and drain. In order to suppress the off-leakage current, multi-gate structures (FinFET, Tri-gate, and Si-nanowire MOSFETs) are replacing conventional planar MOSFETs, and continuous innovation of high-k/metal gate technologies has enabled EOT scaling down to 0.9 nm in production. However, it was found that the multi-gate structures have a future big problem of significant conduction reduction with decrease in fin width. Also it is not easy to further decrease EOT because of the mobility and reliability degradation. Furthermore, the development of EUV (Extremely Ultra-Violet) lithography, which is supposed to be essential for sub-10 nm lithography, delays significantly because of insufficient illumination intensity for production. Thus, it is now expected that the reduction rate of the gate length, which has a strong influence on the off-leakage current, will become slower in near future.

  12. A low-power asynchronous ECG acquisition system in CMOS technology.

    PubMed

    Hwang, Sungkil; Trakimas, Michael; Sonkusale, Sameer

    2010-01-01

    An asynchronous electrocardiogram (ECG) acquisition system is presented for wearable ambulatory monitoring. The proposed system consists of a low noise front-end amplifier (AFE) with tunable bandwidth, an asynchronous analog-to-digital converter (ADC), and digital signal processing (DSP). Data compression is achieved by the inherent signal dependent sampling rate of the asynchronous architecture. This makes the system attractive for compact wearable ECG monitoring applications. The AFE and ADC were fabricated in a 0.18 microm CMOS technology and consume a total of 79 microW. Measured results demonstrating ECG monitoring are presented. PMID:21096052

  13. A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Ye, Han; Quanliang, Li; Cong, Shi; Nanjian, Wu

    2013-08-01

    This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm2 was implemented in a 0.13 μm CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

  14. An image identification system of seal with fingerprint based on CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Xue, Xu-cheng; Zhang, Shu-yan; Guo, Yong-fei

    2006-01-01

    CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analog signal conditioning circuits, A/D converter and digital processing functions. Furthermore, CMOS sensors are the best choices for low-cost imaging systems. An image identification system based on CMOS image sensor is used to identify the seal images that include fingerprint, and then determine whether the seal is fake or not. The system consists of a color CMOS image sensor (OV2610), a buffer memory, a CPLD, a MCU (P89C61X2), a USB2.0 interface chip (ISP1581) and a personal computer. The CPLD implement the logic and timing of the system. The MCU and the USB2.0 interface chip deal with the communications between the images acquisition system and PC. Thus PC can send some parameters and commands to the images acquisition system and also read image data from it. The identification of the images of seal is processed by the PC. The structure and scheme of the system are discussed in detail in this paper. Several test images of seal taken by the system are also provided in the paper.

  15. CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

    PubMed

    Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

    2011-04-01

    In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

  16. High-speed binary CMOS image sensor using a high-responsivity MOSFET-type photodetector

    NASA Astrophysics Data System (ADS)

    Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Choi, Pyung; Shin, Jang-Kyoo

    2015-03-01

    In this paper, a complementary metal oxide semiconductor (CMOS) binary image sensor based on a gate/body-tied (GBT) MOSFET-type photodetector is proposed. The proposed CMOS binary image sensor was simulated and measured using a standard CMOS 0.18-μm process. The GBT MOSFET-type photodetector is composed of a floating gate (n+- polysilicon) tied to the body (n-well) of the p-type MOSFET. The size of the active pixel sensor (APS) using GBT photodetector is smaller than that of APS using the photodiode. This means that the resolution of the image can be increased. The high-gain GBT photodetector has a higher photosensitivity compared to the p-n junction photodiode that is used in a conventional APS. Because GBT has a high sensitivity, fast operation of the binary processing is possible. A CMOS image sensor with the binary processing can be designed with simple circuits composed of a comparator and a Dflip- flop while a complex analog to digital converter (ADC) is not required. In addition, the binary image sensor has low power consumption and high speed operation with the ability to switch back and forth between a binary mode and an analog mode.

  17. On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

    NASA Technical Reports Server (NTRS)

    Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

    2008-01-01

    The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

  18. High performance rf front end circuits using SiGe:C BiCMOS+copper technologies

    NASA Astrophysics Data System (ADS)

    Watanabe, Glenn; Ortiz, Jeff; Holbrook, Rick

    2004-03-01

    Using a first generation standard silicon germanium (SiGe):C HBT BiCMOS process, a personal digital cellular (PDC) LNA noice factor (NF) of 1.0 dB at 850 MHz and 1.2 dB at 1.5 GHz has been achieved. The LNA NF can be further reduced by using the second generation enhanced SiGe:C HBT BiCMOS process. The mixer performance is equally impressive. The NF of the downconversion mixer at 1.5 GHz is just 6.2 dB with a conversion gain of 12 dB. The mixer IIP3 is +9.9 dBm at a current drain of 5.6 mA. Design techniques are given on how to achieve high linearity with minimal current drain resulting in a 881 MHz LNA with an IIP3 of +12.4 dBm with just 6 mA of current and a NF of 1.4 dB using the first generation SiGe:C HBT BiCMOS process. The second generation enhanced SiGe:C HBT BiCMOS process should further reduce the noise figure.

  19. CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

    PubMed

    Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

    2011-04-01

    In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply. PMID:23851206

  20. Overview of CMOS process and design options for image sensor dedicated to space applications

    NASA Astrophysics Data System (ADS)

    Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

    2005-10-01

    With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

  1. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    NASA Technical Reports Server (NTRS)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  2. Color calibration of a CMOS digital camera for mobile imaging

    NASA Astrophysics Data System (ADS)

    Eliasson, Henrik

    2010-01-01

    As white balance algorithms employed in mobile phone cameras become increasingly sophisticated by using, e.g., elaborate white-point estimation methods, a proper color calibration is necessary. Without such a calibration, the estimation of the light source for a given situation may go wrong, giving rise to large color errors. At the same time, the demands for efficiency in the production environment require the calibration to be as simple as possible. Thus it is important to find the correct balance between image quality and production efficiency requirements. The purpose of this work is to investigate camera color variations using a simple model where the sensor and IR filter are specified in detail. As input to the model, spectral data of the 24-color Macbeth Colorchecker was used. This data was combined with the spectral irradiance of mainly three different light sources: CIE A, D65 and F11. The sensor variations were determined from a very large population from which 6 corner samples were picked out for further analysis. Furthermore, a set of 100 IR filters were picked out and measured. The resulting images generated by the model were then analyzed in the CIELAB space and color errors were calculated using the ΔE94 metric. The results of the analysis show that the maximum deviations from the typical values are small enough to suggest that a white balance calibration is sufficient. Furthermore, it is also demonstrated that the color temperature dependence is small enough to justify the use of only one light source in a production environment.

  3. Characterization and reliability of CMOS microstructures

    NASA Astrophysics Data System (ADS)

    Fedder, Gary K.; Blanton, Ronald D. S.

    1999-08-01

    This paper provides an overview of high-aspect-ratio CMOS micromachining, focusing on materials characterization, reliability, and fault analysis. Composite microstrutural beam widths and gaps down to 1.2 micrometers are etched out of conventional CMOS dielectric, aluminum, and gate-polysilicon thin films using post-CMOS dry etching for both structural sidewall definition and for release from the substrate. Differences in stress between the multiple metal and dielectric layers cause vertical stress gradients and curl, while misalignment between layers causes lateral stress gradients and curl. Cracking is induced in a resonant fatigue structures at 620 MPa of repetitive stress after over 50 million cycles. Beams have withstood over 1.3 billion cycles at 124 MPa stress levels induced by electrostatic actuation. Failures due to process defects are classified according to the geometrical features of the defective structures. Relative probability of occurrence of each defect type is extracted from the process simulation results.

  4. Nanopore-CMOS Interfaces for DNA Sequencing.

    PubMed

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-01-01

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces. PMID:27509529

  5. Nanopore-CMOS Interfaces for DNA Sequencing

    PubMed Central

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-01-01

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces. PMID:27509529

  6. High-temperature Complementary Metal Oxide Semiconductors (CMOS)

    NASA Technical Reports Server (NTRS)

    Mcbrayer, J. D.

    1981-01-01

    The results of an investigation into the possibility of using complementary metal oxide semiconductor (CMOS) technology for high temperature electronics are presented. A CMOS test chip was specifically developed as the test bed. This test chip incorporates CMOS transistors that have no gate protection diodes; these diodes are the major cause of leakage in commercial devices.

  7. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    NASA Technical Reports Server (NTRS)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  8. End-of-fabrication CMOS process monitor

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hannaman, D. J.; Lieneweg, U.; Lin, Y.-S.; Sayah, H. R.

    1990-01-01

    A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

  9. Optical addressing technique for a CMOS RAM

    NASA Technical Reports Server (NTRS)

    Wu, W. H.; Bergman, L. A.; Allen, R. A.; Johnston, A. R.

    1988-01-01

    Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull down' OGC, which has been characterized experimentally. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

  10. Ultra low power CMOS technology

    NASA Technical Reports Server (NTRS)

    Burr, J.; Peterson, A.

    1991-01-01

    This paper discusses the motivation, opportunities, and problems associated with implementing digital logic at very low voltages, including the challenge of making use of the available real estate in 3D multichip modules, energy requirements of very large neural networks, energy optimization metrics and their impact on system design, modeling problems, circuit design constraints, possible fabrication process modifications to improve performance, and barriers to practical implementation.

  11. A CMOS detection chip for amperometric sensors with chopper stabilized incremental ΔΣ ADC

    NASA Astrophysics Data System (ADS)

    Min, Chen; Yuntao, Liu; Jingbo, Xiao; Jie, Chen

    2016-06-01

    This paper presents a low noise complimentary metal-oxide-semiconductor (CMOS) detection chip for amperometric electrochemical sensors. In order to effectively remove the input offset of the cascaded integrators and the low frequency noise in the modulator, a novel offset cancellation chopping scheme was proposed in the Incremental ΔΣ analog to digital converter (IADC). A novel low power potentiostat was employed in this chip to provide the biasing voltage for the sensor while mirroring the sensor current out for detection. The chip communicates with FPGA through standard built in I2C interface and SPI bus. Fabricated in 0.18-μm CMOS process, this chip detects current signal with high accuracy and high linearity. A prototype microsystem was produced to verify the detection chip performance with current input as well as micro-sensors. Project supported by the State Key Development Program for Basic Research of China (No. 2015CB352100).

  12. A CMOS detection chip for amperometric sensors with chopper stabilized incremental ΔΣ ADC

    NASA Astrophysics Data System (ADS)

    Min, Chen; Yuntao, Liu; Jingbo, Xiao; Jie, Chen

    2016-06-01

    This paper presents a low noise complimentary metal–oxide-semiconductor (CMOS) detection chip for amperometric electrochemical sensors. In order to effectively remove the input offset of the cascaded integrators and the low frequency noise in the modulator, a novel offset cancellation chopping scheme was proposed in the Incremental ΔΣ analog to digital converter (IADC). A novel low power potentiostat was employed in this chip to provide the biasing voltage for the sensor while mirroring the sensor current out for detection. The chip communicates with FPGA through standard built in I2C interface and SPI bus. Fabricated in 0.18-μm CMOS process, this chip detects current signal with high accuracy and high linearity. A prototype microsystem was produced to verify the detection chip performance with current input as well as micro-sensors. Project supported by the State Key Development Program for Basic Research of China (No. 2015CB352100).

  13. Radiation Tolerance of 65nm CMOS Transistors

    DOE PAGES

    Krohn, M.; Bentele, B.; Christian, D. C.; Cumalat, J. P.; Deptuch, G.; Fahim, F.; Hoff, J.; Shenai, A.; Wagner, S. R.

    2015-12-11

    We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately -20°C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

  14. SEU hardening of CMOS memory circuit

    NASA Technical Reports Server (NTRS)

    Whitaker, S.; Canaris, J.; Liu, K.

    1990-01-01

    This paper reports a design technique to harden CMOS memory circuits against Single Event Upset (SEU) in the space environment. A RAM cell and Flip Flop design are presented to demonstrate the method. The Flip Flop was used in the control circuitry for a Reed Solomon encoder designed for the Space Station.

  15. Design and realization of CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Xu, Jian; Xiao, Zexin

    2008-02-01

    A project was presented that instrumental design of an economical CMOS microscope image sensor. A high performance, low price, black-white camera chip OV5116P was used as the core of the sensor circuit; Designing and realizing peripheral control circuit of sensor; Through the control on dial switch to realize different functions of the sensor chip in the system. For example: auto brightness level descending function on or off; gamma correction function on or off; auto and manual backlight compensation mode conversion and so on. The optical interface of sensor is designed for commercialization and standardization. The images of sample were respectively gathered with CCD and CMOS. Result of the experiment indicates that both performances were identical in several aspects as follows: image definition, contrast control, heating degree and the function can be adjusted according to the demand of user etc. The imperfection was that the CMOS with smaller field and higher noise than CCD; nevertheless, the maximal advantage of choosing the CMOS chip is its low cost. And its imaging quality conformed to requirement of the economical microscope image sensor.

  16. Fully CMOS-compatible titanium nitride nanoantennas

    NASA Astrophysics Data System (ADS)

    Briggs, Justin A.; Naik, Gururaj V.; Petach, Trevor A.; Baum, Brian K.; Goldhaber-Gordon, David; Dionne, Jennifer A.

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  17. Low energy CMOS for space applications

    NASA Technical Reports Server (NTRS)

    Panwar, Ramesh; Alkalaj, Leon

    1992-01-01

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  18. CMOS preamplifiers for detectors large and small

    SciTech Connect

    O`Connor, P.

    1997-12-31

    We describe four CMOS preamplifiers developed for multiwire proportional chambers (MWPC) and silicon drift detectors (SDD) covering a capacitance range from 150 pF to 0.15 pF. Circuit techniques to optimize noise performance, particularly in the low-capacitance regime, are discussed.

  19. Improving CMOS-compatible Germanium photodetectors.

    PubMed

    Li, Guoliang; Luo, Ying; Zheng, Xuezhe; Masini, Gianlorenzo; Mekis, Attila; Sahni, Subal; Thacker, Hiren; Yao, Jin; Shubin, Ivan; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

    2012-11-19

    We report design improvements for evanescently coupled Germanium photodetectors grown at low temperature. The resulting photodetectors with 10 μm Ge length manufactured in a commercial CMOS process achieve >0.8 A/W responsivity over the entire C-band, with a device capacitance of <7 fF based on measured data.

  20. A fail-safe CMOS logic gate

    NASA Technical Reports Server (NTRS)

    Bobin, V.; Whitaker, S.

    1990-01-01

    This paper reports a design technique to make Complex CMOS Gates fail-safe for a class of faults. Two classes of faults are defined. The fail-safe design presented has limited fault-tolerance capability. Multiple faults are also covered.

  1. Low-Power SOI CMOS Transceiver

    NASA Technical Reports Server (NTRS)

    Fujikawa, Gene (Technical Monitor); Cheruiyot, K.; Cothern, J.; Huang, D.; Singh, S.; Zencir, E.; Dogan, N.

    2003-01-01

    The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS

  2. CMOS Image Sensor with a Built-in Lane Detector.

    PubMed

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%. PMID:22573983

  3. CMOS Image Sensor with a Built-in Lane Detector.

    PubMed

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

  4. CMOS Image Sensor with a Built-in Lane Detector

    PubMed Central

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%. PMID:22573983

  5. A CMOS Neural Interface for a Multichannel Vestibular Prosthesis

    PubMed Central

    Hageman, Kristin N.; Kalayjian, Zaven K.; Tejada, Francisco; Chiang, Bryce; Rahman, Mehdi A.; Fridman, Gene Y.; Dai, Chenkai; Pouliquen, Philippe O.; Georgiou, Julio; Della Santina, Charles C.; Andreou, Andreas G.

    2015-01-01

    We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45 ± 0.06 mA with durations as short as 10 µs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68–130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9–16.7°/s for the MVP2 and 2.0–14.2°/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference (t-test, p = 0.034), suggesting that the MVP2A achieves performance at least as good as the larger MVP2. PMID:25974945

  6. CMOS MEMS capacitive absolute pressure sensor

    NASA Astrophysics Data System (ADS)

    Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

    2013-05-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

  7. Performance of digital integrated circuit technologies at very high temperatures

    SciTech Connect

    Prince, J.L.; Draper, B.L.; Rapp, E.A.; Kromberg, J.N.; Fitch, L.T.

    1980-01-01

    Results of investigations of the performance and reliability of digital bipolar and CMOS integrated circuits over the 25 to 340/sup 0/C range are reported. Included in these results are both parametric variation information and analysis of the functional failure mechanisms. Although most of the work was done using commercially available circuits (TTL and CMOS) and test chips from commercially compatible processes, some results of experimental simulations of dielectrically isolated CMOS are also discussed. It was found that commercial Schottky clamped TTL, and dielectrically isolated, low power Schottky-clamped TTL, functioned to junction temperatures in excess of 325/sup 0/C. Standard gold doped TTL functioned only to 250/sup 0/C, while commercial, isolated I/sup 2/L functioned to the range 250/sup 0/C to 275/sup 0/C. Commercial junction isolated CMOS, buffered and unbuffered, functioned to the range 280/sup 0/C to 310/sup 0/C/sup +/, depending on the manufacturer. Experimental simulations of simple dielectrically isolated CMOS integrated circuits, fabricated with heavier doping levels than normal, functioned to temperatures in excess of 340/sup 0/C. High temperature life testing of experimental, silicone-encapsulated simple TTL and CMOS integrated circuits have shown no obvious life limiting problems to date. No barrier to reliable functionality of TTL bipolar or CMOS integrated ciruits at temperatures in excess of 300/sup 0/C has been found.

  8. A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT switch

    NASA Astrophysics Data System (ADS)

    Zonghua, Zheng; Lingling, Sun; Jun, Liu; Shengzhou, Zhang

    2016-01-01

    A novel loss compensation technique for a series-shunt single-pole double-throw (SPDT) switch is presented operating in the 60 GHz. The feed-forward compensation network which is composed of an NMOS, a couple capacitance and a shunt inductance can reduce the impact of the feed forward capacitance to reduce the insertion loss and improve the isolation of the SPDT switch. The measured insertion loss and isolation characteristics of the switch somewhat deviating from the 60 GHz are analyzed revealing that the inaccuracy of the MOS model can greatly degrade the performance of the switch. The switch is implemented in TSMC 90-nm CMOS process and exhibits an isolation of above 27 dB at transmitter mode, and the insertion loss of 1.8-3 dB at 30-65 GHz by layout simulation. The measured insertion loss is 2.45 dB at 52 GHz and keeps < 4 dB at 30-64 GHz. The measured isolation is better than 25 dB at 30-64 GHz and the measured return loss is better than 10 dB at 30-65 GHz. A measured input 1 dB gain compression point of the switch is 13 dBm at 52 GHz and 15 dBm at 60 GHz. The simulated switching speed with rise time and fall time are 720 and 520 ps, respectively. The active chip size of the proposed switch is 0.5 × 0.95 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61331006, 61372021).

  9. Cmos spdt switch for wlan applications

    NASA Astrophysics Data System (ADS)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  10. Advanced CMOS Radiation Effects Testing Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.; Phan, Anthony M.; Seidleck, Christina M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  11. Advanced CMOS Radiation Effects Testing and Analysis

    NASA Technical Reports Server (NTRS)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  12. CMOS Camera Array With Onboard Memory

    NASA Technical Reports Server (NTRS)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  13. Radiation effects on scientific CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Yuanfu, Zhao; Liyan, Liu; Xiaohui, Liu; Xiaofeng, Jin; Xiang, Li

    2015-11-01

    A systemic solution for radiation hardened design is presented. Besides, a series of experiments have been carried out on the samples, and then the photoelectric response characteristic and spectral characteristic before and after the experiments have been comprehensively analyzed. The performance of the CMOS image sensor with the radiation hardened design technique realized total-dose resilience up to 300 krad(Si) and resilience to single-event latch up for LET up to 110 MeV·cm2/mg.

  14. CMOS-array design-automation techniques

    NASA Technical Reports Server (NTRS)

    Feller, A.; Lombardt, T.

    1979-01-01

    Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

  15. A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Kaiming, Nie; Suying, Yao; Jiangtao, Xu; Zhaorui, Jiang

    2014-03-01

    A 10-bit ratio-independent switch-capacitor (SC) cyclic analog-to-digital converter (ADC) with offset canceling for a CMOS image sensor is presented. The proposed ADC completes an N-bit conversion in 1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversion characteristic of the proposed cyclic ADC is inherently insensitive both to capacitor ratio and to amplifier offset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18-μm one-poly four-metal CMOS technology. The measured results indicate that the ADC has a signal-to-noise and distortion ratio (SNDR) of 53.6 dB and a DNL of +0:12/-0:14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 μW with a 1.8 V supply, and its area is 0.03 × 0.8 mm2.

  16. CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications.

    PubMed

    Hussain, Aftab M; Hussain, Muhammad M

    2016-06-01

    Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. PMID:26607553

  17. CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications.

    PubMed

    Hussain, Aftab M; Hussain, Muhammad M

    2016-06-01

    Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered.

  18. Gun muzzle flash detection using a CMOS single photon avalanche diode

    NASA Astrophysics Data System (ADS)

    Merhav, Tomer; Savuskan, Vitali; Nemirovsky, Yael

    2013-10-01

    Si based sensors, in particular CMOS Image sensors, have revolutionized low cost imaging systems but to date have hardly been considered as possible candidates for gun muzzle flash detection, due to performance limitations, and low SNR in the visible spectrum. In this study, a CMOS Single Photon Avalanche Diode (SPAD) module is used to record and sample muzzle flash events in the visible spectrum, from representative weapons, common on the modern battlefield. SPADs possess two crucial properties for muzzle flash imaging - Namely, very high photon detection sensitivity, coupled with a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. This enables high sampling frequencies in the kilohertz range without SNR degradation, in contrast to regular CMOS image sensors. To date, the SPAD has not been utilized for flash detection in an uncontrolled environment, such as gun muzzle flash detection. Gun propellant manufacturers use alkali salts to suppress secondary flashes ignited during the muzzle flash event. Common alkali salts are compounds based on Potassium or Sodium, with spectral emission lines around 769nm and 589nm, respectively. A narrow band filter around the Potassium emission doublet is used in this study to favor the muzzle flash signal over solar radiation. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength under the specified imaging conditions. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics.

  19. Radiation characteristics of scintillator coupled CMOS APS for radiography conditions

    NASA Astrophysics Data System (ADS)

    Kim, Kwang Hyun; Kim, Soongpyung; Kang, Dong-Won; Kim, Dong-Kie

    2006-11-01

    Under industrial radiography conditions, we analyzed short-term radiation characteristics of scintillator coupled CMOS APS (hereinafter SC CMOS APS). By means of experimentation, the contribution of the transmitted X-ray through the scintillator to the properties of the CMOS APS and the afterimage, generated in the acquired image even at low dose condition, were investigated. To see the transmitted X-ray effects on the CMOS APS, Fein focus™ X-ray machine, two scintillators of Lanex™ Fine and Regular, and two CMOS APS array of RadEye™ were used under the conditions of 50 kV p/1 mAs and 100 kV p/1 mAs. By measuring the transmitted X-ray on signal and Noise Power Spectrum, we analytically examined the generation mechanism of the afterimage, based on dark signal or dark current increase in the sensor, and explained the afterimage in the SC CMOS APS.

  20. Design and implementation of IEEE 802.11ac MAC controller in 65 nm CMOS process

    NASA Astrophysics Data System (ADS)

    Peng, Cheng; Bin, Wu; Yong, Hei

    2016-02-01

    An IEEE-802.11ac-1*1 wireless LAN system-on-a-chip (SoC) that integrates an analog front end, a digital base-band processor and a media access controller has been implemented in 65 nm CMOS technology. It can provide significantly increased throughput, high efficiency rate selection, and fully backward compatibility with the existing 802.11a/n WLAN protocols. Especially the measured maximum throughput of UDP traffic can be up to 267 Mbps. Project supported by the National Great Specific Project of China (No. 2012ZX03004004_001).

  1. Multi-purpose CMOS sensor interface for low-power applications

    NASA Astrophysics Data System (ADS)

    Wouters, P.; de Cooman, M.; Puers, R.

    1994-08-01

    A dedicated low-power CMOS transponder microchip is presented as part of a novel telemetry implant for biomedical applications. This mixed analog-digital circuit contains an identification code and collects information on physiological parameters, i.e., body temperature and physical activity, and on the status of the battery. To minimize the amount of data to be transmitted, a dedicated signal processing algorithm is embedded within its circuitry. All telemetry functions (encoding, modulation, generation of the carrier) are implemented on the integrated circuit. Emphasis is on a high degree of flexibility towards sensor inputs and internal data management, extreme miniaturization, and low-power consumption to allow a long implantation lifetime.

  2. Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

    NASA Technical Reports Server (NTRS)

    Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.; Ackland, B.; Dickinson, A.; Eid, E.; Inglis, D.

    1994-01-01

    This paper describes ongoing research and development of CMOS active pixel image sensors for low cost commercial applications. A number of sensor designs have been fabricated and tested in both p-well and n-well technologies. Major elements in the development of the sensor include on-chip analog signal processing circuits for the reduction of fixed pattern noise, on-chip timing and control circuits and on-chip analog-to-digital conversion (ADC). Recent results and continuing efforts in these areas will be presented.

  3. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    PubMed

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-01-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory. PMID:24180626

  4. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    PubMed

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-11-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

  5. VLSI partitioning of a 2-Gs/s digital spectrometer

    NASA Astrophysics Data System (ADS)

    von Herzen, Brian

    1991-05-01

    A digital correlating spectrometer for radio astronomy that is based on a custom GaAs digitizer and a custom micropipelined CMOS correlator is described. The digitizer quantizes at two gigasamples per second (Gs/s) and 2-b resolution. A GaAs demultiplexer distributes the data into eight parallel streams of 250 Ms/s each. The CMOS correlator operates at 250 Ms/s using 20 mW per correlator lag. The correlator output is processed on a host microcomputer to create a 1-GHz spectrum of the input signal that can be displayed interactively. An 8 x 9-mm chip is being developed in a 2-micron process that contains 320 correlator lags. The design is partitioned into GaAs and CMOS components according to the required throughput at each stage of the system. The fastest signals (2 GHz) are kept on the chip level to minimize delay, crosstalk, system noise, and power consumption. Moderate-speed signals (250 MHz) are driven by GaAs components. CMOS components are used where high-speed outputs are not required. A strong synergy between the correlator architecture and micropipelined CMOS technology improves the performance by an order of magnitude compared to existing designs. Preliminary correlator chips have been built and tested at 250 Ms/s; final chips are under design.

  6. Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

    NASA Technical Reports Server (NTRS)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-01-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  7. Thermal Radiometer Signal Processing using Radiation Hard CMOS Application Specific Integrated Circuits for use in Harsh Planetary Environments

    NASA Astrophysics Data System (ADS)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-10-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission [1] require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-cm2/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  8. Development of a large-area CMOS-based detector for real-time x-ray imaging

    NASA Astrophysics Data System (ADS)

    Heo, Sung Kyn; Park, Sung Kyu; Hwang, Sung Ha; Im, Dong Ak; Kosonen, Jari; Kim, Tae Woo; Yun, Seungman; Kim, Ho Kyung

    2010-04-01

    Complementary metal-oxide-semiconductor (CMOS) active pixel sensors (APSs) with high electrical and optical performances are now being attractive for digital radiography (DR) and dental cone-beam computed tomography (CBCT). In this study, we report our prototype CMOS-based detectors capable of real-time imaging. The field-of-view of the detector is 12 × 14.4 cm. The detector employs a CsI:Tl scintillator as an x-ray-to-light converter. The electrical performance of the CMOS APS, such as readout noise and full-well capacity, was evaluated. The x-ray imaging characteristics of the detector were evaluated in terms of characteristic curve, pre-sampling modulation transfer function, noise power spectrum, detective quantum efficiency, and image lag. The overall performance of the detector is demonstrated with phantom images obtained for DR and CBCT applications. The detailed development description and measurement results are addressed. With the results, we suggest that the prototype CMOS-based detector has the potential for CBCT and real-time x-ray imaging applications.

  9. A CMOS pressure sensor tag chip for passive wireless applications.

    PubMed

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

  10. A CMOS pressure sensor tag chip for passive wireless applications.

    PubMed

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-03-23

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

  11. A CMOS Smart Thermal Sensor for Biomedical Application

    NASA Astrophysics Data System (ADS)

    Lee, Ho-Yin; Chen, Shih-Lun; Luo, Ching-Hsing

    This paper describes a smart thermal sensing chip with an integrated vertical bipolar transistor sensor, a Sigma Delta Modulator (SDM), a Micro-Control Unit (MCU), and a bandgap reference voltage generator for biomedical application by using 0.18μm CMOS process. The npn bipolar transistors with the Deep N-Well (DNW) instead of the pnp bipolar transistor is first adopted as the sensor for good isolation from substrate coupling noise. In addition to data compression, Micro-Control Unit (MCU) plays an important role for executing auto-calibration by digitally trimming the bipolar sensor in parallel to save power consumption and to reduce feedback complexity. It is different from the present analog feedback calibration technologies. Using one sensor, instead of two sensors, to create two differential signals in 180° phase difference input to SDM is also a novel design of this work. As a result, in the range of 0°C to 80°C or body temperature (37±5°C), the inaccuracy is less than ±0.1°C or ±0.05°C respectively with one-point calibration after packaging. The average power consumption is 268.4μW with 1.8V supply voltage.

  12. A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

    PubMed Central

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-01-01

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of −20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

  13. A hierarchical approach to test generation for CMOS VLSI circuits

    NASA Astrophysics Data System (ADS)

    Weening, Edward Christiaan

    A hierarchical approach to the automatic test pattern generation for large digital VLSI circuits, fabricated in CMOS technology, is developed and implemented. The use of information on the circuit's hierarchy, which is readily available from most modern CAD (Computer Aided Design) systems, speeds up the test generation process considerably and enhances the quality of the tests generated. The hierarchical test generation tool can also be integrated in future CAD systems making test generation and testability enhancement during circuit design feasible. The hierarchical approach is described at the switch, functional, and behavioral level. A test pattern generation algorithm at the switch level is presented. Test generation and fault simulation algorithms both using OBDD (Ordered Binary Decision Diagram) functional descriptions of the circuit modules are presented. A test plan generation method at the behavioral level is presented. Practical results show that the hierarchical approach to test generation is more efficient than a conventional, non-hierarchical approach, especially for switch level faults. The results also show that the use of Design For Testability (DFT) circuitry is supported at the behavioral level.

  14. Characterization of CMOS image sensors with Nyquist rate pixel-level ADC

    NASA Astrophysics Data System (ADS)

    Yang, David X. D.; Tian, Hui; Fowler, Boyd A.; Liu, Xinqiao; El Gamal, Abbas

    1999-03-01

    Techniques for characterizing CCD imagers have been developed over many years. These techniques have been recently modified and extended to CMOS PPS and APS imagers. With the scaling of CMOS technology, an increasing number of transistors can be added to each pixel. A promising direction to utilize these transistors is to perform pixel level ADC. The authors have designed and prototyped two imagers with pixel level Nyquist rate ADC. The ADCs operate in parallel and output data one bit at a time. The data is read out of the imager array one bit plane at a time in a manner similar to a digital memory. Existing characterization techniques could not be directly used for these imagers, however, since there is no facility to read out the analog pixel values before ADC, and the ADC resolution is limited to only 8 bits. Fortunately, the ADCs are fully testable electrically without the need for any light or optics. This makes it possible obtain the ADC transfer curve, which greatly simplifies characterization. In this paper we describe how we characterize our pixel level ADC imagers. To estimate QE, we measure the imager photon to DN transfer curve and the ADC transfer curve. We find that both curves are quite linear.Using an estimate of the sense node capacitance we then estimate sensitivity, and QE. To estimate FPN we model it as an outcome of the sum of two uncorrelated random processes, one representing the ADC FPN, and the other representing the photodetector FPN, and develop estimators for the model parameters form imager data under uniform illumination. We report characterization result for a 640 by 512 imager, which was fabricated in a 0.35 micrometers standard digital CMOS process.

  15. Failures of CMOS Circuits Irradiated At Low Rates

    NASA Technical Reports Server (NTRS)

    Goben, Charles A.; Price, William E.

    1990-01-01

    Report describes experiments on irradiation of SGS 4007 complementary metal oxide/semiconductor (CMOS) integrated inverter circuits by 60Co and 137Cs radioactive sources. Purpose of experiments to supplement previous observations that minimum radiation doses at which failure occurred in more-complicated CMOS parts were lower at lower dose rates.

  16. Vertical Isolation for Photodiodes in CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata

    2008-01-01

    In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

  17. Monolithic CMOS imaging x-ray spectrometers

    NASA Astrophysics Data System (ADS)

    Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

    2014-07-01

    The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

  18. Using a large area CMOS APS for direct chemiluminescence detection in Western blotting electrophoresis

    NASA Astrophysics Data System (ADS)

    Esposito, Michela; Newcombe, Jane; Anaxagoras, Thalis; Allinson, Nigel M.; Wells, Kevin

    2012-03-01

    Western blotting electrophoretic sequencing is an analytical technique widely used in Functional Proteomics to detect, recognize and quantify specific labelled proteins in biological samples. A commonly used label for western blotting is Enhanced ChemiLuminescence (ECL) reagents based on fluorescent light emission of Luminol at 425nm. Film emulsion is the conventional detection medium, but is characterized by non-linear response and limited dynamic range. Several western blotting digital imaging systems have being developed, mainly based on the use of cooled Charge Coupled Devices (CCDs) and single avalanche diodes that address these issues. Even so these systems present key drawbacks, such as a low frame rate and require operation at low temperature. Direct optical detection using Complementary Metal Oxide Semiconductor (CMOS) Active Pixel Sensors (APS)could represent a suitable digital alternative for this application. In this paper the authors demonstrate the viability of direct chemiluminescent light detection in western blotting electrophoresis using a CMOS APS at room temperature. Furthermore, in recent years, improvements in fabrication techniques have made available reliable processes for very large imagers, which can be now scaled up to wafer size, allowing direct contact imaging of full size western blotting samples. We propose using a novel wafer scale APS (12.8 cm×13.2 cm), with an array architecture using two different pixel geometries that can deliver an inherently low noise and high dynamic range image at the same time representing a dramatic improvement with respect to the current western blotting imaging systems.

  19. A low-power CMOS smart temperature sensor for RFID application

    NASA Astrophysics Data System (ADS)

    Liangbo, Xie; Jiaxin, Liu; Yao, Wang; Guangjun, Wen

    2014-11-01

    This paper presents the design and implement of a CMOS smart temperature sensor, which consists of a low power analog front-end and a 12-bit low-power successive approximation register (SAR) analog-to-digital converter (ADC). The analog front-end generates a proportional-to-absolute-temperature (PTAT) voltage with MOSFET circuits operating in the sub-threshold region. A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage. Using 0.18 μm CMOS technology, measurement results show that the temperature error is -0.69/+0.85 °C after one-point calibration over a temperature range of -40 to 100 °C. Under a conversion speed of 1K samples/s, the power consumption is only 2.02 μW while the chip area is 230 × 225 μm2, and it is suitable for RFID application.

  20. Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

    NASA Astrophysics Data System (ADS)

    Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

    2008-02-01

    Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

  1. Capacitive micropressure sensors with underneath readout circuit using a standard CMOS process

    NASA Astrophysics Data System (ADS)

    Chang, Shihchen; Dai, Chingliang; Chiou, Jinghung; Chang, Peizen

    2001-08-01

    A capacitive micropressure sensor with readout circuits on a single chip is fabricated using commercial 0.35micrometers CMOS process technology and post-processing. The main break through feature of the chip is the positioning of its readout circuits under the pressure sensor, allowing the chip to be smaller. Post-processing included anisotropic dry etching and wet etching to remove the sacrificial layer, and the use of PECVD nitride to seal the etching holes of the pressure sensor. The sacrificial layer was the metal 3 layer of the standard 0.35 micrometers CMOS process. In addition, the readout circuit is divided into analog and digital parts, with the digital part being an alternate coupled RS flip- flop with four inverters that sharpened the output wave. Moreover, the analog part is employed switched capacitor methodology. The pressure sensor contained an 8 X 8 sensing cells array, and the total area of the pressure sensor chip is 2mmx2 mm. In addition to illustrating the design and fabrication of the capacitive pressure sensor, this investigation demonstrates the simulation and testing results of the readout circuit.

  2. Advances in CMOS Solid-state Photomultipliers for Scintillation Detector Applications

    PubMed Central

    Christian, James F.; Stapels, Christopher J.; Johnson, Erik B.; McClish, Mickel; Dokhale, Purushotthom; Shah, Kanai S.; Mukhopadhyay, Sharmistha; Chapman, Eric; Augustine, Frank L.

    2014-01-01

    Solid-state photomultipliers (SSPMs) are a compact, lightweight, potentially low-cost alternative to a photomultiplier tube for a variety of scintillation detector applications, including digital-dosimeter and medical-imaging applications. Manufacturing SSPMs with a commercial CMOS process provides the ability for rapid prototyping, and facilitates production to reduce the cost. RMD designs CMOS SSPM devices that are fabricated by commercial foundries. This work describes the characterization and performance of these devices for scintillation detector applications. This work also describes the terms contributing to device noise in terms of the excess noise of the SSPM, the binomial statistics governing the number of pixels triggered by a scintillation event, and the background, or thermal, count rate. The fluctuations associated with these terms limit the resolution of the signal pulse amplitude. We explore the use of pixel-level signal conditioning, and characterize the performance of a prototype SSPM device that preserves the digital nature of the signal. In addition, we explore designs of position-sensitive SSPM detectors for medical imaging applications, and characterize their performance. PMID:25540471

  3. Design of high speed camera based on CMOS technology

    NASA Astrophysics Data System (ADS)

    Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

    2007-12-01

    The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

  4. Organic Field-Effect Transistors for CMOS Devices

    NASA Astrophysics Data System (ADS)

    Melzer, Christian; von Seggern, Heinz

    Organic field-effect transistors (OFETs) are the key elements of future low cost electronics such as radio frequency identification tags. In order to take full advantage of organic electronics, low power consumption is mandatory, requiring the use of a complementary metal oxide semiconductor (CMOS) like technique. To realize CMOS-devices p-type and n-type organic field-effect transistors on one substrate have to be provided. Here, the latest concepts to produce in a straightforward way complementary acting OFETs for CMOS-like elements are illustrated on basis of the inverter. Starting from a simple description of thin-film transistors, the basic design rules for the development of complementary OFETs are given and some realizations of CMOS-like inverters are discussed. A CMOS-like inverter based on two identical field-effect transistors disclosing almost unipolar p-type and n-type behavior is presented.

  5. Real-time reconfigurable subthreshold CMOS perceptron.

    PubMed

    Aunet, S; Oelmann, B; Norseng, P A; Berg, Y

    2008-04-01

    In this paper, a new, real-time reconfigurable perceptron circuit element is presented. A six-transistor version used as a threshold gate, having a fan-in of three, producing adequate outputs for threshold of T =1, 2 and 3 is demonstrated by chip measurements. Subthreshold operation for supply voltages in the range of 100-350 mV is shown. The circuit performs competitively with a standard static complimentary metal-oxide-semiconductor (CMOS) implementation when maximum speed and energy delay product are taken into account, when used in a ring oscillator. Functionality per transistor is, to our knowledge, the highest reported for a variety of comparable circuits not based on floating gate techniques. Statistical simulations predict probabilities for making working circuits under mismatch and process variations. The simulations, in 120-nm CMOS, also support discussions regarding lower limits to supply voltage and redundancy. A brief discussion on how the circuit may be exploited as a basic building block for future defect tolerant mixed signal circuits, as well as neural networks, exploiting redundancy, is included.

  6. Modulated CMOS camera for fluorescence lifetime microscopy.

    PubMed

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition. PMID:26500051

  7. Challenges of nickel silicidation in CMOS technologies

    SciTech Connect

    Breil, Nicolas; Lavoie, Christian; Ozcan, Ahmet; Baumann, Frieder; Klymko, Nancy; Nummy, Karen; Sun, Bing; Jordan-Sweet, Jean; Yu, Jian; Zhu, Frank; Narasimha, Shreesh; Chudzik, Michael

    2015-04-01

    In our paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g.SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of the nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. Furthermore, we investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (1 0 0) and (1 1 1) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni–Pt–Si–Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.

  8. The 1.2 micron CMOS technology

    NASA Technical Reports Server (NTRS)

    Pina, C. A.

    1985-01-01

    A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.

  9. Modulated CMOS camera for fluorescence lifetime microscopy.

    PubMed

    Chen, Hongtao; Holst, Gerhard; Gratton, Enrico

    2015-12-01

    Widefield frequency-domain fluorescence lifetime imaging microscopy (FD-FLIM) is a fast and accurate method to measure the fluorescence lifetime of entire images. However, the complexity and high costs involved in construction of such a system limit the extensive use of this technique. PCO AG recently released the first luminescence lifetime imaging camera based on a high frequency modulated CMOS image sensor, QMFLIM2. Here we tested and provide operational procedures to calibrate the camera and to improve the accuracy using corrections necessary for image analysis. With its flexible input/output options, we are able to use a modulated laser diode or a 20 MHz pulsed white supercontinuum laser as the light source. The output of the camera consists of a stack of modulated images that can be analyzed by the SimFCS software using the phasor approach. The nonuniform system response across the image sensor must be calibrated at the pixel level. This pixel calibration is crucial and needed for every camera settings, e.g. modulation frequency and exposure time. A significant dependency of the modulation signal on the intensity was also observed and hence an additional calibration is needed for each pixel depending on the pixel intensity level. These corrections are important not only for the fundamental frequency, but also for the higher harmonics when using the pulsed supercontinuum laser. With these post data acquisition corrections, the PCO CMOS-FLIM camera can be used for various biomedical applications requiring a large frame and high speed acquisition.

  10. A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs

    PubMed Central

    Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

    2015-01-01

    This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB. PMID:26712765

  11. A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs.

    PubMed

    Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

    2015-12-26

    This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.

  12. Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications

    PubMed Central

    Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

    2012-01-01

    One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

  13. Mixed Linear/Square-Root Encoded Single Slope Ramp Provides a Fast, Low Noise Analog to Digital Converter with Very High Linearity for Focal Plane Arrays

    NASA Technical Reports Server (NTRS)

    Wrigley, Christopher James (Inventor); Hancock, Bruce R. (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor)

    2014-01-01

    An analog-to-digital converter (ADC) converts pixel voltages from a CMOS image into a digital output. A voltage ramp generator generates a voltage ramp that has a linear first portion and a non-linear second portion. A digital output generator generates a digital output based on the voltage ramp, the pixel voltages, and comparator output from an array of comparators that compare the voltage ramp to the pixel voltages. A return lookup table linearizes the digital output values.

  14. Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

    2008-01-01

    Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

  15. A monolithically integrated torsional CMOS-MEMS relay

    NASA Astrophysics Data System (ADS)

    Riverola, M.; Sobreviela, G.; Torres, F.; Uranga, A.; Barniol, N.

    2016-11-01

    We report experimental demonstrations of a torsional microelectromechanical (MEM) relay fabricated using the CMOS-MEMS approach (or intra-CMOS) which exploits the full foundry inherent characteristics enabling drastic reduction of the fabrication costs and batch production. In particular, the relay is monolithically integrated in the back end of line of a commercial standard CMOS technology (AMS 0.35 μm) and released by means of a simple one-step mask-less wet etching. The fabricated torsional relay exhibits an extremely steep switching behaviour symmetrical about both contact sides with an on-state contact resistance in the k Ω -range throughout the on-off cycling test.

  16. 1984 Joint Congress: CGU and CMOS

    NASA Astrophysics Data System (ADS)

    Camfield, P. A.

    The Canadian Geophysical Union (CGU) had a very successful joint meeting with the Canadian Meteorological and Oceanographic Society (CMOS) at Dalhousie University in Halifax, Nova Scotia, May 29 to June 1, 1984. Thirty-five scientific sessions were held in the 4-day meeting period.The invited speaker for CGU at the plenary session, David Simpson of Lamont-Doherty Geological Observatory, spoke about the Halifax Explosion of 1917 in terms of a seismic event. The 2.6-kt explosion was the largest man-made explosion prior to the detonation of the first atomic bombs. The effective seismic magnitude of the event may have been m, = 2.5-3.0.

  17. Log polar image sensor in CMOS technology

    NASA Astrophysics Data System (ADS)

    Scheffer, Danny; Dierickx, Bart; Pardo, Fernando; Vlummens, Jan; Meynants, Guy; Hermans, Lou

    1996-08-01

    We report on the design, design issues, fabrication and performance of a log-polar CMOS image sensor. The sensor is developed for the use in a videophone system for deaf and hearing impaired people, who are not capable of communicating through a 'normal' telephone. The system allows 15 detailed images per second to be transmitted over existing telephone lines. This framerate is sufficient for conversations by means of sign language or lip reading. The pixel array of the sensor consists of 76 concentric circles with (up to) 128 pixels per circle, in total 8013 pixels. The interior pixels have a pitch of 14 micrometers, up to 250 micrometers at the border. The 8013-pixels image is mapped (log-polar transformation) in a X-Y addressable 76 by 128 array.

  18. CMOS imager for pointing and tracking applications

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

    2006-01-01

    Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

  19. Latchup in CMOS devices from heavy ions

    NASA Technical Reports Server (NTRS)

    Soliman, K.; Nichols, D. K.

    1983-01-01

    It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

  20. CMOS Hybrid Pixel Detectors for Scientific, Industrial and Medical Applications

    NASA Astrophysics Data System (ADS)

    Broennimann, Christian

    2009-03-01

    Crystallography is the principal technique for determining macromolecular structures at atomic resolution and uses advantageously the high intensity of 3rd generation synchrotron X-ray sources . Macromolecular crystallography experiments benefit from excellent beamline equipment, recent software advances and modern X-ray detectors. However, the latter do not take full advantage of the brightness of modern synchrotron sources. CMOS Hybrid pixel array detectors, originally developed for high energy physics experiments, meet these requirements. X-rays are recorded in single photon counting mode and data thus are stored digitally at the earliest possible stage. This architecture leads to several advantages over current detectors: No detector noise is added to the signal. Readout time is reduced to a few milliseconds. The counting rates are matched to beam intensities at protein crystallography beamlines at 3rd generation synchrotrons. The detector is not sensitive to X-rays during readout; therefore no mechanical shutter is required. The detector has a very sharp point spread function (PSF) of one pixel, which allows better resolution of adjacent reflections. Low energy X-rays can be suppressed by the comparator At the Paul Scherrer Institute (PSI) in Switzerland the first and largest array based on this technology was constructed: The Pilatus 6M detector. The detector covers an area of 43.1 x 44.8 cm2 , has 6 million pixels and is read out noise free in 3.7 ms. Since June 2007 the detector is in routine operation at the beamline 6S of the Swiss Light Source (SLS). The company DETCRIS Ltd, has licensed the technology from PSI and is commercially offering the PILATUS detectors. Examples of the wide application range of the detectors will be shown.

  1. Photocurrent estimation from multiple nondestructive samples in CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Liu, Xinqiao; El Gamal, Abbas

    2001-05-01

    CMOS image sensors generally suffer form lower dynamic range than CCDs due to their higher readout noise. Their high speed readout capability and the potential of integrating memory and signal processing with the sensor on the same chip, open up many possibilities for enhancing their dynamic range. Earlier work have demonstrated the use of multiple non-destructive samples to enhance dynamic range, while achieving higher SNR than using other dynamic range enhancement schemes. The high dynamic range image is constructed by appropriately scaling each pixel's last sample before saturation. Conventional CDS is used to reduce offset FPN and reset noise. This simple high dynamic range image construction scheme, however, does not take full advantage of the multiple samples. Readout noise power, which doubles as a result of performing CDS, remain as high as in conventional sensor operation. As a result dynamic range is only extended at the high illumination end. The paper explores the use of linear mean-square-error estimation to more fully exploit the multiple pixel samples to reduce readout noise and thus extend dynamic range at the low illumination end. We present three estimation algorithms: (1) a recursive estimator when reset noise and offset FPN are ignored, (2) a non-recursive algorithm when reset noise and FPN are considered, and (3) a recursive estimation algorithm for case (2), which achieves mean square error close to the non-recursive algorithm without the need to store all the samples. The later recursive algorithm is attractive since it requires the storage of only a few pixel values per pixel, which makes its implementation in a single chip digital imaging system feasible.

  2. Depleted CMOS pixels for LHC proton-proton experiments

    NASA Astrophysics Data System (ADS)

    Wermes, N.

    2016-07-01

    While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

  3. Implementation of CMOS Millimeter-Wave Devices for Rotational Spectroscopy

    NASA Astrophysics Data System (ADS)

    Drouin, Brian; Tang, Adrian; Schlecht, Erich T.; Daly, Adam M.; Brageot, Emily; Gu, Qun Jane; Ye, Yu; Shu, Ran; Chang, M.-C. Frank; Kim, Rod M.

    2015-06-01

    The extension of radio-frequency CMOS circuitry into millimeter wavelengths promises the extension of spectroscopic techniques in compact, power efficient systems. We are now exploring the use of CMOS millimeter devices for low-mass, low-power instrumentation capable of remote or in-situ detection of gas composition during space missions. This effort focuses on the development of a semi-confocal Fabry-Perot cavity with mm-wavelength CMOS transmitter and receiver attached directly to a cavity coupler. Placement of the devices within the cavity structure bypasses problems encountered with signal injection and extraction in traditional cavity designs and simultaneously takes full advantage of the miniaturized form of the CMOS hardware. The presentation will provide an overview of the project and details of the accomplishments thus far, including the development and testing of a pulse modulated 83-98 GHz transmitter.

  4. CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

    NASA Technical Reports Server (NTRS)

    Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

    2006-01-01

    This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

  5. Improved CMOS field isolation using Germaniun/Boron implantation

    SciTech Connect

    Pfiester, J.R.; Alvis, J.R. )

    1988-08-01

    A novel germanium/boron implantation technique for improving the electrical field isolation for high-density CMOS circuits is demonstrated. Germanium implantation causes a reduction in dopant diffusion and segregation during field oxidation and is shown to increase the p-well field threshold voltage by as much as 40 percent with no significant degradation to junction or device performance. Selective germanium implantation with a blanket boron field implant can also improve the electrical field isolation behavior for CMOS circuits.

  6. CMOS front end electronics for the ATLAS muon detector

    SciTech Connect

    Huth, J.; Oliver, J.; Hazen, E.; Shank, J.

    1997-12-31

    An all-CMOS design for an integrated ASD (Amplifier-Shaper-Discriminator) chip for readout of the ATLAS Monitored Drift Tubes (MDTs) is presented. Eight channels of charge-sensitive preamp, two-stage pole/zero shaper, Wilkinson ADC and discriminator with programmable hysteresis are integrated on a single IC. Key elements have been prototyped in 1.2 and 0.5 micron CMOS operating at 5V and 3.3V respectively.

  7. Advancement of CMOS Doping Technology in an External Development Framework

    NASA Astrophysics Data System (ADS)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  8. Surface enhanced biodetection on a CMOS biosensor chip

    NASA Astrophysics Data System (ADS)

    Belloni, Federico; Sandeau, Laure; Contié, Sylvain; Vicaire, Florence; Owens, Roisin; Rigneault, Hervé

    2012-03-01

    We present a rigorous electromagnetic theory of the electromagnetic power emitted by a dipole located in the vicinity of a multilayer stack. We applied this formalism to a luminescent molecule attached to a CMOS photodiode surface and report light collection efficiency larger than 80% toward the CMOS silicon substrate. We applied this result to the development of a low-cost, simple, portable device based on CMOS photodiodes technology for the detection and quantification of biological targets through light detection, presenting high sensitivity, multiplex ability, and fast data processing. The key feature of our approach is to perform the analytical test directly on the CMOS sensor surface, improving dramatically the optical detection of the molecule emitted light into the high refractive index semiconductor CMOS material. Based on adequate surface chemistry modifications, probe spotting and micro-fluidics, we performed proof-of-concept bio-assays directed against typical immuno-markers (TNF-α and IFN-γ). We compared the developed CMOS chip with a commercial micro-plate reader and found similar intrinsic sensitivities in the pg/ml range.

  9. Digital Libraries.

    ERIC Educational Resources Information Center

    Fox, Edward A.; Urs, Shalini R.

    2002-01-01

    Provides an overview of digital libraries research, practice, and literature. Highlights include new technologies; redefining roles; historical background; trends; creating digital content, including conversion; metadata; organizing digital resources; services; access; information retrieval; searching; natural language processing; visualization;…

  10. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    PubMed

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  11. CMOS Amperometric ADC With High Sensitivity, Dynamic Range and Power Efficiency for Air Quality Monitoring.

    PubMed

    Li, Haitao; Boling, C Sam; Mason, Andrew J

    2016-08-01

    Airborne pollutants are a leading cause of illness and mortality globally. Electrochemical gas sensors show great promise for personal air quality monitoring to address this worldwide health crisis. However, implementing miniaturized arrays of such sensors demands high performance instrumentation circuits that simultaneously meet challenging power, area, sensitivity, noise and dynamic range goals. This paper presents a new multi-channel CMOS amperometric ADC featuring pixel-level architecture for gas sensor arrays. The circuit combines digital modulation of input currents and an incremental Σ∆ ADC to achieve wide dynamic range and high sensitivity with very high power efficiency and compact size. Fabricated in 0.5 [Formula: see text] CMOS, the circuit was measured to have 164 dB cross-scale dynamic range, 100 fA sensitivity while consuming only 241 [Formula: see text] and 0.157 [Formula: see text] active area per channel. Electrochemical experiments with liquid and gas targets demonstrate the circuit's real-time response to a wide range of analyte concentrations. PMID:27352395

  12. A CMOS pixel sensor prototype for the outer layers of linear collider vertex detector

    NASA Astrophysics Data System (ADS)

    Zhang, L.; Morel, F.; Hu-Guo, C.; Himmi, A.; Dorokhov, A.; Hu, Y.

    2015-01-01

    The International Linear Collider (ILC) expresses a stringent requirement for high precision vertex detectors (VXD). CMOS pixel sensors (CPS) have been considered as an option for the VXD of the International Large Detector (ILD), one of the detector concepts proposed for the ILC. MIMOSA-31 developed at IPHC-Strasbourg is the first CPS integrated with 4-bit column-level ADC for the outer layers of the VXD, adapted to an original concept minimizing the power consumption. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal noise and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with a self-triggered analog-to-digital converter (ADC). The ADC design was optimized for power saving at a sampling frequency of 6.25 MS/s. The prototype chip is fabricated in a 0.35 μm CMOS technology. This paper presents the details of the prototype chip and its test results.

  13. A low-power column-parallel ADC for high-speed CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Han, Ye; Li, Quanliang; Shi, Cong; Liu, Liyuan; Wu, Nanjian

    2013-08-01

    This paper presents a 10-bit low-power column-parallel cyclic analog-to-digital converter (ADC) used for high-speed CMOS image sensor (CIS). An opamp sharing technique is used to save power and area. Correlated double sampling (CDS) circuit and programmable gain amplifier (PGA) are integrated in the ADC, which avoids stand-alone circuit blocks. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.03mm2 was implemented in a 0.18μm 1P4M CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 2MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 2.1 LSB together with CDS, respectively. The power consumption from 1.8V supply is only 0.36mW.

  14. A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

    NASA Astrophysics Data System (ADS)

    Guang, Yang; Wang, Yao; Jiangwei, Yin; Renliang, Zheng; Wei, Li; Ning, Li; Junyan, Ren

    2009-01-01

    An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

  15. Use and imaging performance of CMOS flat panel imager with LiF/ZnS(Ag) and Gadox scintillation screens for neutron radiography

    NASA Astrophysics Data System (ADS)

    Cha, B. K.; kim, J. Y.; Kim, T. J.; Sim, C.; Cho, G.; Lee, D. H.; Seo, C.-W.; Jeon, S.; Huh, Y.

    2011-01-01

    In digital neutron radiography system, a thermal neutron imaging detector based on neutron-sensitive scintillating screens with CMOS(complementary metal oxide semiconductor) flat panel imager is introduced for non-destructive testing (NDT) application. Recently, large area CMOS APS (active-pixel sensor) in conjunction with scintillation films has been widely used in many digital X-ray imaging applications. Instead of typical imaging detectors such as image plates, cooled-CCD cameras and amorphous silicon flat panel detectors in combination with scintillation screens, we tried to apply a scintillator-based CMOS APS to neutron imaging detection systems for high resolution neutron radiography. In this work, two major Gd2O2S:Tb and 6LiF/ZnS:Ag scintillation screens with various thickness were fabricated by a screen printing method. These neutron converter screens consist of a dispersion of Gd2O2S:Tb and 6LiF/ZnS:Ag scintillating particles in acrylic binder. These scintillating screens coupled-CMOS flat panel imager with 25x50mm2 active area and 48μm pixel pitch was used for neutron radiography. Thermal neutron flux with 6x106n/cm2/s was utilized at the NRF facility of HANARO in KAERI. The neutron imaging characterization of the used detector was investigated in terms of relative light output, linearity and spatial resolution in detail. The experimental results of scintillating screen-based CMOS flat panel detectors demonstrate possibility of high sensitive and high spatial resolution imaging in neutron radiography system.

  16. Studies for a 10 μs, thin, high resolution CMOS pixel sensor for future vertex detectors

    NASA Astrophysics Data System (ADS)

    Voutsinas, G.; Amar-Youcef, S.; Baudot, J.; Bertolone, G.; Brogna, A.; Chon-Sen, N.; Claus, G.; Colledani, C.; Dorokhov, A.; Dozière, G.; Dulinski, W.; Degerli, Y.; De Masi, R.; Deveaux, M.; Gelin, M.; Goffe, M.; Hu-Guo, Ch.; Himmi, A.; Jaaskelainen, K.; Koziel, M.; Morel, F.; Müntz, C.; Orsini, F.; Santos, C.; Schrader, C.; Specht, M.; Stroth, J.; Valin, I.; Wagner, F. M.; Winter, M.

    2011-06-01

    Future high energy physics (HEP) experiments require detectors with unprecedented performances for track and vertex reconstruction. These requirements call for high precision sensors, with low material budget and short integration time. The development of CMOS sensors for HEP applications was initiated at IPHC Strasbourg more than 10 years ago, motivated by the needs for vertex detectors at the International Linear Collider (ILC) [R. Turchetta et al, NIM A 458 (2001) 677]. Since then several other applications emerged. The first real scale digital CMOS sensor MIMOSA26 equips Flavour Tracker at RHIC, as well as for the microvertex detector of the CBM experiment at FAIR. MIMOSA sensors may also offer attractive performances for the ALICE upgrade at LHC. This paper will demonstrate the substantial performance improvement of CMOS sensors based on a high resistivity epitaxial layer. First studies for integrating the sensors into a detector system will be addressed and finally the way to go to a 10 μs readout sensor will be discussed.

  17. A low-power and small-area column-level ADC for high frame-rate CMOS pixel sensor

    NASA Astrophysics Data System (ADS)

    Zhang, L.; Morel, F.; Hu-Guo, C.; Hu, Y.

    2014-07-01

    CMOS pixel sensors (CPS) have demonstrated performances meeting the specifications of the International Linear Collider (ILC) vertex detector (VTX). This paper presents a low-power and small-area 4-bit column-level analog-to-digital converter (ADC) for CMOS pixel sensors. The ADC employs a self-timed trigger and completes the conversion by performing a multi-bit/step approximation. As in the outer layers of the ILC vertex detector hit density is of the order of a few per thousand, in order to reduce power consumption, the ADC is designed to work in two modes: active mode and idle mode. The ADC is fabricated in a 0.35 μm CMOS process with a pixel pitch of 35 μm. It is implemented with 48 columns in a sensor prototype. Each column ADC covers an area of 35 ×545 μm2. The measured temporal noise and Fixed Pattern Noise (FPN) are 0.96 mV and 0.40 mV, respectively. The power consumption, for a 3 V supply and 6.25 MS/s sampling rate, is 486 μW during idle time, which is by far the most frequently employed one. This value rises to 714 μW in the case of the active mode. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.49/-0.28 LSB and 0.29/-0.20 LSB, respectively.

  18. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors

    PubMed Central

    Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

    2015-01-01

    This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within −Tclk~+Tclk. A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration. PMID:26561819

  19. Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

    NASA Astrophysics Data System (ADS)

    Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

    2016-05-01

    In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

  20. Novel CMOS time-delay integration using single-photon counting for high-speed industrial and aerospace applications

    NASA Astrophysics Data System (ADS)

    El-Desouki, Munir M.; Al-Azem, Badeea

    2014-03-01

    Time-delay integration (TDI) is a popular imaging technique that is used in many applications such as machine vision, dental scanning and satellite earth observation. One of the main advantages of using TDI imagers is the increased effective integration time that is achieved while maintaining high frame-rates. Another use for TDI imagers is with moving objects, such as the earth's surface or industrial machine vision applications, where integration time is limited in order to avoid motion blurs. Such technique may even find its way in mobile and consumer based imaging applications where the reduction in pixel size can limit the performance during low-light and high speed applications. Until recently, TDI was only used with charge-coupled devices (CCDs) mainly due to their charge transfer characteristics. CCDs however, are power consuming and slow when compared to CMOS technology and are no longer favorable for mobile applications. In this work, we report on novel single-photon counting based TDI technique that is implemented in standard CMOS technology allowing for complete camera-on-a-chip solution. The imager was fabricated in a standard CMOS 150 nm 5-metal digital process from LFoundry.

  1. Built-in self-test (BIST) techniques for millimeter wave CMOS transceivers

    NASA Astrophysics Data System (ADS)

    Mahzabeen, Tabassum

    The seamless integration of complementary metal oxide semiconductor (CMOS) transceivers with a digital CMOS process enhances on-chip testability, thus reducing production and testing costs. Built in self testability also improves yield by offering on-chip compensation. This work focuses on built in self test techniques for CMOS based millimeter wave (mm-wave) transceivers. Built-in-self-test (BIST) using the loopback method is one cost-effective method for testing these transceivers. Since the loopback switch is always present during the normal operation of the transceiver, the requirement of the switch is different than for a conventional switch. The switch needs to have high isolation and high impedance during its OFF period. Two 80 GHz single pole single throw (SPST) switches have been designed, fabricated in standard CMOS process, and measured to connect the loopback path for BIST applications. The loopback switches in this work provide the required criteria for loopback BIST. A stand alone 80 GHz low noise amplifier (LNA) and the same LNA integrated with one of the loopback switches have been fabricated, and measured to observe the difference in performance when the loopback switch is present. Besides the loopback switch, substrate leakage also forms a path between the transmitter and receiver. Substrate leakage has been characterized as a function of distance between the transmitter and receiver for consideration in using the BIST method. A BIST algorithm has been developed to estimate the process variation in device sizes by probing a low frequency ring oscillator to estimate the device variation and map this variation to the 80 GHz LNA. Probing a low frequency circuit is cheaper compared to the probing of a millimeter wave circuit and reduces the testing costs. The performance of the LNA degrades due to variation in device size. Once the shift in the device size is being estimated (from the ring oscillator's shifted frequency), the LNA's performance can be

  2. Adaptive Threshold Neural Spike Detector Using Stationary Wavelet Transform in CMOS.

    PubMed

    Yang, Yuning; Boling, C Sam; Kamboh, Awais M; Mason, Andrew J

    2015-11-01

    Spike detection is an essential first step in the analysis of neural recordings. Detection at the frontend eases the bandwidth requirement for wireless data transfer of multichannel recordings to extra-cranial processing units. In this work, a low power digital integrated spike detector based on the lifting stationary wavelet transform is presented and developed. By monitoring the standard deviation of wavelet coefficients, the proposed detector can adaptively set a threshold value online for each channel independently without requiring user intervention. A prototype 16-channel spike detector was designed and tested in an FPGA. The method enables spike detection with nearly 90% accuracy even when the signal-to-noise ratio is as low as 2. The design was mapped to 130 nm CMOS technology and shown to occupy 0.014 mm(2) of area and dissipate 1.7 μW of power per channel, making it suitable for implantable multichannel neural recording systems. PMID:25955990

  3. Large area CMOS bio-pixel array for compact high sensitive multiplex biosensing.

    PubMed

    Sandeau, Laure; Vuillaume, Cassandre; Contié, Sylvain; Grinenval, Eva; Belloni, Federico; Rigneault, Hervé; Owens, Roisin M; Fournet, Margaret Brennan

    2015-02-01

    A novel CMOS bio-pixel array which integrates assay substrate and assay readout is demonstrated for multiplex and multireplicate detection of a triplicate of cytokines with single digit pg ml(-1) sensitivities. Uniquely designed large area bio-pixels enable individual assays to be dedicated to and addressed by single pixels. A capability to simultaneously measure a large number of targets is provided by the 128 available pixels. Chemiluminescent assays are carried out directly on the pixel surface which also detects the emitted chemiluminescent photons, facilitating a highly compact sensor and reader format. The high sensitivity of the bio-pixel array is enabled by the high refractive index of silicon based pixels. This in turn generates a strong supercritical angle luminescence response significantly increasing the efficiency of the photon collection over conventional farfield modalities. PMID:25490928

  4. Integrating metal-oxide-decorated CNT networks with a CMOS readout in a gas sensor.

    PubMed

    Lee, Hyunjoong; Lee, Sanghoon; Kim, Dai-Hong; Perello, David; Park, Young June; Hong, Seong-Hyeon; Yun, Minhee; Kim, Suhwan

    2012-01-01

    We have implemented a tin-oxide-decorated carbon nanotube (CNT) network gas sensor system on a single die. We have also demonstrated the deposition of metallic tin on the CNT network, its subsequent oxidation in air, and the improvement of the lifetime of the sensors. The fabricated array of CNT sensors contains 128 sensor cells for added redundancy and increased accuracy. The read-out integrated circuit (ROIC) was combined with coarse and fine time-to-digital converters to extend its resolution in a power-efficient way. The ROIC is fabricated using a 0.35 μm CMOS process, and the whole sensor system consumes 30 mA at 5 V. The sensor system was successfully tested in the detection of ammonia gas at elevated temperatures.

  5. Adaptive Threshold Neural Spike Detector Using Stationary Wavelet Transform in CMOS.

    PubMed

    Yang, Yuning; Boling, C Sam; Kamboh, Awais M; Mason, Andrew J

    2015-11-01

    Spike detection is an essential first step in the analysis of neural recordings. Detection at the frontend eases the bandwidth requirement for wireless data transfer of multichannel recordings to extra-cranial processing units. In this work, a low power digital integrated spike detector based on the lifting stationary wavelet transform is presented and developed. By monitoring the standard deviation of wavelet coefficients, the proposed detector can adaptively set a threshold value online for each channel independently without requiring user intervention. A prototype 16-channel spike detector was designed and tested in an FPGA. The method enables spike detection with nearly 90% accuracy even when the signal-to-noise ratio is as low as 2. The design was mapped to 130 nm CMOS technology and shown to occupy 0.014 mm(2) of area and dissipate 1.7 μW of power per channel, making it suitable for implantable multichannel neural recording systems.

  6. Time-resolved Förster-resonance-energy-transfer DNA assay on an active CMOS microarray

    PubMed Central

    Schwartz, David Eric; Gong, Ping; Shepard, Kenneth L.

    2008-01-01

    We present an active oligonucleotide microarray platform for time-resolved Förster resonance energy transfer (TR-FRET) assays. In these assays, immobilized probe is labeled with a donor fluorophore and analyte target is labeled with a fluorescence quencher. Changes in the fluorescence decay lifetime of the donor are measured to determine the extent of hybridization. In this work, we demonstrate that TR-FRET assays have reduced sensitivity to variances in probe surface density compared with standard fluorescence-based microarray assays. Use of an active array substrate, fabricated in a standard complementary metal-oxide-semiconductor (CMOS) process, provides the additional benefits of reduced system complexity and cost. The array consists of 4096 independent single-photon avalanche diode (SPAD) pixel sites and features on-chip time-to-digital conversion. We demonstrate the functionality of our system by measuring a DNA target concentration series using TR-FRET with semiconductor quantum dot donors. PMID:18515059

  7. Simulation of SEU transients in CMOS ICs

    SciTech Connect

    Kaul, N.; Bhuva, B.L.; Kerns, S.E. )

    1991-12-01

    This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE.

  8. NSC 800, 8-bit CMOS microprocessor

    NASA Technical Reports Server (NTRS)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  9. A CMOS frontend chip for implantable neural recording with wide voltage supply range

    NASA Astrophysics Data System (ADS)

    Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

    2015-10-01

    A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

  10. High dynamic range CMOS-based mammography detector for FFDM and DBT

    NASA Astrophysics Data System (ADS)

    Peters, Inge M.; Smit, Chiel; Miller, James J.; Lomako, Andrey

    2016-03-01

    Digital Breast Tomosynthesis (DBT) requires excellent image quality in a dynamic mode at very low dose levels while Full Field Digital Mammography (FFDM) is a static imaging modality that requires high saturation dose levels. These opposing requirements can only be met by a dynamic detector with a high dynamic range. This paper will discuss a wafer-scale CMOS-based mammography detector with 49.5 μm pixels and a CsI scintillator. Excellent image quality is obtained for FFDM as well as DBT applications, comparing favorably with a-Se detectors that dominate the X-ray mammography market today. The typical dynamic range of a mammography detector is not high enough to accommodate both the low noise and the high saturation dose requirements for DBT and FFDM applications, respectively. An approach based on gain switching does not provide the signal-to-noise benefits in the low-dose DBT conditions. The solution to this is to add frame summing functionality to the detector. In one X-ray pulse several image frames will be acquired and summed. The requirements to implement this into a detector are low noise levels, high frame rates and low lag performance, all of which are unique characteristics of CMOS detectors. Results are presented to prove that excellent image quality is achieved, using a single detector for both DBT as well as FFDM dose conditions. This method of frame summing gave the opportunity to optimize the detector noise and saturation level for DBT applications, to achieve high DQE level at low dose, without compromising the FFDM performance.

  11. A theoretical investigation of spectra utilization for a CMOS based indirect detector for dual energy applications

    NASA Astrophysics Data System (ADS)

    Kalyvas, N.; Martini, N.; Koukou, V.; Michail, C.; Sotiropoulou, P.; Valais, I.; Kandarakis, I.; Fountos, G.

    2015-09-01

    Dual Energy imaging is a promising method for visualizing masses and microcalcifications in digital mammography. Currently commercially available detectors may be suitable for dual energy mammographic applications. The scope of this work was to theoretically examine the performance of the Radeye CMOS digital indirect detector under three low- and high-energy spectral pairs. The detector was modeled through the linear system theory. The pixel size was equal to 22.5μm and the phosphor material of the detector was a 33.9 mg/cm2 Gd2O2S:Tb phosphor screen. The examined spectral pairs were (i) a 40kV W/Ag (0.01cm) and a 70kV W/Cu (0.1cm) target/filter combinations, (ii) a 40kV W/Cd (0.013cm) and a 70kV W/Cu (0.1cm) target/filter combinations and (iii) a 40kV W/Pd (0.008cm) and a 70kV W/Cu (0.1cm) target/filter combinations. For each combination the Detective Quantum Efficiency (DQE), showing the signal to noise ratio transfer, the detector optical gain (DOG), showing the sensitivity of the detector and the coefficient of variation (CV) of the detector output signal were calculated. The second combination exhibited slightly higher DOG (326 photons per X-ray) and lower CV (0.755%) values. In terms of electron output from the RadEye CMOS, the first two combinations demonstrated comparable DQE values; however the second combination provided an increase of 6.5% in the electron output.

  12. Digital Preservation.

    ERIC Educational Resources Information Center

    Yakel, Elizabeth

    2001-01-01

    Reviews research on digital preservation issues, including born-digital and digitally recreated documents. Discusses electronic records research; metadata and other standards; electronic mail; Web-based documents; moving images media; selection of materials for digitization, including primary sources; administrative issues; media stability…

  13. X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

    NASA Astrophysics Data System (ADS)

    Cha, Bo Kyung; Jeon, Seongchae; Seo, Chang-Woo

    2016-09-01

    This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 μm 1-poly/4-metal CMOS process. The pixel size is 100 μm×100 μm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd2O2S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

  14. Real-time fluorescence lifetime actuation for cell sorting using a CMOS SPAD silicon photomultiplier.

    PubMed

    Rocca, Francescopaolo Mattioli Della; Nedbal, Jakub; Tyndall, David; Krstajić, Nikola; Li, David Day-Uei; Ameer-Beg, Simon M; Henderson, Robert K

    2016-02-15

    Time-correlated single photon counting (TCSPC) is a fundamental fluorescence lifetime measurement technique offering high signal to noise ratio (SNR). However, its requirement for complex software algorithms for histogram processing restricts throughput in flow cytometers and prevents on-the-fly sorting of cells. We present a single-point digital silicon photomultiplier (SiPM) detector accomplishing real-time fluorescence lifetime-activated actuation targeting cell sorting applications in flow cytometry. The sensor also achieves burst-integrated fluorescence lifetime (BIFL) detection by TCSPC. The SiPM is a single-chip complementary metal-oxide-semiconductor (CMOS) sensor employing a 32×32 single-photon avalanche diode (SPAD) array and eight pairs of time-interleaved time to digital converters (TI-TDCs) with a 50 ps minimum timing resolution. The sensor's pile-up resistant embedded center of mass method (CMM) processor accomplishes low-latency measurement and thresholding of fluorescence lifetime. A digital control signal is generated with a 16.6 μs latency for cell sorter actuation allowing a maximum cell throughput of 60,000 cells per second and an error rate of 0.6%. PMID:26872160

  15. Development and characterization of CMOS avalanche photodiode arrays

    NASA Astrophysics Data System (ADS)

    Lawrence, William G.; Christian, James F.; Augustine, Frank L.; Squillante, Michael R.; Entine, Gerald

    2005-04-01

    Avalanche photodiode (APD) arrays fabricated by using complementary metal-oxide-semiconductor (CMOS) fabrication technology offer the possibility of combining these high sensitivity detectors with cost effective, on-board, complementary circuitry. Using CMOS techniques, Radiation Monitoring Devices has developed prototype pixels with active diameters ranging from 5 to 60 microns and with measured quantum efficiencies of up to 65%. The prototype CMOS APD pixel designs support both proportional and Geiger modes of photo-detection. When operating in Geiger mode, these APD"s act as single-optical-photon-counting detectors that can be used for time-resolved measurements under signal-starved conditions. We have also designed and fabricated CMOS chips that contain not only the APD pixels, but also associated circuitry for both actively and passively quenching the self-propagating Geiger avalanche. This report presents the noise and timing performance for the prototype CMOS APD pixels in both the proportional and Geiger modes of operation. It compares the quantum efficiency and dark-count rate of different pixel designs as a function of the applied bias and presents a discussion of the maximum count rates that is obtained with each of the two types of quenching circuits for operating the pixel in Geiger mode. Preliminary data on the application of the APD pixels to laser ranging and fluorescent lifetime measurement is also presented.

  16. Improved Space Object Observation Techniques Using CMOS Detectors

    NASA Astrophysics Data System (ADS)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  17. Radiation tolerant back biased CMOS VLSI

    NASA Technical Reports Server (NTRS)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  18. Design and characterization of avalanche photodiodes in submicron CMOS technologies

    NASA Astrophysics Data System (ADS)

    Pancheri, L.; Bendib, T.; Dalla Betta, G.-F.; Stoppa, D.

    2014-03-01

    The fabrication of Avalanche Photodiodes (APDs) in CMOS processes can be exploited in several application domains, including telecommunications, time-resolved optical detection and scintillation detection. CMOS integration allows the realization of systems with a high degree of parallelization which are competitive with hybrid solutions in terms of cost and complexity. In this work, we present a linear-mode APD fabricated in a 0.15μm process, and report its gain and noise characterization. The experimental observations can be accurately predicted using Hayat dead-space noise model. Device simulations based on dead-space model are then used to discuss the current status and the perspectives for the integration of high-performance low-noise devices in standard CMOS processes.

  19. Fabrication of the planar angular rotator using the CMOS process

    NASA Astrophysics Data System (ADS)

    Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

    2002-05-01

    In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

  20. Scaling CMOS photonics transceivers beyond 100 Gb/s

    NASA Astrophysics Data System (ADS)

    Mekis, Attila; Abdalla, Sherif; De Dobbelaere, Peter M.; Foltz, Dennis; Gloeckner, Steffen; Hovey, Steven; Jackson, Steven; Liang, Yi; Mack, Michael; Masini, Gianlorenzo; Novais, Rafaela; Peterson, Mark; Pinguet, Thierry; Sahni, Subal; Schramm, Jeff; Sharp, Michael; Song, Daniel; Welch, Brian P.; Yokoyama, Kosei; Yu, Shuhuan

    2012-01-01

    We report on the performance of an integrated four-channel parallel optical transceiver built in a CMOS photonics process, operating at 28 Gb/s per channel. The optical engine of the transceiver comprises a single silicon die and a hybrid integrated DFB laser. The silicon die contains the all functionalities needed for an optical transceiver: transmitter and receiver optics, electrical driver, receiver and control circuits. We also describe the CMOS photonics platform used to build such transceiver device, which consists of: an optically enabled CMOS process, a photonic device library, and a design infrastructure that is modeled after standard circuit design tools. We discuss how this platform can scale to higher speeds and channel counts.

  1. High-speed polysilicon CMOS photodetector for telecom and datacom

    NASA Astrophysics Data System (ADS)

    Atabaki, Amir H.; Meng, Huaiyu; Alloatti, Luca; Mehta, Karan K.; Ram, Rajeev J.

    2016-09-01

    Absorption by mid-bandgap states in polysilicon or heavily implanted silicon has been previously utilized to implement guided-wave infrared photodetectors in CMOS compatible photonic platforms. Here, we demonstrate a resonant guided-wave photodetector based on the polysilicon layer that is used for the transistor gate in a microelectronic SOI CMOS process without any change to the foundry process flow ("zero-change" CMOS). Through a combination of doping mask layers, a lateral pn junction diode in the polysilicon is demonstrated with a strong electric field to enable efficient photo-carrier extraction and high-speed operation. This photodetector has a responsivity of more than 0.14 A/W from 1300 to 1600 nm, a 10 GHz bandwidth, and 80 nA dark current at 15 V reverse bias.

  2. Operation and biasing for single device equivalent to CMOS

    DOEpatents

    Welch, James D.

    2001-01-01

    Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

  3. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as...

  4. Measuring trunk orientation with a CMOS camera: feasibility and accuracy.

    PubMed

    Gissot, A-S; Barbieri, G; Iacobelis, M; Paindavoine, M; Pérennou, D

    2007-10-01

    The purpose of this study was to develop and validate a new tool to objectively quantify trunk orientation at the bedside, especially dedicated to the measurement of the lateropulsion in acute and subacute stroke patients. We developed software to analyze 2D movement with a CMOS camera (Logitech Quickcam Pro 4000) and to calculate the orientation of a segment defined by two color markers. First, the accuracy, reproducibility and noise when measuring segment orientations were evaluated with the CMOS camera placed in different positions, and second trunk orientation was measured in static and in dynamic conditions both with a CMOS camera and with a gold standard 3D video system (BTS SMART-e). Results showed that the measurement was accurate (mean error=0.05+/-0.12 degrees), reproducible (S.D. over five measurements=0.005 degrees ) and steady (noise signal=0.02 degrees ). The data obtained with the CMOS camera were highly correlated with those obtained with the 3D video system both in static and in dynamic conditions. However, the CMOS camera must be relatively well centered on the measured segment to avoid error due to image distortion. The parallax error was negligible. In conclusion, this could be an important step in the postural assessment of acute and subacute stroke patients. The CMOS camera, a simple, portable, compact, low-cost, commercially available apparatus is the first tool to objectively quantify lateropulsion at the bedside. This method could also support the development of a rehabilitation program for trunk orientation based on biofeedback using the real-time signal provided by the device.

  5. Modifications in CMOS Dynamic Logic Style: A Review Paper

    NASA Astrophysics Data System (ADS)

    Meher, Preetisudha; Mahapatra, Kamalakanta

    2015-12-01

    Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper, an overview and classification of these techniques are first presented and then compared according to their performance.

  6. CMOS Compatible Integrated Thermoelectric Sensors Using Novel Frontside Micromachining

    NASA Astrophysics Data System (ADS)

    Socher, E.; Bochobza-Degani, O.; Nemirovsky, Y.

    2000-12-01

    CMOS compatible integrated thermoelectric sensors were designed and realized using a standard CMOS process and frontside RIE micromachining. The suspended structures were designed to have a spiral structure that enhances the thermal resistance and isolation of the sensor. Using dry RIE frontside micromachining for the release of the sensors allows better yield in realization of sensitive and smaller sensor pixels. Measured results of sensors used for IR detection show NEP's down to 0.4 nW/√Hz and response times down to 3 msec in 70*70 μm2 pixels.

  7. New Multiple-Times Programmable CMOS ROM Cell

    NASA Astrophysics Data System (ADS)

    Chung, In-Young; Jeong, Seong Yeol; Seo, Sung Min; Lee, Myungjin; Jang, Taesu; Cha, Seon-Yong; Park, Young June

    New concept of CMOS nonvolatile memory is presented with demonstration of cell implementations. The memory cell, which is a comparator basically, makes use of comparator offset for storage quantity and the FN stress phenomena for cell programming. We also propose the stress-packet operation which is the relevant programming method to finely control the offset of the memory cell. The memory cell is multiple-time programmable while it is implemented in a standard CMOS process. We fabricated the memory cell arrays of the latch comparator and demonstrated that it is rewritten several times. We also investigated the reliability of cell data retention by monitoring programmed offsets for several months.

  8. CMOS-compatible photonic devices for single-photon generation

    NASA Astrophysics Data System (ADS)

    Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

    2016-09-01

    Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  9. Monolithic 3D CMOS Using Layered Semiconductors.

    PubMed

    Sachid, Angada B; Tosun, Mahmut; Desai, Sujay B; Hsu, Ching-Yi; Lien, Der-Hsien; Madhvapathy, Surabhi R; Chen, Yu-Ze; Hettick, Mark; Kang, Jeong Seuk; Zeng, Yuping; He, Jr-Hau; Chang, Edward Yi; Chueh, Yu-Lun; Javey, Ali; Hu, Chenming

    2016-04-01

    Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported. A variety of digital and analog circuits are implemented on two sequentially integrated layers of devices. Inverter circuit operation at an ultralow supply voltage of 150 mV is achieved, paving the way to high-density, ultralow-voltage, and ultralow-power applications. PMID:26833783

  10. Rolling Shutter Effect aberration compensation in Digital Holographic Microscopy

    NASA Astrophysics Data System (ADS)

    Monaldi, Andrea C.; Romero, Gladis G.; Cabrera, Carlos M.; Blanc, Adriana V.; Alanís, Elvio E.

    2016-05-01

    Due to the sequential-readout nature of most CMOS sensors, each row of the sensor array is exposed at a different time, resulting in the so-called rolling shutter effect that induces geometric distortion to the image if the video camera or the object moves during image acquisition. Particularly in digital holograms recording, while the sensor captures progressively each row of the hologram, interferometric fringes can oscillate due to external vibrations and/or noises even when the object under study remains motionless. The sensor records each hologram row in different instants of these disturbances. As a final effect, phase information is corrupted, distorting the reconstructed holograms quality. We present a fast and simple method for compensating this effect based on image processing tools. The method is exemplified by holograms of microscopic biological static objects. Results encourage incorporating CMOS sensors over CCD in Digital Holographic Microscopy due to a better resolution and less expensive benefits.

  11. Comparative study of a wireless digital system and 2 PSP digital systems on proximal caries detection and pixel values.

    PubMed

    dos Anjos Pontual, Andrea; de Melo, Daniela Pita; Pontual, Maria Luiza dos Anjos; de Almeida, Solange Maria; Haiter-Neto, Francisco

    2013-01-01

    This study compared the radiographic image quality of 2 photostimulable phosphor (PSP) plate systems with a radiographic system against a complementary metal oxide silicon (CMOS) system. Using the 3 digital systems, 160 approximal surfaces were radiographed under standardized conditions. Using a 5-point scale, 6 observers scored the resulting images for the presence of caries. The presence of caries was validated histologically, and the image receptors were evaluated using receiver operating characteristic curve analysis. The digital systems were used to take radiographs of an aluminum step wedge for objective analysis with pixel density measurements. The mean pixel values were analyzed statistically using the Kruskal-Wallis test and Dunn multiple comparison test (P < 0.01). The performance of the new CMOS system was comparable to the PSP plate systems and radiographic film.

  12. CMOS correlated-double-sampling and hold structure based on novel dynamic source-follower for large format infrared focal-plane-array

    NASA Astrophysics Data System (ADS)

    Zhang, Zhi; Yuan, Xianghui; Huang, Youshu

    2003-07-01

    In this paper, a CMOS correlated double sampling and hold (CDSH) structure based on novel dynamic source follower for large format infrared focal-plane array (IRFPA) is proposed. The primary noise (fixed-pattern noise (FPN) and KTC reset noise, etc) of the CMOS image sensor is reduced, through the improved CDSH structure based on the novel dynamic source follower, and all pixels in the selected row can start integrating simultaneously; the readout process happens in the next row selection time, which can increase the frame frequency, and the output waveform is boxcar, which is easy-to-realize analog/digital conversion. SPICE simulation results have shown that the proposed improved CDSH structure can achieve the advantages of simple driving signal, large dynamic range in large format IRFPA with low power consumption.

  13. A powerful ethernet interface module for digital camera control

    NASA Astrophysics Data System (ADS)

    Amato, Stephen M.; Geary, John C.

    2012-09-01

    We have found a commercially-available ethernet interface module with sufficient on-board resources to largely handle all timing generation tasks required by digital imaging systems found in astronomy. In addition to providing a high-bandwidth ethernet interface to the controller, it can largely replace the need for special-purpose timing circuitry. Examples for use with both CCD and CMOS imagers are provided.

  14. Digital Citizenship

    ERIC Educational Resources Information Center

    Isman, Aytekin; Canan Gungoren, Ozlem

    2014-01-01

    Era in which we live is known and referred as digital age.In this age technology is rapidly changed and developed. In light of these technological advances in 21st century, schools have the responsibility of training "digital citizen" as well as a good citizen. Digital citizens must have extensive skills, knowledge, Internet and …

  15. Low-Power Radio-Frequency SiGe Analog-to-Digital Converter

    NASA Technical Reports Server (NTRS)

    Thompson, Willie L, II; Hall, Wesley G.; Piepmeier, Jeffrey R.; Johnson-Bey, Charles T.

    2003-01-01

    A low-power, radio-frequency analog-to-digital converter (RF-ADC) for soil moisture remote sensing was designed and fabricated. The RF-ADC is the fundamental component used in a direct-sampling digital radiometer, which is proposed to minimize the power dissipation and system complexity for synthetic thinned array radiometer. The circuit was implemented using 0.8 micron 35-GHz silicon germanium BiCMOS technology. The total power dissipation was 222 mW.

  16. Single Event Upset Behavior of CMOS Static RAM Cells

    NASA Technical Reports Server (NTRS)

    Lieneweg, Udo; Jeppson, Kjell O.; Buehler, Martin G.

    1993-01-01

    An improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.

  17. CCD AND PIN-CMOS DEVELOPMENTS FOR LARGE OPTICAL TELESCOPE.

    SciTech Connect

    RADEKA, V.

    2006-04-03

    Higher quantum efficiency in near-IR, narrower point spread function and higher readout speed than with conventional sensors have been receiving increased emphasis in the development of CCDs and silicon PIN-CMOS sensors for use in large optical telescopes. Some key aspects in the development of such devices are reviewed.

  18. CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics

    NASA Technical Reports Server (NTRS)

    Yeh, Penshu; Maki, Gary

    2007-01-01

    Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

  19. Effects Of Dose Rates On Radiation Damage In CMOS Parts

    NASA Technical Reports Server (NTRS)

    Goben, Charles A.; Coss, James R.; Price, William E.

    1990-01-01

    Report describes measurements of effects of ionizing-radiation dose rate on consequent damage to complementary metal oxide/semiconductor (CMOS) electronic devices. Depending on irradiation time and degree of annealing, survivability of devices in outer space, or after explosion of nuclear weapons, enhanced. Annealing involving recovery beyond pre-irradiation conditions (rebound) detrimental. Damage more severe at lower dose rates.

  20. Characterisation of a CMOS charge transfer device for TDI imaging

    NASA Astrophysics Data System (ADS)

    Rushton, J.; Holland, A.; Stefanov, K.; Mayer, F.

    2015-03-01

    The performance of a prototype true charge transfer imaging sensor in CMOS is investigated. The finished device is destined for use in TDI applications, especially Earth-observation, and to this end radiation tolerance must be investigated. Before this, complete characterisation is required. This work starts by looking at charge transfer inefficiency and then investigates responsivity using mean-variance techniques.

  1. Fabrication and Characterization of CMOS-MEMS Thermoelectric Micro Generators

    PubMed Central

    Kao, Pin-Hsu; Shih, Po-Jen; Dai, Ching-Liang; Liu, Mao-Chen

    2010-01-01

    This work presents a thermoelectric micro generator fabricated by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-CMOS process. The micro generator is composed of 24 thermocouples in series. Each thermocouple is constructed by p-type and n-type polysilicon strips. The output power of the generator depends on the temperature difference between the hot and cold parts in the thermocouples. In order to prevent heat-receiving in the cold part in the thermocouples, the cold part is covered with a silicon dioxide layer with low thermal conductivity to insulate the heat source. The hot part of the thermocouples is suspended and connected to an aluminum plate, to increases the heat-receiving area in the hot part. The generator requires a post-CMOS process to release the suspended structures. The post-CMOS process uses an anisotropic dry etching to remove the oxide sacrificial layer and an isotropic dry etching to etch the silicon substrate. Experimental results show that the micro generator has an output voltage of 67 μV at the temperature difference of 1 K. PMID:22205869

  2. CMOS VLSI Layout and Verification of a SIMD Computer

    NASA Technical Reports Server (NTRS)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  3. CMOS-compatible LVOF-based visible microspectrometer

    NASA Astrophysics Data System (ADS)

    Emadi, Arvin; Wu, Huaiwen; de Graaf, Ger; Wolffenbuttel, Reinoud F.

    2010-04-01

    This paper reports on a CMOS-Compatible Linear Variable Optical Filter (LVOF) visible micro-spectrometer. The CMOS-compatible post process for fabrication of the LVOF has been used for integration of the LVOF with a CMOS chip containing a 128-element photodiode array and readout circuitry. Fabrication of LVOF involves a process for fabrication of very small taper angles, ranging from 0.001° to 0.1°, in SiO2. These layers can be fabricated flexibly in a resist layer by just one lithography step and a subsequent reflow process. The 3D pattern of the resist structures is subsequently transferred into SiO2 by appropriate etching. Complete LVOF fabrication involves CMOS-compatible deposition of a lower dielectric mirror using a stack of dielectrics on the wafer, tapered layer formation and deposition of the top dielectric mirror. The LVOF has been optimized for 580 nm - 720 nm spectral operating range and has also been mounted on a CCD camera for characterization. The design of LVOF micro-spectrometer, the fabrication and characterization results are presented.

  4. Optical and noise performance of CMOS solid-state photomultipliers

    NASA Astrophysics Data System (ADS)

    Chen, Xiao Jie; Johnson, Erik B.; Staples, Christopher J.; Chapman, Eric; Alberghini, Guy; Christian, James F.

    2010-08-01

    Solid-state photomultipliers (SSPM) are photodetectors composed of avalanche photodiode pixel arrays operating in Geiger mode (biased above diode breakdown voltage). They are built using CMOS technology and can be used in a variety of applications in high energy and nuclear physics, medical imaging and homeland security related areas. The high gain and low cost associated with the SSPM makes it an attractive alternative to existing photodetectors such as the photomultiplier tube (PMT). The capability of integrating CMOS on-chip readout circuitry on the same substrate as the SSPM also provides a compact and low-power-consumption solution to photodetector applications with stringent area and power requirements. The optical performance of the SSPM, specifically the detection and quantum efficiencies, can depend on the geometry and the doping profile associated with each photodiode pixel. The noise associated with the SSPM not only includes dark noise from each pixel, but also consists of excess noise terms due to after pulsing and inter-pixel cross talk. The magnitude of the excess noise terms can depend on biasing conditions, temperature, as well as pixel and inter-pixel dimensions. We present the optical and noise performance of SSPMs fabricated in a conventional CMOS process, and demonstrate the dependence of the SSPM performance on pixel/inter-pixel geometry, doping profile, temperature, as well as bias conditions. The continuing development of CMOS SSPM technology demonstrated here shows that low cost and high performance solid state photodetectors are viable solutions for many existing and future optical detection applications.

  5. Planar CMOS analog SiPMs: design, modeling, and characterization

    NASA Astrophysics Data System (ADS)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-11-01

    Silicon photomultipliers (SiPMs) are large area detectors consisting of an array of single-photon-sensitive microcells, which make SiPMs extremely attractive to substitute the photomultiplier tubes in many applications. We present the design, fabrication, and characterization of analog SiPMs in standard planar 0.35 μm CMOS technology, with about 1 mm × 1 mm total area and different kinds of microcells, based on single-photon avalanche diodes with 30 μm diameter reaching 21.0% fill-factor (FF), 50 μm diameter (FF = 58.3%) or 50 μm square active area with rounded corner of 5 μm radius (FF = 73.7%). We also developed the electrical SPICE model for CMOS SiPMs. Our CMOS SiPMs have 25 V breakdown voltage, in line with most commercial SiPMs and higher gain (8.8 × 106, 13.2 × 106, and 15.0 × 106, respectively). Although dark count rate density is slightly higher than state-of-the-art analog SiPMs, the proposed standard CMOS processing opens the feasibility of integration with active electronics, for switching hot pixels off, drastically reducing the overall dark count rate, or for further on-chip processing.

  6. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    NASA Astrophysics Data System (ADS)

    Rescigno, R.; Finck, Ch.; Juliani, D.; Baudot, J.; Dauvergne, D.; Dedes, G.; Krimmer, J.; Ray, C.; Reithinger, V.; Rousseau, M.; Testa, E.; Winter, M.

    2014-03-01

    Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  7. Attributes and drawbacks of submicron CMOS for IR FPA readouts

    NASA Astrophysics Data System (ADS)

    Kozlowski, L. J.

    1998-09-01

    The availability of submicron CMOS has enabled the development of shingle-chip IR cameras having performance capabilities and on-chip functions which were previously impossible. Sensor designers are, however, encoutering and overcoming several challanges including steadily decreasing operating voltage.

  8. Performance of CMOS ternary full adder at liquid nitrogen temperature

    NASA Astrophysics Data System (ADS)

    Srivastava, A.; Venkatapathy, K.

    We have designed, implemented and studied the performance at liquid nitrogen temperature (77 K) of a CMOS ternary full adder and its building blocks, the simple ternary inverter (STI), positive ternary inverter (PTI) and negative ternary inverter (NTI), and compared the corresponding performance at room temperature (300 K). The ternary full adder has been fabricated in 2 μm, n-well CMOS through MOSIS. In a ternary full adder, the basic building blocks, the PTI and NTI, have been developed using combinations of a CMOS inverter and transmission gate(s). There is close agreement between the simulated and measured voltage transfer characteristics and noise margins of ternary-valued devices. The measured transient times for the NTI, PTI and ternary full adder at 77 K show an improvement by a factor of ≈1.5-2.5 over the corresponding values at 300 K. The present design does not use linear resistors and depletion-mode MOSFETs to implement the ternary full adder and its building blocks, and is fully compatible with current CMOS technology.

  9. Direct readout of gaseous detectors with tiled CMOS circuits

    NASA Astrophysics Data System (ADS)

    Visschers, J. L.; Blanco Carballo, V.; Chefdeville, M.; Colas, P.; van der Graaf, H.; Schmitz, J.; Smits, S.; Timmermans, J.

    2007-03-01

    A coordinated design effort is underway, exploring the three-dimensional direct readout of gaseous detectors by an anode plate equipped with a tiled array of many CMOS pixel readout ASICs, having amplification grids integrated on their topsides and being contacted on their backside.

  10. Distinct development patterns of c-mos protooncogene expression in female and male mouse germ cells

    SciTech Connect

    Mutter, G.L.; Wolgemuth, D.J.

    1987-08-01

    The protooncogene c-mos is expressed in murine reproductive tissues, producing transcripts of 1.7 and 1.4 kilobases in testis and ovary, respectively. In situ hybridization analysis of c-mos expression in histological sections of mouse ovaries revealed that oocytes are the predominant if not exclusive source of c-mos transcripts. /sup 35/S- or /sup 32/P-labelled RNA probes were transcribed. c-mos transcripts accumulate in growing oocytes, increasing 40- to 90-fold during oocyte and follicular development. c-mos transcripts were also detected in male germ cells and are most abundant after the cells have entered the haploid stage of spermatogenesis. This developmentally regulated pattern of c-mos expression in oocytes and spermatogenic cells suggest that the c-mos gene product may have a function in normal germ-cell differentiation or early embryogenesis.

  11. Hybrid CMOS SiPIN detectors as astronomical imagers

    NASA Astrophysics Data System (ADS)

    Simms, Lance Michael

    Charge Coupled Devices (CCDs) have dominated optical and x-ray astronomy since their inception in 1969. Only recently, through improvements in design and fabrication methods, have imagers that use Complimentary Metal Oxide Semiconductor (CMOS) technology gained ground on CCDs in scientific imaging. We are now in the midst of an era where astronomers might begin to design optical telescope cameras that employ CMOS imagers. The first three chapters of this dissertation are primarily composed of introductory material. In them, we discuss the potential advantages that CMOS imagers offer over CCDs in astronomical applications. We compare the two technologies in terms of the standard metrics used to evaluate and compare scientific imagers: dark current, read noise, linearity, etc. We also discuss novel features of CMOS devices and the benefits they offer to astronomy. In particular, we focus on a specific kind of hybrid CMOS sensor that uses Silicon PIN photodiodes to detect optical light in order to overcome deficiencies of commercial CMOS sensors. The remaining four chapters focus on a specific type of hybrid CMOS Silicon PIN sensor: the Teledyne Hybrid Visible Silicon PIN Imager (HyViSI). In chapters four and five, results from testing HyViSI detectors in the laboratory and at the Kitt Peak 2.1m telescope are presented. We present our laboratory measurements of the standard detector metrics for a number of HyViSI devices, ranging from 1k×1k to 4k×4k format. We also include a description of the SIDECAR readout circuit that was used to control the detectors. We then show how they performed at the telescope in terms of photometry, astrometry, variability measurement, and telescope focusing and guiding. Lastly, in the final two chapters we present results on detector artifacts such as pixel crosstalk, electronic crosstalk, and image persistence. One form of pixel crosstalk that has not been discussed elsewhere in the literature, which we refer to as Interpixel Charge

  12. Design of a 3D-IC multi-resolution digital pixel sensor

    NASA Astrophysics Data System (ADS)

    Brochard, N.; Nebhen, J.; Dubois, J.; Ginhac, D.

    2016-04-01

    This paper presents a digital pixel sensor (DPS) integrating a sigma-delta analog-to-digital converter (ADC) at pixel level. The digital pixel includes a photodiode, a delta-sigma modulation and a digital decimation filter. It features adaptive dynamic range and multiple resolutions (up to 10-bit) with a high linearity. A specific row decoder and column decoder are also designed to permit to read a specific pixel chosen in the matrix and its neighborhood of 4 x 4. Finally, a complete design with the CMOS 130 nm 3D-IC FaStack Tezzaron technology is also described, revealing a high fill-factor of about 80%.

  13. The research on binocular stereo video imaging and display system based on low-light CMOS

    NASA Astrophysics Data System (ADS)

    Xie, Ruobing; Li, Li; Jin, Weiqi; Guo, Hong

    2015-10-01

    It is prevalent for the low-light night-vision helmet to equip the binocular viewer with image intensifiers. Such equipment can not only acquire night vision ability, but also obtain the sense of stereo vision to achieve better perception and understanding of the visual field. However, since the image intensifier is for direct-observation, it is difficult to apply the modern image processing technology. As a result, developing digital video technology in night vision is of great significance. In this paper, we design a low-light night-vision helmet with digital imaging device. It consists of three parts: a set of two low-illumination CMOS cameras, a binocular OLED micro display and an image processing PCB. Stereopsis is achieved through the binocular OLED micro display. We choose Speed-Up Robust Feature (SURF) algorithm for image registration. Based on the image matching information and the cameras' calibration parameters, disparity can be calculated in real-time. We then elaborately derive the constraints of binocular stereo display. The sense of stereo vision can be obtained by dynamically adjusting the content of the binocular OLED micro display. There is sufficient space for function extensions in our system. The performance of this low-light night-vision helmet can be further enhanced in combination with The HDR technology and image fusion technology, etc.

  14. A low-power time-domain VCO-based ADC in 65 nm CMOS

    NASA Astrophysics Data System (ADS)

    Chenluan, Wang; Shengxi, Diao; Fujiang, Lin

    2014-10-01

    A low-power, high-FoM (figure of merit), time-domain VCO (voltage controlled oscillator)-based ADC (analog-to-digital converter) in 65 nm CMOS technology is proposed. An asynchronous sigma—delta modulator (ASDM) is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR (exclusive-OR) gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonic-distortion-cancellation technique to its transconductance stage, which increases the SNDR (signal to noise and distortion ratio) performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO's V—F (voltage to frequency) conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADC's low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. dB/54.3 dB in the 8 MHz bandwidth, while consuming 2.8 mW. The FoM of the proposed ADC is a 334 fJ/conv-step.

  15. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    PubMed Central

    He, Diwei; Morgan, Stephen P.; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R.

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

  16. Single InAs/GaSb nanowire low-power CMOS inverter.

    PubMed

    Dey, Anil W; Svensson, Johannes; Borg, B Mattias; Ek, Martin; Wernersson, Lars-Erik

    2012-11-14

    III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

  17. Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

    PubMed

    He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

    2013-09-18

    The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

  18. Laser Doppler Blood Flow Imaging Using a CMOS Imaging Sensor with On-Chip Signal Processing

    PubMed Central

    He, Diwei; Nguyen, Hoang C.; Hayes-Gill, Barrie R.; Zhu, Yiqun; Crowe, John A.; Gill, Cally; Clough, Geraldine F.; Morgan, Stephen P.

    2013-01-01

    The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue. PMID:24051525

  19. Digital Natives or Digital Tribes?

    ERIC Educational Resources Information Center

    Watson, Ian Robert

    2013-01-01

    This research builds upon the discourse surrounding digital natives. A literature review into the digital native phenomena was undertaken and found that researchers are beginning to identify the digital native as not one cohesive group but of individuals influenced by other factors. Primary research by means of questionnaire survey of technologies…

  20. Commercial CMOS image sensors as X-ray imagers and particle beam monitors

    NASA Astrophysics Data System (ADS)

    Castoldi, A.; Guazzoni, C.; Maffessanti, S.; Montemurro, G. V.; Carraresi, L.

    2015-01-01

    CMOS image sensors are widely used in several applications such as mobile handsets webcams and digital cameras among others. Furthermore they are available across a wide range of resolutions with excellent spectral and chromatic responses. In order to fulfill the need of cheap systems as beam monitors and high resolution image sensors for scientific applications we exploited the possibility of using commercial CMOS image sensors as X-rays and proton detectors. Two different sensors have been mounted and tested. An Aptina MT9v034, featuring 752 × 480 pixels, 6μm × 6μm pixel size has been mounted and successfully tested as bi-dimensional beam profile monitor, able to take pictures of the incoming proton bunches at the DeFEL beamline (1-6 MeV pulsed proton beam) of the LaBeC of INFN in Florence. The naked sensor is able to successfully detect the interactions of the single protons. The sensor point-spread-function (PSF) has been qualified with 1MeV protons and is equal to one pixel (6 mm) r.m.s. in both directions. A second sensor MT9M032, featuring 1472 × 1096 pixels, 2.2 × 2.2 μm pixel size has been mounted on a dedicated board as high-resolution imager to be used in X-ray imaging experiments with table-top generators. In order to ease and simplify the data transfer and the image acquisition the system is controlled by a dedicated micro-processor board (DM3730 1GHz SoC ARM Cortex-A8) on which a modified LINUX kernel has been implemented. The paper presents the architecture of the sensor systems and the results of the experimental measurements.

  1. Prototype CMOS SSPM solar particle dosimeter with tissue-equivalent sensor

    NASA Astrophysics Data System (ADS)

    Stapels, C. J.; Johnson, E. B.; Mukhopadhyay, S.; Chapman, E. C.; Christian, J. F.; Benton, Eric

    2009-08-01

    A dosimeter-on-a-chip (DoseChip) comprised of a tissue-equivalent scintillator coupled to a solid-state photomultiplier (SSPM) built using CMOS (complementary metal-oxide semiconductor) technology represents an ideal technology for a space-worthy, real-time solar-particle monitor for astronauts. It provides a tissue-equivalent response to the relevant energies and types of radiation for Low-Earth Orbit (LEO) and interplanetary space flight to the moon or Mars. The DoseChip will complement the existing Crew Passive Dosimeters by providing real-time dosimetry and as an alarming monitor for solar particle events (SPEs).[1] A prototype of the DoseChip, comprised of a 3 x 3 x 3 mm3 cube of BC-430 plastic scintillator coupled to a 2000-pixel SSPM, has successfully demonstrated response to protons at the NASA Space Radiation Laboratory (NSRL) at Brookhaven National Laboratory and at the HIMAC facility in Japan. The dynamic range of the dose has been verified over four orders of magnitude for particles with LET ranging from 0.2 keV/μm to 200 keV/μm, which includes 1-GeV protons to 420-MeV/n Fe nuclei. To exploit the benefits of the CMOS SSPM, we have developed our first autonomous prototype using the DoseChip. An analog circuit is used to process the signals from the SSPM, and an on-board microprocessor is used to digitize and store the pulse height information. Power is distributed over the device from a single dual voltage supply through various regulators and boost converters to appropriate supply voltages to each of the components.

  2. CMOS Imaging of Pin-Printed Xerogel-Based Luminescent Sensor Microarrays.

    PubMed

    Yao, Lei; Yung, Ka Yi; Khan, Rifat; Chodavarapu, Vamsy P; Bright, Frank V

    2010-12-01

    We present the design and implementation of a luminescence-based miniaturized multisensor system using pin-printed xerogel materials which act as host media for chemical recognition elements. We developed a CMOS imager integrated circuit (IC) to image the luminescence response of the xerogel-based sensor array. The imager IC uses a 26 × 20 (520 elements) array of active pixel sensors and each active pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. The imager includes a correlated double sampling circuit and pixel address/digital control circuit; the image data is read-out as coded serial signal. The sensor system uses a light-emitting diode (LED) to excite the target analyte responsive luminophores doped within discrete xerogel-based sensor elements. As a prototype, we developed a 4 × 4 (16 elements) array of oxygen (O2) sensors. Each group of 4 sensor elements in the array (arranged in a row) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a strategic mix of two oxygen sensitive luminophores ([Ru(dpp)3](2+) and ([Ru(bpy)3](2+)) in each pin-printed xerogel sensor element. The CMOS imager consumes an average power of 8 mW operating at 1 kHz sampling frequency driven at 5 V. The developed prototype system demonstrates a low cost and miniaturized luminescence multisensor system. PMID:24489484

  3. A novel multi-actuation CMOS RF MEMS switch

    NASA Astrophysics Data System (ADS)

    Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

    2008-12-01

    This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

  4. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    NASA Astrophysics Data System (ADS)

    Turchetta, R.; French, M.; Manolopoulos, S.; Tyndel, M.; Allport, P.; Bates, R.; O'Shea, V.; Hall, G.; Raymond, M.

    2003-03-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to tape. Because of the large number of pixels, data reduction is needed on the sensor itself or just outside. This brings in stringent requirements on the temporal noise as well as to the sensor uniformity, expressed as a Fixed Pattern Noise (FPN). A pixel architecture with an additional transistor is proposed. This architecture, coupled to correlated double sampling of the signal will allow cancellation of the two dominant noise sources, namely the reset or kTC noise and the FPN. A prototype has been designed in a standard 0.25 μm CMOS technology. It has also a structure for electrical calibration of the sensor. The prototype is functional and detailed tests are under way.

  5. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    PubMed

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

  6. Nanophotonic filters for digital imaging

    NASA Astrophysics Data System (ADS)

    Walls, Kirsty

    There has been an increasing demand for low cost, portable CMOS image sensors because of increased integration, and new applications in the automotive, mobile communication and medical industries, amongst others. Colour reproduction remains imperfect in conventional digital image sensors, due to the limitations of the dye-based filters. Further improvement is required if the full potential of digital imaging is to be realised. In alternative systems, where accurate colour reproduction is a priority, existing equipment is too bulky for anything but specialist use. In this work both these issues are addressed by exploiting nanophotonic techniques to create enhanced trichromatic filters, and multispectral filters, all of which can be fabricated on-chip, i.e. integrated into a conventional digital image sensor, to create compact, low cost, mass produceable imaging systems with accurate colour reproduction. The trichromatic filters are based on plasmonic structures. They exploit the excitation of surface plasmon resonances in arrays of subwavelength holes in metal films to filter light. The currently-known analytical expressions are inadequate for optimising all relevant parameters of a plasmonic structure. In order to obtain arbitrary filter characteristics, an automated design procedure was developed that integrated a genetic algorithm and 3D finite-difference time-domain tool. The optimisation procedure's efficacy is demonstrated by designing a set of plasmonic filters that replicate the CIE (1931) colour matching functions, which themselves mimic the human eye's daytime colour response.

  7. A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

    NASA Technical Reports Server (NTRS)

    Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

    2014-01-01

    Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

  8. The design of the CMOS wireless bar code scanner applying optical system based on ZigBee

    NASA Astrophysics Data System (ADS)

    Chen, Yuelin; Peng, Jian

    2008-03-01

    The traditional bar code scanner is influenced by the length of data line, but the farthest distance of the wireless bar code scanner of wireless communication is generally between 30m and 100m on the market. By rebuilding the traditional CCD optical bar code scanner, a CMOS code scanner is designed based on the ZigBee to meet the demands of market. The scan system consists of the CMOS image sensor and embedded chip S3C2401X, when the two dimensional bar code is read, the results show the inaccurate and wrong code bar, resulted from image defile, disturber, reads image condition badness, signal interference, unstable system voltage. So we put forward the method which uses the matrix evaluation and Read-Solomon arithmetic to solve them. In order to construct the whole wireless optics of bar code system and to ensure its ability of transmitting bar code image signals digitally with long distances, ZigBee is used to transmit data to the base station, and this module is designed based on image acquisition system, and at last the wireless transmitting/receiving CC2430 module circuit linking chart is established. And by transplanting the embedded RTOS system LINUX to the MCU, an applying wireless CMOS optics bar code scanner and multi-task system is constructed. Finally, performance of communication is tested by evaluation software Smart RF. In broad space, every ZIGBEE node can realize 50m transmission with high reliability. When adding more ZigBee nodes, the transmission distance can be several thousands of meters long.

  9. CMOS VLSI Active-Pixel Sensor for Tracking

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  10. Improved Space Object Orbit Determination Using CMOS Detectors

    NASA Astrophysics Data System (ADS)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  11. Digital printing

    NASA Astrophysics Data System (ADS)

    Sobotka, Werner K.

    1997-02-01

    Digital printing is described as a tool to replace conventional printing machines completely. Still this goal was not reached until now with any of the digital printing technologies to be described in the paper. Productivity and costs are still the main parameters and are not really solved until now. Quality in digital printing is no problem anymore. Definition of digital printing is to transfer digital datas directly on the paper surface. This step can be carried out directly or with the use of an intermediate image carrier. Keywords in digital printing are: computer- to-press; erasable image carrier; image carrier with memory. Digital printing is also the logical development of the new digital area as it is pointed out in Nicholas Negropotes book 'Being Digital' and also the answer to networking and Internet technologies. Creating images text and color in one country and publishing the datas in another country or continent is the main advantage. Printing on demand another big advantage and last but not least personalization the last big advantage. Costs and being able to coop with this new world of prepress technology is the biggest disadvantage. Therefore the very optimistic growth rates for the next few years are really nonexistent. The development of complete new markets is too slow and the replacing of old markets is too small.

  12. Digital metamaterials.

    PubMed

    Della Giovampaola, Cristian; Engheta, Nader

    2014-12-01

    Balancing complexity and simplicity has played an important role in the development of many fields in science and engineering. One of the well-known and powerful examples of such balance can be found in Boolean algebra and its impact on the birth of digital electronics and the digital information age. The simplicity of using only two numbers, '0' and '1', in a binary system for describing an arbitrary quantity made the fields of digital electronics and digital signal processing powerful and ubiquitous. Here, inspired by the binary concept, we propose to develop the notion of digital metamaterials. Specifically, we investigate how one can synthesize an electromagnetic metamaterial with a desired permittivity, using as building blocks only two elemental materials, which we call 'metamaterial bits', with two distinct permittivity functions. We demonstrate, analytically and numerically, how proper spatial mixtures of such metamaterial bits lead to elemental 'metamaterial bytes' with effective material parameters that are different from the parameters of the metamaterial bits. We then apply this methodology to several design examples of optical elements, such as digital convex lenses, flat graded-index digital lenses, digital constructs for epsilon-near-zero (ENZ) supercoupling and digital hyperlenses, thus highlighting the power and simplicity of the methodology.

  13. Gun muzzle flash detection using a single photon avalanche diode array in 0.18µm CMOS technology

    NASA Astrophysics Data System (ADS)

    Savuskan, Vitali; Jakobson, Claudio; Merhav, Tomer; Shoham, Avi; Brouk, Igor; Nemirovsky, Yael

    2015-05-01

    In this study, a CMOS Single Photon Avalanche Diode (SPAD) 2D array is used to record and sample muzzle flash events in the visible spectrum, from representative weapons. SPADs detect the emission peaks of alkali salts, potassium or sodium, with spectral emission lines around 769nm and 589nm, respectively. The alkali salts are included in the gunpowder to suppress secondary flashes ignited during the muzzle flash event. The SPADs possess two crucial properties for muzzle flash imaging: (i) very high photon detection sensitivity, (ii) a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. The sole noise sources are the ones prior to the readout circuitry (optical signal distribution, avalanche initiation distribution and nonphotonic generation). This enables high sampling frequencies in the kilohertz range without significant SNR degradation, in contrast to regular CMOS image sensors. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength, in the presence of sunlight. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics and signal processing, which will be reported. The frame rate of ~16 KHz was chosen as an optimum between SNR degradation and temporal profile recognition accuracy. In contrast to a single SPAD, the 2D array allows for multiple events to be processed simultaneously. Moreover, a significant field of view is covered, enabling comprehensive surveillance and imaging.

  14. Predicted image quality of a CMOS APS X-ray detector across a range of mammographic beam qualities

    NASA Astrophysics Data System (ADS)

    Konstantinidis, A.

    2015-09-01

    Digital X-ray detectors based on Complementary Metal-Oxide- Semiconductor (CMOS) Active Pixel Sensor (APS) technology have been introduced in the early 2000s in medical imaging applications. In a previous study the X-ray performance (i.e. presampling Modulation Transfer Function (pMTF), Normalized Noise Power Spectrum (NNPS), Signal-to-Noise Ratio (SNR) and Detective Quantum Efficiency (DQE)) of the Dexela 2923MAM CMOS APS X-ray detector was evaluated within the mammographic energy range using monochromatic synchrotron radiation (i.e. 17-35 keV). In this study image simulation was used to predict how the mammographic beam quality affects image quality. In particular, the experimentally measured monochromatic pMTF, NNPS and SNR parameters were combined with various mammographic spectral shapes (i.e. Molybdenum/Molybdenum (Mo/Mo), Rhodium/Rhodium (Rh/Rh), Tungsten/Aluminium (W/Al) and Tungsten/Rhodium (W/Rh) anode/filtration combinations at 28 kV). The image quality was measured in terms of Contrast-to-Noise Ratio (CNR) using a synthetic breast phantom (4 cm thick with 50% glandularity). The results can be used to optimize the imaging conditions in order to minimize patient's Mean Glandular Dose (MGD).

  15. Low Noise and Highly Linear Wideband CMOS RF Front-End for DVB-H Direct-Conversion Receiver

    NASA Astrophysics Data System (ADS)

    Nam, Ilku; Moon, Hyunwon; Woo, Doo Hyung

    In this paper, a wideband CMOS radio frequency (RF) front-end for digital video broadcasting-handheld (DVB-H) receiver is proposed. The RF front-end circuit is composed of a single-ended resistive feedback low noise amplifier (LNA), a single-to-differential amplifier, an I/Q down-conversion mixer with linearized transconductors employing third order intermodulation distortion cancellation, and a divide-by-two circuit with LO buffers. By employing a third order intermodulation (IMD3) cancellation technique and vertical NPN bipolar junction transistor (BJT) switching pair for an I/Q down-conversion mixer, the proposed RF front-end circuit has high linearity and low low-frequency noise performance. It is fabricated in a 0.18µm deep n-well CMOS technology and draws 12mA from a 1.8V supply voltage. It shows a voltage gain of 31dB, a noise figure (NF) lower than 2.6dB, and an IIP3 of -8dBm from 470MHz to 862MHz.

  16. CMOS RAM cosmic-ray-induced-error-rate analysis

    NASA Technical Reports Server (NTRS)

    Pickel, J. C.; Blandford, J. T., Jr.

    1981-01-01

    A significant number of spacecraft operational anomalies are believed to be associated with cosmic-ray-induced soft errors in the LSI memories. Test programs using a cyclotron to simulate cosmic rays have established conclusively that many common commercial memory types are vulnerable to heavy-ion upset. A description is given of the methodology and the results of a detailed analysis for predicting the bit-error rate in an assumed space environment for CMOS memory devices. Results are presented for three types of commercially available CMOS 1,024-bit RAMs. It was found that the HM6508 is susceptible to single-ion induced latchup from argon and krypton ions. The HS6508 and HS6508RH and the CDP1821 apparently are not susceptible to single-ion induced latchup.

  17. CMOS Imaging Device for Optical Imaging of Biological Activities

    NASA Astrophysics Data System (ADS)

    Shishido, Sanshiro; Oguro, Yasuhiro; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Ohta, Jun

    In this paper, we propose a CMOS image sensor device placed on the brain surface or cerebral sulcus (Fig. 1). The device has a photo detector array where a single optical detector is usually used. The proposed imaging device enables the analysis which reflects a surface blood pattern in the observed area. It is also possible to improve effective sensitivity by image processing and to simplify the measurement system by the CMOS sensor device with on-chip light source. We describe the design details and characterization of proposed device. We also demonstrate detection of hemoglobin oxygenation level with external light source, imaging capability of biological activities, and image processing for sensitivity improvement is also realized.

  18. A CMOS integrated timing discriminator circuit for fast scintillation counters

    SciTech Connect

    Jochmann, M.W.

    1998-06-01

    Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t{sub r} {ge} 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal`s amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range.

  19. A back-illuminated megapixel CMOS image sensor

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Cunningham, Thomas; Nikzad, Shouleh; Hoenk, Michael; Jones, Todd; Wrigley, Chris; Hancock, Bruce

    2005-01-01

    In this paper, we present the test and characterization results for a back-illuminated megapixel CMOS imager. The imager pixel consists of a standard junction photodiode coupled to a three transistor-per-pixel switched source-follower readout [1]. The imager also consists of integrated timing and control and bias generation circuits, and provides analog output. The analog column-scan circuits were implemented in such a way that the imager could be configured to run in off-chip correlated double-sampling (CDS) mode. The imager was originally designed for normal front-illuminated operation, and was fabricated in a commercially available 0.5 pn triple-metal CMOS-imager compatible process. For backside illumination, the imager was thinned by etching away the substrate was etched away in a post-fabrication processing step.

  20. Micromachined high-performance RF passives in CMOS substrate

    NASA Astrophysics Data System (ADS)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-11-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications.

  1. A CMOS image sensor dedicated to medical gamma camera application

    NASA Astrophysics Data System (ADS)

    Salahuddin, Nur S.; Paindavoine, Michel; Ginhac, Dominique; Parmentier, Michel; Tamda, Najia

    2005-03-01

    Generally, medical Gamma Camera are based on the Anger principle. These cameras use a scintillator block coupled to a bulky array of photomultiplier tube (PMT). To simplify this, we designed a new integrated CMOS image sensor in order to replace bulky PMT photodetetors. We studied several photodiodes sensors including current mirror amplifiers. These photodiodes have been fabricated using a CMOS 0.6 micrometers process from Austria Mikro Systeme (AMS). Each sensor pixel in the array occupies respectively, 1mm x 1mm area, 0.5mm x 0.5mm area and 0.2mm 0.2mm area with fill factor 98 % and total chip area is 2 square millimeters. The sensor pixels show a logarithmic response in illumination and are capable of detecting very low green light emitting diode (less than 0.5 lux) . These results allow to use our sensor in new Gamma Camera solid-state concept.

  2. CCD or CMOS camera calibration using point spread function

    NASA Astrophysics Data System (ADS)

    Abdelsalam, D. G.; Stanislas, M.; Coudert, S.

    2014-06-01

    We present a simple method based on the acquisition of a back-illuminated pinhole to estimate the point spread function (PSF) for CCD (or CMOS) sensor characterization. This method is used to measure the variations in sensitivity of the 2D-sensor array systems. The experimental results show that there is a variation in sensitivity for each position on the CCD of the calibrated camera and the pixel optical center error with respect to the geometrical center is in the range of 1/10th of a pixel. We claim that the pixel error comes most probably from the coherence of the laser light used, or eventually from possible defects in shape, surface quality, optical performance of micro-lenses, and the uniformity of the parameters across the wafer. This may have significant consequences for coherent light imaging using CCD (or CMOS) such as Particle Image Velocimetry.

  3. A Brief Discussion of Radiation Hardening of CMOS Microelectronics

    SciTech Connect

    Myers, D.R.

    1998-12-18

    Commercial microchips work well in their intended environments. However, generic microchips will not fimction correctly if exposed to sufficient amounts of ionizing radiation, the kind that satellites encounter in outer space. Modern CMOS circuits must overcome three specific concerns from ionizing radiation: total-dose, single-event, and dose-rate effects. Minority-carrier devices such as bipolar transistors, optical receivers, and solar cells must also deal with recombination-generation centers caused by displacement damage, which are not major concerns for majority-carrier CMOS devices. There are ways to make the chips themselves more resistant to radiation. This extra protection, called radiation hardening, has been called both a science and an art. Radiation hardening requires both changing the designs of the chips and altering the ways that the chips are manufactured.

  4. TID Simulation of Advanced CMOS Devices for Space Applications

    NASA Astrophysics Data System (ADS)

    Sajid, Muhammad

    2016-07-01

    This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

  5. VLSI digital PSK demodulator for space communication

    NASA Astrophysics Data System (ADS)

    Hansen, Flemming; Thomsen, Jan H.; Jacobsen, Freddy L.; Olsen, Karsten

    1993-02-01

    This paper describes the design of a BPSK/QPSK demodulator implemented using multirate digital signal processing in a CMOS ASIC. The demodulator is fully programmable via serial and parallel interfaces, and handles symbol rates from 125 sym/s to 4 Msym/s. It performs at less than 0.5 dB degradation from ideal BER vs. E(b)/N(o) characteristics. System design considerations lead to the choice of a complex IF scheme with sampling at four times the intermediate frequency, and a combined analog and digital matched filtering based on the pulselet concept. Signal processing algorithms include the Costas carrier phase error detector, the zero-crossing detector for timing error, and algorithms for lock detection and loop filtering. Simulations of the entire demodulator including the ASIC part is accomplished by proprietary software. The ASIC is manufactured in a radiation tolerant 1-micron CMOS gate array process using 34085 gates. The main application area is spaceborne coherent transponders.

  6. Digital Discrimination

    ERIC Educational Resources Information Center

    Blansett, Jim

    2008-01-01

    In recent years, the Internet has become a digital commons of commerce and education. However, accessibility standards have often been overlooked online, and the digital equivalents to curb-cuts and other physical accommodations have only rarely been implemented to serve those with print disabilities. (A print disability can be a learning…

  7. Digitizing Preservation.

    ERIC Educational Resources Information Center

    Conway, Paul

    1994-01-01

    Discussion of digital imaging technology focuses on its potential use for preservation of library materials. Topics addressed include converting microfilm to digital; the high cost of conversion from paper or microfilm; quality; indexing; database management issues; incompatibility among imaging systems; longevity; cooperative pilot projects; and…

  8. Digital Roundup

    ERIC Educational Resources Information Center

    Horn, Michael B.

    2013-01-01

    State policy is crucial to the spread of digital-learning opportunities at the elementary and secondary level. A review of recent legislative action reveals policies that are constantly in flux and differ quite markedly from one state to another. Some have hoped for model digital-learning legislation that could handle all the various issues…

  9. Digital TMI

    NASA Technical Reports Server (NTRS)

    Rios, Joseph

    2012-01-01

    Presenting the current status of the Digital TMI project to visiting members of the FAA Command Center. Digital TMI is an effort to store national-level traffic management initiatives in a standards-compliant manner. Work is funded by the FAA.

  10. Hardening of commercial CMOS PROMs with polysilicon fusible links

    NASA Technical Reports Server (NTRS)

    Newman, W. H.; Rauchfuss, J. E.

    1985-01-01

    The method by which a commercial 4K CMOS PROM with polysilicon fuses was hardened and the feasibility of applying this method to a 16K PROM are presented. A description of the process and the necessary minor modifications to the original layout are given. The PROM circuit and discrete device characteristics over radiation to 1000K rad-Si are summarized. The dose rate sensitivity of the 4K PROMs is also presented.

  11. Linear dynamic range enhancement in a CMOS imager

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata (Inventor)

    2008-01-01

    A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

  12. A BiCMOS integrated charge to amplitude converter

    SciTech Connect

    Gallin-Martel, L.; Pouxe, J.; Rossetto, O.

    1996-12-31

    This paper describes a fast two channel gated charge to amplitude converter (QAC) which has been designed with the 1.2 {mu}m BiCMOS technology from AMS (Austria Mikro Systeme). It can integrate fast negative impulse currents up to 100 mA. Associated with an audio 18 bit low cost ADC, it can easily be used to make a 12 to 13 bit QDC. The problems of current to current conversion, pedestal and offset stability are discussed.

  13. CMOS Alcohol Sensor Employing ZnO Nanowire Sensing Films

    NASA Astrophysics Data System (ADS)

    Santra, S.; Ali, S. Z.; Guha, P. K.; Hiralal, P.; Unalan, H. E.; Dalal, S. H.; Covington, J. A.; Milne, W. I.; Gardner, J. W.; Udrea, F.

    2009-05-01

    This paper reports on the utilization of zinc oxide nanowires (ZnO NWs) on a silicon on insulator (SOI) CMOS micro-hotplate for use as an alcohol sensor. The device was designed in Cadence and fabricated in a 1.0 μm SOI CMOS process at XFAB (Germany). The basic resistive gas sensor comprises of a metal micro-heater (made of aluminum) embedded in an ultra-thin membrane. Gold plated aluminum electrodes, formed of the top metal, are used for contacting with the sensing material. This design allows high operating temperatures with low power consumption. The membrane was formed by using deep reactive ion etching. ZnO NWs were grown on SOI CMOS substrates by a simple and low-cost hydrothermal method. A few nanometer of ZnO seed layer was first sputtered on the chips, using a metal mask, and then the chips were dipped in a zinc nitrate hexahydrate and hexamethylenetramine solution at 90° C to grow ZnO NWs. The chemical sensitivity of the on-chip NWs were studied in the presence of ethanol (C2H5OH) vapour (with 10% relative humidity) at two different temperatures: 200 and 250° C (the corresponding power consumptions are only 18 and 22 mW). The concentrations of ethanol vapour were varied from 175-1484 ppm (pers per million) and the maximum response was observed 40% (change in resistance in %) at 786 ppm at 250° C. These preliminary measurements showed that the on-chip deposited ZnO NWs could be a promising material for a CMOS based ethanol sensor.

  14. Accelerated life testing effects on CMOS microcircuit characteristics, phase 1

    NASA Technical Reports Server (NTRS)

    Maximow, B.

    1976-01-01

    An accelerated life test of sufficient duration to generate a minimum of 50% cumulative failures in lots of CMOS devices was conducted to provide a basis for determining the consistency of activation energy at 250 C. An investigation was made to determine whether any thresholds were exceeded during the high temperature testing, which could trigger failure mechanisms unique to that temperature. The usefulness of the 250 C temperature test as a predictor of long term reliability was evaluated.

  15. CMOS integration of inkjet-printed graphene for humidity sensing

    NASA Astrophysics Data System (ADS)

    Santra, S.; Hu, G.; Howe, R. C. T.; de Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-11-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  16. CMOS integration of inkjet-printed graphene for humidity sensing.

    PubMed

    Santra, S; Hu, G; Howe, R C T; De Luca, A; Ali, S Z; Udrea, F; Gardner, J W; Ray, S K; Guha, P K; Hasan, T

    2015-11-30

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10-80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things.

  17. Development of CMOS Imager Block for Capsule Endoscope

    NASA Astrophysics Data System (ADS)

    Shafie, S.; Fodzi, F. A. M.; Tung, L. Q.; Lioe, D. X.; Halin, I. A.; Hasan, W. Z. W.; Jaafar, H.

    2014-04-01

    This paper presents the development of imager block to be associated in a capsule endoscopy system. Since the capsule endoscope is used to diagnose gastrointestinal diseases, the imager block must be in small size which is comfortable for the patients to swallow. In this project, a small size 1.5V button battery is used as the power supply while the voltage supply requirements for other components such as microcontroller and CMOS image sensor are higher. Therefore, a voltage booster circuit is proposed to boost up the voltage supply from 1.5V to 3.3V. A low power microcontroller is used to generate control pulses for the CMOS image sensor and to convert the 8-bits parallel data output to serial data to be transmitted to the display panel. The results show that the voltage booster circuit was able to boost the voltage supply from 1.5V to 3.3V. The microcontroller precisely controls the CMOS image sensor to produce parallel data which is then serialized again by the microcontroller. The serial data is then successfully translated to 2fps image and displayed on computer.

  18. CMOS Active Pixel Sensor (APS) Imager for Scientific Applications

    NASA Astrophysics Data System (ADS)

    Ay, Suat U.; Lesser, Michael P.; Fossum, Eric R.

    2002-12-01

    A 512×512 CMOS Active Pixel Sensor (APS) imager has been designed, fabricate, and tested for frontside illumination suitable for use in astronomy specifically in telescope guider systems as a replacement of CCD chips. The imager features a high-speed differential analog readout, 15 μm pixel pitch, 75 % fill factor (FF), 62 dB dynamic range, 315Ke- pixel capacity, less than 0.25% fixed pattern noise (FPN), 45 dB signal to noise ratio (SNR) and frame rate of up to 40 FPS. Design was implemented in a standard 0.5 μm CMOS process technology consuming less than 200mWatts on a single 5 Volt power supply. CMOS Active Pixel Sensor (APS) imager was developed with pixel structure suitable for both frontside and backside illumination holding large number of electron in relatively small pixel pitch of 15 μm. High-speed readout and signal processing circuits were designed to achieve low fixed pattern noise (FPN) and non-uniformity to provide CCD-like analog outputs. Target spectrum range of operation for the imager is in near ultraviolet (300-400 nm) with high quantum efficiency. This device is going to be used as a test vehicle to develop backside-thinning process.

  19. Transversal-readout CMOS active pixel image sensor

    NASA Astrophysics Data System (ADS)

    Miyatake, Shigehiro; Ishida, Kouichi; Morimoto, Takashi; Masaki, Yasuo; Tanabe, Hideki

    2001-05-01

    This paper presents a CMOS active pixel image sensor (APS) with a transversal readout architecture that eliminates the vertically striped fixed pattern noise (FPN). There are two kinds of FPNs for CMOS APSs. One originates form the pixel- to-pixel variation in dark current and source-follower threshold voltage, and the other from the column-to-column variation in column readout structures. The former may become invisible in the future due to process improvements. However, the latter, which result sin a vertically striped FPN, is and will be conspicuous without some subtraction because of the correlation in the vertical direction. The pixel consists of a photodiode, a row- and a column-reset transistor, a source follower input transistor, and a column-select transistor instead of the row-select transistor in conventional CMOS APSs. The column-select transistor is connected to a signal line, which runs horizontally instead of vertically. Every horizontal signal line is merged into a single vertical signal line via a row- select transistor, which can be made large enough to make its on-resistence variation negligible because of its low driving frequency. Therefore, the sensor has neither a vertical nor horizontal stripe FPN.

  20. An integrated CMOS detection system for optical short-pulse

    NASA Astrophysics Data System (ADS)

    Kim, Chang-Gun; Hong, Nam-Pyo; Choi, Young-Wan

    2014-03-01

    We present design of a front-end readout system consisting of charge sensitive amplifier (CSA) and pulse shaper for detection of stochastic and ultra-small semiconductor scintillator signal. The semiconductor scintillator is double sided silicon detector (DSSD) or avalanche photo detector (APD) for high resolution and peak signal reliability of γ-ray or X-ray spectroscopy. Such system commonly uses low noise multichannel CSA. Each CSA in multichannel includes continuous reset system based on tens of MΩ and charge-integrating capacitor in feedback loop. The high value feedback resistor requires large area and huge power consumption for integrated circuits. In this paper, we analyze these problems and propose a CMOS short pulse detection system with a novel CSA. The novel CSA is composed of continuous reset system with combination of diode connected PMOS and 100 fF. This structure has linearity with increased input charge quantity from tens of femto-coulomb to pico-coulomb. Also, the front-end readout system includes both slow and fast shapers for detecting CSA output and preventing pile-up distortion. Shaping times of fast and slow shapers are 150 ns and 1.4 μs, respectively. Simulation results of the CMOS detection system for optical short-pulse implemented in 0.18 μm CMOS technology are presented.

  1. Optimizing quantum efficiency in a stacked CMOS sensor

    NASA Astrophysics Data System (ADS)

    Hannebauer, Rob; Yoo, Sang Keun; Gilblom, David L.; Gilblom, Alexander D.

    2011-03-01

    Optimizing quantum efficiency of image sensors, whether CCD or CMOS, has usually required backside thinning to bring the photon receiving surface close to the charge generation elements. A new CMOS sensor architecture has been developed that permits high-fill-factor photodiodes to be placed at the silicon surface without the need for backside thinning. The photodiode access provided by this architecture permits application of highly-effective anti-reflection coatings on the input surface and construction of a mirror inside the silicon below the photodiodes to effectively double the optical thickness of the silicon charge generation volume. Secondary benefits of this architecture include prevention of light from reaching the CMOS circuitry under the photodiodes, improvement of near-infrared quantum efficiency, and reduction in optical artifacts caused by reflections from the sensor surface. Utilizing these techniques, a sensor is being constructed with 4096 x 4096 pixels 4.8 μm square with 95% fill factor backed by a mirror tuned to the 400-700 nm visible band and a front-surface anti-reflectance coating. The quantum efficiency is expected to exceed 80% through the visible and the global shutter extinction ratio should exceed 106:1. The sensors have been fabricated and first test data is due in February 2011.

  2. Optimization of precision localization microscopy using CMOS camera technology

    NASA Astrophysics Data System (ADS)

    Fullerton, Stephanie; Bennett, Keith; Toda, Eiji; Takahashi, Teruo

    2012-02-01

    Light microscopy imaging is being transformed by the application of computational methods that permit the detection of spatial features below the optical diffraction limit. Successful localization microscopy (STORM, dSTORM, PALM, PhILM, etc.) relies on the precise position detection of fluorescence emitted by single molecules using highly sensitive cameras with rapid acquisition speeds. Electron multiplying CCD (EM-CCD) cameras are the current standard detector for these applications. Here, we challenge the notion that EM-CCD cameras are the best choice for precision localization microscopy and demonstrate, through simulated and experimental data, that certain CMOS detector technology achieves better localization precision of single molecule fluorophores. It is well-established that localization precision is limited by system noise. Our findings show that the two overlooked noise sources relevant for precision localization microscopy are the shot noise of the background light in the sample and the excess noise from electron multiplication in EM-CCD cameras. At low light conditions (< 200 photons/fluorophore) with no optical background, EM-CCD cameras are the preferred detector. However, in practical applications, optical background noise is significant, creating conditions where CMOS performs better than EM-CCD. Furthermore, the excess noise of EM-CCD is equivalent to reducing the information content of each photon detected which, in localization microscopy, reduces the precision of the localization. Thus, new CMOS technology with 100fps, <1.3 e- read noise and high QE is the best detector choice for super resolution precision localization microscopy.

  3. CMOS integration of inkjet-printed graphene for humidity sensing

    PubMed Central

    Santra, S.; Hu, G.; Howe, R. C. T.; De Luca, A.; Ali, S. Z.; Udrea, F.; Gardner, J. W.; Ray, S. K.; Guha, P. K.; Hasan, T.

    2015-01-01

    We report on the integration of inkjet-printed graphene with a CMOS micro-electro-mechanical-system (MEMS) microhotplate for humidity sensing. The graphene ink is produced via ultrasonic assisted liquid phase exfoliation in isopropyl alcohol (IPA) using polyvinyl pyrrolidone (PVP) polymer as the stabilizer. We formulate inks with different graphene concentrations, which are then deposited through inkjet printing over predefined interdigitated gold electrodes on a CMOS microhotplate. The graphene flakes form a percolating network to render the resultant graphene-PVP thin film conductive, which varies in presence of humidity due to swelling of the hygroscopic PVP host. When the sensors are exposed to relative humidity ranging from 10–80%, we observe significant changes in resistance with increasing sensitivity from the amount of graphene in the inks. Our sensors show excellent repeatability and stability, over a period of several weeks. The location specific deposition of functional graphene ink onto a low cost CMOS platform has the potential for high volume, economic manufacturing and application as a new generation of miniature, low power humidity sensors for the internet of things. PMID:26616216

  4. Fully depleted, thick, monolithic CMOS pixels with high quantum efficiency

    NASA Astrophysics Data System (ADS)

    Clarke, A.; Stefanov, K.; Johnston, N.; Holland, A.

    2015-04-01

    The Centre for Electronic Imaging (CEI) has an active programme of evaluating and designing Complementary Metal-Oxide Semiconductor (CMOS) image sensors with high quantum efficiency, for applications in near-infrared and X-ray photon detection. This paper describes the performance characterisation of CMOS devices made on a high resistivity 50 μ m thick p-type substrate with a particular focus on determining the depletion depth and the quantum efficiency. The test devices contain 8 × 8 pixel arrays using CCD-style charge collection, which are manufactured in a low voltage CMOS process by ESPROS Photonics Corporation (EPC). Measurements include determining under which operating conditions the devices become fully depleted. By projecting a spot using a microscope optic and a LED and biasing the devices over a range of voltages, the depletion depth will change, causing the amount of charge collected in the projected spot to change. We determine if the device is fully depleted by measuring the signal collected from the projected spot. The analysis of spot size and shape is still under development.

  5. Single photon detection and localization accuracy with an ebCMOS camera

    NASA Astrophysics Data System (ADS)

    Cajgfinger, T.; Dominjon, A.; Barbier, R.

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 μm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  6. Hybrid Integration of Graphene Analog and Silicon Complementary Metal-Oxide-Semiconductor Digital Circuits.

    PubMed

    Hong, Seul Ki; Kim, Choong Sun; Hwang, Wan Sik; Cho, Byung Jin

    2016-07-26

    We demonstrate a hybrid integration of a graphene-based analog circuit and a silicon-based digital circuit in order to exploit the strengths of both graphene and silicon devices. This mixed signal circuit integration was achieved using a three-dimensional (3-D) integration technique where a graphene FET multimode phase shifter is fabricated on top of a silicon complementary metal-oxide-semiconductor field-effect transistor (CMOS FET) ring oscillator. The process integration scheme presented here is compatible with the conventional silicon CMOS process, and thus the graphene circuit can successfully be integrated on current semiconductor technology platforms for various applications. This 3-D integration technique allows us to take advantage of graphene's excellent inherent properties and the maturity of current silicon CMOS technology for future electronics. PMID:27403730

  7. Investigation of CMOS photodiodes integrated on an ASIC by a 0.5-µm analog CMOS process

    NASA Astrophysics Data System (ADS)

    Luo, H.; Ricklefs, U.; Hillmer, H.

    2010-04-01

    The characteristics of photodiodes integrated on CMOS ASICs depend on wavelength of radiation, structure of the photodiode itself and the parameters of the process of production. In this paper, the influence of the structure of integrated CMOS photodiodes produced in a standard 0.5 μm mixed signal CMOS process on the sensitivity is described. These photodiodes are used as image sensor elements arranged in an array for noncontact optoelectronic measurements. Models of integrated photodiodes distinguish the lateral and the vertical region of the photodiodes. The standard 0.5 μm CMOS process offers three types of pn-junctions: n+/p-substrate, p+/n-well and n-well/p-substrate. Based on our previous research and on the results from other authors the p+/n-well is chosen due to its better sensitivity and isolation against other structures. The local sensitivity is measured with a scanning setup by applying a diffraction limited spot spot of light on the surface of the diodes. Independent of the wavelength of radiation the charge carriers are generated mainly in the lateral region and not - as expected - in the vertical region. The maximum value of the local sensitivity is found in photodiodes with subdivided p+ regions showing a distance of 1.5 μm between these regions in the space between these two adjacent p+ regions. This local sensitivity is three times smaller than that of a reference PIN photodiode. According to this result, the new photodiodes will be constructed with optimized geometries. All examined structures of this type of photodiodes show a maximal spectral sensitivity in the range of 650 nm - 700 nm.

  8. Real-time, continuous, fluorescence sensing in a freely-moving subject with an implanted hybrid VCSEL/CMOS biosensor

    PubMed Central

    O’Sullivan, Thomas D.; Heitz, Roxana T.; Parashurama, Natesh; Barkin, David B.; Wooley, Bruce A.; Gambhir, Sanjiv S.; Harris, James S.; Levi, Ofer

    2013-01-01

    Performance improvements in instrumentation for optical imaging have contributed greatly to molecular imaging in living subjects. In order to advance molecular imaging in freely moving, untethered subjects, we designed a miniature vertical-cavity surface-emitting laser (VCSEL)-based biosensor measuring 1cm3 and weighing 0.7g that accurately detects both fluorophore and tumor-targeted molecular probes in small animals. We integrated a critical enabling component, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit, which digitized the fluorescence signal to achieve autofluorescence-limited sensitivity. After surgical implantation of the lightweight sensor for two weeks, we obtained continuous and dynamic fluorophore measurements while the subject was un-anesthetized and mobile. The technology demonstrated here represents a critical step in the path toward untethered optical sensing using an integrated optoelectronic implant. PMID:24009996

  9. A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS.

    PubMed

    Jha, Pankaj; Patra, Pravanjan; Naik, Jairaj; Acharya, Amit; Rajalakshmi, P; Singh, Shiv Govind; Dutta, Ashudeb

    2015-08-01

    This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled signal conditioning stage with programmable gain and bandwidth, a new mixed signal automatic gain control (AGC) mechanism and a medically cohesive reconfigurable ΣΔ ADC. The full system is designed in UMC 0.18μm CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47μW power consumption. The ADC provides 2(nd) order noise-shaping while using single integrator and an ENOB of ~11 bits with 5μW power consumption. The system was successfully verified for various ECG signals from PTB database. This system is intended for portable batteryless u-Healthcare devices. PMID:26736391

  10. Superconductor Digital Electronics: -- Current Status, Future Prospects

    NASA Astrophysics Data System (ADS)

    Mukhanov, Oleg

    2011-03-01

    Two major applications of superconductor electronics: communications and supercomputing will be presented. These areas hold a significant promise of a large impact on electronics state-of-the-art for the defense and commercial markets stemming from the fundamental advantages of superconductivity: simultaneous high speed and low power, lossless interconnect, natural quantization, and high sensitivity. The availability of relatively small cryocoolers lowered the foremost market barrier for cryogenically-cooled superconductor electronic systems. These fundamental advantages enabled a novel Digital-RF architecture - a disruptive technological approach changing wireless communications, radar, and surveillance system architectures dramatically. Practical results were achieved for Digital-RF systems in which wide-band, multi-band radio frequency signals are directly digitized and digital domain is expanded throughout the entire system. Digital-RF systems combine digital and mixed signal integrated circuits based on Rapid Single Flux Quantum (RSFQ) technology, superconductor analog filter circuits, and semiconductor post-processing circuits. The demonstrated cryocooled Digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals, enabling multi-net data links, and performing signal acquisition from HF to L-band with 30 GHz clock frequencies. In supercomputing, superconductivity leads to the highest energy efficiencies per operation. Superconductor technology based on manipulation and ballistic transfer of magnetic flux quanta provides a superior low-power alternative to CMOS and other charge-transfer based device technologies. The fundamental energy consumption in SFQ circuits defined by flux quanta energy 2 x 10-19 J. Recently, a novel energy-efficient zero-static-power SFQ technology, eSFQ/ERSFQ was invented, which retains all advantages of standard RSFQ circuits: high-speed, dc power, internal memory. The

  11. CMOS compatible thin-film ALD tungsten nanoelectromechanical devices

    NASA Astrophysics Data System (ADS)

    Davidson, Bradley Darren

    This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different

  12. Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier

    NASA Technical Reports Server (NTRS)

    Zhou, Zhimin (Inventor); Pain, Bedabrata (Inventor)

    1999-01-01

    An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes a single charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.

  13. Solid-state image sensor with focal-plane digital photon-counting pixel array

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Pain, Bedabrata (Inventor)

    1995-01-01

    A photosensitive layer such as a-Si for a UV/visible wavelength band is provided for low light level imaging with at least a separate CMOS amplifier directly connected to each PIN photodetector diode to provide a focal-plane array of NxN pixels, and preferably a separate photon-counting CMOS circuit directly connected to each CMOS amplifier, although one row of counters may be time shared for reading out the photon flux rate of each diode in the array, together with a buffer memory for storing all rows of the NxN image frame before transfer to suitable storage. All CMOS circuitry is preferably fabricated in the same silicon layer as the PIN photodetector diode for a monolithic structure, but when the wavelength band of interest requires photosensitive material different from silicon, the focal-plane array may be fabricated separately on a different semiconductor layer bump-bonded or otherwise bonded for a virtually monolithic structure with one free terminal of each diode directly connected to the input terminal of its CMOS amplifier and digital counter for integration of the photon flux rate at each photodetector of the array.

  14. Flight test of a full authority Digital Electronic Engine Control system in an F-15 aircraft

    NASA Technical Reports Server (NTRS)

    Barrett, W. J.; Rembold, J. P.; Burcham, F. W.; Myers, L.

    1981-01-01

    The Digital Electronic Engine Control (DEEC) system considered is a relatively low cost digital full authority control system containing selectively redundant components and fault detection logic with capability for accommodating faults to various levels of operational capability. The DEEC digital control system is built around a 16-bit, 1.2 microsecond cycle time, CMOS microprocessor, microcomputer system with approximately 14 K of available memory. Attention is given to the control mode, component bench testing, closed loop bench testing, a failure mode and effects analysis, sea-level engine testing, simulated altitude engine testing, flight testing, the data system, cockpit, and real time display.

  15. A single-channel 10-bit 160 MS/s SAR ADC in 65 nm CMOS

    NASA Astrophysics Data System (ADS)

    Yuxiao, Lu; Lu, Sun; Zhe, Li; Jianjun, Zhou

    2014-04-01

    This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 × 200 μm2 is occupied.

  16. Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips.

    PubMed

    Deng, Fangming; He, Yigang; Li, Bing; Zhang, Lihua; Wu, Xiang; Fu, Zhihui; Zuo, Lei

    2015-01-01

    This paper presents an ultra-low embedded power temperature sensor for passive RFID tags. The temperature sensor converts the temperature variation to a PTAT current, which is then transformed into a temperature-controlled frequency. A phase locked loop (PLL)-based sensor interface is employed to directly convert this temperature-controlled frequency into a corresponding digital output without an external reference clock. The fabricated sensor occupies an area of 0.021 mm2 using the TSMC 0.18 1P6M mixed-signal CMOS process. Measurement results of the embedded sensor within the tag system shows a 92 nW power dissipation under 1.0 V supply voltage at room temperature, with a sensing resolution of 0.15 °C/LSB and a sensing accuracy of -0.7/0.6 °C from -30 °C to 70 °C after 1-point calibration at 30 °C.

  17. Next-generation CMOS active pixel sensors for satellite hybrid optical communications/imaging sensor systems

    NASA Astrophysics Data System (ADS)

    Stirbl, Robert C.; Pain, Bedabrata; Cunningham, Thomas J.; Hancock, Bruce R.; McCarty, Kenneth P.

    1998-12-01

    Given the current choices of (1) an ever increasing population of large numbers of satellites in low-earth orbit (LEO) constellations for commercial and military global coverage systems, or (2) the alternative of smaller count geosynchronous satellite system constellations in high-earth (HEO), of higher cost and complexity, a number of commercial communications and military operations satellite systems designers are investigating the potential advantages and issues of operating in the mid-earth orbit altitudes (MEO) (between LEO and HEO). At these MEO altitudes both total dose and displacement damage can be traded against the system advantages of fewer satellites required. With growing demand for higher bandwidth communication for real-time earth observing satellite sensor systems, and NASA's interplanetary and deep space virtual unmanned exploration missions in stressing radiation environments, JPL is developing the next generation of smart sensors to address these new requirements of: low-cost, high bandwidth, miniaturization, ultra low-power and mission environment ruggedness. Radiation hardened/tolerant Active Pixel Sensor CMOS imagers that can be adaptively windowed with low power, on-chip control, timing, digital output and provide data-channel efficient on-chip compression, high bandwidth optical communications links are being designed and investigated to reduce size, weight and cost for common optics/hybrid architectures.

  18. Optical and x-ray characterization of two novel CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Bohndiek, Sarah E.; Arvanitis, Costas D.; Venanzi, Cristian; Royle, Gary J.; Clark, Andy T.; Crooks, Jamie P.; Prydderch, Mark L.; Turchetta, Renato; Blue, Andrew; Speller, Robert D.

    2007-02-01

    A UK consortium (MI3) has been founded to develop advanced CMOS pixel designs for scientific applications. Vanilla, a 520x520 array of 25μm pixels benefits from flushed reset circuitry for low noise and random pixel access for region of interest (ROI) readout. OPIC, a 64x72 test structure array of 30μm digital pixels has thresholding capabilities for sparse readout at 3,700fps. Characterization is performed with both optical illumination and x-ray exposure via a scintillator. Vanilla exhibits 34+/-3e - read noise, interactive quantum efficiency of 54% at 500nm and can read a 6x6 ROI at 24,395fps. OPIC has 46+/-3e - read noise and a wide dynamic range of 65dB due to high full well capacity. Based on these characterization studies, Vanilla could be utilized in applications where demands include high spectral response and high speed region of interest readout while OPIC could be used for high speed, high dynamic range imaging.

  19. High Speed, Radiation Hard CMOS Pixel Sensors for Transmission Electron Microscopy

    NASA Astrophysics Data System (ADS)

    Contarato, Devis; Denes, Peter; Doering, Dionisio; Joseph, John; Krieger, Brad

    CMOS monolithic active pixel sensors are currently being established as the technology of choice for new generation digital imaging systems in Transmission Electron Microscopy (TEM). A careful sensor design that couples μm-level pixel pitches with high frame rate readout and radiation hardness to very high electron doses enables the fabrication of direct electron detectors that are quickly revolutionizing high-resolution TEM imaging in material science and molecular biology. This paper will review the principal characteristics of this novel technology and its advantages over conventional, optically-coupled cameras, and retrace the sensor development driven by the Transmission Electron Aberration corrected Microscope (TEAM) project at the LBNL National Center for Electron Microscopy (NCEM), illustrating in particular the imaging capabilities enabled by single electron detection at high frame rate. Further, the presentation will report on the translation of the TEAM technology to a finer feature size process, resulting in a sensor with higher spatial resolution and superior radiation tolerance currently serving as the baseline for a commercial camera system.

  20. An integrated CMOS time interval measurement system with subnanosecond resolution for the WA-98 calorimeter

    SciTech Connect

    Simpson, M.L.; Britton, C.L.; Wintenberg, A.L.; Young, G.R.

    1997-02-01

    The time interval measurement system of the WA-98 calorimeter is presented. This system consists of a constant fraction discriminator (CFD), a variable delay circuit, a time-to-amplitude converter (TAC), and a Wilkinson analog-to-digital converter (ADC) all realized in a 1.2-{micro}m N-well CMOS process. These circuits measured the time interval between a reference logic signal and a photomultiplier tube (PMT) signal that had amplitude variations of 100:1 and 10-ns rise and fall times. The system operated over the interval range from 2 ns to 200 ns with a resolution of {approximately}{+-}300 ps including all walk and jitter components. The variable delay circuit allowed the CFD output to be delayed /by up to 1 {micro}s with a jitter component of {approximately}0.04% of the delay setting. These circuits operated with a 5-V power supply. Although this application was in nuclear physics instrumentation, these circuits could also be useful in other scientific measurements, medical imaging, automatic test equipment, ranging systems, and industrial electronics.

  1. Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips

    PubMed Central

    Deng, Fangming; He, Yigang; Li, Bing; Zhang, Lihua; Wu, Xiang; Fu, Zhihui; Zuo, Lei

    2015-01-01

    This paper presents an ultra-low embedded power temperature sensor for passive RFID tags. The temperature sensor converts the temperature variation to a PTAT current, which is then transformed into a temperature-controlled frequency. A phase locked loop (PLL)-based sensor interface is employed to directly convert this temperature-controlled frequency into a corresponding digital output without an external reference clock. The fabricated sensor occupies an area of 0.021 mm2 using the TSMC 0.18 1P6M mixed-signal CMOS process. Measurement results of the embedded sensor within the tag system shows a 92 nW power dissipation under 1.0 V supply voltage at room temperature, with a sensing resolution of 0.15 °C/LSB and a sensing accuracy of −0.7/0.6 °C from −30 °C to 70 °C after 1-point calibration at 30 °C. PMID:25993518

  2. Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips.

    PubMed

    Deng, Fangming; He, Yigang; Li, Bing; Zhang, Lihua; Wu, Xiang; Fu, Zhihui; Zuo, Lei

    2015-01-01

    This paper presents an ultra-low embedded power temperature sensor for passive RFID tags. The temperature sensor converts the temperature variation to a PTAT current, which is then transformed into a temperature-controlled frequency. A phase locked loop (PLL)-based sensor interface is employed to directly convert this temperature-controlled frequency into a corresponding digital output without an external reference clock. The fabricated sensor occupies an area of 0.021 mm2 using the TSMC 0.18 1P6M mixed-signal CMOS process. Measurement results of the embedded sensor within the tag system shows a 92 nW power dissipation under 1.0 V supply voltage at room temperature, with a sensing resolution of 0.15 °C/LSB and a sensing accuracy of -0.7/0.6 °C from -30 °C to 70 °C after 1-point calibration at 30 °C. PMID:25993518

  3. Digital Epidemiology

    PubMed Central

    Salathé, Marcel; Bengtsson, Linus; Bodnar, Todd J.; Brewer, Devon D.; Brownstein, John S.; Buckee, Caroline; Campbell, Ellsworth M.; Cattuto, Ciro; Khandelwal, Shashank; Mabry, Patricia L.; Vespignani, Alessandro

    2012-01-01

    Mobile, social, real-time: the ongoing revolution in the way people communicate has given rise to a new kind of epidemiology. Digital data sources, when harnessed appropriately, can provide local and timely information about disease and health dynamics in populations around the world. The rapid, unprecedented increase in the availability of relevant data from various digital sources creates considerable technical and computational challenges. PMID:22844241

  4. Using high frame rate CMOS sensors for three-dimensional eye tracking.

    PubMed

    Clarke, A H; Ditterich, J; Drüen, K; Schönfeld, U; Steineke, C

    2002-11-01

    A novel three-dimensional eye tracker is described and its performance evaluated. In contrast to previous devices based on conventional video standards, the present eye tracker is based on programmable CMOS image sensors, interfaced directly to digital processing circuitry to permit real-time image acquisition and processing. This architecture provides a number of important advantages, including image sampling rates of up to 400/sec measurement, direct pixel addressing for preprocessing and acquisition,and hard-disk storage of relevant image data. The reconfigurable digital processing circuitry also facilitates inline optmization of the front-end, time-critical processes. The primary acquisition algorithm for tracking the pupil and other eye features is designed around the generalized Hough transform. The tracker permits comprehensive measurement of eye movement (three degrees of freedom) and head movement (six degrees of freedom), and thus provides the basis for many types of vestibulo-oculomotor and visual research. The device has been qualified by the German Space Agency (DLR) and NASA for deployment on the International Space Station. It is foreseen that the device will be used together with appropriate stimulus generators as a general purpose facility for visual and vestibular experiments. Initial verification studies with an artificial eye demonstrate a measurement resolution of better than 0.1 degrees in all three components (i.e.,system noise for each of the components measured as 0.006 degrees H, 0.005 degrees V, and 0.016 degrees T. Over a range of +/-20 degrees eye rotation, linearity was found to be <0.5% (H), <0.5% (V), and <2.0% (T). A comparison with the scleral search coil technique yielded near equivalent values for the system noise and the thickness of Listing's plane. PMID:12564559

  5. Digital Collections, Digital Libraries & the Digitization of Cultural Heritage Information.

    ERIC Educational Resources Information Center

    Lynch, Clifford

    2002-01-01

    Discusses digital collections and digital libraries. Topics include broadband availability; digital rights protection; content, both non-profit and commercial; digitization of cultural content; sustainability; metadata harvesting protocol; infrastructure; authorship; linking multiple resources; data mining; digitization of reference works;…

  6. Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations

    NASA Astrophysics Data System (ADS)

    Fukazawa, Mitsuya; Kurimoto, Masanori; Akiyama, Rei; Takata, Hidehiro; Nagata, Makoto

    Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.

  7. SOI CMOS Imager with Suppression of Cross-Talk

    NASA Technical Reports Server (NTRS)

    Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

    2009-01-01

    A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

  8. A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

    PubMed Central

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2012-01-01

    Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

  9. 77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-12-14

    ... (``CalTech''). 77 FR 33488 (June 6, 2012). The complaint alleged violations of section 337 of the Tariff... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations... importation, and the sale within the United States after importation of certain CMOS image sensors...

  10. 77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-06

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to... States after importation of certain CMOS image sensors and products containing same by reason of... image sensors and products containing same that infringe one or more of claims 1 and 2 of the...

  11. CMOS IC fault models, physical defect coverage, and I sub DDQ testing

    SciTech Connect

    Fritzemeier, R.R.; Soden, J.M. ); Hawkins, C.F. . Dept. of Electrical and Computer Engineering)

    1991-01-01

    The development of the stuck-at fault (SAF) model is reviewed with emphasis on its relationship to CMOS integrated circuit (IC) technologies. The ability of the SAF model to represent common physical defects in CMOS ICs is evaluated. A test strategy for defect detection, which includes I{sub DDQ} testing is presented. 16 refs., 4 figs.

  12. Architecture for a 1-GHz Digital RADAR

    NASA Technical Reports Server (NTRS)

    Mallik, Udayan

    2011-01-01

    An architecture for a Direct RF-digitization Type Digital Mode RADAR was developed at GSFC in 2008. Two variations of a basic architecture were developed for use on RADAR imaging missions using aircraft and spacecraft. Both systems can operate with a pulse repetition rate up to 10 MHz with 8 received RF samples per pulse repetition interval, or at up to 19 kHz with 4K received RF samples per pulse repetition interval. The first design describes a computer architecture for a Continuous Mode RADAR transceiver with a real-time signal processing and display architecture. The architecture can operate at a high pulse repetition rate without interruption for an infinite amount of time. The second design describes a smaller and less costly burst mode RADAR that can transceive high pulse repetition rate RF signals without interruption for up to 37 seconds. The burst-mode RADAR was designed to operate on an off-line signal processing paradigm. The temporal distribution of RF samples acquired and reported to the RADAR processor remains uniform and free of distortion in both proposed architectures. The majority of the RADAR's electronics is implemented in digital CMOS (complementary metal oxide semiconductor), and analog circuits are restricted to signal amplification operations and analog to digital conversion. An implementation of the proposed systems will create a 1-GHz, Direct RF-digitization Type, L-Band Digital RADAR--the highest band achievable for Nyquist Rate, Direct RF-digitization Systems that do not implement an electronic IF downsample stage (after the receiver signal amplification stage), using commercially available off-the-shelf integrated circuits.

  13. Silicide Nanowires for Low-Resistance CMOS Transistor Contacts.

    NASA Astrophysics Data System (ADS)

    Zollner, Stefan

    2007-03-01

    Transition metal (TM) silicide nanowires are used as contacts for modern CMOS transistors. (Our smallest wires are ˜20 nm thick and ˜50 nm wide.) While much research on thick TM silicides was conducted long ago, materials perform differently at the nanoscale. For example, the usual phase transformation sequences (e.g., Ni, Ni2Si, NiSi, NiSi2) for the reaction of thick metal films on Si no longer apply to nanostructures, because the surface and interface energies compete with the bulk energy of a given crystal structure. Therefore, a NiSi film will agglomerate into hemispherical droplets of NiSi by annealing before it reaches the lowest-energy (NiSi2) crystalline structure. These dynamics can be tuned by addition of impurities (such as Pt in Ni). The Si surface preparation is also a more important factor for nanowires than for silicidation of thick TM films. Ni nanowires formed on Si surfaces that were cleaned and amorphized by sputtering with Ar ions have a tendency to form NiSi2 pyramids (``spikes'') even at moderate temperatures (˜400^oC), while similar Ni films formed on atomically clean or hydrogen-terminated Si form uniform NiSi nanowires. Another issue affecting TM silicides is the barrier height between the silicide contact and the silicon transistor. For most TM silicides, the Fermi level of the silicide is aligned with the center of the Si band gap. Therefore, silicide contacts experience Schottky barrier heights of around 0.5 eV for both n-type and p-type Si. The resulting contact resistance becomes a significant term for the overall resistance of modern CMOS transistors. Lowering this contact resistance is an important goal in CMOS research. New materials are under investigation (for example PtSi, which has a barrier height of only 0.3 eV to p-type Si). This talk will describe recent results, with special emphasis on characterization techniques and electrical testing useful for the development of silicide nanowires for CMOS contacts. In collaboration

  14. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    PubMed Central

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  15. Performance Analysis of Visible Light Communication Using CMOS Sensors

    PubMed Central

    Do, Trong-Hop; Yoo, Myungsik

    2016-01-01

    This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR), is formulated. Finally, a simulation is conducted to verify the analysis. PMID:26938535

  16. Silicon nanowires integrated with CMOS circuits for biosensing application

    NASA Astrophysics Data System (ADS)

    Jayakumar, G.; Asadollahi, A.; Hellström, P.-E.; Garidis, K.; Östling, M.

    2014-08-01

    We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

  17. The DUV Stability of Superlattice-Doped CMOS Detector Arrays

    NASA Technical Reports Server (NTRS)

    Hoenk, M. E.; Carver, A. G.; Jones, T.; Dickie, M.; Cheng, P.; Greer, H. F.; Nikzad, S.; Sgro, J.; Tsur, S.

    2013-01-01

    JPL and Alacron have recently developed a high performance, DUV camera with a superlattice doped CMOS imaging detector. Supperlattice doped detectors achieve nearly 100% internal quantum efficiency in the deep and far ultraviolet, and a single layer, Al2O3 antireflection coating enables 64% external quantum efficiency at 263nm. In lifetime tests performed at Applied Materials using 263 nm pulsed, solid state and 193 nm pulsed excimer laser, the quantum efficiency and dark current of the JPL/Alacron camera remained stable to better than 1% precision during long-term exposure to several billion laser pulses, with no measurable degradation, no blooming and no image memory at 1000 fps.

  18. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    PubMed

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-07-10

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  19. 120-MHz BiCMOS superscalar RISC processor

    NASA Astrophysics Data System (ADS)

    Tanaka, Shigeya; Hotta, Takashi; Murabayashi, Fumio; Yamada, Hiromichi; Yoshida, Shoji; Shimamura, Kotaro; Katsura, Koyo; Bandoh, Tadaaki; Ikeda, Koichi; Matsubara, Kenji

    1994-04-01

    A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm x 16.5 mm, and utilizes 3.3 V/0.5 micron BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.

  20. Defect classes: An overdue paradigm for CMOS IC testing

    NASA Astrophysics Data System (ADS)

    Hawkins, C. F.; Soden, J. M.; Righter, A. W.; Ferguson, F. J.

    The IC test industry has struggled for more than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS IC's that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the test strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and test facilities and from public literature. We describe test pattern requirements for each defect class and propose a test paradigm.

  1. Design and optimization of BCCD in CMOS technology

    NASA Astrophysics Data System (ADS)

    Gao, Jing; Li, Yi; Gao, Zhi-yuan; Luo, Tao

    2016-09-01

    This paper optimizes the buried channel charge-coupled device (BCCD) structure fabricated by complementary metal oxide semiconductor (CMOS) technology. The optimized BCCD has advantages of low noise, high integration and high image quality. The charge transfer process shows that interface traps, weak fringing fields and potential well between adjacent gates all cause the decrease of charge transfer efficiency ( CTE). CTE and well capacity are simulated with different operating voltages and gap sizes. CTE can achieve 99.999% and the well capacity reaches up to 25 000 electrons for the gap size of 130 nm and the maximum operating voltage of 3 V.

  2. Extrinsic parameter extraction and RF modelling of CMOS

    NASA Astrophysics Data System (ADS)

    Alam, M. S.; Armstrong, G. A.

    2004-05-01

    An analytical approach for CMOS parameter extraction which includes the effect of parasitic resistance is presented. The method is based on small-signal equivalent circuit valid in all region of operation to uniquely extract extrinsic resistances, which can be used to extend the industry standard BSIM3v3 MOSFET model for radio frequency applications. The verification of the model was carried out through frequency domain measurements of S-parameters and direct time domain measurement at 2.4 GHz in a large signal non-linear mode of operation.

  3. Radiation-hard silicon gate bulk CMOS cell family

    SciTech Connect

    Gibbon, C. F.; Habing, D. H.; Flores, R. S.

    1980-01-01

    A radiation-hardened bulk silicon gate CMOS technology and a topologically simple, high-performance dual-port cell family utilizing this process have been demonstrated. Additional circuits, including a random logic circuit containing 4800 transistors on a 236 x 236 mil die, are presently being designed and processed. Finally, a joint design-process effort is underway to redesign the cell family in reduced design rules; this results in a factor of 2.5 cell size reduction and a factor of 3 decrease in chip interconnect area. Cell performance is correspondingly improved.

  4. Dynamic SVL and body bias for low leakage power and high performance in CMOS digital circuits

    NASA Astrophysics Data System (ADS)

    Deshmukh, Jyoti; Khare, Kavita

    2012-12-01

    In this article, a new complementary metal oxide semiconductor design scheme called dynamic self-controllable voltage level (DSVL) is proposed. In the proposed scheme, leakage power is controlled by dynamically disconnecting supply to inactive blocks and adjusting body bias to further limit leakage and to maintain performance. Leakage power measurements at 1.8 V, 75°C demonstrate power reduction by 59.4% in case of 1 bit full adder and by 43.0% in case of a chain of four inverters using SVL circuit as a power switch. Furthermore, we achieve leakage power reduction by 94.7% in case of 1 bit full adder and by 91.8% in case of a chain of four inverters using dynamic body bias. The forward body bias of 0.45 V applied in active mode improves the maximum operating frequency by 16% in case of 1 bit full adder and 5.55% in case of a chain of inverters. Analysis shows that additional benefits of using the DSVL and body bias include high performance, low leakage power consumption in sleep mode, single threshold implementation and state retention even in standby mode.

  5. Experiment on digital CDS with 33-M pixel 120-fps super hi-vision image sensor

    NASA Astrophysics Data System (ADS)

    Yonai, J.; Yasue, T.; Kitamura, K.; Hayashida, T.; Watabe, T.; Shimamoto, H.; Kawahito, S.

    2014-03-01

    We have developed a CMOS image sensor with 33 million pixels and 120 frames per second (fps) for Super Hi-Vision (SHV:8K version of UHDTV). There is a way to reduce the fixed pattern noise (FPN) caused in CMOS image sensors by using digital correlated double sampling (digital CDS), but digital CDS methods need high-speed analog-to-digital conversion and are not applicable to conventional UHDTV image sensors due to their speed limit. Our image sensor, on the other hand, has a very fast analog-to-digital converter (ADC) using "two-stage cyclic ADC" architecture that is capable of being driven at 120-fps, which is double the normal frame rate for TV. In this experiment, we performed experimental digital CDS using the high-frame rate UHDTV image sensor. By reading the same row twice at 120-fps and subtracting dark pixel signals from accumulated pixel signals, we obtained a 60-fps equivalent video signal with digital noise reduction. The results showed that the VFPN was effectively reduced from 24.25 e-rms to 0.43 e-rms.

  6. Closed-loop adaptive optics using a CMOS image quality metric sensor

    NASA Astrophysics Data System (ADS)

    Ting, Chueh; Rayankula, Aditya; Giles, Michael K.; Furth, Paul M.

    2006-08-01

    When compared to a Shack-Hartmann sensor, a CMOS image sharpness sensor has the advantage of reduced complexity in a closed-loop adaptive optics system. It also has the potential to be implemented as a smart sensor using VLSI technology. In this paper, we present a novel adaptive optics testbed that uses a CMOS sharpness imager built in the New Mexico State University (NMSU) Electro-Optics Research Laboratory (EORL). The adaptive optics testbed, which includes a CMOS image quality metric sensor and a 37-channel deformable mirror, has the capability to rapidly compensate higher-order phase aberrations. An experimental performance comparison of the pinhole image sharpness feedback method and the CMOS imager is presented. The experimental data shows that the CMOS sharpness imager works well in a closed-loop adaptive optics system. Its overall performance is better than that of the pinhole method, and it has a fast response time.

  7. Damage effect on CMOS detector irradiated by single-pulse laser

    NASA Astrophysics Data System (ADS)

    Guo, Feng; Zhu, Rongzhen; Wang, Ang; Cheng, Xiang'ai

    2013-09-01

    Imaging systems are widespread observation tools used to fulfill various functions such as recognition, detection and identification. These devices such as CMOS and CCD can be damaged by laser. It is very important to study the damage mechanism of CMOS and CCD. Previous studies focused on the interference and damage of CCD. There were only a few researches on the interaction of CMOS and the laser. In this paper, using a 60ns, 1064 nm single-pulse laser to radiate the front illuminated CMOS detector, the typical experiment phenomena were observed and the corresponding energy density thresholds were measured. According to the experiment phenomena, hard damage process of CMOS can be divided into 3 stages. Based on the structure and working principle of CMOS, studying the damage mechanism of 3 stages by theoretical analysis, point damage was caused by the increase in leakage current due to structural defects resulting from thermal effects, half black line damage and black lines cross damage were caused by signal interruption due to that the device circuit fuses were cut. Enhancing the laser energy density, the damaged area expanded. Even if the laser energy density reached 1.95 J/cm2, black lines has covered most of the detector pixels, the detector still not completely lapsed, the undamaged area can imaging due to that pixels of CMOS were separated with each other. Experiments on CMOS by laser pulses at the wavelength of 1064 nm and the pulse duration in 25ps was carried out, then the thresholds with different pulse durations were measured and compared. Experiments on CMOS by fs pulsed laser at the frequency of 1 Hz, 10 Hz and 1000 Hz were carried out, respectively, the results showed that a high-repetition-rate laser was easier to damage CMOS compared to single-shot laser.

  8. Digital Radiography

    NASA Technical Reports Server (NTRS)

    1986-01-01

    System One, a digital radiography system, incorporates a reusable image medium (RIM) which retains an image. No film is needed; the RIM is read with a laser scanner, and the information is used to produce a digital image on an image processor. The image is stored on an optical disc. System allows the radiologist to "dial away" unwanted images to compare views on three screens. It is compatible with existing equipment and cost efficient. It was commercialized by a Stanford researcher from energy selective technology developed under a NASA grant.

  9. CMOS mm-wave transceivers for Gbps wireless communication

    NASA Astrophysics Data System (ADS)

    Baoyong, Chi; Zheng, Song; Lixue, Kuang; Haikun, Jia; Xiangyu, Meng; Zhihua, Wang

    2016-07-01

    The challenges in the design of CMOS millimeter-wave (mm-wave) transceiver for Gbps wireless communication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the bandwidth expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier (PA) and self-healing technique are introduced to improve the PA's average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers. Project supported in part by the National Natural Science Foundation of China (No. 61331003).

  10. Illumination robust change detection with CMOS imaging sensors

    NASA Astrophysics Data System (ADS)

    Rengarajan, Vijay; Gupta, Sheetal B.; Rajagopalan, A. N.; Seetharaman, Guna

    2015-05-01

    Change detection between two images in the presence of degradations is an important problem in the computer vision community, more so for the aerial scenario which is particularly challenging. Cameras mounted on moving platforms such as aircrafts or drones are subject to general six-dimensional motion as the motion is not restricted to a single plane. With CMOS cameras increasingly in vogue due to their low power consumption, the inevitability of rolling-shutter (RS) effect adds to the challenge. This is caused by sequential exposure of rows in CMOS cameras unlike conventional global shutter cameras where all pixels are exposed simultaneously. The RS effect is particularly pronounced in aerial imaging since each row of the imaging sensor is likely to experience a different motion. For fast-moving platforms, the problem is further compounded since the rows are also affected by motion blur. Moreover, since the two images are shot at different times, illumination differences are common. In this paper, we propose a unified computational framework that elegantly exploits the scarcity constraint to deal with the problem of change detection in images degraded by RS effect, motion blur as well as non-global illumination differences. We formulate an optimization problem where each row of the distorted image is approximated as a weighted sum of the corresponding rows in warped versions of the reference image due to camera motion within the exposure period to account for geometric as well as photometric differences. The method has been validated on both synthetic and real data.

  11. Fabrication and Characterization of CMOS-MEMS Magnetic Microsensors

    PubMed Central

    Hsieh, Chen-Hsuan; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    This study investigates the design and fabrication of magnetic microsensors using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process. The magnetic sensor is composed of springs and interdigitated electrodes, and it is actuated by the Lorentz force. The finite element method (FEM) software CoventorWare is adopted to simulate the displacement and capacitance of the magnetic sensor. A post-CMOS process is utilized to release the suspended structure. The post-process uses an anisotropic dry etching to etch the silicon dioxide layer and an isotropic dry etching to remove the silicon substrate. When a magnetic field is applied to the magnetic sensor, it generates a change in capacitance. A sensing circuit is employed to convert the capacitance variation of the sensor into the output voltage. The experimental results show that the output voltage of the magnetic microsensor varies from 0.05 to 1.94 V in the magnetic field range of 5–200 mT. PMID:24172287

  12. High-Q CMOS-integrated photonic crystal microcavity devices.

    PubMed

    Mehta, Karan K; Orcutt, Jason S; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J

    2014-01-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300-9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems.

  13. High-Q CMOS-integrated photonic crystal microcavity devices

    NASA Astrophysics Data System (ADS)

    Mehta, Karan K.; Orcutt, Jason S.; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J.

    2014-02-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300-9,300 one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems.

  14. CMOS: Efficient Clustered Data Monitoring in Sensor Networks

    PubMed Central

    2013-01-01

    Tiny and smart sensors enable applications that access a network of hundreds or thousands of sensors. Thus, recently, many researchers have paid attention to wireless sensor networks (WSNs). The limitation of energy is critical since most sensors are battery-powered and it is very difficult to replace batteries in cases that sensor networks are utilized outdoors. Data transmission between sensor nodes needs more energy than computation in a sensor node. In order to reduce the energy consumption of sensors, we present an approximate data gathering technique, called CMOS, based on the Kalman filter. The goal of CMOS is to efficiently obtain the sensor readings within a certain error bound. In our approach, spatially close sensors are grouped as a cluster. Since a cluster header generates approximate readings of member nodes, a user query can be answered efficiently using the cluster headers. In addition, we suggest an energy efficient clustering method to distribute the energy consumption of cluster headers. Our simulation results with synthetic data demonstrate the efficiency and accuracy of our proposed technique. PMID:24459444

  15. Fabrication of a miniature CMOS-based optical biosensor.

    PubMed

    Ho, Wei-Jen; Chen, Jung-Sheng; Ker, Ming-Dou; Wu, Tung-Kung; Wu, Chung-Yu; Yang, Yuh-Shyong; Li, Yaw-Kuen; Yuan, Chiun-Jye

    2007-06-15

    This work presents a novel, miniature optical biosensor by immobilizing horseradish peroxidase (HRP) or the HRP/glucose oxidase (GOx) coupled enzyme pair on a CMOS photosensing chip with a detection area of 0.5 mm x 0.5 mm. A highly transparent TEOS/PDMS Ormosil is used to encapsulate and immobilize enzymes on the surface of the photosensor. Interestingly, HRP-catalyzed luminol luminescence can be detected in real time on optical H(2)O(2) and glucose biosensors. The minimum reaction volume of the developed optical biosensors is 10 microL. Both optical H(2)O(2) and glucose biosensors have an optimal operation temperature and pH of 20-25 degrees C and pH 8.4, respectively. The linear dynamic range of optical H(2)O(2) and glucose biosensors is 0.05-20 mM H(2)O(2) and 0.5-20 mM glucose, respectively. The miniature optical glucose biosensor also exhibits good reproducibility with a relative standard deviation of 4.3%. Additionally, ascorbic acid and uric acid, two major interfering substances in the serum during electrochemical analysis, cause only slight interference with the fabricated optical glucose biosensor. In conclusion, the CMOS-photodiode-based optical biosensors proposed herein have many advantages, such as a short detection time, a small sample volume requirement, high reproducibility and wide dynamic range.

  16. BiCMOS-integrated photodiode exploiting drift enhancement

    NASA Astrophysics Data System (ADS)

    Swoboda, Robert; Schneider-Hornstein, Kerstin; Wille, Holger; Langguth, Gernot; Zimmermann, Horst

    2014-08-01

    A vertical pin photodiode with a thick intrinsic layer is integrated in a 0.5-μm BiCMOS process. The reverse bias of the photodiode can be increased far above the circuit supply voltage, enabling a high-drift velocity. Therefore, a highly efficient and very fast photodiode is achieved. Rise/fall times down to 94 ps/141 ps at a bias of 17 V were measured for a wavelength of 660 nm. The bandwidth was increased from 1.1 GHz at 3 V to 2.9 GHz at 17 V due to the drift enhancement. A quantum efficiency of 85% with a 660-nm light was verified. The technological measures to avoid negative effects on an NPN transistor due to the Kirk effect caused by the low-doped I-layer epitaxy are described. With a high-energy collector implant, the NPN transit frequency is held above 20 GHz. CMOS devices are unaffected. This photodiode is suitable for a wide variety of high-sensitivity optical sensor applications, for optical communications, for fiber-in-the-home applications, and for optical interconnects.

  17. CMOS prototype for retinal prosthesis applications with analog processing

    NASA Astrophysics Data System (ADS)

    Castillo-Cabrera, G.; García-Lamont, J.; Reyes-Barranca, M. A.; Matsumoto-Kuwabara, Y.; Moreno-Cadenas, J. A.; Flores-Nava, L. M.

    2014-12-01

    A core architecture for analog processing, which emulates a retina's receptive field, is presented in this work. A model was partially implemented and built on CMOS standard technology through MOSIS. It considers that the receptive field is the basic unit for image processing in the visual system. That is why the design is concerned on a partial solution of receptive field properties in order to be adapted in the future as an aid to people with retinal diseases. A receptive field is represented by an array of 3×3 pixels. Each pixel carries out a process based on four main operations. This means that image processing is developed at pixel level. Operations involved are: (1) photo-transduction by photocurrent integration, (2) signal averaging from eight neighbouring pixels executed by a neu-NMOS (ν-NMOS) neuron, (3) signal average gradient between central pixel and the average value from the eight neighbouring pixels (this gradient is performed by a comparator) and finally (4) a pulse generator. Each one of these operations gives place to circuital blocks which were built on 0.5 μm CMOS technology.

  18. Single donor electronics and quantum functionalities with advanced CMOS technology

    NASA Astrophysics Data System (ADS)

    Jehl, Xavier; Niquet, Yann-Michel; Sanquer, Marc

    2016-03-01

    Recent progresses in quantum dots technology allow fundamental studies of single donors in various semiconductor nanostructures. For the prospect of applications figures of merits such as scalability, tunability, and operation at relatively large temperature are of prime importance. Beyond the case of actual dopant atoms in a host crystal, similar arguments hold for small enough quantum dots which behave as artificial atoms, for instance for single spin control and manipulation. In this context, this experimental review focuses on the silicon-on-insulator devices produced within microelectronics facilities with only very minor modifications to the current industrial CMOS process and tools. This is required for scalability and enabled by shallow trench or mesa isolation. It also paves the way for real integration with conventional circuits, as illustrated by a nanoscale device coupled to a CMOS circuit producing a radio-frequency drive on-chip. At the device level we emphasize the central role of electrostatics in etched silicon nanowire transistors, which allows to understand the characteristics in the full range from zero to room temperature.

  19. Electronic-photonic integrated circuits on the CMOS platform

    NASA Astrophysics Data System (ADS)

    Kimerling, L. C.; Ahn, D.; Apsel, A. B.; Beals, M.; Carothers, D.; Chen, Y.-K.; Conway, T.; Gill, D. M.; Grove, M.; Hong, C.-Y.; Lipson, M.; Liu, J.; Michel, J.; Pan, D.; Patel, S. S.; Pomerene, A. T.; Rasras, M.; Sparacin, D. K.; Tu, K.-Y.; White, A. E.; Wong, C. W.

    2006-02-01

    The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

  20. Single phase dynamic CMOS PLA using charge sharing technique

    NASA Technical Reports Server (NTRS)

    Dhong, Y. B.; Tsang, C. P.

    1991-01-01

    A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

  1. Improvement to the signaling interface for CMOS pixel sensors

    NASA Astrophysics Data System (ADS)

    Shi, Zhan; Tang, Zhenan; Feng, Chong; Cai, Hong

    2016-10-01

    The development of the readout speed of CMOS pixel sensors (CPS) is motivated by the demanding requirements of future high energy physics (HEP) experiments. As the interface between CPS and the data acquisition (DAQ) system, which inputs clock from the DAQ system and outputs data from CPS, the signaling interface should also be improved in terms of data rates. Meanwhile, the power consumption of the signaling interface should be maintained as low as possible. Consequently, a reduced swing differential signaling (RSDS) driver was adopted instead of a low-voltage differential signaling (LVDS) driver to transmit data from CPS to the DAQ system. In order to increase the capability of data rates, a serial source termination technique was employed. A LVDS/RSDS receiver was employed for transmitting clock from the DAQ system to CPS. A new method of generating hysteresis and a special current comparator were used to achieve a higher speed with lower power consumption. The signaling interface was designed and submitted for fabrication in a 0.18 μm CMOS image sensor (CIS) process. Measurement results indicate that the RSDS driver and the LVDS receiver can operate correctly at a data rate of 2 Gb/s with a power consumption of 19.1 mW.

  2. High accuracy digital aging monitor based on PLL-VCO circuit

    NASA Astrophysics Data System (ADS)

    Yuejun, Zhang; Zhidi, Jiang; Pengjun, Wang; Xuelong, Zhang

    2015-01-01

    As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 × 298.94 μm2. After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%.

  3. Digital Batteries

    NASA Astrophysics Data System (ADS)

    Hubler, Alfred

    2009-03-01

    The energy density in conventional capacitors is limited by sparking. We present nano-capacitor arrays, where - like in laser diodes and quantum wells [1] - quantization prevents dielectric breakthrough. We show that the energy density and the power/weight ratio are very high, possibly larger than in hydrogen [2]. Digital batteries are a potential clean energy source for cars, laptops, and mobile devices. The technology is related to flash drives. However, because of the high energy density, safety is a concern. Digital batteries can be easily and safely charged and discharged. In the discharged state they pose no danger. Even if a charged digital battery were to explode, it would produce no radioactive waste, no long-term radiation, and probably could be designed to produce no noxious chemicals. We discuss methodologies to prevent shorts and other measures to make digital batteries safe. [1] H. Higuraskh, A. Toriumi, F. Yamaguchi, K. Kawamura, A. Hubler, Correlation Tunnel Device, U. S. Patent No. 5,679,961 (1997) [2] Alfred Hubler, http://server10.how-why.com/blog/

  4. Digital Badges

    ERIC Educational Resources Information Center

    Frederiksen, Linda

    2013-01-01

    Unlike so much of the current vocabulary in education and technology that seems to stir more confusion than clarity, most public service librarians may already have a general idea about digital badges. As visual representations of individual accomplishments, competencies or skills that are awarded by groups, institutions, or organizations, they…

  5. Digital Tidbits

    ERIC Educational Resources Information Center

    Kumaran, Maha; Geary, Joe

    2011-01-01

    Technology has transformed libraries. There are digital libraries, electronic collections, online databases and catalogs, ebooks, downloadable books, and much more. With free technology such as social websites, newspaper collections, downloadable online calendars, clocks and sticky notes, online scheduling, online document sharing, and online…

  6. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    NASA Astrophysics Data System (ADS)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

    2016-09-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  7. DynAMITe: a prototype large area CMOS APS for breast cancer diagnosis using x-ray diffraction measurements

    NASA Astrophysics Data System (ADS)

    Konstantinidis, A.; Anaxagoras, T.; Esposito, M.; Allinson, N.; Speller, R.

    2012-03-01

    X-ray diffraction studies are used to identify specific materials. Several laboratory-based x-ray diffraction studies were made for breast cancer diagnosis. Ideally a large area, low noise, linear and wide dynamic range digital x-ray detector is required to perform x-ray diffraction measurements. Recently, digital detectors based on Complementary Metal-Oxide- Semiconductor (CMOS) Active Pixel Sensor (APS) technology have been used in x-ray diffraction studies. Two APS detectors, namely Vanilla and Large Area Sensor (LAS), were developed by the Multidimensional Integrated Intelligent Imaging (MI-3) consortium to cover a range of scientific applications including x-ray diffraction. The MI-3 Plus consortium developed a novel large area APS, named as Dynamically Adjustable Medical Imaging Technology (DynAMITe), to combine the key characteristics of Vanilla and LAS with a number of extra features. The active area (12.8 × 13.1 cm2) of DynaMITe offers the ability of angle dispersive x-ray diffraction (ADXRD). The current study demonstrates the feasibility of using DynaMITe for breast cancer diagnosis by identifying six breast-equivalent plastics. Further work will be done to optimize the system in order to perform ADXRD for identification of suspicious areas of breast tissue following a conventional mammogram taken with the same sensor.

  8. Enhancement latitude of civil digital photography system by liquid crystal

    NASA Astrophysics Data System (ADS)

    Zhao, Gaoxiang; Tang, Yuanhe; Liu, Kai; Liu, Hanchen; Gao, Haiyang; Zhang, Ruixia; Liang, Yuan; Li, Qing; Yang, Xusan; Ye, Na

    2008-12-01

    In order to enhance the civil digital photography system's latitude, a kind of new structure is put forward which is made the liquid crystal plate coupled to CCD/CMOS (Charge Coupled Device/Complementary Metal Oxide Semiconductor) sensitive chip in this paper. We call this structure chip is LCCCD (liquid crystal CCD). This new system's key is proximity coupled a high precision HTPS (Low Temperature Poly-Silicon) liquid crystal plate on the foundation of current CCD/CMOS chip; each pixel on the liquid crystal plate corresponds with the pixel on CCD/CMOS one by one. They compose the new sensitive photosensitive chip that can control the each pixel's ratio of photoelectric conversion by changing each liquid crystal unit's transmittance. This paper expounds this system's structure as well as various modules' cooperation mode and the process of achieving the aim. Through analysis original image by common camera and the same image by LCCCD camera, these results are obtained: the image is changed directly on the physical level by the new system is much better than produces by post treatment, moreover the system can rectify images by 10bit precision, and the imaging latitude has been enhanced more than 5EV (EV is exposure level).

  9. Flexible All-Digital Receiver for Bandwidth Efficient Modulations

    NASA Technical Reports Server (NTRS)

    Gray, Andrew; Srinivasan, Meera; Simon, Marvin; Yan, Tsun-Yee

    2000-01-01

    An all-digital high data rate parallel receiver architecture developed jointly by Goddard Space Flight Center and the Jet Propulsion Laboratory is presented. This receiver utilizes only a small number of high speed components along with a majority of lower speed components operating in a parallel frequency domain structure implementable in CMOS, and can currently process up to 600 Mbps with standard QPSK modulation. Performance results for this receiver for bandwidth efficient QPSK modulation schemes such as square-root raised cosine pulse shaped QPSK and Feher's patented QPSK are presented, demonstrating the flexibility of the receiver architecture.

  10. Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

    PubMed

    Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

    2014-02-01

    Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

  11. Single-Chip CMUT-on-CMOS Front-End System for Real-Time Volumetric IVUS and ICE Imaging

    PubMed Central

    Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F. Levent

    2014-01-01

    Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of CMUT arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-µm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-µm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single-chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex-vivo chicken heart sample. The measured axial and lateral point resolutions are 92 µm and 251 µm, respectively. We successfully acquired volumetric imaging data from the ex-vivo chicken heart with 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce real-time volumetric images with image quality and speed suitable for catheter based clinical applications. PMID:24474131

  12. Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

    NASA Technical Reports Server (NTRS)

    Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

    2009-01-01

    In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

  13. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

    PubMed

    Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

    2012-01-11

    Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme.

  14. Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction

    PubMed Central

    Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

    2015-01-01

    A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology. PMID:26184222

  15. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    PubMed Central

    Guo, Nan; Cheung, Ka Wai; Wong, Hiu Tung; Ho, Derek

    2014-01-01

    Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art. PMID:25365460

  16. Digital psychiatry.

    PubMed

    Tang, S; Helmeste, D

    2000-02-01

    The American managed care movement has been viewed as a big experiment and is being watched closely by the rest of the world. In the meanwhile, computer-based information technology (IT) is changing the practice of medicine, much more rapidly than managed care. A New World of digitized knowledge and information has been created. Although literature on IT in psychiatry is largely absent in peer-reviewed psychiatric journals, IT is finding its way into all aspects of medicine, particularly psychiatry. Telepsychiatry programs are becoming very popular. At the same time, medical information sites are flourishing and evolving into a new health-care industry. Patient-physician information asymmetry is decreasing as patients are gaining easy access to medical information hitherto only available to professionals. Thus, psychiatry is facing another paradigm shift, at a time when most attention has been focused on managed care. In this new digital world, knowledge and information are no longer the sole property of professionals. Value will migrate from traditional in-person office-based therapy to digital clinical products, from in-person library search and classroom didactic instruction to interactive on-line searches and distance learning. In this time of value migration, psychiatrists have to determine what their 'distinctive competence' is and where best to add value in the health-care delivery value chain. The authors assess the impact of IT on clinical psychiatry and review how clinical practice, education and research in psychiatry are expected to change in this emerging digital world. PMID:15558872

  17. X-ray imaging using digital cameras

    NASA Astrophysics Data System (ADS)

    Winch, Nicola M.; Edgar, Andrew

    2012-03-01

    The possibility of using the combination of a computed radiography (storage phosphor) cassette and a semiprofessional grade digital camera for medical or dental radiography is investigated. We compare the performance of (i) a Canon 5D Mk II single lens reflex camera with f1.4 lens and full-frame CMOS array sensor and (ii) a cooled CCD-based camera with a 1/3 frame sensor and the same lens system. Both systems are tested with 240 x 180 mm cassettes which are based on either powdered europium-doped barium fluoride bromide or needle structure europium-doped cesium bromide. The modulation transfer function for both systems has been determined and falls to a value of 0.2 at around 2 lp/mm, and is limited by light scattering of the emitted light from the storage phosphor rather than the optics or sensor pixelation. The modulation transfer function for the CsBr:Eu2+ plate is bimodal, with a high frequency wing which is attributed to the light-guiding behaviour of the needle structure. The detective quantum efficiency has been determined using a radioisotope source and is comparatively low at 0.017 for the CMOS camera and 0.006 for the CCD camera, attributed to the poor light harvesting by the lens. The primary advantages of the method are portability, robustness, digital imaging and low cost; the limitations are the low detective quantum efficiency and hence signal-to-noise ratio for medical doses, and restricted range of plate sizes. Representative images taken with medical doses are shown and illustrate the potential use for portable basic radiography.

  18. An Approach for Self-Timed Synchronous CMOS Circuit Design

    NASA Technical Reports Server (NTRS)

    Walker, Alvernon; Lala, Parag K.

    2001-01-01

    In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.

  19. Development of a radiation-hard CMOS process

    NASA Technical Reports Server (NTRS)

    Power, W. L.

    1983-01-01

    It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

  20. Micro-lens maker equation of a CMOS image sensor

    NASA Astrophysics Data System (ADS)

    Wu, Yang

    2007-09-01

    The demand of a large resolution CMOS image sensor (CIS) in a small package drives the pixel pitch size down to the neighborhood of 2 μm. Double-micro-lens (ML) structure is a promising technology to obtain the high focusing capability required by such a small pixel. In this work, an optical model of a double-ML is derived from the well-known lens maker equation. This model predicts the critical back focal length (BFL) and the effective focal length (EFL) of the double-ML embedded in the Back-End-Of-The-Line (BEOL) stack. Explained by this model, a design guideline is provided to optimize the amount of light collected by the photo diode area for a good quantum efficiency (QE), which is crucial to the sensitivity of the sensor.

  1. Rapid Bacterial Detection via an All-Electronic CMOS Biosensor

    PubMed Central

    Nikkhoo, Nasim; Cumby, Nichole; Gulak, P. Glenn; Maxwell, Karen L.

    2016-01-01

    The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections. PMID:27618185

  2. A 20 MHz CMOS reorder buffer for a superscalar microprocessor

    NASA Technical Reports Server (NTRS)

    Lenell, John; Wallace, Steve; Bagherzadeh, Nader

    1992-01-01

    Superscalar processors can achieve increased performance by issuing instructions out-of-order from the original sequential instruction stream. Implementing an out-of-order instruction issue policy requires a hardware mechanism to prevent incorrectly executed instructions from updating register values. A reorder buffer can be used to allow a superscalar processor to issue instructions out-of-order and maintain program correctness. This paper describes the design and implementation of a 20MHz CMOS reorder buffer for superscalar processors. The reorder buffer is designed to accept and retire two instructions per cycle. A full-custom layout in 1.2 micron has been implemented, measuring 1.1058 mm by 1.3542 mm.

  3. Triple inverter pierce oscillator circuit suitable for CMOS

    DOEpatents

    Wessendorf; Kurt O.

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  4. An improved equivalent simulation model for CMOS integrated Hall plates.

    PubMed

    Xu, Yue; Pan, Hong-Bin

    2011-01-01

    An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model's simulation results are in good agreement with the classic experimental results reported in the literature.

  5. An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates

    PubMed Central

    Xu, Yue; Pan, Hong-Bin

    2011-01-01

    An improved equivalent simulation model for a CMOS-integrated Hall plate is described in this paper. Compared with existing models, this model covers voltage dependent non-linear effects, geometrical effects, temperature effects and packaging stress influences, and only includes a small number of physical and technological parameters. In addition, the structure of this model is relatively simple, consisting of a passive network with eight non-linear resistances, four current-controlled voltage sources and four parasitic capacitances. The model has been written in Verilog-A hardware description language and it performed successfully in a Cadence Spectre simulator. The model’s simulation results are in good agreement with the classic experimental results reported in the literature. PMID:22163955

  6. Operational characteristics of a CMOS microprocessor system at cryogenic temperatures

    NASA Astrophysics Data System (ADS)

    Deen, M. J.; Chan, C. Y.; Fong, N.

    In this Paper, the variation of the maximum input clock frequency versus temperature of a CMOS microprocessor with a 'piggy-back' EPROM is described. The maximum input frequency for reliable operation increased from 19 to 33 MHz as the temperature was lowered from 300 to 77 K, and there was a corresponding increase in the power dissipated from 18 to 25 mW using a supply of 5 V. The measurements were repeatable even after thermal cycling more than 10 times and showed no hysteresis on cooling down to 77 K or warming up to 300 K. The results obtained can be qualitatively explained as due to a combination of effects including the increase in the carriers' mobilities, the decrease in junction capacitance, and the decrease in the interconnect resistance with decreasing temperature.

  7. Accelerated life testing effects on CMOS microcircuit characteristics

    NASA Technical Reports Server (NTRS)

    1980-01-01

    The 250 C, 200C and 125C accelerated tests are described. The wear-out distributions from the 250 and 200 C tests were used to estimate the activation energy between the two test temperatures. The duration of the 125 C test was not sufficient to bring the test devices into the wear-out region. It was estimated that, for the most complex of the three devices types, the activation energy between 200 C and 125 C should be at least as high as that between 250 C and 200 C. The practicality of the use of high temperature for the accelerated life tests from the point of view of durability of equipment is assessed. Guidlines for the development of accelerated life-test conditions are proposed. The use of the silicon nitride overcoat to improve the high temperature accelerated life-test characteristics of CMOS microcircuits is described.

  8. State assignment approach to asynchronous CMOS circuit design

    NASA Astrophysics Data System (ADS)

    Kantabutra, Vitit; Andreou, Andreas G.

    1994-04-01

    We present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching events is reduced and dynamic power dissipation may also be reduced. Our approach is suitable for asynchronous sequential circuits that are designed from flow tables or state transition diagrams. The proposed approach may also be useful for designing synchronous circuits, but explorations into the subject of clock power would be necessary to determine its usefulness.

  9. Failure analysis of a half-micron CMOS IC technology

    SciTech Connect

    Liang, A.Y.; Tangyunyong, P.; Bennett, R.S.; Flores, R.S.

    1996-08-01

    We present the results of recent failure analysis of an advanced, 0.5 {mu}m, fully planarized, triple metallization CMOS technology. A variety of failure analysis (FA) tools and techniques were used to localize and identify defects generated by wafer processing. These include light (photon) emission microscopy (LE), fluorescent microthermal imaging (FMI), focused ion beam cross sectioning, SEM/voltage contrast imaging, resistive contrast imaging (RCI), and e-beam testing using an IDS-5000 with an HP 82000. The defects identified included inter- and intra-metal shorts, gate oxide shorts due to plasma processing damage, and high contact resistance due to the contact etch and deposition process. Root causes of these defects were determined and corrective action was taken to improve yield and reliability.

  10. Variation in SEU sensitivity of dose-imprinted CMOS SRAMs

    NASA Technical Reports Server (NTRS)

    Stassinopoulos, E. G.; Brucker, G. J.; Van Gunten, O.; Kim, H. S.

    1989-01-01

    The authors report on an experimental study of dose-induced changes in SEU (single-event-upset) sensitivity of CMOS static RAMs. Two time regimes were investigated following exposure of memories to cobalt-60 gamma rays: the near term, within a few hours after exposure, and the long term, after many days. Samples were irradiated both at room and at liquid nitrogen temperatures. The latter procedure was used in order to freeze in the damage state until SEU measurements could be made prior to annealing. Results show that memories damaged by dose are more sensitive to upsets by heavy ions. The induced changes are substantial: threshold linear energy transfer (LET) values decreased by as much as 46 percent and asymptotic cross sections increased by factors of two to four (unannealed samples).

  11. Rapid Bacterial Detection via an All-Electronic CMOS Biosensor.

    PubMed

    Nikkhoo, Nasim; Cumby, Nichole; Gulak, P Glenn; Maxwell, Karen L

    2016-01-01

    The timely and accurate diagnosis of infectious diseases is one of the greatest challenges currently facing modern medicine. The development of innovative techniques for the rapid and accurate identification of bacterial pathogens in point-of-care facilities using low-cost, portable instruments is essential. We have developed a novel all-electronic biosensor that is able to identify bacteria in less than ten minutes. This technology exploits bacteriocins, protein toxins naturally produced by bacteria, as the selective biological detection element. The bacteriocins are integrated with an array of potassium-selective sensors in Complementary Metal Oxide Semiconductor technology to provide an inexpensive bacterial biosensor. An electronic platform connects the CMOS sensor to a computer for processing and real-time visualization. We have used this technology to successfully identify both Gram-positive and Gram-negative bacteria commonly found in human infections. PMID:27618185

  12. Interferometric metrology of wafer nanotopography for advanced CMOS process integration

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Koliopoulos, Chris L.; Tang, Shouhong

    2001-12-01

    According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

  13. High-Q CMOS-integrated photonic crystal microcavity devices

    PubMed Central

    Mehta, Karan K.; Orcutt, Jason S.; Tehar-Zahav, Ofer; Sternberg, Zvi; Bafrali, Reha; Meade, Roy; Ram, Rajeev J.

    2014-01-01

    Integrated optical resonators are necessary or beneficial in realizations of various functions in scaled photonic platforms, including filtering, modulation, and detection in classical communication systems, optical sensing, as well as addressing and control of solid state emitters for quantum technologies. Although photonic crystal (PhC) microresonators can be advantageous to the more commonly used microring devices due to the former's low mode volumes, fabrication of PhC cavities has typically relied on electron-beam lithography, which precludes integration with large-scale and reproducible CMOS fabrication. Here, we demonstrate wavelength-scale polycrystalline silicon (pSi) PhC microresonators with Qs up to 60,000 fabricated within a bulk CMOS process. Quasi-1D resonators in lateral p-i-n structures allow for resonant defect-state photodetection in all-silicon devices, exhibiting voltage-dependent quantum efficiencies in the range of a few 10 s of %, few-GHz bandwidths, and low dark currents, in devices with loaded Qs in the range of 4,300–9,300; one device, for example, exhibited a loaded Q of 4,300, 25% quantum efficiency (corresponding to a responsivity of 0.31 A/W), 3 GHz bandwidth, and 30 nA dark current at a reverse bias of 30 V. This work demonstrates the possibility for practical integration of PhC microresonators with active electro-optic capability into large-scale silicon photonic systems. PMID:24518161

  14. Packaging commercial CMOS chips for lab on a chip integration.

    PubMed

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems. PMID:24682025

  15. Efficient control structures for digital programmable retinas

    NASA Astrophysics Data System (ADS)

    Bernard, Thierry M.

    2001-05-01

    A digital programmable artificial retina (PAR) is a functional extension of a CMOS imager, in which every pixel is fitted with a local ADC and a tiny digital programmable processor. From an architectural viewpoint, a PAR is an SIMD array processor with local optical input. A PAR is aimed at processing images on-site until they can be output from the array under concentrated form. The overall goal is to get compact, fast and inexpensive vision systems, in particular for robotics applications. A 256 by 256 PAR with up to a few tens bits of local memory per pixel is now within reach at reasonable cost. However, whereas the local memory size benefits quadratically from the feature size decrease, wiring density improvement can only be linear, at best. So control should become more complex with the danger of a growing proportion of the digital pixel area being devoted to instruction or address decoding. We propose efficient scalable solutions to this problem at the architectural, circuit and topological levels, which attempt to minimize both silicon area and power consumption.

  16. CMOS color image sensor with overlaid organic photoconductive layers having narrow absorption band

    NASA Astrophysics Data System (ADS)

    Takada, Shunji; Ihama, Mikio; Inuiya, Masafumi; Komatsu, Takashi; Saito, Takahiro

    2007-02-01

    At EI2006, we proposed the CMOS image sensor, which was overlaid with organic photoconductive layers in order to incorporate in it large light-capturing ability of a color film owing to its multiple-layer structure, and demonstrated the pictures taken by the trial product of the proposed CMOS image sensor overlaid with an organic layer having green sensitivity. In this study, we have tried to get the optimized spectral sensitivity for the proposed CMOS image sensor by means of the simulation to minimize the color difference between the original Macbeth chart and its reproduction with the spectral sensitivity of the sensor as a parameter. As a result, it has been confirmed that the proposed CMOS image sensor with multiple-layer structure possesses high potential capability in terms of imagecapturing efficiency when it is provided with the optimized spectral sensitivity.

  17. Design and coupled-effect simulations of CMOS micro gas sensors built on SOI thin membranes

    NASA Astrophysics Data System (ADS)

    Lu, Chih-Cheng; Udrea, Florin; Gardner, Julian W.; Setiadi, D.; Dogaru, T.; Tsai, T. H.; Covington, James A.

    2001-04-01

    This paper describes coupled-effect simulations of smart micro gas-sensors based on standard BiCMOS technology. The smart sensor features very low power consumption, high sensitivity and potential low fabrication cost achieved through full CMOS integration. For the first time the micro heaters are made of active CMOS elements (i.e. MOSFET transistors) and embedded in a thin SOI membrane consisting of Si and SiO2 thin layers. Micro gas-sensors such as chemoresistive, microcalorimeteric and Pd/polymer gate FET sensors can be made using this technology. Full numerical analyses including 3D electro- thermo-mechanical simulations, in particular stress and deflection studies on the SOI membranes are presented. The transducer circuit design and the post-CMOS fabrication process, which includes single sided back-etching, are also reported.

  18. Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

    NASA Technical Reports Server (NTRS)

    Duong, Tuan A. (Inventor)

    2015-01-01

    A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

  19. ''Normal'' tissues from humans exposed to radium contain an alteration in the c-mos locus

    SciTech Connect

    Huberman, E.; Schlenker, R.A.; Hardwick, J.P.

    1989-01-01

    The structures of a number of human proto-oncogenes from persons with internal systemic exposure to radium were analyzed by restriction enzyme digestion and southern blotting of their DNA. Two extra c-mos Eco R1 restriction-fragment-length bands of 5.0 kb and 5.5 kb were found in tissue DNA from six of seven individuals. The extra c-mos bands were detected in DNA from many, but not all, of the tissues of the individuals exposed to radium. Our results suggest that the c-mos restriction-fragment-length alterations (RFLA) found in individuals exposed to radium were induced rather than inherited, are epigenetic in origin, and most likely result from changes in the methylation of bases surrounding the single exon of the c-mos proto-oncogene. 7 refs., 3 figs., 2 tabs.

  20. Development of radiation hard CMOS active pixel sensors for HL-LHC

    NASA Astrophysics Data System (ADS)

    Pernegger, Heinz

    2016-07-01

    New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

  1. Digital optical computing; Proceedings of the Meeting, Los Angeles, CA, Jan. 13, 14, 1987

    SciTech Connect

    Arrathoon, R.

    1987-01-01

    Recent advances in optical technology for digital computation are examined in reviews and reports. Consideration is given to direct and associative optical computing, optical AI and optical expert systems, optical/electronic logic and D/A systems, and optical interconnects. Topics discussed include symbolic substitution using ZnS interference filters, binary logic by spatial filtering, a directed graph optical processor, computer-vision applications of associative networks, decomposition of digital switching functions, variable-accuracy optical matrix/vector processors, CMOS detector cells for holographic optical interconnects in microcircuits, and S/N simulations for small guided-wave optical networks.

  2. Analog/digital pH meter system I.C.

    NASA Astrophysics Data System (ADS)

    Vincent, Paul; Park, Jea

    The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point.

  3. Analog/digital pH meter system I.C.

    NASA Technical Reports Server (NTRS)

    Vincent, Paul; Park, Jea

    1992-01-01

    The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point.

  4. The total ionizing dose effect in 12-bit, 125 MSPS analog-to-digital converters

    NASA Astrophysics Data System (ADS)

    Xue, Wu; Wu, Lu; Yudong, Li; Qi, Guo; Xin, Wang; Xingyao, Zhang; Xin, Yu; Wuying, Ma

    2014-04-01

    This paper presents the total ionizing dose test results at different biases and dose rates for AD9233, which is fabricated using a modern CMOS process. The experimental results show that the digital parts are more sensitive than the other parts. Power down is the worst-case bias, and this phenomenon is first found in the total ionizing dose effect of analog-to-digital converters. We also find that the AC as well as DC parameters are sensitive to the total ionizing dose at a high dose rate, whereas none of the parameters are sensitive at a low dose rate. The test facilities, results and analysis are presented in detail.

  5. Investigation of phase error correction for digital sinusoidal phase-shifting fringe projection profilometry

    NASA Astrophysics Data System (ADS)

    Ma, S.; Quan, C.; Zhu, R.; Tay, C. J.

    2012-08-01

    Digital sinusoidal phase-shifting fringe projection profilometry (DSPFPP) is a powerful tool to reconstruct three-dimensional (3D) surface of diffuse objects. However, a highly accurate profile is often hindered by nonlinear response, color crosstalk and imbalance of a pair of digital projector and CCD/CMOS camera. In this paper, several phase error correction methods, such as Look-Up-Table (LUT) compensation, intensity correction, gamma correction, LUT-based hybrid method and blind phase error suppression for gray and color-encoded DSPFPP are described. Experimental results are also demonstrated to evaluate the effectiveness of each method.

  6. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    NASA Astrophysics Data System (ADS)

    Benoit, M.; Bilbao de Mendizabal, J.; Casse, G.; Chen, H.; Chen, K.; Di Bello, F. A.; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Lanni, F.; Liu, H.; Meloni, F.; Meng, L.; Miucci, A.; Muenstermann, D.; Nessi, M.; Perić, I.; Rimoldi, M.; Ristic, B.; Barrero Pinto, M. Vicente; Vossebeld, J.; Weber, M.; Wu, W.; Xu, L.

    2016-07-01

    Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  7. A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

    PubMed Central

    Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

    2011-01-01

    This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

  8. Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

    SciTech Connect

    Smith, J.H.; Ellis, J.R.; Montague, S.; Allen, J.J.

    1997-03-01

    One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing. In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.

  9. A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

    NASA Astrophysics Data System (ADS)

    Venter, Petrus J.; Alberts, Antonie C.; du Plessis, Monuko; Joubert, Trudi-Heleen; Goosen, Marius E.; Janse van Rensburg, Christo; Rademeyer, Pieter; Fauré, Nicolaas M.

    2013-03-01

    Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

  10. SEMICONDUCTOR INTEGRATED CIRCUITS: Noise-canceling and IP3 improved CMOS RF front-end for DRM/DAB/DVB-H applications

    NASA Astrophysics Data System (ADS)

    Keping, Wang; Zhigong, Wang; Xuemei, Lei

    2010-02-01

    A CMOS RF (radio frequency) front-end for digital radio broadcasting applications is presented that contains a wideband LNA, I/Q-mixers and VGAs, supporting other various wireless communication standards in the ultra-wide frequency band from 200 kHz to 2 GHz as well. Improvement of the NF (noise figure) and IP3 (third-order intermodulation distortion) is attained without significant degradation of other performances like voltage gain and power consumption. The NF is minimized by noise-canceling technology, and the IP3 is improved by using differential multiple gate transistors (DMGTR). The dB-in-linear VGA (variable gain amplifier) exploits a single PMOS to achieve exponential gain control. The circuit is fabricated in 0.18-μm CMOS technology. The S11 of the RF front-end is lower than -11.4 dB over the whole band of 200 kHz-2 GHz. The variable gain range is 12-42 dB at 0.25 GHz and 4-36 dB at 2 GHz. The DSB NF at maximum gain is 3.1-6.1 dB. The IIP3 at middle gain is -4.7 to 0.2 dBm. It consumes a DC power of only 36 mW at 1.8 V supply.

  11. Behavioral study and design of a digital interpolator filter for wireless reconfigurable transmitters

    NASA Astrophysics Data System (ADS)

    Ferragina, V.; Frassone, A.; Ghittori, N.; Malcovati, P.; Vigna, A.

    2005-06-01

    The behavioral analysis and the design in a 0.13 μm CMOS technology of a digital interpolator filter for wireless applications are presented. The proposed block is designed to be embedded in the baseband part of a reconfigurable transmitter (WLAN 802.11a, UMTS) to operate as a sampling frequency boost between the digital signal processor (DSP) and the digital-to-analog converter (DAC). In recent trends the DAC of such transmitters usually operates at high conversion frequencies (to allow a relaxed implementation of the following analog reconstruction filter), while the DSP output flows at low frequencies (typically Nyquist rate). Thus a block able to increase the digital data rate, like the one proposed, is needed before the DAC. For example, in the WLAN case, an interpolation factor of 4 has been used, allowing the digital data frequency to raise from 20 MHz to 80 MHz. Using a time-domain model of the TX chain, a behavioral analysis has been performed to determine the impact of the filter performance on the quality of the signal at the antenna. This study has led to the evaluation of the z-domain filter transfer function, together with the specifications concerning a finite precision implementation. A VHDL description has allowed an automatic synthesis of the circuit in a 0.13 μm CMOS technology (with a supply voltage of 1.2 V). Post-synthesis simulations have confirmed the effectiveness of the proposed study.

  12. Superconductor digital electronics: Scalability and energy efficiency issues (Review Article)

    NASA Astrophysics Data System (ADS)

    Tolpygo, Sergey K.

    2016-05-01

    Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin superconducting layer for making compact high-kinetic-inductance bias inductors. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The physical limitations imposed on the circuit density by Josephson junctions, circuit inductors, shunt and bias resistors, etc., are discussed. Energy dissipation in superconducting circuits is also reviewed in order to estimate whether this technology, which requires cryogenic refrigeration, can be energy efficient. Fabrication process development required for increasing the density of superconductor digital circuits by a factor of ten and achieving densities above 107 Josephson junctions per cm2 is described.

  13. Self-testable CMOS thermopile-based infrared imager

    NASA Astrophysics Data System (ADS)

    Charlot, Benoit; Parrain, F.; Mir, Salvador; Courtois, Bernard

    2001-04-01

    This paper describes a CMOS-compatible self-testable uncooled InfraRed (IR) imager that can be used in multiple applications such as overheating detection, night vision, and earth tracking for satellite positioning. The imager consists of an array of thermal pixels that sense an infrared radiation. Each pixel is implemented as a front-side bulk micromachined membrane suspended by four arms, each arm containing a thermopile made of Poly/Al thermocouples. The imager has a pixel self-test function that can be activated off-line in the field for validation and maintenance purposes, with an on-chip test signal generation that requires only slight modifications in the pixel design. The self-test of a pixel takes about 15 ms. The area overhead required by the test electronics does not imply any reduction of the pixel fill factor, since the electronics fits in the pixel silicon boundary. However, the additional self-test circuitry contributes to a small increase in the thermal conductance of a pixel due to the wiring of a heating resistor over the suspended arms. The self-test capability of the imager allows for a production test with a standard test equipment, without the need of special infrared sources and the associated optical equipment. A prototype with 8 X 8 pixels is currently in fabrication for validation of the self-test approach. In this prototype, each pixel occupies an area of 200 X 200 micrometer2, with a membrane size of 90 X 90 micrometer2 (fill factor of 0.2). Simulation results indicate a pixel thermal conductance of 22.6 (mu) W/K, giving a responsivity of 138 V/W, with a thermocouple Seebeck coefficient that has been measured at 248 (mu) V/K for the 0.6 micrometer CMOS technology used. The noise equivalent power (considering only Johnson noise in the thermopile) is calculated as 0.18 nW.H-1/2 with a detectivity of 5.03 X 107 cm.Hz1/2.W-1, in line with current state-of-the-art. Since the imager may need to measure irradiation intensities below 1(mu) W

  14. Digital background calibration of charge pump based pipelined ADC

    NASA Astrophysics Data System (ADS)

    Singh, Anil; Agarwal, Alpana

    2016-11-01

    In the presented work, digital background calibration of a charge pump based pipelined ADC is presented. A 10-bit 100 MS/s pipelined ADC is designed using TSMC 0.18 µm CMOS technology operating on a 1.8 V power supply voltage. A power efficient opamp-less charge pump based technique is chosen to achieve the desired stage voltage gain of 2 and digital background calibration is used to calibrate the inter-stage gain error. After calibration, the ADC achieves an SNDR of 66.78 dB and SFDR of 79.3 dB. Also, DNL improves to +0.6/-0.4 LSB and INL improves from +9.3/-9.6 LSB to within ±0.5 LSB, consuming 16.53 mW of power.

  15. Digital demodulator

    NASA Technical Reports Server (NTRS)

    Shull, T. A. (Inventor)

    1982-01-01

    A digital demodulator for converting pulse code modulated data from phase shift key (PSK) to non return to zero (NRZ) and to biphase data is described. The demodulator is composed of standard integrated logic circuits. The key to the demodulation function is a pair of cross coupled one shot multivibrators and which with a flip-flop produce the NRZ-L is all that is required, the circuitry is greatly simplified and the 2(v) times bit rate contraint can be removed from the carrier. A flip-flop, an OR gate, and AND gate and a binary counter generate the bit rate clock (BTCK) for the NRZ-L. The remainder of the circuitry is for converting the NRZ-L and BTCK into biphase data. The device was designed for use in the space shuttle bay environment measurements.

  16. Digital Avionics

    NASA Technical Reports Server (NTRS)

    Koelbl, Terry G.; Ponchak, Denise; Lamarche, Teresa

    2003-01-01

    Digital Avionics activities played an important role in the advancements made in civil aviation, military systems, and space applications. This document profiles advances made in each of these areas by the aerospace industry, NASA centers, and the U.S. military. Emerging communication technologies covered in this document include Internet connectivity onboard aircraft, wireless broadband communication for aircraft, and a mobile router for aircraft to communicate in multiple communication networks over the course of a flight. Military technologies covered in this document include avionics for unmanned combat air vehicles and microsatellites, and head-up displays. Other technologies covered in this document include an electronic flight bag for the Boeing 777, and surveillance systems for managing airport operations.

  17. Digital structural

    USGS Publications Warehouse

    Dohm, J.M.; Anderson, R.C.; Tanaka, K.L.

    1998-01-01

    Magmatic and tectonic activity have both contributed significantly to the surface geology of Mars. Digital structural mapping techniques have now been used to classify and date centers of tectonic activity in the western equatorial region. For example, our results show a center of tectonic activity at Valles Marineris, which may be associated with uplift caused by intrusion. Such evidence may help explain, in part, the development of the large troughs and associated outflow channels and chaotic terrain. We also find a local centre of tectonic activity near the source region of Warrego Valles. Here, we suggest that the valley system may have resulted largely from intrusive-related hydrothermal activity. We hope that this work, together with the current Mars Global Surveyor mission, will lead to a better understanding of the geological processes that shaped the Martian surface.

  18. Digital Avionics

    NASA Technical Reports Server (NTRS)

    Koelbl, Terry G.; Ponchak, Denise; Lamarche, Teresa

    2002-01-01

    The field of digital avionics experienced another year of important advances in civil aviation, military systems, and space applications. As a result of the events of 9/11/2001, NASA has pursued activities to apply its aerospace technologies toward improved aviation security. Both NASA Glenn Research Center and Langley Research Center have performed flight research demonstrations using advanced datalink concepts to transmit live pictures from inside a jetliner, and to downlink the contents of the plane's 'black box' recorder in real time. The U.S. Navy and General Electric demonstrated survivable engine control (SEC) algorithms during engine ground tests at the Weapons Survivability Laboratory at China Lake. The scientists at Boeing Satellite Systems advanced the field of stellar inertial technology with the development of a new method for positioning optical star trackers on satellites.

  19. Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

    NASA Technical Reports Server (NTRS)

    White, Mark; Cooper, Mark; Johnston, Allan

    2011-01-01

    Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

  20. Design and simulation of multi-color infrared CMOS metamaterial absorbers

    NASA Astrophysics Data System (ADS)

    Cheng, Zhengxi; Chen, Yongping; Ma, Bin

    2016-05-01

    Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.