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Sample records for access memories srams

  1. An SEU (single event upset) tolerant memory cell derived from fundamental studies of SEU mechanisms in SRAM (static random access memories)

    SciTech Connect

    Weaver, H.T.; Axness, C.L.; McBrayer, J.D.; Browning, J.S.; Fu, J.S.; Ochoa, A. Jr.; Koga, R.

    1987-01-01

    A new single event upset (SEU) hardening concept, an LRAM cell, is demonstrated theoretically and experimentally. As basis for the LRAM idea, techniques were developed to measure time constants for ion induced voltage transients in conventional static random access memories, SRAM. Time constants of 0.8 and 6.0 nsec were measured for transients following strikes at the n- and p-channel drains, respectively - primary areas of SEU sensitivity. These data are the first transient time measurements on full memory chips and the large difference is fundamental to the LRAM concept. Decoupling resistors in the LRAM are used only to protect against the short transient; longer persisting pulses are blocked by a voltage divider, a basically new concept for SEU protection. In such a design, smaller resistors provide SEU tolerance, allowing higher performance, hardened memories. Test structures of the new design exhibit SEU tolerance with resistors 5-to-10 times smaller than currently used in SRAM. Our advanced transport-plus-circuit numerical simulations of the SEU process predicted this result and account for the LRAM experiments, as well as a variety of experiments on conventional SRAM. 16 refs., 6 figs., 1 tab.

  2. Thin Rechargeable Batteries for CMOS SRAM Memory Protection

    NASA Technical Reports Server (NTRS)

    Crouse, Dennis N.

    1993-01-01

    New rechargeable battery technology is described and compared with classical primary battery back-up of SRAM PC cards. Thin solid polymer electrolyte cells with the thickness of TSOP memory components (1 mm nominal, 1.1 mm max) and capacities of 14 mAh/sq cm can replace coin cells. The SRAM PC cards with permanently installed rechargeable cells and optional electrochromic low battery voltage indicators will free the periodic PC card user from having to 'feed' their PC cards with coin cells and will allow a quick visual check of stored cards for their battery voltage status.

  3. An SEU tolerant memory cell derived from fundamental studies of SEU mechanisms in SRAM

    SciTech Connect

    Weaver, H.T.; Axness, C.L.; McBrayer, J.D.; Browning, J.S.; Fu, J.S.; Ochoa, A. Jr.; Koga, R.

    1987-12-01

    A new single event upset (SEU) hardening concept, an LRAM cell, is demonstrated theoretically and experimentally. Decoupling resistors in the LRAM are used only to protect against the short n-channel transient; longer persisting pulses are reduced in magnitude by a voltage divider, a basically new concept for SEU protection. In such a design, smaller resistors provide SEU tolerance, allowing higher performance, hardened memories. As basis for the LRAM idea, techniques were developed to measure time constants for ion induced voltage transients in conventional static random access memories, SRAM. Time constants of 0.8 and 6.3 nsec were measured for transients following strikes at the n- and p-channel drains, respectively - primary areas of SEU sensitivity. These data are the first transient time measurements on full memory chips and the large difference is fundamental to the LRAM concept. Test structures of the new design exhibit equivalent SEU tolerance with resistors 5-to-10 times smaller than currently used in SRAM. Our advanced transport-plus-circuit numerical simulations of the SEU process predicted this result and account for the LRAM experiments, as well as a variety of experiments on conventional SRAM.

  4. SEU/SRAM as a Process Monitor

    NASA Technical Reports Server (NTRS)

    Blaes, B. R.; Buehler, M. G.

    1993-01-01

    The SEU/SRAM is a 4-kbit Static Random Access Memory (SRAM) designed to detect Single-Event Upsets (SEUs) produced by high energy particles. This device was used to determine the distribution in the memory cell spontaneous flip potential.

  5. Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

    NASA Technical Reports Server (NTRS)

    Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

    2011-01-01

    The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

  6. SRAM As An Array Of Energetic-Ion Detectors

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.; Blaes, Brent R.; Lieneweg, Udo; Nixon, Robert H.

    1993-01-01

    Static random-access memory (SRAM) designed for use as array of energetic-ion detectors. Exploits well-known tendency of incident energetic ions to cause bit flips in cells of electronic memories. Design of ion-detector SRAM involves modifications of standard SRAM design to increase sensitivity to ions. Device fabricated by use of conventional complementary metal oxide/semiconductor (CMOS) processes. Potential uses include gas densimetry, position sensing, and measurement of cosmic-ray spectrum.

  7. An Efficient Fault Syndromes Simulator for SRAM Memories

    NASA Astrophysics Data System (ADS)

    Wan Hasan, Wan Zuha; Abd Halin, Izhal; Mohd Sidek, Roslina; Othman, Masuri

    Testing and diagnosis techniques play a key role in the advance of semiconductor memory technology. The challenge of failure detection has created intensive investigation on efficient testing and diagnosis algorithm for better fault coverage and diagnostic resolution. At present, March test algorithm is used to detect and diagnose all faults related to Random Access Memories. However, the test and diagnosis process are mainly done manually. Due to this, a systematic approach for developing and evaluating memory test algorithm is required. This work is focused on incorporating the March based test algorithm using a software simulator tool for implementing a fast and systematic memory testing algorithm. The simulator allows a user through a GUI to select a March based test algorithm depending on the desired fault coverage and diagnostic resolution. Experimental results show that using the simulator for testing is more efficient than that of the traditional testing algorithm. This new simulator makes it possible for a detailed list of stuck-at faults, transition faults and coupling faults covered by each algorithm and its percentage to be displayed after a set of test algorithms has been chosen. The percentage of diagnostic resolution is also displayed. This proves that the simulator reduces the trade-off between test time, fault coverage and diagnostic resolution. Moreover, the chosen algorithm can be applied to incorporate with memory built-in self-test and diagnosis, to have a better fault coverage and diagnostic resolution. Universities and industry involved in memory Built-in-Self test, Built-in-Self repair and Built-in-Self diagnose will benefit by saving a few years on researching an efficient algorithm to be implemented in their designs.

  8. Ratioless full-complementary 12-transistor static random access memory for ultra low supply voltage operation

    NASA Astrophysics Data System (ADS)

    Kondo, Takahiro; Yamamoto, Hiromasa; Hoketsu, Satoko; Imi, Hitoshi; Okamura, Hitoshi; Nakamura, Kazuyuki

    2015-04-01

    In this study, a ratioless full-complementary 12-transistor static random access memory (SRAM) was developed and measured to evaluate its operation under an ultra low supply voltage range. The ratioless SRAM design concept enables a memory cell design that is free from the consideration of the static noise margin (SNM). Furthermore, it enables a SRAM function without the restriction of transistor parameter (W/L) settings and the dependence on the variability of device characteristics. The test chips that include both conventional 6-transistor SRAM cells and the ratioless full-complementary 12-transistor SRAM cells were developed by a 180 nm CMOS process to compare their stable operations under an ultralow supply voltage condition. The measured results show that the ratioless full-complementary 12-transistor SRAM has superior immunity to device variability, and its inherent operating ability at the supply voltage of 0.22 V was experimentally confirmed.

  9. Computer memory access technique

    NASA Technical Reports Server (NTRS)

    Zottarelli, L. J.

    1967-01-01

    Computer memory access commutator and steering gate configuration produces bipolar current pulses while still employing only the diodes and magnetic cores of the classic commutator, thereby appreciably reducing the complexity of the memory assembly.

  10. False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

    NASA Astrophysics Data System (ADS)

    Sawada, Takuya; Takata, Hidehiro; Nii, Koji; Nagata, Makoto

    2013-04-01

    Static random access memory (SRAM) cores exhibit susceptibility against power supply voltage variation. False operation is investigated among SRAM cells under sinusoidal voltage variation on power lines introduced by direct RF power injection. A standard SRAM core of 16 kbyte in a 90 nm 1.5 V technology is diagnosed with built-in self test and on-die noise monitor techniques. The sensitivity of bit error rate is shown to be high against the frequency of injected voltage variation, while it is not greatly influenced by the difference in frequency and phase against SRAM clocking. It is also observed that the distribution of false bits is substantially random in a cell array.

  11. Application of RADSAFE to Model Single Event Upset Response of a 0.25 micron CMOS SRAM

    NASA Technical Reports Server (NTRS)

    Warren, Kevin M.; Weller, Robert A.; Sierawski, Brian; Reed, Robert A.; Mendenhall, Marcus H.; Schrimpf, Ronald D.; Massengill, Lloyd; Porter, Mark; Wilkerson, Jeff; LaBel, Kenneth A.; Adams, James

    2006-01-01

    The RADSAFE simulation framework is described and applied to model Single Event Upsets (SEU) in a 0.25 micron CMOS 4Mbit Static Random Access Memory (SRAM). For this circuit, the RADSAFE approach produces trends similar to those expected from classical models, but more closely represents the physical mechanisms responsible for SEU in the SRAM circuit.

  12. SEU measurements on HFETS and HFET SRAMS

    SciTech Connect

    Remke, R.L.; Witmer, S.B.; Jones, S.D.F. ); Barber, F.E. ); Flesner, L.D.; O'Brien, M.E. )

    1989-12-01

    The single event upset (SEU) response of n{sup +}-AlGaAs/GaAs heterostructure field effect transistors(HFETs--also known as SDHTs, HEMTs, MODFETs, and TEGFETs) and HFET static random access memories (SRAMs) was evaluated by measuring their response to focused electron pulses. Initially, focused electron beam pulses were used to measure and model HFET drain and gate SEU responses. Circuit simulations using these SEU models predicted that an HFET memory is most vulnerable to a single particle event in the area between the drain and the source (drain hit) of the OFF pull down HFET. Subsequent testing of an HFET SRAM cell confirmed this prediction. The authors discuss how these first SEU evaluations of HFETs and HFET memories show that measurements on individual HFETs and circuit simulations of SEU hits may be used to predict the SEU response of HFET memories.

  13. Design and characterization of an SRAM-based neutron detector for particle therapy

    NASA Astrophysics Data System (ADS)

    Ytre-Hauge, Kristian S.; Velure, Arild; Larsen, Eivind F.; Stokkevåg, Camilla H.; Röhrich, Dieter; Brekke, Njål; Odland, Odd Harald

    2015-12-01

    A neutron detector based on registration of radiation effects in Static Random Access Memories (SRAMs) has been developed at the University of Bergen for applications in particle therapy. Nine different SRAMs were tested and a 16 Mibit SRAM from Cypress was chosen for the final detector. The SRAMs were irradiated in beam lines at PTB Braunschweig, the Oslo Cyclotron Laboratory, The Svedberg Laboratory, The Institute for Energy Technology (IFE, Kjeller) and the CERN-EU high-energy reference field. The results from the measurements demonstrate the feasibility of using the selected SRAMs for neutron detection. The results indicate low or no sensitivity to thermal neutrons while the cross section for fast neutrons increases with neutron energy before reaching a more stable level at energies of several tenths of MeV.

  14. Atomic memory access hardware implementations

    SciTech Connect

    Ahn, Jung Ho; Erez, Mattan; Dally, William J

    2015-02-17

    Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

  15. Is random access memory random?

    NASA Technical Reports Server (NTRS)

    Denning, P. J.

    1986-01-01

    Most software is contructed on the assumption that the programs and data are stored in random access memory (RAM). Physical limitations on the relative speeds of processor and memory elements lead to a variety of memory organizations that match processor addressing rate with memory service rate. These include interleaved and cached memory. A very high fraction of a processor's address requests can be satified from the cache without reference to the main memory. The cache requests information from main memory in blocks that can be transferred at the full memory speed. Programmers who organize algorithms for locality can realize the highest performance from these computers.

  16. Ferroelectric random access memories.

    PubMed

    Ishiwara, Hiroshi

    2012-10-01

    Ferroelectric random access memory (FeRAM) is a nonvolatile memory, in which data are stored using hysteretic P-E (polarization vs. electric field) characteristics in a ferroelectric film. In this review, history and characteristics of FeRAMs are first introduced. It is described that there are two types of FeRAMs, capacitor-type and FET-type, and that only the capacitor-type FeRAM is now commercially available. In chapter 2, properties of ferroelectric films are discussed from a viewpoint of FeRAM application, in which particular attention is paid to those of Pb(Zr,Ti)O3, SrBi2Ta2O9, and BiFeO3. Then, cell structures and operation principle of the capacitor-type FeRAMs are discussed in chapter 3. It is described that the stacked technology of ferroelectric capacitors and development of new materials with large remanent polarization are important for fabricating high-density memories. Finally, in chapter 4, the optimized gate structure in ferroelectric-gate field-effect transistors is discussed and experimental results showing excellent data retention characteristics are presented. PMID:23421123

  17. Closed-form analytical model of static noise margin for ultra-low voltage eight-transistor tunnel FET static random access memory

    NASA Astrophysics Data System (ADS)

    Fuketa, Hiroshi; O'uchi, Shin-ichi; Fukuda, Koichi; Mori, Takahiro; Morita, Yukinori; Masahara, Meishoku; Matsukawa, Takashi

    2016-04-01

    Variations of eight-transistor (8T) tunnel FET (TFET) static random access memory (SRAM) cells at ultra-low supply voltage (V DD) of 0.3 V are discussed. A closed-form analytical model for the static noise margin (SNM) of the TFET SRAM cells is proposed to clarify the dependence of SNM on device parameters and is verified by simulations. The SNM variations caused by process variations are investigated using the proposed model, and we show a requirement for the threshold voltage (V TH) variation in the TFET SRAM design, which indicates that the V TH variation must be reduced as the subthreshold swing becomes steeper. In addition, a feasibility of the TFET SRAM cells operating at V DD = 0.3 V in two different process technologies is evaluated using the proposed model.

  18. Evaluation and Control of Break-Even Time of Nonvolatile Static Random Access Memory Based on Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

    NASA Astrophysics Data System (ADS)

    Shuto, Yusuke; Yamamoto, Shuu'ichirou; Sugahara, Satoshi

    2012-04-01

    The energy performance of a nonvolatile static random access memory (NV-SRAM) cell for power gating applications was quantitatively analyzed for the first time using the performance index of break-even time (BET). The NV-SRAM cell is based on spin-transistor architecture using ordinary metal-oxide-semiconductor field-effect transistors (MOSFETs) and spin-transfer-torque magnetic tunnel junctions (STT-MTJs), whose circuit representation of spin-transistor is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The cell is configured with a standard six-transistor SRAM cell and two PS-MOSFETs. The NV-SRAM cell basically has a short BET of submicroseconds. Although the write (store) operation to the STT-MTJs causes an increase in the BET, it can be successfully reduced by the proposed power-aware bias-control for the PS-MOSFETs.

  19. Synergistic effects of total ionizing dose on single event upset sensitivity in static random access memory under proton irradiation

    NASA Astrophysics Data System (ADS)

    Xiao, Yao; Guo, Hong-Xia; Zhang, Feng-Qi; Zhao, Wen; Wang, Yan-Ping; Zhang, Ke-Ying; Ding, Li-Li; Fan, Xue; Luo, Yin-Hong; Wang, Yuan-Ming

    2014-11-01

    Synergistic effects of the total ionizing dose (TID) on the single event upset (SEU) sensitivity in static random access memories (SRAMs) were studied by using protons. The total dose was cumulated with high flux protons during the TID exposure, and the SEU cross section was tested with low flux protons at several cumulated dose steps. Because of the radiation-induced off-state leakage current increase of the CMOS transistors, the noise margin became asymmetric and the memory imprint effect was observed.

  20. Nonvolatile random access memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

    1994-01-01

    A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a 0 or 1 state. The element remains in the 0 or 1 state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.

  1. Remote direct memory access

    DOEpatents

    Archer, Charles J.; Blocksome, Michael A.

    2012-12-11

    Methods, parallel computers, and computer program products are disclosed for remote direct memory access. Embodiments include transmitting, from an origin DMA engine on an origin compute node to a plurality target DMA engines on target compute nodes, a request to send message, the request to send message specifying a data to be transferred from the origin DMA engine to data storage on each target compute node; receiving, by each target DMA engine on each target compute node, the request to send message; preparing, by each target DMA engine, to store data according to the data storage reference and the data length, including assigning a base storage address for the data storage reference; sending, by one or more of the target DMA engines, an acknowledgment message acknowledging that all the target DMA engines are prepared to receive a data transmission from the origin DMA engine; receiving, by the origin DMA engine, the acknowledgement message from the one or more of the target DMA engines; and transferring, by the origin DMA engine, data to data storage on each of the target compute nodes according to the data storage reference using a single direct put operation.

  2. A 0.5-V Six-Transistor Static Random Access Memory with Ferroelectric-Gate Field Effect Transistors

    NASA Astrophysics Data System (ADS)

    Tanakamaru, Shuhei; Hatanaka, Teruyoshi; Yajima, Ryoji; Miyaji, Kousuke; Takahashi, Mitsue; Sakai, Shigeki; Takeuchi, Ken

    2010-12-01

    A 0.5 V six-transistor static random access memory (6T-SRAM) with ferroelectric-gate field-effect-transistors (Fe-FETs) is proposed and experimentally demonstrated for the first time. During the read and the hold, the threshold voltage (VTH) of Fe-FETs automatically changes to increase the static noise margin (SNM) by 60%. During the stand-by, the VTH of the proposed SRAM cell increases to decrease the leakage current by 42%. In case of the read, the VTH of the read transistor decreases and increases the cell read current to achieve the fast read. During the write, the VTH of the SRAM cell dynamically changes and assist the cell data to flip, realizing a write assist function. The enlarged SNM realizes the VDD reduction by 0.11 V, which decreases the active power by 32%. The proposed SRAM layout is the same as the conventional 6T-SRAM and there is no area penalty.

  3. SRAM Based Re-programmable FPGA for Space Applications

    NASA Technical Reports Server (NTRS)

    Wang, J. J.; Sun, J. S.; Cronquist, B. E.; McCollum, J. L.; Speers, T. M.; Plants, W. C.; Katz, R. B.

    1999-01-01

    An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

  4. Garnet Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.

    1995-01-01

    Random-access memory (RAM) devices of proposed type exploit magneto-optical properties of magnetic garnets exhibiting perpendicular anisotropy. Magnetic writing and optical readout used. Provides nonvolatile storage and resists damage by ionizing radiation. Because of basic architecture and pinout requirements, most likely useful as small-capacity memory devices.

  5. Plated wire random access memories

    NASA Technical Reports Server (NTRS)

    Gouldin, L. D.

    1975-01-01

    A program was conducted to construct 4096-work by 18-bit random access, NDRO-plated wire memory units. The memory units were subjected to comprehensive functional and environmental tests at the end-item level to verify comformance with the specified requirements. A technical description of the unit is given, along with acceptance test data sheets.

  6. Design of power balance SRAM for DPA-resistance

    NASA Astrophysics Data System (ADS)

    Keji, Zhou; Pengjun, Wang; Liang, Wen

    2016-04-01

    A power balance static random-access memory (SRAM) for resistance to differential power analysis (DPA) is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanced by discharging and pre-charging the key nodes of the output circuit and adding an additional short-circuit current path. Thus, the power consumption is constant in every read cycle. As a result, the DPA-resistant ability of the SRAM is improved. In 65 nm CMOS technology, the power balance SRAM is fully custom designed with a layout area of 5863.6 μm2. The post-simulation results show that the normalized energy deviation (NED) and normalized standard deviation (NSD) are 0.099% and 0.04%, respectively. Compared to existing power balance circuits, the power balance ability of the proposed SRAM has improved 53%. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. LQ14F040001), the National Natural Science Foundation of China (Nos. 61274132, 61234002), and the K. C. Wong Magna Fund in Ningbo University, China.

  7. SRAM Detector Calibration

    NASA Technical Reports Server (NTRS)

    Soli, G. A.; Blaes, B. R.; Beuhler, M. G.

    1994-01-01

    Custom proton sensitive SRAM chips are being flown on the BMDO Clementine missions and Space Technology Research Vehicle experiments. This paper describes the calibration procedure for the SRAM proton detectors and their response to the space environment.

  8. Memory availability and referential access

    PubMed Central

    Johns, Clinton L.; Gordon, Peter C.; Long, Debra L.; Swaab, Tamara Y.

    2013-01-01

    Most theories of coreference specify linguistic factors that modulate antecedent accessibility in memory; however, whether non-linguistic factors also affect coreferential access is unknown. Here we examined the impact of a non-linguistic generation task (letter transposition) on the repeated-name penalty, a processing difficulty observed when coreferential repeated names refer to syntactically prominent (and thus more accessible) antecedents. In Experiment 1, generation improved online (event-related potentials) and offline (recognition memory) accessibility of names in word lists. In Experiment 2, we manipulated generation and syntactic prominence of antecedent names in sentences; both improved online and offline accessibility, but only syntactic prominence elicited a repeated-name penalty. Our results have three important implications: first, the form of a referential expression interacts with an antecedent’s status in the discourse model during coreference; second, availability in memory and referential accessibility are separable; and finally, theories of coreference must better integrate known properties of the human memory system. PMID:24443621

  9. Robust Three-Metallization Back End of Line Process for 0.18 μm Embedded Ferroelectric Random Access Memory

    NASA Astrophysics Data System (ADS)

    Kang, Seung-Kuk; Rhie, Hyoung-Seub; Kim, Hyun-Ho; Koo, Bon-Jae; Joo, Heung-Jin; Park, Jung-Hun; Kang, Young-Min; Choi, Do-Hyun; Lee, Sung-Young; Jeong, Hong-Sik; Kim, Kinam

    2005-04-01

    We developed ferroelectric random access memory (FRAM)-embedded smartcards in which FRAM replaces electrically erasable PROM (EEPROM) and static random access memory (SRAM) to improve the read/write cycle time and endurance of data memories during operation, in which the main time delay retardation observed in EEPROM embedded smartcards occurs because of slow data update time. EEPROM-embedded smartcards have EEPROM, ROM, and SRAM. To utilize FRAM-embedded smartcards, we should integrate submicron ferroelectric capacitors into embedded logic complementary metal oxide semiconductor (CMOS) without the degradation of the ferroelectric properties. We resolved this process issue from the viewpoint of the back end of line (BEOL) process. As a result, we realized a highly reliable sensing window for FRAM-embedded smartcards that were realized by novel integration schemes such as tungsten and barrier metal (BM) technology, multilevel encapsulating (EBL) layer scheme and optimized intermetallic dielectrics (IMD) technology.

  10. Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

    NASA Technical Reports Server (NTRS)

    Wu, Jiin C.; Katti, Romney R.; Stadler, Henry L.

    1991-01-01

    The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

  11. Pattern imprinting in deep sub-micron static random access memories induced by total dose irradiation

    NASA Astrophysics Data System (ADS)

    Zheng, Qi-Wen; Yu, Xue-Feng; Cui, Jiang-Wei; Guo, Qi; Ren, Di-Yuan; Cong, Zhong-Chao; Zhou, Hang

    2014-10-01

    Pattern imprinting in deep sub-micron static random access memories (SRAMs) during total dose irradiation is investigated in detail. As the dose accumulates, the data pattern of memory cells loading during irradiation is gradually imprinted on their background data pattern. We build a relationship between the memory cell's static noise margin (SNM) and the background data, and study the influence of irradiation on the probability density function of ΔSNM, which is the difference between two data sides' SNMs, to discuss the reason for pattern imprinting. Finally, we demonstrate that, for micron and deep sub-micron devices, the mechanism of pattern imprinting is the bias-dependent threshold shift of the transistor, but for a deep sub-micron device the shift results from charge trapping in the shallow trench isolation (STI) oxide rather than from the gate oxide of the micron-device.

  12. Dynamic computing random access memory

    NASA Astrophysics Data System (ADS)

    Traversa, F. L.; Bonani, F.; Pershin, Y. V.; Di Ventra, M.

    2014-07-01

    The present von Neumann computing paradigm involves a significant amount of information transfer between a central processing unit and memory, with concomitant limitations in the actual execution speed. However, it has been recently argued that a different form of computation, dubbed memcomputing (Di Ventra and Pershin 2013 Nat. Phys. 9 200-2) and inspired by the operation of our brain, can resolve the intrinsic limitations of present day architectures by allowing for computing and storing of information on the same physical platform. Here we show a simple and practical realization of memcomputing that utilizes easy-to-build memcapacitive systems. We name this architecture dynamic computing random access memory (DCRAM). We show that DCRAM provides massively-parallel and polymorphic digital logic, namely it allows for different logic operations with the same architecture, by varying only the control signals. In addition, by taking into account realistic parameters, its energy expenditures can be as low as a few fJ per operation. DCRAM is fully compatible with CMOS technology, can be realized with current fabrication facilities, and therefore can really serve as an alternative to the present computing technology.

  13. Dynamic computing random access memory.

    PubMed

    Traversa, F L; Bonani, F; Pershin, Y V; Di Ventra, M

    2014-07-18

    The present von Neumann computing paradigm involves a significant amount of information transfer between a central processing unit and memory, with concomitant limitations in the actual execution speed. However, it has been recently argued that a different form of computation, dubbed memcomputing (Di Ventra and Pershin 2013 Nat. Phys. 9 200-2) and inspired by the operation of our brain, can resolve the intrinsic limitations of present day architectures by allowing for computing and storing of information on the same physical platform. Here we show a simple and practical realization of memcomputing that utilizes easy-to-build memcapacitive systems. We name this architecture dynamic computing random access memory (DCRAM). We show that DCRAM provides massively-parallel and polymorphic digital logic, namely it allows for different logic operations with the same architecture, by varying only the control signals. In addition, by taking into account realistic parameters, its energy expenditures can be as low as a few fJ per operation. DCRAM is fully compatible with CMOS technology, can be realized with current fabrication facilities, and therefore can really serve as an alternative to the present computing technology. PMID:24972387

  14. SEE induced in SRAM operating in a superconducting electron linear accelerator environment

    NASA Astrophysics Data System (ADS)

    Makowski, D.; Mukherjee, Bhaskar; Grecki, M.; Simrock, Stefan

    2005-02-01

    Strong fields of bremsstrahlung photons and photoneutrons are produced during the operation of high-energy electron linacs. Therefore, a mixed gamma and neutron radiation field dominates the accelerators environment. The gamma radiation induced Total Ionizing Dose (TID) effect manifests the long-term deterioration of the electronic devices operating in accelerator environment. On the other hand, the neutron radiation is responsible for Single Event Effects (SEE) and may cause a temporal loss of functionality of electronic systems. This phenomenon is known as Single Event Upset (SEU). The neutron dose (KERMA) was used to scale the neutron induced SEU in the SRAM chips. Hence, in order to estimate the neutron KERMA conversion factor for Silicon (Si), dedicated calibration experiments using an Americium-Beryllium (241Am/Be) neutron standard source was carried out. Single Event Upset (SEU) influences the short-term operation of SRAM compared to the gamma induced TID effect. We are at present investigating the feasibility of an SRAM based real-time beam-loss monitor for high-energy accelerators utilizing the SEU caused by fast neutrons. This paper highlights the effects of gamma and neutron radiations on Static Random Access Memory (SRAM), placed at selected locations near the Superconducting Linear Accelerator driving the Vacuum UV Free Electron Laser (VUVFEL) of DESY.

  15. Memory access in shared virtual memory

    SciTech Connect

    Berrendorf, R. )

    1992-01-01

    Shared virtual memory (SVM) is a virtual memory layer with a single address space on top of a distributed real memory on parallel computers. We examine the behavior and performance of SVM running a parallel program with medium-grained, loop-level parallelism on top of it. A simulator for the underlying parallel architecture can be used to examine the behavior of SVM more deeply. The influence of several parameters, such as the number of processors, page size, cold or warm start, and restricted page replication, is studied.

  16. Memory access in shared virtual memory

    SciTech Connect

    Berrendorf, R.

    1992-09-01

    Shared virtual memory (SVM) is a virtual memory layer with a single address space on top of a distributed real memory on parallel computers. We examine the behavior and performance of SVM running a parallel program with medium-grained, loop-level parallelism on top of it. A simulator for the underlying parallel architecture can be used to examine the behavior of SVM more deeply. The influence of several parameters, such as the number of processors, page size, cold or warm start, and restricted page replication, is studied.

  17. 39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme

    NASA Astrophysics Data System (ADS)

    Yamamoto, Yasue; Moriwaki, Shinichi; Kawasumi, Atsushi; Miyano, Shinji; Shinohara, Hirofumi

    2016-04-01

    We propose novel circuit techniques for 1 clock (1CLK) 1 read/1 write (1R/1W) 2-port static random-access memories (SRAMs) to improve read access time (tAC) and write margins at low voltages. Two-stage read boost (TSR-BST) and write word line boost (WWL-BST) after the read sensing schemes have been proposed. TSR-BST reduces the worst read bit line (RBL) delay by 61% and RBL amplitude by 10% at V DD = 0.5 V, which improves tAC by 39% and reduces energy dissipation by 11% at V DD = 0.55 V. WWL-BST after read sensing scheme improves minimum operating voltage (V min) by 140 mV. A 32 kbit 1CLK 1R/1W 2-port SRAM with TSR-BST and WWL-BST has been developed using a 40 nm CMOS.

  18. Mitigating Upsets in SRAM-Based FPGAs from the Xilinx Virtex 2 Family

    NASA Technical Reports Server (NTRS)

    Swift, G. M.; Yui, C. C.; Carmichael, C.; Koga, R.; George, J. S.

    2003-01-01

    Static random access memory (SRAM) upset rates in field programmable gate arrays (FPGAs) from the Xilinx Virtex 2 family have been tested for radiation effects on configuration memory, block RAM and the power-on-reset (POR) and SelectMAP single event functional interrupts (SEFIs). Dynamic testing has shown the effectiveness and value of Triple Module Redundancy (TMR) and partial reconfiguration when used in conjunction. Continuing dynamic testing for more complex designs and other Virtex 2 capabilities (i.e., I/O standards, digital clock managers (DCM), etc.) is scheduled.

  19. Influence of edge effects on single event upset susceptibility of SOI SRAMs

    NASA Astrophysics Data System (ADS)

    Gu, Song; Liu, Jie; Zhao, Fazhan; Zhang, Zhangang; Bi, Jinshun; Geng, Chao; Hou, Mingdong; Liu, Gang; Liu, Tianqi; Xi, Kai

    2015-01-01

    An experimental investigation of the single event upset (SEU) susceptibility for heavy ions at tilted incidence was performed. The differences of SEU cross-sections between tilted incidence and normal incidence at equivalent effective linear energy transfer were 21% and 57% for the silicon-on-insulator (SOI) static random access memories (SRAMs) of 0.5 μm and 0.18 μm feature size, respectively. The difference of SEU cross-section raised dramatically with increasing tilt angle for SOI SRAM of deep-submicron technology. The result of CRÈME-MC simulation for tilted irradiation of the sensitive volume indicates that the energy deposition spectrum has a substantial tail extending into the low energy region. The experimental results show that the influence of edge effects on SEU susceptibility cannot be ignored in particular with device scaling down.

  20. Magnetic Analog Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.; Wu, Jiin-Chuan; Stadler, Henry L.

    1991-01-01

    Proposed integrated, solid-state, analog random-access memory base on principle of magnetic writing and magnetoresistive reading. Current in writing conductor magnetizes storage layer. Remanent magnetization in storage layer penetrates readout layer and detected by magnetoresistive effect or Hall effect. Memory cells are part of integrated circuit including associated reading and writing transistors. Intended to provide high storage density and rapid access, nonvolatile, consumes little power, and relatively invulnerable to ionizing radiation.

  1. Alpha-particle sensitive test SRAMs

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Blaes, B. R.

    1990-01-01

    A bench-level test is being developed to evaluate memory-cell upsets in a test SRAM designed with a cell offset voltage. This offset voltage controls the critical charge needed to upset the cell. The effect is demonstrated using a specially designed 2-micron n-well CMOS 4-kb test SRAM and a Po-208 5.1-MeV 0.61-LET alpha-particle source. This test SRAM has been made sensitive to alpha particles through the use of a cell offset voltage, and this has allowed a bench-level characterization in a laboratory setting. The experimental data are linked to a alpha-particle interaction physics and to SPICE circuit simulations through the alpha-particle collection depth. The collection depth is determined by two methods and found to be about 7 micron. In addition, alpha particles that struck outside the bloated drain were able to flip the SRAM cells. This lateral charge collection was observed to be more than 6 micron.

  2. Detailed analysis of minimum operation voltage of extraordinarily unstable cells in fully depleted silicon-on-buried-oxide six-transistor static random access memory

    NASA Astrophysics Data System (ADS)

    Mizutani, Tomoko; Yamamoto, Yoshiki; Makiyama, Hideki; Yamashita, Tomohiro; Oda, Hidekazu; Kamohara, Shiro; Sugii, Nobuyuki; Hiramoto, Toshiro

    2015-04-01

    The minimum operation voltage (Vmin) of very unstable cells in silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) static random access memory (SRAM) is analyzed in detail. It is found that the worst cell in 16k SRAM is very unstable and the stability characteristics of the worst cell correspond to approximately 6σ from those of the median cell. It is also found that extraordinarily unstable cells are much more sensitive to VTH change than median cells and that the static noise margin (SNM) and Vmin well correlate only in extraordinarily unstable cells. A simple VTH model for evaluating Vmin is developed and validated by Vmin measured in extraordinarily unstable cells.

  3. Evaluation of soft error rates using nuclear probes in bulk and SOI SRAMs with a technology node of 90 nm

    NASA Astrophysics Data System (ADS)

    Abo, Satoshi; Masuda, Naoyuki; Wakaya, Fujio; Onoda, Shinobu; Hirao, Toshio; Ohshima, Takeshi; Iwamatsu, Toshiaki; Takai, Mikio

    2010-06-01

    The difference of soft error rates (SERs) in conventional bulk Si and silicon-on-insulator (SOI) static random access memories (SRAMs) with a technology node of 90 nm has been investigated by helium ion probes with energies ranging from 0.8 to 6.0 MeV and a dose of 75 ions/μm 2. The SERs in the SOI SRAM were also investigated by oxygen ion probes with energies ranging from 9.0 to 18.0 MeV and doses of 0.14-0.76 ions/μm 2. The soft error in the bulk and SOI SRAMs occurred by helium ion irradiation with energies at and above 1.95 and 2.10 MeV, respectively. The SER in the bulk SRAM saturated with ion energies at and above 2.5 MeV. The SER in the SOI SRAM became the highest by helium ion irradiation at 2.5 MeV and drastically decreased with increasing the ion energies above 2.5 MeV, in which helium ions at this energy range generated the maximum amount of excess charge carriers in a SOI body. The soft errors occurred by helium ions were induced by a floating body effect due to generated excess charge carriers in the channel regions. The soft error occurred by oxygen ion irradiation with energies at and above 10.5 MeV in the SOI SRAM. The SER in the SOI SRAM gradually increased with energies from 10.5 to 13.5 MeV and saturated at 18 MeV, in which the amount of charge carriers induced by oxygen ions in this energy range gradually increased. The computer calculation indicated that the oxygen ions with energies above 13.0 MeV generated more excess charge carriers than the critical charge of the 90 nm node SOI SRAM with the designed over-layer thickness. The soft errors, occurred by oxygen ions with energies at and below 12.5 MeV, were induced by a floating body effect due to the generated excess charge carriers in the channel regions and those with energies at and above 13.0 MeV were induced by both the floating body effect and generated excess carriers. The difference of the threshold energy of the oxygen ions between the experiment and the computer calculation might

  4. Validation techniques for fault emulation of SRAM-based FPGAs

    SciTech Connect

    Quinn, Heather; Wirthlin, Michael

    2015-08-07

    A variety of fault emulation systems have been created to study the effect of single-event effects (SEEs) in static random access memory (SRAM) based field-programmable gate arrays (FPGAs). These systems are useful for augmenting radiation-hardness assurance (RHA) methodologies for verifying the effectiveness for mitigation techniques; understanding error signatures and failure modes in FPGAs; and failure rate estimation. For radiation effects researchers, it is important that these systems properly emulate how SEEs manifest in FPGAs. If the fault emulation systems does not mimic the radiation environment, the system will generate erroneous data and incorrect predictions of behavior of the FPGA in a radiation environment. Validation determines whether the emulated faults are reasonable analogs to the radiation-induced faults. In this study we present methods for validating fault emulation systems and provide several examples of validated FPGA fault emulation systems.

  5. Validation techniques for fault emulation of SRAM-based FPGAs

    DOE PAGESBeta

    Quinn, Heather; Wirthlin, Michael

    2015-08-07

    A variety of fault emulation systems have been created to study the effect of single-event effects (SEEs) in static random access memory (SRAM) based field-programmable gate arrays (FPGAs). These systems are useful for augmenting radiation-hardness assurance (RHA) methodologies for verifying the effectiveness for mitigation techniques; understanding error signatures and failure modes in FPGAs; and failure rate estimation. For radiation effects researchers, it is important that these systems properly emulate how SEEs manifest in FPGAs. If the fault emulation systems does not mimic the radiation environment, the system will generate erroneous data and incorrect predictions of behavior of the FPGA inmore » a radiation environment. Validation determines whether the emulated faults are reasonable analogs to the radiation-induced faults. In this study we present methods for validating fault emulation systems and provide several examples of validated FPGA fault emulation systems.« less

  6. SEU immunity: The effects of scaling on the peripheral circuits of SRAMs

    SciTech Connect

    Jacunski, L.; Doyle, S.; Jallice, D.; Haddad, N.; Scott, T. )

    1994-12-01

    Heavy ion testing on a scaled 256K SRAM has shown that SEU analysis of the peripheral circuits as well as the memory cell must be performed as circuits are scaled to smaller and smaller dimensions. This paper describes the SEU induce phenomena experienced by the scaled version of a previous 256K radiation hardened SRAM design, affected by circuits in the periphery.

  7. Low latency memory access and synchronization

    DOEpatents

    Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.; Gara, Alan G.; Giampapa, Mark E.; Heidelberger, Philip; Hoenicke, Dirk; Ohmacht, Martin; Steinmacher-Burow, Burkhard D.; Takken, Todd E.; Vranas, Pavlos M.

    2007-02-06

    A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.

  8. Low latency memory access and synchronization

    DOEpatents

    Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.; Gara, Alan G.; Giampapa, Mark E.; Heidelberger, Philip; Hoenicke, Dirk; Ohmacht, Martin; Steinmacher-Burow, Burkhard D.; Takken, Todd E. , Vranas; Pavlos M.

    2010-10-19

    A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.

  9. Dose measurement based on threshold shift in MOSFET arrays in commercial SRAMS

    NASA Technical Reports Server (NTRS)

    Scheick, L. Z.; Swift, G.

    2002-01-01

    A new method using an array of MOS transistors isdescribed for measuring dose absorbed from ionizingradiation. Using the array of MOSFETs in a SRAM, a direct measurement of the number of MOS cells which change as a function of applied bias on the SRAM. Since the input and output of a SRAM used as a dosimeter is completely digital, the measurement of dose is easily accessible by a remote processing system.

  10. Designing high-performance cost-efficient embedded SRAM in deep-submicron era

    NASA Astrophysics Data System (ADS)

    Kobozeva, Olga; Venkatraman, Ramnath; Castagnetti, Ruggero; Duan, Franklin; Kamath, Arvind; Ramesh, Shiva

    2004-05-01

    We have previously presented the smallest and fastest 6 Transistor (6T)-Static Random Access Memories (SRAM) bitcells for System-on-Chip (SoC) high-density (HD) memories in 0.18 μm and 0.13 μm technologies. Our 1.87 μm2 6TSRAM bitcell with cell current of 47 μA and industry lowest soft error rate (0.35 FIT/Kbit) is used to assemble memory blocks embedded into SoC designs in 0.13 μm process technology. Excellent performance is achieved at a low overall cost, as our bitcells are based on standard CMOS process and demonstrate high yields in manufacturing. This paper discusses our methodology of embedded SRAM bitcell design. The key aspects of our approach are: 1) judicious selection of tightest achievable yet manufacturable design rules to build the cell; 2) compatibility with standard Optical Proximity Correction (OPC) flow; 3) use of parametric testing and yield analysis to achieve excellent design robustness and manufacturability. A thorough understanding of process limitations, particularly those related to photolithography was critical to the successful design and manufacturing of our aggressive, yet robust SRAM bitcells. The patterning of critical layers, such as diffusion, poly gate, contact and metal 1 has profound implications on functionality, electrical performance and manufacturability of memories. We have conducted the development of SRAM bitcells using two approaches for OPC: a) "manual" OPC, wherein the bitcell layout of each of the critical layers is achieved using iterative improvement of layout & aerial image simulation and b) automated OPC-compatible design, wherein the drawn bitcell layout becomes a subject of a full chip OPC. While manual-OPC remains a popular option, automated OPC-compatible bitcell design is very attractive, as it does not require additional development costs to achieve fab-to-fab portability. In both cases we have obtained good results with respect to patterning of the critical layers, electrical performance of the bitcell

  11. Impact of temperature on single event upset measurement by heavy ions in SRAM devices

    NASA Astrophysics Data System (ADS)

    Tianqi, Liu; Chao, Geng; Zhangang, Zhang; Fazhan, Zhao; Song, Gu; Teng, Tong; Kai, Xi; Gang, Liu; Zhengsheng, Han; Mingdong, Hou; Jie, Liu

    2014-08-01

    The temperature dependence of single event upset (SEU) measurement both in commercial bulk and silicon on insulator (SOI) static random access memories (SRAMs) has been investigated by experiment in the Heavy Ion Research Facility in Lanzhou (HIRFL). For commercial bulk SRAM, the SEU cross section measured by 12C ions is very sensitive to the temperature. The temperature test of SEU in SOI SRAM was conducted by 209Bi and 12C ions, respectively, and the SEU cross sections display a remarkable growth with the elevated temperature for 12C ions but keep constant for 209Bi ions. The impact of temperature on SEU measurement was analyzed by Monte Carlo simulation. It is revealed that the SEU cross section is significantly affected by the temperature around the threshold linear energy transfer of SEU occurrence. As the SEU occurrence approaches saturation, the SEU cross section gradually exhibits less temperature dependency. Based on this result, the experimental data measured in HIRFL was analyzed, and then a reasonable method of predicting the on-orbit SEU rate was proposed.

  12. Non-volatile magnetic random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-Chuan (Inventor)

    1994-01-01

    Improvements are made in a non-volatile magnetic random access memory. Such a memory is comprised of an array of unit cells, each having a Hall-effect sensor and a thin-film magnetic element made of material having an in-plane, uniaxial anisotropy and in-plane, bipolar remanent magnetization states. The Hall-effect sensor is made more sensitive by using a 1 m thick molecular beam epitaxy grown InAs layer on a silicon substrate by employing a GaAs/AlGaAs/InAlAs superlattice buffering layer. One improvement avoids current shunting problems of matrix architecture. Another improvement reduces the required magnetizing current for the micromagnets. Another improvement relates to the use of GaAs technology wherein high electron-mobility GaAs MESFETs provide faster switching times. Still another improvement relates to a method for configuring the invention as a three-dimensional random access memory.

  13. SEU mitigation strategies for SRAM-based FPGA

    NASA Astrophysics Data System (ADS)

    Luo, Pei; Zhang, Jian

    2011-08-01

    The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the

  14. Remote direct memory access over datagrams

    DOEpatents

    Grant, Ryan Eric; Rashti, Mohammad Javad; Balaji, Pavan; Afsahi, Ahmad

    2014-12-02

    A communication stack for providing remote direct memory access (RDMA) over a datagram network is disclosed. The communication stack has a user level interface configured to accept datagram related input and communicate with an RDMA enabled network interface card (NIC) via an NIC driver. The communication stack also has an RDMA protocol layer configured to supply one or more data transfer primitives for the datagram related input of the user level. The communication stack further has a direct data placement (DDP) layer configured to transfer the datagram related input from a user storage to a transport layer based on the one or more data transfer primitives by way of a lower layer protocol (LLP) over the datagram network.

  15. Parallel Optical Random Access Memory (PORAM)

    NASA Technical Reports Server (NTRS)

    Alphonse, G. A.

    1989-01-01

    It is shown that the need to minimize component count, power and size, and to maximize packing density require a parallel optical random access memory to be designed in a two-level hierarchy: a modular level and an interconnect level. Three module designs are proposed, in the order of research and development requirements. The first uses state-of-the-art components, including individually addressed laser diode arrays, acousto-optic (AO) deflectors and magneto-optic (MO) storage medium, aimed at moderate size, moderate power, and high packing density. The next design level uses an electron-trapping (ET) medium to reduce optical power requirements. The third design uses a beam-steering grating surface emitter (GSE) array to reduce size further and minimize the number of components.

  16. Direct memory access transfer completion notification

    DOEpatents

    Chen, Dong; Giampapa, Mark E.; Heidelberger, Philip; Kumar, Sameer; Parker, Jeffrey J.; Steinmacher-Burow, Burkhard D.; Vranas, Pavlos

    2010-07-27

    Methods, compute nodes, and computer program products are provided for direct memory access (`DMA`) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (`FIFO`) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.

  17. Conductance Quantization in Resistive Random Access Memory.

    PubMed

    Li, Yang; Long, Shibing; Liu, Yang; Hu, Chen; Teng, Jiao; Liu, Qi; Lv, Hangbing; Suñé, Jordi; Liu, Ming

    2015-12-01

    The intrinsic scaling-down ability, simple metal-insulator-metal (MIM) sandwich structure, excellent performances, and complementary metal-oxide-semiconductor (CMOS) technology-compatible fabrication processes make resistive random access memory (RRAM) one of the most promising candidates for the next-generation memory. The RRAM device also exhibits rich electrical, thermal, magnetic, and optical effects, in close correlation with the abundant resistive switching (RS) materials, metal-oxide interface, and multiple RS mechanisms including the formation/rupture of nanoscale to atomic-sized conductive filament (CF) incorporated in RS layer. Conductance quantization effect has been observed in the atomic-sized CF in RRAM, which provides a good opportunity to deeply investigate the RS mechanism in mesoscopic dimension. In this review paper, the operating principles of RRAM are introduced first, followed by the summarization of the basic conductance quantization phenomenon in RRAM and the related RS mechanisms, device structures, and material system. Then, we discuss the theory and modeling of quantum transport in RRAM. Finally, we present the opportunities and challenges in quantized RRAM devices and our views on the future prospects. PMID:26501832

  18. Conductance Quantization in Resistive Random Access Memory

    NASA Astrophysics Data System (ADS)

    Li, Yang; Long, Shibing; Liu, Yang; Hu, Chen; Teng, Jiao; Liu, Qi; Lv, Hangbing; Suñé, Jordi; Liu, Ming

    2015-10-01

    The intrinsic scaling-down ability, simple metal-insulator-metal (MIM) sandwich structure, excellent performances, and complementary metal-oxide-semiconductor (CMOS) technology-compatible fabrication processes make resistive random access memory (RRAM) one of the most promising candidates for the next-generation memory. The RRAM device also exhibits rich electrical, thermal, magnetic, and optical effects, in close correlation with the abundant resistive switching (RS) materials, metal-oxide interface, and multiple RS mechanisms including the formation/rupture of nanoscale to atomic-sized conductive filament (CF) incorporated in RS layer. Conductance quantization effect has been observed in the atomic-sized CF in RRAM, which provides a good opportunity to deeply investigate the RS mechanism in mesoscopic dimension. In this review paper, the operating principles of RRAM are introduced first, followed by the summarization of the basic conductance quantization phenomenon in RRAM and the related RS mechanisms, device structures, and material system. Then, we discuss the theory and modeling of quantum transport in RRAM. Finally, we present the opportunities and challenges in quantized RRAM devices and our views on the future prospects.

  19. 76 FR 55417 - In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-09-07

    ... COMMISSION In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products... States after importation of certain dynamic random access memory and NAND flash memory devices and... the sale within the United States after importation of certain dynamic random access memory and...

  20. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

    DOEpatents

    Ohmacht, Martin

    2014-09-09

    In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

  1. Neutron induced single-word multiple-bit upset in SRAM

    SciTech Connect

    Johansson, K.; Ohlsson, M.; Olsson, N.; Blomgren, J.; Renberg, P.U.

    1999-12-01

    The Single-word Multiple-bit Upset (SMU) frequency for nine commercial Static Random Access Memories (SRAM) have been evaluated at eight different neutron energies: 0-11MeV, 14MeV, 22MeV, 35MeV, 45MeV, 75MeV, 96MeV, 160MeV. The SRAM types used at these experiments have sizes from 256Kbit up to 1Mbit, with date-codes ranging from 9209 up to 9809. The result showed a slightly rising dependence on the neutron energy. Also experiments at two neutron energies, 45MeV and 96MeV, were performed where the supply voltage influence on the SMU-rate was studied. Five device types were used at 96MeV and the supply voltage was changed between 5V, 3.3V and 2.5V. At 45MeV three devices at 5V and 3.3V were irradiated. The experiments showed a relation between the amount of total upset and SMU that indicates no clear supply voltage dependence.

  2. BCH codes for large IC random-access memory systems

    NASA Technical Reports Server (NTRS)

    Lin, S.; Costello, D. J., Jr.

    1983-01-01

    In this report some shortened BCH codes for possible applications to large IC random-access memory systems are presented. These codes are given by their parity-check matrices. Encoding and decoding of these codes are discussed.

  3. Radiation Effects of Commercial Resistive Random Access Memories

    NASA Technical Reports Server (NTRS)

    Chen, Dakai; LaBel, Kenneth; Berg, Melanie; Wilcox, Edward; Kim, Hak; Phan, Anthony; Figueiredo, Marco; Buchner, Stephen; Khachatrian, Ani; Roche, Nicolas

    2014-01-01

    We present results for the single-event effect response of commercial production-level resistive random access memories. We found that the resistive memory arrays are immune to heavy ion-induced upsets. However, the devices were susceptible to single-event functional interrupts, due to upsets from the control circuits. The intrinsic radiation tolerant nature of resistive memory makes the technology an attractive consideration for future space applications.

  4. The Dynamics of Access to Groups in Working Memory

    ERIC Educational Resources Information Center

    Farrell, Simon; Lelievre, Anna

    2012-01-01

    The finding that participants leave a pause between groups when attempting serial recall of temporally grouped lists has been taken to indicate access to a hierarchical representation of the list in working memory. An alternative explanation is that the dynamics of serial recall solely reflect output (rather than memorial) processes, with the…

  5. Clementine RRELAX SRAM Particle Spectrometer

    NASA Technical Reports Server (NTRS)

    Buehler, M.; Soli, G.; Blaes, B.; Ratliff, J.; Garrett, H.

    1994-01-01

    The Clementine RRELAX radiation monitor chip consists of a p-FET total dose monitor and a 4-kbit SRAM particle spectrometer. Eight of these chips were included in the RRELAX and used to detect the passage of the Clementine (S/C) and the innerstage adapter (ISA) through the earth's radiation belts and the 21-Feb 1994 solar flare. This is the first space flight for this 1.2 micron rad-soft custom CMOS radiation monitor. This paper emphasizes results from the SRAM particle detector which showed that it a) has a detection range of five orders of magnitude relative to the 21-Feb solar flare, b) is not affected by electrons, and c) detected microflares occurring with a 26.5 day period.

  6. Direct access inter-process shared memory

    DOEpatents

    Brightwell, Ronald B; Pedretti, Kevin; Hudson, Trammell B

    2013-10-22

    A technique for directly sharing physical memory between processes executing on processor cores is described. The technique includes loading a plurality of processes into the physical memory for execution on a corresponding plurality of processor cores sharing the physical memory. An address space is mapped to each of the processes by populating a first entry in a top level virtual address table for each of the processes. The address space of each of the processes is cross-mapped into each of the processes by populating one or more subsequent entries of the top level virtual address table with the first entry in the top level virtual address table from other processes.

  7. Memory for recently accessed visual attributes.

    PubMed

    Jiang, Yuhong V; Shupe, Joshua M; Swallow, Khena M; Tan, Deborah H

    2016-08-01

    Recent reports have suggested that the attended features of an item may be rapidly forgotten once they are no longer relevant for an ongoing task (attribute amnesia). This finding relies on a surprise memory procedure that places high demands on declarative memory. We used intertrial priming to examine whether the representation of an item's identity is lost completely once it becomes task irrelevant. If so, then the identity of a target on one trial should not influence performance on the next trial. In 3 experiments, we replicated the finding that a target's identity is poorly recognized in a surprise memory test. However, we also observed location and identity repetition priming across consecutive trials. These data suggest that, although explicit recognition on a surprise memory test may be impaired, some information about a particular target's identity can be retained after it is no longer needed for a task. (PsycINFO Database Record PMID:26844575

  8. Integrated semiconductor-magnetic random access memory system

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Blaes, Brent R. (Inventor)

    2001-01-01

    The present disclosure describes a non-volatile magnetic random access memory (RAM) system having a semiconductor control circuit and a magnetic array element. The integrated magnetic RAM system uses CMOS control circuit to read and write data magnetoresistively. The system provides a fast access, non-volatile, radiation hard, high density RAM for high speed computing.

  9. Simulation and research on a 4T-cell based duplication redundancy SRAM for SEU radiation hardening

    NASA Astrophysics Data System (ADS)

    Xinhong, Hong; Liyang, Pan; Wendi, Zhang; Dongmei, Ji; Dong, Wu; Chen, Shen; Jun, Xu

    2015-11-01

    A novel 4T-cell based duplication redundancy SRAM is proposed for SEU radiation hardening applications. The memory cell is designed with a 65-nm low leakage process; the operation principle and the SEU radiation hardening mechanism are discussed in detail. The SEE characteristics and failure mechanism are also studied with a 3-D device simulator. The results show that the proposed SRAM structure exhibits high SEU hardening performance with a small cell size.

  10. Scaling Linear Algebra Kernels using Remote Memory Access

    SciTech Connect

    Krishnan, Manoj Kumar; Lewis, Robert R.; Vishnu, Abhinav

    2010-09-13

    This paper describes the scalability of linear algebra kernels based on remote memory access approach. The current approach differs from the other linear algebra algorithms by the explicit use of shared memory and remote memory access (RMA) communication rather than message passing. It is suitable for clusters and scalable shared memory systems. The experimental results on large scale systems (Linux-Infiniband cluster, Cray XT) demonstrate consistent performance advantages over ScaLAPACK suite, the leading implementation of parallel linear algebra algorithms used today. For example, on a Cray XT4 for a matrix size of 102400, our RMA-based matrix multiplication achieved over 55 teraflops while ScaLAPACK’s pdgemm measured close to 42 teraflops on 10000 processes.

  11. A Cerebellar-model Associative Memory as a Generalized Random-access Memory

    NASA Technical Reports Server (NTRS)

    Kanerva, Pentti

    1989-01-01

    A versatile neural-net model is explained in terms familiar to computer scientists and engineers. It is called the sparse distributed memory, and it is a random-access memory for very long words (for patterns with thousands of bits). Its potential utility is the result of several factors: (1) a large pattern representing an object or a scene or a moment can encode a large amount of information about what it represents; (2) this information can serve as an address to the memory, and it can also serve as data; (3) the memory is noise tolerant--the information need not be exact; (4) the memory can be made arbitrarily large and hence an arbitrary amount of information can be stored in it; and (5) the architecture is inherently parallel, allowing large memories to be fast. Such memories can become important components of future computers.

  12. 75 FR 14467 - In the Matter of: Certain Dynamic Random Access Memory Semiconductors and Products Containing...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-03-25

    ... COMMISSION In the Matter of: Certain Dynamic Random Access Memory Semiconductors and Products Containing Same... random access memory semiconductors and products containing same, including memory modules, by reason of... after importation of certain dynamic random access memory semiconductors or products containing the...

  13. Fin shape fluctuations in FinFET: Correlation to electrical variability and impact on 6-T SRAM noise margins

    NASA Astrophysics Data System (ADS)

    Baravelli, Emanuele; De Marchi, Luca; Speciale, Nicolò

    2009-12-01

    Threshold voltage (VT) and drive current (ION) variability of low stand-by power (LSTP)-32 nm FinFETs subject to fin line-edge roughness (LER) is investigated through Technology Computer-Aided Design (TCAD) simulations featuring quantum-corrected hydrodynamic transport. Statistical results provided by an ensemble Monte Carlo (MC) approach highlight an increase in the average VT and a decrease in the average ION with respect to sensitivity analysis based predictions. Correlations of fin shape fluctuations to electrical performance are investigated, thus assessing further limitations of sensitivity analysis and proposing better alternatives to the expensive MC approach. An equivalent fin width is calculated, which allows reducing the spread in ION scatter plots and highlights relative importance of LER in different fin regions. Simplified device instances with linearly varying fin width are simulated to better assess the impact of local thinning/thickening in the channel, source and drain extensions. Asymmetries in the device behavior are observed upon swapping the taper direction and the critical role of extensions is identified. Moreover, the impact of LER on noise margins of FinFET-based Static Random Access Memories (SRAMs) is investigated, considering the hold, read and write operating modes. Results are compared to published data on fabricated cells with similar device features. " μ-6σ" statistics extracted from 1000 mixed-mode simulations helps with assessing variability concerns for mainstream integration of aggressively scaled of FinFET-SRAMs.

  14. Direct memory access transfer completion notification

    DOEpatents

    Archer, Charles J.; Blocksome, Michael A.; Parker, Jeffrey J.

    2011-02-15

    DMA transfer completion notification includes: inserting, by an origin DMA engine on an origin node in an injection first-in-first-out (`FIFO`) buffer, a data descriptor for an application message to be transferred to a target node on behalf of an application on the origin node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying a packet header for a completion notification packet; transferring, by the origin DMA engine to the target node, the message in dependence upon the data descriptor; sending, by the origin DMA engine, the completion notification packet to a local reception FIFO buffer using a local memory FIFO transfer operation; and notifying, by the origin DMA engine, the application that transfer of the message is complete in response to receiving the completion notification packet in the local reception FIFO buffer.

  15. Magnetic Random Access Memory (MRAM) Device Development

    SciTech Connect

    Cerjan, C; Law, B P

    2000-01-18

    The recent discovery of materials that have anomalous magneto-resistive properties has generated renewed commercial interest in metal-based fast memory storage as an alternative to the currently used semiconductor-based devices. One particularly promising ternary alloy, fabricated at LLNL, appeared to have exceptional field response. This proposal extended the investigation of this class of materials by examining the scaling properties of test structures made from this material that could definitively verify the preliminary observations of high field sensitivity. Although the expected scaling was observed, technical issues, such as excessive oxidation, prevented a definitive assessment of the effect. Despite the difficulties encountered, several test structures demonstrated superior performance in a ''spin-valve'' configuration that might have applications for very high density recording heads.

  16. Access Analysis-Based Tight Localization of Abstract Memories

    NASA Astrophysics Data System (ADS)

    Oh, Hakjoo; Brutschy, Lucas; Yi, Kwangkeun

    On-the-fly localization of abstract memory states is vital for economical abstract interpretation of imperative programs. Such localization is sometimes called "abstract garbage collection" or "framing". In this article we present a new memory localization technique that is more effective than the conventional reachability-based approach. Our technique is based on a key observation that collecting the reachable memory parts is too conservative and the accessed parts are usually tiny subsets of the reachable. Our technique first estimates, by an efficient pre-analysis, the set of locations that will be accessed during the analysis of each code block. Then the main analysis uses the access-set results to trim the memory entries before analyzing code blocks. In experiments with an industrial-strength global C static analyzer, the technique is applied right before analyzing each procedure's body and reduces the average analysis time and memory by 92.1% and 71.2%, respectively, without sacrificing the analysis precision. Localizing more frequently such as at loop bodies and basic blocks as well as procedure bodies, the generalized localization additionally reduces analysis time by an average of 31.8%.

  17. A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

    SciTech Connect

    Quinn, Heather M; Graham, Paul S; Morgan, Keith S; Caffrey, Michael P

    2008-01-01

    Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.

  18. AYUSH: A Technique for Extending Lifetime of SRAM-NVM Hybrid Caches

    SciTech Connect

    Mittal, Sparsh; Vetter, Jeffrey S

    2014-01-01

    Recently, researchers have explored way-based hybrid SRAM-NVM (non-volatile memory) last level caches (LLCs) to bring the best of SRAM and NVM together. However, the limited write endurance of NVMs restricts the lifetime of these hybrid caches. We present AYUSH, a technique to enhance the lifetime of hybrid caches, which works by using data-migration to preferentially use SRAM for storing frequently-reused data. Microarchitectural simulations confirm that AYUSH achieves larger improvement in lifetime than a previous technique and also maintains performance and energy efficiency. For single, dual and quad-core workloads, the average increase in cache lifetime with AYUSH is 6.90X, 24.06X and 47.62X, respectively.

  19. Quantifying Locality in the Memory Access Patterns of HPCApplications

    SciTech Connect

    Weinberg, Jonathan; Snavely, Allan; McCracken, Michael O.; Strohmaier, Erich

    2005-07-25

    Several benchmarks for measuring memory performance of HPC systems along dimensions of spatial and temporal memory locality have recently been proposed. However, little is understood about the relationships of these benchmarks to real applications and to each other. In this paper, we propose a methodology for producing architecture-neutral characterizations of the spatial and temporal locality exhibited by the memory access patterns of applications. We demonstrate that the results track intuitive notions of spatial and temporal locality on several synthetic and application benchmarks. We employ the methodology to analyze the memory performance components of the HPC Challenge Benchmarks, the Apex-MAP benchmark, and their relationships to each other and other benchmarks and applications. We show that this analysis can be used to both increase understanding of the benchmarks and enhance their usefulness by mapping them, along with applications, to a 2-D space along axes of spatial and temporal locality.

  20. Power Management and SRAM for Energy-Autonomous and Low-Power Systems

    NASA Astrophysics Data System (ADS)

    Chen, Gregory K.

    We demonstrate the two first-known, complete, self-powered millimeter-scale computer systems. These microsystems achieve zero-net-energy operation using solar energy harvesting and ultra-low-power circuits. A medical implant for monitoring intraocular pressure (IOP) is presented as part of a treatment for glaucoma. The 1.5mm3 IOP monitor is easily implantable because of its small size and measures IOP with 0.5mmHg accuracy. It wirelessly transmits data to an external wand while consuming 4.70nJ/bit. This provides rapid feedback about treatment efficacies to decrease physician response time and potentially prevent unnecessary vision loss. A nearly-perpetual temperature sensor is presented that processes data using a 2.1muW near-threshold ARMRTM Cortex-M3(TM) muP that provides a widely-used and trusted programming platform. Energy harvesting and power management techniques for these two microsystems enable energy-autonomous operation. The IOP monitor harvests 80nW of solar power while consuming only 5.3nW, extending lifetime indefinitely. This allows the device to provide medical information for extended periods of time, giving doctors time to converge upon the best glaucoma treatment. The temperature sensor uses on-demand power delivery to improve low-load dc-dc voltage conversion efficiency by 4.75x. It also performs linear regulation to deliver power with low noise, improved load regulation, and tight line regulation. Low-power high-throughput SRAM techniques help millimeter-scale microsystems meet stringent power budgets. VDD scaling in memory decreases energy per access, but also decreases stability margins. These margins can be improved using sizing, VTH selection, and assist circuits, as well as new bitcell designs. Adaptive Crosshairs modulation of SRAM power supplies fixes 70% of parametric failures. Half-differential SRAM design improves stability, reducing VMIN by 72mV. The circuit techniques for energy autonomy presented in this dissertation enable

  1. CMOS Interface Circuits for Spin Tunneling Junction Based Magnetic Random Access Memories

    SciTech Connect

    Ganesh Saripalli

    2002-12-31

    Magneto resistive memories (MRAM) are non-volatile memories which use magnetic instead of electrical structures to store data. These memories, apart from being non-volatile, offer a possibility to achieve densities better than DRAMs and speeds faster than SRAMs. MRAMs could potentially replace all computer memory RAM technologies in use today, leading to future applications like instan-on computers and longer battery life for pervasive devices. Such rapid development was made possible due to the recent discovery of large magnetoresistance in Spin tunneling junction devices. Spin tunneling junctions (STJ) are composite structures consisting of a thin insulating layer sandwiched between two magnetic layers. This thesis research is targeted towards these spin tunneling junction based Magnetic memories. In any memory, some kind of an interface circuit is needed to read the logic states. In this thesis, four such circuits are proposed and designed for Magnetic memories (MRAM). These circuits interface to the Spin tunneling junctions and act as sense amplifiers to read their magnetic states. The physical structure and functional characteristics of these circuits are discussed in this thesis. Mismatch effects on the circuits and proper design techniques are also presented. To demonstrate the functionality of these interface structures, test circuits were designed and fabricated in TSMC 0.35{micro} CMOS process. Also circuits to characterize the process mismatches were fabricated and tested. These results were then used in Matlab programs to aid in design process and to predict interface circuit's yields.

  2. Kokkos: Enabling manycore performance portability through polymorphic memory access patterns

    SciTech Connect

    Carter Edwards, H.; Trott, Christian R.; Sunderland, Daniel

    2014-07-22

    The manycore revolution can be characterized by increasing thread counts, decreasing memory per thread, and diversity of continually evolving manycore architectures. High performance computing (HPC) applications and libraries must exploit increasingly finer levels of parallelism within their codes to sustain scalability on these devices. We found that a major obstacle to performance portability is the diverse and conflicting set of constraints on memory access patterns across devices. Contemporary portable programming models address manycore parallelism (e.g., OpenMP, OpenACC, OpenCL) but fail to address memory access patterns. The Kokkos C++ library enables applications and domain libraries to achieve performance portability on diverse manycore architectures by unifying abstractions for both fine-grain data parallelism and memory access patterns. In this paper we describe Kokkos’ abstractions, summarize its application programmer interface (API), present performance results for unit-test kernels and mini-applications, and outline an incremental strategy for migrating legacy C++ codes to Kokkos. Furthermore, the Kokkos library is under active research and development to incorporate capabilities from new generations of manycore architectures, and to address a growing list of applications and domain libraries.

  3. Kokkos: Enabling manycore performance portability through polymorphic memory access patterns

    DOE PAGESBeta

    Carter Edwards, H.; Trott, Christian R.; Sunderland, Daniel

    2014-07-22

    The manycore revolution can be characterized by increasing thread counts, decreasing memory per thread, and diversity of continually evolving manycore architectures. High performance computing (HPC) applications and libraries must exploit increasingly finer levels of parallelism within their codes to sustain scalability on these devices. We found that a major obstacle to performance portability is the diverse and conflicting set of constraints on memory access patterns across devices. Contemporary portable programming models address manycore parallelism (e.g., OpenMP, OpenACC, OpenCL) but fail to address memory access patterns. The Kokkos C++ library enables applications and domain libraries to achieve performance portability on diversemore » manycore architectures by unifying abstractions for both fine-grain data parallelism and memory access patterns. In this paper we describe Kokkos’ abstractions, summarize its application programmer interface (API), present performance results for unit-test kernels and mini-applications, and outline an incremental strategy for migrating legacy C++ codes to Kokkos. Furthermore, the Kokkos library is under active research and development to incorporate capabilities from new generations of manycore architectures, and to address a growing list of applications and domain libraries.« less

  4. Resistive random access memory utilizing ferritin protein with Pt nanoparticles

    NASA Astrophysics Data System (ADS)

    Uenuma, Mutsunori; Kawano, Kentaro; Zheng, Bin; Okamoto, Naofumi; Horita, Masahiro; Yoshii, Shigeo; Yamashita, Ichiro; Uraoka, Yukiharu

    2011-05-01

    This study reports controlled single conductive paths found in resistive random access memory (ReRAM) formed by embedding Pt nanoparticles (Pt NPs) in NiO film. Homogeneous Pt NPs produced and placed by ferritin protein produce electric field convergence which leads to controlled conductive path formation. The ReRAM with Pt NPs shows stable switching behavior. A Pt NP density decrease results in an increase of OFF state resistance and decrease of forming voltage, whereas ON resistance was independent of the Pt NP density, which indicates that a single metal NP in a memory cell will achieve low power and stable operation.

  5. Integrated, nonvolatile, high-speed analog random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor)

    1994-01-01

    This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

  6. Magnet/Hall-Effect Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1991-01-01

    In proposed magnet/Hall-effect random-access memory (MHRAM), bits of data stored magnetically in Perm-alloy (or equivalent)-film memory elements and read out by using Hall-effect sensors to detect magnetization. Value of each bit represented by polarity of magnetization. Retains data for indefinite time or until data rewritten. Speed of Hall-effect sensors in MHRAM results in readout times of about 100 nanoseconds. Other characteristics include high immunity to ionizing radiation and storage densities of order 10(Sup6)bits/cm(Sup 2) or more.

  7. Performance Evaluation of Remote Memory Access (RMA) Programming on Shared Memory Parallel Computers

    NASA Technical Reports Server (NTRS)

    Jin, Hao-Qiang; Jost, Gabriele; Biegel, Bryan A. (Technical Monitor)

    2002-01-01

    The purpose of this study is to evaluate the feasibility of remote memory access (RMA) programming on shared memory parallel computers. We discuss different RMA based implementations of selected CFD application benchmark kernels and compare them to corresponding message passing based codes. For the message-passing implementation we use MPI point-to-point and global communication routines. For the RMA based approach we consider two different libraries supporting this programming model. One is a shared memory parallelization library (SMPlib) developed at NASA Ames, the other is the MPI-2 extensions to the MPI Standard. We give timing comparisons for the different implementation strategies and discuss the performance.

  8. Paging memory from random access memory to backing storage in a parallel computer

    DOEpatents

    Archer, Charles J; Blocksome, Michael A; Inglett, Todd A; Ratterman, Joseph D; Smith, Brian E

    2013-05-21

    Paging memory from random access memory (`RAM`) to backing storage in a parallel computer that includes a plurality of compute nodes, including: executing a data processing application on a virtual machine operating system in a virtual machine on a first compute node; providing, by a second compute node, backing storage for the contents of RAM on the first compute node; and swapping, by the virtual machine operating system in the virtual machine on the first compute node, a page of memory from RAM on the first compute node to the backing storage on the second compute node.

  9. 76 FR 73676 - Certain Dynamic Random Access Memory Devices, and Products Containing Same; Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-11-29

    ... COMMISSION Certain Dynamic Random Access Memory Devices, and Products Containing Same; Receipt of Complaint... complaint entitled In Re Certain Dynamic Random Access Memory Devices, and Products Containing Same, DN 2859... within the United States after importation of certain dynamic random access memory devices, and...

  10. 76 FR 80964 - Certain Dynamic Random Access Memory Devices, and Products Containing Same; Institution of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-12-27

    ... COMMISSION Certain Dynamic Random Access Memory Devices, and Products Containing Same; Institution of... States after importation of certain dynamic random access memory devices, and products containing same by... dynamic random access memory devices, and products containing same that infringe one or more of claims...

  11. Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order

    NASA Technical Reports Server (NTRS)

    Wulf, William A. (Inventor); McKee, Sally A. (Inventor); Klenke, Robert (Inventor); Schwab, Andrew J. (Inventor); Moyer, Stephen A. (Inventor); Aylor, James (Inventor); Hitchcock, Charles Young (Inventor)

    2000-01-01

    A data processing system is disclosed which comprises a data processor and memory control device for controlling the access of information from the memory. The memory control device includes temporary storage and decision ability for determining what order to execute the memory accesses. The compiler detects the requirements of the data processor and selects the data to stream to the memory control device which determines a memory access order. The order in which to access said information is selected based on the location of information stored in the memory. The information is repeatedly accessed from memory and stored in the temporary storage until all streamed information is accessed. The information is stored until required by the data processor. The selection of the order in which to access information maximizes bandwidth and decreases the retrieval time.

  12. Nonvolatile GaAs Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.; Stadler, Henry L.; Wu, Jiin-Chuan

    1994-01-01

    Proposed random-access integrated-circuit electronic memory offers nonvolatile magnetic storage. Bits stored magnetically and read out with Hall-effect sensors. Advantages include short reading and writing times and high degree of immunity to both single-event upsets and permanent damage by ionizing radiation. Use of same basic material for both transistors and sensors simplifies fabrication process, with consequent benefits in increased yield and reduced cost.

  13. If memory serves, will language? Later verbal accessibility of early memories.

    PubMed

    Bauer, P J; Kroupina, M G; Schwade, J A; Dropik, P L; Wewerka, S S

    1998-01-01

    Of major interest to those concerned with early mnemonic process and function is the question of whether early memories likely encoded without the benefit of language later are accessible to verbal report. In the context of a controlled laboratory study, we examined this question in children who were 16 and 20 months at the time of exposure to specific target events and who subsequently were tested for their memories of the events after a delay of either 6 or 12 months (at 22-32 months) and then again at 3 years. At the first delayed-recall test, children evidenced memory both nonverbally and verbally. Nonverbal mnemonic expression was related to age at the time of test; verbal mnemonic expression was related to verbal fluency at the time of test. At the second delayed-recall test, children evidenced continued accessibility of their early memories. Verbal mnemonic expression was related to previous mnemonic expression, both nonverbal and verbal, each of which contributed unique variance. The relevance of these findings on memory for controlled laboratory events for issues of memory for traumatic experiences is discussed. PMID:9886220

  14. Vortex-Core Reversal Dynamics: Towards Vortex Random Access Memory

    NASA Astrophysics Data System (ADS)

    Kim, Sang-Koog

    2011-03-01

    An energy-efficient, ultrahigh-density, ultrafast, and nonvolatile solid-state universal memory is a long-held dream in the field of information-storage technology. The magnetic random access memory (MRAM) along with a spin-transfer-torque switching mechanism is a strong candidate-means of realizing that dream, given its nonvolatility, infinite endurance, and fast random access. Magnetic vortices in patterned soft magnetic dots promise ground-breaking applications in information-storage devices, owing to the very stable twofold ground states of either their upward or downward core magnetization orientation and plausible core switching by in-plane alternating magnetic fields or spin-polarized currents. However, two technologically most important but very challenging issues --- low-power recording and reliable selection of each memory cell with already existing cross-point architectures --- have not yet been resolved for the basic operations in information storage, that is, writing (recording) and readout. Here, we experimentally demonstrate a magnetic vortex random access memory (VRAM) in the basic cross-point architecture. This unique VRAM offers reliable cell selection and low-power-consumption control of switching of out-of-plane core magnetizations using specially designed rotating magnetic fields generated by two orthogonal and unipolar Gaussian-pulse currents along with optimized pulse width and time delay. Our achievement of a new device based on a new material, that is, a medium composed of patterned vortex-state disks, together with the new physics on ultrafast vortex-core switching dynamics, can stimulate further fruitful research on MRAMs that are based on vortex-state dot arrays.

  15. Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

    NASA Astrophysics Data System (ADS)

    Huynh-Bao, Trong; Ryckaert, Julien; Sakhare, Sushil; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron; Wambacq, Piet

    2016-03-01

    In this paper, we present a layout and performance analysis of logic and SRAM circuits for vertical and lateral GAA FETs using 5nm (iN5) design rules. Extreme ultra-violet lithography (EUVL) processes are exploited to print the critical features: 32 nm gate pitch and 24 nm metal pitch. Layout architectures and patterning compromises for enabling the 5nm node will be discussed in details. A distinct standard-cell template for vertical FETs is proposed and elaborated for the first time. To assess electrical performances, a BSIM-CMG model has been developed and calibrated with TCAD simulations, which accounts for the quasi-ballistic transport in the nanowire channel. The results show that the inbound power rail layout construct for vertical devices could achieve the highest density while the interleaving diffusion template can maximize the port accessibility. By using a representative critical path circuit of a generic low power SoCs, it is shown that the VFET-based circuit is 40% more energy efficient than LFET designs at iso-performance. Regarding SRAMs, benefits given by vertical channel orientation in VFETs has reduced the SRAM area by 20%~30% compared to lateral SRAMs. A double exposures with EUV canner is needed to reach a minimum tip-to-tip (T2T) of 16 nm for middle-of-line (MOL) layers. To enable HD SRAMs with two metal layers, a fully self-aligned gate contact for LFETs and 2D routing of the top electrode for VFETs are required. The standby leakage of vertical SRAMs is 4~6X lower than LFET-based SRAMs at iso-performance and iso-area. The minimum operating voltage (Vmin) of vertical SRAMs is 170 mV lower than lateral SRAMs. A high-density SRAM bitcell of 0.014 um2 can be obtained for the iN5 technology node, which fully follows the SRAM scaling trend for the 45nm nodes and beyond.

  16. Proton-sensitive custom SRAM detector

    SciTech Connect

    Soli, G.A.; Blaes, B.R.; Buehler, M.G. )

    1992-10-01

    Because of the recently discovered importance of protons to the upset of spaceborne electronics, a custom 4--bit SRAM chip was tested with protons. The SRAM was developed to determine the Single Event Upset hardness of CMOS latches using alpha particle measurements, by adjusting an offset voltage that reduces the charge required to upset a cell. The proton experiments were designed to observe both proton and silicon recoil produced ionization. The silicon recoils were generated by protons undergoing nuclear coulomb scattering. It was discovered that silicon recoil produced charge can be collected from very deep in the silicon substrate. This paper describes a calibration procedure for rhe SRAM detector. Source spectra were acquired with this chip by measuring the number of upset cells versus offset voltage.

  17. Serendipitous SEU hardening of resistive load SRAMs

    SciTech Connect

    Koga, R.; Kirshman, J.F.; Pinkerton, S.D.; Hansel, S.J.; Crawford, K.B.; Crain, W.R.

    1996-06-01

    High and low resistive load versions of Micron Technology`s MT5C1008C (128K {times} 8) and MT5C2561C (256K {times} 1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load. A substantially larger number of multiple-bit errors were observed for the low resistive load SRAMs, which also exhibited a 1 {r_arrow} 0 to 0 {r_arrow} 1 bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations.

  18. Complex dynamics of semantic memory access in reading.

    PubMed

    Baggio, Giosué; Fonseca, André

    2012-02-01

    Understanding a word in context relies on a cascade of perceptual and conceptual processes, starting with modality-specific input decoding, and leading to the unification of the word's meaning into a discourse model. One critical cognitive event, turning a sensory stimulus into a meaningful linguistic sign, is the access of a semantic representation from memory. Little is known about the changes that activating a word's meaning brings about in cortical dynamics. We recorded the electroencephalogram (EEG) while participants read sentences that could contain a contextually unexpected word, such as 'cold' in 'In July it is very cold outside'. We reconstructed trajectories in phase space from single-trial EEG time series, and we applied three nonlinear measures of predictability and complexity to each side of the semantic access boundary, estimated as the onset time of the N400 effect evoked by critical words. Relative to controls, unexpected words were associated with larger prediction errors preceding the onset of the N400. Accessing the meaning of such words produced a phase transition to lower entropy states, in which cortical processing becomes more predictable and more regular. Our study sheds new light on the dynamics of information flow through interfaces between sensory and memory systems during language processing. PMID:21715401

  19. Administering an epoch initiated for remote memory access

    SciTech Connect

    Blocksome, Michael A; Miller, Douglas R

    2014-03-18

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  20. Administering an epoch initiated for remote memory access

    DOEpatents

    Blocksome, Michael A; Miller, Douglas R

    2012-10-23

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  1. Administering an epoch initiated for remote memory access

    DOEpatents

    Blocksome, Michael A.; Miller, Douglas R.

    2013-01-01

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  2. Resistive random access memory enabled by carbon nanotube crossbar electrodes.

    PubMed

    Tsai, Cheng-Lin; Xiong, Feng; Pop, Eric; Shim, Moonsub

    2013-06-25

    We use single-walled carbon nanotube (CNT) crossbar electrodes to probe sub-5 nm memory domains of thin AlOx films. Both metallic and semiconducting CNTs effectively switch AlOx bits between memory states with high and low resistance. The low-resistance state scales linearly with CNT series resistance down to ∼10 MΩ, at which point the ON-state resistance of the AlOx filament becomes the limiting factor. Dependence of switching behavior on the number of cross-points suggests a single channel to dominate the overall characteristics in multi-crossbar devices. We demonstrate ON/OFF ratios up to 5 × 10(5) and programming currents of 1 to 100 nA with few-volt set/reset voltages. Remarkably low reset currents enable a switching power of 10-100 nW and estimated switching energy as low as 0.1-10 fJ per bit. These results are essential for understanding the ultimate scaling limits of resistive random access memory at single-nanometer bit dimensions. PMID:23705675

  3. Efficient Memory Access with NumPy Global Arrays using Local Memory Access

    SciTech Connect

    Daily, Jeffrey A.; Berghofer, Dan C.

    2013-08-03

    This paper discusses the work completed working with Global Arrays of data on distributed multi-computer systems and improving their performance. The tasks completed were done at Pacific Northwest National Laboratory in the Science Undergrad Laboratory Internship program in the summer of 2013 for the Data Intensive Computing Group in the Fundamental and Computational Sciences DIrectorate. This work was done on the Global Arrays Toolkit developed by this group. This toolkit is an interface for programmers to more easily create arrays of data on networks of computers. This is useful because scientific computation is often done on large amounts of data sometimes so large that individual computers cannot hold all of it. This data is held in array form and can best be processed on supercomputers which often consist of a network of individual computers doing their computation in parallel. One major challenge for this sort of programming is that operations on arrays on multiple computers is very complex and an interface is needed so that these arrays seem like they are on a single computer. This is what global arrays does. The work done here is to use more efficient operations on that data that requires less copying of data to be completed. This saves a lot of time because copying data on many different computers is time intensive. The way this challenge was solved is when data to be operated on with binary operations are on the same computer, they are not copied when they are accessed. When they are on separate computers, only one set is copied when accessed. This saves time because of less copying done although more data access operations were done.

  4. An FPGA-Based Test-Bed for Reliability and Endurance Characterization of Non-Volatile Memory

    NASA Technical Reports Server (NTRS)

    Rao, Vikram; Patel, Jagdish; Patel, Janak; Namkung, Jeffrey

    2001-01-01

    Memory technologies are divided into two categories. The first category, nonvolatile memories, are traditionally used in read-only or read-mostly applications because of limited write endurance and slow write speed. These memories are derivatives of read only memory (ROM) technology, which includes erasable programmable ROM (EPROM), electrically-erasable programmable ROM (EEPROM), Flash, and more recent ferroelectric non-volatile memory technology. Nonvolatile memories are able to retain data in the absence of power. The second category, volatile memories, are random access memory (RAM) devices including SRAM and DRAM. Writing to these memories is fast and write endurance is unlimited, so they are most often used to store data that change frequently, but they cannot store data in the absence of power. Nonvolatile memory technologies with better future potential are FRAM, Chalcogenide, GMRAM, Tunneling MRAM, and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) EEPROM.

  5. Spin-Hall-assisted magnetic random access memory

    SciTech Connect

    Brink, A. van den Swagten, H. J. M.; Koopmans, B.; Cosemans, S.; Manfrini, M.; Van Roy, W.; Min, T.; Cornelissen, S.; Vaysset, A.; Departement elektrotechniek , KU Leuven, Kasteelpark Arenberg 10, B-3001 Heverlee

    2014-01-06

    We propose a write scheme for perpendicular spin-transfer torque magnetoresistive random-access memory that significantly reduces the required tunnel current density and write energy. A sub-nanosecond in-plane polarized spin current pulse is generated using the spin-Hall effect, disturbing the stable magnetic state. Subsequent switching using out-of-plane polarized spin current becomes highly efficient. Through evaluation of the Landau-Lifshitz-Gilbert equation, we quantitatively assess the viability of this write scheme for a wide range of system parameters. A typical example shows an eight-fold reduction in tunnel current density, corresponding to a fifty-fold reduction in write energy, while maintaining a 1 ns write time.

  6. Materials selection for oxide-based resistive random access memories

    SciTech Connect

    Guo, Yuzheng; Robertson, John

    2014-12-01

    The energies of atomic processes in resistive random access memories (RRAMs) are calculated for four typical oxides, HfO{sub 2}, TiO{sub 2}, Ta{sub 2}O{sub 5}, and Al{sub 2}O{sub 3}, to define a materials selection process. O vacancies have the lowest defect formation energy in the O-poor limit and dominate the processes. A band diagram defines the operating Fermi energy and O chemical potential range. It is shown how the scavenger metal can be used to vary the O vacancy formation energy, via controlling the O chemical potential, and the mean Fermi energy. The high endurance of Ta{sub 2}O{sub 5} RRAM is related to its more stable amorphous phase and the adaptive lattice rearrangements of its O vacancy.

  7. Complementary resistive switching behavior for conductive bridge random access memory

    NASA Astrophysics Data System (ADS)

    Zheng, Hao-Xuan; Chang, Ting-Chang; Chang, Kuan-Chang; Tsai, Tsung-Ming; Shih, Chih-Cheng; Zhang, Rui; Chen, Kai-Huang; Wang, Ming-Hui; Zheng, Jin-Cheng; Lo, Ikai; Wu, Cheng-Hsien; Tseng, Yi-Ting; Sze, Simon M.

    2016-06-01

    In this study, a structure of Pt/Cu18Si12O70/TiN has been investigated. By co-sputtering the Cu and SiO2 targets in the switching layer, we can measure the operation mechanism of complementary resistive switching (CRS). This differs from conventional conductive bridge random access memory (CBRAM) that tends to use Cu electrodes rather than Cu18Si12O70. By changing the voltage and compliance current, we can control device operating characteristics. Because Cu distributes differently in the device depending on this setting, the operating end can be located at either the top or bottom electrode. Device current–voltage (I–V) curves are used to demonstrate that the CRS in the CBRAM device is a double-electrode operation.

  8. Taxing Working Memory during Retrieval of Emotional Memories Does Not Reduce Memory Accessibility When Cued with Reminders

    PubMed Central

    van Schie, Kevin; Engelhard, Iris M.; van den Hout, Marcel A.

    2015-01-01

    Earlier studies have shown that when individuals recall an emotional memory while simultaneously doing a demanding dual-task [e.g., playing Tetris, mental arithmetic, making eye movements (EM)], this reduces self-reported vividness and emotionality of the memory. These effects have been found up to 1 week later, but have largely been confined to self-report ratings. This study examined whether this dual-tasking intervention reduces memory performance (i.e., accessibility of emotional memories). Undergraduates (N = 60) studied word-image pairs and rated the retrieved image on vividness and emotionality when cued with the word. Then they viewed the cues and recalled the images with or without making EM. Finally, they re-rated the images on vividness and emotionality. Additionally, fragments from images from all conditions were presented and participants identified which fragment was paired earlier with which cue. Findings showed no effect of the dual-task manipulation on self-reported ratings and latency responses. Several possible explanations for the lack of effects are discussed, but the cued recall procedure in our experiment seems to explain the absence of effects best. The study demonstrates boundaries to the effects of the “dual-tasking” procedure. PMID:25729370

  9. Development of a radiation-hardened SRAM with EDAC algorithm for fast readout CMOS pixel sensors for charged particle tracking

    NASA Astrophysics Data System (ADS)

    Wei, X.; Li, B.; Chen, N.; Wang, J.; Zheng, R.; Gao, W.; Wei, T.; Gao, D.; Hu, Y.

    2014-08-01

    CMOS pixel sensors (CPS) are attractive for use in the innermost particle detectors for charged particle tracking due to their good trade-off between spatial resolution, material budget, radiation hardness, and readout speed. With the requirements of high readout speed and high radiation hardness to total ionizing dose (TID) for particle tracking, fast readout CPS are composed by integrating a data compression block and two SRAM IP cores. However, the radiation hardness of the SRAM IP cores is not as high as that of the other parts in CPS, and thus the radiation hardness of the whole CPS chip is lowered. Especially, when CPS are migrated into 0.18-μm processes, the single event upset (SEU) effects should be also considered besides TID and single event latchup (SEL) effects. This paper presents a radiation-hardened SRAM with enhanced radiation hardness to SEU. An error detection and correction (EDAC) algorithm and a bit-interleaving storage strategy are adopted in the design. The prototype design has been fabricated in a 0.18-μm process. The area of the new SRAM is increased 1.6 times as compared with a non-radiation-hardened SRAM due to the integration of EDAC algorithm and the adoption of radiation hardened layout. The access time is increased from 5 ns to 8 ns due to the integration of EDAC algorithm. The test results indicate that the design satisfy requirements of CPS for charged particle tracking.

  10. Laser SEU sensitivity mapping of deep submicron CMOS SRAM

    NASA Astrophysics Data System (ADS)

    Yongtao, Yu; Guoqiang, Feng; Rui, Chen; Jianwei, Han

    2014-06-01

    The pulsed laser facility for SEU sensitivity mapping is utilized to study the SEU sensitive regions of a 0.18 μm CMOS SRAM cell. Combined with the device layout micrograph, SEU sensitivity maps of the SRAM cell are obtained. TCAD simulation work is performed to examine the SEU sensitivity characteristics of the SRAM cell. The laser mapping experiment results are discussed and compared with the electron micrograph information of the SRAM cell and the TCAD simulation results. The results present that the test technique is reliable and of high mapping precision for the deep submicron technology device.

  11. Accessibility versus Accuracy in Retrieving Spatial Memory: Evidence for Suboptimal Assumed Headings

    ERIC Educational Resources Information Center

    Yerramsetti, Ashok; Marchette, Steven A.; Shelton, Amy L.

    2013-01-01

    Orientation dependence in spatial memory has often been interpreted in terms of accessibility: Object locations are encoded relative to a reference orientation that affords the most accurate access to spatial memory. An open question, however, is whether people naturally use this "preferred" orientation whenever recalling the space. We…

  12. 75 FR 44989 - In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-07-30

    ... December 10, 2008, based on a complaint filed by Rambus, Inc. of Los Altos, California (``Rambus''). 73 FR... COMMISSION In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory... chips having synchronous dynamic random access memory controllers and product containing the same...

  13. The Cost of Accessing an Object's Feature Stored in Visual Working Memory

    PubMed Central

    Woodman, Geoffrey F.; Vecera, Shaun P.

    2010-01-01

    The effects of accessing or retrieving information held in working memory are poorly understood compared to what we know about the nature of information storage in this limited-capacity memory system. Previous studies of object-based attention have often relied upon memory-demanding tasks, and this work could indicate that accessing a piece of information in visual working memory may have deleterious effects upon the other representations being maintained. In the present study, we tested the hypothesis that accessing a feature of an object represented in visual working memory degrades the representations of the other stored objects’ features. Our findings support this hypothesis and point to important new questions about the nature of effects resulting from accessing information stored in visual working memory. PMID:21221413

  14. Optimizing NEURON Simulation Environment Using Remote Memory Access with Recursive Doubling on Distributed Memory Systems.

    PubMed

    Shehzad, Danish; Bozkuş, Zeki

    2016-01-01

    Increase in complexity of neuronal network models escalated the efforts to make NEURON simulation environment efficient. The computational neuroscientists divided the equations into subnets amongst multiple processors for achieving better hardware performance. On parallel machines for neuronal networks, interprocessor spikes exchange consumes large section of overall simulation time. In NEURON for communication between processors Message Passing Interface (MPI) is used. MPI_Allgather collective is exercised for spikes exchange after each interval across distributed memory systems. The increase in number of processors though results in achieving concurrency and better performance but it inversely affects MPI_Allgather which increases communication time between processors. This necessitates improving communication methodology to decrease the spikes exchange time over distributed memory systems. This work has improved MPI_Allgather method using Remote Memory Access (RMA) by moving two-sided communication to one-sided communication, and use of recursive doubling mechanism facilitates achieving efficient communication between the processors in precise steps. This approach enhanced communication concurrency and has improved overall runtime making NEURON more efficient for simulation of large neuronal network models. PMID:27413363

  15. Optimizing NEURON Simulation Environment Using Remote Memory Access with Recursive Doubling on Distributed Memory Systems

    PubMed Central

    Bozkuş, Zeki

    2016-01-01

    Increase in complexity of neuronal network models escalated the efforts to make NEURON simulation environment efficient. The computational neuroscientists divided the equations into subnets amongst multiple processors for achieving better hardware performance. On parallel machines for neuronal networks, interprocessor spikes exchange consumes large section of overall simulation time. In NEURON for communication between processors Message Passing Interface (MPI) is used. MPI_Allgather collective is exercised for spikes exchange after each interval across distributed memory systems. The increase in number of processors though results in achieving concurrency and better performance but it inversely affects MPI_Allgather which increases communication time between processors. This necessitates improving communication methodology to decrease the spikes exchange time over distributed memory systems. This work has improved MPI_Allgather method using Remote Memory Access (RMA) by moving two-sided communication to one-sided communication, and use of recursive doubling mechanism facilitates achieving efficient communication between the processors in precise steps. This approach enhanced communication concurrency and has improved overall runtime making NEURON more efficient for simulation of large neuronal network models. PMID:27413363

  16. Single Event Effects on Space Radiation Hardened 64K SRAMS at Room temperature

    NASA Technical Reports Server (NTRS)

    Kim, O.; Schwartz, H.; McCarty, K.; Coss, J.; Barnes, C.

    1993-01-01

    The laser threshold linear Energy transfer for single event upsetscan be estimaed, even at room temperature, for space radiation hardened 64K SRAMs. The memories where independently developed to quality for the Qualified Manufacturer's List by IBM and Honeywell. The memory was so hard that high energy heavy ions generated by the Van de Graff could not determine the SEU threshold at room temperature. Use of pulsed Laser tests would meake it possible to forgo very expensive testing at ultra-high energy accelerators.

  17. Working memory capacity and retrieval limitations from long-term memory: an examination of differences in accessibility.

    PubMed

    Unsworth, Nash; Spillers, Gregory J; Brewer, Gene A

    2012-01-01

    In two experiments, the locus of individual differences in working memory capacity and long-term memory recall was examined. Participants performed categorical cued and free recall tasks, and individual differences in the dynamics of recall were interpreted in terms of a hierarchical-search framework. The results from this study are in accordance with recent theorizing suggesting a strong relation between working memory capacity and retrieval from long-term memory. Furthermore, the results also indicate that individual differences in categorical recall are partially due to differences in accessibility. In terms of accessibility of target information, two important factors drive the difference between high- and low-working-memory-capacity participants. Low-working-memory-capacity participants fail to utilize appropriate retrieval strategies to access cues, and they also have difficulty resolving cue overload. Thus, when low-working-memory-capacity participants were given specific cues that activated a smaller set of potential targets, their recall performance was the same as that of high-working-memory-capacity participants. PMID:22800472

  18. Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests

    DOEpatents

    Gala, Alan; Ohmacht, Martin

    2014-09-02

    A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.

  19. Viable chemical approach for patterning nanoscale magnetoresistive random access memory

    SciTech Connect

    Kim, Taeseung; Kim, Younghee; Chen, Jack Kun-Chieh; Chang, Jane P.

    2015-03-15

    A reactive ion etching process with alternating Cl{sub 2} and H{sub 2} exposures has been shown to chemically etch CoFe film that is an integral component in magnetoresistive random access memory (MRAM). Starting with systematic thermodynamic calculations assessing various chemistries and reaction pathways leading to the highest possible vapor pressure of the etch products reactions, the potential chemical combinations were verified by etch rate investigation and surface chemistry analysis in plasma treated CoFe films. An ∼20% enhancement in etch rate was observed with the alternating use of Cl{sub 2} and H{sub 2} plasmas, in comparison with the use of only Cl{sub 2} plasma. This chemical combination was effective in removing metal chloride layers, thus maintaining the desired magnetic properties of the CoFe films. Scanning electron microscopy equipped with energy-dispersive x-ray spectroscopy showed visually and spectroscopically that the metal chloride layers generated by Cl{sub 2} plasma were eliminated with H{sub 2} plasma to yield a clean etch profile. This work suggests that the selected chemistries can be used to etch magnetic metal alloys with a smooth etch profile and this general strategy can be applied to design chemically based etch processes to enable the fabrication of highly integrated nanoscale MRAM devices.

  20. Radiation dosimetry using three-dimensional optical random access memories

    NASA Technical Reports Server (NTRS)

    Moscovitch, M.; Phillips, G. W.

    2001-01-01

    Three-dimensional optical random access memories (3D ORAMs) are a new generation of high-density data storage devices. Binary information is stored and retrieved via a light induced reversible transformation of an ensemble of bistable photochromic molecules embedded in a polymer matrix. This paper describes the application of 3D ORAM materials to radiation dosimetry. It is shown both theoretically and experimentally, that ionizing radiation in the form of heavy charged particles is capable of changing the information originally stored on the ORAM material. The magnitude and spatial distribution of these changes are used as a measure of the absorbed dose, particle type and energy. The effects of exposure on 3D ORAM materials have been investigated for a variety of particle types and energies, including protons, alpha particles and 12C ions. The exposed materials are observed to fluoresce when exposed to laser light. The intensity and the depth of the fluorescence is dependent on the type and energy of the particle to which the materials were exposed. It is shown that these effects can be modeled using Monte Carlo calculations. The model provides a better understanding of the properties of these materials. which should prove useful for developing systems for charged particle and neutron dosimetry/detector applications. c2001 Published by Elsevier Science B.V.

  1. Predicting fluctuations in widespread interest: memory decay and goal-related memory accessibility in internet search trends.

    PubMed

    Masicampo, E J; Ambady, Nalini

    2014-02-01

    Memory and interest respond in similar ways to people's shifting needs and motivations. We therefore tested whether memory and interest might produce similar, observable patterns in people's responses over time. Specifically, the present studies examined whether fluctuations in widespread interest (as measured by Internet search trends) resemble two well-established memory patterns: memory decay and goal-related memory accessibility. We examined national and international events (e.g., Nobel Prize selections, holidays) that produced spikes in widespread interest in certain people and foods. When the events that triggered widespread interest were incidental (e.g., the death of a celebrity), widespread interest conformed to memory decay patterns: It rose quickly, fell slowly according to a power function, and was higher after the event than before it. When the events that triggered widespread interest were goal related (e.g., political elections), widespread interest conformed to patterns of goal-related memory accessibility: It rose slowly, fell quickly according to a sigmoid function, and was lower after the event than before it. Fluctuations in widespread interest over time are thus similar to standard memory patterns observed at the individual level due perhaps to common mechanisms and functions. PMID:23127417

  2. Adult Age Differences in Accessing and Retrieving Information from Long-Term Memory.

    ERIC Educational Resources Information Center

    Petros, Thomas V.; And Others

    1983-01-01

    Investigated adult age differences in accessing and retrieving information from long-term memory. Results showed that older adults (N=26) were slower than younger adults (N=35) at feature extraction, lexical access, and accessing category information. The age deficit was proportionally greater when retrieval of category information was required.…

  3. Overview of emerging nonvolatile memory technologies

    PubMed Central

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  4. Overview of emerging nonvolatile memory technologies.

    PubMed

    Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  5. Remote Memory Access Protocol Target Node Intellectual Property

    NASA Technical Reports Server (NTRS)

    Haddad, Omar

    2013-01-01

    The MagnetoSpheric Multiscale (MMS) mission had a requirement to use the Remote Memory Access Protocol (RMAP) over its SpaceWire network. At the time, no known intellectual property (IP) cores were available for purchase. Additionally, MMS preferred to implement the RMAP functionality with control over the low-level details of the design. For example, not all the RMAP standard functionality was needed, and it was desired to implement only the portions of the RMAP protocol that were needed. RMAP functionality had been previously implemented in commercial off-the-shelf (COTS) products, but the IP core was not available for purchase. The RMAP Target IP core is a VHDL (VHSIC Hardware Description Language description of a digital logic design suitable for implementation in an FPGA (field-programmable gate array) or ASIC (application-specific integrated circuit) that parses SpaceWire packets that conform to the RMAP standard. The RMAP packet protocol allows a network host to access and control a target device using address mapping. This capability allows SpaceWire devices to be managed in a standardized way that simplifies the hardware design of the device, as well as the development of the software that controls the device. The RMAP Target IP core has some features that are unique and not specified in the RMAP standard. One such feature is the ability to automatically abort transactions if the back-end logic does not respond to read/write requests within a predefined time. When a request times out, the RMAP Target IP core automatically retracts the request and returns a command response with an appropriate status in the response packet s header. Another such feature is the ability to control the SpaceWire node or router using RMAP transactions in the extended address range. This allows the SpaceWire network host to manage the SpaceWire network elements using RMAP packets, which reduces the number of protocols that the network host needs to support.

  6. RAPID: A random access picture digitizer, display, and memory system

    NASA Technical Reports Server (NTRS)

    Yakimovsky, Y.; Rayfield, M.; Eskenazi, R.

    1976-01-01

    RAPID is a system capable of providing convenient digital analysis of video data in real-time. It has two modes of operation. The first allows for continuous digitization of an EIA RS-170 video signal. Each frame in the video signal is digitized and written in 1/30 of a second into RAPID's internal memory. The second mode leaves the content of the internal memory independent of the current input video. In both modes of operation the image contained in the memory is used to generate an EIA RS-170 composite video output signal representing the digitized image in the memory so that it can be displayed on a monitor.

  7. A software solution to estimate the SEU-induced soft error rate for systems implemented on SRAM-based FPGAs

    NASA Astrophysics Data System (ADS)

    Zhongming, Wang; Zhibin, Yao; Hongxia, Guo; Min, Lu

    2011-05-01

    SRAM-based FPGAs are very susceptible to radiation-induced Single-Event Upsets (SEUs) in space applications. The failure mechanism in FPGA's configuration memory differs from those in traditional memory device. As a result, there is a growing demand for methodologies which could quantitatively evaluate the impact of this effect. Fault injection appears to meet such requirement. In this paper, we propose a new methodology to analyze the soft errors in SRAM-based FPGAs. This method is based on in depth understanding of the device architecture and failure mechanisms induced by configuration upsets. The developed programs read in the placed and routed netlist, search for critical logic nodes and paths that may destroy the circuit topological structure, and then query a database storing the decoded relationship of the configurable resources and corresponding control bit to get the sensitive bits. Accelerator irradiation test and fault injection experiments were carried out to validate this approach.

  8. Development of Curie point switching for thin film, random access, memory device

    NASA Technical Reports Server (NTRS)

    Lewicki, G. W.; Tchernev, D. I.

    1967-01-01

    Managanese bismuthide films are used in the development of a random access memory device of high packing density and nondestructive readout capability. Memory entry is by Curie point switching using a laser beam. Readout is accomplished by microoptical or micromagnetic scanning.

  9. Control of Access to Memory: The Use of Task Interference as a Behavioral Probe

    ERIC Educational Resources Information Center

    Loft, Shayne; Humphreys, Michael S.; Whitney, Susannah J.

    2008-01-01

    Directed forgetting and prospective memory methods were combined to examine differences in the control of memory access. Between studying two lists of target words, participants were either instructed to forget the first list, or to continue remembering the first list. After study participants performed a lexical decision task with an additional…

  10. Implications of the spatial dependence of the single-event-upset threshold in SRAMs measured with a pulsed laser

    SciTech Connect

    Buchner, S. SFA Inc., Landover, MD ); Langworthy, J.B.; Stapor, W.J.; Campbell, A.B. ); Rivet, S. )

    1994-12-01

    Pulsed laser light was used to measure single event upset (SEU) thresholds for a large number of memory cells in both CMOS and bipolar SRAMs. Results showed that small variations in intercell upset threshold could not explain the gradual rise in the curve of cross section versus linear energy transfer (LET). The memory cells exhibited greater intracell variations implying that the charge collection efficiency within a memory cell varies spatially and contributes substantially to the shape of the curve of cross section versus LET. The results also suggest that the pulsed laser can be used for hardness-assurance measurements on devices with sensitive areas larger than the diameter of the laser beam.

  11. Scaling constraints in nanoelectronic random-access memories.

    PubMed

    Amsinck, Christian J; Di Spigna, Neil H; Nackashi, David P; Franzon, Paul D

    2005-10-01

    Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F(2)) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simulation approach, the impact of both the device and interconnect architecture on the scalability of a conductivity-state memory system is quantified. This establishes criteria showing the conditions and on/off ratios for the large-scale integration of molecular devices, guiding molecular device design. With 10% readout margin on the resistive load, a memory device needs to have an on/off ratio of at least 7 to be integrated into a 64 x 64 array, while an on/off ratio of 43 is necessary to scale the memory to 512 x 512. PMID:20818005

  12. The structured memory access architecture: An implementation and performance-evaluation

    SciTech Connect

    Cyr, J.B.

    1986-08-01

    The Structured Memory Access (SMS) architecture implementation presented in this thesis is formulated with the intention of alleviating two well-known inefficiencies that exist in current scalar computer architectures: address generation overhead and memory bandwidth utilization. Furthermore, the SMA architecture introduces an additional level of parallelism which is not present in current pipelined supercomputers, namely, overlapped execution of the access process and execute process on two distinct special-purpose, asynchronously-coupled processors. Each processor executes a separate instruction stream to perform its specific task which, together, are functionally equivalent in a conventional program. Our simulation results show that, for typical numerical programs, the access processor (MAP) is capable of achieving slip, i.e., running sufficiently ahead of the execute processor (CP) so that operand fetch requests for data items required by the CP are issued early enough and rapidly enough for the CP rarely to experience any memory access wait time. In this manner the SMA tolerates long memory access time, albeit high bandwidth, paths to memory without sacrificing performance. Speedups relative to the Cray-1 in scalar mode often exceed two, due to dual processing and reductions in memory wait time. 17 refs., 11 figs., 3 tabs.

  13. Integration of lead zirconium titanate thin films for high density ferroelectric random access memory

    NASA Astrophysics Data System (ADS)

    Kim, Kinam; Lee, Sungyung

    2006-09-01

    Interests are being focused on types of nonvolatile memories such as ferroelectric random access memory (FRAM), phase change random access memory, or magnetoresistance random access memory due to their distinct memory properties such as excellent write performance which conventional nonvolatile memories do not possess. Among these types of nonvolatile memories, FRAM whose cell structure and operation are almost identical to dynamic random access memory (DRAM) can ideally realize cell size and speed of DRAM. Thus FRAM is the most appropriate candidate for future universal memory where all memory functions are performed with a single chip solution. Due to the poor ferroelectric properties of downscaled ultrathin lead zirconium titanate (PZT) capacitors as well as technical issues such as hydrogen and plasma related degradation arising from embedding ferroelectric metal-insulator-metal capacitors into conventional complementary metal oxide semiconductor processes, current FRAM still falls far below its ideally attainable cell size and performance. In this paper, based upon PZT capacitor, current mass-productive one pass transistor and one storage capacitor (1T1C), capacitor over bit line (COB) cell technologies are introduced upon which cell size of 0.937μm2 at 250nm minimum feature size technology node has been realized. And then, most recent 1T1C, COB cell technologies are discussed from which cell size of 0.27μm2 at 150nm minimum feature size technology node has been realized, and finally future three dimensional capacitor technologies for the FRAM with cell size of less than 0.08μm2 beyond 100nm minimum feature size technology node are suggested.

  14. Optimization criteria for SRAM design: lithography contribution

    NASA Astrophysics Data System (ADS)

    Cole, Daniel C.; Bula, Orest; Conrad, Edward W.; Coops, Daniel S.; Leipold, William C.; Mann, Randy W.; Oppold, Jeffrey H.

    1999-07-01

    Here we discuss the use of well calibrated resist and etch bias models, in conjunction with a fast microlithography aerial image simulator, to predict and 'optimize' the printed shapes through all critical levels in a dense SRAM design. Our key emphasis here is on 'optimization criteria', namely, having achieved good predictability for printability with lithography models, how to use this capability in conjunction of best electrical performance, yield, and density. The key lithography/design optimization issues discussed here are: (1) tightening of gate width variation by reducing spatial curvature in the source and drain regions, (2) achieving sufficient contact areas, (3) maximizing process window for overlay, (4) reducing leakage mechanisms by reducing contributions of stress and strain due to the printed shape of oxide isolation regions, (5) examining topological differences in design during the optimization process, (6) accounting for mask corner rounding, and (7) designing for scalability to smaller dimensions to achieve optical design reusability issues without hardware.

  15. High speed magneto-resistive random access memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

    1992-01-01

    A high speed read MRAM memory element is configured from a sandwich of magnetizable, ferromagnetic film surrounding a magneto-resistive film which may be ferromagnetic or not. One outer ferromagnetic film has a higher coercive force than the other and therefore remains magnetized in one sense while the other may be switched in sense by a switching magnetic field. The magneto-resistive film is therefore sensitive to the amplitude of the resultant field between the outer ferromagnetic films and may be constructed of a high resistivity, high magneto-resistive material capable of higher sensing currents. This permits higher read voltages and therefore faster read operations. Alternate embodiments with perpendicular anisotropy, and in-plane anisotropy are shown, including an embodiment which uses high permeability guides to direct the closing flux path through the magneto-resistive material. High density, high speed, radiation hard, memory matrices may be constructed from these memory elements.

  16. Dynamic Optical Gratings Accessed by Reversible Shape Memory.

    PubMed

    Tippets, Cary A; Li, Qiaoxi; Fu, Yulan; Donev, Eugenii U; Zhou, Jing; Turner, Sara A; Jackson, Anne-Martine S; Ashby, Valerie Sheares; Sheiko, Sergei S; Lopez, Rene

    2015-07-01

    Shape memory polymers (SMPs) have been shown to accurately replicate photonic structures that produce tunable optical responses, but in practice, these responses are limited by the irreversibility of conventional shape memory processes. Here, we report the intensity modulation of a diffraction grating utilizing two-way reversible shape changes. Reversible shifting of the grating height was accomplished through partial melting and recrystallization of semicrystalline poly(octylene adipate). The concurrent variations of the grating shape and diffraction intensity were monitored via atomic force microscopy and first order diffraction measurements, respectively. A maximum reversibility of the diffraction intensity of 36% was repeatable over multiple cycles. To that end, the reversible shape memory process is shown to broaden the functionality of SMP-based optical devices. PMID:26081101

  17. Hybrid Flexible Resistive Random Access Memory-Gated Transistor for Novel Nonvolatile Data Storage.

    PubMed

    Han, Su-Ting; Zhou, Ye; Chen, Bo; Wang, Chundong; Zhou, Li; Yan, Yan; Zhuang, Jiaqing; Sun, Qijun; Zhang, Hua; Roy, V A L

    2016-01-20

    Here, a single-device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch gate for field effect transistor (FET) on a flexible substrate. A high performance flexible RRAM with a three-layered structure is fabricated by utilizing solution-processed MoS2 nanosheets sandwiched between poly(methyl methacrylate) polymer layers. Gate coupling with the pentacene-based transistor can be controlled by the RRAM memory state to produce a nonprogrammed state (inactive) and a programmed state (active) with a well-defined memory window. Compared to the reference flash memory device based on the MoS2 floating gate, the hybrid device presents robust access speed and retention ability. Furthermore, the hybrid RRAM-gated FET is used to build an integrated logic circuit and a wide logic window in inverter logic is achieved. The controllable, well-defined memory window, long retention time, and fast access speed of this novel hybrid device may open up new possibilities of realizing fully functional nonvolatile memory for high-performance flexible electronics. PMID:26578160

  18. Asymmetrical access to color and location in visual working memory.

    PubMed

    Rajsic, Jason; Wilson, Daryl E

    2014-10-01

    Models of visual working memory (VWM) have benefitted greatly from the use of the delayed-matching paradigm. However, in this task, the ability to recall a probed feature is confounded with the ability to maintain the proper binding between the feature that is to be reported and the feature (typically location) that is used to cue a particular item for report. Given that location is typically used as a cue-feature, we used the delayed-estimation paradigm to compare memory for location to memory for color, rotating which feature was used as a cue and which was reported. Our results revealed several novel findings: 1) the likelihood of reporting a probed object's feature was superior when reporting location with a color cue than when reporting color with a location cue; 2) location report errors were composed entirely of swap errors, with little to no random location reports; and 3) both colour and location reports greatly benefitted from the presence of nonprobed items at test. This last finding suggests that it is uncertainty over the bindings between locations and colors at memory retrieval that drive swap errors, not at encoding. We interpret our findings as consistent with a representational architecture that nests remembered object features within remembered locations. PMID:25190322

  19. Phase-change Random Access Memory: A Scalable Technology

    SciTech Connect

    Raoux, S.; Burr, G; Breitwisch, M; Rettner, C; Chen, Y; Shelby, R; Salinga, M; Krebs, D; Chen, S; Lung, H

    2008-01-01

    Nonvolatile RAM using resistance contrast in phase-change materials [or phase-change RAM (PCRAM)] is a promising technology for future storage-class memory. However, such a technology can succeed only if it can scale smaller in size, given the increasingly tiny memory cells that are projected for future technology nodes (i.e., generations). We first discuss the critical aspects that may affect the scaling of PCRAM, including materials properties, power consumption during programming and read operations, thermal cross-talk between memory cells, and failure mechanisms. We then discuss experiments that directly address the scaling properties of the phase-change materials themselves, including studies of phase transitions in both nanoparticles and ultrathin films as a function of particle size and film thickness. This work in materials directly motivated the successful creation of a series of prototype PCRAM devices, which have been fabricated and tested at phase-change material cross-sections with extremely small dimensions as low as 3 nm x 20 nm. These device measurements provide a clear demonstration of the excellent scaling potential offered by this technology, and they are also consistent with the scaling behavior predicted by extensive device simulations. Finally, we discuss issues of device integration and cell design, manufacturability, and reliability.

  20. Optical interconnection network for parallel access to multi-rank memory in future computing systems.

    PubMed

    Wang, Kang; Gu, Huaxi; Yang, Yintang; Wang, Kun

    2015-08-10

    With the number of cores increasing, there is an emerging need for a high-bandwidth low-latency interconnection network, serving core-to-memory communication. In this paper, aiming at the goal of simultaneous access to multi-rank memory, we propose an optical interconnection network for core-to-memory communication. In the proposed network, the wavelength usage is delicately arranged so that cores can communicate with different ranks at the same time and broadcast for flow control can be achieved. A distributed memory controller architecture that works in a pipeline mode is also designed for efficient optical communication and transaction address processes. The scaling method and wavelength assignment for the proposed network are investigated. Compared with traditional electronic bus-based core-to-memory communication, the simulation results based on the PARSEC benchmark show that the bandwidth enhancement and latency reduction are apparent. PMID:26367901

  1. Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

    SciTech Connect

    Ando, K. Yuasa, S.; Fujita, S.; Ito, J.; Yoda, H.; Suzuki, Y.; Nakatani, Y.; Miyazaki, T.

    2014-05-07

    Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed.

  2. Symmetric Data Objects and Remote Memory Access Communication for Fortran 95-Applications.

    SciTech Connect

    Nieplocha, Jarek; Baxter, Douglas J.; Tipparaju, Vinod; Rasmussen, Craig; Numrich, Robert W.

    2005-08-01

    Symmetric data objects have been introduced by Cray Inc. in context of SHMEM remote memory access communication on Cray T3D/E systems and later adopted by SGI for their Origin servers. Symmetric data objects greatly simplify parallel programming by allowing to reference remote instance of a data structure by specifying address of the local counterpart. The current paper describes how symmetric data objects and remote memory access communication could be implemented in Fortran-95 without requiring specialized hardware or compiler support. NAS Multi-Grid parallel benchmark was used as an application example and demonstrated competitive performance to the standard MPI implementation

  3. Knowledge Accessibility, Achievement Goals, and Memory Strategy Maintenance

    ERIC Educational Resources Information Center

    Escribe, Christian; Huet, Nathalie

    2005-01-01

    Background: An important aim of educational psychology is to account for the difficulties in cognitive strategy maintenance. Possible explanations may be found in developmental studies concerning the interdependence of knowledge accessibility and strategy use, and in current achievement goal models which assume that individuals with a learning…

  4. Characterizing SRAM Single Event Upset in Terms of Single and Double Node Charge Collection

    NASA Technical Reports Server (NTRS)

    Black, J. D.; Ball, D. R., II; Robinson, W. H.; Fleetwood, D. M.; Schrimpf, R. D.; Reed, R. A.; Black, D. A.; Warren, K. M.; Tipton, A. D.; Dodd, P. E.; Haddad, N. F.; Xapsos, M. A.; Kim, H.; Friendlich, M.

    2008-01-01

    A well-collapse source-injection mode for SRAM SEU is demonstrated through TCAD modeling. The recovery of the SRAM s state is shown to be based upon the resistive path from the p+-sources in the SRAM to the well. Multiple cell upset patterns for direct charge collection and the well-collapse source-injection mechanisms are then predicted and compared to recent SRAM test data.

  5. Program partitioning for NUMA multiprocessor computer systems. [Nonuniform memory access

    SciTech Connect

    Wolski, R.M.; Feo, J.T. )

    1993-11-01

    Program partitioning and scheduling are essential steps in programming non-shared-memory computer systems. Partitioning is the separation of program operations into sequential tasks, and scheduling is the assignment of tasks to processors. To be effective, automatic methods require an accurate representation of the model of computation and the target architecture. Current partitioning methods assume today's most prevalent models -- macro dataflow and a homogeneous/two-level multicomputer system. Based on communication channels, neither model represents well the emerging class of NUMA multiprocessor computer systems consisting of hierarchical read/write memories. Consequently, the partitions generated by extant methods do not execute well on these systems. In this paper, the authors extend the conventional graph representation of the macro-dataflow model to enable mapping heuristics to consider the complex communication options supported by NUMA architectures. They describe two such heuristics. Simulated execution times of program graphs show that the model and heuristics generate higher quality program mappings than current methods for NUMA architectures.

  6. Electrical Evaluation of RCA MWS5501D Random Access Memory, Volume 2, Appendix a

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    The electrical characterization and qualification test results are presented for the RCA MWS5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. The address access time, address readout time, the data hold time, and the data setup time are some of the results surveyed.

  7. SRAM-Based Digital Arbiter PUF

    SciTech Connect

    Dondero, Rachel Elizabeth

    2015-05-01

    The increased use of Field Programmable Gate Arrays (FPGAs) in critical systems brings new challenges in securing the diversely programmable fabric from cyber-attacks. FPGAs are an inexpensive, efficient, and flexible alternative to Application Specific Integrated Circuits (ASICs), which are becoming increasingly expensive and impractical for low volume manufacturing as technology nodes continue to shrink. Unfortunately, FPGAs are not designed for high security applications, and their high-flexibility lends itself to low security and vulnerability to malicious attacks. Similar to securing an ASIC’s functionality, FPGA programmers can exploit the inherent randomness introduced into hardware structures during fabrication for security applications. Physically Unclonable Functions (PUFs) are one such solution that uses the die specific variability in hardware fabrication for both secret key generation and verification. PUFs strive to be random, unique, and reliable. Throughout recent years many PUF structures have been presented to try and maximize these three design constraints, reliability being the most difficult of the three to achieve. This thesis presents a new PUF structure that combines two elementary PUF concepts (a bi-stable SRAM PUF and a delay-based arbiter PUF) to create a PUF with increased reliability, while maintaining both random and unique qualities. Properties of the new PUF will be discussed as well as the various design modifications that can be made to tweak the desired performance and overhead.

  8. Making Physical Activity Accessible to Older Adults with Memory Loss: A Feasibility Study

    ERIC Educational Resources Information Center

    Logsdon, Rebecca G.; McCurry, Susan M.; Pike, Kenneth C.; Teri, Linda

    2009-01-01

    Purpose: For individuals with mild cognitive impairment (MCI), memory loss may prevent successful engagement in exercise, a key factor in preventing additional disability. The Resources and Activities for Life Long Independence (RALLI) program uses behavioral principles to make exercise more accessible for these individuals. Exercises are broken…

  9. 77 FR 26789 - Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-07

    ... violation of section 337 in the infringement of certain patents. 73 FR 75131. The principal respondent was... order. 75 FR 44989-90 (July 30, 2010). The Commission also issued cease and desist orders against those... COMMISSION Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers...

  10. Evaluation of Remote Memory Access Communication on the Cray XT3

    SciTech Connect

    Kot, Andriy; Tipparaju, Vinod; Nieplocha, Jarek; Bruggencate, Monika T.; Chrisochoides, Nikos

    2007-03-26

    This paper evaluates remote memory access (RMA) communication capabilities and performance on the Cray XT3. We discuss properties of the network hardware and Portals networking software layer and corresponding implementation issues for SHMEM and ARMCI portable RMA interfaces. The performance of these interfaces is studied and compared to MPI performance

  11. 76 FR 2336 - Dynamic Random Access Memory Semiconductors From the Republic of Korea: Final Results of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-01-13

    ...On September 14, 2010, the Department of Commerce published in the Federal Register its preliminary results of administrative review of the countervailing duty order on dynamic random access memory semiconductors from the Republic of Korea for the period January 1, 2008, through August 10, 2008. We provided interested parties with an opportunity to comment on the preliminary results. Our......

  12. Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOEpatents

    Blocksome, Michael A.; Mamidala, Amith R.

    2013-09-03

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  13. Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOEpatents

    Blocksome, Michael A; Mamidala, Amith R

    2014-02-11

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  14. 75 FR 20564 - Dynamic Random Access Memory Semiconductors from the Republic of Korea: Extension of Time Limit...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-04-20

    ... Antidumping and Countervailing Duty Administrative Reviews and Requests for Revocation in Part, 74 FR 48224... International Trade Administration Dynamic Random Access Memory Semiconductors from the Republic of Korea... administrative review of the countervailing duty order on dynamic random access memory semiconductors from...

  15. 75 FR 44283 - In the Matter of Certain Dynamic Random Access Memory Semiconductors and Products Containing Same...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-07-28

    ... America Corp. of Milpitas, California (collectively ``complainants''). 75 FR 14467-68 (March 25, 2010... COMMISSION In the Matter of Certain Dynamic Random Access Memory Semiconductors and Products Containing Same... within the United States after importation of certain dynamic random access memory semiconductors...

  16. Shared direct memory access on the Explorer 2-LX

    NASA Technical Reports Server (NTRS)

    Musgrave, Jeffrey L.

    1990-01-01

    Advances in Expert System technology and Artificial Intelligence have provided a framework for applying automated Intelligence to the solution of problems which were generally perceived as intractable using more classical approaches. As a result, hybrid architectures and parallel processing capability have become more common in computing environments. The Texas Instruments Explorer II-LX is an example of a machine which combines a symbolic processing environment, and a computationally oriented environment in a single chassis for integrated problem solutions. This user's manual is an attempt to make these capabilities more accessible to a wider range of engineers and programmers with problems well suited to solution in such an environment.

  17. Impact of technology trends on SEU in CMOS SRAMs

    SciTech Connect

    Dodd, P.E.; Sexton, F.W.; Hash, G.L.; Shaneyfelt, M.R.; Draper, B.L.; Farino, A.J.; Flores, R.S.

    1996-12-01

    The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. The authors study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation to the development of a 0.5-{micro}m radiation-hardened CMOS SRAM is presented.

  18. An event-based neural network architecture with an asynchronous programmable synaptic memory.

    PubMed

    Moradi, Saber; Indiveri, Giacomo

    2014-02-01

    We present a hybrid analog/digital very large scale integration (VLSI) implementation of a spiking neural network with programmable synaptic weights. The synaptic weight values are stored in an asynchronous Static Random Access Memory (SRAM) module, which is interfaced to a fast current-mode event-driven DAC for producing synaptic currents with the appropriate amplitude values. These currents are further integrated by current-mode integrator synapses to produce biophysically realistic temporal dynamics. The synapse output currents are then integrated by compact and efficient integrate and fire silicon neuron circuits with spike-frequency adaptation and adjustable refractory period and spike-reset voltage settings. The fabricated chip comprises a total of 32 × 32 SRAM cells, 4 × 32 synapse circuits and 32 × 1 silicon neurons. It acts as a transceiver, receiving asynchronous events in input, performing neural computation with hybrid analog/digital circuits on the input spikes, and eventually producing digital asynchronous events in output. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event Representation (AER). Using this representation it is possible to interface the device to a workstation or a micro-controller and explore the effect of different types of Spike-Timing Dependent Plasticity (STDP) learning algorithms for updating the synaptic weights values in the SRAM module. We present experimental results demonstrating the correct operation of all the circuits present on the chip. PMID:24681923

  19. Towards Terabit Memories

    NASA Astrophysics Data System (ADS)

    Hoefflinger, Bernd

    Memories have been the major yardstick for the continuing validity of Moore's law. In single-transistor-per-Bit dynamic random-access memories (DRAM), the number of bits per chip pretty much gives us the number of transistors. For decades, DRAM's have offered the largest storage capacity per chip. However, DRAM does not scale any longer, both in density and voltage, severely limiting its power efficiency to 10 fJ/b. A differential DRAM would gain four-times in density and eight-times in energy. Static CMOS RAM (SRAM) with its six transistors/cell is gaining in reputation because it scales well in cell size and operating voltage so that its fundamental advantage of speed, non-destructive read-out and low-power standby could lead to just 2.5 electrons/bit in standby and to a dynamic power efficiency of 2aJ/b. With a projected 2020 density of 16 Gb/cm², the SRAM would be as dense as normal DRAM and vastly better in power efficiency, which would mean a major change in the architecture and market scenario for DRAM versus SRAM. Non-volatile Flash memory have seen two quantum jumps in density well beyond the roadmap: Multi-Bit storage per transistor and high-density TSV (through-silicon via) technology. The number of electrons required per Bit on the storage gate has been reduced since their first realization in 1996 by more than an order of magnitude to 400 electrons/Bit in 2010 for a complexity of 32Gbit per chip at the 32 nm node. Chip stacking of eight chips with TSV has produced a 32GByte solid-state drive (SSD). A stack of 32 chips with 2 b/cell at the 16 nm node will reach a density of 2.5 Terabit/cm². Non-volatile memory with a density of 10 × 10 nm²/Bit is the target for widespread development. Phase-change memory (PCM) and resistive memory (RRAM) lead in cell density, and they will reach 20 Gb/cm² in 2D and higher with 3D chip stacking. This is still almost an order-of-magnitude less than Flash. However, their read-out speed is ~10-times faster, with as yet

  20. Optical Shared Memory Computing and Multiple Access Protocols for Photonic Networks

    NASA Astrophysics Data System (ADS)

    Li, Kuang-Yu.

    In this research we investigate potential applications of optics in massively parallel computer systems, especially focusing on design issues in three-dimensional optical data storage and free-space photonic networks. An optical implementation of a shared memory uses a single photorefractive crystal and can realize the set of memory modules in a digital shared memory computer. A complete instruction set consists of R sc EAD, W sc RITE, S sc ELECTIVE E sc RASE, and R sc EFRESH, which can be applied to any memory module independent of (and in parallel with) instructions to the other memory modules. In addition, a memory module can execute a sequence of R sc EAD operations simultaneously with the execution of a W sc RITE operation to accommodate differences in optical recording and readout times common to optical volume storage media. An experimental shared memory system is demonstrated and its projected performance is analyzed. A multiplexing technique is presented to significantly reduce both grating- and beam-degeneracy crosstalk in volume holographic systems, by incorporating space, angle, and wavelength as the multiplexing parameters. In this approach, each hologram, which results from the interference between a single input node and an object array, partially overlaps with the other holograms in its neighborhood. This technique can offer improved interconnection density, optical throughput, signal fidelity, and space-bandwidth product utilization. Design principles and numerical simulation results are presented. A free-space photonic cellular hypercube parallel computer, with emphasis on the design of a collisionless multiple access protocol, is presented. This design incorporates wavelength-, space-, and time-multiplexing to achieve multiple access, wavelength reuse, dense connectivity, collisionless communications, and a simple control mechanism. Analytic models based on semi-Markov processes are employed to analyze this protocol. The performance of the

  1. Effects of erbium doping of indium tin oxide electrode in resistive random access memory

    NASA Astrophysics Data System (ADS)

    Chen, Po-Hsun; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Pan, Chih-Hung; Lin, Chih-Yang; Jin, Fu-Yuan; Chen, Min-Chen; Huang, Hui-Chun; Lo, Ikai; Zheng, Jin-Cheng; Sze, Simon M.

    2016-03-01

    Identical insulators and bottom electrodes were fabricated and capped by an indium tin oxide (ITO) film, either undoped or doped with erbium (Er), as a top electrode. This distinctive top electrode dramatically altered the resistive random access memory (RRAM) characteristics, for example, lowering the operation current and enlarging the memory window. In addition, the RESET voltage increased, whereas the SET voltage remained almost the same. A conduction model of Er-doped ITO is proposed through current-voltage (I-V) measurement and current fitting to explain the resistance switching mechanism of Er-doped ITO RRAM and is confirmed by material analysis and reliability tests.

  2. Multilevel Cell Storage and Resistance Variability in Resistive Random Access Memory

    NASA Astrophysics Data System (ADS)

    Pantelis, D. I.; Karakizis, P. N.; Dragatogiannis, D. A.; Charitidis, C. A.

    2016-06-01

    Multilevel per cell (MLC) storage in resistive random access memory (ReRAM) is attractive in achieving high-density and low-cost memory and will be required in future. In this chapter, MLC storage and resistance variability and reliability of multilevel in ReRAM are discussed. Different MLC operation schemes with their physical mechanisms and a comprehensive analysis of resistance variability have been provided. Various factors that can induce variability and their effect on the resistance margin between the multiple resistance levels are assessed. The reliability characteristics and the impact on MLC storage have also been assessed.

  3. A new laterally conductive bridge random access memory by fully CMOS logic compatible process

    NASA Astrophysics Data System (ADS)

    Hsieh, Min-Che; Chin, Yung-Wen; Lin, Yu-Cheng; Chih, Yu-Der; Tsai, Kan-Hsueh; Tsai, Ming-Jinn; King, Ya-Chin; Lin, Chrong Jung

    2014-01-01

    This paper proposes a novel laterally conductive bridge random access memory (L-CBRAM) module using a fully CMOS logic compatible process. A contact buffer layer between the poly-Si and contact plug enables the lateral Ti-based atomic layer to provide on/off resistance ratio via bipolar operations. The proposed device reached more than 100 pulse cycles with an on/off ratio over 10 and very stable data retention under high temperature operations. These results make this Ti-based L-CBRAM cell a promising solution for advanced embedded multi-time programmable (MTP) memory applications.

  4. Metallurgical evaluation of SRAM II/SRAM A programmer base plates

    SciTech Connect

    Damkroger, B.K.; Maguire, M.C.; Robino, C.V.

    1993-05-01

    Ten MC4073/4369 programmer base plates were analyzed. This component, a programmer base plate for the SRAM II (and later the SRAM A), is specified as a Grade C quality casting made of aluminum Alloy A356, heat treated to the T6 condition. A concern was expressed regarding the choice of an A356 casting for this application, given the complexity and severity of the loading environment. Preliminary tests and analyses suggested that the design was adequate, but noted the uncertainty involved in a number of their underlying assumptions. The uncertainty was compounded by the discovery that the casting used in the original series of mechanical tests failed. In this investigation, several production castings were examined and found to be of a quality superior to that required under current specifications. Their defect content and microstructure were studied and compared with published data to establish a mechanical property data base. The data base was supplemented with a series of X-direction static tests, which characterized the loading environment and measured the overall casting performance. It was found that the mechanical properties of the supplied castings were adequate for the anticipated X-direction loading environment, but the component is not over-designed. The established data base further indicates that a reduction in casting quality to the allowable level could result in failure of the component. Recommendations were made including (1) change the component specification to require higher casting quality in highly stressed areas, (2) supplement the inspection procedures to ensure adequate quality in critical regions, (3) alter the component design to reduce the stress levels in the mounting feet, (4) substitute a modified A356 alloy to improve the mechanical properties and their consistency, and (5) more thoroughly establish a data base for the mechanical property consequences of levels and configurations of casting defects.

  5. Large Capacity of Conscious Access for Incidental Memories in Natural Scenes.

    PubMed

    Kaunitz, Lisandro N; Rowe, Elise G; Tsuchiya, Naotsugu

    2016-09-01

    When searching a crowd, people can detect a target face only by direct fixation and attention. Once the target is found, it is consciously experienced and remembered, but what is the perceptual fate of the fixated nontarget faces? Whereas introspection suggests that one may remember nontargets, previous studies have proposed that almost no memory should be retained. Using a gaze-contingent paradigm, we asked subjects to visually search for a target face within a crowded natural scene and then tested their memory for nontarget faces, as well as their confidence in those memories. Subjects remembered up to seven fixated, nontarget faces with more than 70% accuracy. Memory accuracy was correlated with trial-by-trial confidence ratings, which implies that the memory was consciously maintained and accessed. When the search scene was inverted, no more than three nontarget faces were remembered. These findings imply that incidental memory for faces, such as those recalled by eyewitnesses, is more reliable than is usually assumed. PMID:27507869

  6. Importance of ion energy on SEU in CMOS SRAMs

    SciTech Connect

    Dodd, P.E.; Shaneyfelt, M.R.; Sexton, F.W.; Hash, G.L.; Winokur, P.S.; Musseau, O.; Leray, J.L.

    1998-03-01

    The single-event upset (SEU) responses of 16 Kbit to 1 Mbit SRAMs irradiated with low and high-energy heavy ions are reported. Standard low-energy heavy ion tests appear to be sufficiently conservative for technologies down to 0.5 {micro}m.

  7. SEU sensitive depth in a submicron SRAM technology

    SciTech Connect

    Detcheverry, C.; Bruguier, G.; Palau, J.M.; Gasiot, J.; Ecoffet, R.; Duzellier, S.; Barak, J.; Lifshitz, Y.

    1998-06-01

    This work determines experimentally and by simulation the SEU sensitive depth in a 0.6 {micro}m SRAM technology. A good correlation is obtained between the two studies in the case of heavy ions deposing energy close to the critical energy. Other simulation results complete the first investigation by studying the minimum sensitive depth for ions deposing higher energies (at greater LET).

  8. Simulation of SRAM SEU Sensitivity at Reduced Operating Temperatures

    NASA Technical Reports Server (NTRS)

    Sanathanamurthy, S.; Ramachandran, V.; Alles, M. L.; Reed, R. A.; Massengill, L. W.; Raman, A.; Turowski, M.; Mantooth, A.; Woods, B.; Barlow, M.; Moen, K.; Bellini, M.; Sutton, A.; Cressler, J. D.

    2009-01-01

    A new NanoTCAD-to-Spectre interface is applied to perform mixed-mode SEU simulations of an SRAM cell. Results using newly calibrated TCAD cold temperature substrate mobility models, and BSIM3 compact models extracted explicitly for the cold temperature designs, indicate a 33% reduction in SEU threshold for the range of temperatures simulated.

  9. Design of Unstructured Adaptive (UA) NAS Parallel Benchmark Featuring Irregular, Dynamic Memory Accesses

    NASA Technical Reports Server (NTRS)

    Feng, Hui-Yu; VanderWijngaart, Rob; Biswas, Rupak; Biegel, Bryan (Technical Monitor)

    2001-01-01

    We describe the design of a new method for the measurement of the performance of modern computer systems when solving scientific problems featuring irregular, dynamic memory accesses. The method involves the solution of a stylized heat transfer problem on an unstructured, adaptive grid. A Spectral Element Method (SEM) with an adaptive, nonconforming mesh is selected to discretize the transport equation. The relatively high order of the SEM lowers the fraction of wall clock time spent on inter-processor communication, which eases the load balancing task and allows us to concentrate on the memory accesses. The benchmark is designed to be three-dimensional. Parallelization and load balance issues of a reference implementation will be described in detail in future reports.

  10. Dramatic reduction of read disturb through pulse width control in spin torque random access memory

    NASA Astrophysics Data System (ADS)

    Wang, Zihui; Wang, Xiaobin; Gan, Huadong; Jung, Dongha; Satoh, Kimihiro; Lin, Tsann; Zhou, Yuchen; Zhang, Jing; Huai, Yiming; Chang, Yao-Jen; Wu, Te-ho

    2013-09-01

    Magnetizations dynamic effect in low current read disturb region is studied both experimentally and theoretically. Dramatic read error rate reduction through read pulse width control is theoretically predicted and experimentally observed. The strong dependence of read error rate upon pulse width contrasts conventional energy barrier approach and can only be obtained considering detailed magnetization dynamics at long time thermal magnetization reversal region. Our study provides a design possibility for ultra-fast low current spin torque random access memory.

  11. Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 5, Appendix D

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    The electrical characterization and qualification test results are presented for the RCA MWS 5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. Average input high current, worst case input high current, output low current, and data setup time are some of the results presented.

  12. Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 4, Appendix C

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    The electrical characterization and qualification test results are presented for the RCA MWS5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. Statistical analysis data is supplied along with write pulse width, read cycle time, write cycle time, and chip enable time data.

  13. Immigration, language proficiency, and autobiographical memories: Lifespan distribution and second-language access.

    PubMed

    Esposito, Alena G; Baker-Ward, Lynne

    2016-08-01

    This investigation examined two controversies in the autobiographical literature: how cross-language immigration affects the distribution of autobiographical memories across the lifespan and under what circumstances language-dependent recall is observed. Both Spanish/English bilingual immigrants and English monolingual non-immigrants participated in a cue word study, with the bilingual sample taking part in a within-subject language manipulation. The expected bump in the number of memories from early life was observed for non-immigrants but not immigrants, who reported more memories for events surrounding immigration. Aspects of the methodology addressed possible reasons for past discrepant findings. Language-dependent recall was influenced by second-language proficiency. Results were interpreted as evidence that bilinguals with high second-language proficiency, in contrast to those with lower second-language proficiency, access a single conceptual store through either language. The final multi-level model predicting language-dependent recall, including second-language proficiency, age of immigration, internal language, and cue word language, explained ¾ of the between-person variance and (1)/5 of the within-person variance. We arrive at two conclusions. First, major life transitions influence the distribution of memories. Second, concept representation across multiple languages follows a developmental model. In addition, the results underscore the importance of considering language experience in research involving memory reports. PMID:26274061

  14. Ge2Sb2Te5 Confined Structures and Integration of 64 Mb Phase-Change Random Access Memory

    NASA Astrophysics Data System (ADS)

    Yeung, Fai; Ahn, Su-Jin; Hwang, Young-Nam; Jeong, Chang-Wook; Song, Yoon-Jong; Lee, Su-Youn; Lee, Se-Ho; Ryoo, Kyung-Chang; Park, Jae-Hyun; Shin, Jae-Min; Jeong, Won-Cheol; Kim, Young-Tae; Koh, Gwan-Hyeob; Jeong, Gi-Tae; Jeong, Hong-Sik; Kim, Kinam

    2005-04-01

    Phase-change random access memory is considered a potential challenger for conventional memories, such as dynamic random access memory and flash memory due to its numerous advantages. Nevertheless, high reset current is the ultimate problem in developing high-density phase-change random access memory (PRAM). We focus on the adoption of Ge2Sb2Te5 confined structures to achieve lower reset currents. By changing from a normal to a GST confined structure, the reset current drops to as low as 0.8 mA. Eventually, our integrated 64 Mb PRAM based on 0.18 μm CMOS technology offers a large sensing margin: Rreset ˜200 kΩ and Rset ˜2 kΩ, as well as reasonable reliability: an endurance of 1.0× 109 cycles and a retention time of 2 years at 85°C.

  15. Ultralow-power ferroelectric memory for SoC

    NASA Astrophysics Data System (ADS)

    Natarajan, Sreedhar; Alvandpour, Atila

    2004-03-01

    The endurance of a FRAM is 1014 cycles with better retention times (>10 years). FRAM's have fast read/write access, low standby current, scalable and capable of ultra-low voltage operation. FRAM's share architectural features such as addressing schemes and I/O circuitry with other types of random access memories (DRAMs), but they have distinct features with respect to accessing the stored data, sensing, and overall circuit topology. The FRAM is a great advantage for SoC and wireless and mobile products, since it supports non-volatility but also delivers a fast memory access. Today's 1T/1C FRAM have an access time of 30 nS, a cycle time of 35 nS at 1.2 V power supply in a standard CMOS process with 2 mask adders. The cell size of a FRAM is comparable to that of a planar DRAM and is 3 - 4x denser than SRAM. This paper outlines the circuit innovations in embedded ferroelectric memories, and will cover the architecture, reference circuits, sense amplifiers, reliability issues and references to other memory technologies.

  16. Comprehension of Linguistic Dependencies: Speed-Accuracy Tradeoff Evidence for Direct-Access Retrieval From Memory

    PubMed Central

    Foraker, Stephani; McElree, Brian

    2012-01-01

    Comprehenders can rapidly and efficiently interpret expressions with various types of non-adjacent dependencies. In the sentence The boy that the teacher warned fell, boy is readily interpreted as the subject of the verb fall despite the fact that a relative clause, that the teacher warned, intervenes between the two dependent elements. We review research investigating three memory operations proposed for resolving this and other types of non-adjacent dependencies: serial search retrieval, in which the dependent constituent is recovered by a search process through representations in memory, direct-access retrieval in which the dependent constituent is recovered directly by retrieval cue operations without search, and active maintenance of the dependent constituent in focal attention. Studies using speed-accuracy tradeoff methodology to examine the full timecourse of interpreting a wide range of non-adjacent dependencies indicate that comprehenders retrieve dependent constituents with a direct-access operation, consistent with the claim that representations formed during comprehension are accessed with a cue-driven, content-addressable retrieval process. The observed timecourse profiles are inconsistent with a broad class of models based on several search operations for retrieval. The profiles are also inconsistent with active maintenance of a constituent while concurrently processing subsequent material, and suggest that, with few exceptions, direct-access retrieval is required to process non-adjacent dependencies. PMID:22448181

  17. Daily Access to Sucrose Impairs Aspects of Spatial Memory Tasks Reliant on Pattern Separation and Neural Proliferation in Rats

    ERIC Educational Resources Information Center

    Reichelt, Amy C.; Morris, Margaret J.; Westbrook, Reginald Frederick

    2016-01-01

    High sugar diets reduce hippocampal neurogenesis, which is required for minimizing interference between memories, a process that involves "pattern separation." We provided rats with 2 h daily access to a sucrose solution for 28 d and assessed their performance on a spatial memory task. Sucrose consuming rats discriminated between objects…

  18. Encoding and Retrieval Processes Involved in the Access of Source Information in the Absence of Item Memory

    ERIC Educational Resources Information Center

    Ball, B. Hunter; DeWitt, Michael R.; Knight, Justin B.; Hicks, Jason L.

    2014-01-01

    The current study sought to examine the relative contributions of encoding and retrieval processes in accessing contextual information in the absence of item memory using an extralist cuing procedure in which the retrieval cues used to query memory for contextual information were "related" to the target item but never actually studied.…

  19. Interleaved synchronous bus access protocol for a shared memory multi-processor system

    SciTech Connect

    Moore, W.T.

    1989-01-10

    A method is described for providing asynchronous processors with inter-processor communication and access to several memory modules over a common bus which includes a first bus and a second bus, comprising: providing clock pulses on the common bus, each pulse having a period; asserting a request signal and placing priority signal on the common bus; polling the processors during the first period to determine whether the processors request access to the common bus and to determine which one processor has priority; sending a destination address from the one processor to a destination during a second period, the destination being chosen from the processors and the several memory modules; performing one of reading input data between the destination and the processor; multiplexing priority and reading input data signals on the first bus, and multiplexing address and writing output data signals on the second bus; generating poll inhibit signals prior to each reading input data signal and prior to each memory address signal preceding a writing output data operation; and queuing the input data in a first-in-first-out manner for each of the processors when the input data indicates an interprocessor interrupt.

  20. Low-power resistive random access memory by confining the formation of conducting filaments

    NASA Astrophysics Data System (ADS)

    Huang, Yi-Jen; Shen, Tzu-Hsien; Lee, Lan-Hsuan; Wen, Cheng-Yen; Lee, Si-Chen

    2016-06-01

    Owing to their small physical size and low power consumption, resistive random access memory (RRAM) devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiOx/silver nanoparticles/TiOx/AlTiOx, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V), low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistance state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiOx layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.

  1. Single event upset in irradiated 16k CMOS SRAMs

    SciTech Connect

    Axness, C.L.; Schwank, J.R.; Winokur, P.S.; Browning, J.S.; Fleetwood, D.M.; Koga, R.

    1988-12-01

    The Single Event Upset (SEU) characteristics of a CMOS SRAM cell irradiated under conditions that simulate the total-dose degradation anticipated in space applications are experimentally and theoretically investigated. Simulations of SEU sensitivity utilizing a 2D circuit/device simulator, with measured transistor threshold-voltage shifts and mobility degradations as inputs, are shown to be in good agreement with experimental data at high total dose. Both simulation and experiment show a strong SRAM cell SEU imbalance, resulting in a more SEU tolerant preferred state and a less tolerant non-preferred state. The resulting cell imbalance causes an overall degradation in SEU immunity which increases with increasing total dose and which should be taken into account in SEU testing and part characterization.

  2. High-density magnetoresistive random access memory operating at ultralow voltage at room temperature

    PubMed Central

    Hu, Jia-Mian; Li, Zheng; Chen, Long-Qing; Nan, Ce-Wen

    2011-01-01

    The main bottlenecks limiting the practical applications of current magnetoresistive random access memory (MRAM) technology are its low storage density and high writing energy consumption. Although a number of proposals have been reported for voltage-controlled memory device in recent years, none of them simultaneously satisfy the important device attributes: high storage capacity, low power consumption and room temperature operation. Here we present, using phase-field simulations, a simple and new pathway towards high-performance MRAMs that display significant improvements over existing MRAM technologies or proposed concepts. The proposed nanoscale MRAM device simultaneously exhibits ultrahigh storage capacity of up to 88 Gb inch−2, ultralow power dissipation as low as 0.16 fJ per bit and room temperature high-speed operation below 10 ns. PMID:22109527

  3. Extremely small test cell structure for resistive random access memory element with removable bottom electrode

    SciTech Connect

    Koh, Sang-Gyu; Kishida, Satoru; Kinoshita, Kentaro

    2014-02-24

    We established a method of preparing an extremely small memory cell by fabricating a resistive random access memory (ReRAM) structure on the tip of a cantilever of an atomic force microscope. This structure has the high robustness against the drift of the cantilever, and the effective cell size was estimated to be less than 10 nm in diameter due to the electric field concentration at the tip of the cantilever, which was confirmed using electric field simulation. The proposed structure, which has a removable bottom electrode, enables not only the preparation of a tiny ReRAM structure but also the performance of unique experiments, by making the most of its high robustness against the drift of the cantilever.

  4. Bipolar resistive switching characteristics in tantalum nitride-based resistive random access memory devices

    SciTech Connect

    Kim, Myung Ju; Jeon, Dong Su; Park, Ju Hyun; Kim, Tae Geun

    2015-05-18

    This paper reports the bipolar resistive switching characteristics of TaN{sub x}-based resistive random access memory (ReRAM). The conduction mechanism is explained by formation and rupture of conductive filaments caused by migration of nitrogen ions and vacancies; this mechanism is in good agreement with either Ohmic conduction or the Poole-Frenkel emission model. The devices exhibit that the reset voltage varies from −0.82 V to −0.62 V, whereas the set voltage ranges from 1.01 V to 1.30 V for 120 DC sweep cycles. In terms of reliability, the devices exhibit good retention (>10{sup 5 }s) and pulse-switching endurance (>10{sup 6} cycles) properties. These results indicate that TaN{sub x}-based ReRAM devices have a potential for future nonvolatile memory devices.

  5. Self-assembled tin dioxide for forming-free resistive random-access memory application

    NASA Astrophysics Data System (ADS)

    Hong, Ying-Jhan; Wang, Tsang-Hsuan; Wei, Shih-Yuan; Chang, Pin; Yew, Tri-Rung

    2016-06-01

    A novel resistive switching structure, tin-doped indium oxide (ITO)/SnO2‑ x (defined as SnO2 with oxygen vacancies)/SnS was demonstrated with a set voltage of 0.38 V, a reset voltage of ‑0.15 V, a ratio of high resistance to low resistance of 544, and forming-free and nonlinear current–voltage (I–V) characteristics. The interface of the ITO and the self-assembled SnO2‑ x contributed to the resistive switching behavior. This device showed great potential for resistive random access memory (RRAM) application and solving the sneak path problem in cross-bar memory arrays. Furthermore, a nanostructured resistive switching device was demonstrated successfully.

  6. The effect of ultraviolet irradiation on data retention characteristics of resistive random access memory

    NASA Astrophysics Data System (ADS)

    Kinoshita, Kentaro; Kimura, Kouhei; Ohmi, Koutoku; Kishida, Satoru

    It is getting more and more serious to generate soft-errors by cosmic radiation, with increasing the density of memory devices. Therefore, the irradiation resistance of resistance random access memory (ReRAM) to cosmic radiation has to be elucidated for practical use. In this paper, we investigated the data retention characteristics against ultraviolet irradiation to ReRAM with Pt/NiO/ITO structure. Soft-errors were confirmed to be caused by ultraviolet irradiation in both low and high resistance states. The analysis of irradiation frequency dependence of data retention characteristics suggested that electronic excitation by the irradiation caused the errors. Based on a statistically estimated soft-error rate, the errors were suggested to be caused by aggregation and dispersion of oxygen vacancies due to the generation of electron-hole pairs and valence change by the ultraviolet irradiation.

  7. Gate controllable resistive random access memory devices using reduced graphene oxide

    NASA Astrophysics Data System (ADS)

    Hazra, Preetam; Resmi, A. N.; Jinesh, K. B.

    2016-04-01

    The biggest challenge in the resistive random access memory (ReRAM) technology is that the basic operational parameters, such as the set and reset voltages, the current on-off ratios (hence the power), and their operational speeds, strongly depend on the active and electrode materials and their processing methods. Therefore, for its actual technological implementations, the unification of the operational parameters of the ReRAM devices appears to be a difficult task. In this letter, we show that by fabricating a resistive memory device in a thin film transistor configuration and thus applying an external gate bias, we can control the switching voltage very accurately. Taking partially reduced graphene oxide, the gate controllable switching is demonstrated, and the possible mechanisms are discussed.

  8. Hydrogen induced redox mechanism in amorphous carbon resistive random access memory

    PubMed Central

    2014-01-01

    We investigated the bipolar resistive switching characteristics of the resistive random access memory (RRAM) device with amorphous carbon layer. Applying a forming voltage, the amorphous carbon layer was carbonized to form a conjugation double bond conductive filament. We proposed a hydrogen redox model to clarify the resistive switch mechanism of high/low resistance states (HRS/LRS) in carbon RRAM. The electrical conduction mechanism of LRS is attributed to conductive sp2 carbon filament with conjugation double bonds by dehydrogenation, while the electrical conduction of HRS resulted from the formation of insulating sp3-type carbon filament through hydrogenation process. PMID:24475979

  9. A stochastic simulation method for the assessment of resistive random access memory retention reliability

    SciTech Connect

    Berco, Dan Tseng, Tseung-Yuen

    2015-12-21

    This study presents an evaluation method for resistive random access memory retention reliability based on the Metropolis Monte Carlo algorithm and Gibbs free energy. The method, which does not rely on a time evolution, provides an extremely efficient way to compare the relative retention properties of metal-insulator-metal structures. It requires a small number of iterations and may be used for statistical analysis. The presented approach is used to compare the relative robustness of a single layer ZrO{sub 2} device with a double layer ZnO/ZrO{sub 2} one, and obtain results which are in good agreement with experimental data.

  10. One electron-controlled multiple-valued dynamic random-access-memory

    NASA Astrophysics Data System (ADS)

    Kye, H. W.; Song, B. N.; Lee, S. E.; Kim, J. S.; Shin, S. J.; Choi, J. B.; Yu, Y.-S.; Takahashi, Y.

    2016-02-01

    We propose a new architecture for a dynamic random-access-memory (DRAM) capable of storing multiple values by using a single-electron transistor (SET). The gate of a SET is designed to be connected to a plurality of DRAM unit cells that are arrayed at intersections of word lines and bitlines. In this SET-DRAM hybrid scheme, the multiple switching characteristics of SET enables multiple value data stored in a DRAM unit cell, and this increases the storage functionality of the device. Moreover, since refreshing data requires only a small amount of SET driving current, this enables device operating with low standby power consumption.

  11. Conductive Filament Expansion in TaOx Bipolar Resistive Random Access Memory during Pulse Cycling

    NASA Astrophysics Data System (ADS)

    Ninomiya, Takeki; Katayama, Koji; Muraoka, Shunsaku; Yasuhara, Ryutaro; Mikawa, Takumi; Wei, Zhiqiang

    2013-11-01

    The post-cycling data retention of filamentary operated resistive random access memory (ReRAM) can be improved by minimizing conductive filament expansion during pulse cycling. We find that filament size gradually grows with increasing pulse cycles due to oxygen diffusion from the region surrounding each filament. To achieve long term use of ReRAM while suppressing filament expansion, the key is to control both electric power and pulse width input during switching. We minimize CF expansion based on this concept and demonstrate long data retention even after 106 pulse switchings under optimized reset conditions.

  12. Spin-transfer-torque efficiency enhanced by edge-damage of perpendicular magnetic random access memories

    SciTech Connect

    Song, Kyungmi; Lee, Kyung-Jin

    2015-08-07

    We numerically investigate the effect of magnetic and electrical damages at the edge of a perpendicular magnetic random access memory (MRAM) cell on the spin-transfer-torque (STT) efficiency that is defined by the ratio of thermal stability factor to switching current. We find that the switching mode of an edge-damaged cell is different from that of an undamaged cell, which results in a sizable reduction in the switching current. Together with a marginal reduction of the thermal stability factor of an edge-damaged cell, this feature makes the STT efficiency large. Our results suggest that a precise edge control is viable for the optimization of STT-MRAM.

  13. Complementary resistive switching behavior induced by varying forming current compliance in resistance random access memory

    NASA Astrophysics Data System (ADS)

    Tseng, Yi-Ting; Tsai, Tsung-Ming; Chang, Ting-Chang; Shih, Chih-Cheng; Chang, Kuan-Chang; Zhang, Rui; Chen, Kai-Huang; Chen, Jung-Hui; Li, Yu-Chiuan; Lin, Chih-Yang; Hung, Ya-Chi; Syu, Yong-En; Zheng, Jin-Cheng; Sze, Simon M.

    2015-05-01

    In this study of resistance random access memory in a resistive switching film, the breakdown degree was controlled by varying forming current compliance. A SiOx layer was introduced into the ZnO layer of the structure to induce both typical bipolar resistive switching (RS) and complementary resistive switching (CRS). In addition, the SiOx layer-generated vacuum spaces in typical bipolar RS can be verified by electrical characteristics. Changing forming current compliance strikingly modifies the oxygen storage capacity of the inserted SiOx layer. CRS can be achieved, therefore, by tuning the oxygen ion storage behavior made possible by the SiOx layer.

  14. Microstructural Characterization in Reliability Measurement of Phase Change Random Access Memory

    NASA Astrophysics Data System (ADS)

    Bae, Junsoo; Hwang, Kyuman; Park, Kwangho; Jeon, Seongbu; Kang, Dae-hwan; Park, Soonoh; Ahn, Juhyeon; Kim, Seoksik; Jeong, Gitae; Chung, Chilhee

    2011-04-01

    The cell failures after cycling endurance in phase-change random access memory (PRAM) have been classified into three groups, which have been analyzed by transmission electron microscopy (TEM). Both stuck reset of the set state (D0) and stuck set of the reset state (D1) are due to a void created inside GeSbTe (GST) film or thereby lowering density of GST film. The decrease of the both set and reset resistances that leads to the tails from the reset distribution are induced from the Sb increase with cycles.

  15. Optical and electronic error correction schemes for highly parallel access memories

    NASA Astrophysics Data System (ADS)

    Neifeld, Mark A.; Hayes, Jerry D.

    1993-11-01

    We have fabricated and tested an optically addressed, parallel electronic Reed-Solomon decoder for use with parallel access optical memories. A comparison with various serial implementations has demonstrated that for many instances of code block size and error correction capability, the parallel approach is superior from the perspectives of VLSI layout area and decoding latency. The demonstrated Reed-Solomon parallel pipeline decoder operates on 60 bit input words and has been demonstrated at a clock rate of 5 MHz yielding a demonstrated data rate of 300 Mbps.

  16. Random access memory immune to single event upset using a T-resistor

    DOEpatents

    Ochoa, Jr., Agustin

    1989-01-01

    In a random access memory cell, a resistance "T" decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell.

  17. A random access memory immune to single event upset using a T-Resistor

    DOEpatents

    Ochoa, A. Jr.

    1987-10-28

    In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

  18. Analysis and modeling of resistive switching mechanisms oriented to resistive random-access memory

    NASA Astrophysics Data System (ADS)

    Huang, Da; Wu, Jun-Jie; Tang, Yu-Hua

    2013-03-01

    With the progress of the semiconductor industry, the resistive random-access memory (RAM) has drawn increasing attention. The discovery of the memristor has brought much attention to this study. Research has focused on the resistive switching characteristics of different materials and the analysis of resistive switching mechanisms. We discuss the resistive switching mechanisms of different materials in this paper and analyze the differences of those mechanisms from the view point of circuitry to establish their respective circuit models. Finally, simulations are presented. We give the prospect of using different materials in resistive RAM on account of their resistive switching mechanisms, which are applied to explain their resistive switchings.

  19. Hydrogen doping in HfO2 resistance change random access memory

    NASA Astrophysics Data System (ADS)

    Duncan, D.; Magyari-Köpe, B.; Nishi, Y.

    2016-01-01

    The structures and energies of hydrogen-doped monoclinic hafnium dioxide were calculated using density-functional theory. The electronic interactions are described within the LDA + U formalism, where on-site Coulomb corrections are applied to the 5d orbital electrons of Hf atoms and 2p orbital electrons of the O atoms. The effects of charge state, defect-defect interactions, and hydrogenation are investigated and compared with experiment. It is found that hydrogenation of HfO2 resistance-change random access memory devices energetically stabilizes the formation of oxygen vacancies and conductive vacancy filaments through multiple mechanisms, leading to improved switching characteristic and device yield.

  20. A stochastic simulation method for the assessment of resistive random access memory retention reliability

    NASA Astrophysics Data System (ADS)

    Berco, Dan; Tseng, Tseung-Yuen

    2015-12-01

    This study presents an evaluation method for resistive random access memory retention reliability based on the Metropolis Monte Carlo algorithm and Gibbs free energy. The method, which does not rely on a time evolution, provides an extremely efficient way to compare the relative retention properties of metal-insulator-metal structures. It requires a small number of iterations and may be used for statistical analysis. The presented approach is used to compare the relative robustness of a single layer ZrO2 device with a double layer ZnO/ZrO2 one, and obtain results which are in good agreement with experimental data.

  1. TiO2 thin film based transparent flexible resistive switching random access memory

    NASA Astrophysics Data System (ADS)

    Pham, Kim Ngoc; Dung Hoang, Van; Tran, Cao Vinh; Thang Phan, Bach

    2016-03-01

    In our work we have fabricated TiO2 based resistive switching devices both on transparent substrates (ITO, IGZO/glass) and transparent flexible substrate (ITO/PET). All devices demonstrate the reproducibility of forming free bipolar resistive switching with high transparency in the visible light range (∼80% at the wavelength of 550 nm). Particularly, transparent and flexible device exhibits stable resistive switching performance at the initial state (flat) and even after bending state up to 500 times with curvature radius of 10% compared to flat state. The achieved characteristics of resistive switching of TiO2 thin films seem to be promising for transparent flexible random access memory.

  2. Positive alcohol expectancies and drinking behavior: the influence of expectancy strength and memory accessibility.

    PubMed

    Palfai, T; Wood, M D

    2001-03-01

    College student drinkers (N = 314) participated in a health survey in which they (a) completed an alcohol-related memory association task (expectancy accessibility measure), (b) rated their positive expectancies about alcohol use (expectancy strength measure), and (c) reported their level of alcohol involvement. Hierarchical regression analyses showed that both expectancy accessibility and expectancy strength predicted frequency of alcohol use and alcohol-related problems. Moreover, moderational analyses showed that the association between expectancy strength and frequency of alcohol use was greater for those who generated more alcohol responses on the expectancy association task. These findings suggest that the outcome association measure and Likert scale ratings of expectancies may assess distinct properties of expectancy representations, which may have independent and interactive effects on different aspects of drinking behavior. PMID:11255940

  3. Analyzing the Energy and Power Consumption of Remote Memory Accesses in the OpenSHMEM Model

    SciTech Connect

    Jana, Siddhartha; Hernandez, Oscar R; Poole, Stephen W; Hsu, Chung-Hsing; Chapman, Barbara

    2014-01-01

    PGAS models like OpenSHMEM provide interfaces to explicitly initiate one-sided remote memory accesses among processes. In addition, the model also provides synchronizing barriers to ensure a consistent view of the distributed memory at different phases of an application. The incorrect use of such interfaces affects the scalability achievable while using a parallel programming model. This study aims at understanding the effects of these constructs on the energy and power consumption behavior of OpenSHMEM applications. Our experiments show that cost incurred in terms of the total energy and power consumed depends on multiple factors across the software and hardware stack. We conclude that there is a significant impact on the power consumed by the CPU and DRAM due to multiple factors including the design of the data transfer patterns within an application, the design of the communication protocols within a middleware, the architectural constraints laid by the interconnect solutions, and also the levels of memory hierarchy within a compute node. This work motivates treating energy and power consumption as important factors while designing compute solutions for current and future distributed systems.

  4. Temperature dependence of resistive switching behaviors in resistive random access memory based on graphene oxide film

    NASA Astrophysics Data System (ADS)

    Yi, Mingdong; Cao, Yong; Ling, Haifeng; Du, Zhuzhu; Wang, Laiyuan; Yang, Tao; Fan, Quli; Xie, Linghai; Huang, Wei

    2014-05-01

    We reported resistive switching behaviors in the resistive random access memory (RRAM) devices based on the different annealing temperatures of graphene oxide (GO) film as active layers. It was found that the resistive switching characteristics of an indium tin oxide (ITO)/GO/Ag structure have a strong dependence on the annealing temperature of GO film. When the annealing temperature of the GO film was 20 °C, the devices showed typical write-once-read-many-times (WORM) type memory behaviors, which have good memory performance with a higher ON/OFF current ratio (˜104), the higher the high resistance state (HRS)/low resistance state (LRS) ratio (˜105) and stable retention characteristics (>103 s) under lower programming voltage (-1 V and -0.5 V). With the increasing annealing temperature of GO film, the resistive switching behavior of RRAM devices gradually weakened and eventually disappeared. This phenomenon could be understood by the different energy level distributions of the charge traps in GO film, and the different charge injection ability from the Ag electrode to GO film, which is caused by the different annealing temperatures of the GO film.

  5. Temperature dependence of resistive switching behaviors in resistive random access memory based on graphene oxide film.

    PubMed

    Yi, Mingdong; Cao, Yong; Ling, Haifeng; Du, Zhuzhu; Wang, Laiyuan; Yang, Tao; Fan, Quli; Xie, Linghai; Huang, Wei

    2014-05-01

    We reported resistive switching behaviors in the resistive random access memory (RRAM) devices based on the different annealing temperatures of graphene oxide (GO) film as active layers. It was found that the resistive switching characteristics of an indium tin oxide (ITO)/GO/Ag structure have a strong dependence on the annealing temperature of GO film. When the annealing temperature of the GO film was 20 °C, the devices showed typical write-once-read-many-times (WORM) type memory behaviors, which have good memory performance with a higher ON/OFF current ratio (∼10(4)), the higher the high resistance state (HRS)/low resistance state (LRS) ratio (∼10(5)) and stable retention characteristics (>10(3) s) under lower programming voltage (-1 V and -0.5 V). With the increasing annealing temperature of GO film, the resistive switching behavior of RRAM devices gradually weakened and eventually disappeared. This phenomenon could be understood by the different energy level distributions of the charge traps in GO film, and the different charge injection ability from the Ag electrode to GO film, which is caused by the different annealing temperatures of the GO film. PMID:24739543

  6. Low power switching of Si-doped Ta2O5 resistive random access memory for high density memory application

    NASA Astrophysics Data System (ADS)

    Kim, Beom Yong; Jeung Lee, Kee; Ock Chung, Su; Gil Kim, Soo; Ko, Young Seok; Kim, Hyeong Soo

    2016-04-01

    We report, for the first time, the resistive switching properties of Si-doped Ta2O5 grown by atomic layer deposition (ALD). The reduced switching current, improved on/off current ratio, and excellent endurance property are demonstrated in the Si-doped Ta2O5 resistive random access memory (ReRAM) devices of 50 nm tech node. The switching mechanism for the Si-doped Ta2O5 resistor is discussed. Si dopants enable switching layer to have conformal distribution of oxygen vacancy and easily form conductive filament. This leads to higher on/off current ratio at even low operation current of 5-10 µA. Finally, one selector-one resistor (1S1R) ReRAM was developed for large cell array application. For the optimized 1S1R stack, 0.2 µA of off current and 5.0 of on/off current ratio were successfully achieved at 10 µA of low operation current.

  7. Daily access to sucrose impairs aspects of spatial memory tasks reliant on pattern separation and neural proliferation in rats.

    PubMed

    Reichelt, Amy C; Morris, Margaret J; Westbrook, Reginald Frederick

    2016-07-01

    High sugar diets reduce hippocampal neurogenesis, which is required for minimizing interference between memories, a process that involves "pattern separation." We provided rats with 2 h daily access to a sucrose solution for 28 d and assessed their performance on a spatial memory task. Sucrose consuming rats discriminated between objects in novel and familiar locations when there was a large spatial separation between the objects, but not when the separation was smaller. Neuroproliferation markers in the dentate gyrus of the sucrose-consuming rats were reduced relative to controls. Thus, sucrose consumption impaired aspects of spatial memory and reduced hippocampal neuroproliferation. PMID:27317199

  8. Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operation

    NASA Astrophysics Data System (ADS)

    Huh, In; Cheon, Woo Young; Choi, Woo Young

    2016-04-01

    A subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory (SAT RAM) has been proposed and fabricated for low-power nonvolatile memory applications. The proposed SAT RAM cell demonstrates adjustable subthreshold swing (SS) depending on stored information: small SS in the erase state ("1" state) and large SS in the program state ("0" state). Thus, SAT RAM cells can achieve low read voltage (Vread) with a large memory window in addition to the effective suppression of ambipolar behavior. These unique features of the SAT RAM are originated from the locally stored charge, which modulates the tunneling barrier width (Wtun) of the source-to-channel tunneling junction.

  9. Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors

    SciTech Connect

    Yang, Jyun-Bao; Chen, Yu-Ting; Chu, Ann-Kuo; Chang, Ting-Chang; Huang, Jheng-Jie; Chen, Yu-Chun; Tseng, Hsueh-Chih; Sze, Simon M.

    2014-04-14

    In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

  10. Temporal analysis of SEU in SOI/GAA SRAMs

    SciTech Connect

    Francis, P.; Colinge, J.P.; Berger, G.

    1995-12-01

    This paper analyzes the very strong SEU hardness of a 1k static random-access memory fabricated using the SOI/GAA technology, irradiated with a xenon ion beam at various angles of incidence. The memory has been shown to operate with a supply voltage as low as 2V while still presenting excellent SEU hardness. Since the different physical charge collection mechanisms are particularly slow in SOI devices, it is shown that collected and critical charges must be dynamically compared in order to determine the SEU threshold. A new approach is then proposed to evaluate the time-variable critical charge independently of the pulse shape generated by the incident ion, and a general analytical model is derived. Finally, predictions in good agreement with experimental data are obtained.

  11. Low-energy Resistive Random Access Memory Devices with No Need for a Compliance Current

    PubMed Central

    Xu, Zedong; Yu, Lina; Wu, Yong; Dong, Chang; Deng, Ning; Xu, Xiaoguang; Miao, J.; Jiang, Yong

    2015-01-01

    A novel resistive random access memory device is designed with SrTiO3/ La2/3Sr1/3MnO3 (LSMO)/MgAl2O4 (MAO)/Cu structure, in which metallic epitaxial LSMO is employed as the bottom electrode rather than traditional metal materials. In this device, the critical external compliance current is no longer necessary due to the high self-resistance of LSMO. The LMSO bottom electrode can act as a series resistor to offer a compliance current during the set process. Besides, the device also has excellent switching features which are originated in the formation of Cu filaments under external voltage. Therefore it provides the possibility of reducing power consumption and accelerating the commercialization of resistive switching devices. PMID:25982101

  12. Low-energy Resistive Random Access Memory Devices with No Need for a Compliance Current

    NASA Astrophysics Data System (ADS)

    Xu, Zedong; Yu, Lina; Wu, Yong; Dong, Chang; Deng, Ning; Xu, Xiaoguang; Miao, J.; Jiang, Yong

    2015-05-01

    A novel resistive random access memory device is designed with SrTiO3/ La2/3Sr1/3MnO3 (LSMO)/MgAl2O4 (MAO)/Cu structure, in which metallic epitaxial LSMO is employed as the bottom electrode rather than traditional metal materials. In this device, the critical external compliance current is no longer necessary due to the high self-resistance of LSMO. The LMSO bottom electrode can act as a series resistor to offer a compliance current during the set process. Besides, the device also has excellent switching features which are originated in the formation of Cu filaments under external voltage. Therefore it provides the possibility of reducing power consumption and accelerating the commercialization of resistive switching devices.

  13. Joule heating effect in nonpolar and bipolar resistive random access memory

    NASA Astrophysics Data System (ADS)

    Uenuma, Mutsunori; Ishikawa, Yasuaki; Uraoka, Yukiharu

    2015-08-01

    The position of the conductive filament (CF) and the heating behaviour during a switching process in nonpolar and bipolar resistive random access memories (ReRAMs) were evaluated using thermal analysis. The position of the CF was clearly observed from Joule heating at the surface of the electrode on the CF. The position of the CF did not change during the switching cycle, except in the case of an unstable CF. In the nonpolar ReRAM, spike-shaped temperature increments were observed during both the forming and the set processes because of the overshoot current. However, the behaviour of the temperature increment in the bipolar ReRAM was virtually consistent with the profile of the electrical power.

  14. Simulation study on heat conduction of a nanoscale phase-change random access memory cell.

    PubMed

    Kim, Junho; Song, Ki-Bong

    2006-11-01

    We have investigated heat transfer characteristics of a nano-scale phase-change random access memory (PRAM) cell using finite element method (FEM) simulation. Our PRAM cell is based on ternary chalcogenide alloy, Ge2Sb2Te5 (GST), which is used as a recording layer. For contact area of 100 x 100 nm2, simulations of crystallization and amorphization processes were carried out. Physical quantities such as electric conductivity, thermal conductivity, and specific heat were treated as temperature-dependent parameters. Through many simulations, it is concluded that one can reduce set current by decreasing both electric conductivities of amorphous GST and crystalline GST, and in addition to these conditions by decreasing electric conductivity of molten GST one can also reduce reset current significantly. PMID:17252792

  15. Characteristics and mechanism study of cerium oxide based random access memories

    SciTech Connect

    Hsieh, Cheng-Chih; Roy, Anupam; Rai, Amritesh; Chang, Yao-Feng; Banerjee, Sanjay K.

    2015-04-27

    In this work, low operating voltage and high resistance ratio of different resistance states of binary transition metal oxide based resistive random access memories (RRAMs) are demonstrated. Binary transition metal oxides with high dielectric constant have been explored for RRAM application for years. However, CeO{sub x} is considered as a relatively new material to other dielectrics. Since research on CeO{sub x} based RRAM is still at preliminary stage, fundamental characteristics of RRAM such as scalability and mechanism studies need to be done before moving further. Here, we show very high operation window and low switching voltage of CeO{sub x} RRAMs and also compare electrical performance of Al/CeO{sub x}/Au system between different thin film deposition methods and discuss characteristics and resistive switching mechanism.

  16. Novel Capacitor Structure Using Sidewall Spacer for Highly Reliable Ferroelectric Random Access Memory Device

    NASA Astrophysics Data System (ADS)

    Kim, Hyun-Ho; Park, Jung-Hoon; Song, Yoon-Jong; Jang, Nak-Won; Joo, Heung-Jin; Kang, Seung-Kuk; Joo, Seok-Ho; Lee, Sung-Young; Kim, Kinam

    2004-04-01

    Since ferroelectric capacitors prepared by 1-mask etching are degraded after the etching, we systematically investigated the origin of the degradation. It was found that the major degradation originates from the formation of the nonstoichiometric and amorphorized Pb(ZrxTi1-x)O3 (PZT) layer on the sidewall of the PZT film during etching of the bottom electrode (BE). Therefore, to eliminate the undesired etch-damaged layer, we developed a novel etching technology using a ferroelectric (FE) sidewall spacer, which results in the enhancement of the remnant polarization after completing the capacitor etching process. Using the novel FE sidewall spacer, the sensing margin of bit-line-developed voltage was improved to 400 mV, which can guarantee highy reliable high-density ferroelectric random access memory (FRAM) devices.

  17. Electrical Characterization of the RCA CDP1822SD Random Access Memory, Volume 1, Appendix a

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    Electrical characteristization tests were performed on 35 RCA CDP1822SD, 256-by-4-bit, CMOS, random access memories. The tests included three functional tests, AC and DC parametric tests, a series of schmoo plots, rise/fall time screening, and a data retention test. All tests were performed on an automated IC test system with temperatures controlled by a thermal airstream unit. All the functional tests, the data retention test, and the AC and DC parametric tests were performed at ambient temperatures of 25 C, -20 C, -55 C, 85 C, and 125 C. The schmoo plots were performed at ambient temperatures of 25 C, -55 C, and 125 C. The data retention test was performed at 25 C. Five devices failed one or more functional tests and four of these devices failed to meet the expected limits of a number of AC parametric tests. Some of the schmoo plots indicated a small degree of interaction between parameters.

  18. Voltage induced magnetostrictive switching of nanomagnets: Strain assisted strain transfer torque random access memory

    NASA Astrophysics Data System (ADS)

    Khan, Asif; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Ghani, Tahir; Young, Ian A.

    2014-06-01

    A spintronic device, called the "strain assisted spin transfer torque (STT) random access memory (RAM)," is proposed by combining the magnetostriction effect and the spin transfer torque effect which can result in a dramatic improvement in the energy dissipation relative to a conventional STT-RAM. Magnetization switching in the device which is a piezoelectric-ferromagnetic heterostructure via the combined magnetostriction and STT effect is simulated by solving the Landau-Lifshitz-Gilbert equation incorporating the influence of thermal noise. The simulations show that, in such a device, each of these two mechanisms (magnetostriction and spin transfer torque) provides in a 90° rotation of the magnetization leading a deterministic 180° switching with a critical current significantly smaller than that required for spin torque alone. Such a scheme is an attractive option for writing magnetic RAM cells.

  19. Microstructural transitions in resistive random access memory composed of molybdenum oxide with copper during switching cycles.

    PubMed

    Arita, Masashi; Ohno, Yuuki; Murakami, Yosuke; Takamizawa, Keisuke; Tsurumaki-Fukuchi, Atsushi; Takahashi, Yasuo

    2016-08-21

    The switching operation of a Cu/MoOx/TiN resistive random access memory (ReRAM) device was investigated using in situ transmission electron microscopy (TEM), where the TiN surface was slightly oxidized (ox-TiN). The relationship between the switching properties and the dynamics of the ReRAM microstructure was confirmed experimentally. The growth and/or shrinkage of the conductive filament (CF) can be classified into two set modes and two reset modes. These switching modes depend on the device's switching history, factors such as the amount of Cu inclusions in the MoOx layer and the CF geometry. High currents are needed to produce an observable change in the CF. However, sharp and stable switching behaviour can be achieved without requiring such a major change. The local region around the CF is thought to contribute to the ReRAM switching process. PMID:27456192

  20. New Approach on Logic Application of Ferroelectric Random Access Memory Technology

    NASA Astrophysics Data System (ADS)

    Takayama, Masao; Koyama, Shinzo; Nozawa, Hiroshi

    2002-11-01

    In this paper, a new approach is described to solve some problems that occur when ferroelectric random access memory (FeRAM) is applied to logic circuits, particularly RSA cryptography. Application of a programmable switch device to RSA-based cryptography processing circuits was explored. RSA-based cryptography processing circuits have been designed as code conversion circuits. The capacity of the code conversion programmable AND gate and FeRAM and the translation rate have been investigated as a function of bit length. As a result, a problem of huge capacity at the practical bit length can be predicted theoretically. To solve this problem, we propose a new scheme for circuits and a new algorithm of logic operation using the binomial theorem.

  1. Understanding Electrical Conduction States in WO3 Thin Films Applied for Resistive Random-Access Memory

    NASA Astrophysics Data System (ADS)

    Ta, Thi Kieu Hanh; Pham, Kim Ngoc; Dao, Thi Bang Tam; Tran, Dai Lam; Phan, Bach Thang

    2016-05-01

    The electrical conduction and associated resistance switching mechanism of top electrode/WO3/bottom electrode devices [top electrode (TE): Ag, Ti; bottom electrode (BE): Pt, fluorine-doped tin oxide] have been investigated. The direction of switching and switching ability depended on both the top and bottom electrode material. Multiple electrical conduction mechanisms control the leakage current of such switching devices, including trap-controlled space-charge, ballistic, Ohmic, and Fowler-Nordheim tunneling effects. The transition between electrical conduction states is also linked to the switching (SET-RESET) process. This is the first report of ballistic conduction in research into resistive random-access memory. The associated resistive switching mechanisms are also discussed.

  2. Low-energy Resistive Random Access Memory Devices with No Need for a Compliance Current.

    PubMed

    Xu, Zedong; Yu, Lina; Wu, Yong; Dong, Chang; Deng, Ning; Xu, Xiaoguang; Miao, J; Jiang, Yong

    2015-01-01

    A novel resistive random access memory device is designed with SrTiO3/ La2/3Sr1/3MnO3 (LSMO)/MgAl2O4 (MAO)/Cu structure, in which metallic epitaxial LSMO is employed as the bottom electrode rather than traditional metal materials. In this device, the critical external compliance current is no longer necessary due to the high self-resistance of LSMO. The LMSO bottom electrode can act as a series resistor to offer a compliance current during the set process. Besides, the device also has excellent switching features which are originated in the formation of Cu filaments under external voltage. Therefore it provides the possibility of reducing power consumption and accelerating the commercialization of resistive switching devices. PMID:25982101

  3. Improvement of Resistive Random Access Memory Device Performance via Embedding of Low-K Dielectric Layer.

    PubMed

    Jang, Sung Hwan; Ryu, Ju Tae; Jung, Hyun Soo; Kim, Tae Whan

    2016-02-01

    The switching mechanisms of resistive random access memories (ReRAMs) were strongly related to the formation and rupture of conduction filaments (CFs) in the transition metal oxide (TMO) layer. The novel method approached to enhance the electrical characteristics of ReRAMs by introducing of the local insertion of the low-k dielectric layer inside the TMO layer. Simulation results showed that the insertion of the low-k dielectric layer in the TMO layer reduced the switching volume and the generation of CFs. The large variation of resistive switching properties was caused by the stochastic characteristics of the CFs, which was involved in switching by generation and rupture. The electrical characteristics of the novel ReRAMs exhibited a low reset current of below 20 microA, the high uniformity of the resistive switching, and the narrow variation of the resistance for the high resistance state. PMID:27433626

  4. Atomistic study of dynamics for metallic filament growth in conductive-bridge random access memory.

    PubMed

    Qin, Shengjun; Liu, Zhan; Zhang, Guo; Zhang, Jinyu; Sun, Yaping; Wu, Huaqiang; Qian, He; Yu, Zhiping

    2015-04-14

    The growth dynamics for metallic filaments in conductive-bridge resistive-switching random access memory (CBRAM) are studied using the kinetic Monte Carlo (KMC) method. The physical process at the atomistic level is revealed in explaining the experimental observation that filament growth can originate at either the cathode or the anode. The statistical nature of the filament growth is best shown by the random topography of dendrite-like conductive paths obtained. Critical material properties, such as charged-particle mobility in the switching layer of a solid electrolyte or a dielectric, are mapped to KMC model parameters through activation energy, etc. The accuracy of the simulator is established by the good agreement between the simulated forming time and the measured data. PMID:25750983

  5. Voltage induced magnetostrictive switching of nanomagnets: Strain assisted strain transfer torque random access memory

    SciTech Connect

    Khan, Asif Nikonov, Dmitri E.; Manipatruni, Sasikanth; Ghani, Tahir; Young, Ian A.

    2014-06-30

    A spintronic device, called the “strain assisted spin transfer torque (STT) random access memory (RAM),” is proposed by combining the magnetostriction effect and the spin transfer torque effect which can result in a dramatic improvement in the energy dissipation relative to a conventional STT-RAM. Magnetization switching in the device which is a piezoelectric-ferromagnetic heterostructure via the combined magnetostriction and STT effect is simulated by solving the Landau-Lifshitz-Gilbert equation incorporating the influence of thermal noise. The simulations show that, in such a device, each of these two mechanisms (magnetostriction and spin transfer torque) provides in a 90° rotation of the magnetization leading a deterministic 180° switching with a critical current significantly smaller than that required for spin torque alone. Such a scheme is an attractive option for writing magnetic RAM cells.

  6. Conductive-bridging random access memory: challenges and opportunity for 3D architecture.

    PubMed

    Jana, Debanjan; Roy, Sourav; Panja, Rajeswar; Dutta, Mrinmoy; Rahaman, Sheikh Ziaur; Mahapatra, Rajat; Maikap, Siddheswar

    2015-01-01

    The performances of conductive-bridging random access memory (CBRAM) have been reviewed for different switching materials such as chalcogenides, oxides, and bilayers in different structures. The structure consists of an inert electrode and one oxidized electrode of copper (Cu) or silver (Ag). The switching mechanism is the formation/dissolution of a metallic filament in the switching materials under external bias. However, the growth dynamics of the metallic filament in different switching materials are still debated. All CBRAM devices are switching under an operation current of 0.1 μA to 1 mA, and an operation voltage of ±2 V is also needed. The device can reach a low current of 5 pA; however, current compliance-dependent reliability is a challenging issue. Although a chalcogenide-based material has opportunity to have better endurance as compared to an oxide-based material, data retention and integration with the complementary metal-oxide-semiconductor (CMOS) process are also issues. Devices with bilayer switching materials show better resistive switching characteristics as compared to those with a single switching layer, especially a program/erase endurance of >10(5) cycles with a high speed of few nanoseconds. Multi-level cell operation is possible, but the stability of the high resistance state is also an important reliability concern. These devices show a good data retention of >10(5) s at >85°C. However, more study is needed to achieve a 10-year guarantee of data retention for non-volatile memory application. The crossbar memory is benefited for high density with low power operation. Some CBRAM devices as a chip have been reported for proto-typical production. This review shows that operation current should be optimized for few microamperes with a maintaining speed of few nanoseconds, which will have challenges and also opportunities for three-dimensional (3D) architecture. PMID:25977660

  7. Metal oxide resistive random access memory based synaptic devices for brain-inspired computing

    NASA Astrophysics Data System (ADS)

    Gao, Bin; Kang, Jinfeng; Zhou, Zheng; Chen, Zhe; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan

    2016-04-01

    The traditional Boolean computing paradigm based on the von Neumann architecture is facing great challenges for future information technology applications such as big data, the Internet of Things (IoT), and wearable devices, due to the limited processing capability issues such as binary data storage and computing, non-parallel data processing, and the buses requirement between memory units and logic units. The brain-inspired neuromorphic computing paradigm is believed to be one of the promising solutions for realizing more complex functions with a lower cost. To perform such brain-inspired computing with a low cost and low power consumption, novel devices for use as electronic synapses are needed. Metal oxide resistive random access memory (ReRAM) devices have emerged as the leading candidate for electronic synapses. This paper comprehensively addresses the recent work on the design and optimization of metal oxide ReRAM-based synaptic devices. A performance enhancement methodology and optimized operation scheme to achieve analog resistive switching and low-energy training behavior are provided. A three-dimensional vertical synapse network architecture is proposed for high-density integration and low-cost fabrication. The impacts of the ReRAM synaptic device features on the performances of neuromorphic systems are also discussed on the basis of a constructed neuromorphic visual system with a pattern recognition function. Possible solutions to achieve the high recognition accuracy and efficiency of neuromorphic systems are presented.

  8. Ultrafast switching in nanoscale phase-change random access memory with superlattice-like structures.

    PubMed

    Loke, Desmond; Shi, Luping; Wang, Weijie; Zhao, Rong; Yang, Hongxin; Ng, Lung-Tat; Lim, Kian-Guan; Chong, Tow-Chong; Yeo, Yee-Chia

    2011-06-24

    Phase-change random access memory cells with superlattice-like (SLL) GeTe/Sb(2)Te(3) were demonstrated to have excellent scaling performance in terms of switching speed and operating voltage. In this study, the correlations between the cell size, switching speed and operating voltage of the SLL cells were identified and investigated. We found that small SLL cells can achieve faster switching speed and lower operating voltage compared to the large SLL cells. Fast amorphization and crystallization of 300 ps and 1 ns were achieved in the 40 nm SLL cells, respectively, both significantly faster than those observed in the Ge(2)Sb(2)Te(5) (GST) cells of the same cell size. 40 nm SLL cells were found to switch with low amorphization voltage of 0.9 V when pulse-widths of 5 ns were employed, which is much lower than the 1.6 V required by the GST cells of the same cell size. These effects can be attributed to the fast heterogeneous crystallization, low thermal conductivity and high resistivity of the SLL structures. Nanoscale PCRAM with SLL structure promises applications in high speed and low power memory devices. PMID:21572204

  9. Does the mismatch negativity operate on a consciously accessible memory trace?

    PubMed

    Dykstra, Andrew R; Gutschalk, Alexander

    2015-11-01

    The extent to which the contents of short-term memory are consciously accessible is a fundamental question of cognitive science. In audition, short-term memory is often studied via the mismatch negativity (MMN), a change-related component of the auditory evoked response that is elicited by violations of otherwise regular stimulus sequences. The prevailing functional view of the MMN is that it operates on preattentive and even preconscious stimulus representations. We directly examined the preconscious notion of the MMN using informational masking and magnetoencephalography. Spectrally isolated and otherwise suprathreshold auditory oddball sequences were occasionally random rendered inaudible by embedding them in random multitone masker "clouds." Despite identical stimulation/task contexts and a clear representation of all stimuli in auditory cortex, MMN was only observed when the preceding regularity (that is, the standard stream) was consciously perceived. The results call into question the preconscious interpretation of MMN and raise the possibility that it might index partial awareness in the absence of overt behavior. PMID:26702432

  10. Does the mismatch negativity operate on a consciously accessible memory trace?

    PubMed Central

    Dykstra, Andrew R.; Gutschalk, Alexander

    2015-01-01

    The extent to which the contents of short-term memory are consciously accessible is a fundamental question of cognitive science. In audition, short-term memory is often studied via the mismatch negativity (MMN), a change-related component of the auditory evoked response that is elicited by violations of otherwise regular stimulus sequences. The prevailing functional view of the MMN is that it operates on preattentive and even preconscious stimulus representations. We directly examined the preconscious notion of the MMN using informational masking and magnetoencephalography. Spectrally isolated and otherwise suprathreshold auditory oddball sequences were occasionally random rendered inaudible by embedding them in random multitone masker “clouds.” Despite identical stimulation/task contexts and a clear representation of all stimuli in auditory cortex, MMN was only observed when the preceding regularity (that is, the standard stream) was consciously perceived. The results call into question the preconscious interpretation of MMN and raise the possibility that it might index partial awareness in the absence of overt behavior. PMID:26702432

  11. Influence of ultraviolet irradiation on data retention characteristics in resistive random access memory

    NASA Astrophysics Data System (ADS)

    Kimura, K.; Ohmi, K.; Kishida, S.; Kinoshita, K.

    2016-03-01

    With increasing density of memory devices, the issue of generating soft errors by cosmic rays is becoming more and more serious. Therefore, the irradiation resistance of resistance random access memory (ReRAM) to cosmic radiation has to be elucidated for practical use. In this paper, we investigated the data retention characteristics of ReRAM against ultraviolet irradiation with a Pt/NiO/ITO structure. Soft errors were confirmed to be caused by ultraviolet irradiation in both low- and high-resistance states. An analysis of the wavelength dependence of light irradiation on data retention characteristics suggested that electronic excitation from the valence to the conduction band and to the energy level generated due to the introduction of oxygen vacancies caused the errors. Based on a statistically estimated soft error rates, the errors were suggested to be caused by the cohesion and dispersion of oxygen vacancies owing to the generation of electron-hole pairs and valence changes by the ultraviolet irradiation.

  12. Microstructural transitions in resistive random access memory composed of molybdenum oxide with copper during switching cycles

    NASA Astrophysics Data System (ADS)

    Arita, Masashi; Ohno, Yuuki; Murakami, Yosuke; Takamizawa, Keisuke; Tsurumaki-Fukuchi, Atsushi; Takahashi, Yasuo

    2016-08-01

    The switching operation of a Cu/MoOx/TiN resistive random access memory (ReRAM) device was investigated using in situ transmission electron microscopy (TEM), where the TiN surface was slightly oxidized (ox-TiN). The relationship between the switching properties and the dynamics of the ReRAM microstructure was confirmed experimentally. The growth and/or shrinkage of the conductive filament (CF) can be classified into two set modes and two reset modes. These switching modes depend on the device's switching history, factors such as the amount of Cu inclusions in the MoOx layer and the CF geometry. High currents are needed to produce an observable change in the CF. However, sharp and stable switching behaviour can be achieved without requiring such a major change. The local region around the CF is thought to contribute to the ReRAM switching process.The switching operation of a Cu/MoOx/TiN resistive random access memory (ReRAM) device was investigated using in situ transmission electron microscopy (TEM), where the TiN surface was slightly oxidized (ox-TiN). The relationship between the switching properties and the dynamics of the ReRAM microstructure was confirmed experimentally. The growth and/or shrinkage of the conductive filament (CF) can be classified into two set modes and two reset modes. These switching modes depend on the device's switching history, factors such as the amount of Cu inclusions in the MoOx layer and the CF geometry. High currents are needed to produce an observable change in the CF. However, sharp and stable switching behaviour can be achieved without requiring such a major change. The local region around the CF is thought to contribute to the ReRAM switching process. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr02602h

  13. Context controls access to working and reference memory in the pigeon (Columba livia).

    PubMed

    Roberts, William A; Macpherson, Krista; Strang, Caroline

    2016-01-01

    The interaction between working and reference memory systems was examined under conditions in which salient contextual cues were presented during memory retrieval. Ambient colored lights (red or green) bathed the operant chamber during the presentation of comparison stimuli in delayed matching-to-sample training (working memory) and during the presentation of the comparison stimuli as S+ and S- cues in discrimination training (reference memory). Strong competition between memory systems appeared when the same contextual cue appeared during working and reference memory training. When different contextual cues were used, however, working memory was completely protected from reference memory interference. PMID:26781056

  14. Memory.

    ERIC Educational Resources Information Center

    McKean, Kevin

    1983-01-01

    Discusses current research (including that involving amnesiacs and snails) into the nature of the memory process, differentiating between and providing examples of "fact" memory and "skill" memory. Suggests that three brain parts (thalamus, fornix, mammilary body) are involved in the memory process. (JN)

  15. Evaluation of Data Retention Characteristics for Ferroelectric Random Access Memories (FRAMs)

    NASA Technical Reports Server (NTRS)

    Sharma, Ashok K.; Teverovsky, Alexander

    2001-01-01

    Data retention and fatigue characteristics of 64 Kb lead zirconate titanate (PZT)-based Ferroelectric Random Access Memories (FRAMs) microcircuits manufactured by Ramtron were examined over temperature range from -85 C to +310 C for ceramic packaged parts and from -85 C to +175 C for plastic parts, during retention periods up to several thousand hours. Intrinsic failures, which were caused by a thermal degradation of the ferroelectric cells, occurred in ceramic parts after tens or hundreds hours of aging at temperatures above 200 C. The activation energy of the retention test failures was 1.05 eV and the extrapolated mean-time-to-failure (MTTF) at room temperature was estimated to be more than 280 years. Multiple write-read cycling (up to 3x10(exp 7)) during the fatigue testing of plastic and ceramic parts did not result in any parametric or functional failures. However, operational currents linearly decreased with the logarithm of number of cycles thus indicating fatigue process in PZT films. Plastic parts, that had more recent date code as compared to ceramic parts, appeared to be using die with improved process technology and showed significantly smaller changes in operational currents and data access times.

  16. Three-Year-Old Children Can Access Their Own Memory to Guide Responses on a Visual Matching Task

    ERIC Educational Resources Information Center

    Balcomb, Frances K.; Gerken, LouAnn

    2008-01-01

    Many models of learning rely on accessing internal knowledge states. Yet, although infants and young children are recognized to be proficient learners, the ability to act on metacognitive information is not thought to develop until early school years. In the experiments reported here, 3.5-year-olds demonstrated memory-monitoring skills by…

  17. Impact of Device Scaling on Deep Sub-micron Transistor Reliability: A Study of Reliability Trends using SRAM

    NASA Technical Reports Server (NTRS)

    White, Mark; Huang, Bing; Qin, Jin; Gur, Zvi; Talmor, Michael; Chen, Yuan; Heidecker, Jason; Nguyen, Duc; Bernstein, Joseph

    2005-01-01

    As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.

  18. Evaluating a radiation monitor for mixed-field environments based on SRAM technology

    NASA Astrophysics Data System (ADS)

    Tsiligiannis, G.; Dilillo, L.; Bosio, A.; Girard, P.; Pravossoudovitch, S.; Todri, A.; Virazel, A.; Mekki, J.; Brugger, M.; Wrobel, F.; Saigne, F.

    2014-05-01

    Instruments operating in particle accelerators and colliders are exposed to radiations that are composed of particles of different types and energies. Several of these instruments often embed devices that are not hardened against radiation effects. Thus, there is a strong need for monitoring the levels of radiation inside the mixed-field radiation areas, throughout different positions. Different metrics exist for measuring the radiation damage induced to electronic devices, such as the Total Ionizing Dose (TID), the Displacement Damage (DD) and of course the fluence of particles for estimating the error rates of the electronic devices among other applications. In this paper, we propose an SRAM based monitor, that is used to define the fluence of High Energy Hadrons (HEH) by detecting Single Event Upsets in the memory array. We evaluated the device by testing it inside the H4IRRAD area of CERN, a test area that reproduces the radiation conditions inside the Large Hadron Collider (LHC) tunnel and its shielded areas. By using stability estimation methods and presenting experimental data, we prove that this device is proper to be used for such a purpose.

  19. Susceptibility of Redundant Versus Singular Clock Domains Implemented in SRAM-Based FPGA TMR Designs

    NASA Technical Reports Server (NTRS)

    Berg, Melanie D.; LaBel, Kenneth A.; Pellish, Jonathan

    2016-01-01

    We present the challenges that arise when using redundant clock domains due to their clock-skew. Radiation data show that a singular clock domain (DTMR) provides an improved TMR methodology for SRAM-based FPGAs over redundant clocks.

  20. SEU response of an entire SRAM cell simulated as one contiguous three dimensional device domain

    SciTech Connect

    Roche, P.; Palau, J.M.; Bruguier, G.; Gasiot, J.; Belhaddad, K.; Ecoffet, R.

    1998-12-01

    The first SEU response of a complete 3-D SRAM cell is presented. This simulation method allows to verify the accuracy of the commonly used mixed-mode technique and to study coupling effects between different junctions of the cell.

  1. Tuning resistance states by thickness control in an electroforming-free nanometallic complementary resistance random access memory

    NASA Astrophysics Data System (ADS)

    Yang, Xiang; Lu, Yang; Lee, Jongho; Chen, I.-Wei

    2016-01-01

    Tuning low resistance state is crucial for resistance random access memory (RRAM) that aims to achieve optimal read margin and design flexibility. By back-to-back stacking two nanometallic bipolar RRAMs with different thickness into a complementary structure, we have found that its low resistance can be reliably tuned over several orders of magnitude. Such high tunability originates from the exponential thickness dependence of the high resistance state of nanometallic RRAM, in which electron wave localization in a random network gives rise to the unique scaling behavior. The complementary nanometallic RRAM provides electroforming-free, multi-resistance-state, sub-100 ns switching capability with advantageous characteristics for memory arrays.

  2. Performance improvement of gadolinium oxide resistive random access memory treated by hydrogen plasma immersion ion implantation

    SciTech Connect

    Wang, Jer-Chyi Hsu, Chih-Hsien; Ye, Yu-Ren; Ai, Chi-Fong; Tsai, Wen-Fa

    2014-03-15

    Characteristics improvement of gadolinium oxide (Gd{sub x}O{sub y}) resistive random access memories (RRAMs) treated by hydrogen plasma immersion ion implantation (PIII) was investigated. With the hydrogen PIII treatment, the Gd{sub x}O{sub y} RRAMs exhibited low set/reset voltages and a high resistance ratio, which were attributed to the enhanced movement of oxygen ions within the Gd{sub x}O{sub y} films and the increased Schottky barrier height at Pt/Gd{sub x}O{sub y} interface, respectively. The resistive switching mechanism of Gd{sub x}O{sub y} RRAMs was dominated by Schottky emission, as proved by the area dependence of the resistance in the low resistance state. After the hydrogen PIII treatment, a retention time of more than 10{sup 4} s was achieved at an elevated measurement temperature. In addition, a stable cycling endurance with the resistance ratio of more than three orders of magnitude of the Gd{sub x}O{sub y} RRAMs can be obtained.

  3. Switching methods in magnetic random access memory for low power applications

    NASA Astrophysics Data System (ADS)

    Guchang, Han; Jiancheng, Huang; Cheow Hin, Sim; Tran, Michael; Sze Ter, Lim

    2015-06-01

    Effect of saturation magnetization (Ms) of the free layer (FL) on the switching current is analyzed for spin transfer torque (STT) magnetic random access memory (MRAM). For in-plane FL, critical switching current (Ic0) decreases as Ms decreases. However, reduction in Ms also results in a low thermal stability factor (Δ), which must be compensated through increasing shape anisotropy, thus limiting scalability. For perpendicular FL, Ic0 reduction by using low-Ms materials is actually at the expense of data retention. To save energy consumed by STT current, two electric field (EF) controlled switching methods are proposed. Our simulation results show that elliptical FL can be switched by an EF pulse with a suitable width. However, it is difficult to implement this type of switching in real MRAM devices due to the distribution of the required switching pulse widths. A reliable switching method is to use an Oersted field guided switching. Our simulation and experimental results show that the bi-directional magnetization switching could be realized by an EF with an external field as low as  ±5 Oe if the offset field could be removed.

  4. Solution-processed carbon nanotube thin-film complementary static random access memory

    NASA Astrophysics Data System (ADS)

    Geier, Michael L.; McMorrow, Julian J.; Xu, Weichao; Zhu, Jian; Kim, Chris H.; Marks, Tobin J.; Hersam, Mark C.

    2015-11-01

    Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties, making them one of the most promising candidates for solution-processable, high-performance integrated circuits. In particular, advances in the enrichment of high-purity semiconducting SWCNTs have enabled recent circuit demonstrations including synchronous digital logic, flexible electronics and high-frequency applications. However, due to the stringent requirements of the transistors used in complementary metal-oxide-semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.

  5. Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 1

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    Electrical characterization and qualification tests were performed on the RCA MWS5001D, 1024 by 1-bit, CMOS, random access memory. Characterization tests were performed on five devices. The tests included functional tests, AC parametric worst case pattern selection test, determination of worst-case transition for setup and hold times and a series of schmoo plots. The qualification tests were performed on 32 devices and included a 2000 hour burn in with electrical tests performed at 0 hours and after 168, 1000, and 2000 hours of burn in. The tests performed included functional tests and AC and DC parametric tests. All of the tests in the characterization phase, with the exception of the worst-case transition test, were performed at ambient temperatures of 25, -55 and 125 C. The worst-case transition test was performed at 25 C. The preburn in electrical tests were performed at 25, -55, and 125 C. All burn in endpoint tests were performed at 25, -40, -55, 85, and 125 C.

  6. Single-crystalline CuO nanowires for resistive random access memory applications

    SciTech Connect

    Hong, Yi-Siang; Chen, Jui-Yuan; Huang, Chun-Wei; Chiu, Chung-Hua; Huang, Yu-Ting; Huang, Ting Kai; He, Ruo Shiuan; Wu, Wen-Wei

    2015-04-27

    Recently, the mechanism of resistive random access memory (RRAM) has been partly clarified and determined to be controlled by the forming and erasing of conducting filaments (CF). However, the size of the CF may restrict the application and development as devices are scaled down. In this work, we synthesized CuO nanowires (NW) (∼150 nm in diameter) to fabricate a CuO NW RRAM nanodevice that was much smaller than the filament (∼2 μm) observed in a bulk CuO RRAM device in a previous study. HRTEM indicated that the Cu{sub 2}O phase was generated after operation, which demonstrated that the filament could be minimize to as small as 3.8 nm when the device is scaled down. In addition, energy dispersive spectroscopy (EDS) and electron energy loss spectroscopy (EELS) show the resistive switching of the dielectric layer resulted from the aggregated oxygen vacancies, which also match with the I-V fitting results. Those results not only verify the switching mechanism of CuO RRAM but also show RRAM has the potential to shrink in size, which will be beneficial to the practical application of RRAM devices.

  7. Solution-processed carbon nanotube thin-film complementary static random access memory.

    PubMed

    Geier, Michael L; McMorrow, Julian J; Xu, Weichao; Zhu, Jian; Kim, Chris H; Marks, Tobin J; Hersam, Mark C

    2015-11-01

    Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties, making them one of the most promising candidates for solution-processable, high-performance integrated circuits. In particular, advances in the enrichment of high-purity semiconducting SWCNTs have enabled recent circuit demonstrations including synchronous digital logic, flexible electronics and high-frequency applications. However, due to the stringent requirements of the transistors used in complementary metal-oxide-semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. PMID:26344184

  8. High uniformity and improved nonlinearity by embedding nanocrystals in selector-less resistive random access memory.

    PubMed

    Banerjee, Writam; Lu, Nianduan; Li, Ling; Sun, Pengxiao; Liu, Qi; Lv, Hangbing; Long, Shibing; Liu, Ming

    2014-12-10

    The sneak path problem is one of the major hindrances for the application of high density 3D crossbar resistive random access memory (RRAM). For the selector-less RRAM devices, nonlinear (NL) current-voltage (I-V) characteristics are an alternative approach to minimize the sneak paths. In this work we have demonstrated metallic IrOx nanocrystal (IrOx-NC) based selector-less crossbar RRAM devices in an IrOx/AlOx/IrOx-NC/AlOx/W structure with very reliable hysteresis resistive switching of >10 000 cycles, stable multiple levels, and high temperature (HT) data retention. Moreover, an improvement in the NL behavior has been reported as compared to a pure high-κ AlOx RRAM. The origin of the NL nature has been discussed using the hopping model and Luittenger's 1D metal theory. The nonlinearity can be further improved by structure engineering and will improve the sensing margin of the devices, which is rewarding for crossbar array integration. PMID:25491764

  9. Flexible conductive-bridging random-access-memory cell vertically stacked with top Ag electrode, PEO, PVK, and bottom Pt electrode.

    PubMed

    Seung, Hyun-Min; Kwon, Kyoung-Cheol; Lee, Gon-Sub; Park, Jea-Gun

    2014-10-31

    Flexible conductive-bridging random-access-memory (RAM) cells were fabricated with a cross-bar memory cell stacked with a top Ag electrode, conductive polymer (poly(n-vinylcarbazole): PVK), electrolyte (polyethylene oxide: PEO), bottom Pt electrode, and flexible substrate (polyethersulfone: PES), exhibiting the bipolar switching behavior of resistive random access memory (ReRAM). The cell also exhibited bending-fatigue-free nonvolatile memory characteristics: i.e., a set voltage of 1.0 V, a reset voltage of -1.6 V, retention time of >1 × 10(5) s with a memory margin of 9.2 × 10(5), program/erase endurance cycles of >10(2) with a memory margin of 8.4 × 10(5), and bending-fatigue-free cycles of ∼1 × 10(3) with a memory margin (I(on)/I(off)) of 3.3 × 10(5). PMID:25297517

  10. Detailed 8-transistor SRAM cell analysis for improved alpha particle radiation hardening in nanometer technologies

    NASA Astrophysics Data System (ADS)

    Bota, Sebastià A.; Torrens, Gabriel; Verd, Jaume; Segura, Jaume

    2015-09-01

    Eight-transistor (8T) cells were introduced to improve variability tolerance, cell stability and low-voltage operation in high-speed SRAM caches by decoupling the read and write design requirements. Altogether, 8T-SRAM can be designed without significant area penalty over 6T-SRAM. Ionizing radiation effects are nowadays a major concern for reliability and dependability of emerging electronic SRAM devices, even for sea-level applications. In this paper we demonstrate from experimental results that the 8T-SRAM also exhibits an enhanced overall intrinsic tolerance to alpha particle radiation even though its critical charge values are smaller than conventional 6T cells. We have experimentally found that the soft error rate measured in accelerated experiments with alpha particles in SRAM devices implemented in a 65 nm CMOS is 56% better for 8T cells with respect to standard 6T-cells. Even more, we show that this value can be increased up to a 200% through transistor sizing optimization.

  11. An amorphous titanium dioxide metal insulator metal selector device for resistive random access memory crossbar arrays with tunable voltage margin

    NASA Astrophysics Data System (ADS)

    Cortese, Simone; Khiat, Ali; Carta, Daniela; Light, Mark E.; Prodromakis, Themistoklis

    2016-01-01

    Resistive random access memory (ReRAM) crossbar arrays have become one of the most promising candidates for next-generation non volatile memories. To become a mature technology, the sneak path current issue must be solved without compromising all the advantages that crossbars offer in terms of electrical performances and fabrication complexity. Here, we present a highly integrable access device based on nickel and sub-stoichiometric amorphous titanium dioxide (TiO2-x), in a metal insulator metal crossbar structure. The high voltage margin of 3 V, amongst the highest reported for monolayer selector devices, and the good current density of 104 A/cm2 make it suitable to sustain ReRAM read and write operations, effectively tackling sneak currents in crossbars without compromising fabrication complexity in a 1 Selector 1 Resistor (1S1R) architecture. Furthermore, the voltage margin is found to be tunable by an annealing step without affecting the device's characteristics.

  12. Encoding and retrieval processes involved in the access of source information in the absence of item memory.

    PubMed

    Ball, B Hunter; DeWitt, Michael R; Knight, Justin B; Hicks, Jason L

    2014-09-01

    The current study sought to examine the relative contributions of encoding and retrieval processes in accessing contextual information in the absence of item memory using an extralist cuing procedure in which the retrieval cues used to query memory for contextual information were related to the target item but never actually studied. In Experiments 1 and 2, participants studied 1 category member (e.g., onion) from a variety of different categories and at test were presented with an unstudied category label (e.g., vegetable) to probe memory for item and source information. In Experiments 3 and 4, 1 member of unidirectional (e.g., credit or card) or bidirectional (e.g., salt or pepper) associates was studied, whereas the other unstudied member served as a test probe. When recall failed, source information was accessible only when items were processed deeply during encoding (Experiments 1 and 2) and when there was strong forward associative strength between the retrieval cue and target (Experiments 3 and 4). These findings suggest that a retrieval probe diagnostic of semantically related item information reinstantiates information bound in memory during encoding that results in reactivation of associated contextual information, contingent upon sufficient learning of the item itself and the association between the item and its context information. PMID:24933700

  13. Chemical state of Ag in Conducting Bridge Random Access Memory cells: a depth resolved X-ray Absorption Spectroscopy investigation.

    NASA Astrophysics Data System (ADS)

    d'Acapito, F.; Souchier, E.; Noe, P.; Blaise, P.; Bernard, M.; Jousseaume, V.

    2016-05-01

    Conducting Bridge Random Access Memories (CBRAM) are a promising substitute for FLASH technology but problems with limited retention of the low resistance ON state still hamper their massive deployment. Depth resolved X-ray Absorption Spectroscopy has been used to describe the chemical state of the atoms of the active electrode (in this case Ag) and to reveal the role of Sb as stabilizer of the metallic state.

  14. ViSA: a neurodynamic model for visuo-spatial working memory, attentional blink, and conscious access.

    PubMed

    Simione, Luca; Raffone, Antonino; Wolters, Gezinus; Salmas, Paola; Nakatani, Chie; Belardinelli, Marta Olivetti; van Leeuwen, Cees

    2012-10-01

    Two separate lines of study have clarified the role of selectivity in conscious access to visual information. Both involve presenting multiple targets and distracters: one simultaneously in a spatially distributed fashion, the other sequentially at a single location. To understand their findings in a unified framework, we propose a neurodynamic model for Visual Selection and Awareness (ViSA). ViSA supports the view that neural representations for conscious access and visuo-spatial working memory are globally distributed and are based on recurrent interactions between perceptual and access control processors. Its flexible global workspace mechanisms enable a unitary account of a broad range of effects: It accounts for the limited storage capacity of visuo-spatial working memory, attentional cueing, and efficient selection with multi-object displays, as well as for the attentional blink and associated sparing and masking effects. In particular, the speed of consolidation for storage in visuo-spatial working memory in ViSA is not fixed but depends adaptively on the input and recurrent signaling. Slowing down of consolidation due to weak bottom-up and recurrent input as a result of brief presentation and masking leads to the attentional blink. Thus, ViSA goes beyond earlier 2-stage and neuronal global workspace accounts of conscious processing limitations. PMID:22823385

  15. Physical and chemical mechanisms in oxide-based resistance random access memory

    NASA Astrophysics Data System (ADS)

    Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Zhang, Rui; Hung, Ya-Chi; Syu, Yong-En; Chang, Yao-Feng; Chen, Min-Chen; Chu, Tian-Jian; Chen, Hsin-Lu; Pan, Chih-Hung; Shih, Chih-Cheng; Zheng, Jin-Cheng; Sze, Simon M.

    2015-03-01

    In this review, we provide an overview of our work in resistive switching mechanisms on oxide-based resistance random access memory (RRAM) devices. Based on the investigation of physical and chemical mechanisms, we focus on its materials, device structures, and treatment methods so as to provide an in-depth perspective of state-of-the-art oxide-based RRAM. The critical voltage and constant reaction energy properties were found, which can be used to prospectively modulate voltage and operation time to control RRAM device working performance and forecast material composition. The quantized switching phenomena in RRAM devices were demonstrated at ultra-cryogenic temperature (4K), which is attributed to the atomic-level reaction in metallic filament. In the aspect of chemical mechanisms, we use the Coulomb Faraday theorem to investigate the chemical reaction equations of RRAM for the first time. We can clearly observe that the first-order reaction series is the basis for chemical reaction during reset process in the study. Furthermore, the activation energy of chemical reactions can be extracted by changing temperature during the reset process, from which the oxygen ion reaction process can be found in the RRAM device. As for its materials, silicon oxide is compatible to semiconductor fabrication lines. It is especially promising for the silicon oxide-doped metal technology to be introduced into the industry. Based on that, double-ended graphene oxide-doped silicon oxide based via-structure RRAM with filament self-aligning formation, and self-current limiting operation ability is demonstrated. The outstanding device characteristics are attributed to the oxidation and reduction of graphene oxide flakes formed during the sputter process. Besides, we have also adopted a new concept of supercritical CO2 fluid treatment to efficiently reduce the operation current of RRAM devices for portable electronic applications.

  16. Physical and chemical mechanisms in oxide-based resistance random access memory.

    PubMed

    Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Zhang, Rui; Hung, Ya-Chi; Syu, Yong-En; Chang, Yao-Feng; Chen, Min-Chen; Chu, Tian-Jian; Chen, Hsin-Lu; Pan, Chih-Hung; Shih, Chih-Cheng; Zheng, Jin-Cheng; Sze, Simon M

    2015-01-01

    In this review, we provide an overview of our work in resistive switching mechanisms on oxide-based resistance random access memory (RRAM) devices. Based on the investigation of physical and chemical mechanisms, we focus on its materials, device structures, and treatment methods so as to provide an in-depth perspective of state-of-the-art oxide-based RRAM. The critical voltage and constant reaction energy properties were found, which can be used to prospectively modulate voltage and operation time to control RRAM device working performance and forecast material composition. The quantized switching phenomena in RRAM devices were demonstrated at ultra-cryogenic temperature (4K), which is attributed to the atomic-level reaction in metallic filament. In the aspect of chemical mechanisms, we use the Coulomb Faraday theorem to investigate the chemical reaction equations of RRAM for the first time. We can clearly observe that the first-order reaction series is the basis for chemical reaction during reset process in the study. Furthermore, the activation energy of chemical reactions can be extracted by changing temperature during the reset process, from which the oxygen ion reaction process can be found in the RRAM device. As for its materials, silicon oxide is compatible to semiconductor fabrication lines. It is especially promising for the silicon oxide-doped metal technology to be introduced into the industry. Based on that, double-ended graphene oxide-doped silicon oxide based via-structure RRAM with filament self-aligning formation, and self-current limiting operation ability is demonstrated. The outstanding device characteristics are attributed to the oxidation and reduction of graphene oxide flakes formed during the sputter process. Besides, we have also adopted a new concept of supercritical CO2 fluid treatment to efficiently reduce the operation current of RRAM devices for portable electronic applications. PMID:25873842

  17. Current Development Status and Future Challenges of Ferroelectric Random Access Memory Technologies

    NASA Astrophysics Data System (ADS)

    Lee, Sungyung; Kim, Kinam

    2006-04-01

    For ferroelectric random access memory (FRAM) to be beneficial in future mobile devices, high-density FRAM with nm scaled cell should be developed. We have succeeded in scaling further the cell size of one-pass transistor and one-storage capacitor (1T1C) FRAM down to 0.27 μm2 at 150 nm technology node. Owing to new SrRuO3 (SRO) electrode technology along with ultrathin PbZrTiO3 (PZT) using metal organic chemical vapor deposition (MOCVD) technology, two-dimensional (2-D) metal-insulator-metal (MIM) ferroelectric capacitor was successfully scaled down vertically to 200 nm. By the application of a new double hard mask capacitor etching technology, 0.11-μm2-area 200-nm-thick 2-D PZT capacitor was successfully isolated with 180 nm spacing. As a result, a high remanent polarization of 40 μC/cm2 was obtained at 1.6 V on a 0.11 μm2 ferroelectric storage capacitor of the 0.27 μm2 cell 1T1C FRAM. Great advances in three-dimensional (3-D) ferroelectric capacitor, which is essential for 6-8 F2 cell 1T1C FRAM at nm scaled technology node, have been made by introducing a new atomic layer deposition (ALD) method for 3-D electrode and a novel MOCVD PZT deposition for 3-D PZT. As a result, for the first time, robust hysteresis was obtained from a 3-D PZT capacitor.

  18. Accessibility

    MedlinePlus

    ... www.nlm.nih.gov/medlineplus/accessibility.html MedlinePlus Accessibility To use the sharing features on this page, ... Subscribe to RSS Follow us Disclaimers Copyright Privacy Accessibility Quality Guidelines Viewers & Players MedlinePlus Connect for EHRs ...

  19. PIYAS-proceeding to intelligent service oriented memory allocation for flash based data centric sensor devices in wireless sensor networks.

    PubMed

    Rizvi, Sanam Shahla; Chung, Tae-Sun

    2010-01-01

    Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks. PMID:22315541

  20. Contexts and Control Operations Used in Accessing List-Specific, Generalized, and Semantic Memories

    ERIC Educational Resources Information Center

    Humphreys, Michael S.; Murray, Krista L.; Maguire, Angela M.

    2009-01-01

    The human ability to focus memory retrieval operations on a particular list, episode or memory structure has not been fully appreciated or documented. In Experiment 1-3, we make it increasingly difficult for participants to switch between a less recent list (multiple study opportunities), and a more recent list (single study opportunity). Task…

  1. Speed and Accuracy of Accessing Information in Working Memory: An Individual Differences Investigation of Focus Switching

    ERIC Educational Resources Information Center

    Unsworth, Nash; Engle, Randall W.

    2008-01-01

    Three experiments examined the nature of individual differences in switching the focus of attention in working memory. Participants performed 3 versions of a continuous counting task that required successive updating and switching between counts. Across all 3 experiments, individual differences in working memory span and fluid intelligence were…

  2. Retrieval practice enhances the accessibility but not the quality of memory.

    PubMed

    Sutterer, David W; Awh, Edward

    2016-06-01

    Numerous studies have demonstrated that retrieval from long-term memory (LTM) can enhance subsequent memory performance, a phenomenon labeled the retrieval practice effect. However, the almost exclusive reliance on categorical stimuli in this literature leaves open a basic question about the nature of this improvement in memory performance. It has not yet been determined whether retrieval practice improves the probability of successful memory retrieval or the quality of the retrieved representation. To answer this question, we conducted three experiments using a mixture modeling approach (Zhang & Luck, 2008) that provides a measure of both the probability of recall and the quality of the recalled memories. Subjects attempted to memorize the color of 400 unique shapes. After every 10 images were presented, subjects either recalled the last 10 colors (the retrieval practice condition) by clicking on a color wheel with each shape as a retrieval cue or they participated in a control condition that involved no further presentations (Experiment 1) or restudy of the 10 shape/color associations (Experiments 2 and 3). Performance in a subsequent delayed recall test revealed a robust retrieval practice effect. Subjects recalled a significantly higher proportion of items that they had previously retrieved relative to items that were untested or that they had restudied. Interestingly, retrieval practice did not elicit any improvement in the precision of the retrieved memories. The same empirical pattern also was observed following delays of greater than 24 hours. Thus, retrieval practice increases the probability of successful memory retrieval but does not improve memory quality. PMID:26404635

  3. Oxide Defect Engineering Methods for Valence Change (VCM) Resistive Random Access Memories

    NASA Astrophysics Data System (ADS)

    Capulong, Jihan O.

    Electrical switching requirements for resistive random access memory (ReRAM) devices are multifaceted, based on device application. Thus, it is important to obtain an understanding of these switching properties and how they relate to the oxygen vacancy concentration and oxygen vacancy defects. Oxygen vacancy defects in the switching oxide of valence-change-based ReRAM (VCM ReRAM) play a significant role in device switching properties. Oxygen vacancies facilitate resistive switching as they form the conductive filament that changes the resistance state of the device. This dissertation will present two methods of modulating the defect concentration in VCM ReRAM composed of Pt/HfOx/Ti stack: 1) rapid thermal annealing (RTA) in Ar using different temperatures, and 2) doping using ion implantation under different dose levels. Metrology techniques such as x-ray diffractometry (XRD), x-ray photoelectron spectroscopy (XPS), and photoluminescence (PL) spectroscopy were utilized to characterize the HfOx switching oxide, which provided insight on the material properties and oxygen vacancy concentration in the oxide that was used to explain the changes in the electrical properties of the ReRAM devices. The resulting impact on the resistive switching characteristics of the devices, such as the forming voltage, set and reset threshold voltages, ON and OFF resistances, resistance ratio, and switching dispersion or uniformity were explored and summarized. Annealing in Ar showed significant impact on the forming voltage, with as much as 45% (from 22V to 12 V) of improvement, as the annealing temperature was increased. However, drawbacks of a higher oxide leakage and worse switching uniformity were seen with increasing annealing temperature. Meanwhile, doping the oxide by ion implantation showed significant effects on the resistive switching characteristics. Ta doping modulated the following switching properties with increasing dose: a) the reduction of the forming voltage, and Vset

  4. Effect of embedded metal nanocrystals on the resistive switching characteristics in NiN-based resistive random access memory cells

    SciTech Connect

    Yun, Min Ju; Kim, Hee-Dong; Man Hong, Seok; Hyun Park, Ju; Su Jeon, Dong; Geun Kim, Tae

    2014-03-07

    The metal nanocrystals (NCs) embedded-NiN-based resistive random access memory cells are demonstrated using several metal NCs (i.e., Pt, Ni, and Ti) with different physical parameters in order to investigate the metal NC's dependence on resistive switching (RS) characteristics. First, depending on the electronegativity of metal, the size of metal NCs is determined and this affects the operating current of memory cells. If metal NCs with high electronegativity are incorporated, the size of the NCs is reduced; hence, the operating current is reduced owing to the reduced density of the electric field around the metal NCs. Second, the potential wells are formed by the difference of work function between the metal NCs and active layer, and the barrier height of the potential wells affects the level of operating voltage as well as the conduction mechanism of metal NCs embedded memory cells. Therefore, by understanding these correlations between the active layer and embedded metal NCs, we can optimize the RS properties of metal NCs embedded memory cells as well as predict their conduction mechanisms.

  5. Memory Circuit Fault Simulator

    NASA Technical Reports Server (NTRS)

    Sheldon, Douglas J.; McClure, Tucker

    2013-01-01

    Spacecraft are known to experience significant memory part-related failures and problems, both pre- and postlaunch. These memory parts include both static and dynamic memories (SRAM and DRAM). These failures manifest themselves in a variety of ways, such as pattern-sensitive failures, timingsensitive failures, etc. Because of the mission critical nature memory devices play in spacecraft architecture and operation, understanding their failure modes is vital to successful mission operation. To support this need, a generic simulation tool that can model different data patterns in conjunction with variable write and read conditions was developed. This tool is a mathematical and graphical way to embed pattern, electrical, and physical information to perform what-if analysis as part of a root cause failure analysis effort.

  6. Set statistics in conductive bridge random access memory device with Cu/HfO{sub 2}/Pt structure

    SciTech Connect

    Zhang, Meiyun; Long, Shibing Wang, Guoming; Xu, Xiaoxin; Li, Yang; Liu, Qi; Lv, Hangbing; Liu, Ming; Lian, Xiaojuan; Miranda, Enrique; Suñé, Jordi

    2014-11-10

    The switching parameter variation of resistive switching memory is one of the most important challenges in its application. In this letter, we have studied the set statistics of conductive bridge random access memory with a Cu/HfO{sub 2}/Pt structure. The experimental distributions of the set parameters in several off resistance ranges are shown to nicely fit a Weibull model. The Weibull slopes of the set voltage and current increase and decrease logarithmically with off resistance, respectively. This experimental behavior is perfectly captured by a Monte Carlo simulator based on the cell-based set voltage statistics model and the Quantum Point Contact electron transport model. Our work provides indications for the improvement of the switching uniformity.

  7. Device modeling of ferroelectric memory field-effect transistor for the application of ferroelectric random access memory.

    PubMed

    Lue, Hang-Ting; Wu, Chien-Jang; Tseng, Tseung-Yuen

    2003-01-01

    An improved theoretical analysis on the electrical characteristics of ferroelectric memory field-effect transistor (FeMFET) is given. First, we propose a new analytical expression for the polarization versus electric field (P-E) for the ferroelectric material. It is determined by one parameter and explicitly includes both the saturated and nonsaturated hysteresis loops. Using this expression, we then examine the operational properties for two practical devices such as the metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) and metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) as well. A double integral also has been used, in order to include the possible effects due to the nonuniform field and charge distribution along the channel of the device, to calculate the drain current of FeMFET. By using the relevant material parameters close to the (Bi, La)4Ti3O12 (BLT) system, accurate analyses on the capacitors and FeMFET's at various applied biases are made. We also address the issues of depolarization field and retention time about such a device. PMID:12578132

  8. Stream specificity and asymmetries in feature binding and content-addressable access in visual encoding and memory.

    PubMed

    Huynh, Duong L; Tripathy, Srimant P; Bedell, Harold E; Ögmen, Haluk

    2015-01-01

    Human memory is content addressable-i.e., contents of the memory can be accessed using partial information about the bound features of a stored item. In this study, we used a cross-feature cuing technique to examine how the human visual system encodes, binds, and retains information about multiple stimulus features within a set of moving objects. We sought to characterize the roles of three different features (position, color, and direction of motion, the latter two of which are processed preferentially within the ventral and dorsal visual streams, respectively) in the construction and maintenance of object representations. We investigated the extent to which these features are bound together across the following processing stages: during stimulus encoding, sensory (iconic) memory, and visual short-term memory. Whereas all features examined here can serve as cues for addressing content, their effectiveness shows asymmetries and varies according to cue-report pairings and the stage of information processing and storage. Position-based indexing theories predict that position should be more effective as a cue compared to other features. While we found a privileged role for position as a cue at the stimulus-encoding stage, position was not the privileged cue at the sensory and visual short-term memory stages. Instead, the pattern that emerged from our findings is one that mirrors the parallel processing streams in the visual system. This stream-specific binding and cuing effectiveness manifests itself in all three stages of information processing examined here. Finally, we find that the Leaky Flask model proposed in our previous study is applicable to all three features. PMID:26382005

  9. Asymmetric dual-gate-structured one-transistor dynamic random access memory cells for retention characteristics improvement

    NASA Astrophysics Data System (ADS)

    Kim, Hyungjin; Lee, Jong-Ho; Park, Byung-Gook

    2016-08-01

    One of the major concerns of one-transistor dynamic random access memory (1T-DRAM) is poor retention time. In this letter, a 1T-DRAM cell with two separated asymmetric gates was fabricated and evaluated to improve sensing margin and retention characteristics. It was observed that significantly enhanced sensing margin and retention time over 1 s were obtained using a negatively biased second gate and trapped electrons in the nitride layer because of increased hole capacity in the floating body. These findings indicate that the proposed device could serve as a promising candidate for overcoming retention issues of 1T-DRAM cells.

  10. Suppression of relaxation effect in HfO2 resistive random access memory array by improved program operations

    NASA Astrophysics Data System (ADS)

    Wang, Chen; Wu, Huaqiang; Gao, Bin; Dai, Lingjun; Deng, Ning; Sekar, Deepak; Lu, Zhichao; Kellam, Mark; Bronner, Gary; Qian, He

    2016-05-01

    As a postprograming resistance shift, the relaxation effect could be a major issue for resistive random access memory (RRAM) applications. To understand the physical mechanisms of the relaxation effect, temperature-related ion and charge movements are analyzed using the incremental-step-pulse program (ISPP) and repeat-cycle program (RCP). Pre-electron detrapping (PED) operation is found to minimize the amount of interfacial trapped charges and thus to greatly reduce the resistance relaxation effect. Our experimental results demonstrate the improved data retention and tight distribution of RRAM arrays as a result of the above optimized program operations.

  11. High-Performance Pattern Placement Metrology on Dynamic Random Access Memory Layers of 0.25 μm Technology

    NASA Astrophysics Data System (ADS)

    Trube, Jutta; Huber, Hans-Ludwig; Bangert, Carola Bläsing-; Rinn, Klaus; Röth, Klaus-Dieter

    1993-12-01

    Pattern placement metrology is a key function in the evaluation of new manufacturing technology and processes. For future dynamic random access memory (DRAM) generations, ground rules of less than 0.25 μm must be achieved. This paper presents the results of an investigation of the Leitz LMS 2020 laser metrology system from Leica for pattern placement metrology for different layers of DRAM and X-ray mask fabrication processes. The results demonstrate clearly that the new Leitz LMS 2020 tool is well suited for pattern placement control of typical CMOS process wafers and X-ray masks with 30 nm accuracy.

  12. Towards scalable parellelism in Monte Carlo particle transport codes using remote memory access

    SciTech Connect

    Romano, Paul K; Brown, Forrest B; Forget, Benoit

    2010-01-01

    One forthcoming challenge in the area of high-performance computing is having the ability to run large-scale problems while coping with less memory per compute node. In this work, they investigate a novel data decomposition method that would allow Monte Carlo transport calculations to be performed on systems with limited memory per compute node. In this method, each compute node remotely retrieves a small set of geometry and cross-section data as needed and remotely accumulates local tallies when crossing the boundary of the local spatial domain. initial results demonstrate that while the method does allow large problems to be run in a memory-limited environment, achieving scalability may be difficult due to inefficiencies in the current implementation of RMA operations.

  13. Memories.

    ERIC Educational Resources Information Center

    Brand, Judith, Ed.

    1998-01-01

    This theme issue of the journal "Exploring" covers the topic of "memories" and describes an exhibition at San Francisco's Exploratorium that ran from May 22, 1998 through January 1999 and that contained over 40 hands-on exhibits, demonstrations, artworks, images, sounds, smells, and tastes that demonstrated and depicted the biological,…

  14. The Aviation Careers Accessibility Program (ACAP) at Florida Memorial College. Final Report.

    ERIC Educational Resources Information Center

    Florida Memorial Coll., Miami.

    This project, referred to as the Aviation Careers Accessibility Program (ACAP) established a model program for inner-city minority high school students that would allow them information and accessibility to careers and opportunities in the aviation industry. The project featured two program components: an academic year component during and a 5- or…

  15. Realization of a reversible switching in TaO{sub 2} polymorphs via Peierls distortion for resistance random access memory

    SciTech Connect

    Zhu, Linggang; Sun, Zhimei; Zhou, Jian; Guo, Zhonglu

    2015-03-02

    Transition-metal-oxide based resistance random access memory (RRAM) is a promising candidate for next-generation universal non-volatile memories. Searching and designing appropriate materials used in the memories becomes an urgent task. Here, a structure with the TaO{sub 2} formula was predicted using evolutionary algorithms in combination with first-principles calculations. This triclinic structure (T-TaO{sub 2}) is both energetically and dynamically more favorable than the commonly believed rutile structure (R-TaO{sub 2}). The metal-insulator transition (MIT) between metallic R-TaO{sub 2} and T-TaO{sub 2} (band gap: 1.0 eV) is via a Peierls distortion, which makes TaO{sub 2} a potential candidate for RRAM. The energy barrier for the reversible phase transition is 0.19 eV/atom and 0.23 eV/atom, respectively, suggesting low power consumption for the resistance switch. The present findings about the MIT as the resistance-switch mechanism in Ta-O system will stimulate experimental work to fabricate tantalum oxides based RRAM.

  16. Magnetoelectric assisted 180° magnetization switching for electric field addressable writing in magnetoresistive random-access memory.

    PubMed

    Wang, Zhiguang; Zhang, Yue; Wang, Yaojin; Li, Yanxi; Luo, Haosu; Li, Jiefang; Viehland, Dwight

    2014-08-26

    Magnetization-based memories, e.g., hard drive and magnetoresistive random-access memory (MRAM), use bistable magnetic domains in patterned nanomagnets for information recording. Electric field (E) tunable magnetic anisotropy can lower the energy barrier between two distinct magnetic states, promising reduced power consumption and increased recording density. However, integration of magnetoelectric heterostructure into MRAM is a highly challenging task owing to the particular architecture requirements of each component. Here, we show an epitaxial growth of self-assembled CoFe2O4 nanostripes with bistable in-plane magnetizations on Pb(Mg,Nb)O3-PbTiO3 (PMN-PT) substrates, where the magnetic switching can be triggered by E-induced elastic strain effect. An unprecedented magnetic coercive field change of up to 600 Oe was observed with increasing E. A near 180° magnetization rotation can be activated by E in the vicinity of the magnetic coercive field. These findings might help to solve the 1/2-selection problem in traditional MRAM by providing reduced magnetic coercive field in E field selected memory cells. PMID:25093903

  17. Perpendicular spin transfer torque magnetic random access memories with high spin torque efficiency and thermal stability for embedded applications (invited)

    NASA Astrophysics Data System (ADS)

    Thomas, Luc; Jan, Guenole; Zhu, Jian; Liu, Huanlong; Lee, Yuan-Jen; Le, Son; Tong, Ru-Ying; Pi, Keyu; Wang, Yu-Jen; Shen, Dongna; He, Renren; Haq, Jesmin; Teng, Jeffrey; Lam, Vinh; Huang, Kenlin; Zhong, Tom; Torng, Terry; Wang, Po-Kang

    2014-05-01

    Magnetic random access memories based on the spin transfer torque phenomenon (STT-MRAMs) have become one of the leading candidates for next generation memory applications. Among the many attractive features of this technology are its potential for high speed and endurance, read signal margin, low power consumption, scalability, and non-volatility. In this paper, we discuss our recent results on perpendicular STT-MRAM stack designs that show STT efficiency higher than 5 kBT/μA, energy barriers higher than 100 kBT at room temperature for sub-40 nm diameter devices, and tunnel magnetoresistance higher than 150%. We use both single device data and results from 8 Mb array to demonstrate data retention sufficient for automotive applications. Moreover, we also demonstrate for the first time thermal stability up to 400 °C exceeding the requirement of Si CMOS back-end processing, thus opening the realm of non-volatile embedded memory to STT-MRAM technology.

  18. The role of the local chemical environment of Ag on the resistive switching mechanism of conductive bridging random access memories.

    PubMed

    Souchier, E; D'Acapito, F; Noé, P; Blaise, P; Bernard, M; Jousseaume, V

    2015-10-01

    Conductive bridging random access memories (CBRAMs) are one of the most promising emerging technologies for the next generation of non-volatile memory. However, the lack of understanding of the switching mechanism at the nanoscale level prevents successful transfer to industry. In this paper, Ag/GeSx/W CBRAM devices are analyzed using depth selective X-ray Absorption Spectroscopy before and after switching. The study of the local environment around Ag atoms in such devices reveals that Ag is in two very distinct environments with short Ag-S bonds due to Ag dissolved in the GeSx matrix, and longer Ag-Ag bonds related to an Ag metallic phase. These experiments allow the conclusion that the switching process involves the formation of metallic Ag nano-filaments initiated at the Ag electrode. All these experimental features are well supported by ab initio molecular dynamics simulations showing that Ag favorably bonds to S atoms, and permit the proposal of a model at the microscopic level that can explain the instability of the conductive state in these Ag-GeSx CBRAM devices. Finally, the principle of the nondestructive method described here can be extended to other types of resistive memory concepts. PMID:26312954

  19. Perpendicular spin transfer torque magnetic random access memories with high spin torque efficiency and thermal stability for embedded applications (invited)

    SciTech Connect

    Thomas, Luc Jan, Guenole; Zhu, Jian; Liu, Huanlong; Lee, Yuan-Jen; Le, Son; Tong, Ru-Ying; Pi, Keyu; Wang, Yu-Jen; Shen, Dongna; He, Renren; Haq, Jesmin; Teng, Jeffrey; Lam, Vinh; Huang, Kenlin; Zhong, Tom; Torng, Terry; Wang, Po-Kang

    2014-05-07

    Magnetic random access memories based on the spin transfer torque phenomenon (STT-MRAMs) have become one of the leading candidates for next generation memory applications. Among the many attractive features of this technology are its potential for high speed and endurance, read signal margin, low power consumption, scalability, and non-volatility. In this paper, we discuss our recent results on perpendicular STT-MRAM stack designs that show STT efficiency higher than 5 k{sub B}T/μA, energy barriers higher than 100 k{sub B}T at room temperature for sub-40 nm diameter devices, and tunnel magnetoresistance higher than 150%. We use both single device data and results from 8 Mb array to demonstrate data retention sufficient for automotive applications. Moreover, we also demonstrate for the first time thermal stability up to 400 °C exceeding the requirement of Si CMOS back-end processing, thus opening the realm of non-volatile embedded memory to STT-MRAM technology.

  20. Realization of a reversible switching in TaO2 polymorphs via Peierls distortion for resistance random access memory

    NASA Astrophysics Data System (ADS)

    Zhu, Linggang; Zhou, Jian; Guo, Zhonglu; Sun, Zhimei

    2015-03-01

    Transition-metal-oxide based resistance random access memory (RRAM) is a promising candidate for next-generation universal non-volatile memories. Searching and designing appropriate materials used in the memories becomes an urgent task. Here, a structure with the TaO2 formula was predicted using evolutionary algorithms in combination with first-principles calculations. This triclinic structure (T-TaO2) is both energetically and dynamically more favorable than the commonly believed rutile structure (R-TaO2). The metal-insulator transition (MIT) between metallic R-TaO2 and T-TaO2 (band gap: 1.0 eV) is via a Peierls distortion, which makes TaO2 a potential candidate for RRAM. The energy barrier for the reversible phase transition is 0.19 eV/atom and 0.23 eV/atom, respectively, suggesting low power consumption for the resistance switch. The present findings about the MIT as the resistance-switch mechanism in Ta-O system will stimulate experimental work to fabricate tantalum oxides based RRAM.

  1. In situ observation of nickel as an oxidizable electrode material for the solid-electrolyte-based resistive random access memory

    SciTech Connect

    Sun, Jun; Wu, Xing; Xu, Feng; Xu, Tao; Sun, Litao; Liu, Qi; Xie, Hongwei; Long, Shibing; Lv, Hangbing; Li, Yingtao; Liu, Ming

    2013-02-04

    In this letter, we dynamically investigate the resistive switching characteristics and physical mechanism of the Ni/ZrO{sub 2}/Pt device. The device shows stable bipolar resistive switching behaviors after forming process, which is similar to the Ag/ZrO{sub 2}/Pt and Cu/ZrO{sub 2}/Pt devices. Using in situ transmission electron microscopy, we observe in real time that several conductive filaments are formed across the ZrO{sub 2} layer between Ni and Pt electrodes after forming. Energy-dispersive X-ray spectroscopy results confirm that Ni is the main composition of the conductive filaments. The ON-state resistance increases with increasing temperature, exhibiting the feature of metallic conduction. In addition, the calculated resistance temperature coefficient is equal to that of the 10-30 nm diameter Ni nanowire, further indicating that the nanoscale Ni conductive bridge is the physical origin of the observed conductive filaments. The resistive switching characteristics and the conductive filament's component of Ni/ZrO{sub 2}/Pt device are consistent with the characteristics of the typical solid-electrolyte-based resistive random access memory. Therefore, aside from Cu and Ag, Ni can also be used as an oxidizable electrode material for resistive random access memory applications.

  2. [Co/Ni]-CoFeB hybrid free layer stack materials for high density magnetic random access memory applications

    NASA Astrophysics Data System (ADS)

    Liu, E.; Swerts, J.; Couet, S.; Mertens, S.; Tomczak, Y.; Lin, T.; Spampinato, V.; Franquet, A.; Van Elshocht, S.; Kar, G.; Furnemont, A.; De Boeck, J.

    2016-03-01

    Alternative free layer materials with high perpendicular anisotropy are researched to provide spin-transfer-torque magnetic random access memory stacks' sufficient thermal stability at critical dimensions of 20 nm and below. We demonstrate a high tunnel magetoresistance (TMR) MgO-based magnetic tunnel junction stack with a hybrid free layer design made of a [Co/Ni] multilayer and CoFeB. The seed material on which the [Co/Ni] multilayer is deposited determines its switching characteristics. When deposited on a Pt seed layer, soft magnetic switching behavior with high squareness is obtained. When deposited on a NiCr seed, the perpendicular anisotropy remains high, but the squareness is low and coercivity exceeds 1000 Oe. Interdiffusion of the seed material with the [Co/Ni] multilayers is found to be responsible for the different switching characteristics. In optimized stacks, a TMR of 165% and low resistance-area (RA) product of 7.0 Ω μm2 are attained for free layers with an effective perpendicular magnetic anisotropy energy of 1.25 erg/cm2, which suggests that the hybrid free layer materials may be a viable candidate for high density magnetic random access memory applications.

  3. Hyperlink Format, Categorization Abilities and Memory Span as Contributors to Deaf Users Hypertext Access

    ERIC Educational Resources Information Center

    Farjardo, Inmaculada; Arfe, Barbara; Benedetti, Patrizia; Altoe, Gianmarco

    2008-01-01

    Sixty deaf and hearing students were asked to search for goods in a Hypertext Supermarket with either graphical or textual links of high typicality, frequency, and familiarity. Additionally, they performed a picture and word categorization task and two working memory span tasks (spatial and verbal). Results showed that deaf students were faster in…

  4. Respecting Relations: Memory Access and Antecedent Retrieval in Incremental Sentence Processing

    ERIC Educational Resources Information Center

    Kush, Dave W.

    2013-01-01

    This dissertation uses the processing of anaphoric relations to probe how linguistic information is encoded in and retrieved from memory during real-time sentence comprehension. More specifically, the dissertation attempts to resolve a tension between the demands of a linguistic processor implemented in a general-purpose cognitive architecture and…

  5. Cost-effective, transfer-free, flexible resistive random access memory using laser-scribed reduced graphene oxide patterning technology.

    PubMed

    Tian, He; Chen, Hong-Yu; Ren, Tian-Ling; Li, Cheng; Xue, Qing-Tang; Mohammad, Mohammad Ali; Wu, Can; Yang, Yi; Wong, H-S Philip

    2014-06-11

    Laser scribing is an attractive reduced graphene oxide (rGO) growth and patterning technology because the process is low-cost, time-efficient, transfer-free, and flexible. Various laser-scribed rGO (LSG) components such as capacitors, gas sensors, and strain sensors have been demonstrated. However, obstacles remain toward practical application of the technology where all the components of a system are fabricated using laser scribing. Memory components, if developed, will substantially broaden the application space of low-cost, flexible electronic systems. For the first time, a low-cost approach to fabricate resistive random access memory (ReRAM) using laser-scribed rGO as the bottom electrode is experimentally demonstrated. The one-step laser scribing technology allows transfer-free rGO synthesis directly on flexible substrates or non-flat substrates. Using this time-efficient laser-scribing technology, the patterning of a memory-array area up to 100 cm(2) can be completed in 25 min. Without requiring the photoresist coating for lithography, the surface of patterned rGO remains as clean as its pristine state. Ag/HfOx/LSG ReRAM using laser-scribing technology is fabricated in this work. Comprehensive electrical characteristics are presented including forming-free behavior, stable switching, reasonable reliability performance and potential for 2-bit storage per memory cell. The results suggest that laser-scribing technology can potentially produce more cost-effective and time-effective rGO-based circuits and systems for practical applications. PMID:24801736

  6. Electron-induced single event upsets in 28 nm and 45 nm bulk SRAMs

    DOE PAGESBeta

    Trippe, J. M.; Reed, R. A.; Austin, R. A.; Sierawski, B. D.; Weller, R. A.; Funkhouser, E. D.; King, M. P.; Narasimham, B.; Bartz, B.; Baumann, R.; et al

    2015-12-01

    In this study, we present experimental evidence of single electron-induced upsets in commercial 28 nm and 45 nm CMOS SRAMs from a monoenergetic electron beam. Upsets were observed in both technology nodes when the SRAM was operated in a low power state. The experimental cross section depends strongly on both bias and technology node feature size, consistent with previous work in which SRAMs were irradiated with low energy muons and protons. Accompanying simulations demonstrate that δ-rays produced by the primary electrons are responsible for the observed upsets. Additional simulations predict the on-orbit event rates for various Earth and Jovian environmentsmore » for a set of sensitive volumes representative of current technology nodes. The electron contribution to the total upset rate for Earth environments is significant for critical charges as high as 0.2 fC. This value is comparable to that of sub-22 nm bulk SRAMs. Similarly, for the Jovian environment, the electron-induced upset rate is larger than the proton-induced upset rate for critical charges as high as 0.3 fC.« less

  7. P-well or N-well CMOS technology for advanced SEU-hard SRAMs

    SciTech Connect

    Fu, J.S.

    1988-01-01

    The decoupling resistances required for SEU hardening CMOS SRAMs of the 2..mu..m p-well and n-well technologies are compared. An advanced device-plus-circuit simulator has been used to illuminate the underpinings of why one technology is intrinsically more SEU tolerant than the other. 3 refs., 5 figs.

  8. Electron-induced single event upsets in 28 nm and 45 nm bulk SRAMs

    SciTech Connect

    Trippe, J. M.; Reed, R. A.; Austin, R. A.; Sierawski, B. D.; Weller, R. A.; Funkhouser, E. D.; King, M. P.; Narasimham, B.; Bartz, B.; Baumann, R.; Schrimpf, R. D.; Labello, R.; Nichols, J.; Weeden-Wright, S. L.

    2015-12-01

    In this study, we present experimental evidence of single electron-induced upsets in commercial 28 nm and 45 nm CMOS SRAMs from a monoenergetic electron beam. Upsets were observed in both technology nodes when the SRAM was operated in a low power state. The experimental cross section depends strongly on both bias and technology node feature size, consistent with previous work in which SRAMs were irradiated with low energy muons and protons. Accompanying simulations demonstrate that δ-rays produced by the primary electrons are responsible for the observed upsets. Additional simulations predict the on-orbit event rates for various Earth and Jovian environments for a set of sensitive volumes representative of current technology nodes. The electron contribution to the total upset rate for Earth environments is significant for critical charges as high as 0.2 fC. This value is comparable to that of sub-22 nm bulk SRAMs. Similarly, for the Jovian environment, the electron-induced upset rate is larger than the proton-induced upset rate for critical charges as high as 0.3 fC.

  9. A 320 mV, 6 kb subthreshold 10T SRAM employing voltage lowering techniques

    NASA Astrophysics Data System (ADS)

    Jiangzheng, Cai; Sumin, Zhang; Jia, Yuan; Xinchao, Shang; Liming, Chen; Yong, Hei

    2015-06-01

    This paper presents a 6 kb SRAM that uses a novel 10T cell to achieve a minimum operating voltage of 320 mV in a 130 nm CMOS process. A number of low power circuit techniques are included to enable the proposed SRAM to operate in the subthreshold region. The reverse short channel effect and the reverse narrow channel effect are utilized to improve the performance of the SRAM. A novel subthreshold pulse generation circuit produces an ideal pulse to make read operation stable. A floating write bit-line effectively reduces the standby leakage consumption. Finally, a short read bit-line makes the read operation fast and energy-saving. Measurements indicate that these techniques are effective, the SRAM can operate at 800 kHz and consume 1.94 μW at its lowest voltage (320 mV). Project supported by the National Natural Science Foundation of China (No. 61306039) and the Next Generation of Information Technology for Sensing China (No. XDA06020401).

  10. Integration of Radiation-Hard Magnetic Random Access Memory with CMOS ICs

    SciTech Connect

    Cerjan, C.J.; Sigmon, T.W.

    2000-02-15

    The research undertaken in this LDRD-funded project addressed the joint development of magnetic material-based nonvolatile, radiation-hard memory cells with Sandia National Laboratory. Specifically, the goal of this project was to demonstrate the intrinsic radiation-hardness of Giant Magneto-Resistive (GMR) materials by depositing representative alloy combinations upon radiation-hardened silicon-based integrated circuits. All of the stated goals of the project were achieved successfully. The necessary films were successfully deposited upon typical integrated circuits; the materials retained their magnetic field response at the highest radiation doses; and a patterning approach was developed that did not degrade the as-fabricated properties of the underlying circuitry. These results establish the feasibility of building radiation-hard magnetic memory cells.

  11. Observations of single-event upsets in non-hardened high-density SRAMs in sun-synchronous orbit

    NASA Astrophysics Data System (ADS)

    Underwood, C. I.; Ward, J. W.; Dyer, C. S.; Sims, A. J.

    1992-12-01

    Observations of single-event upset (SEU) activity in nonhardened static and dynamic RAMs of both low (16-kb) and high (256-kb, 1-Mb), density are presented for a family of small spacecraft in low-earth, near-polar, sun-synchronous orbits. The observation of single-event multiple-bit upset (MBU) in these devices is discussed, and the implications of such events for error-protection coding schemes are examined. Contrary to expectations, the 1-Mb static RAMs (SRAMs) are more resilient to SEU than the 246-kb SRAMs, and one type of commercial 1-Mb SRAM shows a particularly low error rate.

  12. On EMDR: eye movements during retrieval reduce subjective vividness and objective memory accessibility during future recall.

    PubMed

    van den Hout, Marcel A; Bartelski, Nicola; Engelhard, Iris M

    2013-01-01

    In eye movement desensitization and reprocessing (EMDR), a treatment for post-traumatic stress disorder (PTSD), patients make eye movements (EM) during trauma recall. Earlier experimental studies found that EM during recall reduces memory vividness during future recalls, and this was taken as laboratory support for the underlying mechanism of EMDR. However, reduced vividness was assessed with self-reports that may be affected by demand characteristics. We tested whether recall+EM also reduces memory vividness on a behavioural reaction time (RT) task. Undergraduates (N=32) encoded two pictures, recalled them, and rated their vividness. In the EM group, one of the pictures was recalled again while making EM. In the no-EM group one of the pictures was recalled without EM. Then fragments from both the recalled and non-recalled pictures, and new fragments were presented and participants rated whether these were (or were not) seen before. Both pictures were rated again for vividness. In the EM group, self-rated vividness of the recalled+EM picture decreased, relative to the non-recalled picture. In the no-EM group there was no difference between the recalled versus non-recalled picture. The RT task showed the same pattern. Reduction of memory vividness due to recall+EM is also evident from non-self-report data. PMID:22765837

  13. An energy-efficient SIMD DSP with multiple VLIW configurations and an advanced memory access unit for LTE-A modem LSIs

    NASA Astrophysics Data System (ADS)

    Tomono, Mitsuru; Ito, Makiko; Nomura, Yoshitaka; Mouri, Makoto; Hirose, Yoshio

    2015-12-01

    Energy efficiency is the most important factor in the design of wireless modem LSIs for mobile handset systems. We have developed an energy-efficient SIMD DSP for LTE-A modem LSIs. Our DSP has mainly two hardware features in order to reduce energy consumption. The first one is multiple VLIW configurations to minimize accesses to instruction memories. The second one is an advanced memory access unit to realize complex memory accesses required for wireless baseband processing. With these features, performance of our DSP is about 1.7 times faster than a base DSP on average for standard LTE-A Libraries. Our DSP achieves about 20% improvement in energy efficiency compared to a base DSP for LTE-A modem LSIs.

  14. An Account of Performance in Accessing Information Stored in Long-Term Memory. A Fixed-Links Model Approach

    ERIC Educational Resources Information Center

    Altmeyer, Michael; Schweizer, Karl; Reiss, Siegbert; Ren, Xuezhu; Schreiner, Michael

    2013-01-01

    Performance in working memory and short-term memory tasks was employed for predicting performance in a long-term memory task in order to find out about the underlying processes. The types of memory were represented by versions of the Posner Task, the Backward Counting Task and the Sternberg Task serving as measures of long-term memory, working…

  15. Performance and characteristics of double layer porous silicon oxide resistance random access memory

    NASA Astrophysics Data System (ADS)

    Tsai, Tsung-Ming; Chang, Kuan-Chang; Zhang, Rui; Chang, Ting-Chang; Lou, J. C.; Chen, Jung-Hui; Young, Tai-Fa; Tseng, Bae-Heng; Shih, Chih-Cheng; Pan, Yin-Chih; Chen, Min-Chen; Pan, Jhih-Hong; Syu, Yong-En; Sze, Simon M.

    2013-06-01

    A bilayer resistive switching memory device with an inserted porous silicon oxide layer is investigated in this letter. Compared with single Zr:SiOx layer structure, Zr:SiOx/porous SiOx structure outperforms from various aspects, including low operating voltages, tighter distributions of set voltage, higher stability of both low resistance state and high resistance state, and satisfactory endurance characteristics. Electric field simulation by comsolTM Multiphysics is applied, which corroborates that intensive electric field around the pore in porous SiOx layer guides the conduction of electrons. The constraint of conduction path leads to better stabilization and prominent performance of bilayer resistive switching devices.

  16. An analog random access memory in the AVLSI-RA process for an interpolating pad chamber

    SciTech Connect

    Britton, C.L. Jr.; Wittenberg, A.L.; Read, K.F.; Clonts, L.G.; Kennedy, E.J.; Smith, R.S.; Swann, B.K.; Musser, J.A.

    1995-12-01

    An analog memory for an interpolating pad chamber has been designed at Oak Ridge National Laboratory and fabricated by Harris Semiconductor in the AVLSI-RA CMOS process. The goal was to develop a rad-hard analog pipeline that would deliver approximately 9-b performance, a readout settling time of 500 ns following read enable, an input and output dynamic range of {+-} 2.25 V, a corrected rms pedestal of approximately 5 mV or less, and a power dissipation of less than 10 mW/channel. The pre- and post-radiation measurements to 5 MRad are presented.

  17. 75 FR 16507 - In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-04-01

    ..., California (``Rambus''). 73 FR 75131-2. The complaint, as amended and supplemented, alleges violations of... Commission's action. See Presidential Memorandum of July 21, 2005, 70 FR 43251 (July 26, 2005). During this... COMMISSION In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access...

  18. Access to Attitude-Relevant Information in Memory as a Determinant of Attitude-Behavior Consistency.

    ERIC Educational Resources Information Center

    Kallgren, Carl A.; Wood, Wendy

    Recent reserach has attempted to determine systematically how attitudes influence behavior. This research examined whether access to attitude-relevant beliefs and prior experiences would mediate the relation between attitudes and behavior. Subjects were 49 college students with a mean age of 27 who did not live with their parents or in…

  19. Improving Memory after Interruption: Exploiting Soft Constraints and Manipulating Information Access Cost

    ERIC Educational Resources Information Center

    Morgan, Phillip L.; Patrick, John; Waldron, Samuel M.; King, Sophia L.; Patrick, Tanya

    2009-01-01

    Forgetting what one was doing prior to interruption is an everyday problem. The recent soft constraints hypothesis (Gray, Sims, Fu, & Schoelles, 2006) emphasizes the strategic adaptation of information processing strategy to the task environment. It predicts that increasing information access cost (IAC: the time, and physical and mental effort…

  20. A Symptom-Focused Hypnotic Approach to Accessing and Processing Previously Repressed/Dissociated Memories.

    ERIC Educational Resources Information Center

    Ratican, Kathleen L.

    1996-01-01

    The kinesthetic track back technique accesses the origins of current symptoms and may uncover previously repressed/dissociated material, if such material exists in the client's unconscious mind, is relevant to the symptoms, and is ready to be processed consciously. Case examples are given to illustrate proper use of this technique. (LSR)

  1. Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOEpatents

    Blocksome, Michael A.; Mamidala, Amith R.

    2015-07-07

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  2. Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOEpatents

    Blocksome, Michael A.; Mamidala, Amith R.

    2015-07-14

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  3. Reducing operation current of Ni-doped silicon oxide resistance random access memory by supercritical CO2 fluid treatment

    NASA Astrophysics Data System (ADS)

    Chang, Kuan-Chang; Tsai, Tsung-Ming; Chang, Ting-Chang; Syu, Yong-En; Wang, Chia-C.; Chuang, Siang-Lan; Li, Cheng-Hua; Gan, Der-Shin; Sze, Simon M.

    2011-12-01

    In the study, we reduced the operation current of resistance random access memory (RRAM) by supercritical CO2 (SCCO2) fluids treatment. The power consumption and joule heating degradation of RRAM device can be improved greatly by SCCO2 treatment. The defect of nickel-doped silicon oxide (Ni:SiOx) was passivated effectively by the supercritical fluid technology. The current conduction of high resistant state in post-treated Ni:SiOx film was transferred to Schottky emission from Frenkel-Pool due to the passivation effect. Additionally, we can demonstrate the passivation mechanism of SCCO2 for Ni:SiOx by material analyses of x-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy.

  4. Robust Two-Dimensional Stack Capacitor Technologies for 64 Mbit One-Transistor-One-Capacitor Ferroelectric Random Access Memory

    NASA Astrophysics Data System (ADS)

    Jung, Ju-Young; Joo, Heung-Jin; Park, Jung-Hoon; Kang, Seung-Kuk; Kim, Hwi-San; Choi, Do-Yeon; Kim, Jai-Hyun; Lee, Eun-Sun; Hong, Young-Ki; Kim, Hyun-Ho; Jung, Dong-Jin; Kang, Young-Min; Lee, Sung-Yung; Jeong, Hong-Sik; Kim, Kinam

    2007-04-01

    It is very important to develop capacitor module technologies such as robust Pb(ZrxTi1-x)O3 (PZT) film technology at nm scaled PZT thickness and damage minimized ferroelectric capacitor etching technology are crucial for the success of high density one-transistor-one-capacitor (1T1C) ferroelectric random access memory (FRAM). We resolved this issue from the change of the capacitor etching system and optimization of the PZT/SrRuO3 (SRO) deposition process. As a result, we realized a highly reliable sensing window for 64 Mbit 1T1C FRAM that were realized by novel technologies such as robust MOCVD PZT deposition technologies, optimized SRO electrode and damage minimized ferroelectric capacitor etching technologies.

  5. Glprof: A Gprof inspired, Callgraph-oriented Per-Object Disseminating Memory Access Multi-Cache Profiler

    SciTech Connect

    Janjusic, Tommy; Kartsaklis, Christos

    2015-01-01

    Application analysis is facilitated through a number of program profiling tools. The tools vary in their complexity, ease of deployment, design, and profiling detail. Specifically, understand- ing, analyzing, and optimizing is of particular importance for scientific applications where minor changes in code paths and data-structure layout can have profound effects. Understanding how intricate data-structures are accessed and how a given memory system responds is a complex task. In this paper we describe a trace profiling tool, Glprof, specifically aimed to lessen the burden of the programmer to pin-point heavily involved data-structures during an application's run-time, and understand data-structure run-time usage. Moreover, we showcase the tool's modularity using additional cache simulation components. We elaborate on the tool's design, and features. Finally we demonstrate the application of our tool in the context of Spec bench- marks using the Glprof profiler and two concurrently running cache simulators, PPC440 and AMD Interlagos.

  6. Oxide thickness dependence of resistive switching characteristics for Ni/HfOx/Pt resistive random access memory device

    NASA Astrophysics Data System (ADS)

    Ito, Daisuke; Hamada, Yoshihumi; Otsuka, Shintaro; Shimizu, Tomohiro; Shingubara, Shoso

    2015-06-01

    The switching process of the conductive filament formed in Ni/HfOx/Pt resistive random access memory (ReRAM) devices were studied. We evaluated the oxide thickness dependence and temperature dependence of voltage for the Forming, Set and Reset operations for HfOx layers whose thickness are between 3.3 and 6.5 nm. The resistance of conductive filaments showed typical metallic behavior, which suggests Ni filament formation in the HfOx layer. There is a clear dependence of switching voltages for the Set and Reset processes on oxide thickness, which implies that the formation and rupture of conductive filaments occur in the entire thickness range of the HfOx layer. This finding differs from that of a previous study by Yang, which suggests the existence of a constant-thickness switching region. It is suggested that the thickness of the switching region in HfOx may be larger than 6.5 nm.

  7. Guideline model for the bias-scheme-dependent power consumption of a resistive random access memory crossbar array

    NASA Astrophysics Data System (ADS)

    Sun, Wookyung; Choi, Sujin; Lim, Hyein; Shin, Hyungsoon

    2016-04-01

    The 1/2 and 1/3 bias schemes are commonly used to select a cell in a resistive random access memory (ReRAM) crossbar array. The 1/3 bias scheme is advantageous in terms of its write margin but typically requires a higher power consumption than the 1/2 bias scheme. The power consumption of ReRAM can vary according to the nonlinearity of the selector device. In this paper, we propose a power guideline model that suggests selector nonlinearity requirements to guarantee a lower power consumption for the 1/3 bias scheme than for the 1/2 bias scheme. Therefore, the selector nonlinearity requirements for the low power consumption of the 1/3 bias scheme can be immediately obtained using this guideline model without simulation.

  8. Temperature induced complementary switching in titanium oxide resistive random access memory

    NASA Astrophysics Data System (ADS)

    Panda, D.; Simanjuntak, F. M.; Tseng, T.-Y.

    2016-07-01

    On the way towards high memory density and computer performance, a considerable development in energy efficiency represents the foremost aspiration in future information technology. Complementary resistive switch consists of two antiserial resistive switching memory (RRAM) elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption. Here we present a titanium oxide based complementary RRAM (CRRAM) device with Pt top and TiN bottom electrode. A subsequent post metal annealing at 400°C induces CRRAM. Forming voltage of 4.3 V is required for this device to initiate switching process. The same device also exhibiting bipolar switching at lower compliance current, Ic <50 μA. The CRRAM device have high reliabilities. Formation of intermediate titanium oxi-nitride layer is confirmed from the cross-sectional HRTEM analysis. The origin of complementary switching mechanism have been discussed with AES, HRTEM analysis and schematic diagram. This paper provides valuable data along with analysis on the origin of CRRAM for the application in nanoscale devices.

  9. Impact of adolescent sucrose access on cognitive control, recognition memory, and parvalbumin immunoreactivity

    PubMed Central

    Killcross, Simon; Hambly, Luke D.; Morris, Margaret J.; Westbrook, R. Fred

    2015-01-01

    In this study we sought to determine the effect of daily sucrose consumption in young rats on their subsequent performance in tasks that involve the prefrontal cortex and hippocampus. High levels of sugar consumption have been associated with the development of obesity, however less is known about how sugar consumption influences behavioral control and high-order cognitive processes. Of particular concern is the fact that sugar intake is greatest in adolescence, an important neurodevelopmental period. We provided sucrose to rats when they were progressing through puberty and adolescence. Cognitive performance was assessed in adulthood on a task related to executive function, a rodent analog of the Stroop task. We found that sucrose-exposed rats failed to show context-appropriate responding during incongruent stimulus compounds presented at test, indicative of impairments in prefrontal cortex function. Sucrose exposed rats also showed deficits in an on object-in-place recognition memory task, indicating that both prefrontal and hippocampal function was impaired. Analysis of brains showed a reduction in expression of parvalbumin-immunoreactive GABAergic interneurons in the hippocampus and prefrontal cortex, indicating that sucrose consumption during adolescence induced long-term pathology, potentially underpinning the cognitive deficits observed. These results suggest that consumption of high levels of sugar-sweetened beverages by adolescents may also impair neurocognitive functions affecting decision-making and memory, potentially rendering them at risk for developing mental health disorders. PMID:25776039

  10. The structure-sensitivity of memory access: evidence from Mandarin Chinese

    PubMed Central

    Dillon, Brian; Chow, Wing-Yee; Wagers, Matthew; Guo, Taomei; Liu, Fengqin; Phillips, Colin

    2014-01-01

    The present study examined the processing of the Mandarin Chinese long-distance reflexive ziji to evaluate the role that syntactic structure plays in the memory retrieval operations that support sentence comprehension. Using the multiple-response speed-accuracy tradeoff (MR-SAT) paradigm, we measured the speed with which comprehenders retrieve an antecedent for ziji. Our experimental materials contrasted sentences where ziji's antecedent was in the local clause with sentences where ziji's antecedent was in a distant clause. Time course results from MR-SAT suggest that ziji dependencies with syntactically distant antecedents are slower to process than syntactically local dependencies. To aid in interpreting the SAT data, we present a formal model of the antecedent retrieval process, and derive quantitative predictions about the time course of antecedent retrieval. The modeling results support the Local Search hypothesis: during syntactic retrieval, comprehenders initially limit memory search to the local syntactic domain. We argue that Local Search hypothesis has important implications for theories of locality effects in sentence comprehension. In particular, our results suggest that not all locality effects may be reduced to the effects of temporal decay and retrieval interference. PMID:25309486

  11. Brain potentials reflect access to visual and emotional memories for faces.

    PubMed

    Bobes, Maria A; Quiñonez, Ileana; Perez, Jhoanna; Leon, Inmaculada; Valdés-Sosa, Mitchell

    2007-05-01

    Familiar faces convey different types of information, unlocking memories related to social-emotional significance. Here, the availability over time of different types of memory was evaluated using the time-course of P3 event related potentials. Two oddball paradigms were employed, both using unfamiliar faces as standards. The infrequent targets were, respectively, artificially-learned faces (devoid of social-emotional content) and faces of acquaintances. Although in both tasks targets were detected accurately, the corresponding time-course and scalp distribution of the P3 responses differed. Artificially-learned and acquaintance faces both elicited a P3b, maximal over centro-parietal sites, and a latency of 500ms. Faces of acquaintances elicited an additional component, an early P3 maximal over frontal sites: with a latency of 350ms. This suggests that visual familiarity can only trigger the overt recognition processes leading to the slower P3b, whereas emotional-social information can also elicit fast and automatic assessments (indexed by the frontal-P3) crucial for successful social interactions. PMID:17350154

  12. ERP evidence for hemispheric asymmetries in exemplar-specific explicit memory access.

    PubMed

    Küper, Kristina; Zimmer, Hubert D

    2015-11-01

    The right cerebral hemisphere (RH) appears to be more effective in representing visual objects as distinct exemplars than the left hemisphere (LH) which is presumably biased towards coding objects at the level of abstract prototypes. As of yet, relatively little is known about the role that asymmetries in exemplar-specificity play at the level of explicit memory retrieval. In the present study, we addressed this issue by examining hemispheric asymmetries in the putative event-related potential (ERP) correlates of familiarity (FN400) and recollection (LPC). In an incidental study phase, pictures of familiar objects were presented centrally. At test, participants performed a memory inclusion task on identical repetitions and different exemplars of study items as well as new items which were presented in only one visual hemifield using the divided visual field technique. With respect to familiarity, we observed exemplar-specific FN400 old/new effects that were more pronounced for identical repetitions than different exemplars, irrespective of the hemisphere governing initial stimulus processing. In contrast, LPC old/new effects were subject to some hemispheric asymmetries indicating that exemplar-specific recollection was more extensive in the RH than in the LH. This further corroborates the idea that hemispheric asymmetries should not be generalized but need to be distinguished not only in different domains but also at different levels of processing. PMID:26279112

  13. Thin Co/Ni-based bottom pinned spin-transfer torque magnetic random access memory stacks with high annealing tolerance

    NASA Astrophysics Data System (ADS)

    Tomczak, Y.; Swerts, J.; Mertens, S.; Lin, T.; Couet, S.; Liu, E.; Sankaran, K.; Pourtois, G.; Kim, W.; Souriau, L.; Van Elshocht, S.; Kar, G.; Furnemont, A.

    2016-01-01

    Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as a replacement for next generation embedded and stand-alone memory applications. One of the main challenges in the STT-MRAM stack development is the compatibility of the stack with CMOS process flows in which thermal budgets up to 400 °C are applied. In this letter, we report on a perpendicularly magnetized MgO-based tunnel junction (p-MTJ) on a thin Co/Ni perpendicular synthetic antiferromagnetic layer with high annealing tolerance. Tunnel magneto resistance (TMR) loss after annealing occurs when the reference layer loses its perpendicular magnetic anisotropy due to reduction of the CoFeB/MgO interfacial anisotropy. A stable Co/Ni based p-MTJ stack with TMR values of 130% at resistance-area products of 9 Ω μm2 after 400 °C anneal is achieved via moment control of the Co/Ta/CoFeB reference layer. Thinning of the CoFeB polarizing layer down to 0.8 nm is the key enabler to achieve 400 °C compatibility with limited TMR loss. Thinning the Co below 0.6 nm leads to a loss of the antiferromagnetic interlayer exchange coupling strength through Ru. Insight into the thickness and moment engineering of the reference layer is displayed to obtain the best magnetic properties and high thermal stability for thin Co/Ni SAF-based STT-MRAM stacks.

  14. Evolution of conductive filament and its impact on reliability issues in oxide-electrolyte based resistive random access memory

    PubMed Central

    Lv, Hangbing; Xu, Xiaoxin; Liu, Hongtao; Liu, Ruoyu; Liu, Qi; Banerjee, Writam; Sun, Haitao; Long, Shibing; Li, Ling; Liu, Ming

    2015-01-01

    The electrochemical metallization cell, also referred to as conductive bridge random access memory, is considered to be a promising candidate or complementary component to the traditional charge based memory. As such, it is receiving additional focus to accelerate the commercialization process. To create a successful mass product, reliability issues must first be rigorously solved. In-depth understanding of the failure behavior of the ECM is essential for performance optimization. Here, we reveal the degradation of high resistance state behaves as the majority cases of the endurance failure of the HfO2 electrolyte based ECM cell. High resolution transmission electron microscopy was used to characterize the change in filament nature after repetitive switching cycles. The result showed that Cu accumulation inside the filament played a dominant role in switching failure, which was further supported by measuring the retention of cycle dependent high resistance state and low resistance state. The clarified physical picture of filament evolution provides a basic understanding of the mechanisms of endurance and retention failure, and the relationship between them. Based on these results, applicable approaches for performance optimization can be implicatively developed, ranging from material tailoring to structure engineering and algorithm design. PMID:25586207

  15. Evolution of conductive filament and its impact on reliability issues in oxide-electrolyte based resistive random access memory.

    PubMed

    Lv, Hangbing; Xu, Xiaoxin; Liu, Hongtao; Liu, Ruoyu; Liu, Qi; Banerjee, Writam; Sun, Haitao; Long, Shibing; Li, Ling; Liu, Ming

    2015-01-01

    The electrochemical metallization cell, also referred to as conductive bridge random access memory, is considered to be a promising candidate or complementary component to the traditional charge based memory. As such, it is receiving additional focus to accelerate the commercialization process. To create a successful mass product, reliability issues must first be rigorously solved. In-depth understanding of the failure behavior of the ECM is essential for performance optimization. Here, we reveal the degradation of high resistance state behaves as the majority cases of the endurance failure of the HfO2 electrolyte based ECM cell. High resolution transmission electron microscopy was used to characterize the change in filament nature after repetitive switching cycles. The result showed that Cu accumulation inside the filament played a dominant role in switching failure, which was further supported by measuring the retention of cycle dependent high resistance state and low resistance state. The clarified physical picture of filament evolution provides a basic understanding of the mechanisms of endurance and retention failure, and the relationship between them. Based on these results, applicable approaches for performance optimization can be implicatively developed, ranging from material tailoring to structure engineering and algorithm design. PMID:25586207

  16. High performance of graphene oxide-doped silicon oxide-based resistance random access memory

    PubMed Central

    2013-01-01

    In this letter, a double active layer (Zr:SiO x /C:SiO x ) resistive switching memory device with outstanding performance is presented. Through current fitting, hopping conduction mechanism is found in both high-resistance state (HRS) and low-resistance state (LRS) of double active layer RRAM devices. By analyzing Raman and FTIR spectra, we observed that graphene oxide exists in C:SiO x layer. Compared with single Zr:SiO x layer structure, Zr:SiO x /C:SiO x structure has superior performance, including low operating current, improved uniformity in both set and reset processes, and satisfactory endurance characteristics, all of which are attributed to the double-layer structure and the existence of graphene oxide flakes formed by the sputter process. PMID:24261454

  17. The role of the inserted layer in resistive random access memory device

    NASA Astrophysics Data System (ADS)

    Zhang, Dainan; Ma, Guokun; Zhang, Huaiwu; Tang, Xiaoli; Zhong, Zhiyong; Jie, Li; Su, Hua

    2016-07-01

    NiO resistive switching devices were fabricated by reactive DC magnetron sputtering at room temperature containing different inserted layers. From measurements, we demonstrated the filaments were made up by metal Co rather than the oxygen defect or other metal. A current jumping phenomenon in the SET process was observed, evidencing that the filament generating procedure was changed due to the inserted layers. In this process, we demonstrate the current jumping appeared in higher voltage region when the position of inserted layer was close to the bottom electrode. The I–V curves shifted to the positive direction as the thickness of inserted layer increasing. With the change of the number of inserted layers, SET voltages varied while the RESET voltage kept stable. According to the electrochemical metallization memory mechanism, detailed explanations on all the phenomena were addressed. This discovery is supposed of great potentials in the use of designing multi-layer RRAM devices.

  18. High performance of graphene oxide-doped silicon oxide-based resistance random access memory.

    PubMed

    Zhang, Rui; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Chen, Kai-Huang; Lou, Jen-Chung; Chen, Jung-Hui; Young, Tai-Fa; Shih, Chih-Cheng; Yang, Ya-Liang; Pan, Yin-Chih; Chu, Tian-Jian; Huang, Syuan-Yong; Pan, Chih-Hung; Su, Yu-Ting; Syu, Yong-En; Sze, Simon M

    2013-01-01

    In this letter, a double active layer (Zr:SiOx/C:SiOx) resistive switching memory device with outstanding performance is presented. Through current fitting, hopping conduction mechanism is found in both high-resistance state (HRS) and low-resistance state (LRS) of double active layer RRAM devices. By analyzing Raman and FTIR spectra, we observed that graphene oxide exists in C:SiOx layer. Compared with single Zr:SiOx layer structure, Zr:SiOx/C:SiOx structure has superior performance, including low operating current, improved uniformity in both set and reset processes, and satisfactory endurance characteristics, all of which are attributed to the double-layer structure and the existence of graphene oxide flakes formed by the sputter process. PMID:24261454

  19. Access to long-term optical memories using photon echoes retrieved from semiconductor spins

    NASA Astrophysics Data System (ADS)

    Langer, L.; Poltavtsev, S. V.; Yugova, I. A.; Salewski, M.; Yakovlev, D. R.; Karczewski, G.; Wojtowicz, T.; Akimov, I. A.; Bayer, M.

    2014-11-01

    The ability to store optical information is important for both classical and quantum communication. Achieving this in a comprehensive manner (converting the optical field into material excitation, storing this excitation, and releasing it after a controllable time delay) is greatly complicated by the many, often conflicting, properties of the material. More specifically, optical resonances in semiconductor quantum structures with high oscillator strength are inevitably characterized by short excitation lifetimes (and, therefore, short optical memory). Here, we present a new experimental approach to stimulated photon echoes by transferring the information contained in the optical field into a spin system, where it is decoupled from the optical vacuum field and may persist much longer. We demonstrate this for an n-doped CdTe/(Cd,Mg)Te quantum well, the storage time of which could be increased by more than three orders of magnitude, from the picosecond range up to tens of nanoseconds.

  20. Distribution of nanoscale nuclei in the amorphous dome of a phase change random access memory

    SciTech Connect

    Lee, Bong-Sub Darmawikarta, Kristof; Abelson, John R.; Raoux, Simone; Shih, Yen-Hao; Zhu, Yu

    2014-02-17

    The nanoscale crystal nuclei in an amorphous Ge{sub 2}Sb{sub 2}Te{sub 5} bit in a phase change memory device were evaluated by fluctuation transmission electron microscopy. The quench time in the device (∼10 ns) afforded more and larger nuclei in the melt-quenched state than in the as-deposited state. However, nuclei were even more numerous and larger in a test structure with a longer quench time (∼100 ns), verifying the prediction of nucleation theory that slower cooling produces more nuclei. It also demonstrates that the thermal design of devices will strongly influence the population of nuclei, and thus the speed and data retention characteristics.

  1. Highly reliable switching via phase transition using hydrogen peroxide in homogeneous and multi-layered GaZnO(x)-based resistive random access memory devices.

    PubMed

    Park, Sung Pyo; Yoon, Doo Hyun; Tak, Young Jun; Lee, Heesoo; Kim, Hyun Jae

    2015-06-01

    Here, we propose an effective method for improving the resistive switching characteristics of solution-processed gallium-doped zinc oxide (GaZnO(x)) resistive random access memory (RRAM) devices using hydrogen peroxide. Our results imply that solution processed GaZnO(x) RRAM devices could be one of the candidates for the development of low cost RRAM. PMID:25947353

  2. Hybrid inverse lithography techniques for advanced hierarchical memories

    NASA Astrophysics Data System (ADS)

    Xiao, Guangming; Hooker, Kevin; Irby, Dave; Zhang, Yunqiang; Ward, Brian; Cecil, Tom; Hall, Brett; Lee, Mindy; Kim, Dave; Lucas, Kevin

    2014-03-01

    Traditional segment-based model-based OPC methods have been the mainstream mask layout optimization techniques in volume production for memory and embedded memory devices for many device generations. These techniques have been continually optimized over time to meet the ever increasing difficulties of memory and memory periphery patterning. There are a range of difficult issues for patterning embedded memories successfully. These difficulties include the need for a very high level of symmetry and consistency (both within memory cells themselves and between cells) due to circuit effects such as noise margin requirements in SRAMs. Memory cells and access structures consume a large percentage of area in embedded devices so there is a very high return from shrinking the cell area as much as possible. This aggressive scaling leads to very difficult resolution, 2D CD control and process window requirements. Additionally, the range of interactions between mask synthesis corrections of neighboring areas can extend well beyond the size of the memory cell, making it difficult to fully take advantage of the inherent designed cell hierarchy in mask pattern optimization. This is especially true for non-traditional (i.e., less dependent on geometric rule) OPC/RET methods such as inverse lithography techniques (ILT) which inherently have more model-based decisions in their optimizations. New inverse methods such as model-based SRAF placement and ILT are, however, well known to have considerable benefits in finding flexible mask pattern solutions to improve process window, improve 2D CD control, and improve resolution in ultra-dense memory patterns. They also are known to reduce recipe complexity and provide native MRC compliant mask pattern solutions. Unfortunately, ILT is also known to be several times slower than traditional OPC methods due to the increased computational lithographic optimizations it performs. In this paper, we describe and present results for a methodology to

  3. A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

    NASA Technical Reports Server (NTRS)

    Phillips, Thomas A.; Bailey, Mark; Ho, Fat Duen

    2004-01-01

    The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

  4. Distinct Effects of Memory Retrieval and Articulatory Preparation when Learning and Accessing New Word Forms

    PubMed Central

    Nora, Anni; Renvall, Hanna; Kim, Jeong-Young; Service, Elisabet; Salmelin, Riitta

    2015-01-01

    Temporal and frontal activations have been implicated in learning of novel word forms, but their specific roles remain poorly understood. The present magnetoencephalography (MEG) study examines the roles of these areas in processing newly-established word form representations. The cortical effects related to acquiring new phonological word forms during incidental learning were localized. Participants listened to and repeated back new word form stimuli that adhered to native phonology (Finnish pseudowords) or were foreign (Korean words), with a subset of the stimuli recurring four times. Subsequently, a modified 1-back task and a recognition task addressed whether the activations modulated by learning were related to planning for overt articulation, while parametrically added noise probed reliance on developing memory representations during effortful perception. Learning resulted in decreased left superior temporal and increased bilateral frontal premotor activation for familiar compared to new items. The left temporal learning effect persisted in all tasks and was strongest when stimuli were embedded in intermediate noise. In the noisy conditions, native phonotactics evoked overall enhanced left temporal activation. In contrast, the frontal learning effects were present only in conditions requiring overt repetition and were more pronounced for the foreign language. The results indicate a functional dissociation between temporal and frontal activations in learning new phonological word forms: the left superior temporal responses reflect activation of newly-established word-form representations, also during degraded sensory input, whereas the frontal premotor effects are related to planning for articulation and are not preserved in noise. PMID:25961571

  5. SEU rate prediction and measurement of GaAs SRAMs onboard the CRRES satellite

    SciTech Connect

    Weatherford, T.R.; McDonald, P.T. Naval Research Lab., Washington, DC ); Campbell, A.B.; Langworthy, J.B. )

    1993-12-01

    The Combined Release and Radiation Effects Satellite (CRRES) launched in July of 1990 included experiments to study effects of Single Event Upset (SEU) on various microelectronic ICs. The MicroElectronics Package (MEP) subsection of the satellite experiments monitored upset rates on 65 devices over a 15 month period. One of the purposes of the SEU experiments was to determine if the soft error modeling techniques were of sufficient accuracy to predict error rates, and if not, to determine where the deficiencies existed. An analysis is presented on SPICE predicted, SEU ground tested, and CRRES observed heavy ion and proton soft error rates of GaAs SRAMs. Upset rates overestimated the susceptibility of the GaAs SRAMs. Differences are accounted to several factors.

  6. Integration of SrBi2Ta2O9 thin films for high density ferroelectric random access memory

    NASA Astrophysics Data System (ADS)

    Wouters, D. J.; Maes, D.; Goux, L.; Lisoni, J. G.; Paraschiv, V.; Johnson, J. A.; Schwitters, M.; Everaert, J.-L.; Boullart, W.; Schaekers, M.; Willegems, M.; Vander Meeren, H.; Haspeslagh, L.; Artoni, C.; Caputa, C.; Casella, P.; Corallo, G.; Russo, G.; Zambrano, R.; Monchoix, H.; Vecchio, G.; Van Autryve, L.

    2006-09-01

    Ferroelectric random access memory (FeRAM) is an attractive candidate technology for embedded nonvolatile memory, especially in applications where low power and high program speed are important. Market introduction of high-density FeRAM is, however, lagging behind standard complementary metal-oxide semiconductor (CMOS) because of the difficult integration technology. This paper discusses the major integration issues for high-density FeRAM, based on SrBi2Ta2O9 (strontium bismuth tantalate or SBT), in relation to the fabrication of our stacked cell structure. We have worked in the previous years on the development of SBT-FeRAM integration technology, based on a so-called pseudo-three-dimensional (3D) cell, with a capacitor that can be scaled from quasi two-dimensional towards a true three-dimensional capacitor where the sidewalls will importantly contribute to the signal. In the first phase of our integration development, we integrated our FeRAM cell in a 0.35μm CMOS technology. In a second phase, then, possibility of scaling of our cell is demonstrated in 0.18μm technology. The excellent electrical and reliability properties of the small integrated ferroelectric capacitors prove the feasibility of the technology, while the verification of the potential 3D effect confirms the basic scaling potential of our concept beyond that of the single-mask capacitor. The paper outlines the different material and technological challenges, and working solutions are demonstrated. While some issues are specific to our own cell, many are applicable to different stacked FeRAM cell concepts, or will become more general concerns when more developments are moving into 3D structures.

  7. Variation in SEU sensitivity of dose-imprinted CMOS SRAMs

    SciTech Connect

    Stassinopoulos, E.G. ); Brucker, G.S. ); Van Gunten, O. ); Kim, H.S. )

    1989-12-01

    This paper reports on an experimental study of dose-induced changes in SEU sensitivity of CMOS static RAMs. Two time-regimes were investigated following exposure of memories to Cobalt-60 gamma rays: the near term within a few hours after exposure, and the long term, after many days. Samples were irradiated both at room and at liquid nitrogen temperatures. The latter procedure was used in order to freeze-in the damage state until SEU measurements could be made before annealing would take place. Results show that memories damaged by dose are more sensitive to upsets by heavy ions. The induced changes are substantial: threshold linear energy transfer (LET) values decreased by as much as 46% and asymptotic cross sections increased by factors of 2 to 4 (unannealed samples).

  8. Variation in SEU sensitivity of dose-imprinted CMOS SRAMs

    NASA Technical Reports Server (NTRS)

    Stassinopoulos, E. G.; Brucker, G. J.; Van Gunten, O.; Kim, H. S.

    1989-01-01

    The authors report on an experimental study of dose-induced changes in SEU (single-event-upset) sensitivity of CMOS static RAMs. Two time regimes were investigated following exposure of memories to cobalt-60 gamma rays: the near term, within a few hours after exposure, and the long term, after many days. Samples were irradiated both at room and at liquid nitrogen temperatures. The latter procedure was used in order to freeze in the damage state until SEU measurements could be made prior to annealing. Results show that memories damaged by dose are more sensitive to upsets by heavy ions. The induced changes are substantial: threshold linear energy transfer (LET) values decreased by as much as 46 percent and asymptotic cross sections increased by factors of two to four (unannealed samples).

  9. Resistance switching behavior of ZnO resistive random access memory with a reduced graphene oxide capping layer

    NASA Astrophysics Data System (ADS)

    Lin, Cheng-Li; Chang, Wei-Yi; Huang, Yen-Lun; Juan, Pi-Chun; Wang, Tse-Wen; Hung, Ke-Yu; Hsieh, Cheng-Yu; Kang, Tsung-Kuei; Shi, Jen-Bin

    2015-04-01

    In this work, we investigate the characteristics of ZnO resistive random access memory (RRAM) with a reduced graphene oxide (rGO) capping layer and the polarity effect of the SET/RESET bias on the RRAM. The rGO film insertion enhances the stability of the current-voltage (I-V) switching curve and the superior resistance ratio (˜105) of high-resistance state (HRS) to low-resistance state (LRS). Using the appropriate polarity of the SET/RESET bias applied to the rGO-capped ZnO RRAM enables the oxygen ions to move mainly at the interface of the rGO and ZnO films, resulting in the best performance. Presumably, the rGO film acts as an oxygen reservoir and enhances the easy in and out motion of the oxygen ions from the rGO film. The rGO film also prevents the interaction of oxygen ions and the Al electrode, resulting in excellent performance. In a pulse endurance test, the rGO-capped ZnO RRAM reveals superior endurance of up to 108 cycles over that of the ZnO RRAM without rGO insertion (106 cycles).

  10. Effects of different dopants on switching behavior of HfO2-based resistive random access memory

    NASA Astrophysics Data System (ADS)

    Deng, Ning; Pang, Hua; Wu, Wei

    2014-10-01

    In this study the effects of doping atoms (Al, Cu, and N) with different electro-negativities and ionic radii on resistive switching of HfO2-based resistive random access memory (RRAM) are systematically investigated. The results show that forming voltages and set voltages of Al/Cu-doped devices are reduced. Among all devices, Cu-doped device shows the narrowest device-to-device distributions of set voltage and low resistance. The effects of different dopants on switching behavior are explained with deferent types of CFs formed in HfO2 depending on dopants: oxygen vacancy (Vo) filaments for Al-doped HfO2 devices, hybrid filaments composed of oxygen vacancies and Cu atoms for Cu-doped HfO2 devices, and nitrogen/oxygen vacancy filaments for N-doped HfO2 devices. The results suggest that a metal dopant with a larger electro-negativity than host metal atom offers the best comprehensive performance.

  11. Cu impurity in insulators and in metal-insulator-metal structures: Implications for resistance-switching random access memories

    SciTech Connect

    Pandey, Sumeet C. Meade, Roy; Sandhu, Gurtej S.

    2015-02-07

    We present numerical results from atomistic simulations of Cu in SiO{sub 2} and Al{sub 2}O{sub 3}, with an emphasis on the thermodynamic, kinetic, and electronic properties. The calculated properties of Cu impurity at various concentrations (9.91 × 10{sup 20 }cm{sup −3} and 3.41 × 10{sup 22 }cm{sup −3}) in bulk oxides are presented. The metal-insulator interfaces result in up to a ∼4 eV reduction in the formation energies relative to the crystalline bulk. Additionally, the importance of Cu-Cu interaction in lowering the chemical potential is introduced. These concepts are then discussed in the context of formation and stability of localized conductive paths in resistance-switching Random Access Memories (RRAM-M). The electronic density of states and non-equilibrium transmission through these localized paths are studied, confirming conduction by showing three orders of magnitude increase in the electron transmission. The dynamic behavior of the conductive paths is investigated with atomistic drift-diffusion calculations. Finally, the paper concludes with a molecular dynamics simulation of a RRAM-M cell that attempts to combine the aforementioned phenomena in one self-consistent model.

  12. Low leakage ZrO2 based capacitors for sub 20 nm dynamic random access memory technology nodes

    NASA Astrophysics Data System (ADS)

    Pešić, Milan; Knebel, Steve; Geyer, Maximilian; Schmelzer, Sebastian; Böttger, Ulrich; Kolomiiets, Nadiia; Afanas'ev, Valeri V.; Cho, Kyuho; Jung, Changhwa; Chang, Jaewan; Lim, Hanjin; Mikolajick, Thomas; Schroeder, Uwe

    2016-02-01

    During dynamic random access memory (DRAM) capacitor scaling, a lot of effort was put searching for new material stacks to overcome the scaling limitations of the current material stack, such as leakage and sufficient capacitance. In this study, very promising results for a SrTiO3 based capacitor with a record low capacitance equivalent thickness value of 0.2 nm at target leakage current are presented. Due to the material properties of SrTiO3 films (high vacancy concentration and low band gap), which are leading to an increased leakage current, a physical thickness of at least 8 nm is required at target leakage specifications. However, this physical thickness would not fit into an 18 nm DRAM structure. Therefore, two different new approaches to develop a new ZrO2 based DRAM capacitor stack by changing the inter-layer material from Al2O3 to SrO and the exchange of the top electrode material from TiN to Pt are presented. A combination of these two approaches leads to a capacitance equivalent thickness value of 0.47 nm. Most importantly, the physical thickness of <5 nm for the dielectric stack is in accordance with the target specifications. Detailed evaluation of the leakage current characteristics leads to a capacitor model which allows the prediction of the electrical behavior with thickness scaling.

  13. Switching characteristics in Cu:SiO2 by chemical soak methods for resistive random access memory (ReRAM)

    NASA Astrophysics Data System (ADS)

    Chin, Fun-Tat; Lin, Yu-Hsien; Yang, Wen-Luh; Liao, Chin-Hsuan; Lin, Li-Min; Hsiao, Yu-Ping; Chao, Tien-Sheng

    2015-01-01

    A limited copper (Cu)-source Cu:SiO2 switching layer composed of various Cu concentrations was fabricated using a chemical soaking (CS) technique. The switching layer was then studied for developing applications in resistive random access memory (ReRAM) devices. Observing the resistive switching mechanism exhibited by all the samples suggested that Cu conductive filaments formed and ruptured during the set/reset process. The experimental results indicated that the endurance property failure that occurred was related to the joule heating effect. Moreover, the endurance switching cycle increased as the Cu concentration decreased. In high-temperature tests, the samples demonstrated that the operating (set/reset) voltages decreased as the temperature increased, and an Arrhenius plot was used to calculate the activation energy of the set/reset process. In addition, the samples demonstrated stable data retention properties when baked at 85 °C, but the samples with low Cu concentrations exhibited short retention times in the low-resistance state (LRS) during 125 °C tests. Therefore, Cu concentration is a crucial factor in the trade-off between the endurance and retention properties; furthermore, the Cu concentration can be easily modulated using this CS technique.

  14. A Characterization of Endurance in 64 Mbit Ferroelectric Random Access Memory by Analyzing the Space Charge Concentration

    NASA Astrophysics Data System (ADS)

    Lee, Eun Sun; Jung, Dong Jin; Kang, Young Min; Kim, Hyun Ho; Hong, Young Ki; Park, Jung Hoon; Kuk Kang, Seung; Kim, Jae Hyun; San Kim, Hee; Jung, Won Woong; Ahn, Woo Song; Jung, Ju Young; Kang, Jin Young; Choi, Do Yeon; Goh, Han Kyung; Kim, Song Yi; Lee, Sang Young; Jeong, Hong Sik

    2008-04-01

    Space charge concentration due to fatigue cycles was examined with an adequate modeling in order to expect read/write endurance of a 64 Mbit one-transistor and one-capacitor (1T1C) ferroelectric random access memory (FRAM). For monitoring the change in space charge concentration according to fatigue cycles, we assumed that our ferroelectric capacitor is governed by a partially depleted Schottky conduction model. With this, the space charge concentration at the each decade of the fatigue cycles was calculated by measuring the current-voltage characteristics. The space charge concentration at the initial stage was evaluated into 1.95 ×1020 and 2.16 ×1020/cm3 after the 1011 cycles. The concentration of 2.29 ×1020/cm3 was expected at the fatigue cycles of 1016 through a linear regression of the concentration plot against fatigue cycles. Accordingly, it could be said that our ferroelectric capacitor has few problems of endurance up to the 1016 cycles considering the concentration of ˜1020 and the film thickness of 80 nm. Other empirical data obtained in the capacitor level after full integration are supporting this expectation as well.

  15. Switching characteristics for ferroelectric random access memory based on RC model in poly(vinylidene fluoride-trifluoroethylene) ultrathin films

    NASA Astrophysics Data System (ADS)

    Liu, ChangLi; Wang, XueJun; Zhang, XiuLi; Du, XiaoLi; Xu, HaiSheng

    2016-05-01

    The switching characteristic of the poly(vinylidene fluoride-trifluoroethlene) (P(VDF-TrFE)) films have been studied at different ranges of applied electric field. It is suggest that the increase of the switching speed upon nucleation protocol and the deceleration of switching could be related to the presence of a non-ferroelectric layer. Remarkably, a capacitor and resistor (RC) links model plays significant roles in the polarization switching dynamics of the thin films. For P(VDF-TrFE) ultrathin films with electroactive interlayer, it is found that the switching dynamic characteristics are strongly affected by the contributions of resistor and non-ferroelectric (non-FE) interface factors. A corresponding experiment is designed using poly(3,4-ethylene dioxythiophene):poly(styrene sulfonic) (PEDOT-PSSH) as interlayer with different proton concentrations, and the testing results show that the robust switching is determined by the proton concentration in interlayer and lower leakage current in circuit to reliable applications of such polymer films. These findings provide a new feasible method to enhance the polarization switching for the ferroelectric random access memory.

  16. Energetics of intrinsic defects in NiO and the consequences for its resistive random access memory performance

    NASA Astrophysics Data System (ADS)

    Dawson, J. A.; Guo, Y.; Robertson, J.

    2015-09-01

    Energetics for a variety of intrinsic defects in NiO are calculated using state-of-the-art ab initio hybrid density functional theory calculations. At the O-rich limit, Ni vacancies are the lowest cost defect for all Fermi energies within the gap, in agreement with the well-known p-type behaviour of NiO. However, the ability of the metal electrode in a resistive random access memory metal-oxide-metal setup to shift the oxygen chemical potential towards the O-poor limit results in unusual NiO behaviour and O vacancies dominating at lower Fermi energy levels. Calculated band diagrams show that O vacancies in NiO are positively charged at the operating Fermi energy giving it the advantage of not requiring a scavenger metal layer to maximise drift. Ni and O interstitials are generally found to be higher in energy than the respective vacancies suggesting that significant recombination of O vacancies and interstitials does not take place as proposed in some models of switching behaviour.

  17. Energetics of intrinsic defects in NiO and the consequences for its resistive random access memory performance

    SciTech Connect

    Dawson, J. A. Guo, Y.; Robertson, J.

    2015-09-21

    Energetics for a variety of intrinsic defects in NiO are calculated using state-of-the-art ab initio hybrid density functional theory calculations. At the O-rich limit, Ni vacancies are the lowest cost defect for all Fermi energies within the gap, in agreement with the well-known p-type behaviour of NiO. However, the ability of the metal electrode in a resistive random access memory metal-oxide-metal setup to shift the oxygen chemical potential towards the O-poor limit results in unusual NiO behaviour and O vacancies dominating at lower Fermi energy levels. Calculated band diagrams show that O vacancies in NiO are positively charged at the operating Fermi energy giving it the advantage of not requiring a scavenger metal layer to maximise drift. Ni and O interstitials are generally found to be higher in energy than the respective vacancies suggesting that significant recombination of O vacancies and interstitials does not take place as proposed in some models of switching behaviour.

  18. Vividness of Visual Imagery and Incidental Recall of Verbal Cues, When Phenomenological Availability Reflects Long-Term Memory Accessibility

    PubMed Central

    D’Angiulli, Amedeo; Runge, Matthew; Faulkner, Andrew; Zakizadeh, Jila; Chan, Aldrich; Morcos, Selvana

    2013-01-01

    The relationship between vivid visual mental images and unexpected recall (incidental recall) was replicated, refined, and extended. In Experiment 1, participants were asked to generate mental images from imagery-evoking verbal cues (controlled on several verbal properties) and then, on a trial-by-trial basis, rate the vividness of their images; 30 min later, participants were surprised with a task requiring free recall of the cues. Higher vividness ratings predicted better incidental recall of the cues than individual differences (whose effect was modest). Distributional analysis of image latencies through ex-Gaussian modeling showed an inverse relation between vividness and latency. However, recall was unrelated to image latency. The follow-up Experiment 2 showed that the processes underlying trial-by-trial vividness ratings are unrelated to the Vividness of Visual Imagery Questionnaire (VVIQ), as further supported by a meta-analysis of a randomly selected sample of relevant literature. The present findings suggest that vividness may act as an index of availability of long-term sensory traces, playing a non-epiphenomenal role in facilitating the access of those memories. PMID:23382719

  19. Calculation of energy-barrier lowering by incoherent switching in spin-transfer torque magnetoresistive random-access memory

    SciTech Connect

    Munira, Kamaram; Visscher, P. B.

    2015-05-07

    To make a useful spin-transfer torque magnetoresistive random-access memory (STT-MRAM) device, it is necessary to be able to calculate switching rates, which determine the error rates of the device. In a single-macrospin model, one can use a Fokker-Planck equation to obtain a low-current thermally activated rate ∝exp(−E{sub eff}/k{sub B}T). Here, the effective energy barrier E{sub eff} scales with the single-macrospin energy barrier KV, where K is the effective anisotropy energy density and V the volume. A long-standing paradox in this field is that the actual energy barrier appears to be much smaller than this. It has been suggested that incoherent motions may lower the barrier, but this has proved difficult to quantify. In the present paper, we show that the coherent precession has a magnetostatic instability, which allows quantitative estimation of the energy barrier and may resolve the paradox.

  20. Finding Oxygen Reservoir by Using Extremely Small Test Cell Structure for Resistive Random Access Memory with Replaceable Bottom Electrode

    PubMed Central

    Kinoshita, Kentaro; Koh, Sang-Gyu; Moriyama, Takumi; Kishida, Satoru

    2015-01-01

    Although the presence of an oxygen reservoir (OR) is assumed in many models that explain resistive switching of resistive random access memory (ReRAM) with electrode/metal oxide (MO)/electrode structures, the location of OR is not clear. We have previously reported a method, which involved the use of an AFM cantilever, for preparing an extremely small ReRAM cell that has a removable bottom electrode (BE). In this study, we used this cell structure to specify the location of OR. Because an anode is often assumed to work as OR, we investigated the effect of changing anodes without changing the MO layer and the cathode on the occurrence of reset. It was found that the reset occurred independently of the catalytic ability and Gibbs free energy (ΔG) of the anode. Our proposed structure enabled to determine that the reset was caused by repairing oxygen vacancies of which a filament consists due to the migration of oxygen ions from the surrounding area when high ΔG anode metal is used, whereas by oxidizing the anode due to the migration of oxygen ions from the MO layer when low ΔG anode metal is used, suggesting the location of OR depends on ΔG of the anode. PMID:26689682

  1. Finding Oxygen Reservoir by Using Extremely Small Test Cell Structure for Resistive Random Access Memory with Replaceable Bottom Electrode.

    PubMed

    Kinoshita, Kentaro; Koh, Sang-Gyu; Moriyama, Takumi; Kishida, Satoru

    2015-01-01

    Although the presence of an oxygen reservoir (OR) is assumed in many models that explain resistive switching of resistive random access memory (ReRAM) with electrode/metal oxide (MO)/electrode structures, the location of OR is not clear. We have previously reported a method, which involved the use of an AFM cantilever, for preparing an extremely small ReRAM cell that has a removable bottom electrode (BE). In this study, we used this cell structure to specify the location of OR. Because an anode is often assumed to work as OR, we investigated the effect of changing anodes without changing the MO layer and the cathode on the occurrence of reset. It was found that the reset occurred independently of the catalytic ability and Gibbs free energy (ΔG) of the anode. Our proposed structure enabled to determine that the reset was caused by repairing oxygen vacancies of which a filament consists due to the migration of oxygen ions from the surrounding area when high ΔG anode metal is used, whereas by oxidizing the anode due to the migration of oxygen ions from the MO layer when low ΔG anode metal is used, suggesting the location of OR depends on ΔG of the anode. PMID:26689682

  2. Finding Oxygen Reservoir by Using Extremely Small Test Cell Structure for Resistive Random Access Memory with Replaceable Bottom Electrode

    NASA Astrophysics Data System (ADS)

    Kinoshita, Kentaro; Koh, Sang-Gyu; Moriyama, Takumi; Kishida, Satoru

    2015-12-01

    Although the presence of an oxygen reservoir (OR) is assumed in many models that explain resistive switching of resistive random access memory (ReRAM) with electrode/metal oxide (MO)/electrode structures, the location of OR is not clear. We have previously reported a method, which involved the use of an AFM cantilever, for preparing an extremely small ReRAM cell that has a removable bottom electrode (BE). In this study, we used this cell structure to specify the location of OR. Because an anode is often assumed to work as OR, we investigated the effect of changing anodes without changing the MO layer and the cathode on the occurrence of reset. It was found that the reset occurred independently of the catalytic ability and Gibbs free energy (ΔG) of the anode. Our proposed structure enabled to determine that the reset was caused by repairing oxygen vacancies of which a filament consists due to the migration of oxygen ions from the surrounding area when high ΔG anode metal is used, whereas by oxidizing the anode due to the migration of oxygen ions from the MO layer when low ΔG anode metal is used, suggesting the location of OR depends on ΔG of the anode.

  3. Total ionizing dose effect of γ-ray radiation on the switching characteristics and filament stability of HfOx resistive random access memory

    SciTech Connect

    Fang, Runchen; Yu, Shimeng; Gonzalez Velo, Yago; Chen, Wenhao; Holbert, Keith E.; Kozicki, Michael N.; Barnaby, Hugh

    2014-05-05

    The total ionizing dose (TID) effect of gamma-ray (γ-ray) irradiation on HfOx based resistive random access memory was investigated by electrical and material characterizations. The memory states can sustain TID level ∼5.2 Mrad (HfO{sub 2}) without significant change in the functionality or the switching characteristics under pulse cycling. However, the stability of the filament is weakened after irradiation as memory states are more vulnerable to flipping under the electrical stress. X-ray photoelectron spectroscopy was performed to ascertain the physical mechanism of the stability degradation, which is attributed to the Hf-O bond breaking by the high-energy γ-ray exposure.

  4. Resistive Switching Behavior in Organic-Inorganic Hybrid CH3 NH3 PbI3-x Clx Perovskite for Resistive Random Access Memory Devices.

    PubMed

    Yoo, Eun Ji; Lyu, Miaoqiang; Yun, Jung-Ho; Kang, Chi Jung; Choi, Young Jin; Wang, Lianzhou

    2015-10-28

    The CH3 NH3 PbI3- x Clx organic-inorganic hybrid perovskite material demonstrates remarkable resistive switching behavior, which can be applicable in resistive random access memory devices. The simply designed Au/CH3 NH3 PbI3- x Clx /FTO structure is fabricated by a low-temperature, solution-processable method, which exhibits remarkable bipolar resistive switching and nonvolatile properties. PMID:26331363

  5. Predictions for proton and heavy ions induced SEUs in 65 nm SRAMs

    NASA Astrophysics Data System (ADS)

    Shougang, Du; Suge, Yue; Hongxia, Liu; Long, Fan; Hongchao, Zheng

    2015-11-01

    We report on irradiation induced single event upset (SEU) by high-energy protons and heavy ions. The experiments were performed at the Paul Scherer Institute, and heavy ions at the SEE irradiating Facility on the HI-13 Tandem Accelerator in China's Institute of Atomic Energy, Beijing and the Heavy Ion Research Facility in Lanzhou in the Institute of Modern Physics, Chinese Academy of Sciences. The results of proton and heavy ions induced (SEU) in 65 nm bulk silicon CMOS SRAMS are discussed and the prediction on several typical orbits are presented.

  6. Determination of key parameters of SEU occurrence using 3-D full cell SRAM simulations

    SciTech Connect

    Roche, P.; Palau, J.M.; Bruguier, G.; Tavernier, C.; Ecoffet, R.; Gasiot, J.

    1999-12-01

    A 3-D entire SRAM cell, based on a 0.35-{micro}m current CMOS technology, is simulated in this work with a DEVICE simulator. The transient current, resulting from a heavy ion strike in the most sensitive region of the cell, is studied as a function of the LET value, the cell layout and the ion penetration depth. A definition of the critical charge is proposed and two new methods are presented to compute this basic amount of charge only using SPICE simulations. Numerical applications are performed with two different generations of submicron CMOS technologies, including the determination of the sensitive thicknesses.

  7. SPICE analysis of the SEU sensitivity of a fully depleted SOI CMOS SRAM cell

    SciTech Connect

    Alles, M.L. )

    1994-12-01

    Fully depleted silicon-on-insulator (SOI) technologies are of interest for commercial applications as well as for use in harsh (radiation-intensive) environments. In both types of application, effects of charged particles (single-event effects) are of concern. Here, SPICE analysis of SEU sensitivity of a 6-T SRAM cell using commercially-representative fully depleted SOI CMOS technology parameters indicates that reduction of the minority carrier lifetime (parasitic bipolar gain) and use of thinner silicon can significantly reduce SEU sensitivity.

  8. Advanced Mass Memory Concept Development

    NASA Astrophysics Data System (ADS)

    Sanchez, A. V.; Furano, G.; Ciccone, M.; Taylor, C.; Tejedor, N. G.; Knoblauch, M.; Parra Espada, P.; PrietoMateo, M.

    2008-08-01

    Current Solid State Mass Memory (SSMM) developments for space borne data handling systems are ad-hoc designs tailored f or a specific mission or mission class. This is mainly due to the technological constraints given b y the use of specific memory chips (SRAM, DRAM, DDRAM and in future FLASH), b y the interfaces towards other DHS units (packetwire, spacewire, custom) and, by the services that are needed in the SSMM unit (file store, mailbox, compression). Those designs n ormally lack of re-usability, and involve significant customization once ported to different systems. Within this work we will demonstrate that existing space technologies (including, hardware, interfaces and SW) already cover the building blocks required for an implementation of a scalable and modular SSMM, providing also a greater level of redundancy a nd greater capabilities with respect to existing designs. Providing that standard interfaces agreed for each building block, complex subsystems may be constructed from relatively simple individual blocks. By applying this approach the SSMM will be developed from already existing satellite technology a dapted to provide standard interfaces. This design a pproach also allows any block within the SSMM to be replaced without affecting the remaining blocks, thus decreasing development times and increasing the re-usability and adaptability between different missions, not mentioning the inherent redundancy. A nother key aspect in the SSMM design is the number of services implemented within the unit and their purpose. Several trade-off can be performed for example: should the SSMM provide a file system? If so, which kind of file system should be implemented? S hall the file system wrap up and enhance the functionality of another storage systems (e.g. packet store)? W hich kind of technology should be implemented to increase the resilience to failure? And many more. T his paper is intended to present the current conceptual view of a SSMM using a building

  9. Memory protection

    NASA Technical Reports Server (NTRS)

    Denning, Peter J.

    1988-01-01

    Accidental overwriting of files or of memory regions belonging to other programs, browsing of personal files by superusers, Trojan horses, and viruses are examples of breakdowns in workstations and personal computers that would be significantly reduced by memory protection. Memory protection is the capability of an operating system and supporting hardware to delimit segments of memory, to control whether segments can be read from or written into, and to confine accesses of a program to its segments alone. The absence of memory protection in many operating systems today is the result of a bias toward a narrow definition of performance as maximum instruction-execution rate. A broader definition, including the time to get the job done, makes clear that cost of recovery from memory interference errors reduces expected performance. The mechanisms of memory protection are well understood, powerful, efficient, and elegant. They add to performance in the broad sense without reducing instruction execution rate.

  10. Implementation of nitrogen-doped titanium-tungsten tunable heater in phase change random access memory and its effects on device performance

    SciTech Connect

    Tan, Chun Chia; Zhao, Rong Chong, Tow Chong; Shi, Luping

    2014-10-13

    Nitrogen-doped titanium-tungsten (N-TiW) was proposed as a tunable heater in Phase Change Random Access Memory (PCRAM). By tuning N-TiW's material properties through doping, the heater can be tailored to optimize the access speed and programming current of PCRAM. Experiments reveal that N-TiW's resistivity increases and thermal conductivity decreases with increasing nitrogen-doping ratio, and N-TiW devices displayed (∼33% to ∼55%) reduced programming currents. However, there is a tradeoff between the current and speed for heater-based PCRAM. Analysis of devices with different N-TiW heaters shows that N-TiW doping levels could be optimized to enable low RESET currents and fast access speeds.

  11. SEU-hardened silicon bipolar and GaAs MESFET SRAM cells using local redundancy techniques

    SciTech Connect

    Hauser, J.R. )

    1992-02-01

    Silicon bipolar and GaAs FET SRAM's have proven to be more difficult to harden with respect to single-event upset mechanisms than have silicon CMOS SRAM's. This is a fundamental property of bipolar and JFET or MESFET device technologies which do not have a high-impedance, nonactive isolation between the control electrode and the current or voltage being controlled. All SEU circuit level hardening techniques applied at the local level must use some type of information storage redundancy so that information loss on one node due to an SEU event can be recovered from information stored elsewhere in the cell. In CMOS technologies, this can be achieved by the use of simple cross-coupling resistors, whereas in bipolar and FET technologies, no such simple approach is possible. Several approaches to the use of local redundancy in bipolar and FET technologies are discussed in this paper. At the expense of increased cell complexity and increased power consumption and write time, several approaches are capable of providing complete SEU hardness at the local cell level.

  12. Detrimental effect of interfacial Dzyaloshinskii-Moriya interaction on perpendicular spin-transfer-torque magnetic random access memory

    SciTech Connect

    Jang, Peong-Hwa; Lee, Seo-Won E-mail: kj-lee@korea.ac.kr; Song, Kyungmi; Lee, Seung-Jae; Lee, Kyung-Jin E-mail: kj-lee@korea.ac.kr

    2015-11-16

    Interfacial Dzyaloshinskii-Moriya interaction in ferromagnet/heavy metal bilayers is recently of considerable interest as it offers an efficient control of domain walls and the stabilization of magnetic skyrmions. However, its effect on the performance of perpendicular spin transfer torque memory has not been explored yet. We show based on numerical studies that the interfacial Dzyaloshinskii-Moriya interaction decreases the thermal energy barrier while increases the switching current. As high thermal energy barrier as well as low switching current is required for the commercialization of spin torque memory, our results suggest that the interfacial Dzyaloshinskii-Moriya interaction should be minimized for spin torque memory applications.

  13. A simple device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory.

    PubMed

    Lee, Myoung-Jae; Ahn, Seung-Eon; Lee, Chang Bum; Kim, Chang-Jung; Jeon, Sanghun; Chung, U-In; Yoo, In-Kyeong; Park, Gyeong-Su; Han, Seungwu; Hwang, In Rok; Park, Bae-Ho

    2011-11-01

    Present charge-based silicon memories are unlikely to reach terabit densities because of scaling limits. As the feature size of memory shrinks to just tens of nanometers, there is insufficient volume available to store charge. Also, process temperatures higher than 800 °C make silicon incompatible with three-dimensional (3D) stacking structures. Here we present a device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory using resistance switching. It is demonstrated that NiO films are scalable to around 30 nm and compatible with multilevel cell technology. The device unit can be a building block for 3D stacking structure because of its simple structure and constituent, high performance, and process temperature lower than 300 °C. Memory resistance switching of NiO storage element is accompanied by an increase in density of grain boundary while threshold resistance switching of NiO switch element is controlled by current flowing through NiO film. PMID:21988144

  14. Quantifying data retention of perpendicular spin-transfer-torque magnetic random access memory chips using an effective thermal stability factor method

    SciTech Connect

    Thomas, Luc Jan, Guenole; Le, Son; Wang, Po-Kang

    2015-04-20

    The thermal stability of perpendicular Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) devices is investigated at chip level. Experimental data are analyzed in the framework of the Néel-Brown model including distributions of the thermal stability factor Δ. We show that in the low error rate regime important for applications, the effect of distributions of Δ can be described by a single quantity, the effective thermal stability factor Δ{sub eff}, which encompasses both the median and the standard deviation of the distributions. Data retention of memory chips can be assessed accurately by measuring Δ{sub eff} as a function of device diameter and temperature. We apply this method to show that 54 nm devices based on our perpendicular STT-MRAM design meet our 10 year data retention target up to 120 °C.

  15. Experimental evidence of the quantum point contact theory in the conduction mechanism of bipolar HfO2-based resistive random access memories

    NASA Astrophysics Data System (ADS)

    Prócel, L. M.; Trojman, L.; Moreno, J.; Crupi, F.; Maccaronio, V.; Degraeve, R.; Goux, L.; Simoen, E.

    2013-08-01

    The quantum point contact (QPC) model for dielectric breakdown is used to explain the electron transport mechanism in HfO2-based resistive random access memories (ReRAM) with TiN(30 nm)HfO2(5 nm)Hf(10 nm)TiN(30 nm) stacks. Based on experimental I-V characteristics of bipolar HfO2-based ReRAM, we extracted QPC model parameters related to the conduction mechanism in several devices in order to make a statistical study. In addition, we investigated the temperature effect on the conduction mechanism and compared it with the QPC model. Based on these experimental results, we show that the QPC model agrees well with the conduction behavior of HfO2-based ReRAM memory cells.

  16. Investigation of thermal stability and reliability of HfO2 based resistive random access memory devices with cross-bar structure

    NASA Astrophysics Data System (ADS)

    Chand, Umesh; Huang, Kuan-Chang; Huang, Chun-Yang; Ho, Chia-Hua; Lin, Chen-Hsi; Tseng, Tseung-Yuen

    2015-05-01

    The effect of the annealing treatment of a HfO2 resistive switching layer and the memory performance of a HfO2-based resistive random access memory (cross-bar structure) device were investigated. Oxygen is released from HfO2 resistive switching layers during vacuum annealing, leading to unstable resistive switching properties. This oxygen release problem can be suppressed by inserting an Al2O3 thin film, which has a lower Gibbs free energy, between the HfO2 layer and top electrode to form a Ti/Al2O3/HfO2/TiN structure. This device structure exhibited good reliability after high temperature vacuum annealing and post metal annealing (PMA) treatments. Moreover, the endurance and retention properties of the device were also improved after the PMA treatment.

  17. Reducing operation voltages by introducing a low-k switching layer in indium–tin-oxide-based resistance random access memory

    NASA Astrophysics Data System (ADS)

    Jin, Fu-Yuan; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Pan, Chih-Hung; Lin, Chih-Yang; Chen, Po-Hsun; Chen, Min-Chen; Huang, Hui-Chun; Lo, Ikai; Zheng, Jin-Cheng; Sze, Simon M.

    2016-06-01

    In this letter, we inserted a low dielectric constant (low-k) or high dielectric constant (high-k) material as a switching layer in indium–tin-oxide-based resistive random-access memory. After measuring the two samples, we found that the low-k material device has very low operating voltages (‑80 and 110 mV for SET and RESET operations, respectively). Current fitting results were then used with the COMSOL software package to simulate electric field distribution in the layers. After combining the electrical measurement results with simulations, a conduction model was proposed to explain resistance switching behaviors in the two structures.

  18. Bit Distribution and Reliability of High Density 1.5 V Ferroelectric Random Access Memory Embedded with 130 nm, 5 lm Copper Complementary Metal Oxide Semiconductor Logic

    NASA Astrophysics Data System (ADS)

    Udayakumar, K. R.; Boku, K.; Remack, K. A.; Rodriguez, J.; Summerfelt, S. R.; Celii, F. G.; Aggarwal, S.; Martin, J. S.; Hall, L.; Matz, L.; Rathsack, B.; McAdams, H.; Moise, T. S.

    2006-04-01

    High density embedded ferroelectric random access memory (FRAM), operable at 1.5 V, has been fabricated within a 130 nm, 5 lm Cu/fluorosilicate glass (FSG) logic process. To evaluate FRAM extendability to future process nodes, we have measured the bit distribution and reliability properties of arrays with varying individual capacitor areas ranging from 0.40 μm2 (130 nm node) to 0.15 μm2 (˜65 nm node). Wide signal margins, stable retention (≫10 years at 85 °C), and high endurance read/write cycling (≫1012 cycles) have been demonstrated, suggesting that reliable, high density FRAM can be realized.

  19. Mechanism of power consumption inhibitive multi-layer Zn:SiO2/SiO2 structure resistance random access memory

    NASA Astrophysics Data System (ADS)

    Zhang, Rui; Tsai, Tsung-Ming; Chang, Ting-Chang; Chang, Kuan-Chang; Chen, Kai-Huang; Lou, Jen-Chung; Young, Tai-Fa; Chen, Jung-Hui; Huang, Syuan-Yong; Chen, Min-Chen; Shih, Chih-Cheng; Chen, Hsin-Lu; Pan, Jhih-Hong; Tung, Cheng-Wei; Syu, Yong-En; Sze, Simon M.

    2013-12-01

    In this paper, multi-layer Zn:SiO2/SiO2 structure is introduced to reduce the operation power consumption of resistive random access memory (RRAM) device by modifying the filament formation process. And the configuration of multi-layer Zn:SiO2/SiO2 structure is confirmed and demonstrated by auger electron spectrum. Material analysis together with conduction current fitting is applied to qualitatively evaluate the carrier conduction mechanism on both low resistance state and high resistance state. Finally, single layer and multilayer conduction models are proposed, respectively, to clarify the corresponding conduction characteristics of two types of RRAM devices.

  20. Mechanism of power consumption inhibitive multi-layer Zn:SiO{sub 2}/SiO{sub 2} structure resistance random access memory

    SciTech Connect

    Zhang, Rui; Lou, Jen-Chung; Tsai, Tsung-Ming E-mail: tcchang@mail.phys.nsysu.edu.tw; Chang, Kuan-Chang; Huang, Syuan-Yong; Shih, Chih-Cheng; Pan, Jhih-Hong; Tung, Cheng-Wei; Chang, Ting-Chang E-mail: tcchang@mail.phys.nsysu.edu.tw; Chen, Kai-Huang; Young, Tai-Fa; Chen, Hsin-Lu; Chen, Jung-Hui; Chen, Min-Chen; Syu, Yong-En; Sze, Simon M.

    2013-12-21

    In this paper, multi-layer Zn:SiO{sub 2}/SiO{sub 2} structure is introduced to reduce the operation power consumption of resistive random access memory (RRAM) device by modifying the filament formation process. And the configuration of multi-layer Zn:SiO{sub 2}/SiO{sub 2} structure is confirmed and demonstrated by auger electron spectrum. Material analysis together with conduction current fitting is applied to qualitatively evaluate the carrier conduction mechanism on both low resistance state and high resistance state. Finally, single layer and multilayer conduction models are proposed, respectively, to clarify the corresponding conduction characteristics of two types of RRAM devices.

  1. A DRAM compiler algorithm for high performance VLSI embedded memories

    NASA Technical Reports Server (NTRS)

    Eldin, A. G.

    1992-01-01

    In many applications, the limited density of the embedded SRAM does not allow integrating the memory on the same chip with other logic and functional blocks. In such cases, the embedded DRAM provides the optimum combination of very high density, low power, and high performance. For ASIC's to take full advantage of this design strategy, an efficient and highly reliable DRAM compiler must be used. The embedded DRAM architecture, cell, and peripheral circuit design considerations and the algorithm of a high performance memory compiler are presented .

  2. SiO2 doped Ge2Sb2Te5 thin films with high thermal efficiency for applications in phase change random access memory.

    PubMed

    Ryu, Seung Wook; Lyeo, Ho-Ki; Lee, Jong Ho; Ahn, Young Bae; Kim, Gun Hwan; Kim, Choon Hwan; Kim, Soo Gil; Lee, Se-Ho; Kim, Ka Young; Kim, Jong Hyeop; Kim, Won; Hwang, Cheol Seong; Kim, Hyeong Joon

    2011-06-24

    This study examined the various physical, structural and electrical properties of SiO(2) doped Ge(2)Sb(2)Te(5) (SGST) films for phase change random access memory applications. Interestingly, SGST had a layered structure (LS) resulting from the inhomogeneous distribution of SiO(2) after annealing. The physical parameters able to affect the reset current of phase change memory (I(res)) were predicted from the Joule heating and heat conservation equations. When SiO(2) was doped into GST, thermal conductivity largely decreased by ∼ 55%. The influence of SiO(2)-doping on I(res) was examined using the test phase change memory cell. I(res) was reduced by ∼ 45%. An electro-thermal simulation showed that the reduced thermal conductivity contributes to the improvement of cell efficiency as well as the reduction of I(res), while the increased dynamic resistance contributes only to the latter. The formation and presence of the LS thermal conductivity in the set state test cell after repeated switching was confirmed. PMID:21572208

  3. a-SiNx:H-based ultra-low power resistive random access memory with tunable Si dangling bond conduction paths

    PubMed Central

    Jiang, Xiaofan; Ma, Zhongyuan; Xu, Jun; Chen, Kunji; Xu, Ling; Li, Wei; Huang, Xinfan; Feng, Duan

    2015-01-01

    The realization of ultra-low power Si-based resistive switching memory technology will be a milestone in the development of next generation non-volatile memory. Here we show that a high performance and ultra-low power resistive random access memory (RRAM) based on an Al/a-SiNx:H/p+-Si structure can be achieved by tuning the Si dangling bond conduction paths. We reveal the intrinsic relationship between the Si dangling bonds and the N/Si ratio x for the a-SiNx:H films, which ensures that the programming current can be reduced to less than 1 μA by increasing the value of x. Theoretically calculated current-voltage (I–V ) curves combined with the temperature dependence of the I–V characteristics confirm that, for the low-resistance state (LRS), the Si dangling bond conduction paths obey the trap-assisted tunneling model. In the high-resistance state (HRS), conduction is dominated by either hopping or Poole–Frenkel (P–F) processes. Our introduction of hydrogen in the a-SiNx:H layer provides a new way to control the Si dangling bond conduction paths, and thus opens up a research field for ultra-low power Si-based RRAM. PMID:26508086

  4. a-SiNx:H-based ultra-low power resistive random access memory with tunable Si dangling bond conduction paths.

    PubMed

    Jiang, Xiaofan; Ma, Zhongyuan; Xu, Jun; Chen, Kunji; Xu, Ling; Li, Wei; Huang, Xinfan; Feng, Duan

    2015-01-01

    The realization of ultra-low power Si-based resistive switching memory technology will be a milestone in the development of next generation non-volatile memory. Here we show that a high performance and ultra-low power resistive random access memory (RRAM) based on an Al/a-SiNx:H/p(+)-Si structure can be achieved by tuning the Si dangling bond conduction paths. We reveal the intrinsic relationship between the Si dangling bonds and the N/Si ratio x for the a-SiNx:H films, which ensures that the programming current can be reduced to less than 1 μA by increasing the value of x. Theoretically calculated current-voltage (I-V) curves combined with the temperature dependence of the I-V characteristics confirm that, for the low-resistance state (LRS), the Si dangling bond conduction paths obey the trap-assisted tunneling model. In the high-resistance state (HRS), conduction is dominated by either hopping or Poole-Frenkel (P-F) processes. Our introduction of hydrogen in the a-SiNx:H layer provides a new way to control the Si dangling bond conduction paths, and thus opens up a research field for ultra-low power Si-based RRAM. PMID:26508086

  5. a-SiNx:H-based ultra-low power resistive random access memory with tunable Si dangling bond conduction paths

    NASA Astrophysics Data System (ADS)

    Jiang, Xiaofan; Ma, Zhongyuan; Xu, Jun; Chen, Kunji; Xu, Ling; Li, Wei; Huang, Xinfan; Feng, Duan

    2015-10-01

    The realization of ultra-low power Si-based resistive switching memory technology will be a milestone in the development of next generation non-volatile memory. Here we show that a high performance and ultra-low power resistive random access memory (RRAM) based on an Al/a-SiNx:H/p+-Si structure can be achieved by tuning the Si dangling bond conduction paths. We reveal the intrinsic relationship between the Si dangling bonds and the N/Si ratio x for the a-SiNx:H films, which ensures that the programming current can be reduced to less than 1 μA by increasing the value of x. Theoretically calculated current-voltage (I-V ) curves combined with the temperature dependence of the I-V characteristics confirm that, for the low-resistance state (LRS), the Si dangling bond conduction paths obey the trap-assisted tunneling model. In the high-resistance state (HRS), conduction is dominated by either hopping or Poole-Frenkel (P-F) processes. Our introduction of hydrogen in the a-SiNx:H layer provides a new way to control the Si dangling bond conduction paths, and thus opens up a research field for ultra-low power Si-based RRAM.

  6. Accessing Epstein-Barr Virus-Specific T-Cell Memory with Peptide-Loaded Dendritic Cells

    PubMed Central

    Redchenko, I. V.; Rickinson, A. B.

    1999-01-01

    The conventional means of studying Epstein-Barr virus (EBV)-induced cytotoxic T-lymphocyte (CTL) memory, by in vitro stimulation with the latently infected autologous lymphoblastoid cell line (LCL), has important limitations. First, it gives no information on memory to lytic cycle antigens; second, it preferentially amplifies the dominant components of latent antigen-specific memory at the expense of key subdominant reactivities. Here we describe an alternative approach, based on in vitro stimulation with epitope peptide-loaded dendritic cells (DCs), which allows one to probe the CTL repertoire for any individual reactivity of choice; this method proved significantly more efficient than stimulation with peptide alone. Using this approach we first show that reactivities to the immunodominant and subdominant lytic cycle epitopes identified by T cells during primary EBV infection are regularly detectable in the CTL memory of virus carriers; this implies that in such carriers chronic virus replication remains under direct T-cell control. We further show that subdominant latent cycle reactivities to epitopes in the latent membrane protein LMP2, though rarely undetectable in LCL-stimulated populations, can be reactivated by DC stimulation and selectively expanded as polyclonal CTL lines; the adoptive transfer of such preparations may be of value in targeting certain EBV-positive malignancies. PMID:9847337

  7. Loss of Object Recognition Memory Produced by Extended Access to Methamphetamine Self-Administration is Reversed by Positive Allosteric Modulation of Metabotropic Glutamate Receptor 5

    PubMed Central

    Reichel, Carmela M; Schwendt, Marek; McGinty, Jacqueline F; Olive, M Foster; See, Ronald E

    2011-01-01

    Chronic methamphetamine (meth) abuse can lead to persisting cognitive deficits. Here, we utilized a long-access meth self-administration (SA) protocol to assess recognition memory and metabotropic glutamate receptor (mGluR) expression, and the possible reversal of cognitive impairments with the mGluR5 allosteric modulator, 3-cyano-N-(1,3-diphenyl-1H-pyrazol-5-yl) benzamide (CDPPB). Male, Long-Evans rats self-administered i.v. meth (0.02 mg/infusion) on an FR1 schedule of reinforcement or received yoked-saline infusions. After seven daily 1-h sessions, rats were switched to 6-h daily sessions for 14 days, and then underwent drug abstinence. Rats were tested for object recognition memory at 1 week after meth SA at 90 min and 24 h retention intervals. In a separate experiment, rats underwent the same protocol, but received either vehicle or CDPPB (30 mg/kg) after familiarization. Rats were killed on day 8 or 14 post-SA and brain tissue was obtained. Meth intake escalated over the extended access period. Additionally, meth-experienced rats showed deficits in both short- and long-term recognition memory, demonstrated by a lack of novel object exploration. The deficit at 90 min was reversed by CDPPB treatment. On day 8, meth intake during SA negatively correlated with mGluR expression in the perirhinal and prefrontal cortex, and mGluR5 receptor expression was decreased 14 days after discontinuation of meth. This effect was specific to mGluR5 levels in the perirhinal cortex, as no differences were identified in the hippocampus or in mGluR2/3 receptors. These results from a clinically-relevant animal model of addiction suggest that mGluR5 receptor modulation may be a potential treatment of cognitive dysfunction in meth addiction. PMID:21150906

  8. Gas-Sensing Flip-Flop Circuits

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.; Blaes, Brent R.; Williams, Roger; Ryan, Margaret A.

    1995-01-01

    Gas-sensing integrated circuits consisting largely of modified static random-access memories (SRAMs) undergoing development, building on experience gained in use of modified SRAMs as radiation sensors. Each SRAM memory cell includes flip-flop circuit; sensors exploit metastable state that lies between two stable states (corresponding to binary logic states) of flip-flop circuit. Voltages of metastable states vary with exposures of gas-sensitive resistors.

  9. TOPICAL REVIEW Nanoscale memory devices

    NASA Astrophysics Data System (ADS)

    Chung, Andy; Deen, Jamal; Lee, Jeong-Soo; Meyyappan, M.

    2010-10-01

    This article reviews the current status and future prospects for the use of nanomaterials and devices in memory technology. First, the status and continuing scaling trends of the flash memory are discussed. Then, a detailed discussion on technologies trying to replace flash in the near-term is provided. This includes phase change random access memory, Fe random access memory and magnetic random access memory. The long-term nanotechnology prospects for memory devices include carbon-nanotube-based memory, molecular electronics and memristors based on resistive materials such as TiO2.

  10. Quantification of the memory imprint effect for a charged particle environment

    NASA Technical Reports Server (NTRS)

    Bhuva, B. L.; Johnson, R. L., Jr.; Gyurcsik, R. S.; Kerns, S. E.; Fernald, K. W.

    1987-01-01

    The effects of total accumulated dose on the single-event vulnerability of NMOS resistive-load SRAMs are investigated. The bias-dependent shifts in device parameters can imprint the memory state present during exposure or erase the imprinted state. Analysis of these effects is presented along with an analytic model developed for the quantification of these effects. The results indicate that the imprint effect is dominated by the difference in the threshold voltage of the n-channel devices.

  11. Light sensitivity of a one transistor-one capacitor memory cell when used as a micromirror actuator in projector applications

    NASA Astrophysics Data System (ADS)

    Huffman, James Douglas

    2001-11-01

    The most important issue facing the future business success of the Digital Micromirror Device or DMD™ produced by Texas Instruments is the cost of the actual device. As the business and consumer markets call for higher resolution displays, the array size will have to be increased to incorporate more pixels. The manufacturing costs associated with building these higher resolution displays follow an exponential relation with the number of pixels due to yield loss and reduced number of chips per silicon wafer. Each pixel is actuated by electrostatics that are provided by a memory cell that is built in the underlying silicon substrate. One way to decrease cost of the wafer is to change the memory cell architecture from a static random access configuration or SRAM to a dynamic random access configuration or DRAM. This change has the benefits of having fewer components per area and a lower metal density. This reduction in the component count and metal density has a dramatic effect on the yield of the memory array by reducing the particle sensitivity of the underlying cell. The main drawback to using a DRAM configuration in a display application is the light sensitivity of a charge storage device built in the silicon substrate. As the photons pass through the mechanical micromirrors and illuminate the DRAM cell, the effective electrostatic potential of the memory element used for the mirror actuation is reduced. This dissertation outlines the issues associated with the light sensitivity of a DRAM memory cell as the actuation element for a micromirror. The concept of charge depletion on a silicon capacitor due to recombination of photogenerated carriers is explored and experimentally verified. The effects of the reduced potential on the capacitor on the micromirror are also explored. Optical modeling is used to determine the incoming photon flux to determine the benefits of adding a charge recombination region as part of the DRAM memory cell. Several options are explored

  12. Empirical modeling of Single-Event Upset (SEU) in NMOS depletion-mode-load static RAM (SRAM) chips

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.; Smith, S. L.; Atwood, G. E.

    1986-01-01

    A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.

  13. Ease of Access to List Items in Short-Term Memory Depends on the Order of the Recognition Probes

    ERIC Educational Resources Information Center

    Lange, Elke B.; Cerella, John; Verhaeghen, Paul

    2011-01-01

    We report data from 4 experiments using a recognition design with multiple probes to be matched to specific study positions. Items could be accessed rapidly, independent of set size, when the test order matched the study order (forward condition). When the order of testing was random, backward, or in a prelearned irregular sequence (reordered…

  14. ViSA: A Neurodynamic Model for Visuo-Spatial Working Memory, Attentional Blink, and Conscious Access

    ERIC Educational Resources Information Center

    Simione, Luca; Raffone, Antonino; Wolters, Gezinus; Salmas, Paola; Nakatani, Chie; Belardinelli, Marta Olivetti; van Leeuwen, Cees

    2012-01-01

    Two separate lines of study have clarified the role of selectivity in conscious access to visual information. Both involve presenting multiple targets and distracters: one "simultaneously" in a spatially distributed fashion, the other "sequentially" at a single location. To understand their findings in a unified framework, we propose a…

  15. Self-compliance Pt/HfO2/Ti/Si one-diode-one-resistor resistive random access memory device and its low temperature characteristics

    NASA Astrophysics Data System (ADS)

    Lu, Chao; Yu, Jue; Chi, Xiao-Wei; Lin, Guang-Yang; Lan, Xiao-Ling; Huang, Wei; Wang, Jian-Yuan; Xu, Jian-Fang; Wang, Chen; Li, Cheng; Chen, Song-Yan; Liu, Chunli; Lai, Hong-Kai

    2016-04-01

    A bipolar one-diode-one-resistor (1D1R) device with a Pt/HfO2/Ti/n-Si(001) structure was demonstrated. The 1D1R resistive random access memory (RRAM) device consists of a Ti/n-Si(001) diode and a Pt/HfO2/Ti resistive switching cell. By using the Ti layer as the shared electrode for both the diode and the resistive switching cell, the 1D1R device exhibits the property of stable self-compliance and the characteristic of robust resistive switching with high uniformity. The high/low resistance ratio reaches 103. The electrical RESET/SET curve does not deteriorate after 68 loops. Low-temperature studies show that the 1D1R RRAM device has a critical working temperature of 250 K, and at temperatures below 250 K, the device fails to switch its resistances.

  16. Low leakage Ru-strontium titanate-Ru metal-insulator-metal capacitors for sub-20 nm technology node in dynamic random access memory

    NASA Astrophysics Data System (ADS)

    Popovici, M.; Swerts, J.; Redolfi, A.; Kaczer, B.; Aoulaiche, M.; Radu, I.; Clima, S.; Everaert, J.-L.; Van Elshocht, S.; Jurczak, M.

    2014-02-01

    Improved metal-insulator-metal capacitor (MIMCAP) stacks with strontium titanate (STO) as dielectric sandwiched between Ru as top and bottom electrode are shown. The Ru/STO/Ru stack demonstrates clearly its potential to reach sub-20 nm technology nodes for dynamic random access memory. Downscaling of the equivalent oxide thickness, leakage current density (Jg) of the MIMCAPs, and physical thickness of the STO have been realized by control of the Sr/Ti ratio and grain size using a heterogeneous TiO2/STO based nanolaminate stack deposition and a two-step crystallization anneal. Replacement of TiN with Ru as both top and bottom electrodes reduces the amount of electrically active defects and is essential to achieve a low leakage current in the MIM capacitor.

  17. Low leakage Ru-strontium titanate-Ru metal-insulator-metal capacitors for sub-20 nm technology node in dynamic random access memory

    SciTech Connect

    Popovici, M. Swerts, J.; Redolfi, A.; Kaczer, B.; Aoulaiche, M.; Radu, I.; Clima, S.; Everaert, J.-L.; Van Elshocht, S.; Jurczak, M.

    2014-02-24

    Improved metal-insulator-metal capacitor (MIMCAP) stacks with strontium titanate (STO) as dielectric sandwiched between Ru as top and bottom electrode are shown. The Ru/STO/Ru stack demonstrates clearly its potential to reach sub-20 nm technology nodes for dynamic random access memory. Downscaling of the equivalent oxide thickness, leakage current density (J{sub g}) of the MIMCAPs, and physical thickness of the STO have been realized by control of the Sr/Ti ratio and grain size using a heterogeneous TiO{sub 2}/STO based nanolaminate stack deposition and a two-step crystallization anneal. Replacement of TiN with Ru as both top and bottom electrodes reduces the amount of electrically active defects and is essential to achieve a low leakage current in the MIM capacitor.

  18. Evaluation of in-plane local stress distribution in stacked IC chip using dynamic random access memory cell array for highly reliable three-dimensional IC

    NASA Astrophysics Data System (ADS)

    Tanikawa, Seiya; Kino, Hisashi; Fukushima, Takafumi; Koyanagi, Mitsumasa; Tanaka, Tetsu

    2016-04-01

    As three-dimensional (3D) ICs have many advantages, IC performances can be enhanced without scaling down of transistor size. However, 3D IC has mechanical stresses inside Si substrates owing to its 3D stacking structure, which induces negative effects on transistor performances such as carrier mobility changes. One of the mechanical stresses is local bending stress due to organic adhesive shrinkage among stacked IC chips. In this paper, we have proposed an evaluation method for in-plane local stress distribution in the stacked IC chips using retention time modulation of a dynamic random access memory (DRAM) cell array. We fabricated a test structure composed of a DRAM chip bonded on a Si interposer with dummy Cu/Sn microbumps. As a result, we clarified that the DRAM cell array can precisely evaluate the in-plane local stress distribution in the stacked IC chips.

  19. The reason for the increased threshold switching voltage of SiO2 doped Ge2Sb2Te5 thin films for phase change random access memory

    NASA Astrophysics Data System (ADS)

    Ryu, Seung Wook; Lee, Jong Ho; Ahn, Young Bae; Kim, Choon Hwan; Yang, Bong Seob; Kim, Gun Hwan; Kim, Soo Gil; Lee, Se-Ho; Hwang, Cheol Seong; Kim, Hyeong Joon

    2009-09-01

    This study examined the threshold switching voltage (VT) of 150 nm thick SiO2 doped Ge2Sb2Te5 (SGST) films for phase change random access memory applications. The VT of the SGST films increased from ˜0.9 V (for GST) to ˜1.5 V with increasing SiO2 content. The optical band gap and Urbach edge of the SGST films were similar regardless of the SiO2 concentration. The dielectric constant decreased by ˜37% and the electrical resistivity increased by ˜19%. The increase in VT of SGST films is associated with an effective increase in electric field and the decreased generation rate caused by impact ionization.

  20. Phase transformation behaviors of SiO2 doped Ge2Sb2Te5 films for application in phase change random access memory

    NASA Astrophysics Data System (ADS)

    Ryu, Seung Wook; Oh, Jin Ho; Lee, Jong Ho; Choi, Byung Joon; Kim, Won; Hong, Suk Kyoung; Hwang, Cheol Seong; Kim, Hyeong Joon

    2008-04-01

    The improvement in the phase change characteristics of Ge2Sb2Te5 (GST) films for phase change random access memory applications was investigated by doping the GST films with SiO2 using cosputtering at room temperature. As the sputtering power of SiO2 increased from 0to150W, the activation energy for crystallization increased from 2.1±0.2to3.1±0.15eV. SiO2 inhibited the crystallization of the amorphous GST films, which improved the long term stability of the metastable amorphous phase. The melting point decreased with increasing concentration of SiO2, which reduced the power consumption as well as the reset current.

  1. Multi-step resistive switching behavior of Li-doped ZnO resistance random access memory device controlled by compliance current

    NASA Astrophysics Data System (ADS)

    Lin, Chun-Cheng; Tang, Jian-Fu; Su, Hsiu-Hsien; Hong, Cheng-Shong; Huang, Chih-Yu; Chu, Sheng-Yuan

    2016-06-01

    The multi-step resistive switching (RS) behavior of a unipolar Pt/Li0.06Zn0.94O/Pt resistive random access memory (RRAM) device is investigated. It is found that the RRAM device exhibits normal, 2-, 3-, and 4-step RESET behaviors under different compliance currents. The transport mechanism within the device is investigated by means of current-voltage curves, in-situ transmission electron microscopy, and electrochemical impedance spectroscopy. It is shown that the ion transport mechanism is dominated by Ohmic behavior under low electric fields and the Poole-Frenkel emission effect (normal RS behavior) or Li+ ion diffusion (2-, 3-, and 4-step RESET behaviors) under high electric fields.

  2. Correlative transmission electron microscopy and electrical properties study of switchable phase-change random access memory line cells

    SciTech Connect

    Oosthoek, J. L. M.; Kooi, B. J.; Voogt, F. C.; Attenborough, K.; Verheijen, M. A.; Hurkx, G. A. M.; Gravesteijn, D. J.

    2015-02-14

    Phase-change memory line cells, where the active material has a thickness of 15 nm, were prepared for transmission electron microscopy (TEM) observation such that they still could be switched and characterized electrically after the preparation. The result of these observations in comparison with detailed electrical characterization showed (i) normal behavior for relatively long amorphous marks, resulting in a hyperbolic dependence between SET resistance and SET current, indicating a switching mechanism based on initially long and thin nanoscale crystalline filaments which thicken gradually, and (ii) anomalous behavior, which holds for relatively short amorphous marks, where initially directly a massive crystalline filament is formed that consumes most of the width of the amorphous mark only leaving minor residual amorphous regions at its edges. The present results demonstrate that even in (purposely) thick TEM samples, the TEM sample preparation hampers the probability to observe normal behavior and it can be debated whether it is possible to produce electrically switchable TEM specimen in which the memory cells behave the same as in their original bulk embedded state.

  3. Chronic restricted access to 10% sucrose solution in adolescent and young adult rats impairs spatial memory and alters sensitivity to outcome devaluation.

    PubMed

    Kendig, Michael D; Boakes, Robert A; Rooney, Kieron B; Corbit, Laura H

    2013-08-15

    Although increasing consumption of sugar drinks is recognized as a significant public health concern, little is known about (a) the cognitive effects resulting from sucrose consumption; and (b) whether the long-term effects of sucrose consumption are more pronounced for adolescents. This experiment directly compared performance on a task of spatial learning and memory (the Morris Water Maze) and sensitivity to outcome devaluation following 28 days of 2-h/day access to a 10% sucrose solution in adolescent and young-adult Wistar rats. Sucrose groups developed elevated fasting blood glucose levels after the diet intervention, despite drawing <15% of calories from sucrose and gaining no more weight than controls. In subsequent behavioral testing, sucrose groups were impaired on the Morris Water Maze, with some residual deficits in spatial memory observed more than 6 weeks after the end of sucrose exposure. Further, results from outcome devaluation testing indicated that in the older cohort of rats, those fed sucrose showed reduced sensitivity to devaluation of the outcome, suggestive of differences in instrumental learning following sucrose exposure. Data provide strong evidence that sucrose consumption can induce deficits in spatial cognition and reward-oriented behavior at levels that resemble patterns of sugar drink consumption in young people, and which can remain long after exposure. PMID:23954407

  4. Basic Performance of a Logic Intellectual Property Compatible Embedded Dynamic Random Access Memory with Cylinder Capacitors in Low-k/Cu Back End on the Line Layers

    NASA Astrophysics Data System (ADS)

    Kume, Ippei; Inoue, Naoya; Hijioka, Ken'ichiro; Kawahara, Jun; Takeda, Kouichi; Furutake, Naoya; Shirai, Hiroki; Kazama, Kenya; Kuwabara, Shin'ichi; Watarai, Msasatoshi; Sakoh, Takashi; Takahashi, Takafumi; Ogura, Takashi; Taiji, Toshiji; Kasama, Yoshiko; Sakamoto, Misato; Hane, Masami; Hayashi, Yoshihiro

    2012-02-01

    We have confirmed the basic performance of a new logic intellectual property (IP) compatible (LIC) embedded dynamic random access memory (eDRAM) with cylinder capacitors in the low-k/Cu back end on the line (BEOL) layers. The LIC-eDRAM reduces the contact (CT) height, or essentially the RC delays due to the parasitic component to the contact. By circuit simulation, a 28-nm-node LIC-eDRAM with the reduced CT height controls the logic delay with Δτd < 5% to that of 28-nm-node standard complementary metal oxide semiconductor (CMOS) logics, enabling us ensure the logic IP compatibility. This was confirmed also by a 40-nm-node LIC-eDRAM test-chip fabricated. The 40-nm-node inverter delays in the test-chip were controlled actually within Δτd < 5%, referred to those of a pure-CMOS logic LSI. Meanwhile the retention time of the DRAM macro was in the range of milliseconds, which has no difference to that of a conventional eDRAM with a capacitor-on-bitline (COB) structure. The LIC-eDRAM is one type of BEOL memory on standard CMOS devices, and is sustainable for widening eDRAM applications combined with a variety of leading-edge CMOS logic IPs, especially beyond 28-nm-nodes.

  5. Highly flexible nearest-neighbor-search associative memory with integrated k nearest neighbor classifier, configurable parallelism and dual-storage space

    NASA Astrophysics Data System (ADS)

    An, Fengwei; Mihara, Keisuke; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2016-04-01

    VLSI-implementations are often applied to solve the high computational cost of pattern matching but have usually low flexibility for satisfying different target applications. In this paper, a digital word-parallel associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern recognition, is reported applying the squared Euclidean distance measure. The reported architecture features reconfigurable parallelism, dual-storage space to achieve a flexible number of reference vectors, and a dedicated majority vote circuit. Programmable switching circuits, located between vector components, enable scalability of the searching parallelism by configuring the reference feature-vector dimensionality. A pipelined storage with dual static-random-access-memory (SRAM) cells for each unit and an intermediate winner control circuit are designed to extend the applicability by improving the flexibility of the reference storage. A test chip in 180 nm CMOS technology, which has 32 rows, 4 elements in each row and 2-parallel 8-bit dual-components in each element, consumes altogether 61.4 mW and in particular only 11.9 mW during the reconfigurable KNN classification (at 45.58 MHz and 1.8 V).

  6. Verification of E-Beam direct write integration into 28nm BEOL SRAM technology

    NASA Astrophysics Data System (ADS)

    Hohle, Christoph; Choi, Kang-Hoon; Gutsch, Manuela; Hanisch, Norbert; Seidel, Robert; Steidel, Katja; Thrun, Xaver; Werner, Thomas

    2015-03-01

    Electron beam direct write lithography (EBDW) potentially offers advantages for low-volume semiconductor manufacturing, rapid prototyping or design verification due to its high flexibility without the need of costly masks. However, the integration of this advanced patterning technology into complex CMOS manufacturing processes remains challenging. The low throughput of today's single e-Beam tools limits high volume manufacturing applications and maturity of parallel (multi) beam systems is still insufficient [1,2]. Additional concerns like transistor or material damage of underlying layers during exposure at high electron density or acceleration voltage have to be addressed for advanced technology nodes. In the past we successfully proved that potential degradation effects of high-k materials or ULK shrink can be neglected and were excluded by demonstrating integrated electrical results of 28nm node transistor and BEOL performance following 50kV electron beam dry exposure [3]. Here we will give an update on the integration of EBDW in the 300mm CMOS manufacturing processes of advanced integrated circuits at the 28nm SRAM node of GLOBALFOUNDRIES Dresden. The work is an update to what has been previously published [4]. E-beam patterning results of BEOL full chip metal and via layers with a dual damascene integration scheme using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMSCNT are demonstrated. For the patterning of the Metal layer a Mix & Match concept based on the sequence litho - etch -litho -etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. Etch results are shown and compared to the POR. Results are also shown on overlay performance and optimized e-Beam exposure time using most advanced data prep solutions and resist processes. The patterning results have been verified using fully integrated electrical measurement of metal lines and vias on wafer level. In

  7. The role of internal structure in the anomalous switching dynamics of metal-oxide/polymer resistive random access memories

    NASA Astrophysics Data System (ADS)

    Rocha, Paulo R. F.; Kiazadeh, Asal; De Leeuw, Dago M.; Meskers, Stefan C. J.; Verbakel, Frank; Taylor, David M.; Gomes, Henrique L.

    2013-04-01

    The dynamic response of a non-volatile, bistable resistive memory fabricated in the form of Al2O3/polymer diodes has been probed in both the off- and on-state using triangular and step voltage profiles. The results provide insight into the wide spread in switching times reported in the literature and explain an apparently anomalous behaviour of the on-state, namely the disappearance of the negative differential resistance region at high voltage scan rates which is commonly attributed to a "dead time" phenomenon. The off-state response follows closely the predictions based on a classical, two-layer capacitor description of the device. As voltage scan rates increase, the model predicts that the fraction of the applied voltage, Vox, appearing across the oxide decreases. Device responses to step voltages in both the off- and on-state show that switching events are characterized by a delay time. Coupling such delays to the lower values of Vox attained during fast scan rates, the anomalous observation in the on-state that, device currents decrease with increasing voltage scan rate, is readily explained. Assuming that a critical current is required to turn off a conducting channel in the oxide, a tentative model is suggested to explain the shift in the onset of negative differential resistance to lower voltages as the voltage scan rate increases. The findings also suggest that the fundamental limitations on the speed of operation of a bilayer resistive memory are the time- and voltage-dependences of the switch-on mechanism and not the switch-off process.

  8. Retracing Memories

    ERIC Educational Resources Information Center

    Harrison, David L.

    2005-01-01

    There are plenty of paths to poetry but few are as accessible as retracing ones own memories. When students are asked to write about something they remember, they are given them the gift of choosing from events that are important enough to recall. They remember because what happened was funny or scary or embarrassing or heartbreaking or silly.…

  9. Fault Tolerance Implementation within SRAM Based FPGA Designs based upon Single Event Upset Occurrence Rates

    NASA Technical Reports Server (NTRS)

    Berg, Melanie

    2006-01-01

    Emerging technology is enabling the design community to consistently expand the amount of functionality that can be implemented within Integrated Circuits (ICs). As the number of gates placed within an FPGA increases, the complexity of the design can grow exponentially. Consequently, the ability to create reliable circuits has become an incredibly difficult task. In order to ease the complexity of design completion, the commercial design community has developed a very rigid (but effective) design methodology based on synchronous circuit techniques. In order to create faster, smaller and lower power circuits, transistor geometries and core voltages have decreased. In environments that contain ionizing energy, such a combination will increase the probability of Single Event Upsets (SEUs) and will consequently affect the state space of a circuit. In order to combat the effects of radiation, the aerospace community has developed several "Hardened by Design" (fault tolerant) design schemes. This paper will address design mitigation schemes targeted for SRAM Based FPGA CMOS devices. Because some mitigation schemes may be over zealous (too much power, area, complexity, etc.. . .), the designer should be conscious that system requirements can ease the amount of mitigation necessary for acceptable operation. Therefore, various degrees of Fault Tolerance will be demonstrated along with an analysis of its effectiveness.

  10. Comparative study of MC-50 and ANITA neutron beams by using 55 nm SRAM

    NASA Astrophysics Data System (ADS)

    Baeg, Sanghyeon; Lee, Soonyoung; Bak, Geun Yong; Jeong, Hyunsoo; Jeon, Sang Hoon

    2012-09-01

    Single event upset (SEU) is mainly caused by neutrons in the terrestrial environment. In addition, SEU effects become more and more problematic as technology scales. It is, therefore, important to understand the SEU behaviors of semiconductor devices under neutron reactions. ANITA (atmospheric-like neutrons from thick target) in TSL (The Svedberg Laboratory), Sweden, resembles the neutron energy and flux spectrum to neutrons at the terrestrial level and are typically used to estimate the soft error rate (SER). On the other hand, the neutron energy and flux spectrum from the MC-50 cyclotron at KIRAMS (Korea Institute of Radiological & Medical Sciences) differs greatly from the atmospheric environment. The main objective of this work is finding the efficacy of the neutron beam at KIRAMS for a SEU analysis by using a comparative analysis; 55 nm SRAM is used to determine SEU difference under the beams at two different locations. Since MCU (multi-cell upset) is the dominant effect in emerging technologies with smaller critical charges, the MCU cross sections from the two different beam tests are compared.

  11. Magnetic bubble domain memories

    NASA Technical Reports Server (NTRS)

    Ypma, J. E.

    1974-01-01

    Some attractive features of Bubble Domain Memory and its relation to existing technologies are discussed. Two promising applications are block access mass memory and tape recorder replacement. The required chip capabilities for these uses are listed, and the specifications for a block access mass memory designed to fit between core and HPT disk are presented. A feasibility model for a tape recorder replacement is introduced.

  12. Novel synaptic memory device for neuromorphic computing

    PubMed Central

    Mandal, Saptarshi; El-Amin, Ammaarah; Alexander, Kaitlyn; Rajendran, Bipin; Jha, Rashmi

    2014-01-01

    This report discusses the electrical characteristics of two-terminal synaptic memory devices capable of demonstrating an analog change in conductance in response to the varying amplitude and pulse-width of the applied signal. The devices are based on Mn doped HfO2 material. The mechanism behind reconfiguration was studied and a unified model is presented to explain the underlying device physics. The model was then utilized to show the application of these devices in speech recognition. A comparison between a 20 nm × 20 nm sized synaptic memory device with that of a state-of-the-art VLSI SRAM synapse showed ~10× reduction in area and >106 times reduction in the power consumption per learning cycle. PMID:24939247

  13. Retention modeling for ultra-thin density of Cu-based conductive bridge random access memory (CBRAM)

    NASA Astrophysics Data System (ADS)

    Aga, Fekadu Gochole; Woo, Jiyong; Lee, Sangheon; Song, Jeonghwan; Park, Jaesung; Park, Jaehyuk; Lim, Seokjae; Sung, Changhyuck; Hwang, Hyunsang

    2016-02-01

    We investigate the effect of Cu concentration On-state resistance retention characteristics of W/Cu/Ti/HfO2/Pt memory cell. The development of RRAM device for application depends on the understanding of the failure mechanism and the key parameters for device optimization. In this study, we develop analytical expression for cations (Cu+) diffusion model using Gaussian distribution for detailed analysis of data retention time at high temperature. It is found that the improvement of data retention time depends not only on the conductive filament (CF) size but also on Cu atoms concentration density in the CF. Based on the simulation result, better data retention time is observed for electron wave function associated with Cu+ overlap and an extended state formation. This can be verified by analytical calculation of Cu atom defects inside the filament, based on Cu+ diffusion model. The importance of Cu diffusion for the device reliability and the corresponding local temperature of the filament were analyzed by COMSOL Multiphysics simulation.

  14. High LET Single Event Upset Cross Sections For Bulk and SOI CMOS SRAMs

    SciTech Connect

    McDaniel, F.D.; Doyle, B.L.; Vizkelethy, G.; Dodd, P.E.; Rossi, P.

    2003-08-26

    Electronics in spacecraft and satellites are exposed to high-energy cosmic radiation. In addition, terrestrial radiation can also affect earth-based electronics. To study the effects of radiation upon integrated circuits and to insure the reliability of electronic devices, cosmic and terrestrial radiations are simulated with ion beams from particle accelerators. A new, higher Linear Energy Transfer (LET) acceleration system for heavy ions has been developed at Sandia National Laboratories. Heavy ions from a 6.5 MV EN tandem Van de Graaff accelerator at 0.25 MeV/amu are injected into a two-stage Radio Frequency Quadrupole (RFQ) linac, which accelerates the ions to 1.9 MeV/amu. These ions together with those from the Brookhaven National Laboratory MP Tandem have been used to measure single event upset (SEU) cross sections as a function of LET for both bulk and Silicon on Insulator (SOI) Complementary Metal Oxide Semiconductor, Static Random Access Memories. The magnitudes of these cross sections indicate that the upsets in both the SOI and bulk parts are caused by OFF-drain strikes.

  15. Reproducible resistive switching in nonstoichiometric nickel oxide films grown by rf reactive sputtering for resistive random access memory applications

    SciTech Connect

    Park, Jae-Wan; Park, Jong-Wan; Kim, Dal-Young; Lee, Jeon-Kook

    2005-09-15

    Ni{sub 1-{delta}}O binary oxide films were deposited on Pt/Ti/SiO{sub 2}/Si substrates by radio-frequency reactive magnetron sputtering. The NiO-based metal-oxide-metal structures were fabricated for measurement of electrical properties. The electrical properties of the Pt/Ni{sub 1-{delta}}O/Pt structure as a function of growth temperature were investigated. The growth temperature was varied from room temperature to 400 deg. C. From all samples, negative resistance phenomenon and nonvolatile memory switching behavior were observed. The ratios between the high-resistance state (OFF state) and the low-resistance state (ON state) were larger than. 10{sup 2}. As the growth temperature was increased, both SET and RESET voltages increased due to the decrease of defects in nickel oxide films. On the basis of x-ray diffraction patterns, we confirmed that the defects in Ni{sub 1-{delta}}O film decreased with increasing the growth temperature due to sufficient diffusion and redistribution of adatoms. X-ray photoelectron spectroscopy and Rutherford backscattering spectroscopy analysis revealed that the nickel oxide films were Ni deficient and that Ni had three different Ni bond states caused by various defects in nickel oxide films. In order to investigate the influence of the upper limit of SET current (i.e., Compliance SET current), the compliance SET current was varied from 1 to 50 mA. This result showed that the ON-state current and the RESET voltage were strongly dependent on the magnitude of the compliance SET current. As the compliance SET current was increased, both the ON-state current and the RESET voltage increased due to the increase of the conducting path. The results suggest that the resistance switching behavior is related to the formation and fracture of the conducting path which is composed of defects in the nickel oxide film.

  16. Analysis of static noise margin improvement for low voltage SRAM composed of nano-scale MOSFETs with ideal subthreshold factor and small variability

    NASA Astrophysics Data System (ADS)

    Tanaka, Chika; Saitoh, Masumi; Ota, Kensuke; Numata, Toshinori

    2015-07-01

    An ultra-low voltage performance of nanowire-transistors-based SRAM cell is investigated using the SPICE model parameters extracted from measurement data. The impact of S-factor and threshold voltage variations on the static noise margin and the minimum operating voltage is evaluated in nanowire transistor as well as in planar bulk transistor and quasi-planar bulk transistor. The performance benefits of undoped nanowire-transistor-based SRAM are measured in terms of the read stability for low voltage and low off leakage current operation.

  17. Modeling of an Oil-Free Carbon Dioxide Compressor Using Sanderson-Rocker Arm Motion (S-RAM) Mechanism

    NASA Astrophysics Data System (ADS)

    Yang, Bin; Kurtulus, Orkan; Groll, Eckhard A.

    2015-08-01

    A simulation model to predict the performance of a prototype CO2 compressor is presented. This prototype compressor employs the Sanderson-Rocker Arm Motion (S-RAM) mechanism, which converts the rotary motion of the shaft into a linear reciprocating motion of the cylinders. The piston stroke can be variable by changing the incline angle between the connecting rod and compressor main shaft centerline. The compressor model is mainly composed of two main sub-models simulating the kinematics of the drive mechanism and the compression process. A valve sub-model is included in the compression process model.

  18. Residual Clamping Force and Dynamic Random Access Memory Data Retention Improved by Gate Tungsten Etch Dechucking Condition in a Bipolar Electrostatic Chuck

    NASA Astrophysics Data System (ADS)

    Lee, Chung-Yuan; Lai, Chao-Sung; Yang, Chia-Ming; Wang, David HL; Lin, Betty; Lee, Siimon; Huang, Chi-Hung; Wei, Chen Chang

    2012-08-01

    It was found that the residual clamping force of bipolar electrostatic chucks created by the residual charge between a wafer and an electrode would not only cause a wafer sticking problem but also degrade dynamic random access memory (DRAM) data retention performance. The residual clamping force and data retention fail bit count (FBC) of DRAM showed strong correlations to the gate tungsten etch dechucking process condition. Wafer sticking only degraded DRAM cell retention performance, and did not influence any in-line measurement or electrical parameters. Electrical characterization analysis of the FBC proved that the retention loss was mainly due to junction leakage rather than gate-induced-drain-leakage current. A new approach was proposed to suppress this leakage by introducing N2 gas instead of O2 to supply more plasma charges for neutralizing the wafer surface residual charges. The wafer shift dynamic alignment (DA) offset and retention FBC could be reduced by 50 and 40%, respectively. Poor data retention was suspected because of the compressive stress caused by wafer sticking DA shift resulting in a high electric field at the junction and an increase in junction leakage at the storage node.

  19. Sustained Resistive Switching in a Single Cu:7,7,8,8-tetracyanoquinodimethane Nanowire: A Promising Material for Resistive Random Access Memory

    NASA Astrophysics Data System (ADS)

    Basori, Rabaya; Kumar, Manoranjan; Raychaudhuri, Arup K.

    2016-06-01

    We report a new type of sustained and reversible unipolar resistive switching in a nanowire device made from a single strand of Cu:7,7,8,8-tetracyanoquinodimethane (Cu:TCNQ) nanowire (diameter <100 nm) that shows high ON/OFF ratio (~103), low threshold voltage of switching (~3.5 V) and large cycling endurance (>103). This indicates a promising material for high density resistive random access memory (ReRAM) device integration. Switching is observed in Cu:TCNQ single nanowire devices with two different electrode configuration: symmetric (C-Pt/Cu:TCNQ/C-Pt) and asymmetric (Cu/Cu:TCNQ/C-Pt), where contacts connecting the nanowire play an important role. This report also developed a method of separating out the electrode and material contributions in switching using metal-semiconductor-metal (MSM) device model along with a direct 4-probe resistivity measurement of the nanowire in the OFF as well as ON state. The device model was followed by a phenomenological model of current transport through the nanowire device which shows that lowering of potential barrier at the contacts likely occur due to formation of Cu filaments in the interface between nanowire and contact electrodes. We obtain quantitative agreement of numerically analyzed results with the experimental switching data.

  20. Power- and Low-Resistance-State-Dependent, Bipolar Reset-Switching Transitions in SiN-Based Resistive Random-Access Memory.

    PubMed

    Kim, Sungjun; Park, Byung-Gook

    2016-12-01

    A study on the bipolar-resistive switching of an Ni/SiN/Si-based resistive random-access memory (RRAM) device shows that the influences of the reset power and the resistance value of the low-resistance state (LRS) on the reset-switching transitions are strong. For a low LRS with a large conducting path, the sharp reset switching, which requires a high reset power (>7 mW), was observed, whereas for a high LRS with small multiple-conducting paths, the step-by-step reset switching with a low reset power (<7 mW) was observed. The attainment of higher nonlinear current-voltage (I-V) characteristics in terms of the step-by-step reset switching is due to the steep current-increased region of the trap-controlled space charge-limited current (SCLC) model. A multilevel cell (MLC) operation, for which the reset stop voltage (V STOP) is used in the DC sweep mode and an incremental amplitude is used in the pulse mode for the step-by-step reset switching, is demonstrated here. The results of the present study suggest that well-controlled conducting paths in a SiN-based RRAM device, which are not too strong and not too weak, offer considerable potential for the realization of low-power and high-density crossbar-array applications. PMID:27518231

  1. Correlation of anomalous write error rates and ferromagnetic resonance spectrum in spin-transfer-torque-magnetic-random-access-memory devices containing in-plane free layers

    SciTech Connect

    Evarts, Eric R.; Rippard, William H.; Pufall, Matthew R.; Heindl, Ranko

    2014-05-26

    In a small fraction of magnetic-tunnel-junction-based magnetic random-access memory devices with in-plane free layers, the write-error rates (WERs) are higher than expected on the basis of the macrospin or quasi-uniform magnetization reversal models. In devices with increased WERs, the product of effective resistance and area, tunneling magnetoresistance, and coercivity do not deviate from typical device properties. However, the field-swept, spin-torque, ferromagnetic resonance (FS-ST-FMR) spectra with an applied DC bias current deviate significantly for such devices. With a DC bias of 300 mV (producing 9.9 × 10{sup 6} A/cm{sup 2}) or greater, these anomalous devices show an increase in the fraction of the power present in FS-ST-FMR modes corresponding to higher-order excitations of the free-layer magnetization. As much as 70% of the power is contained in higher-order modes compared to ≈20% in typical devices. Additionally, a shift in the uniform-mode resonant field that is correlated with the magnitude of the WER anomaly is detected at DC biases greater than 300 mV. These differences in the anomalous devices indicate a change in the micromagnetic resonant mode structure at high applied bias.

  2. Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition.

    PubMed

    Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

    2016-01-01

    With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption. PMID:27312225

  3. Investigation of Cr0.06(Sb4Te)0.94 alloy for high-speed and high-data-retention phase change random access memory applications

    NASA Astrophysics Data System (ADS)

    Li, Le; Song, Sannian; Zhang, Zhonghua; Song, Zhitang; Cheng, Yan; Lv, Shilong; Wu, Liangcai; Liu, Bo; Feng, Songlin

    2015-08-01

    The effects of Cr doping on the structural and electrical properties of Cr x (Sb4Te)1- x materials have been investigated in order to solve the contradiction between thermal stability and fast crystallization speed of Sb4Te alloys. Cr0.06(Sb4Te)0.94 alloy is considered to be a potential candidate for phase change random access memory (PCM), as evidenced by a higher crystallization temperature (204 °C), a better data retention ability (137.6 °C for 10 years), a lower melting point (558 °C), a lower energy consumption, and a faster switching speed in comparison with those of Ge2Sb2Te5. A reversible switching between set and reset states can be realized by an electric pulse as short as 5 ns for Cr0.06(Sb4Te)0.94-based PCM cell. In addition, Cr0.06(Sb4Te)0.94 shows good endurance up to 1.1 × 104 cycles with a resistance ratio of about two orders of magnitude.

  4. Highly Reliable 0.15 μm/14 F2 Cell Ferroelectric Random Access Memory Capacitor Using SrRuO3 Buffer Layer

    NASA Astrophysics Data System (ADS)

    Heo, Jang‑Eun; Bae, Byoung‑Jae; Yoo, Dong‑Chul; Nam, Sang‑Don; Lim, Ji‑Eun; Im, Dong‑Hyun; Joo, Suk‑Ho; Jung, Yong‑Ju; Choi, Suk‑Hun; Park, Soon‑Oh; Kim, Hee‑Seok; Chung, U‑In; Moon, Joo‑Tae

    2006-04-01

    We investigated a novel technique of modifying the interface between a Pb(ZrxTi1-x)O3 (PZT) thin film and electrodes for high density 64 Mbit ferroelectric random access memory (FRAM) device. Using a SrRuO3 buffer layer, we successfully developed highly reliable 0.15 μm/14 F2 cell FRAM capacitors with 75-nm-thick polycrystalline PZT thin films. The SrRuO3 buffer layer greatly enhanced ferroelectric characteristics due to the decrease in interfacial defect density. In PZT capacitors with a total thickness of 180 nm for whole capacitor stack, a remnant polarization of approximately 42 μC/cm2 was measured with a 1.4 V operation. In addition, an opposite state remnant polarization loss of less than 15% was observed after baking at 150 °C for 100 h. In particular, we found that the SrRuO3 buffer layer also played a key role in inhibiting the diffusion of Pb and O from the PZT thin films.

  5. Integration and Electrical Properties of Novel Ferroelectric Capacitors for 0.25 μm 1 Transistor 1 Capacitor Ferroelectric Random Access Memory (1T1C FRAM)

    NASA Astrophysics Data System (ADS)

    Song, Y. J.; Jang, N. W.; Jung, D. J.; Kim, H. H.; Joo, H. J.; Lee, S. Y.; Lee, K. M.; Joo, S. H.; Park, S. O.; Kim, Kinam

    2002-04-01

    Since the space margin between capacitors has been greatly reduced in 32 Mb high-density ferroelectric random access memory (FRAM) with a 0.25 μm design rule, considering the limitation of current etching technology, the stack height of ferroelectric capacitors should be minimized for stable node separation. In this paper, novel capacitors with a total thickness of 4000 Å were prepared using a seeding layer, low temperature processing, and optimal top electrode annealing. The 1000 Å Pb(Zr1-xTix)O3 (PZT) films showed excellent structural and ferroelectric properties such as strong (111) orientation and large remanent polarization of 40 μC/cm2. The low stack capacitors were then implemented into 0.6 μm and prototype 0.25 μm FRAM. Compared to a conventional capacitor stack, the ferroelectric capacitors exhibited adequate sensing margin of 250 fC, thus giving rise to a fully working die of 4 Mb FRAM. Therefore, it was clearly demonstrated that the novel capacitors can enable the realization of a high-density 32 Mb FRAM device with a 0.25 μm design rule.

  6. Plasma-Assisted Dry Etching of Ferroelectric Capacitor Modules and Application to a 32M Ferroelectric Random Access Memory Devices with Submicron Feature Sizes

    NASA Astrophysics Data System (ADS)

    Lee, Sang-Woo; Joo, Suk-Ho; Cho, Sung Lae; Son, Yoon-Ho; Lee, Kyu-Mann; Nam, Sang-Don; Park, Kun-Sang; Lee, Yong-Tak; Seo, Jung-Suk; Kim, Young-Dae; An, Hyeong-Geun; Kim, Hyoung-Joon; Jung, Yong-Ju; Heo, Jang-Eun; Lee, Moon-Sook; Park, Soon-Oh; Chung, U-In; Moon, Joo-Tae

    2002-11-01

    In the manufacturing of a 32M ferroelectric random access memory (FRAM) device on the basis of 0.25 design rule (D/R), one of the most difficult processes is to pattern a submicron capacitor module while retaining good ferroelectric properties. In this paper, we report the ferroelectric property of patterned submicron capacitor modules with a stack height of 380 nm, where the 100 nm-thick Pb(Zr, Ti)O3 (PZT) films were prepared by the sol-gel method. After patterning, overall sidewall slope was approximately 70° and cell-to-cell node separation was made to be 80 nm to prevent possible twin-bit failure in the device. Finally, several heat treatment conditions were investigated to retain the ferroelectric property of the patterned capacitor. It was found that rapid thermal processing (RTP) treatment yields better properties than conventional furnace annealing. This result is directly related to the near-surface chemistry of the PZT films, as confirmed by X-ray photoelectron spectroscopy (XPS) analysis. The resultant switching polarization value of the submicron capacitor was approximately 30 μC/cm2 measured at 3 V.

  7. Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

    2016-06-01

    With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption.

  8. Sustained Resistive Switching in a Single Cu:7,7,8,8-tetracyanoquinodimethane Nanowire: A Promising Material for Resistive Random Access Memory.

    PubMed

    Basori, Rabaya; Kumar, Manoranjan; Raychaudhuri, Arup K

    2016-01-01

    We report a new type of sustained and reversible unipolar resistive switching in a nanowire device made from a single strand of Cu:7,7,8,8-tetracyanoquinodimethane (Cu:TCNQ) nanowire (diameter <100 nm) that shows high ON/OFF ratio (~10(3)), low threshold voltage of switching (~3.5 V) and large cycling endurance (>10(3)). This indicates a promising material for high density resistive random access memory (ReRAM) device integration. Switching is observed in Cu:TCNQ single nanowire devices with two different electrode configuration: symmetric (C-Pt/Cu:TCNQ/C-Pt) and asymmetric (Cu/Cu:TCNQ/C-Pt), where contacts connecting the nanowire play an important role. This report also developed a method of separating out the electrode and material contributions in switching using metal-semiconductor-metal (MSM) device model along with a direct 4-probe resistivity measurement of the nanowire in the OFF as well as ON state. The device model was followed by a phenomenological model of current transport through the nanowire device which shows that lowering of potential barrier at the contacts likely occur due to formation of Cu filaments in the interface between nanowire and contact electrodes. We obtain quantitative agreement of numerically analyzed results with the experimental switching data. PMID:27245099

  9. Sustained Resistive Switching in a Single Cu:7,7,8,8-tetracyanoquinodimethane Nanowire: A Promising Material for Resistive Random Access Memory

    PubMed Central

    Basori, Rabaya; Kumar, Manoranjan; Raychaudhuri, Arup K.

    2016-01-01

    We report a new type of sustained and reversible unipolar resistive switching in a nanowire device made from a single strand of Cu:7,7,8,8-tetracyanoquinodimethane (Cu:TCNQ) nanowire (diameter <100 nm) that shows high ON/OFF ratio (~103), low threshold voltage of switching (~3.5 V) and large cycling endurance (>103). This indicates a promising material for high density resistive random access memory (ReRAM) device integration. Switching is observed in Cu:TCNQ single nanowire devices with two different electrode configuration: symmetric (C-Pt/Cu:TCNQ/C-Pt) and asymmetric (Cu/Cu:TCNQ/C-Pt), where contacts connecting the nanowire play an important role. This report also developed a method of separating out the electrode and material contributions in switching using metal-semiconductor-metal (MSM) device model along with a direct 4-probe resistivity measurement of the nanowire in the OFF as well as ON state. The device model was followed by a phenomenological model of current transport through the nanowire device which shows that lowering of potential barrier at the contacts likely occur due to formation of Cu filaments in the interface between nanowire and contact electrodes. We obtain quantitative agreement of numerically analyzed results with the experimental switching data. PMID:27245099

  10. Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition

    PubMed Central

    Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

    2016-01-01

    With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption. PMID:27312225

  11. Switching operation and degradation of resistive random access memory composed of tungsten oxide and copper investigated using in-situ TEM

    PubMed Central

    Arita, Masashi; Takahashi, Akihito; Ohno, Yuuki; Nakane, Akitoshi; Tsurumaki-Fukuchi, Atsushi; Takahashi, Yasuo

    2015-01-01

    In-situ transmission electron microscopy (in-situ TEM) was performed to investigate the switching operation of a resistive random access memory (ReRAM) made of copper, tungsten oxide and titanium nitride (Cu/WOx/TiN). In the first Set (Forming) operation to initialize the device, precipitation appeared inside the WOx layer. It was presumed that a Cu conducting filament was formed, lowering the resistance (on-state). The Reset operation induced a higher resistance (the off-state). No change in the microstructure was identified in the TEM images. Only when an additional Reset current was applied after switching to the off-state could erasure of the filament be seen (over-Reset). Therefore, it was concluded that structural change relating to the resistance switch was localized in a very small area around the filament. With repeated switching operations and increasing operational current, the WOx/electrode interfaces became indistinct. At the same time, the resistance of the off-state gradually decreased. This is thought to be caused by Cu condensation at the interfaces because of leakage current through the area other than through the filament. This will lead to device degradation through mechanisms such as endurance failure. This is the first accelerated aging test of ReRAM achieved using in-situ TEM. PMID:26611856

  12. Interfacial Electrode-Driven Enhancement of the Switching Parameters of a Copper Oxide-Based Resistive Random-Access Memory Device

    NASA Astrophysics Data System (ADS)

    Sangani, L. D. Varma; Kumar, Ch. Ravi; Krishna, M. Ghanashyam

    2016-01-01

    The characteristics of an Au/Cu x O/Au bipolar resistive random-access memory device are reported. It is demonstrated that switching parameters of this device structure can be enhanced by introducing an interfacial Al layer between the Au top electrode and the Cu x O-based dielectric layer. The set and reset voltages are, respectively, between -2.5 V to -6.0 V and +1.2 V to +3.0 V for the Al-based device. In contrast, the range of values are -0.5 V to -2.5 V and +0.5 V to +1.5 V for the set and reset voltages in the absence of Al. The Al-based device has a higher low resistance state value of 5-6 KΩ as compared to the 0.3-0.5 KΩ for the Au-based device, which leads to a 12 times lower power dissipation factor and lower reset current of 370 μA. Endurance studies carried out over 50 switching cycles show less than 2% variation in both the low resistance and high resistance values. The conduction is ohmic at low values of bias and non-ohmic at higher bias voltage which shows that the enhanced behaviour is a result of the formation of an insulating aluminum oxide layer at the Al-Cu x O interface.

  13. Switching operation and degradation of resistive random access memory composed of tungsten oxide and copper investigated using in-situ TEM.

    PubMed

    Arita, Masashi; Takahashi, Akihito; Ohno, Yuuki; Nakane, Akitoshi; Tsurumaki-Fukuchi, Atsushi; Takahashi, Yasuo

    2015-01-01

    In-situ transmission electron microscopy (in-situ TEM) was performed to investigate the switching operation of a resistive random access memory (ReRAM) made of copper, tungsten oxide and titanium nitride (Cu/WOx/TiN). In the first Set (Forming) operation to initialize the device, precipitation appeared inside the WOx layer. It was presumed that a Cu conducting filament was formed, lowering the resistance (on-state). The Reset operation induced a higher resistance (the off-state). No change in the microstructure was identified in the TEM images. Only when an additional Reset current was applied after switching to the off-state could erasure of the filament be seen (over-Reset). Therefore, it was concluded that structural change relating to the resistance switch was localized in a very small area around the filament. With repeated switching operations and increasing operational current, the WOx/electrode interfaces became indistinct. At the same time, the resistance of the off-state gradually decreased. This is thought to be caused by Cu condensation at the interfaces because of leakage current through the area other than through the filament. This will lead to device degradation through mechanisms such as endurance failure. This is the first accelerated aging test of ReRAM achieved using in-situ TEM. PMID:26611856

  14. Resistive switching and electrical control of ferromagnetism in a Ag/HfO₂/Nb:SrTiO₃/Ag resistive random access memory (RRAM) device at room temperature.

    PubMed

    Ren, Shaoqing; Zhu, Gengchang; Xie, Jihao; Bu, Jianpei; Qin, Hongwei; Hu, Jifan

    2016-02-10

    Electrically induced resistive switching and modulated ferromagnetism are simultaneously found in a Ag/HfO2/Nb:SrTiO3/Ag resistive random access memory device at room temperature. The bipolar resistive switching (RS) can be controlled by the modification of a Schottky-like barrier with an electron injection-trapped/detrapped process at the interface of HfO2-Nb:SrTiO3. The multilevel RS transition can be observed in the reset process with larger negative voltage sweepings, which is connected to the different degree of electron detrapping in the interfacial depletion region of the HfO2 layer during the reset process. The origin of the electrical control of room-temperature ferromagnetism may be connected to the change of density of oxygen vacancies in the HfO2 film. The multilevel resistance states and the electric field controlled ferromagnetism have potential for applications in ultrahigh-density storage and magnetic logic device. PMID:26761365

  15. Self-selection effects and modulation of TaOx resistive switching random access memory with bottom electrode of highly doped Si

    NASA Astrophysics Data System (ADS)

    Yu, Muxi; Fang, Yichen; Wang, Zongwei; Pan, Yue; Li, Ming; Cai, Yimao; Huang, Ru

    2016-05-01

    In this paper, we propose a TaOx resistive switching random access memory (RRAM) device with operation-polarity-dependent self-selection effect by introducing highly doped silicon (Si) electrode, which is promising for large-scale integration. It is observed that with highly doped Si as the bottom electrode (BE), the RRAM devices show non-linear (>103) I-V characteristic during negative Forming/Set operation and linear behavior during positive Forming/Set operation. The underling mechanisms for the linear and non-linear behaviors at low resistance states of the proposed device are extensively investigated by varying operation modes, different metal electrodes, and Si doping type. Experimental data and theoretical analysis demonstrate that the operation-polarity-dependent self-selection effect in our devices originates from the Schottky barrier between the TaOx layer and the interfacial SiOx formed by reaction between highly doped Si BE and immigrated oxygen ions in the conductive filament area.

  16. Modulation of surface trap induced resistive switching by electrode annealing in individual PbS micro/nanowire-based devices for resistance random access memory.

    PubMed

    Zheng, Jianping; Cheng, Baochang; Wu, Fuzhang; Su, Xiaohui; Xiao, Yanhe; Guo, Rui; Lei, Shuijin

    2014-12-10

    Bipolar resistive switching (RS) devices are commonly believed as a promising candidate for next generation nonvolatile resistance random access memory (RRAM). Here, two-terminal devices based on individual PbS micro/nanowires with Ag electrodes are constructed, whose electrical transport depends strongly on the abundant surface and bulk trap states in micro/nanostructures. The surface trap states can be filled/emptied effectively at negative/positive bias voltage, respectively, and the corresponding rise/fall of the Fermi level induces a variation in a degenerate/nondegenerate state, resulting in low/high resistance. Moreover, the filling/emptying of trap states can be utilized as RRAM. After annealing, the surface trap state can almost be eliminated completely; while most of the bulk trap states can still remain. In the devices unannealed and annealed at both ends, therefore, the symmetrical back-to-back Fowler-Nordheim tunneling with large ON/OFF resistance ratio and Poole-Frenkel emission with poor hysteresis can be observed under cyclic sweep voltage, respectively. However, a typical bipolar RS behavior can be observed effectively in the devices annealed at one end. The acquirement of bipolar RS and nonvolatile RRAM by the modulation of electrode annealing demonstrates the abundant trap states in micro/nanomaterials will be advantageous to the development of new type electronic components. PMID:25398100

  17. Switching operation and degradation of resistive random access memory composed of tungsten oxide and copper investigated using in-situ TEM

    NASA Astrophysics Data System (ADS)

    Arita, Masashi; Takahashi, Akihito; Ohno, Yuuki; Nakane, Akitoshi; Tsurumaki-Fukuchi, Atsushi; Takahashi, Yasuo

    2015-11-01

    In-situ transmission electron microscopy (in-situ TEM) was performed to investigate the switching operation of a resistive random access memory (ReRAM) made of copper, tungsten oxide and titanium nitride (Cu/WOx/TiN). In the first Set (Forming) operation to initialize the device, precipitation appeared inside the WOx layer. It was presumed that a Cu conducting filament was formed, lowering the resistance (on-state). The Reset operation induced a higher resistance (the off-state). No change in the microstructure was identified in the TEM images. Only when an additional Reset current was applied after switching to the off-state could erasure of the filament be seen (over-Reset). Therefore, it was concluded that structural change relating to the resistance switch was localized in a very small area around the filament. With repeated switching operations and increasing operational current, the WOx/electrode interfaces became indistinct. At the same time, the resistance of the off-state gradually decreased. This is thought to be caused by Cu condensation at the interfaces because of leakage current through the area other than through the filament. This will lead to device degradation through mechanisms such as endurance failure. This is the first accelerated aging test of ReRAM achieved using in-situ TEM.

  18. Integration of e-beam direct write in BEOL processes of 28nm SRAM technology node using mix and match

    NASA Astrophysics Data System (ADS)

    Gutsch, Manuela; Choi, Kang-Hoon; Hanisch, Norbert; Hohle, Christoph; Seidel, Robert; Steidel, Katja; Thrun, Xaver; Werner, Thomas

    2014-10-01

    Many efforts were spent in the development of EUV technologies, but from a customer point of view EUV is still behind expectations. In parallel since years maskless lithography is included in the ITRS roadmap wherein multi electron beam direct patterning is considered as an alternative or complementary approach for patterning of advanced technology nodes. The process of multi beam exposures can be emulated by single beam technologies available in the field. While variable shape-beam direct writers are already used for niche applications, the integration capability of e-beam direct write at advanced nodes has not been proven, yet. In this study the e-beam lithography was implemented in the BEoL processes of the 28nm SRAM technology. Integrated 300mm wafers with a 28nm back-end of line (BEoL) stack from GLOBALFOUNDRIES, Dresden, were used for the experiments. For the patterning of the Metal layer a Mix and Match concept based on the sequence litho - etch - litho - etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. E-beam patterning results of BEoL Metal and Via layers are presented using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMS-CNT. Etch results are shown and compared to the POR. In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node.

  19. Joint optimization of layout and litho for SRAM and logic towards the 20nm node using 193i

    NASA Astrophysics Data System (ADS)

    De Bisschop, Peter; Laenens, Bart; Iwase, Kazuya; Yao, Teruyoshi; Dusa, Mircea; Smayling, Michael C.

    2011-04-01

    This paper reports on a simulation study in which we compare different possibilities to find a litho solution for SRAM and Logic for planar technology nodes between 28 nm and 20 nm, using 193 nm immersion lithography. At these nodes, it becomes essential to include the layout itself into the optimization process. The so-called gridded layout style is an attractive candidate to facilitate the printability of several layers, but the benefit of this style, as compared to less restricted layout styles, is not well quantified for the various technology nodes of interest. We therefore compare it with two other, less restricted, layout styles, on an identical (small) SRAM-Logic test chip. Exploring a number of paths in the layout-style - litho-options search space, we try to quantify merits and trade-offs for some of the relevant options. We will show that layout restrictions are really becoming mandatory for the technology nodes studied in this paper. Other important enablers for these aggressive nodes are multiple patterning, the use of a local-interconnect layer, negative-tone development, SMO and the use of optimized free-form illumination sources (from which we also include a few initial wafer results).

  20. Fabrication of dynamic oxide semiconductor random access memory with 3.9 fF storage capacitance and greater than 1 h retention by using c-axis aligned crystalline oxide semiconductor transistor with L of 60 nm

    NASA Astrophysics Data System (ADS)

    Onuki, Tatsuya; Kato, Kiyoshi; Nomura, Masumi; Yakubo, Yuto; Nagatsuka, Shuhei; Matsuzaki, Takanori; Hondo, Suguru; Hata, Yuki; Okazaki, Yutaka; Nagai, Masaharu; Atsumi, Tomoaki; Sakakura, Masayuki; Okuda, Takashi; Yamamoto, Yoshitaka; Yamazaki, Shunpei

    2015-04-01

    A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.

  1. Memory beyond expression.

    PubMed

    Delorenzi, A; Maza, F J; Suárez, L D; Barreiro, K; Molina, V A; Stehberg, J

    2014-01-01

    The idea that memories are not invariable after the consolidation process has led to new perspectives about several mnemonic processes. In this framework, we review our studies on the modulation of memory expression during reconsolidation. We propose that during both memory consolidation and reconsolidation, neuromodulators can determine the probability of the memory trace to guide behavior, i.e. they can either increase or decrease its behavioral expressibility without affecting the potential of persistent memories to be activated and become labile. Our hypothesis is based on the findings that positive modulation of memory expression during reconsolidation occurs even if memories are behaviorally unexpressed. This review discusses the original approach taken in the studies of the crab Neohelice (Chasmagnathus) granulata, which was then successfully applied to test the hypothesis in rodent fear memory. Data presented offers a new way of thinking about both weak trainings and experimental amnesia: memory retrieval can be dissociated from memory expression. Furthermore, the strategy presented here allowed us to show in human declarative memory that the periods in which long-term memory can be activated and become labile during reconsolidation exceeds the periods in which that memory is expressed, providing direct evidence that conscious access to memory is not needed for reconsolidation. Specific controls based on the constraints of reminders to trigger reconsolidation allow us to distinguish between obliterated and unexpressed but activated long-term memories after amnesic treatments, weak trainings and forgetting. In the hypothesis discussed, memory expressibility--the outcome of experience-dependent changes in the potential to behave--is considered as a flexible and modulable attribute of long-term memories. Expression seems to be just one of the possible fates of re-activated memories. PMID:25102126

  2. Influence of cooling rate in planar thermally assisted magnetic random access memory: Improved writeability due to spin-transfer-torque influence

    SciTech Connect

    Chavent, A.; Ducruet, C.; Portemont, C.; Creuzet, C.; Alvarez-Hérault, J.; Vila, L.; Sousa, R. C.; Prejbeanu, I. L.; Dieny, B.

    2015-09-14

    This paper investigates the effect of a controlled cooling rate on magnetic field reversal assisted by spin transfer torque (STT) in thermally assisted magnetic random access memory. By using a gradual linear decrease of the voltage at the end of the write pulse, the STT decays more slowly or at least at the same rate as the temperature. This condition is necessary to make sure that the storage layer magnetization remains in the desired written direction during cooling of the cell. The influence of the write current pulse decay rate was investigated on two exchange biased synthetic ferrimagnet (SyF) electrodes. For a NiFe based electrode, a significant improvement in writing reproducibility was observed using a gradual linear voltage transition. The write error rate decreases by a factor of 10 when increasing the write pulse fall-time from ∼3 ns to 70 ns. For comparison, a second CoFe/NiFe based electrode was also reversed by magnetic field assisted by STT. In this case, no difference between sharp and linear write pulse fall shape was observed. We attribute this observation to the higher thermal stability of the CoFe/NiFe electrode during cooling. In real-time measurements of the magnetization reversal, it was found that Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling in the SyF electrode vanishes for the highest pulse voltages that were used due to the high temperature reached during write. As a result, during the cooling phase, the final state is reached through a spin-flop transition of the SyF storage layer.

  3. Influence of cooling rate in planar thermally assisted magnetic random access memory: Improved writeability due to spin-transfer-torque influence

    NASA Astrophysics Data System (ADS)

    Chavent, A.; Ducruet, C.; Portemont, C.; Creuzet, C.; Vila, L.; Alvarez-Hérault, J.; Sousa, R. C.; Prejbeanu, I. L.; Dieny, B.

    2015-09-01

    This paper investigates the effect of a controlled cooling rate on magnetic field reversal assisted by spin transfer torque (STT) in thermally assisted magnetic random access memory. By using a gradual linear decrease of the voltage at the end of the write pulse, the STT decays more slowly or at least at the same rate as the temperature. This condition is necessary to make sure that the storage layer magnetization remains in the desired written direction during cooling of the cell. The influence of the write current pulse decay rate was investigated on two exchange biased synthetic ferrimagnet (SyF) electrodes. For a NiFe based electrode, a significant improvement in writing reproducibility was observed using a gradual linear voltage transition. The write error rate decreases by a factor of 10 when increasing the write pulse fall-time from ˜3 ns to 70 ns. For comparison, a second CoFe/NiFe based electrode was also reversed by magnetic field assisted by STT. In this case, no difference between sharp and linear write pulse fall shape was observed. We attribute this observation to the higher thermal stability of the CoFe/NiFe electrode during cooling. In real-time measurements of the magnetization reversal, it was found that Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling in the SyF electrode vanishes for the highest pulse voltages that were used due to the high temperature reached during write. As a result, during the cooling phase, the final state is reached through a spin-flop transition of the SyF storage layer.

  4. Size-dependent resistive switching properties of the active region in nickel nitride-based crossbar array resistive random access memory.

    PubMed

    Kim, Hee-Dong; Yun, Min Ju; Hong, Seok Man; Kim, Tae Geun

    2014-12-01

    The size-dependent resistive switching (RS) properties of the active region in a 1 x 1 NiN-based crossbar array (CBA) resistive random access memory (ReRAM) are investigated in the range of 2 x 2 μm2 to 8 x 8 μm2. In the forming test, the forming voltage is reduced by decreasing the cell size of the active region. Compared to the 8 x 8 μm2 CBA ReRAM, the forming voltage of the 2 x 2 μm2 CBA ReRAM was reduced from 8 V to 6.2 V. In addition, V(SET/RESET) and the current for the reset operation are reduced in the current-voltage (I-V) results by reducing the cell size, while the current at a high-resistance state (HRS) is increased. As a result, the current ratio between the HRS and a low-resistance state (LRS) is reduced. On the other hand, the variation of V(SET) for I-V curves repetitively acquired 100 times is decreased by decreasing the cell size in the reliability test. Further, the current at the HRS for the 2 x 2 μm2 CBA ReRAM is the most stable with the smallest current variation for 1000 s in the retention test. These results show that reducing the active region in the CBA ReRAM structure is effective for improving the reliability of ReRAM cells because it reduces the operating voltage and current as well as the variation of V(SET) and the current at the HRS. PMID:25971015

  5. Optical mass memories

    NASA Technical Reports Server (NTRS)

    Bailey, G. A.

    1976-01-01

    Optical and magnetic variants in the design of trillion-bit read/write memories are compared and tabulated. Components and materials suitable for a random access read/write nonmoving memory system are examined, with preference given to holography and photoplastic materials. Advantages and deficiencies of photoplastics are reviewed. Holographic page composer design, essential features of an optical memory with no moving parts, fiche-oriented random access memory design, and materials suitable for an efficient photoplastic fiche are considered. The optical variants offer advantages in lower volume and weight at data transfer rates near 1 Mbit/sec, but power drain is of the same order as for the magnetic variants (tape memory, disk memory). The mechanical properties of photoplastic film materials still leave much to be desired.

  6. Improved Writing-Conductor Designs For Magnetic Memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1994-01-01

    Writing currents reduced to practical levels. Improved conceptual designs for writing conductors in micromagnet/Hall-effect random-access integrated-circuit memory reduces electrical current needed to magnetize micromagnet in each memory cell. Basic concept of micromagnet/Hall-effect random-access memory presented in "Magnetic Analog Random-Access Memory" (NPO-17999).

  7. Quantum memory Quantum memory

    NASA Astrophysics Data System (ADS)

    Le Gouët, Jean-Louis; Moiseev, Sergey

    2012-06-01

    Interaction of quantum radiation with multi-particle ensembles has sparked off intense research efforts during the past decade. Emblematic of this field is the quantum memory scheme, where a quantum state of light is mapped onto an ensemble of atoms and then recovered in its original shape. While opening new access to the basics of light-atom interaction, quantum memory also appears as a key element for information processing applications, such as linear optics quantum computation and long-distance quantum communication via quantum repeaters. Not surprisingly, it is far from trivial to practically recover a stored quantum state of light and, although impressive progress has already been accomplished, researchers are still struggling to reach this ambitious objective. This special issue provides an account of the state-of-the-art in a fast-moving research area that makes physicists, engineers and chemists work together at the forefront of their discipline, involving quantum fields and atoms in different media, magnetic resonance techniques and material science. Various strategies have been considered to store and retrieve quantum light. The explored designs belong to three main—while still overlapping—classes. In architectures derived from photon echo, information is mapped over the spectral components of inhomogeneously broadened absorption bands, such as those encountered in rare earth ion doped crystals and atomic gases in external gradient magnetic field. Protocols based on electromagnetic induced transparency also rely on resonant excitation and are ideally suited to the homogeneous absorption lines offered by laser cooled atomic clouds or ion Coulomb crystals. Finally off-resonance approaches are illustrated by Faraday and Raman processes. Coupling with an optical cavity may enhance the storage process, even for negligibly small atom number. Multiple scattering is also proposed as a way to enlarge the quantum interaction distance of light with matter. The

  8. Working memory capacity and controlled serial memory search.

    PubMed

    Mızrak, Eda; Öztekin, Ilke

    2016-08-01

    The speed-accuracy trade-off (SAT) procedure was used to investigate the relationship between working memory capacity (WMC) and the dynamics of temporal order memory retrieval. High- and low-span participants (HSs, LSs) studied sequentially presented five-item lists, followed by two probes from the study list. Participants indicated the more recent probe. Overall, accuracy was higher for HSs compared to LSs. Crucially, in contrast to previous investigations that observed no impact of WMC on speed of access to item information in memory (e.g., Öztekin & McElree, 2010), recovery of temporal order memory was slower for LSs. While accessing an item's representation in memory can be direct, recovery of relational information such as temporal order information requires a more controlled serial memory search. Collectively, these data indicate that WMC effects are particularly prominent during high demands of cognitive control, such as serial search operations necessary to access temporal order information from memory. PMID:27135712

  9. Radiation tolerance tests of SRAM-based FPGAs for the potential usage in the readout electronics for the LHCb experiment

    NASA Astrophysics Data System (ADS)

    Färber, C.; Uwer, U.; Wiedner, D.; Leverington, B.; Ekelhof, R.

    2014-02-01

    This paper describes radiation studies of a SRAM-based FPGA as a central component for a upgrade of the LHCb Outer Tracker front-end electronics to a readout frequency of 40 MHz. Two Arria GX FPGAs were irradiated with 20 MeV protons to radiation doses of up to 7 Mrad. During and between the irradiation periods the different FPGA currents, the package temperature, the firmware error rate, the PLL stability, and the stability of a 32 channel TDC implemented on the FPGA were monitored. Results on the radiation tolerance of the FPGA and the measured firmware error rates will be presented. The Arria GX FPGA fulfills the radiation tolerance required for the LHCb upgrade (30 krad) and an expected firmware error rate of roughly 10-6 Hz makes the chip a possible component for the upgraded front-end electronics.

  10. Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM

    NASA Astrophysics Data System (ADS)

    Yinhong, Luo; Fengqi, Zhang; Hongxia, Guo; Yao, Xiao; Wen, Zhao; Lili, Ding; Yuanming, Wang

    2015-11-01

    Single event multiple-cell upsets (MCU) increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices.

  11. Memory for Traumatic Experiences in Early Childhood

    ERIC Educational Resources Information Center

    Cordon, Ingrid M.; Pipe, Margaret-Ellen; Sayfan, Liat; Melinder, Annika; Goodman, Gail S.

    2004-01-01

    Traumatic experiences in early childhood raise important questions about memory development in general and about the durability and accessibility of memories for traumatic events in particular. We discuss memory for early childhood traumatic events, from a developmental perspective, focusing on those factors that may equally influence memories for…

  12. Autosuggestibility in memory development.

    PubMed

    Brainerd, C J; Reyna, V F

    1995-02-01

    Autosuggestibility is a potentially common source of false memories in children. We studied a form of autosuggestibility in which children's answers to memory tests were shifted in the direction of their illogical solutions to reasoning problems. In Experiments 1 and 2, illogic-consistent shifts were identified in children's memories of the numerical inputs on class-inclusion problems. The magnitudes of the shifts declined with age, and they appeared to be due to the intrusion of inappropriate gist on memory probes rather than retroactive interference from illogical reasoning. A model of how gist intrusion causes autosuggestibility was investigated in Experiments 3-5. The model assumes that children retrieve and process inappropriate gist when memory tests supply cues that are inadequate to permit access to verbatim memories. PMID:7895469

  13. Does fascia hold memories?

    PubMed

    Tozzi, Paolo

    2014-04-01

    The idea that tissues may possess some sort of memory is a controversial topic in manual medicine, calling for research and clinical exploration. Many bodyworkers, at some point in their practice, have experienced phenomena that may be interpreted as representing a release of memory traces when working on dysfunctional tissues. This feeling may have been accompanied by some type of sensory experience, for the therapist and/or the patient. In some cases, early traumatic experiences may be recalled. When this happens, the potency of the memory may be erased or eased, along with restoration of tissue function. Hence the questions: can memories be held in the fascia? And: are these memories accessible during manual fascial work? Modern research has proposed a variety of different interpretations as to how memory might be stored in soft tissues, possibly involving other forms of information storage not exclusively processed neurologically (Box 1). PMID:24725795

  14. Monolithically integrated enhancement/depletion-mode AlGaN/GaN HEMTs SRAM unit and voltage level shifter using fluorine plasma treatment

    NASA Astrophysics Data System (ADS)

    Yonghe, Chen; Xuefeng, Zheng; Jincheng, Zhang; Xiaohua, Ma; Yue, Hao

    2016-05-01

    A GaN-based E/D mode direct-couple logic 6 transistors SRAM unit and a voltage level shifter were designed and fabricated. E-mode and D-mode AlGaN/GaN HEMTs were integrated in one wafer using fluorine plasma treatment and using a moderate AlGaN barrier layer heterojunction structure. The 6 transistors SRAM unit consists of two symmetrical E/D mode inverters and two E-mode switch HEMTs. The output low and high voltage of the SRAM unit are 0.95 and 0.07 V at a voltage supply of 1 V. The voltage level shifter lowers the supply voltage using four Ni-AlGaN Schottky diodes in a series at a positive supply voltage of 6 V and a negative supply voltage of ‑6 V. By controlling the states of inverter modules of the level shifter in turn, the level shifter offers two channel voltage outputs of ‑0.5 and ‑5 V. The flip voltage of the level shifter is 0.76 V. Both the SRAM unit and voltage shifter operate correctly, demonstrating the promising potential for GaN-based E/D mode digital and analog integrated circuits. Several considerations are proposed to avoid the influence of threshold voltage degradation of D-mode and E-mode HEMT on the operation of the circuit. Project supported by the National Natural Science Foundation of China (No. 61334002), the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201206), and the Program for New Century Excellent Talents in University (No. NCET-12-0915).

  15. Mechanical memory

    DOEpatents

    Gilkey, Jeffrey C.; Duesterhaus, Michelle A.; Peter, Frank J.; Renn, Rosemarie A.; Baker, Michael S.

    2006-08-15

    A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.

  16. Mechanical memory

    DOEpatents

    Gilkey, Jeffrey C.; Duesterhaus, Michelle A.; Peter, Frank J.; Renn, Rosemarie A.; Baker, Michael S.

    2006-05-16

    A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.

  17. Observation and prediction of SEU in Hitachi SRAMs in low altitude polar orbits

    SciTech Connect

    Harboe-Sorensen, R.; Daly, E.J.; Adams, L. ); Underwood, C.I. . Surrey Satellite Technology); Mueller, R. . Institut fuer Datenverarbeitungsanlagen)

    1993-12-01

    In-orbit SEU data from three microsatellites are separated into Galactic Cosmic Ray (GCR), South Atlantic Anomaly (SAA) and solar flare upsets. Heavy ion and proton testing of the same devices are reported and predictions using LET-dependent ion cross sections and a 2-parameter fit to proton cross section data are compared with in-flight data. SEU trends in memory devices from a single manufacturer, from 16 K-bit to 4 M-bit, are identified.

  18. Bipartite memory network architectures for parallel processing

    SciTech Connect

    Smith, W.; Kale, L.V. . Dept. of Computer Science)

    1990-01-01

    Parallel architectures are boradly classified as either shared memory or distributed memory architectures. In this paper, the authors propose a third family of architectures, called bipartite memory network architectures. In this architecture, processors and memory modules constitute a bipartite graph, where each processor is allowed to access a small subset of the memory modules, and each memory module allows access from a small set of processors. The architecture is particularly suitable for computations requiring dynamic load balancing. The authors explore the properties of this architecture by examining the Perfect Difference set based topology for the graph. Extensions of this topology are also suggested.

  19. Plated wire memory subsystem

    NASA Technical Reports Server (NTRS)

    Reynolds, L.; Tweed, H.

    1972-01-01

    The work performed entailed the design, development, construction and testing of a 4000 word by 18 bit random access, NDRO plated wire memory for use in conjunction with a spacecraft imput/output unit and central processing unit. The primary design parameters, in order of importance, were high reliability, low power, volume and weight. A single memory unit, referred to as a qualification model, was delivered.

  20. Plated wire memory subsystem

    NASA Technical Reports Server (NTRS)

    Carpenter, K. H.

    1974-01-01

    The design, construction, and test history of a 4096 word by 18 bit random access NDRO Plated Wire Memory for use in conjunction with a spacecraft input/output and central processing unit is reported. A technical and functional description is given along with diagrams illustrating layout and systems operation. Test data is shown on the procedures and results of system level and memory stack testing, and hybrid circuit screening. A comparison of the most significant physical and performance characteristics of the memory unit versus the specified requirements is also included.

  1. Towards the development of flexible non-volatile memories.

    PubMed

    Han, Su-Ting; Zhou, Ye; Roy, V A L

    2013-10-11

    Flexible non-volatile memories have attracted tremendous attentions for data storage for future electronics application. From device perspective, the advantages of flexible memory devices include thin, lightweight, printable, foldable and stretchable. The flash memories, resistive random access memories (RRAM) and ferroelectric random access memory/ferroelectric field-effect transistor memories (FeRAM/FeFET) are considered as promising candidates for next generation non-volatile memory device. Here, we review the general background knowledge on device structure, working principle, materials, challenges and recent progress with the emphasis on the flexibility of above three categories of non-volatile memories. PMID:24038631

  2. Memory Matters

    MedlinePlus

    ... different parts. Some of them are important for memory. The hippocampus (say: hih-puh-KAM-pus) is one of the more important parts of the brain that processes memories. Old information and new information, or memories, are ...

  3. Remembering, imagining, false memories & personal meanings.

    PubMed

    Conway, Martin A; Loveday, Catherine

    2015-05-01

    The Self-Memory System encompasses the working self, autobiographical memory and episodic memory. Specific autobiographical memories are patterns of activation over knowledge structures in autobiographical and episodic memory brought about by the activating effect of cues. The working self can elaborate cues based on the knowledge they initially activate and so control the construction of memories of the past and the future. It is proposed that such construction takes place in the remembering-imagining system - a window of highly accessible recent memories and simulations of near future events. How this malfunctions in various disorders is considered as are the implication of what we term the modern view of human memory for notions of memory accuracy. We show how all memories are to some degree false and that the main role of memories lies in generating personal meanings. PMID:25592676

  4. Highly Stable Etch Stopper Technology for 0.25 μm 1 Transistor 1 Capacitor (1T1C) 32 Mega-Bit Ferroelectric Random Access Memory (FRAM)

    NASA Astrophysics Data System (ADS)

    Jang, Nak-Won; Song, Yoon-Jong; Joo, Suk-Ho; Lee, Kyu-Mann; Kim, Hyun-Ho; Joo, Heung-Jin; Park, Jung-Hoon; Lee, Sang-Woo; Lee, Sung-Yung; Kim, Kinam

    2003-04-01

    Since current 32 Mb high-density ferroelectric random access memory (FRAM) shows very narrow sensing window, it is strongly desired to improve the sensing widow for generating a reliable high yield. In this paper, we propose a TiAlN oxygen stopping layer for enhancing the diffusion barrier layer, which makes it possible to reduce the bottom stack height from 180 nm to 90 nm, resulting in the increase of effective cell area and cell charge. In addition to the enhanced diffusion barrier, we developed a stable PE-SiN etch stopper for replacing Ir noble metal etch stopper that has strong stress variation and eventually deteriorates the cell charge distribution. By using TiAlN oxygen stopping layer and PE-SiN etch stopper, the 32 Mb FRAM device shows very wide sensing window of 100 fC, which guarantees a reliable high yield.

  5. CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Simulation of Phase-Change Random Access Memory with Ring-Type Contactor for Low Reset Current by Finite Element Modelling

    NASA Astrophysics Data System (ADS)

    Gong, Yue-Feng; Ling, Yun; Song, Zhi-Tang; Feng, Song-Lin

    2008-09-01

    A three-dimensional finite element models for phase change random access memory (PCRAM) is established to simulate thermal and electrical behaviours during RESET operation. The RESET behaviours of the conventional structure (CS) and the ring-type contact in bottom electrode (RIB) are compared with each other. The simulation results indicate that the RIB cell has advantages of high heat efficiency for melting phase change material in cell, reduction of contact area and lower RESET current with maintaining good resistance contrast. The RESET current decreases from 1.26mA to 1.2mA and the heat consumption in GST material during programming increases from 12% to 37% in RIB structure. Thus the RIB structure PCRAM cell is suitable for future device with high heat efficiency and smaller RESET current.

  6. Demystifying the Beginnings of Memory

    ERIC Educational Resources Information Center

    Howe, Mark L.; Courage, Mary L.

    2004-01-01

    A longstanding issue in psychology has been, When does human memory begin? More particularly, when do we begin to remember personal experiences in a way that makes them accessible to recollection later in life? Current popular and scientific thinking would have us believe that memories are possible not only at the time of our birth, but also in…

  7. Influence of carbon content on the copper-telluride phase formation and on the resistive switching behavior of carbon alloyed Cu-Te conductive bridge random access memory cells

    SciTech Connect

    Devulder, Wouter De Schutter, Bob; Detavernier, Christophe; Opsomer, Karl; Franquet, Alexis; Meersschaut, Johan; Muller, Robert; Van Elshocht, Sven; Jurczak, Malgorzata; Goux, Ludovic; Belmonte, Attilio

    2014-02-07

    In this paper, we investigate the influence of the carbon content on the Cu-Te phase formation and on the resistive switching behavior in carbon alloyed Cu{sub 0.6}Te{sub 0.4} based conductive bridge random access memory (CBRAM) cells. Carbon alloying of copper-tellurium inhibits the crystallization, while attractive switching behavior is preserved when using the material as Cu-supply layer in CBRAM cells. The phase formation is first investigated in a combinatorial way. With increasing carbon content, an enlargement of the temperature window in which the material stays amorphous was observed. Moreover, if crystalline phases are formed, subsequent phase transformations are inhibited. The electrical switching behavior of memory cells with different carbon contents is then investigated by implementing them in 580 μm diameter dot TiN/Cu{sub 0.6}Te{sub 0.4}-C/Al{sub 2}O{sub 3}/Si memory cells. Reliable switching behavior is observed for carbon contents up to 40 at. %, with a resistive window of more than 2 orders of magnitude, whereas for 50 at. % carbon, a higher current in the off state and only a small resistive window are present after repeated cycling. This degradation can be ascribed to the higher thermal and lower drift contribution to the reset operation due to a lower Cu affinity towards the supply layer, leading cycle-after-cycle to an increasing amount of Cu in the switching layer, which contributes to the current. The thermal diffusion of Cu into Al{sub 2}O{sub 3} under annealing also gives an indication of the Cu affinity of the source layer. Time of flight secondary ion mass spectroscopy was used to investigate this migration depth in Al{sub 2}O{sub 3} before and after annealing, showing a higher Cu, Te, and C migration for high carbon contents.

  8. O-doped Si2Sb2Te5 nano-composite phase change material for application of chalcogenide random access memory.

    PubMed

    Zhang, Ting; Song, Zhitang; Liu, Bo; Wang, Feng; Feng, Songlin

    2009-02-01

    A method to prepare nano-composite phase change material was proposed and demonstrated by oxygen doping into Si2Sb2Te5 material. According to transmission electron microscope images, Si-Sb-Te-rich domains are separated from each other by SiOx-rich domains within the material. A proper dose of O-doping into Si2Sb2Te5 significantly reduces the grain size of the phase change material. Average size of Si-Sb-Te-rich domains is about 10 nm. Such separation will limit the phase-change to a relatively small volume. The reduction of grain size further results in the promotion of data retention and thermal stability of the material. Memory device based on O-doped Si2Sb2Te5 nano-composite phase change material, with a bottom electrode contact of 260 nm in diameter, was fabricated and characterized. The memory cell shows a better electrical performance compared with the Ge2Sb2Te5 based one. PMID:19441462

  9. Effect of annealing treatment on the electrical characteristics of Pt/Cr-embedded ZnO/Pt resistance random access memory devices

    SciTech Connect

    Chang, Li-Chun; Kao, Hsuan-Ling; Liu, Keng-Hao

    2014-03-15

    ZnO/Cr/ZnO trilayer films sandwiched with Pt electrodes were prepared for nonvolatile resistive memory applications. The threshold voltage of a ZnO device embedded with a 3-nm Cr interlayer was approximately 50% lower than that of a ZnO monolayer device. This study investigated threshold voltage as a function of Cr thickness. Both the ZnO monolayer device and the Cr-embedded ZnO device structures exhibited resistance switching under electrical bias both before and after rapid thermal annealing (RTA) treatment, but resistive switching effects in the two cases exhibited distinct characteristics. Compared with the as-fabricated device, the memory cell after RTA demonstrated remarkable device parameter improvements, including a lower threshold voltage, a lower write current, and a higher R{sub off}/R{sub on} ratio. Both transmission electron microscope observations and Auger electron spectroscopy revealed that the Cr charge trapping layer in Cr-embedded ZnO dispersed uniformly into the storage medium after RTA, and x-ray diffraction and x-ray photoelectron spectroscopy analyses demonstrated that the Cr atoms lost electrons to become Cr{sup 3+} ions after dispersion. These results indicated that the altered status of Cr in ZnO/Cr/ZnO trilayer films during RTA treatment was responsible for the switching mechanism transition.

  10. Performance of immersion lithography for 45-nm-node CMOS and ultra-high density SRAM with 0.25um2

    NASA Astrophysics Data System (ADS)

    Mimotogi, Shoji; Uesawa, Fumikatsu; Tominaga, Makoto; Fujise, Hiroharu; Sho, Koutaro; Katsumata, Mikio; Hane, Hiroki; Ikegami, Atsushi; Nagahara, Seiji; Ema, Tatsuhiko; Asano, Masafumi; Kanai, Hideki; Kimura, Taiki; Iwai, Masaaki

    2007-03-01

    Immersion lithography was applied to 45nm node logic and 0.25um2 ultra-high density SRAM. The predictable enhancement of focus margin and resolution were obtained for all levels which were exposed by immersion tool. In particular, the immersion lithography enabled to apply the attenuating phase shift mask to the gate level. The enough lithography margin for the alternating phase shift mask was also obtained by using not only immersion tool but also dry tool for gate level. The immersion lithography shrunk the minimum hole pitch from 160nm to 140nm. Thus, the design rule for 45nm node became available by using immersion lithography.

  11. [Memory systems and memory disorders].

    PubMed

    Van der Linden, Martial; Juillerat, Anne-Claude

    2003-02-15

    Recent cognitive models suggest that memory has a complex structure, composed of several independent systems (working memory, and four long-term memory systems: episodic memory, semantic memory, perceptual representation system, and procedural memory). Furthermore, neuropsychological studies show that a brain lesion can selectively impair some systems or some particular process in a system, while others are spared. In this theoretical context, the objective of assessment is to detect the impaired memory systems and processes as well as those, which remain intact. To do this, the clinician has to use various-tests specifically designed to assess the integrity of each memory system and process. PMID:12708274

  12. Memory Loss and Retrieval

    ERIC Educational Resources Information Center

    Reid, Ian

    2016-01-01

    Underlying the generally oblivious attitude of teachers and learners towards the past is insufficient respect for the role of memory in giving meaning to experience and access to knowledge. We shape our identity by making sense of our past and its relationship to present and future selves, a process that should be intensively cultivated when we…

  13. Memory Palaces

    ERIC Educational Resources Information Center

    Wood, Marianne

    2007-01-01

    This article presents a lesson called Memory Palaces. A memory palace is a memory tool used to remember information, usually as visual images, in a sequence that is logical to the person remembering it. In his book, "In the Palaces of Memory", George Johnson calls them "...structure(s) for arranging knowledge. Lots of connections to language arts,…

  14. High-performance 0.25-um CMOS technology for fast SRAMs

    NASA Astrophysics Data System (ADS)

    Hayden, James D.; McNelly, T. F.; Perera, Asanga H.; Pfiester, Jim R.; Subramanian, C. K.; Thompson, Matthew A.

    1996-09-01

    A high performance 0.25 micrometers CMOS process has been developed for fast static RAMs. This technology features retrograde wells, shallow trench isolation scalable to a 0.45 micrometers active pitch, surface channel 0.25 micrometers NMOS and PMOS transistors with a 55 angstroms nitrided gate oxide providing drive currents of 630 and 300 (mu) A/micrometers respectively at off-leakages of 10 pA/micrometers , overgated TFTs with an on/off ratio greater than 6(DOT)105, stacked capacitors for improved SER protection, five levels of polysilicon planarized by chemical-mechanical polishing with two self-aligned interpoly contacts, 0.35 micrometers contacts and a 0.625 metal pitch. In this technology, a triple well structure was used for SER protection. High energy retrograde wells were integrated with shallow trench isolation and epi providing excellent interwell isolation for both leakage and latch-up down to n+/p+ spaces of 0.60 micrometers . PMOS transistors were scaled to a physical gate length of 0.1 micrometers while maintaining excellent short channel characteristics. A split word-line bitcell was scaled to 1.425 micrometers X 2.625 micrometers equals 3.74 micrometers 2 using 0.25 micrometers rules. A tungsten interpoly plug was used to connect the PMOS TFT loads to the underlying NMOS latch gates without a parasitic diode or dopant interdiffusion, connecting 3 polysilicon layers with self-aligned isolation from an intervening polysilicon layer used as a local interconnect. With this plug, TFT drive currents were greatly improved, particularly at low voltages and the memory nodes pulled to the fully supply voltage. Functional 0.25 micrometers bitcells were demonstrated and with an LDD resistor it was possible to double the cell stability. Bitcell simulation was used to demonstrate that a 4T bitcell will be stable at 2.5 V but that a word-line boost will be required for 1.8 V operation.

  15. Vertical-Bloch-Line Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.; Wu, Jiin-Chuan; Stadler, Henry L.

    1993-01-01

    Vertical-Bloch-line memory is developmental very-large-scale integrated-circuit block-access magnetic memory. Stores data in form of localized pairs of twists (VBL pairs) in magnetic field at edge of ferromagnetic domain in each stripe. Presence or absence of VBL pair at bit position denotes one or zero, respectively. Offers advantages of resistance to ionizing radiation, potential areal storage density approximately less than 1 Gb/cm squared, data rates approximately less than 1 Gb/s, and average access times of order of milliseconds. Furthermore, mass, volume, and demand for power less than other magnetic and electronic memories.

  16. Development of Next Generation Memory Test Experiment for Deployment on a Small Satellite

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd; Ho, Fat D.

    2012-01-01

    The original Memory Test Experiment successfully flew on the FASTSAT satellite launched in November 2010. It contained a single Ramtron 512K ferroelectric memory. The memory device went through many thousands of read/write cycles and recorded any errors that were encountered. The original mission length was schedule to last 6 months but was extended to 18 months. New opportunities exist to launch a similar satellite and considerations for a new memory test experiment should be examined. The original experiment had to be designed and integrated in less than two months, so the experiment was a simple design using readily available parts. The follow-on experiment needs to be more sophisticated and encompass more technologies. This paper lays out the considerations for the design and development of this follow-on flight memory experiment. It also details the results from the original Memory Test Experiment that flew on board FASTSAT. Some of the design considerations for the new experiment include the number and type of memory devices to be used, the kinds of tests that will be performed, other data needed to analyze the results, and best use of limited resources on a small satellite. The memory technologies that are considered are FRAM, FLASH, SONOS, Resistive Memory, Phase Change Memory, Nano-wire Memory, Magneto-resistive Memory, Standard DRAM, and Standard SRAM. The kinds of tests that could be performed are read/write operations, non-volatile memory retention, write cycle endurance, power measurements, and testing Error Detection and Correction schemes. Other data that may help analyze the results are GPS location of recorded errors, time stamp of all data recorded, radiation measurements, temperature, and other activities being perform by the satellite. The resources of power, volume, mass, temperature, processing power, and telemetry bandwidth are extremely limited on a small satellite. Design considerations must be made to allow the experiment to not interfere

  17. Logic gates and memory cells based on single C60 electromechanical transistors

    NASA Astrophysics Data System (ADS)

    Ami, S.; Joachim, C.

    2001-03-01

    The equivalent electrical circuit of a single C60 electromechanical transistor in a planar lay-out is presented using its experimental STM characteristics. This circuit is used to demonstrate that such a hybrid molecular electronic device can be used as a class A amplifier, a NOT or NOR gate and to implement an SRAM memory point. All the devices are simulated using the SPICE routine to find their optimum load resistance and cantilever grid size. The class A amplifier can operate with a cut-off frequency of a few gigahertz while the logic gate and memory are limited to a few tens of megahertz, but for a very small power design in the picowatt range.

  18. Comparison of single event upset rates for microelectronic memory devices during interplanetary solar particle events

    NASA Technical Reports Server (NTRS)

    Mckerracher, P. L.; Kinnison, J. D.; Maurer, R. H.

    1993-01-01

    Variability in the methods and models used for single event upset calculations in microelectronic memory devices can lead to a range of possible upset rates. Using heavy ion and proton data for selected DRAM and SRAM memories, we have calculated an array of upset rates in order to compare the Adams worst case interplanetary solar flare model to a model proposed by scientists at the Jet Propulsion Laboratory. In addition, methods of upset rate calculation are compared: the Cosmic Ray Effects on Microelectronics CREME code and a Monte Carlo algorithm developed at the Applied Physics Laboratory. The results show that use of a more realistic, although still conservative, model of the space environment can have significant cost saving benefits.

  19. Implementing a bubble memory hierarchy system

    NASA Technical Reports Server (NTRS)

    Segura, R.; Nichols, C. D.

    1979-01-01

    This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

  20. Resistive switching mechanisms in random access memory devices incorporating transition metal oxides: TiO2, NiO and Pr0.7Ca0.3MnO3.

    PubMed

    Magyari-Köpe, Blanka; Tendulkar, Mihir; Park, Seong-Geon; Lee, Hyung Dong; Nishi, Yoshio

    2011-06-24

    Resistance change random access memory (RRAM) cells, typically built as MIM capacitor structures, consist of insulating layers I sandwiched between metal layers M, where the insulator performs the resistance switching operation. These devices can be electrically switched between two or more stable resistance states at a speed of nanoseconds, with long retention times, high switching endurance, low read voltage, and large switching windows. They are attractive candidates for next-generation non-volatile memory, particularly as a flash successor, as the material properties can be scaled to the nanometer regime. Several resistance switching models have been suggested so far for transition metal oxide based devices, such as charge trapping, conductive filament formation, Schottky barrier modulation, and electrochemical migration of point defects. The underlying fundamental principles of the switching mechanism still lack a detailed understanding, i.e. how to control and modulate the electrical characteristics of devices incorporating defects and impurities, such as oxygen vacancies, metal interstitials, hydrogen, and other metallic atoms acting as dopants. In this paper, state of the art ab initio theoretical methods are employed to understand the effects that filamentary types of stable oxygen vacancy configurations in TiO(2) and NiO have on the electronic conduction. It is shown that strong electronic interactions between metal ions adjacent to oxygen vacancy sites results in the formation of a conductive path and thus can explain the 'ON' site conduction in these materials. Implication of hydrogen doping on electroforming is discussed for Pr(0.7)Ca(0.3)MnO(3) devices based on electrical characterization and FTIR measurements. PMID:21572196

  1. ISDC Data Access Layer

    NASA Astrophysics Data System (ADS)

    Jennings, D.; Borkowski, J.; Contessi, T.; Lock, T.; Rohlfs, R.; Walter, R.

    The ISDC Data Access Layer (DAL) is an ANSI C and \\fortran 90 compatible library under development in support of the ESA INTEGRAL mission data analysis software. DALs primary purpose is to isolate the analysis software from the specifics of the data formats while at the same time providing new data abstraction and access capabilities. DAL supports the creation and manipulation of hierarchical data sets which may span multiple files and, in theory, multiple computer systems. A number of Application Programming Interfaces (APIs) are supported by DAL that allow software to view and access data at different levels of complexity. DAL also allows data sets to reside on disk, in conventional memory or in shared memory in a way that is transparent to the user/application.

  2. Nanoporous silicon oxide memory.

    PubMed

    Wang, Gunuk; Yang, Yang; Lee, Jae-Hwang; Abramova, Vera; Fei, Huilong; Ruan, Gedeng; Thomas, Edwin L; Tour, James M

    2014-08-13

    Oxide-based two-terminal resistive random access memory (RRAM) is considered one of the most promising candidates for next-generation nonvolatile memory. We introduce here a new RRAM memory structure employing a nanoporous (NP) silicon oxide (SiOx) material which enables unipolar switching through its internal vertical nanogap. Through the control of the stochastic filament formation at low voltage, the NP SiOx memory exhibited an extremely low electroforming voltage (∼ 1.6 V) and outstanding performance metrics. These include multibit storage ability (up to 9-bits), a high ON-OFF ratio (up to 10(7) A), a long high-temperature lifetime (≥ 10(4) s at 100 °C), excellent cycling endurance (≥ 10(5)), sub-50 ns switching speeds, and low power consumption (∼ 6 × 10(-5) W/bit). Also provided is the room temperature processability for versatile fabrication without any compliance current being needed during electroforming or switching operations. Taken together, these metrics in NP SiOx RRAM provide a route toward easily accessed nonvolatile memory applications. PMID:24992278

  3. A Pilot Memory Café for People with Learning Disabilities and Memory Difficulties

    ERIC Educational Resources Information Center

    Kiddle, Hannah; Drew, Neil; Crabbe, Paul; Wigmore, Jonathan

    2016-01-01

    Memory cafés have been found to normalise experiences of dementia and provide access to an accepting social network. People with learning disabilities are at increased risk of developing dementia, but the possible benefits of attending a memory café are not known. This study evaluates a 12-week pilot memory café for people with learning…

  4. Neural Correlates of Conceptual Implicit Memory and Their Contamination of Putative Neural Correlates of Explicit Memory

    ERIC Educational Resources Information Center

    Voss, Joel L.; Paller, Ken A.

    2007-01-01

    During episodic recognition tests, meaningful stimuli such as words can engender both conscious retrieval (explicit memory) and facilitated access to meaning that is distinct from the awareness of remembering (conceptual implicit memory). Neuroimaging investigations of one type of memory are frequently subject to the confounding influence of the…

  5. Memory systems.

    PubMed

    Wolk, David A; Budson, Andrew E

    2010-08-01

    Converging evidence from patient and neuroimaging studies suggests that memory is a collection of abilities that use different neuroanatomic systems. Neurologic injury may impair one or more of these memory systems. Episodic memory allows us to mentally travel back in time and relive an episode of our life. Episodic memory depends on the hippocampus, other medial temporal lobe structures, the limbic system, and the frontal lobes, as well as several other brain regions. Semantic memory provides our general knowledge about the world and is unconnected to any specific episode of our life. Although semantic memory likely involves much of the neocortex, the inferolateral temporal lobes (particularly the left) are most important. Procedural memory enables us to learn cognitive and behavioral skills and algorithms that operate at an automatic, unconscious level. Damage to the basal ganglia, cerebellum, and supplementary motor area often impair procedural memory. PMID:22810510

  6. Cognitive memory.

    PubMed

    Widrow, Bernard; Aragon, Juan Carlos

    2013-05-01

    Regarding the workings of the human mind, memory and pattern recognition seem to be intertwined. You generally do not have one without the other. Taking inspiration from life experience, a new form of computer memory has been devised. Certain conjectures about human memory are keys to the central idea. The design of a practical and useful "cognitive" memory system is contemplated, a memory system that may also serve as a model for many aspects of human memory. The new memory does not function like a computer memory where specific data is stored in specific numbered registers and retrieval is done by reading the contents of the specified memory register, or done by matching key words as with a document search. Incoming sensory data would be stored at the next available empty memory location, and indeed could be stored redundantly at several empty locations. The stored sensory data would neither have key words nor would it be located in known or specified memory locations. Sensory inputs concerning a single object or subject are stored together as patterns in a single "file folder" or "memory folder". When the contents of the folder are retrieved, sights, sounds, tactile feel, smell, etc., are obtained all at the same time. Retrieval would be initiated by a query or a prompt signal from a current set of sensory inputs or patterns. A search through the memory would be made to locate stored data that correlates with or relates to the prompt input. The search would be done by a retrieval system whose first stage makes use of autoassociative artificial neural networks and whose second stage relies on exhaustive search. Applications of cognitive memory systems have been made to visual aircraft identification, aircraft navigation, and human facial recognition. Concerning human memory, reasons are given why it is unlikely that long-term memory is stored in the synapses of the brain's neural networks. Reasons are given suggesting that long-term memory is stored in DNA or RNA

  7. Unifying Memory and Database Transactions

    NASA Astrophysics Data System (ADS)

    Dias, Ricardo J.; Lourenço, João M.

    Software Transactional Memory is a concurrency control technique gaining increasing popularity, as it provides high-level concurrency control constructs and eases the development of highly multi-threaded applications. But this easiness comes at the expense of restricting the operations that can be executed within a memory transaction, and operations such as terminal and file I/O are either not allowed or incur in serious performance penalties. Database I/O is another example of operations that usually are not allowed within a memory transaction. This paper proposes to combine memory and database transactions in a single unified model, benefiting from the ACID properties of the database transactions and from the speed of main memory data processing. The new unified model covers, without differentiating, both memory and database operations. Thus, the users are allowed to freely intertwine memory and database accesses within the same transaction, knowing that the memory and database contents will always remain consistent and that the transaction will atomically abort or commit the operations in both memory and database. This approach allows to increase the granularity of the in-memory atomic actions and hence, simplifies the reasoning about them.

  8. 0.6-1.0 V operation set/reset voltage (3 V) generator for three-dimensional integrated resistive random access memory and NAND flash hybrid solid-state drive

    NASA Astrophysics Data System (ADS)

    Tanaka, Masahiro; Hachiya, Shogo; Ishii, Tomoya; Ning, Sheyang; Tsurumi, Kota; Takeuchi, Ken

    2016-04-01

    A 0.6-1.0 V, 25.9 mm2 boost converter is proposed to generate resistive random access memory (ReRAM) write (set/reset) voltage for three-dimensional (3D) integrated ReRAM and NAND flash hybrid solid-state drive (SSD). The proposed boost converter uses an integrated area-efficient V BUF generation circuit to obtain short ReRAM sector write time, small circuit size, and small energy consumption simultaneously. In specific, the proposed boost converter reduces ReRAM sector write time by 65% compared with a conventional one-stage boost converter (Conventional 1) which uses 1.0 V operating voltage. On the other hand, by using the same ReRAM sector write time, the proposed boost converter reduces 49% circuit area and 46% energy consumption compared with a conventional two-stage boost converter (Conventional 2). In addition, by using the proposed boost converter, the operating voltage, V DD, can be reduced to 0.6 V. The lowest 159 nJ energy consumption can be obtained when V DD is 0.7 V.

  9. Resistive switching and electrical control of ferromagnetism in a Ag/HfO2/Nb:SrTiO3/Ag resistive random access memory (RRAM) device at room temperature

    NASA Astrophysics Data System (ADS)

    Ren, Shaoqing; Zhu, Gengchang; Xie, Jihao; Bu, Jianpei; Qin, Hongwei; Hu, Jifan

    2016-02-01

    Electrically induced resistive switching and modulated ferromagnetism are simultaneously found in a Ag/HfO2/Nb:SrTiO3/Ag resistive random access memory device at room temperature. The bipolar resistive switching (RS) can be controlled by the modification of a Schottky-like barrier with an electron injection-trapped/detrapped process at the interface of HfO2-Nb:SrTiO3. The multilevel RS transition can be observed in the reset process with larger negative voltage sweepings, which is connected to the different degree of electron detrapping in the interfacial depletion region of the HfO2 layer during the reset process. The origin of the electrical control of room-temperature ferromagnetism may be connected to the change of density of oxygen vacancies in the HfO2 film. The multilevel resistance states and the electric field controlled ferromagnetism have potential for applications in ultrahigh-density storage and magnetic logic device.

  10. Declarative memory.

    PubMed

    Riedel, Wim J; Blokland, Arjan

    2015-01-01

    Declarative Memory consists of memory for events (episodic memory) and facts (semantic memory). Methods to test declarative memory are key in investigating effects of potential cognition-enhancing substances--medicinal drugs or nutrients. A number of cognitive performance tests assessing declarative episodic memory tapping verbal learning, logical memory, pattern recognition memory, and paired associates learning are described. These tests have been used as outcome variables in 34 studies in humans that have been described in the literature in the past 10 years. Also, the use of episodic tests in animal research is discussed also in relation to the drug effects in these tasks. The results show that nutritional supplementation of polyunsaturated fatty acids has been investigated most abundantly and, in a number of cases, but not all, show indications of positive effects on declarative memory, more so in elderly than in young subjects. Studies investigating effects of registered anti-Alzheimer drugs, cholinesterase inhibitors in mild cognitive impairment, show positive and negative effects on declarative memory. Studies mainly carried out in healthy volunteers investigating the effects of acute dopamine stimulation indicate enhanced memory consolidation as manifested specifically by better delayed recall, especially at time points long after learning and more so when drug is administered after learning and if word lists are longer. The animal studies reveal a different picture with respect to the effects of different drugs on memory performance. This suggests that at least for episodic memory tasks, the translational value is rather poor. For the human studies, detailed parameters of the compositions of word lists for declarative memory tests are discussed and it is concluded that tailored adaptations of tests to fit the hypothesis under study, rather than "off-the-shelf" use of existing tests, are recommended. PMID:25977084

  11. Logical Access Control Mechanisms in Computer Systems.

    ERIC Educational Resources Information Center

    Hsiao, David K.

    The subject of access control mechanisms in computer systems is concerned with effective means to protect the anonymity of private information on the one hand, and to regulate the access to shareable information on the other hand. Effective means for access control may be considered on three levels: memory, process and logical. This report is a…

  12. Implementation of Ferroelectric Memories for Space Applications

    NASA Technical Reports Server (NTRS)

    Philpy, Stephen C.; Derbenwick, Gary F.; Kamp, David A.; Isaacson, Alan F.

    2000-01-01

    Ferroelectric random access semiconductor memories (FeRAMs) are an ideal nonvolatile solution for space applications. These memories have low power performance, high endurance and fast write times. By combining commercial ferroelectric memory technology with radiation hardened CMOS technology, nonvolatile semiconductor memories for space applications can be attained. Of the few radiation hardened semiconductor manufacturers, none have embraced the development of radiation hardened FeRAMs, due a limited commercial space market and funding limitations. Government funding may be necessary to assure the development of radiation hardened ferroelectric memories for space applications.

  13. Virtual memory

    NASA Technical Reports Server (NTRS)

    Denning, P. J.

    1986-01-01

    Virtual memory was conceived as a way to automate overlaying of program segments. Modern computers have very large main memories, but need automatic solutions to the relocation and protection problems. Virtual memory serves this need as well and is thus useful in computers of all sizes. The history of the idea is traced, showing how it has become a widespread, little noticed feature of computers today.

  14. Vertical bloch line memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-chuan (Inventor)

    1995-01-01

    A new read gate design for the vertical Bloch line (VBL) memory is disclosed which offers larger operating margin than the existing read gate designs. In the existing read gate designs, a current is applied to all the stripes. The stripes that contain a VBL pair are chopped, while the stripes that do not contain a VBL pair are not chopped. The information is then detected by inspecting the presence or absence of the bubble. The margin of the chopping current amplitude is very small, and sometimes non-existent. A new method of reading Vertical Bloch Line memory is also disclosed. Instead of using the wall chirality to separate the two binary states, the spatial deflection of the stripe head is used. Also disclosed herein is a compact memory which uses vertical Bloch line (VBL) memory technology for providing data storage. A three-dimensional arrangement in the form of stacks of VBL memory layers is used to achieve high volumetric storage density. High data transfer rate is achieved by operating all the layers in parallel. Using Hall effect sensing, and optical sensing via the Faraday effect to access the data from within the three-dimensional packages, an even higher data transfer rate can be achieved due to parallel operation within each layer.

  15. Three dimensional magnetic abacus memory

    NASA Astrophysics Data System (ADS)

    Zhang, Shilei; Zhang, Jingyan; Baker, Alexander; Wang, Shouguo; Yu, Guanghua; Hesjedal, Thorsten

    2015-03-01

    Stacking nonvolatile memory cells into a three-dimensional matrix represents a powerful solution for the future of magnetic memory. However, it is technologically challenging to access the individual data in the storage medium if large numbers of bits are stacked on top of each other. Here we introduce a new type of multilevel, nonvolatile magnetic memory concept, the magnetic abacus. Instead of storing information in individual magnetic layers, thereby having to read out each magnetic layer separately, the magnetic abacus adopts a new encoding scheme which envisages a classical abacus with the beads operated by electron spins. It is inspired by the idea of second quantization, dealing with the memory state of the entire stack simultaneously. Direct read operations are implemented by measuring the artificially engineered `quantized' Hall voltage, representing a count of the spin-up and spin-down layers in the stack. This concept of `second quantization of memory' realizes the 3D memory architecture with superior reading and operation efficiency, thus is a promising approach for future nonvolatile magnetic random access memory.

  16. Ferroelectric memory

    NASA Astrophysics Data System (ADS)

    Vorotilov, K. A.; Sigov, A. S.

    2012-05-01

    The current status of developments in the field of ferroelectric memory devices has been considered. The rapidly growing market of non-volatile memory devices has been analyzed, and the current state of the art and prospects for the scaling of parameters of non-volatile memory devices of different types have been considered. The basic constructive and technological solutions in the field of the design of ferroelectric memory devices, as well as the "roadmaps" of the development of this technology, have been discussed.

  17. Neural correlates of conceptual implicit memory and their contamination of putative neural correlates of explicit memory.

    PubMed

    Voss, Joel L; Paller, Ken A

    2007-04-01

    During episodic recognition tests, meaningful stimuli such as words can engender both conscious retrieval (explicit memory) and facilitated access to meaning that is distinct from the awareness of remembering (conceptual implicit memory). Neuroimaging investigations of one type of memory are frequently subject to the confounding influence of the other type of memory, thus posing a serious impediment to theoretical advances in this area. We used minimalist visual shapes (squiggles) to attempt to overcome this problem. Subjective ratings of squiggle meaningfulness varied idiosyncratically, and behavioral indications of conceptual implicit memory were evident only for stimuli given higher ratings. These effects did not result from perceptual-based fluency or from explicit remembering. Distinct event-related brain potentials were associated with conceptual implicit memory and with explicit memory by virtue of contrasts based on meaningfulness ratings and memory judgments, respectively. Frontal potentials from 300 to 500 msec after the onset of repeated squiggles varied systematically with perceived meaningfulness. Explicit memory was held constant in this contrast, so these potentials were taken as neural correlates of conceptual implicit memory. Such potentials can contaminate putative neural correlates of explicit memory, in that they are frequently attributed to the expression of explicit memory known as familiarity. These findings provide the first neural dissociation of these two memory phenomena during recognition testing and underscore the necessity of taking both types of memory into account in order to obtain valid neural correlates of specific memory functions. PMID:17412965

  18. Childhood Memories.

    ERIC Educational Resources Information Center

    Danielson, Kathy Everts

    1989-01-01

    Provides numerous ideas for helping students write about special memories in the following categories: growing up--future dreams; authors and illustrators; family history; special places; and special memories. Describes how to write a "bio poem," and includes a bibliography of children's books that enhance and enrich student learning and writing.…

  19. Memory Magic.

    ERIC Educational Resources Information Center

    Hartman, Thomas G.; Nowak, Norman

    This paper outlines several "tricks" that aid students in improving their memories. The distinctions between operational and figural thought processes are noted. Operational memory is described as something that allows adults to make generalizations about numbers and the rules by which they may be combined, thus leading to easier memorization.…

  20. Collaging Memories

    ERIC Educational Resources Information Center

    Wallach, Michele

    2011-01-01

    Even middle school students can have memories of their childhoods, of an earlier time. The art of Romare Bearden and the writings of Paul Auster can be used to introduce ideas about time and memory to students and inspire works of their own. Bearden is an exceptional role model for young artists, not only because of his astounding art, but also…

  1. Episodic Memories

    ERIC Educational Resources Information Center

    Conway, Martin A.

    2009-01-01

    An account of episodic memories is developed that focuses on the types of knowledge they represent, their properties, and the functions they might serve. It is proposed that episodic memories consist of "episodic elements," summary records of experience often in the form of visual images, associated to a "conceptual frame" that provides a…

  2. Runtime and Programming Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory

    SciTech Connect

    Mills, Richard T; Yue, Chuan; Andreas, Stathopoulos; Nikolopoulos, Dimitrios S

    2007-01-01

    The ever increasing memory demands of many scientific applications and the complexity of today's shared computational resources still require the occasional use of virtual memory, network memory, or even out-of-core implementations, with well known drawbacks in performance and usability. In Mills et al. (Adapting to memory pressure from within scientific applications on multiprogrammed COWS. In: International Parallel and Distributed Processing Symposium, IPDPS, Santa Fe, NM, 2004), we introduced a basic framework for a runtime, user-level library, MMlib, in which DRAM is treated as a dynamic size cache for large memory objects residing on local disk. Application developers can specify and access these objects through MMlib, enabling their application to execute optimally under variable memory availability, using as much DRAM as fluctuating memory levels will allow. In this paper, we first extend our earlier MMlib prototype from a proof of concept to a usable, robust, and flexible library. We present a general framework that enables fully customizable memory malleability in a wide variety of scientific applications. We provide several necessary enhancements to the environment sensing capabilities of MMlib, and introduce a remote memory capability, based on MPI communication of cached memory blocks between 'compute nodes' and designated memory servers. The increasing speed of interconnection networks makes a remote memory approach attractive, especially at the large granularity present in large scientific applications. We show experimental results from three important scientific applications that require the general MMlib framework. The memory-adaptive versions perform nearly optimally under constant memory pressure and execute harmoniously with other applications competing for memory, without thrashing the memory system. Under constant memory pressure, we observe execution time improvements of factors between three and

  3. 32-Bit-Wide Memory Tolerates Failures

    NASA Technical Reports Server (NTRS)

    Buskirk, Glenn A.

    1990-01-01

    Electronic memory system of 32-bit words corrects bit errors caused by some common type of failures - even failure of entire 4-bit-wide random-access-memory (RAM) chip. Detects failure of two such chips, so user warned that ouput of memory may contain errors. Includes eight 4-bit-wide DRAM's configured so each bit of each DRAM assigned to different one of four parallel 8-bit words. Each DRAM contributes only 1 bit to each 8-bit word.

  4. Direct memory access transfer completion notification

    DOEpatents

    Archer, Charles J.; Blocksome, Michael A.; Parker, Jeffrey J.

    2010-08-17

    Methods, apparatus, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA engine on an origin compute node in an injection FIFO buffer, a data descriptor for an application message to be transferred to a target compute node on behalf of an application on the origin compute node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying an address of a completion notification field in application storage for the application; transferring, by the origin DMA engine to the target compute node, the message in dependence upon the data descriptor; and notifying, by the origin DMA engine, the application that the transfer of the message is complete, including performing a local direct put operation to store predesignated notification data at the address of the completion notification field.

  5. Direct memory access transfer completion notification

    DOEpatents

    Archer, Charles J. , Blocksome; Michael A. , Parker; Jeffrey J.

    2011-02-15

    Methods, systems, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA on an origin node in an origin injection FIFO, a data descriptor for an application message; inserting, by the origin DMA, a reflection descriptor in the origin injection FIFO, the reflection descriptor specifying a remote get operation for injecting a completion notification descriptor in a reflection injection FIFO on a reflection node; transferring, by the origin DMA to a target node, the message in dependence upon the data descriptor; in response to completing the message transfer, transferring, by the origin DMA to the reflection node, the completion notification descriptor in dependence upon the reflection descriptor; receiving, by the origin DMA from the reflection node, a completion packet; and notifying, by the origin DMA in response to receiving the completion packet, the origin node's processing core that the message transfer is complete.

  6. Three dimensional magnetic abacus memory

    NASA Astrophysics Data System (ADS)

    Zhang, Shilei; Zhang, Jingyan; Baker, Alexander A.; Wang, Shouguo; Yu, Guanghua; Hesjedal, Thorsten

    2014-08-01

    Stacking nonvolatile memory cells into a three-dimensional matrix represents a powerful solution for the future of magnetic memory. However, it is technologically challenging to access the data in the storage medium if large numbers of bits are stacked on top of each other. Here we introduce a new type of multilevel, nonvolatile magnetic memory concept, the magnetic abacus. Instead of storing information in individual magnetic layers, thereby having to read out each magnetic layer separately, the magnetic abacus adopts a new encoding scheme. It is inspired by the idea of second quantisation, dealing with the memory state of the entire stack simultaneously. Direct read operations are implemented by measuring the artificially engineered `quantised' Hall voltage, each representing a count of the spin-up and spin-down layers in the stack. This new memory system further allows for both flexible scaling of the system and fast communication among cells. The magnetic abacus provides a promising approach for future nonvolatile 3D magnetic random access memory.

  7. Three dimensional magnetic abacus memory.

    PubMed

    Zhang, ShiLei; Zhang, JingYan; Baker, Alexander A; Wang, ShouGuo; Yu, GuangHua; Hesjedal, Thorsten

    2014-01-01

    Stacking nonvolatile memory cells into a three-dimensional matrix represents a powerful solution for the future of magnetic memory. However, it is technologically challenging to access the data in the storage medium if large numbers of bits are stacked on top of each other. Here we introduce a new type of multilevel, nonvolatile magnetic memory concept, the magnetic abacus. Instead of storing information in individual magnetic layers, thereby having to read out each magnetic layer separately, the magnetic abacus adopts a new encoding scheme. It is inspired by the idea of second quantisation, dealing with the memory state of the entire stack simultaneously. Direct read operations are implemented by measuring the artificially engineered 'quantised' Hall voltage, each representing a count of the spin-up and spin-down layers in the stack. This new memory system further allows for both flexible scaling of the system and fast communication among cells. The magnetic abacus provides a promising approach for future nonvolatile 3D magnetic random access memory. PMID:25146338

  8. Kanerva's sparse distributed memory: An associative memory algorithm well-suited to the Connection Machine

    NASA Technical Reports Server (NTRS)

    Rogers, David

    1988-01-01

    The advent of the Connection Machine profoundly changes the world of supercomputers. The highly nontraditional architecture makes possible the exploration of algorithms that were impractical for standard Von Neumann architectures. Sparse distributed memory (SDM) is an example of such an algorithm. Sparse distributed memory is a particularly simple and elegant formulation for an associative memory. The foundations for sparse distributed memory are described, and some simple examples of using the memory are presented. The relationship of sparse distributed memory to three important computational systems is shown: random-access memory, neural networks, and the cerebellum of the brain. Finally, the implementation of the algorithm for sparse distributed memory on the Connection Machine is discussed.

  9. A Calendar Savant with Episodic Memory Impairments

    PubMed Central

    Olson, Ingrid R.; Berryhill, Marian E.; Drowos, David B.; Brown, Lawrence; Chatterjee, Anjan

    2010-01-01

    Patients with memory disorders have severely restricted learning and memory. For instance, patients with anterograde amnesia can learn motor procedures as well as retaining some restricted ability to learn new words and factual information. However, such learning is inflexible and frequently inaccessible to conscious awareness. Here we present a case of patient AC596, a 25-year old male with severe episodic memory impairments, presumably due to anoxia during a preterm birth. In contrast to his poor episodic memory, he exhibits savant-like memory for calendar information that can be flexibly accessed by day, month, and year cues. He also has the ability to recollect the exact date of a wide range of personal experiences over the past 20 years. The patient appears to supplement his generally poor episodic memory by using memorized calendar information as a retrieval cue for autobiographical events. These findings indicate that islands of preserved memory functioning, such as a highly developed semantic memory system, can exist in individuals with severely impaired episodic memory systems. In this particular case, our patient’s memory for dates far outstripped that of normal individuals and served as a keen retrieval cue, allowing him to access information that was otherwise unavailable. PMID:20104390

  10. Memory reloaded: memory load effects in the attentional blink.

    PubMed

    Visser, Troy A W

    2010-06-01

    When two targets are presented in rapid succession, identification of the first is nearly perfect, while identification of the second is impaired when it follows the first by less than about 700 ms. According to bottleneck models, this attentional blink (AB) occurs because the second target is unable to gain access to capacity-limited working memory processes already occupied by the first target. Evidence for this hypothesis, however, has been mixed, with recent reports suggesting that increasing working memory load does not affect the AB. The present paper explores possible reasons for failures to find a link between memory load and the AB and shows that a reliable effect of load can be obtained when the item directly after T1 (Target 1) is omitted. This finding provides initial evidence that working memory load can influence the AB and additional evidence for a link between T1 processing time and the AB predicted by bottleneck models. PMID:19787551

  11. Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

    SciTech Connect

    Schreiber, Robert

    2014-11-26

    Summary of technical results of Blackcomb Memory Devices We explored various different memory technologies (STTRAM, PCRAM, FeRAM, and ReRAM). The progress can be classified into three categories, below. Modeling and Tool Releases Various modeling tools have been developed over the last decade to help in the design of SRAM or DRAM-based memory hierarchies. To explore new design opportunities that NVM technologies can bring to the designers, we have developed similar high-level models for NVM, including PCRAMsim [Dong 2009], NVSim [Dong 2012], and NVMain [Poremba 2012]. NVSim is a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies. On the other side, NVMain is a cycle accurate main memory simulator designed to simulate emerging nonvolatile memories at the architectural level. We have released these models as open source tools and provided contiguous support to them. We also proposed PS3-RAM, which is a fast, portable and scalable statistical STT-RAM reliability analysis model [Wen 2012]. Design Space Exploration and Optimization With the support of these models, we explore different device/circuit optimization techniques. For example, in [Niu 2012a] we studied the power reduction technique for the application of ECC scheme in ReRAM designs and proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both 1T1R and cross-point ReRAM designs. In [Xu 2011], we proposed a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We also studied the tradeoffs in building a reliable crosspoint Re

  12. Memory loss

    MedlinePlus

    ... usually include asking questions of family members and friends. For this reason, they should come to the appointment. Medical history questions may include: Type of memory loss, such as short-term or long-term ...

  13. Staging memory for massively parallel processor

    NASA Technical Reports Server (NTRS)

    Batcher, Kenneth E. (Inventor)

    1988-01-01

    The invention herein relates to a computer organization capable of rapidly processing extremely large volumes of data. A staging memory is provided having a main stager portion consisting of a large number of memory banks which are accessed in parallel to receive, store, and transfer data words simultaneous with each other. Substager portions interconnect with the main stager portion to match input and output data formats with the data format of the main stager portion. An address generator is coded for accessing the data banks for receiving or transferring the appropriate words. Input and output permutation networks arrange the lineal order of data into and out of the memory banks.

  14. A memory advantage for property.

    PubMed

    DeScioli, Peter; Rosa, Nicole M; Gutchess, Angela H

    2015-01-01

    People's access to resources depends on their status as the owner of particular items. To respect property, people need to remember who owns which objects. We test the hypothesis that people possess enhanced memory for ownership relations compared to unrelated objects. Participants viewed a sequence of 10 person-object pairs before completing a surprise associative memory test in which they matched each person with the previously paired object. We varied the description of the person-object pairs in the instructions. Across three experiments, participants showed better recall when the person was described as the owner of the object compared to being unrelated. Furthermore, memory for property was better than a physical relation (bumping), whereas it did not differ from mental relations (wanting and thinking). These patterns were observed both for memory of items (Experiments 1 and 2) and perceptual details (Experiment 3). We discuss implications for how people remember other people's property. PMID:25986536

  15. Misaligned feeding impairs memories

    PubMed Central

    Loh, Dawn H; Jami, Shekib A; Flores, Richard E; Truong, Danny; Ghiani, Cristina A; O’Dell, Thomas J; Colwell, Christopher S

    2015-01-01

    Robust sleep/wake rhythms are important for health and cognitive function. Unfortunately, many people are living in an environment where their circadian system is challenged by inappropriate meal- or work-times. Here we scheduled food access to the sleep time and examined the impact on learning and memory in mice. Under these conditions, we demonstrate that the molecular clock in the master pacemaker, the suprachiasmatic nucleus (SCN), is unaltered while the molecular clock in the hippocampus is synchronized by the timing of food availability. This chronic circadian misalignment causes reduced hippocampal long term potentiation and total CREB expression. Importantly this mis-timed feeding resulted in dramatic deficits in hippocampal-dependent learning and memory. Our findings suggest that the timing of meals have far-reaching effects on hippocampal physiology and learned behaviour. DOI: http://dx.doi.org/10.7554/eLife.09460.001 PMID:26652002

  16. Basic memory module

    NASA Technical Reports Server (NTRS)

    Tietze, F. C.

    1974-01-01

    Construction and electrical characterization of the 4096 x 2-bit Basic Memory Module (BMM) are reported for the Space Ultrareliable Modular Computer (SUMC) program. The module uses four 2K x 1-bit N-channel FET, random access memory chips, called array chips, and two sense amplifier chips, mounted and interconnected on a ceramic substrate. Four 5% tolerance power supplies are required. At the Module, the address, chip select, and array select lines require a 0-8.5 V MOS signal level. The data output, read-strobe, and write-enable lines operate at TTl levels. Although the module is organized as 4096 x 2 bits, it can be used in a 8196 x 1-bit application with appropriate external connections. A 4096 x 1-bit organization can be obtained by depopulating chips.

  17. Device simulation of charge collection and single-event upset

    SciTech Connect

    Dodd, P.E.

    1996-04-01

    In this paper the author reviews the current status of device simulation of ionizing-radiation-induced charge collection and single-event upset (SEU), with an emphasis on significant results of recent years. The author presents an overview of device-modeling techniques applicable to the SEU problem and the unique challenges this task presents to the device modeler. He examines unloaded simulations of radiation-induced charge collection in simple p/n diodes, SEU in dynamic random access memories (DRAM`s), and SEU in static random access memories (SRAM`s). The author concludes with a few thoughts on future issues likely to confront the SEU device modeler.

  18. System and method for programmable bank selection for banked memory subsystems

    DOEpatents

    Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

    2010-09-07

    A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

  19. Empathy and autobiographical memory: are they linked?

    PubMed

    Tani, Franca; Peterson, Carole; Smorti, Andrea

    2014-01-01

    Autobiographical memory and empathy have been linked with social interaction variables as well as gender in independent bodies of literature. However a scarcity of research exists on the direct link between autobiographical memory and empathy. Exploring this link, in particular for memory of friendships and empathy, was the authors' main aim. A total of 107 Italian undergraduates participated. A memory fluency task was used to assess accessibility of memories spanning their entire life (preschool through university) and an empathy scale (Italian version of the Interpersonal Reactivity Index) was employed to measure the participants' level and dimensions of empathy. For men, empathy scores were related to how many memories they could recall. Specifically, men with higher scores on the fantasy and empathic concern scales and those with lower scores on the personal distress scales recalled more memories of friends. However, affective quality of their memories was unrelated to empathy. In contrast, for women there was no relationship between number of memories and empathy, but the emotional tone of their memories was related to empathy: those with higher scores on the personal distress scale had proportionately fewer affectively positive memories. Results are discussed in terms of gender differences in both empathy and parental socialization patterns. PMID:25175530

  20. Memory consolidation.

    PubMed

    Squire, Larry R; Genzel, Lisa; Wixted, John T; Morris, Richard G

    2015-08-01

    Conscious memory for a new experience is initially dependent on information stored in both the hippocampus and neocortex. Systems consolidation is the process by which the hippocampus guides the reorganization of the information stored in the neocortex such that it eventually becomes independent of the hippocampus. Early evidence for systems consolidation was provided by studies of retrograde amnesia, which found that damage to the hippocampus-impaired memories formed in the recent past, but typically spared memories formed in the more remote past. Systems consolidation has been found to occur for both episodic and semantic memories and for both spatial and nonspatial memories, although empirical inconsistencies and theoretical disagreements remain about these issues. Recent work has begun to characterize the neural mechanisms that underlie the dialogue between the hippocampus and neocortex (e.g., "neural replay," which occurs during sharp wave ripple activity). New work has also identified variables, such as the amount of preexisting knowledge, that affect the rate of consolidation. The increasing use of molecular genetic tools (e.g., optogenetics) can be expected to further improve understanding of the neural mechanisms underlying consolidation. PMID:26238360