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Sample records for access memory rram

  1. Feasibility study of using a Zener diode as the selection device for bipolar RRAM and WORM memory arrays

    NASA Astrophysics Data System (ADS)

    Li, Yingtao; Fu, Liping; Tao, Chunlan; Jiang, Xinyu; Sun, Pengxiao

    2014-01-01

    Cross-bar arrays are usually used for the high density application of resistive random access memory (RRAM) devices. However, cross-talk interference limits an increase in the integration density. In this paper, the Zener diode is proposed as a selection device to suppress the sneak current in bipolar RRAM arrays. Measurement results show that the Zener diode can act as a good selection device, and the sneak current can be effectively suppressed. The readout margin is sufficiently improved compared to that obtained without the selection device. Due to the improvement for the reading disturbance, the size of the cross-bar array can be enhanced to more than 103 × 103. Furthermore, the possibility of using a write-once-read-many-times (WORM) cross-bar array is also demonstrated by connecting the Zener diode and the bipolar RRAM in series. These results strongly suggest that using a Zener diode as a selection device opens up great opportunities to realize high density bipolar RRAM arrays.

  2. An efficient method for evaluating RRAM crossbar array performance

    NASA Astrophysics Data System (ADS)

    Song, Lin; Zhang, Jinyu; Chen, An; Wu, Huaqiang; Qian, He; Yu, Zhiping

    2016-06-01

    An efficient method is proposed in this paper to mitigate computational burden in resistive random access memory (RRAM) array simulation. In the worst case scenario, a 4 Mb RRAM array with line resistance is greatly reduced using this method. For 1S1R-RRAM array structures, static and statistical parameters in both reading and writing processes are simulated. Error analysis is performed to prove the reliability of the algorithm when line resistance is extremely small compared with the junction resistance. Results show that high precision is maintained even if the size of RRAM array is reduced by one thousand times, which indicates significant improvements in both computational efficiency and memory requirements.

  3. High mechanical endurance RRAM based on amorphous gadolinium oxide for flexible nonvolatile memory application

    NASA Astrophysics Data System (ADS)

    Zhao, Hongbin; Tu, Hailing; Wei, Feng; Shi, Zhitian; Xiong, Yuhua; Zhang, Yan; Du, Jun

    2015-05-01

    In this paper, we use amorphous Gd2O3 as the switching layer for fabricated RRAM devices with novel high performance, excellent flexibility, and mechanical endurance properties as potential candidate memory for flexible electronics applications. The obtained Cu/Gd2O3/Pt devices on flexible polyethylene terephthalate (PET) substrates show bipolar switching characteristics, low voltage operation (<2 V) and long retention time (>106 s). No performance degradation occurs, and the stored information is not lost after the device has been bent to different angles and up to 104 times in the bending tests. Based on temperature-dependent switching characteristics, the formation of Cu conducting filaments stemming from electrochemical reactions is believed to be the reason for the resistance switching from a high resistance state to a low resistance state. The studies of the integrated experiment and mechanism lay the foundation for the development of high-performance flexible RRAM.

  4. A Built-In Self-Test Structure (BIST) for Resistive RAMs characterization: Application to bipolar OxRRAM

    NASA Astrophysics Data System (ADS)

    Aziza, H.; Bocquet, M.; Moreau, M.; Portal, J.-M.

    2015-01-01

    Resistive Random Access Memory (RRAM) is a form of nonvolatile storage that operates by changing the resistance of a specially formulated solid dielectric material [1]. Among RRAMs, oxide-based Resistive RAMs (so-called OxRRAMs) are promising candidates due their compatibility with CMOS processes and high ON/OFF resistance ratio. Common problems with OxRRAM are related to high variability in operating conditions and low yield. OxRRAM variability mainly impact ON/OFF resistance ratio. This ratio is a key parameter to determine the overall performance of an OxRRAM memory. In this context, the presented built-in structure allows collecting statistical data related to the OxRRAM memory array (ON/OFF resistance distributions) for reliability assessment of the technology.

  5. Characteristics and mechanism study of cerium oxide based random access memories

    SciTech Connect

    Hsieh, Cheng-Chih; Roy, Anupam; Rai, Amritesh; Chang, Yao-Feng; Banerjee, Sanjay K.

    2015-04-27

    In this work, low operating voltage and high resistance ratio of different resistance states of binary transition metal oxide based resistive random access memories (RRAMs) are demonstrated. Binary transition metal oxides with high dielectric constant have been explored for RRAM application for years. However, CeO{sub x} is considered as a relatively new material to other dielectrics. Since research on CeO{sub x} based RRAM is still at preliminary stage, fundamental characteristics of RRAM such as scalability and mechanism studies need to be done before moving further. Here, we show very high operation window and low switching voltage of CeO{sub x} RRAMs and also compare electrical performance of Al/CeO{sub x}/Au system between different thin film deposition methods and discuss characteristics and resistive switching mechanism.

  6. Thermal crosstalk in 3-dimensional RRAM crossbar array.

    PubMed

    Sun, Pengxiao; Lu, Nianduan; Li, Ling; Li, Yingtao; Wang, Hong; Lv, Hangbing; Liu, Qi; Long, Shibing; Liu, Su; Liu, Ming

    2015-01-01

    High density 3-dimensional (3D) crossbar resistive random access memory (RRAM) is one of the major focus of the new age technologies. To compete with the ultra-high density NAND and NOR memories, understanding of reliability mechanisms and scaling potential of 3D RRAM crossbar array is needed. Thermal crosstalk is one of the most critical effects that should be considered in 3D crossbar array application. The Joule heat generated inside the RRAM device will determine the switching behavior itself, and for dense memory arrays, the temperature surrounding may lead to a consequent resistance degradation of neighboring devices. In this work, thermal crosstalk effect and scaling potential under thermal effect in 3D RRAM crossbar array are systematically investigated. It is revealed that the reset process is dominated by transient thermal effect in 3D RRAM array. More importantly, thermal crosstalk phenomena could deteriorate device retention performance and even lead to data storage state failure from LRS (low resistance state) to HRS (high resistance state) of the disturbed RRAM cell. In addition, the resistance state degradation will be more serious with continuously scaling down the feature size. Possible methods for alleviating thermal crosstalk effect while further advancing the scaling potential are also provided and verified by numerical simulation. PMID:26310537

  7. Thermal crosstalk in 3-dimensional RRAM crossbar array.

    PubMed

    Sun, Pengxiao; Lu, Nianduan; Li, Ling; Li, Yingtao; Wang, Hong; Lv, Hangbing; Liu, Qi; Long, Shibing; Liu, Su; Liu, Ming

    2015-08-27

    High density 3-dimensional (3D) crossbar resistive random access memory (RRAM) is one of the major focus of the new age technologies. To compete with the ultra-high density NAND and NOR memories, understanding of reliability mechanisms and scaling potential of 3D RRAM crossbar array is needed. Thermal crosstalk is one of the most critical effects that should be considered in 3D crossbar array application. The Joule heat generated inside the RRAM device will determine the switching behavior itself, and for dense memory arrays, the temperature surrounding may lead to a consequent resistance degradation of neighboring devices. In this work, thermal crosstalk effect and scaling potential under thermal effect in 3D RRAM crossbar array are systematically investigated. It is revealed that the reset process is dominated by transient thermal effect in 3D RRAM array. More importantly, thermal crosstalk phenomena could deteriorate device retention performance and even lead to data storage state failure from LRS (low resistance state) to HRS (high resistance state) of the disturbed RRAM cell. In addition, the resistance state degradation will be more serious with continuously scaling down the feature size. Possible methods for alleviating thermal crosstalk effect while further advancing the scaling potential are also provided and verified by numerical simulation.

  8. Thermal crosstalk in 3-dimensional RRAM crossbar array

    PubMed Central

    Sun, Pengxiao; Lu, Nianduan; Li, Ling; Li, Yingtao; Wang, Hong; Lv, Hangbing; Liu, Qi; Long, Shibing; Liu, Su; Liu, Ming

    2015-01-01

    High density 3-dimensional (3D) crossbar resistive random access memory (RRAM) is one of the major focus of the new age technologies. To compete with the ultra-high density NAND and NOR memories, understanding of reliability mechanisms and scaling potential of 3D RRAM crossbar array is needed. Thermal crosstalk is one of the most critical effects that should be considered in 3D crossbar array application. The Joule heat generated inside the RRAM device will determine the switching behavior itself, and for dense memory arrays, the temperature surrounding may lead to a consequent resistance degradation of neighboring devices. In this work, thermal crosstalk effect and scaling potential under thermal effect in 3D RRAM crossbar array are systematically investigated. It is revealed that the reset process is dominated by transient thermal effect in 3D RRAM array. More importantly, thermal crosstalk phenomena could deteriorate device retention performance and even lead to data storage state failure from LRS (low resistance state) to HRS (high resistance state) of the disturbed RRAM cell. In addition, the resistance state degradation will be more serious with continuously scaling down the feature size. Possible methods for alleviating thermal crosstalk effect while further advancing the scaling potential are also provided and verified by numerical simulation. PMID:26310537

  9. Hybrid Flexible Resistive Random Access Memory-Gated Transistor for Novel Nonvolatile Data Storage.

    PubMed

    Han, Su-Ting; Zhou, Ye; Chen, Bo; Wang, Chundong; Zhou, Li; Yan, Yan; Zhuang, Jiaqing; Sun, Qijun; Zhang, Hua; Roy, V A L

    2016-01-20

    Here, a single-device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch gate for field effect transistor (FET) on a flexible substrate. A high performance flexible RRAM with a three-layered structure is fabricated by utilizing solution-processed MoS2 nanosheets sandwiched between poly(methyl methacrylate) polymer layers. Gate coupling with the pentacene-based transistor can be controlled by the RRAM memory state to produce a nonprogrammed state (inactive) and a programmed state (active) with a well-defined memory window. Compared to the reference flash memory device based on the MoS2 floating gate, the hybrid device presents robust access speed and retention ability. Furthermore, the hybrid RRAM-gated FET is used to build an integrated logic circuit and a wide logic window in inverter logic is achieved. The controllable, well-defined memory window, long retention time, and fast access speed of this novel hybrid device may open up new possibilities of realizing fully functional nonvolatile memory for high-performance flexible electronics.

  10. Hybrid Flexible Resistive Random Access Memory-Gated Transistor for Novel Nonvolatile Data Storage.

    PubMed

    Han, Su-Ting; Zhou, Ye; Chen, Bo; Wang, Chundong; Zhou, Li; Yan, Yan; Zhuang, Jiaqing; Sun, Qijun; Zhang, Hua; Roy, V A L

    2016-01-20

    Here, a single-device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch gate for field effect transistor (FET) on a flexible substrate. A high performance flexible RRAM with a three-layered structure is fabricated by utilizing solution-processed MoS2 nanosheets sandwiched between poly(methyl methacrylate) polymer layers. Gate coupling with the pentacene-based transistor can be controlled by the RRAM memory state to produce a nonprogrammed state (inactive) and a programmed state (active) with a well-defined memory window. Compared to the reference flash memory device based on the MoS2 floating gate, the hybrid device presents robust access speed and retention ability. Furthermore, the hybrid RRAM-gated FET is used to build an integrated logic circuit and a wide logic window in inverter logic is achieved. The controllable, well-defined memory window, long retention time, and fast access speed of this novel hybrid device may open up new possibilities of realizing fully functional nonvolatile memory for high-performance flexible electronics. PMID:26578160

  11. Effects of erbium doping of indium tin oxide electrode in resistive random access memory

    NASA Astrophysics Data System (ADS)

    Chen, Po-Hsun; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Pan, Chih-Hung; Lin, Chih-Yang; Jin, Fu-Yuan; Chen, Min-Chen; Huang, Hui-Chun; Lo, Ikai; Zheng, Jin-Cheng; Sze, Simon M.

    2016-03-01

    Identical insulators and bottom electrodes were fabricated and capped by an indium tin oxide (ITO) film, either undoped or doped with erbium (Er), as a top electrode. This distinctive top electrode dramatically altered the resistive random access memory (RRAM) characteristics, for example, lowering the operation current and enlarging the memory window. In addition, the RESET voltage increased, whereas the SET voltage remained almost the same. A conduction model of Er-doped ITO is proposed through current-voltage (I-V) measurement and current fitting to explain the resistance switching mechanism of Er-doped ITO RRAM and is confirmed by material analysis and reliability tests.

  12. Single-crystalline CuO nanowires for resistive random access memory applications

    SciTech Connect

    Hong, Yi-Siang; Chen, Jui-Yuan; Huang, Chun-Wei; Chiu, Chung-Hua; Huang, Yu-Ting; Huang, Ting Kai; He, Ruo Shiuan; Wu, Wen-Wei

    2015-04-27

    Recently, the mechanism of resistive random access memory (RRAM) has been partly clarified and determined to be controlled by the forming and erasing of conducting filaments (CF). However, the size of the CF may restrict the application and development as devices are scaled down. In this work, we synthesized CuO nanowires (NW) (∼150 nm in diameter) to fabricate a CuO NW RRAM nanodevice that was much smaller than the filament (∼2 μm) observed in a bulk CuO RRAM device in a previous study. HRTEM indicated that the Cu{sub 2}O phase was generated after operation, which demonstrated that the filament could be minimize to as small as 3.8 nm when the device is scaled down. In addition, energy dispersive spectroscopy (EDS) and electron energy loss spectroscopy (EELS) show the resistive switching of the dielectric layer resulted from the aggregated oxygen vacancies, which also match with the I-V fitting results. Those results not only verify the switching mechanism of CuO RRAM but also show RRAM has the potential to shrink in size, which will be beneficial to the practical application of RRAM devices.

  13. Physical and chemical mechanisms in oxide-based resistance random access memory.

    PubMed

    Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Zhang, Rui; Hung, Ya-Chi; Syu, Yong-En; Chang, Yao-Feng; Chen, Min-Chen; Chu, Tian-Jian; Chen, Hsin-Lu; Pan, Chih-Hung; Shih, Chih-Cheng; Zheng, Jin-Cheng; Sze, Simon M

    2015-01-01

    In this review, we provide an overview of our work in resistive switching mechanisms on oxide-based resistance random access memory (RRAM) devices. Based on the investigation of physical and chemical mechanisms, we focus on its materials, device structures, and treatment methods so as to provide an in-depth perspective of state-of-the-art oxide-based RRAM. The critical voltage and constant reaction energy properties were found, which can be used to prospectively modulate voltage and operation time to control RRAM device working performance and forecast material composition. The quantized switching phenomena in RRAM devices were demonstrated at ultra-cryogenic temperature (4K), which is attributed to the atomic-level reaction in metallic filament. In the aspect of chemical mechanisms, we use the Coulomb Faraday theorem to investigate the chemical reaction equations of RRAM for the first time. We can clearly observe that the first-order reaction series is the basis for chemical reaction during reset process in the study. Furthermore, the activation energy of chemical reactions can be extracted by changing temperature during the reset process, from which the oxygen ion reaction process can be found in the RRAM device. As for its materials, silicon oxide is compatible to semiconductor fabrication lines. It is especially promising for the silicon oxide-doped metal technology to be introduced into the industry. Based on that, double-ended graphene oxide-doped silicon oxide based via-structure RRAM with filament self-aligning formation, and self-current limiting operation ability is demonstrated. The outstanding device characteristics are attributed to the oxidation and reduction of graphene oxide flakes formed during the sputter process. Besides, we have also adopted a new concept of supercritical CO2 fluid treatment to efficiently reduce the operation current of RRAM devices for portable electronic applications.

  14. Materials selection for oxide-based resistive random access memories

    SciTech Connect

    Guo, Yuzheng; Robertson, John

    2014-12-01

    The energies of atomic processes in resistive random access memories (RRAMs) are calculated for four typical oxides, HfO{sub 2}, TiO{sub 2}, Ta{sub 2}O{sub 5}, and Al{sub 2}O{sub 3}, to define a materials selection process. O vacancies have the lowest defect formation energy in the O-poor limit and dominate the processes. A band diagram defines the operating Fermi energy and O chemical potential range. It is shown how the scavenger metal can be used to vary the O vacancy formation energy, via controlling the O chemical potential, and the mean Fermi energy. The high endurance of Ta{sub 2}O{sub 5} RRAM is related to its more stable amorphous phase and the adaptive lattice rearrangements of its O vacancy.

  15. Chemical insight into origin of forming-free resistive random-access memory devices

    NASA Astrophysics Data System (ADS)

    Wu, X.; Fang, Z.; Li, K.; Bosman, M.; Raghavan, N.; Li, X.; Yu, H. Y.; Singh, N.; Lo, G. Q.; Zhang, X. X.; Pey, K. L.

    2011-09-01

    We demonstrate the realization of a forming-step free resistive random access memory (RRAM) device using a HfOx/TiOx/HfOx/TiOx multilayer structure, as a replacement for the conventional HfOx-based single layer structure. High-resolution transmission electron microscopy (HRTEM), along with electron energy loss spectroscopy (EELS) analysis has been carried out to identify the distribution and the role played by Ti in the RRAM stack. Our results show that Ti out-diffusion into the HfOx layer is the chemical cause of forming-free behavior. Moreover, the capability of Ti to change its ionic state in HfOx eases the reduction-oxidation (redox) reaction, thus lead to the RRAM devices performance improvements.

  16. Illumination Effect on Bipolar Switching Properties of Gd:SiO2 RRAM Devices Using Transparent Indium Tin Oxide Electrode.

    PubMed

    Chen, Kai-Huang; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Liang, Shu-Ping; Young, Tai-Fa; Syu, Yong-En; Sze, Simon M

    2016-12-01

    To discuss the optoelectronic effect on resistive random access memory (RRAM) devices, the bipolar switching properties and electron-hole pair generation behavior in the transparent indium tin oxide (ITO) electrode of Gd:SiO2 thin films under the ultraviolet (λ = 400 nm) and red-light (λ = 770 nm) illumination for high resistance state (HRS)/low resistance state (LRS) was observed and investigated. In dark environment, the Gd:SiO2 RRAM devices exhibited the ohmic conduction mechanism for LRS, exhibited the Schottky emission conduction and Poole-Frankel conduction mechanism for HRS. For light illumination effect, the operation current of the Gd:SiO2 RRAM devices for HRS/LRS was slightly increased. Finally, the electron-hole pair transport mechanism, switching conduction diagram, and energy band of the RRAM devices will be clearly demonstrated and explained. PMID:27117634

  17. Illumination Effect on Bipolar Switching Properties of Gd:SiO2 RRAM Devices Using Transparent Indium Tin Oxide Electrode

    NASA Astrophysics Data System (ADS)

    Chen, Kai-Huang; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Liang, Shu-Ping; Young, Tai-Fa; Syu, Yong-En; Sze, Simon M.

    2016-04-01

    To discuss the optoelectronic effect on resistive random access memory (RRAM) devices, the bipolar switching properties and electron-hole pair generation behavior in the transparent indium tin oxide (ITO) electrode of Gd:SiO2 thin films under the ultraviolet ( λ = 400 nm) and red-light ( λ = 770 nm) illumination for high resistance state (HRS)/low resistance state (LRS) was observed and investigated. In dark environment, the Gd:SiO2 RRAM devices exhibited the ohmic conduction mechanism for LRS, exhibited the Schottky emission conduction and Poole-Frankel conduction mechanism for HRS. For light illumination effect, the operation current of the Gd:SiO2 RRAM devices for HRS/LRS was slightly increased. Finally, the electron-hole pair transport mechanism, switching conduction diagram, and energy band of the RRAM devices will be clearly demonstrated and explained.

  18. Improvement of Bipolar Switching Properties of Gd:SiOx RRAM Devices on Indium Tin Oxide Electrode by Low-Temperature Supercritical CO2 Treatment

    NASA Astrophysics Data System (ADS)

    Chen, Kai-Huang; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Liang, Shu-Ping; Young, Tai-Fa; Syu, Yong-En; Sze, Simon M.

    2016-02-01

    Bipolar switching resistance behaviors of the Gd:SiO2 resistive random access memory (RRAM) devices on indium tin oxide electrode by the low-temperature supercritical CO2-treated technology were investigated. For physical and electrical measurement results obtained, the improvement on oxygen qualities, properties of indium tin oxide electrode, and operation current of the Gd:SiO2 RRAM devices were also observed. In addition, the initial metallic filament-forming model analyses and conduction transferred mechanism in switching resistance properties of the RRAM devices were verified and explained. Finally, the electrical reliability and retention properties of the Gd:SiO2 RRAM devices for low-resistance state (LRS)/high-resistance state (HRS) in different switching cycles were also measured for applications in nonvolatile random memory devices.

  19. Improvement of Bipolar Switching Properties of Gd:SiOx RRAM Devices on Indium Tin Oxide Electrode by Low-Temperature Supercritical CO2 Treatment.

    PubMed

    Chen, Kai-Huang; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Liang, Shu-Ping; Young, Tai-Fa; Syu, Yong-En; Sze, Simon M

    2016-12-01

    Bipolar switching resistance behaviors of the Gd:SiO2 resistive random access memory (RRAM) devices on indium tin oxide electrode by the low-temperature supercritical CO2-treated technology were investigated. For physical and electrical measurement results obtained, the improvement on oxygen qualities, properties of indium tin oxide electrode, and operation current of the Gd:SiO2 RRAM devices were also observed. In addition, the initial metallic filament-forming model analyses and conduction transferred mechanism in switching resistance properties of the RRAM devices were verified and explained. Finally, the electrical reliability and retention properties of the Gd:SiO2 RRAM devices for low-resistance state (LRS)/high-resistance state (HRS) in different switching cycles were also measured for applications in nonvolatile random memory devices.

  20. Engineering the switching dynamics of TiOx-based RRAM with Al doping

    NASA Astrophysics Data System (ADS)

    Trapatseli, Maria; Khiat, Ali; Cortese, Simone; Serb, Alexantrou; Carta, Daniela; Prodromakis, Themistoklis

    2016-07-01

    Titanium oxide (TiOx) has attracted a lot of attention as an active material for resistive random access memory (RRAM), due to its versatility and variety of possible crystal phases. Although existing RRAM materials have demonstrated impressive characteristics, like ultra-fast switching and high cycling endurance, this technology still encounters challenges like low yields, large variability of switching characteristics, and ultimately device failure. Electroforming has been often considered responsible for introducing irreversible damage to devices, with high switching voltages contributing to device degradation. In this paper, we have employed Al doping for tuning the resistive switching characteristics of titanium oxide RRAM. The resistive switching threshold voltages of undoped and Al-doped TiOx thin films were first assessed by conductive atomic force microscopy. The thin films were then transferred in RRAM devices and tested with voltage pulse sweeping, demonstrating that the Al-doped devices could on average form at lower potentials compared to the undoped ones and could support both analog and binary switching at potentials as low as 0.9 V. This work demonstrates a potential pathway for implementing low-power RRAM systems.

  1. Resistance switching behavior of ZnO resistive random access memory with a reduced graphene oxide capping layer

    NASA Astrophysics Data System (ADS)

    Lin, Cheng-Li; Chang, Wei-Yi; Huang, Yen-Lun; Juan, Pi-Chun; Wang, Tse-Wen; Hung, Ke-Yu; Hsieh, Cheng-Yu; Kang, Tsung-Kuei; Shi, Jen-Bin

    2015-04-01

    In this work, we investigate the characteristics of ZnO resistive random access memory (RRAM) with a reduced graphene oxide (rGO) capping layer and the polarity effect of the SET/RESET bias on the RRAM. The rGO film insertion enhances the stability of the current-voltage (I-V) switching curve and the superior resistance ratio (˜105) of high-resistance state (HRS) to low-resistance state (LRS). Using the appropriate polarity of the SET/RESET bias applied to the rGO-capped ZnO RRAM enables the oxygen ions to move mainly at the interface of the rGO and ZnO films, resulting in the best performance. Presumably, the rGO film acts as an oxygen reservoir and enhances the easy in and out motion of the oxygen ions from the rGO film. The rGO film also prevents the interaction of oxygen ions and the Al electrode, resulting in excellent performance. In a pulse endurance test, the rGO-capped ZnO RRAM reveals superior endurance of up to 108 cycles over that of the ZnO RRAM without rGO insertion (106 cycles).

  2. Performance improvement of gadolinium oxide resistive random access memory treated by hydrogen plasma immersion ion implantation

    SciTech Connect

    Wang, Jer-Chyi Hsu, Chih-Hsien; Ye, Yu-Ren; Ai, Chi-Fong; Tsai, Wen-Fa

    2014-03-15

    Characteristics improvement of gadolinium oxide (Gd{sub x}O{sub y}) resistive random access memories (RRAMs) treated by hydrogen plasma immersion ion implantation (PIII) was investigated. With the hydrogen PIII treatment, the Gd{sub x}O{sub y} RRAMs exhibited low set/reset voltages and a high resistance ratio, which were attributed to the enhanced movement of oxygen ions within the Gd{sub x}O{sub y} films and the increased Schottky barrier height at Pt/Gd{sub x}O{sub y} interface, respectively. The resistive switching mechanism of Gd{sub x}O{sub y} RRAMs was dominated by Schottky emission, as proved by the area dependence of the resistance in the low resistance state. After the hydrogen PIII treatment, a retention time of more than 10{sup 4} s was achieved at an elevated measurement temperature. In addition, a stable cycling endurance with the resistance ratio of more than three orders of magnitude of the Gd{sub x}O{sub y} RRAMs can be obtained.

  3. Space electric field concentrated effect for Zr:SiO2 RRAM devices using porous SiO2 buffer layer

    PubMed Central

    2013-01-01

    To improve the operation current lowing of the Zr:SiO2 RRAM devices, a space electric field concentrated effect established by the porous SiO2 buffer layer was investigated and found in this study. The resistive switching properties of the low-resistance state (LRS) and high-resistance state (HRS) in resistive random access memory (RRAM) devices for the single-layer Zr:SiO2 and bilayer Zr:SiO2/porous SiO2 thin films were analyzed and discussed. In addition, the original space charge limited current (SCLC) conduction mechanism in LRS and HRS of the RRAM devices using bilayer Zr:SiO2/porous SiO2 thin films was found. Finally, a space electric field concentrated effect in the bilayer Zr:SiO2/porous SiO2 RRAM devices was also explained and verified by the COMSOL Multiphysics simulation model. PMID:24330524

  4. Mechanism of power consumption inhibitive multi-layer Zn:SiO2/SiO2 structure resistance random access memory

    NASA Astrophysics Data System (ADS)

    Zhang, Rui; Tsai, Tsung-Ming; Chang, Ting-Chang; Chang, Kuan-Chang; Chen, Kai-Huang; Lou, Jen-Chung; Young, Tai-Fa; Chen, Jung-Hui; Huang, Syuan-Yong; Chen, Min-Chen; Shih, Chih-Cheng; Chen, Hsin-Lu; Pan, Jhih-Hong; Tung, Cheng-Wei; Syu, Yong-En; Sze, Simon M.

    2013-12-01

    In this paper, multi-layer Zn:SiO2/SiO2 structure is introduced to reduce the operation power consumption of resistive random access memory (RRAM) device by modifying the filament formation process. And the configuration of multi-layer Zn:SiO2/SiO2 structure is confirmed and demonstrated by auger electron spectrum. Material analysis together with conduction current fitting is applied to qualitatively evaluate the carrier conduction mechanism on both low resistance state and high resistance state. Finally, single layer and multilayer conduction models are proposed, respectively, to clarify the corresponding conduction characteristics of two types of RRAM devices.

  5. Atomic memory access hardware implementations

    DOEpatents

    Ahn, Jung Ho; Erez, Mattan; Dally, William J

    2015-02-17

    Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

  6. Analysis on the Filament Structure Evolution in Reset Transition of Cu/HfO2/Pt RRAM Device.

    PubMed

    Zhang, Meiyun; Long, Shibing; Li, Yang; Liu, Qi; Lv, Hangbing; Miranda, Enrique; Suñé, Jordi; Liu, Ming

    2016-12-01

    The resistive switching (RS) process of resistive random access memory (RRAM) is dynamically correlated with the evolution process of conductive path or conductive filament (CF) during its breakdown (rupture) and recovery (reformation). In this study, a statistical evaluation method is developed to analyze the filament structure evolution process in the reset operation of Cu/HfO2/Pt RRAM device. This method is based on a specific functional relationship between the Weibull slopes of reset parameters' distributions and the CF resistance (R on). The CF of the Cu/HfO2/Pt device is demonstrated to be ruptured abruptly, and the CF structure of the device has completely degraded in the reset point. Since no intermediate states are generated in the abrupt reset process, it is quite favorable for the reliable and stable one-bit operation in RRAM device. Finally, on the basis of the cell-based analytical thermal dissolution model, a Monte Carlo (MC) simulation is implemented to further verify the experimental results. This work provides inspiration for RRAM reliability and performance design to put RRAM into practical application.

  7. Analysis on the Filament Structure Evolution in Reset Transition of Cu/HfO2/Pt RRAM Device

    NASA Astrophysics Data System (ADS)

    Zhang, Meiyun; Long, Shibing; Li, Yang; Liu, Qi; Lv, Hangbing; Miranda, Enrique; Suñé, Jordi; Liu, Ming

    2016-05-01

    The resistive switching (RS) process of resistive random access memory (RRAM) is dynamically correlated with the evolution process of conductive path or conductive filament (CF) during its breakdown (rupture) and recovery (reformation). In this study, a statistical evaluation method is developed to analyze the filament structure evolution process in the reset operation of Cu/HfO2/Pt RRAM device. This method is based on a specific functional relationship between the Weibull slopes of reset parameters' distributions and the CF resistance ( R on). The CF of the Cu/HfO2/Pt device is demonstrated to be ruptured abruptly, and the CF structure of the device has completely degraded in the reset point. Since no intermediate states are generated in the abrupt reset process, it is quite favorable for the reliable and stable one-bit operation in RRAM device. Finally, on the basis of the cell-based analytical thermal dissolution model, a Monte Carlo (MC) simulation is implemented to further verify the experimental results. This work provides inspiration for RRAM reliability and performance design to put RRAM into practical application.

  8. Analysis on the Filament Structure Evolution in Reset Transition of Cu/HfO2/Pt RRAM Device.

    PubMed

    Zhang, Meiyun; Long, Shibing; Li, Yang; Liu, Qi; Lv, Hangbing; Miranda, Enrique; Suñé, Jordi; Liu, Ming

    2016-12-01

    The resistive switching (RS) process of resistive random access memory (RRAM) is dynamically correlated with the evolution process of conductive path or conductive filament (CF) during its breakdown (rupture) and recovery (reformation). In this study, a statistical evaluation method is developed to analyze the filament structure evolution process in the reset operation of Cu/HfO2/Pt RRAM device. This method is based on a specific functional relationship between the Weibull slopes of reset parameters' distributions and the CF resistance (R on). The CF of the Cu/HfO2/Pt device is demonstrated to be ruptured abruptly, and the CF structure of the device has completely degraded in the reset point. Since no intermediate states are generated in the abrupt reset process, it is quite favorable for the reliable and stable one-bit operation in RRAM device. Finally, on the basis of the cell-based analytical thermal dissolution model, a Monte Carlo (MC) simulation is implemented to further verify the experimental results. This work provides inspiration for RRAM reliability and performance design to put RRAM into practical application. PMID:27389343

  9. Is random access memory random?

    NASA Technical Reports Server (NTRS)

    Denning, P. J.

    1986-01-01

    Most software is contructed on the assumption that the programs and data are stored in random access memory (RAM). Physical limitations on the relative speeds of processor and memory elements lead to a variety of memory organizations that match processor addressing rate with memory service rate. These include interleaved and cached memory. A very high fraction of a processor's address requests can be satified from the cache without reference to the main memory. The cache requests information from main memory in blocks that can be transferred at the full memory speed. Programmers who organize algorithms for locality can realize the highest performance from these computers.

  10. Nonvolatile random access memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

    1994-01-01

    A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a 0 or 1 state. The element remains in the 0 or 1 state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.

  11. Remote direct memory access

    DOEpatents

    Archer, Charles J.; Blocksome, Michael A.

    2012-12-11

    Methods, parallel computers, and computer program products are disclosed for remote direct memory access. Embodiments include transmitting, from an origin DMA engine on an origin compute node to a plurality target DMA engines on target compute nodes, a request to send message, the request to send message specifying a data to be transferred from the origin DMA engine to data storage on each target compute node; receiving, by each target DMA engine on each target compute node, the request to send message; preparing, by each target DMA engine, to store data according to the data storage reference and the data length, including assigning a base storage address for the data storage reference; sending, by one or more of the target DMA engines, an acknowledgment message acknowledging that all the target DMA engines are prepared to receive a data transmission from the origin DMA engine; receiving, by the origin DMA engine, the acknowledgement message from the one or more of the target DMA engines; and transferring, by the origin DMA engine, data to data storage on each of the target compute nodes according to the data storage reference using a single direct put operation.

  12. Realization of a reversible switching in TaO{sub 2} polymorphs via Peierls distortion for resistance random access memory

    SciTech Connect

    Zhu, Linggang; Sun, Zhimei; Zhou, Jian; Guo, Zhonglu

    2015-03-02

    Transition-metal-oxide based resistance random access memory (RRAM) is a promising candidate for next-generation universal non-volatile memories. Searching and designing appropriate materials used in the memories becomes an urgent task. Here, a structure with the TaO{sub 2} formula was predicted using evolutionary algorithms in combination with first-principles calculations. This triclinic structure (T-TaO{sub 2}) is both energetically and dynamically more favorable than the commonly believed rutile structure (R-TaO{sub 2}). The metal-insulator transition (MIT) between metallic R-TaO{sub 2} and T-TaO{sub 2} (band gap: 1.0 eV) is via a Peierls distortion, which makes TaO{sub 2} a potential candidate for RRAM. The energy barrier for the reversible phase transition is 0.19 eV/atom and 0.23 eV/atom, respectively, suggesting low power consumption for the resistance switch. The present findings about the MIT as the resistance-switch mechanism in Ta-O system will stimulate experimental work to fabricate tantalum oxides based RRAM.

  13. Garnet Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.

    1995-01-01

    Random-access memory (RAM) devices of proposed type exploit magneto-optical properties of magnetic garnets exhibiting perpendicular anisotropy. Magnetic writing and optical readout used. Provides nonvolatile storage and resists damage by ionizing radiation. Because of basic architecture and pinout requirements, most likely useful as small-capacity memory devices.

  14. Plated wire random access memories

    NASA Technical Reports Server (NTRS)

    Gouldin, L. D.

    1975-01-01

    A program was conducted to construct 4096-work by 18-bit random access, NDRO-plated wire memory units. The memory units were subjected to comprehensive functional and environmental tests at the end-item level to verify comformance with the specified requirements. A technical description of the unit is given, along with acceptance test data sheets.

  15. Memory availability and referential access

    PubMed Central

    Johns, Clinton L.; Gordon, Peter C.; Long, Debra L.; Swaab, Tamara Y.

    2013-01-01

    Most theories of coreference specify linguistic factors that modulate antecedent accessibility in memory; however, whether non-linguistic factors also affect coreferential access is unknown. Here we examined the impact of a non-linguistic generation task (letter transposition) on the repeated-name penalty, a processing difficulty observed when coreferential repeated names refer to syntactically prominent (and thus more accessible) antecedents. In Experiment 1, generation improved online (event-related potentials) and offline (recognition memory) accessibility of names in word lists. In Experiment 2, we manipulated generation and syntactic prominence of antecedent names in sentences; both improved online and offline accessibility, but only syntactic prominence elicited a repeated-name penalty. Our results have three important implications: first, the form of a referential expression interacts with an antecedent’s status in the discourse model during coreference; second, availability in memory and referential accessibility are separable; and finally, theories of coreference must better integrate known properties of the human memory system. PMID:24443621

  16. Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition

    PubMed Central

    Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

    2016-01-01

    With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption. PMID:27312225

  17. Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition.

    PubMed

    Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

    2016-01-01

    With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption. PMID:27312225

  18. Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

    2016-06-01

    With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption.

  19. Characteristics of HfO2/Hf-based bipolar resistive memories

    NASA Astrophysics Data System (ADS)

    Jinshun, Bi; Zhengsheng, Han

    2015-06-01

    Nano-scale Hf/HfO2-based resistive random-access-memory (RRAM) devices were fabricated. The cross-over between top and bottom electrodes of RRAM forms the metal-insulator-metal sandwich structure. The electrical responses of RRAM are studied in detail, including forming process, SET process and RESET process. The correlations between SET voltage and RESET voltage, high resistance state and low resistance state are discussed. The electrical characteristics of RRAM are in a strong relationship with the compliance current in the SET process. The conduction mechanism of nano-scale Hf/HfO2-based RRAM can be explained by the quantum point contact model. Project supported by the National Natural Science Foundation of China (Nos. 11179003, 61176095).

  20. Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device.

    PubMed

    Park, Sangsu; Noh, Jinwoo; Choo, Myung-Lae; Sheri, Ahmad Muqeem; Chang, Man; Kim, Young-Bae; Kim, Chang Jung; Jeon, Moongu; Lee, Byung-Geun; Lee, Byoung Hun; Hwang, Hyunsang

    2013-09-27

    Efforts to develop scalable learning algorithms for implementation of networks of spiking neurons in silicon have been hindered by the considerable footprints of learning circuits, which grow as the number of synapses increases. Recent developments in nanotechnologies provide an extremely compact device with low-power consumption.In particular, nanoscale resistive switching devices (resistive random-access memory (RRAM)) are regarded as a promising solution for implementation of biological synapses due to their nanoscale dimensions, capacity to store multiple bits and the low energy required to operate distinct states. In this paper, we report the fabrication, modeling and implementation of nanoscale RRAM with multi-level storage capability for an electronic synapse device. In addition, we first experimentally demonstrate the learning capabilities and predictable performance by a neuromorphic circuit composed of a nanoscale 1 kbit RRAM cross-point array of synapses and complementary metal-oxide-semiconductor neuron circuits. These developments open up possibilities for the development of ubiquitous ultra-dense, ultra-low-power cognitive computers.

  1. Adjustable built-in resistor on oxygen-vacancy-rich electrode-capped resistance random access memory

    NASA Astrophysics Data System (ADS)

    Pan, Chih-Hung; Chang, Ting-Chang; Tsai, Tsung-Ming; Chang, Kuan-Chang; Chu, Tian-Jian; Chen, Po-Hsun; Chen, Min-Chen; Sze, Simon M.

    2016-10-01

    In this study, an adjustable built-in resistor was observed on an indium-tin oxide (ITO)-capped resistance random access memory (RRAM) device, which has the potential to reduce operating power. Quite notably, the high-resistance state (HRS) current of the device decreased with decreasing current compliance, and a special situation, that is, a gradual change in current always appears and climbs slowly to reach the compliance current in the set process even when the compliance current decreases, was observed. Owing to this observed phenomenon, the device is regarded to be equipped with an adjustable built-in resistor, which has the potential for low-power device application.

  2. Self-assembled tin dioxide for forming-free resistive random-access memory application

    NASA Astrophysics Data System (ADS)

    Hong, Ying-Jhan; Wang, Tsang-Hsuan; Wei, Shih-Yuan; Chang, Pin; Yew, Tri-Rung

    2016-06-01

    A novel resistive switching structure, tin-doped indium oxide (ITO)/SnO2- x (defined as SnO2 with oxygen vacancies)/SnS was demonstrated with a set voltage of 0.38 V, a reset voltage of -0.15 V, a ratio of high resistance to low resistance of 544, and forming-free and nonlinear current-voltage (I-V) characteristics. The interface of the ITO and the self-assembled SnO2- x contributed to the resistive switching behavior. This device showed great potential for resistive random access memory (RRAM) application and solving the sneak path problem in cross-bar memory arrays. Furthermore, a nanostructured resistive switching device was demonstrated successfully.

  3. Flexible Nonvolatile Polymer Memory Array on Plastic Substrate via Initiated Chemical Vapor Deposition.

    PubMed

    Jang, Byung Chul; Seong, Hyejeong; Kim, Sung Kyu; Kim, Jong Yun; Koo, Beom Jun; Choi, Junhwan; Yang, Sang Yoon; Im, Sung Gap; Choi, Sung-Yool

    2016-05-25

    Resistive random access memory based on polymer thin films has been developed as a promising flexible nonvolatile memory for flexible electronic systems. Memory plays an important role in all modern electronic systems for data storage, processing, and communication; thus, the development of flexible memory is essential for the realization of flexible electronics. However, the existing solution-processed, polymer-based RRAMs have exhibited serious drawbacks in terms of the uniformity, electrical stability, and long-term stability of the polymer thin films. Here, we present poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3)-based RRAM arrays fabricated via the solvent-free technique called initiated chemical vapor deposition (iCVD) process for flexible memory application. Because of the outstanding chemical stability of pV3D3 films, the pV3D3-RRAM arrays can be fabricated by a conventional photolithography process. The pV3D3-RRAM on flexible substrates showed unipolar resistive switching memory with an on/off ratio of over 10(7), stable retention time for 10(5) s, excellent cycling endurance over 10(5) cycles, and robust immunity to mechanical stress. In addition, pV3D3-RRAMs showed good uniformity in terms of device-to-device distribution. The pV3D3-RRAM will pave the way for development of next-generation flexible nonvolatile memory devices. PMID:27142537

  4. Disturbance characteristics of half-selected cells in a cross-point resistive switching memory array

    NASA Astrophysics Data System (ADS)

    Chen, Zhe; Li, Haitong; Chen, Hong-Yu; Chen, Bing; Liu, Rui; Huang, Peng; Zhang, Feifei; Jiang, Zizhen; Ye, Hongfei; Gao, Bin; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng; Wong, H.-S. Philip; Yu, Shimeng

    2016-05-01

    Disturbance characteristics of cross-point resistive random access memory (RRAM) arrays are comprehensively studied in this paper. An analytical model is developed to quantify the number of pulses (#Pulse) the cell can bear before disturbance occurs under various sub-switching voltage stresses based on physical understanding. An evaluation methodology is proposed to assess the disturb behavior of half-selected (HS) cells in cross-point RRAM arrays by combining the analytical model and SPICE simulation. The characteristics of cross-point RRAM arrays such as energy consumption, reliable operating cycles and total error bits are evaluated by the methodology. A possible solution to mitigate disturbance is proposed.

  5. Multi-step resistive switching behavior of Li-doped ZnO resistance random access memory device controlled by compliance current

    NASA Astrophysics Data System (ADS)

    Lin, Chun-Cheng; Tang, Jian-Fu; Su, Hsiu-Hsien; Hong, Cheng-Shong; Huang, Chih-Yu; Chu, Sheng-Yuan

    2016-06-01

    The multi-step resistive switching (RS) behavior of a unipolar Pt/Li0.06Zn0.94O/Pt resistive random access memory (RRAM) device is investigated. It is found that the RRAM device exhibits normal, 2-, 3-, and 4-step RESET behaviors under different compliance currents. The transport mechanism within the device is investigated by means of current-voltage curves, in-situ transmission electron microscopy, and electrochemical impedance spectroscopy. It is shown that the ion transport mechanism is dominated by Ohmic behavior under low electric fields and the Poole-Frenkel emission effect (normal RS behavior) or Li+ ion diffusion (2-, 3-, and 4-step RESET behaviors) under high electric fields.

  6. Self-compliance Pt/HfO2/Ti/Si one-diode-one-resistor resistive random access memory device and its low temperature characteristics

    NASA Astrophysics Data System (ADS)

    Lu, Chao; Yu, Jue; Chi, Xiao-Wei; Lin, Guang-Yang; Lan, Xiao-Ling; Huang, Wei; Wang, Jian-Yuan; Xu, Jian-Fang; Wang, Chen; Li, Cheng; Chen, Song-Yan; Liu, Chunli; Lai, Hong-Kai

    2016-04-01

    A bipolar one-diode-one-resistor (1D1R) device with a Pt/HfO2/Ti/n-Si(001) structure was demonstrated. The 1D1R resistive random access memory (RRAM) device consists of a Ti/n-Si(001) diode and a Pt/HfO2/Ti resistive switching cell. By using the Ti layer as the shared electrode for both the diode and the resistive switching cell, the 1D1R device exhibits the property of stable self-compliance and the characteristic of robust resistive switching with high uniformity. The high/low resistance ratio reaches 103. The electrical RESET/SET curve does not deteriorate after 68 loops. Low-temperature studies show that the 1D1R RRAM device has a critical working temperature of 250 K, and at temperatures below 250 K, the device fails to switch its resistances.

  7. Investigation on the RESET switching mechanism of bipolar Cu/HfO2/Pt RRAM devices with a statistical methodology

    NASA Astrophysics Data System (ADS)

    Yang, Xiaoyi; Long, Shibing; Zhang, Kangwei; Liu, Xiaoyu; Wang, Guoming; Lian, Xiaojuan; Liu, Qi; Lv, Hangbing; Wang, Ming; Xie, Hongwei; Sun, Haitao; Sun, Pengxiao; Suñé, Jordi; Liu, Ming

    2013-06-01

    The RESET switching of bipolar Cu/HfO2/Pt resistance random access memory (RRAM) is investigated. With a statistical methodology, we systematically analyze the RESET voltage (VRESET) and RESET current (IRESET). VRESET shows a U-shape distribution as a function of RON according to the scatter plot of the raw experimental data. After data correction by a series resistance (RS), VRESET is nearly constant, while IRESET decreases linearly with RCF. These behaviours are consistent with the thermal dissolution model of RESET. Moreover, the IRESET and VRESET distributions are strongly affected by the RON distribution. Using a ‘resistance screening’ method, the IRESET and VRESET distributions are found to be compatible with the Weibull distribution model. The Weibull slopes of the VRESET and IRESET distributions are independent of RCF, indicating that the RESET point corresponds to the initial phase of conductive filament (CF) dissolution, according to our cell-based model for the unipolar RESET of RRAM devices. The scale factor of the VRESET distributions is roughly constant, while that of the IRESET distributions scale with 1/RCF. Accordingly, the RESET switching of the HfO2-based solid electrolyte memory is compatible with the thermal dissolution mechanism, improving our understanding on the physics of resistive switching of RRAM devices.

  8. Excellent nonlinearity of a selection device based on anti-series connected Zener diodes for ultrahigh-density bipolar RRAM arrays.

    PubMed

    Li, Yingtao; Li, Rongrong; Fu, Liping; Gao, Xiaoping; Wang, Yang; Tao, Chunlan

    2015-10-23

    A crossbar array is usually used for the high-density application of a resistive random access memory (RRAM) device. However, the cross-talk interference limits the increase in the integration density. In this paper, anti-series connected Zener diodes as a selection device are proposed for bipolar RRAM arrays. Simulation results show that, by using the anti-series connected Zener diodes as a selection device, the readout margin is sufficiently improved compared to that obtained without a selection device or with anti-parallel connected diodes as the selection device. The maximum size of the crossbar arrays with anti-series connected Zener diodes as a selection device over 1 TB is estimated by theoretical simulation. In addition, the feasibility of using the anti-series connected Zener diodes as a selection device for bipolar RRAM is demonstrated experimentally. These results indicate that anti-series connected Zener diodes as a selection device opens up great opportunities to realize ultrahigh-density bipolar RRAM arrays.

  9. Direct Observation of a Carbon Filament in Water-Resistant Organic Memory.

    PubMed

    Lee, Byung-Hyun; Bae, Hagyoul; Seong, Hyejeong; Lee, Dong-Il; Park, Hongkeun; Choi, Young Joo; Im, Sung-Gap; Kim, Sang Ouk; Choi, Yang-Kyu

    2015-07-28

    The memory for the Internet of Things (IoT) requires versatile characteristics such as flexibility, wearability, and stability in outdoor environments. Resistive random access memory (RRAM) to harness a simple structure and organic material with good flexibility can be an attractive candidate for IoT memory. However, its solution-oriented process and unclear switching mechanism are critical problems. Here we demonstrate iCVD polymer-intercalated RRAM (i-RRAM). i-RRAM exhibits robust flexibility and versatile wearability on any substrate. Stable operation of i-RRAM, even in water, is demonstrated, which is the first experimental presentation of water-resistant organic memory without any waterproof protection package. Moreover, the direct observation of a carbon filament is also reported for the first time using transmission electron microscopy, which puts an end to the controversy surrounding the switching mechanism. Therefore, reproducibility is feasible through comprehensive modeling. Furthermore, a carbon filament is superior to a metal filament in terms of the design window and selection of the electrode material. These results suggest an alternative to solve the critical issues of organic RRAM and an optimized memory type suitable for the IoT era.

  10. Direct Observation of a Carbon Filament in Water-Resistant Organic Memory.

    PubMed

    Lee, Byung-Hyun; Bae, Hagyoul; Seong, Hyejeong; Lee, Dong-Il; Park, Hongkeun; Choi, Young Joo; Im, Sung-Gap; Kim, Sang Ouk; Choi, Yang-Kyu

    2015-07-28

    The memory for the Internet of Things (IoT) requires versatile characteristics such as flexibility, wearability, and stability in outdoor environments. Resistive random access memory (RRAM) to harness a simple structure and organic material with good flexibility can be an attractive candidate for IoT memory. However, its solution-oriented process and unclear switching mechanism are critical problems. Here we demonstrate iCVD polymer-intercalated RRAM (i-RRAM). i-RRAM exhibits robust flexibility and versatile wearability on any substrate. Stable operation of i-RRAM, even in water, is demonstrated, which is the first experimental presentation of water-resistant organic memory without any waterproof protection package. Moreover, the direct observation of a carbon filament is also reported for the first time using transmission electron microscopy, which puts an end to the controversy surrounding the switching mechanism. Therefore, reproducibility is feasible through comprehensive modeling. Furthermore, a carbon filament is superior to a metal filament in terms of the design window and selection of the electrode material. These results suggest an alternative to solve the critical issues of organic RRAM and an optimized memory type suitable for the IoT era. PMID:26056735

  11. First-principles thermodynamics and defect kinetics guidelines for engineering a tailored RRAM device

    NASA Astrophysics Data System (ADS)

    Clima, Sergiu; Chen, Yang Yin; Chen, Chao Yang; Goux, Ludovic; Govoreanu, Bogdan; Degraeve, Robin; Fantini, Andrea; Jurczak, Malgorzata; Pourtois, Geoffrey

    2016-06-01

    Resistive Random Access Memories are among the most promising candidates for the next generation of non-volatile memory. Transition metal oxides such as HfOx and TaOx attracted a lot of attention due to their CMOS compatibility. Furthermore, these materials do not require the inclusion of extrinsic conducting defects since their operation is based on intrinsic ones (oxygen vacancies). Using Density Functional Theory, we evaluated the thermodynamics of the defects formation and the kinetics of diffusion of the conducting species active in transition metal oxide RRAM materials. The gained insights based on the thermodynamics in the Top Electrode, Insulating Matrix and Bottom Electrode and at the interfaces are used to design a proper defect reservoir, which is needed for a low-energy reliable switching device. The defect reservoir has also a direct impact on the retention of the Low Resistance State due to the resulting thermodynamic driving forces. The kinetics of the diffusing conducting defects in the Insulating Matrix determine the switching dynamics and resistance retention. The interface at the Bottom Electrode has a significant impact on the low-current operation and long endurance of the memory cell. Our first-principles findings are confirmed by experimental measurements on fabricated RRAM devices.

  12. A new compact model for bipolar RRAMs based on truncated-cone conductive filaments—a Verilog-A approach

    NASA Astrophysics Data System (ADS)

    González-Cordero, G.; Roldan, J. B.; Jiménez-Molinos, F.; Suñé, J.; Long, S.; Liu, M.

    2016-11-01

    A new model for bipolar resistive random-access memories (RRAMs) is presented in this article. Redox and diffusion processes are used to describe in detail the physics behind the filamentary resistive switching (RS) mechanisms of the RRAMs under study. The model includes truncated-cone shaped filaments which are known to be close to the real conductive filament (CF) geometry and a detailed thermal approach, where two temperatures are considered to describe the rupture process at the CF’s narrowest part and also the main CF body’s electrical conductivity variations. Ti/ZrO2/Pt RRAM devices have been fabricated and measured, and the model has allowed us to reproduce the experimental data for all the cases analyzed. Finally, the model has been implemented in Verilog-A code within the ADS circuit simulator, and the response of a device to pulsed external voltages within a characterization circuit has been simulated, producing good results when compared with experimental measurements.

  13. Dynamic computing random access memory

    NASA Astrophysics Data System (ADS)

    Traversa, F. L.; Bonani, F.; Pershin, Y. V.; Di Ventra, M.

    2014-07-01

    The present von Neumann computing paradigm involves a significant amount of information transfer between a central processing unit and memory, with concomitant limitations in the actual execution speed. However, it has been recently argued that a different form of computation, dubbed memcomputing (Di Ventra and Pershin 2013 Nat. Phys. 9 200-2) and inspired by the operation of our brain, can resolve the intrinsic limitations of present day architectures by allowing for computing and storing of information on the same physical platform. Here we show a simple and practical realization of memcomputing that utilizes easy-to-build memcapacitive systems. We name this architecture dynamic computing random access memory (DCRAM). We show that DCRAM provides massively-parallel and polymorphic digital logic, namely it allows for different logic operations with the same architecture, by varying only the control signals. In addition, by taking into account realistic parameters, its energy expenditures can be as low as a few fJ per operation. DCRAM is fully compatible with CMOS technology, can be realized with current fabrication facilities, and therefore can really serve as an alternative to the present computing technology.

  14. Dynamic computing random access memory.

    PubMed

    Traversa, F L; Bonani, F; Pershin, Y V; Di Ventra, M

    2014-07-18

    The present von Neumann computing paradigm involves a significant amount of information transfer between a central processing unit and memory, with concomitant limitations in the actual execution speed. However, it has been recently argued that a different form of computation, dubbed memcomputing (Di Ventra and Pershin 2013 Nat. Phys. 9 200-2) and inspired by the operation of our brain, can resolve the intrinsic limitations of present day architectures by allowing for computing and storing of information on the same physical platform. Here we show a simple and practical realization of memcomputing that utilizes easy-to-build memcapacitive systems. We name this architecture dynamic computing random access memory (DCRAM). We show that DCRAM provides massively-parallel and polymorphic digital logic, namely it allows for different logic operations with the same architecture, by varying only the control signals. In addition, by taking into account realistic parameters, its energy expenditures can be as low as a few fJ per operation. DCRAM is fully compatible with CMOS technology, can be realized with current fabrication facilities, and therefore can really serve as an alternative to the present computing technology.

  15. X-ray spectromicroscopy investigation of soft and hard breakdown in RRAM devices.

    PubMed

    Carta, D; Guttmann, P; Regoutz, A; Khiat, A; Serb, A; Gupta, I; Mehonic, A; Buckwell, M; Hudziak, S; Kenyon, A J; Prodromakis, T

    2016-08-26

    Resistive random access memory (RRAM) is considered an attractive candidate for next generation memory devices due to its competitive scalability, low-power operation and high switching speed. The technology however, still faces several challenges that overall prohibit its industrial translation, such as low yields, large switching variability and ultimately hard breakdown due to long-term operation or high-voltage biasing. The latter issue is of particular interest, because it ultimately leads to device failure. In this work, we have investigated the physicochemical changes that occur within RRAM devices as a consequence of soft and hard breakdown by combining full-field transmission x-ray microscopy with soft x-ray spectroscopic analysis performed on lamella samples. The high lateral resolution of this technique (down to 25 nm) allows the investigation of localized nanometric areas underneath permanent damage of the metal top electrode. Results show that devices after hard breakdown present discontinuity in the active layer, Pt inclusions and the formation of crystalline phases such as rutile, which indicates that the temperature increased locally up to 1000 K. PMID:27420908

  16. X-ray spectromicroscopy investigation of soft and hard breakdown in RRAM devices.

    PubMed

    Carta, D; Guttmann, P; Regoutz, A; Khiat, A; Serb, A; Gupta, I; Mehonic, A; Buckwell, M; Hudziak, S; Kenyon, A J; Prodromakis, T

    2016-08-26

    Resistive random access memory (RRAM) is considered an attractive candidate for next generation memory devices due to its competitive scalability, low-power operation and high switching speed. The technology however, still faces several challenges that overall prohibit its industrial translation, such as low yields, large switching variability and ultimately hard breakdown due to long-term operation or high-voltage biasing. The latter issue is of particular interest, because it ultimately leads to device failure. In this work, we have investigated the physicochemical changes that occur within RRAM devices as a consequence of soft and hard breakdown by combining full-field transmission x-ray microscopy with soft x-ray spectroscopic analysis performed on lamella samples. The high lateral resolution of this technique (down to 25 nm) allows the investigation of localized nanometric areas underneath permanent damage of the metal top electrode. Results show that devices after hard breakdown present discontinuity in the active layer, Pt inclusions and the formation of crystalline phases such as rutile, which indicates that the temperature increased locally up to 1000 K.

  17. X-ray spectromicroscopy investigation of soft and hard breakdown in RRAM devices

    NASA Astrophysics Data System (ADS)

    Carta, D.; Guttmann, P.; Regoutz, A.; Khiat, A.; Serb, A.; Gupta, I.; Mehonic, A.; Buckwell, M.; Hudziak, S.; Kenyon, A. J.; Prodromakis, T.

    2016-08-01

    Resistive random access memory (RRAM) is considered an attractive candidate for next generation memory devices due to its competitive scalability, low-power operation and high switching speed. The technology however, still faces several challenges that overall prohibit its industrial translation, such as low yields, large switching variability and ultimately hard breakdown due to long-term operation or high-voltage biasing. The latter issue is of particular interest, because it ultimately leads to device failure. In this work, we have investigated the physicochemical changes that occur within RRAM devices as a consequence of soft and hard breakdown by combining full-field transmission x-ray microscopy with soft x-ray spectroscopic analysis performed on lamella samples. The high lateral resolution of this technique (down to 25 nm) allows the investigation of localized nanometric areas underneath permanent damage of the metal top electrode. Results show that devices after hard breakdown present discontinuity in the active layer, Pt inclusions and the formation of crystalline phases such as rutile, which indicates that the temperature increased locally up to 1000 K.

  18. Modulation of surface trap induced resistive switching by electrode annealing in individual PbS micro/nanowire-based devices for resistance random access memory.

    PubMed

    Zheng, Jianping; Cheng, Baochang; Wu, Fuzhang; Su, Xiaohui; Xiao, Yanhe; Guo, Rui; Lei, Shuijin

    2014-12-10

    Bipolar resistive switching (RS) devices are commonly believed as a promising candidate for next generation nonvolatile resistance random access memory (RRAM). Here, two-terminal devices based on individual PbS micro/nanowires with Ag electrodes are constructed, whose electrical transport depends strongly on the abundant surface and bulk trap states in micro/nanostructures. The surface trap states can be filled/emptied effectively at negative/positive bias voltage, respectively, and the corresponding rise/fall of the Fermi level induces a variation in a degenerate/nondegenerate state, resulting in low/high resistance. Moreover, the filling/emptying of trap states can be utilized as RRAM. After annealing, the surface trap state can almost be eliminated completely; while most of the bulk trap states can still remain. In the devices unannealed and annealed at both ends, therefore, the symmetrical back-to-back Fowler-Nordheim tunneling with large ON/OFF resistance ratio and Poole-Frenkel emission with poor hysteresis can be observed under cyclic sweep voltage, respectively. However, a typical bipolar RS behavior can be observed effectively in the devices annealed at one end. The acquirement of bipolar RS and nonvolatile RRAM by the modulation of electrode annealing demonstrates the abundant trap states in micro/nanomaterials will be advantageous to the development of new type electronic components.

  19. Scanning transmission X-ray microscopy probe for in situ mechanism study of graphene-oxide-based resistive random access memory.

    PubMed

    Nho, Hyun Woo; Kim, Jong Yun; Wang, Jian; Shin, Hyun-Joon; Choi, Sung-Yool; Yoon, Tae Hyun

    2014-01-01

    Here, an in situ probe for scanning transmission X-ray microscopy (STXM) has been developed and applied to the study of the bipolar resistive switching (BRS) mechanism in an Al/graphene oxide (GO)/Al resistive random access memory (RRAM) device. To perform in situ STXM studies at the C K- and O K-edges, both the RRAM junctions and the I0 junction were fabricated on a single Si3N4 membrane to obtain local XANES spectra at these absorption edges with more delicate I0 normalization. Using this probe combined with the synchrotron-based STXM technique, it was possible to observe unique chemical changes involved in the BRS process of the Al/GO/Al RRAM device. Reversible oxidation and reduction of GO induced by the externally applied bias voltages were observed at the O K-edge XANES feature located at 538.2 eV, which strongly supported the oxygen ion drift model that was recently proposed from ex situ transmission electron microscope studies.

  20. Memory access in shared virtual memory

    SciTech Connect

    Berrendorf, R.

    1992-09-01

    Shared virtual memory (SVM) is a virtual memory layer with a single address space on top of a distributed real memory on parallel computers. We examine the behavior and performance of SVM running a parallel program with medium-grained, loop-level parallelism on top of it. A simulator for the underlying parallel architecture can be used to examine the behavior of SVM more deeply. The influence of several parameters, such as the number of processors, page size, cold or warm start, and restricted page replication, is studied.

  1. Memory access in shared virtual memory

    SciTech Connect

    Berrendorf, R. )

    1992-01-01

    Shared virtual memory (SVM) is a virtual memory layer with a single address space on top of a distributed real memory on parallel computers. We examine the behavior and performance of SVM running a parallel program with medium-grained, loop-level parallelism on top of it. A simulator for the underlying parallel architecture can be used to examine the behavior of SVM more deeply. The influence of several parameters, such as the number of processors, page size, cold or warm start, and restricted page replication, is studied.

  2. Stack optimization of oxide-based RRAM for fast write speed (<1 μs) at low operating current (<10 μA)

    NASA Astrophysics Data System (ADS)

    Chen, C. Y.; Goux, L.; Fantini, A.; Degraeve, R.; Redolfi, A.; Groeseneken, G.; Jurczak, M.

    2016-11-01

    In this paper we engineer a TiN ⧹ Al2O3 ⧹ (Hf,Al)O2 ⧹ Ta2O5 ⧹ Hf Oxide Resistive Random Access Memory (OxRRAM) device for fast switching at low operation current without sacrificing the retention and endurance properties. The integrated 40 nm × 40 nm cell switches at 10 μA using write pulses shorter than 100 ns (resp. 1 μs) for Reset (resp. Set) and with amplitude <2 V. Using these conditions in a specially developed verify algorithm, a resistive window of 10× is reliably obtained, decreasing the write speed by more than 1 decade compared to state-of-the-art OxRRAM stacks at same current level.

  3. Low-power resistive random access memory by confining the formation of conducting filaments

    NASA Astrophysics Data System (ADS)

    Huang, Yi-Jen; Shen, Tzu-Hsien; Lee, Lan-Hsuan; Wen, Cheng-Yen; Lee, Si-Chen

    2016-06-01

    Owing to their small physical size and low power consumption, resistive random access memory (RRAM) devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiOx/silver nanoparticles/TiOx/AlTiOx, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V), low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistance state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiOx layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.

  4. Solution-processed Al-chelated gelatin for highly transparent non-volatile memory applications

    SciTech Connect

    Chang, Yu-Chi; Wang, Yeong-Her

    2015-03-23

    Using the biomaterial of Al-chelated gelatin (ACG) prepared by sol-gel method in the ITO/ACG/ITO structure, a highly transparent resistive random access memory (RRAM) was obtained. The transmittance of the fabricated device is approximately 83% at 550 nm while that of Al/gelatin/ITO is opaque. As to the ITO/gelatin/ITO RRAM, no resistive switching behavior can be seen. The ITO/ACG/ITO RRAM shows high ON/OFF current ratio (>10{sup 5}), low operation voltage, good uniformity, and retention characteristics at room temperature and 85 °C. The mechanism of the ACG-based memory devices is presented. The enhancement of these electrical properties can be attributed to the chelate effect of Al ions with gelatin. Results show that transparent ACG-based memory devices possess the potential for next-generation resistive memories and bio-electronic applications.

  5. Cu impurity in insulators and in metal-insulator-metal structures: Implications for resistance-switching random access memories

    SciTech Connect

    Pandey, Sumeet C. Meade, Roy; Sandhu, Gurtej S.

    2015-02-07

    We present numerical results from atomistic simulations of Cu in SiO{sub 2} and Al{sub 2}O{sub 3}, with an emphasis on the thermodynamic, kinetic, and electronic properties. The calculated properties of Cu impurity at various concentrations (9.91 × 10{sup 20 }cm{sup −3} and 3.41 × 10{sup 22 }cm{sup −3}) in bulk oxides are presented. The metal-insulator interfaces result in up to a ∼4 eV reduction in the formation energies relative to the crystalline bulk. Additionally, the importance of Cu-Cu interaction in lowering the chemical potential is introduced. These concepts are then discussed in the context of formation and stability of localized conductive paths in resistance-switching Random Access Memories (RRAM-M). The electronic density of states and non-equilibrium transmission through these localized paths are studied, confirming conduction by showing three orders of magnitude increase in the electron transmission. The dynamic behavior of the conductive paths is investigated with atomistic drift-diffusion calculations. Finally, the paper concludes with a molecular dynamics simulation of a RRAM-M cell that attempts to combine the aforementioned phenomena in one self-consistent model.

  6. Magnetic Analog Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.; Wu, Jiin-Chuan; Stadler, Henry L.

    1991-01-01

    Proposed integrated, solid-state, analog random-access memory base on principle of magnetic writing and magnetoresistive reading. Current in writing conductor magnetizes storage layer. Remanent magnetization in storage layer penetrates readout layer and detected by magnetoresistive effect or Hall effect. Memory cells are part of integrated circuit including associated reading and writing transistors. Intended to provide high storage density and rapid access, nonvolatile, consumes little power, and relatively invulnerable to ionizing radiation.

  7. Statistical analysis of random telegraph noise in HfO2-based RRAM devices in LRS

    NASA Astrophysics Data System (ADS)

    Puglisi, Francesco Maria; Pavan, Paolo; Larcher, Luca; Padovani, Andrea

    2015-11-01

    In this work, we present a thorough statistical characterization of Random Telegraph Noise (RTN) in HfO2-based Resistive Random Access Memory (RRAM) cells in Low Resistive State (LRS). Devices are tested under a variety of operational conditions. A Factorial Hidden Markov Model (FHMM) analysis is exploited to extrapolate the properties of the traps causing multi-level RTN in LRS. The trapping and de-trapping of charge carriers into/out of defects located in the proximity of the conductive filament results in a shielding effect on a portion of the conductive filament, leading to the observed RTN current fluctuations. It is found that both oxygen vacancies and oxygen ions defects may be responsible for the observed RTN. The variations of the current observed at subsequent set/reset cycles are instead attributed to the stochastic variations in the filament due to oxidation/reduction processes during reset and set operations, respectively.

  8. a-SiNx:H-based ultra-low power resistive random access memory with tunable Si dangling bond conduction paths.

    PubMed

    Jiang, Xiaofan; Ma, Zhongyuan; Xu, Jun; Chen, Kunji; Xu, Ling; Li, Wei; Huang, Xinfan; Feng, Duan

    2015-10-28

    The realization of ultra-low power Si-based resistive switching memory technology will be a milestone in the development of next generation non-volatile memory. Here we show that a high performance and ultra-low power resistive random access memory (RRAM) based on an Al/a-SiNx:H/p(+)-Si structure can be achieved by tuning the Si dangling bond conduction paths. We reveal the intrinsic relationship between the Si dangling bonds and the N/Si ratio x for the a-SiNx:H films, which ensures that the programming current can be reduced to less than 1 μA by increasing the value of x. Theoretically calculated current-voltage (I-V) curves combined with the temperature dependence of the I-V characteristics confirm that, for the low-resistance state (LRS), the Si dangling bond conduction paths obey the trap-assisted tunneling model. In the high-resistance state (HRS), conduction is dominated by either hopping or Poole-Frenkel (P-F) processes. Our introduction of hydrogen in the a-SiNx:H layer provides a new way to control the Si dangling bond conduction paths, and thus opens up a research field for ultra-low power Si-based RRAM.

  9. a-SiNx:H-based ultra-low power resistive random access memory with tunable Si dangling bond conduction paths

    PubMed Central

    Jiang, Xiaofan; Ma, Zhongyuan; Xu, Jun; Chen, Kunji; Xu, Ling; Li, Wei; Huang, Xinfan; Feng, Duan

    2015-01-01

    The realization of ultra-low power Si-based resistive switching memory technology will be a milestone in the development of next generation non-volatile memory. Here we show that a high performance and ultra-low power resistive random access memory (RRAM) based on an Al/a-SiNx:H/p+-Si structure can be achieved by tuning the Si dangling bond conduction paths. We reveal the intrinsic relationship between the Si dangling bonds and the N/Si ratio x for the a-SiNx:H films, which ensures that the programming current can be reduced to less than 1 μA by increasing the value of x. Theoretically calculated current-voltage (I–V ) curves combined with the temperature dependence of the I–V characteristics confirm that, for the low-resistance state (LRS), the Si dangling bond conduction paths obey the trap-assisted tunneling model. In the high-resistance state (HRS), conduction is dominated by either hopping or Poole–Frenkel (P–F) processes. Our introduction of hydrogen in the a-SiNx:H layer provides a new way to control the Si dangling bond conduction paths, and thus opens up a research field for ultra-low power Si-based RRAM. PMID:26508086

  10. Microscopic origin of read current noise in TaOx-based resistive switching memory by ultra-low temperature measurement

    NASA Astrophysics Data System (ADS)

    Pan, Yue; Cai, Yimao; Liu, Yefan; Fang, Yichen; Yu, Muxi; Tan, Shenghu; Huang, Ru

    2016-04-01

    TaOx-based resistive random access memory (RRAM) attracts considerable attention for the development of next generation nonvolatile memories. However, read current noise in RRAM is one of the critical concerns for storage application, and its microscopic origin is still under debate. In this work, the read current noise in TaOx-based RRAM was studied thoroughly. Based on a noise power spectral density analysis at room temperature and at ultra-low temperature of 25 K, discrete random telegraph noise (RTN) and continuous average current fluctuation (ACF) are identified and decoupled from the total read current noise in TaOx RRAM devices. A statistical comparison of noise amplitude further reveals that ACF depends strongly on the temperature, whereas RTN is independent of the temperature. Measurement results combined with conduction mechanism analysis show that RTN in TaOx RRAM devices arises from electron trapping/detrapping process in the hopping conduction, and ACF is originated from the thermal activation of conduction centers that form the percolation network. At last, a unified model in the framework of hopping conduction is proposed to explain the underlying mechanism of both RTN and ACF noise, which can provide meaningful guidelines for designing noise-immune RRAM devices.

  11. Ultra-low power, highly uniform polymer memory by inserted multilayer graphene electrode

    NASA Astrophysics Data System (ADS)

    Jang, Byung Chul; Seong, Hyejeong; Kim, Jong Yun; Koo, Beom Jun; Kim, Sung Kyu; Yang, Sang Yoon; Gap Im, Sung; Choi, Sung-Yool

    2015-12-01

    Filament type resistive random access memory (RRAM) based on polymer thin films is a promising device for next generation, flexible nonvolatile memory. However, the resistive switching nonuniformity and the high power consumption found in the general filament type RRAM devices present critical issues for practical memory applications. Here, we introduce a novel approach not only to reduce the power consumption but also to improve the resistive switching uniformity in RRAM devices based on poly(1,3,5-trimethyl-3,4,5-trivinyl cyclotrisiloxane) by inserting multilayer graphene (MLG) at the electrode/polymer interface. The resistive switching uniformity was thereby significantly improved, and the power consumption was markedly reduced by 250 times. Furthermore, the inserted MLG film enabled a transition of the resistive switching operation from unipolar resistive switching to bipolar resistive switching and induced self-compliance behavior. The findings of this study can pave the way toward a new area of application for graphene in electronic devices.

  12. Low latency memory access and synchronization

    DOEpatents

    Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.; Gara, Alan G.; Giampapa, Mark E.; Heidelberger, Philip; Hoenicke, Dirk; Ohmacht, Martin; Steinmacher-Burow, Burkhard D.; Takken, Todd E. , Vranas; Pavlos M.

    2010-10-19

    A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.

  13. Low latency memory access and synchronization

    DOEpatents

    Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.; Gara, Alan G.; Giampapa, Mark E.; Heidelberger, Philip; Hoenicke, Dirk; Ohmacht, Martin; Steinmacher-Burow, Burkhard D.; Takken, Todd E.; Vranas, Pavlos M.

    2007-02-06

    A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.

  14. A biohybrid dynamic random access memory.

    PubMed

    Sinclair, Jon; Granfeldt, Daniel; Pihl, Johan; Millingen, Maria; Lincoln, Per; Farre, Cecilia; Peterson, Lena; Orwar, Owe

    2006-04-19

    We report that GABA(A) receptors in a patch-clamped biological cell form a short-term memory circuit when integrated with a scanning-probe microfluidic device. Laminar patterns of receptor activators (agonists) provided by the microfluidic device define and periodically update the data input which is read and stored by the receptors as state distributions (based on intrinsic multistate kinetics). The memory is discharged over time and lasts for seconds to minutes depending on the input function. The function of the memory can be represented by an equivalent electronic circuit with striking similarity in function to a dynamic random access memory (DRAM) used in electronic computers. Multiplexed biohybrid memories may form the basis of large-scale integrated biocomputational/sensor devices with the curious ability to use chemical signals including odorants, neurotransmitters, chemical and biological warfare agents, and many more as input signals.

  15. Non-volatile magnetic random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-Chuan (Inventor)

    1994-01-01

    Improvements are made in a non-volatile magnetic random access memory. Such a memory is comprised of an array of unit cells, each having a Hall-effect sensor and a thin-film magnetic element made of material having an in-plane, uniaxial anisotropy and in-plane, bipolar remanent magnetization states. The Hall-effect sensor is made more sensitive by using a 1 m thick molecular beam epitaxy grown InAs layer on a silicon substrate by employing a GaAs/AlGaAs/InAlAs superlattice buffering layer. One improvement avoids current shunting problems of matrix architecture. Another improvement reduces the required magnetizing current for the micromagnets. Another improvement relates to the use of GaAs technology wherein high electron-mobility GaAs MESFETs provide faster switching times. Still another improvement relates to a method for configuring the invention as a three-dimensional random access memory.

  16. Parallel-access memory management using fast-fits

    SciTech Connect

    Johnson, T.

    1994-12-01

    The two most common approaches to managing shared-access memory-free lists and buddy system-have significant drawbacks. Free list algorithms have poor memory access characteristics, and buddy systems utilize their space inefficiently. In this paper, we present an alternative approach to parallel-access memory management based on the fast-fits algorithm. A fast-fits memory manager stores free blocks in a tree structure, providing fast access and efficient space use. Since the fast-fits algorithm accesses fewer blocks than a free list algorithm, it reduces the amount of cache invalidation overhead due to the memory manager. Our performance experiments show that the parallel-access fast-fits memory manager allows significantly greater access rates than a serial-access fast-fits memory manager does. We not that shared-memory multiprocessor systems need efficient dynamic storage allocators, both for system purposes and to support parallel programs.

  17. Anomalous random telegraph noise and temporary phenomena in resistive random access memory

    NASA Astrophysics Data System (ADS)

    Puglisi, Francesco Maria; Larcher, Luca; Padovani, Andrea; Pavan, Paolo

    2016-11-01

    In this paper we present a comprehensive examination of the characteristics of complex Random Telegraph Noise (RTN) signals in Resistive Random Access Memory (RRAM) devices with TiN/Ti/HfO2/TiN structure. Initially, the anomalous RTN (aRTN) is investigated through careful systematic experiment, dedicated characterization procedures, and physics-based simulations to gain insights into the physics of this phenomenon. The experimentally observed RTN parameters (amplitude of the current fluctuations, capture and emission times) are analyzed in different operating conditions. Anomalous behaviors are characterized and their statistical characteristics are evaluated. Physics-based simulations considering both the Coulomb interactions among different defects in the device and the possible existence of defects with metastable states are exploited to suggest a possible physical origin of aRTN. The same simulation framework is also shown to be able to predict other temporary phenomena related to RTN, such as the temporary change in RTN stochastic properties or the sudden and iterative random appearing and vanishing of RTN fluctuations always exhibiting the same statistical characteristics. Results highlight the central role of the electrostatic interactions among individual defects and the trapped charge in describing RTN and related phenomena.

  18. Self-selection bipolar resistive switching phenomena observed in NbON/NbN bilayer for cross-bar array memory applications

    SciTech Connect

    Kim, Hee-Dong; Yun, Min Ju; Kim, Tae Geun

    2014-11-24

    In this letter, to integrate bipolar resistive switching cells into cross bar array (CBA) structure, we study one-selector (1S) and one-resistor (1R) behavior of a niobium oxynitride (NbON) and niobium nitride (NbN) bilayer for the applications of resistive random access memory (RRAM). In this structure, a NbN layer exhibits bipolar switching characteristics while a NbON layer acts as the selector. The NbN-based 1S1R devices within a single RRAM memory cell can be directly integrated into a CBA structure without the need of extra diodes; this can significantly reduce the fabrication complexity.

  19. First principle simulations on the effects of oxygen vacancy in HfO2-based RRAM

    NASA Astrophysics Data System (ADS)

    Dai, Yuehua; Zhao, Yuanyang; Wang, Jiayu; Xu, Jianbin; Yang, Fei

    2015-01-01

    HfO2-based resistive random access memory (RRAM) takes advantage of oxygen vacancy (V o) defects in its principle of operation. Since the change in resistivity of the material is controlled by the level of oxygen deficiency in the material, it is significantly important to study the performance of oxygen vacancies in formation of conductive filament. Excluding effects of the applied voltage, the Vienna ab initio simulation package (VASP) is used to investigate the orientation and concentration mechanism of the oxygen vacancies based on the first principle. The optimal value of crystal orientation [010] is identified by means of the calculated isosurface plots of partial charge density, formation energy, highest isosurface value, migration barrier, and energy band of oxygen vacancy in ten established orientation systems. It will effectively influence the SET voltage, forming voltage, and the ON/OFF ratio of the device. Based on the results of orientation dependence, different concentration models are established along crystal orientation [010]. The performance of proposed concentration models is evaluated and analyzed in this paper. The film is weakly conductive for the samples deposited in a mixture with less than 4.167at.% of V o contents, and the resistive switching (RS) phenomenon cannot be observed in this case. The RS behavior improves with an increase in the V o contents from 4.167at.% to 6.25at.%; nonetheless, it is found difficult to switch to a stable state. However, a higher V o concentration shows a more favorable uniformity and stability for HfO2-based RRAM.

  20. Simplified ZrTiO x -based RRAM cell structure with rectifying characteristics by integrating Ni/n + -Si diode

    PubMed Central

    2014-01-01

    A simplified one-diode one-resistor (1D1R) resistive switching memory cell that uses only four layers of TaN/ZrTiO x /Ni/n+-Si was proposed to suppress sneak current where TaN/ZrTiO x /Ni can be regarded as a resistive-switching random access memory (RRAM) device while Ni/n+-Si acts as an Schottky diode. This is the first RRAM cell structure that employs metal/semiconductor Schottky diode for current rectifying. The 1D1R cell exhibits bipolar switching behavior with SET/RESET voltage close to 1 V without requiring a forming process. More importantly, the cell shows tight resistance distribution for different states, significantly rectifying characteristics with forward/reverse current ratio higher than 103 and a resistance ratio larger than 103 between two states. Furthermore, the cell also displays desirable reliability performance in terms of long data retention time of up to 104 s and robust endurance of 105 cycles. Based on the promising characteristics, the four-layer 1D1R structure holds the great potential for next-generation nonvolatile memory technology. PMID:24936165

  1. Power- and Low-Resistance-State-Dependent, Bipolar Reset-Switching Transitions in SiN-Based Resistive Random-Access Memory

    NASA Astrophysics Data System (ADS)

    Kim, Sungjun; Park, Byung-Gook

    2016-08-01

    A study on the bipolar-resistive switching of an Ni/SiN/Si-based resistive random-access memory (RRAM) device shows that the influences of the reset power and the resistance value of the low-resistance state (LRS) on the reset-switching transitions are strong. For a low LRS with a large conducting path, the sharp reset switching, which requires a high reset power (>7 mW), was observed, whereas for a high LRS with small multiple-conducting paths, the step-by-step reset switching with a low reset power (<7 mW) was observed. The attainment of higher nonlinear current-voltage ( I-V) characteristics in terms of the step-by-step reset switching is due to the steep current-increased region of the trap-controlled space charge-limited current (SCLC) model. A multilevel cell (MLC) operation, for which the reset stop voltage ( V STOP) is used in the DC sweep mode and an incremental amplitude is used in the pulse mode for the step-by-step reset switching, is demonstrated here. The results of the present study suggest that well-controlled conducting paths in a SiN-based RRAM device, which are not too strong and not too weak, offer considerable potential for the realization of low-power and high-density crossbar-array applications.

  2. Self-selection effects and modulation of TaOx resistive switching random access memory with bottom electrode of highly doped Si

    NASA Astrophysics Data System (ADS)

    Yu, Muxi; Fang, Yichen; Wang, Zongwei; Pan, Yue; Li, Ming; Cai, Yimao; Huang, Ru

    2016-05-01

    In this paper, we propose a TaOx resistive switching random access memory (RRAM) device with operation-polarity-dependent self-selection effect by introducing highly doped silicon (Si) electrode, which is promising for large-scale integration. It is observed that with highly doped Si as the bottom electrode (BE), the RRAM devices show non-linear (>103) I-V characteristic during negative Forming/Set operation and linear behavior during positive Forming/Set operation. The underling mechanisms for the linear and non-linear behaviors at low resistance states of the proposed device are extensively investigated by varying operation modes, different metal electrodes, and Si doping type. Experimental data and theoretical analysis demonstrate that the operation-polarity-dependent self-selection effect in our devices originates from the Schottky barrier between the TaOx layer and the interfacial SiOx formed by reaction between highly doped Si BE and immigrated oxygen ions in the conductive filament area.

  3. Power- and Low-Resistance-State-Dependent, Bipolar Reset-Switching Transitions in SiN-Based Resistive Random-Access Memory.

    PubMed

    Kim, Sungjun; Park, Byung-Gook

    2016-12-01

    A study on the bipolar-resistive switching of an Ni/SiN/Si-based resistive random-access memory (RRAM) device shows that the influences of the reset power and the resistance value of the low-resistance state (LRS) on the reset-switching transitions are strong. For a low LRS with a large conducting path, the sharp reset switching, which requires a high reset power (>7 mW), was observed, whereas for a high LRS with small multiple-conducting paths, the step-by-step reset switching with a low reset power (<7 mW) was observed. The attainment of higher nonlinear current-voltage (I-V) characteristics in terms of the step-by-step reset switching is due to the steep current-increased region of the trap-controlled space charge-limited current (SCLC) model. A multilevel cell (MLC) operation, for which the reset stop voltage (V STOP) is used in the DC sweep mode and an incremental amplitude is used in the pulse mode for the step-by-step reset switching, is demonstrated here. The results of the present study suggest that well-controlled conducting paths in a SiN-based RRAM device, which are not too strong and not too weak, offer considerable potential for the realization of low-power and high-density crossbar-array applications. PMID:27518231

  4. Remote direct memory access over datagrams

    DOEpatents

    Grant, Ryan Eric; Rashti, Mohammad Javad; Balaji, Pavan; Afsahi, Ahmad

    2014-12-02

    A communication stack for providing remote direct memory access (RDMA) over a datagram network is disclosed. The communication stack has a user level interface configured to accept datagram related input and communicate with an RDMA enabled network interface card (NIC) via an NIC driver. The communication stack also has an RDMA protocol layer configured to supply one or more data transfer primitives for the datagram related input of the user level. The communication stack further has a direct data placement (DDP) layer configured to transfer the datagram related input from a user storage to a transport layer based on the one or more data transfer primitives by way of a lower layer protocol (LLP) over the datagram network.

  5. Direct memory access transfer completion notification

    DOEpatents

    Chen, Dong; Giampapa, Mark E.; Heidelberger, Philip; Kumar, Sameer; Parker, Jeffrey J.; Steinmacher-Burow, Burkhard D.; Vranas, Pavlos

    2010-07-27

    Methods, compute nodes, and computer program products are provided for direct memory access (`DMA`) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (`FIFO`) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.

  6. Resistive switching characteristics of Al/Si3N4/p-Si MIS-based resistive switching memory devices

    NASA Astrophysics Data System (ADS)

    Kim, Hee-Dong; Yun, Min Ju; Kim, Sungho

    2016-08-01

    In this study, we proposed and demonstrated a self-rectifying property of a silicon nitride (Si3N4)-based resistive random access memory (RRAM) device by employing p-type silicon ( p-Si) as the bottom electrode. The RRAM devices consisting of Al/Si3N4/ p-Si are fabricated by using a low-pressure chemical-vapor deposition and exhibited an intrinsic diode property with non-linear current-voltage ( I-V) behavior. In addition, compared to the conventional metal/insulator/metal (MIM) structure of Al/Si3N4/Ti RRAM cells, the operating current over the entire bias region for the proposed metal/insulator/semiconductor (MIS) cells is dramatically lower because the introduced p-Si bottom electrode efficiently suppresses the current in both the low- and the high resistance states. Then, the results mean that when p-Si is employed as a bottom electrode, the Si3N4-based RRAM cells can be applied to selector-free RRAM cells.

  7. Self-Testing Static Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Chau, Savio; Rennels, David

    1991-01-01

    Proposed static random-access memory for computer features improved error-detecting and -correcting capabilities. New self-testing scheme provides for detection and correction of errors at any time during normal operation - even while data being written into memory. Faults in equipment causing errors in output data detected by repeatedly testing every memory cell to determine whether it can still store both "one" and "zero", without destroying data stored in memory.

  8. 76 FR 55417 - In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-09-07

    ... COMMISSION In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products... States after importation of certain dynamic random access memory and NAND flash memory devices and... the sale within the United States after importation of certain dynamic random access memory and...

  9. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

    SciTech Connect

    Ohmacht, Martin

    2014-09-09

    In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

  10. MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays

    NASA Astrophysics Data System (ADS)

    Shenoy, Rohit S.; Burr, Geoffrey W.; Virwani, Kumar; Jackson, Bryan; Padilla, Alvaro; Narayanan, Pritish; Rettner, Charles T.; Shelby, Robert M.; Bethune, Donald S.; Raman, Karthik V.; BrightSky, Matthew; Joseph, Eric; Rice, Philip M.; Topuria, Teya; Kellock, Andrew J.; Kurdi, Bülent; Gopalakrishnan, Kailash

    2014-10-01

    Several attractive applications call for the organization of memristive devices (or other resistive non-volatile memory (NVM)) into large, densely-packed crossbar arrays. While resistive-NVM devices frequently possess some degree of inherent nonlinearity (typically 3-30× contrast), the operation of large (\\gt 1000×1000 device) arrays at low power tends to require quite large (\\gt 1e7) ON-to-OFF ratios (between the currents passed at high and at low voltages). One path to such large nonlinearities is the inclusion of a distinct access device (AD) together with each of the state-bearing resistive-NVM elements. While such an AD need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device. Several candidate ADs have been proposed, but obtaining high performance without requiring single-crystal silicon and/or the high processing temperatures of the front-end-of-the-line—which would eliminate any opportunity for 3D stacking—has been difficult. We review our work at IBM Research—Almaden on high-performance ADs based on Cu-containing mixed-ionic-electronic conduction (MIEC) materials [1-7]. These devices require only the low processing temperatures of the back-end-of-the-line, making them highly suitable for implementing multi-layer cross-bar arrays. MIEC-based ADs offer large ON/OFF ratios (\\gt 1e7), a significant voltage margin {{V}m} (over which current \\lt 10 nA), and ultra-low leakage (\\lt 10 pA), while also offering the high current densities needed for phase-change memory and the fully bipolar operation needed for high-performance RRAM. Scalability to critical lateral dimensions \\lt 30 nm and thicknesses \\lt 15 nm, tight distributions and 100% yield in large (512 kBit) arrays, long-term stability of the ultra-low leakage states, and sub-50 ns turn-ON times have all been demonstrated. Numerical modeling of these MIEC-based ADs shows that their operation depends on C{{u}+} mediated hole

  11. Effects of different dopants on switching behavior of HfO2-based resistive random access memory

    NASA Astrophysics Data System (ADS)

    Deng, Ning; Pang, Hua; Wu, Wei

    2014-10-01

    In this study the effects of doping atoms (Al, Cu, and N) with different electro-negativities and ionic radii on resistive switching of HfO2-based resistive random access memory (RRAM) are systematically investigated. The results show that forming voltages and set voltages of Al/Cu-doped devices are reduced. Among all devices, Cu-doped device shows the narrowest device-to-device distributions of set voltage and low resistance. The effects of different dopants on switching behavior are explained with deferent types of CFs formed in HfO2 depending on dopants: oxygen vacancy (Vo) filaments for Al-doped HfO2 devices, hybrid filaments composed of oxygen vacancies and Cu atoms for Cu-doped HfO2 devices, and nitrogen/oxygen vacancy filaments for N-doped HfO2 devices. The results suggest that a metal dopant with a larger electro-negativity than host metal atom offers the best comprehensive performance.

  12. Resistance switching memory in perovskite oxides

    SciTech Connect

    Yan, Z.B. Liu, J.-M.

    2015-07-15

    The resistance switching behavior has recently attracted great attentions for its application as resistive random access memories (RRAMs) due to a variety of advantages such as simple structure, high-density, high-speed and low-power. As a leading storage media, the transition metal perovskite oxide owns the strong correlation of electrons and the stable crystal structure, which brings out multifunctionality such as ferroelectric, multiferroic, superconductor, and colossal magnetoresistance/electroresistance effect, etc. The existence of rich electronic phases, metal–insulator transition and the nonstoichiometric oxygen in perovskite oxide provides good platforms to insight into the resistive switching mechanisms. In this review, we first introduce the general characteristics of the resistance switching effects, the operation methods and the storage media. Then, the experimental evidences of conductive filaments, the transport and switching mechanisms, and the memory performances and enhancing methods of perovskite oxide based filamentary RRAM cells have been summarized and discussed. Subsequently, the switching mechanisms and the performances of the uniform RRAM cells associating with the carrier trapping/detrapping and the ferroelectric polarization switching have been discussed. Finally, the advices and outlook for further investigating the resistance switching and enhancing the memory performances are given.

  13. Temperature induced complementary switching in titanium oxide resistive random access memory

    NASA Astrophysics Data System (ADS)

    Panda, D.; Simanjuntak, F. M.; Tseng, T.-Y.

    2016-07-01

    On the way towards high memory density and computer performance, a considerable development in energy efficiency represents the foremost aspiration in future information technology. Complementary resistive switch consists of two antiserial resistive switching memory (RRAM) elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption. Here we present a titanium oxide based complementary RRAM (CRRAM) device with Pt top and TiN bottom electrode. A subsequent post metal annealing at 400°C induces CRRAM. Forming voltage of 4.3 V is required for this device to initiate switching process. The same device also exhibiting bipolar switching at lower compliance current, Ic <50 μA. The CRRAM device have high reliabilities. Formation of intermediate titanium oxi-nitride layer is confirmed from the cross-sectional HRTEM analysis. The origin of complementary switching mechanism have been discussed with AES, HRTEM analysis and schematic diagram. This paper provides valuable data along with analysis on the origin of CRRAM for the application in nanoscale devices.

  14. Super non-linear RRAM with ultra-low power for 3D vertical nano-crossbar arrays.

    PubMed

    Luo, Qing; Xu, Xiaoxin; Liu, Hongtao; Lv, Hangbing; Gong, Tiancheng; Long, Shibing; Liu, Qi; Sun, Haitao; Banerjee, Writam; Li, Ling; Gao, Jianfeng; Lu, Nianduan; Liu, Ming

    2016-08-25

    Vertical crossbar arrays provide a cost-effective approach for high density three-dimensional (3D) integration of resistive random access memory. However, an individual selector device is not allowed to be integrated with the memory cell separately. The development of V-RRAM has impeded the lack of satisfactory self-selective cells. In this study, we have developed a high performance bilayer self-selective device using HfO2 as the memory switching layer and a mixed ionic and electron conductor as the selective layer. The device exhibits high non-linearity (>10(3)) and ultra-low half-select leakage (<0.1 pA). A four layer vertical crossbar array was successfully demonstrated based on the developed self-selective device. High uniformity, ultra-low leakage, sub-nA operation, self-compliance, and excellent read/write disturbance immunity were achieved. The robust array level performance shows attractive potential for low power and high density 3D data storage applications. PMID:27510434

  15. Investigation of the Switching Mechanism in TiO2-Based RRAM: A Two-Dimensional EDX Approach.

    PubMed

    Carta, Daniela; Salaoru, Iulia; Khiat, Ali; Regoutz, Anna; Mitterbauer, Christoph; Harrison, Nicholas M; Prodromakis, Themistoklis

    2016-08-01

    The next generation of nonvolatile memory storage may well be based on resistive switching in metal oxides. TiO2 as transition metal oxide has been widely used as active layer for the fabrication of a variety of multistate memory nanostructure devices. However, progress in their technological development has been inhibited by the lack of a thorough understanding of the underlying switching mechanisms. Here, we employed high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) combined with two-dimensional energy dispersive X-ray spectroscopy (2D EDX) to provide a novel, nanoscale view of the mechanisms involved. Our results suggest that the switching mechanism involves redistribution of both Ti and O ions within the active layer combined with an overall loss of oxygen that effectively render conductive filaments. Our study shows evidence of titanium movement in a 10 nm TiO2 thin-film through direct EDX mapping that provides a viable starting point for the improvement of the robustness and lifetime of TiO2-based resistive random access memory (RRAM). PMID:27409358

  16. Enhanced resistive switching performance for bilayer HfO2/TiO2 resistive random access memory

    NASA Astrophysics Data System (ADS)

    Ye, Cong; Deng, Tengfei; Zhang, Junchi; Shen, Liangping; He, Pin; Wei, Wei; Wang, Hao

    2016-10-01

    We prepared bilayer HfO2/TiO2 resistive random accessory memory (RRAM) using magnetron sputtering on an ITO/PEN flexible substrate. The switching voltages (V SET and V RESET) were smaller for the Pt/HfO2/TiO2/ITO device than for a Pt/HfO2/ITO memory device. The insertion of a TiO2 layer in the switching layer was inferred to act as an oxygen reservoir to reduce the switching voltages. In addition, greatly improved uniformity was achieved, which showed the coefficient of the variations of V SET and V RESET to be 9.90% and 6.35% for the bilayer structure RRAM. We deduced that occurrence of conductive filament connection/rupture at the interface of the HfO2 and TiO2, in combination with the HfO2 acting as a virtual cathode, led to the improved uniformity. A multilevel storage capability can be obtained by varying the stop voltage in the RESET process for bilayer HfO2/TiO2 RRAM. By analyzing the current conduction mechanism, we demonstrated that the multilevel high resistance state (HRS) was attributable to the increased barrier height when the stop voltage was increased.

  17. BCH codes for large IC random-access memory systems

    NASA Technical Reports Server (NTRS)

    Lin, S.; Costello, D. J., Jr.

    1983-01-01

    In this report some shortened BCH codes for possible applications to large IC random-access memory systems are presented. These codes are given by their parity-check matrices. Encoding and decoding of these codes are discussed.

  18. Radiation Effects of Commercial Resistive Random Access Memories

    NASA Technical Reports Server (NTRS)

    Chen, Dakai; LaBel, Kenneth A.; Berg, Melanie; Wilcox, Edward; Kim, Hak; Phan, Anthony; Figueiredo, Marco; Buchner, Stephen; Khachatrian, Ani; Roche, Nicolas

    2014-01-01

    We present results for the single-event effect response of commercial production-level resistive random access memories. We found that the resistive memory arrays are immune to heavy ion-induced upsets. However, the devices were susceptible to single-event functional interrupts, due to upsets from the control circuits. The intrinsic radiation tolerant nature of resistive memory makes the technology an attractive consideration for future space applications.

  19. Memory for Recently Accessed Visual Attributes

    ERIC Educational Resources Information Center

    Jiang, Yuhong V.; Shupe, Joshua M.; Swallow, Khena M.; Tan, Deborah H.

    2016-01-01

    Recent reports have suggested that the attended features of an item may be rapidly forgotten once they are no longer relevant for an ongoing task (attribute amnesia). This finding relies on a surprise memory procedure that places high demands on declarative memory. We used intertrial priming to examine whether the representation of an item's…

  20. The Dynamics of Access to Groups in Working Memory

    ERIC Educational Resources Information Center

    Farrell, Simon; Lelievre, Anna

    2012-01-01

    The finding that participants leave a pause between groups when attempting serial recall of temporally grouped lists has been taken to indicate access to a hierarchical representation of the list in working memory. An alternative explanation is that the dynamics of serial recall solely reflect output (rather than memorial) processes, with the…

  1. Direct access inter-process shared memory

    SciTech Connect

    Brightwell, Ronald B; Pedretti, Kevin; Hudson, Trammell B

    2013-10-22

    A technique for directly sharing physical memory between processes executing on processor cores is described. The technique includes loading a plurality of processes into the physical memory for execution on a corresponding plurality of processor cores sharing the physical memory. An address space is mapped to each of the processes by populating a first entry in a top level virtual address table for each of the processes. The address space of each of the processes is cross-mapped into each of the processes by populating one or more subsequent entries of the top level virtual address table with the first entry in the top level virtual address table from other processes.

  2. Memory for recently accessed visual attributes.

    PubMed

    Jiang, Yuhong V; Shupe, Joshua M; Swallow, Khena M; Tan, Deborah H

    2016-08-01

    Recent reports have suggested that the attended features of an item may be rapidly forgotten once they are no longer relevant for an ongoing task (attribute amnesia). This finding relies on a surprise memory procedure that places high demands on declarative memory. We used intertrial priming to examine whether the representation of an item's identity is lost completely once it becomes task irrelevant. If so, then the identity of a target on one trial should not influence performance on the next trial. In 3 experiments, we replicated the finding that a target's identity is poorly recognized in a surprise memory test. However, we also observed location and identity repetition priming across consecutive trials. These data suggest that, although explicit recognition on a surprise memory test may be impaired, some information about a particular target's identity can be retained after it is no longer needed for a task. (PsycINFO Database Record

  3. Integrated semiconductor-magnetic random access memory system

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Blaes, Brent R. (Inventor)

    2001-01-01

    The present disclosure describes a non-volatile magnetic random access memory (RAM) system having a semiconductor control circuit and a magnetic array element. The integrated magnetic RAM system uses CMOS control circuit to read and write data magnetoresistively. The system provides a fast access, non-volatile, radiation hard, high density RAM for high speed computing.

  4. Emulating the Electrical Activity of the Neuron Using a Silicon Oxide RRAM Cell.

    PubMed

    Mehonic, Adnan; Kenyon, Anthony J

    2016-01-01

    In recent years, formidable effort has been devoted to exploring the potential of Resistive RAM (RRAM) devices to model key features of biological synapses. This is done to strengthen the link between neuro-computing architectures and neuroscience, bearing in mind the extremely low power consumption and immense parallelism of biological systems. Here we demonstrate the feasibility of using the RRAM cell to go further and to model aspects of the electrical activity of the neuron. We focus on the specific operational procedures required for the generation of controlled voltage transients, which resemble spike-like responses. Further, we demonstrate that RRAM devices are capable of integrating input current pulses over time to produce thresholded voltage transients. We show that the frequency of the output transients can be controlled by the input signal, and we relate recent models of the redox-based nanoionic resistive memory cell to two common neuronal models, the Hodgkin-Huxley (HH) conductance model and the leaky integrate-and-fire model. We employ a simplified circuit model to phenomenologically describe voltage transient generation. PMID:26941598

  5. Emulating the Electrical Activity of the Neuron Using a Silicon Oxide RRAM Cell

    PubMed Central

    Mehonic, Adnan; Kenyon, Anthony J.

    2016-01-01

    In recent years, formidable effort has been devoted to exploring the potential of Resistive RAM (RRAM) devices to model key features of biological synapses. This is done to strengthen the link between neuro-computing architectures and neuroscience, bearing in mind the extremely low power consumption and immense parallelism of biological systems. Here we demonstrate the feasibility of using the RRAM cell to go further and to model aspects of the electrical activity of the neuron. We focus on the specific operational procedures required for the generation of controlled voltage transients, which resemble spike-like responses. Further, we demonstrate that RRAM devices are capable of integrating input current pulses over time to produce thresholded voltage transients. We show that the frequency of the output transients can be controlled by the input signal, and we relate recent models of the redox-based nanoionic resistive memory cell to two common neuronal models, the Hodgkin-Huxley (HH) conductance model and the leaky integrate-and-fire model. We employ a simplified circuit model to phenomenologically describe voltage transient generation. PMID:26941598

  6. Scaling Linear Algebra Kernels using Remote Memory Access

    SciTech Connect

    Krishnan, Manoj Kumar; Lewis, Robert R.; Vishnu, Abhinav

    2010-09-13

    This paper describes the scalability of linear algebra kernels based on remote memory access approach. The current approach differs from the other linear algebra algorithms by the explicit use of shared memory and remote memory access (RMA) communication rather than message passing. It is suitable for clusters and scalable shared memory systems. The experimental results on large scale systems (Linux-Infiniband cluster, Cray XT) demonstrate consistent performance advantages over ScaLAPACK suite, the leading implementation of parallel linear algebra algorithms used today. For example, on a Cray XT4 for a matrix size of 102400, our RMA-based matrix multiplication achieved over 55 teraflops while ScaLAPACK’s pdgemm measured close to 42 teraflops on 10000 processes.

  7. A Cerebellar-model Associative Memory as a Generalized Random-access Memory

    NASA Technical Reports Server (NTRS)

    Kanerva, Pentti

    1989-01-01

    A versatile neural-net model is explained in terms familiar to computer scientists and engineers. It is called the sparse distributed memory, and it is a random-access memory for very long words (for patterns with thousands of bits). Its potential utility is the result of several factors: (1) a large pattern representing an object or a scene or a moment can encode a large amount of information about what it represents; (2) this information can serve as an address to the memory, and it can also serve as data; (3) the memory is noise tolerant--the information need not be exact; (4) the memory can be made arbitrarily large and hence an arbitrary amount of information can be stored in it; and (5) the architecture is inherently parallel, allowing large memories to be fast. Such memories can become important components of future computers.

  8. Conduction mechanism of a TaOx-based selector and its application in crossbar memory arrays

    NASA Astrophysics Data System (ADS)

    Wang, Ming; Zhou, Jiantao; Yang, Yuchao; Gaba, Siddharth; Liu, Ming; Lu, Wei D.

    2015-03-01

    The conduction mechanism of a Pd/TaOx/Ta/Pd selector device, which exhibits high non-linearity (~104) and excellent uniformity, has been systematically investigated by current-voltage-temperature characterization. The measurement and simulation results indicate two dominant processes of selector current at opposite biases: thermionic emission and tunnel emission. The current-voltage-temperature behaviors of the selector can be well explained using the Simmons' trapezoidal energy barrier model. The TaOx-based selective layer was further integrated with a HfO2-based resistive switching layer to form a selector-less resistive random access memory (RRAM) device structure. The integrated device showed a reliable resistive switching behavior with a high non-linearity (~5 × 103) in the low resistance state (LRS), which can effectively mitigate the sneak path current issue in RRAM crossbar arrays. Evaluations of a crossbar array based on these selector-less RRAM cells show less than 4% degradation in read margin for arrays up to 1 Mbit in size. These results highlight the different conduction mechanisms in selector device operation and will provide insight into continued design and optimization of RRAM arrays.

  9. Impact of program/erase operation on the performances of oxide-based resistive switching memory

    NASA Astrophysics Data System (ADS)

    Wang, Guoming; Long, Shibing; Yu, Zhaoan; Zhang, Meiyun; Li, Yang; Xu, Dinglin; Lv, Hangbing; Liu, Qi; Yan, Xiaobing; Wang, Ming; Xu, Xiaoxin; Liu, Hongtao; Yang, Baohe; Liu, Ming

    2015-02-01

    Further performance improvement is necessary for resistive random access memory (RRAM) to realize its commercialization. In this work, a novel pulse operation method is proposed to improve the performance of RRAM based on Ti/HfO2/Pt structure. In the DC voltage sweep of the RRAM device, the SET transition is abrupt under positive bias. If current sweep with positive bias is utilized in SET process, the SET switching will become gradual, so SET is current controlled. In the negative voltage sweep for RESET process, the change of current with applied voltage is gradual, so RESET is voltage controlled. Current sweep SET and voltage sweep RESET shows better controllability on the parameter variation. Considering the SET/RESET characteristics in DC sweep, in the corresponding pulse operation, the width and height of the pulse series can be adjusted to control the SET and RESET process, respectively. Our new method is different from the traditional pulse operation in which both the width and height of program/erase pulse are simply kept constant which would lead to unnecessary damage to the device. In our new method, in each program or erase operation, a series of pulses with the width/height gradually increased are made use of to fully finish the SET/RESET switching but no excessive stress is generated at the same time, so width/height-controlled accurate SET/RESET can be achieved. Through the operation, the uniformity and endurance of the RRAM device has been significantly improved.

  10. The role of the inserted layer in resistive random access memory device

    NASA Astrophysics Data System (ADS)

    Zhang, Dainan; Ma, Guokun; Zhang, Huaiwu; Tang, Xiaoli; Zhong, Zhiyong; Jie, Li; Su, Hua

    2016-07-01

    NiO resistive switching devices were fabricated by reactive DC magnetron sputtering at room temperature containing different inserted layers. From measurements, we demonstrated the filaments were made up by metal Co rather than the oxygen defect or other metal. A current jumping phenomenon in the SET process was observed, evidencing that the filament generating procedure was changed due to the inserted layers. In this process, we demonstrate the current jumping appeared in higher voltage region when the position of inserted layer was close to the bottom electrode. The I-V curves shifted to the positive direction as the thickness of inserted layer increasing. With the change of the number of inserted layers, SET voltages varied while the RESET voltage kept stable. According to the electrochemical metallization memory mechanism, detailed explanations on all the phenomena were addressed. This discovery is supposed of great potentials in the use of designing multi-layer RRAM devices.

  11. High performance of graphene oxide-doped silicon oxide-based resistance random access memory

    PubMed Central

    2013-01-01

    In this letter, a double active layer (Zr:SiO x /C:SiO x ) resistive switching memory device with outstanding performance is presented. Through current fitting, hopping conduction mechanism is found in both high-resistance state (HRS) and low-resistance state (LRS) of double active layer RRAM devices. By analyzing Raman and FTIR spectra, we observed that graphene oxide exists in C:SiO x layer. Compared with single Zr:SiO x layer structure, Zr:SiO x /C:SiO x structure has superior performance, including low operating current, improved uniformity in both set and reset processes, and satisfactory endurance characteristics, all of which are attributed to the double-layer structure and the existence of graphene oxide flakes formed by the sputter process. PMID:24261454

  12. Normally-off type nonvolatile static random access memory with perpendicular spin torque transfer-magnetic random access memory cells and smallest number of transistors

    NASA Astrophysics Data System (ADS)

    Tanaka, Chika; Abe, Keiko; Noguchi, Hiroki; Nomura, Kumiko; Ikegami, Kazutaka; Fujita, Shinobu

    2014-01-01

    In this paper, we present a novel nonvolatile-random access memory (RAM) cell design based on a “normally-off memory architecture” using a perpendicular spin torque transfer-magnetic random access memory (STT-MRAM) based on a four-transistors static random access memory (SRAM) in order to reduce the operating power of mobile processors. After the cell design concept and basic operation are proposed, a stable and reliable operation for read/write is confirmed by circuit simulation.

  13. Direct memory access transfer completion notification

    DOEpatents

    Archer, Charles J.; Blocksome, Michael A.; Parker, Jeffrey J.

    2011-02-15

    DMA transfer completion notification includes: inserting, by an origin DMA engine on an origin node in an injection first-in-first-out (`FIFO`) buffer, a data descriptor for an application message to be transferred to a target node on behalf of an application on the origin node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying a packet header for a completion notification packet; transferring, by the origin DMA engine to the target node, the message in dependence upon the data descriptor; sending, by the origin DMA engine, the completion notification packet to a local reception FIFO buffer using a local memory FIFO transfer operation; and notifying, by the origin DMA engine, the application that transfer of the message is complete in response to receiving the completion notification packet in the local reception FIFO buffer.

  14. Quantifying Locality in the Memory Access Patterns of HPCApplications

    SciTech Connect

    Weinberg, Jonathan; Snavely, Allan; McCracken, Michael O.; Strohmaier, Erich

    2005-07-25

    Several benchmarks for measuring memory performance of HPC systems along dimensions of spatial and temporal memory locality have recently been proposed. However, little is understood about the relationships of these benchmarks to real applications and to each other. In this paper, we propose a methodology for producing architecture-neutral characterizations of the spatial and temporal locality exhibited by the memory access patterns of applications. We demonstrate that the results track intuitive notions of spatial and temporal locality on several synthetic and application benchmarks. We employ the methodology to analyze the memory performance components of the HPC Challenge Benchmarks, the Apex-MAP benchmark, and their relationships to each other and other benchmarks and applications. We show that this analysis can be used to both increase understanding of the benchmarks and enhance their usefulness by mapping them, along with applications, to a 2-D space along axes of spatial and temporal locality.

  15. Kokkos: Enabling manycore performance portability through polymorphic memory access patterns

    SciTech Connect

    Carter Edwards, H.; Trott, Christian R.; Sunderland, Daniel

    2014-07-22

    The manycore revolution can be characterized by increasing thread counts, decreasing memory per thread, and diversity of continually evolving manycore architectures. High performance computing (HPC) applications and libraries must exploit increasingly finer levels of parallelism within their codes to sustain scalability on these devices. We found that a major obstacle to performance portability is the diverse and conflicting set of constraints on memory access patterns across devices. Contemporary portable programming models address manycore parallelism (e.g., OpenMP, OpenACC, OpenCL) but fail to address memory access patterns. The Kokkos C++ library enables applications and domain libraries to achieve performance portability on diverse manycore architectures by unifying abstractions for both fine-grain data parallelism and memory access patterns. In this paper we describe Kokkos’ abstractions, summarize its application programmer interface (API), present performance results for unit-test kernels and mini-applications, and outline an incremental strategy for migrating legacy C++ codes to Kokkos. Furthermore, the Kokkos library is under active research and development to incorporate capabilities from new generations of manycore architectures, and to address a growing list of applications and domain libraries.

  16. Kokkos: Enabling manycore performance portability through polymorphic memory access patterns

    DOE PAGES

    Carter Edwards, H.; Trott, Christian R.; Sunderland, Daniel

    2014-07-22

    The manycore revolution can be characterized by increasing thread counts, decreasing memory per thread, and diversity of continually evolving manycore architectures. High performance computing (HPC) applications and libraries must exploit increasingly finer levels of parallelism within their codes to sustain scalability on these devices. We found that a major obstacle to performance portability is the diverse and conflicting set of constraints on memory access patterns across devices. Contemporary portable programming models address manycore parallelism (e.g., OpenMP, OpenACC, OpenCL) but fail to address memory access patterns. The Kokkos C++ library enables applications and domain libraries to achieve performance portability on diversemore » manycore architectures by unifying abstractions for both fine-grain data parallelism and memory access patterns. In this paper we describe Kokkos’ abstractions, summarize its application programmer interface (API), present performance results for unit-test kernels and mini-applications, and outline an incremental strategy for migrating legacy C++ codes to Kokkos. Furthermore, the Kokkos library is under active research and development to incorporate capabilities from new generations of manycore architectures, and to address a growing list of applications and domain libraries.« less

  17. Integrated, nonvolatile, high-speed analog random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor)

    1994-01-01

    This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

  18. Magnet/Hall-Effect Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1991-01-01

    In proposed magnet/Hall-effect random-access memory (MHRAM), bits of data stored magnetically in Perm-alloy (or equivalent)-film memory elements and read out by using Hall-effect sensors to detect magnetization. Value of each bit represented by polarity of magnetization. Retains data for indefinite time or until data rewritten. Speed of Hall-effect sensors in MHRAM results in readout times of about 100 nanoseconds. Other characteristics include high immunity to ionizing radiation and storage densities of order 10(Sup6)bits/cm(Sup 2) or more.

  19. Paging memory from random access memory to backing storage in a parallel computer

    DOEpatents

    Archer, Charles J; Blocksome, Michael A; Inglett, Todd A; Ratterman, Joseph D; Smith, Brian E

    2013-05-21

    Paging memory from random access memory (`RAM`) to backing storage in a parallel computer that includes a plurality of compute nodes, including: executing a data processing application on a virtual machine operating system in a virtual machine on a first compute node; providing, by a second compute node, backing storage for the contents of RAM on the first compute node; and swapping, by the virtual machine operating system in the virtual machine on the first compute node, a page of memory from RAM on the first compute node to the backing storage on the second compute node.

  20. Performance Evaluation of Remote Memory Access (RMA) Programming on Shared Memory Parallel Computers

    NASA Technical Reports Server (NTRS)

    Jin, Hao-Qiang; Jost, Gabriele; Biegel, Bryan A. (Technical Monitor)

    2002-01-01

    The purpose of this study is to evaluate the feasibility of remote memory access (RMA) programming on shared memory parallel computers. We discuss different RMA based implementations of selected CFD application benchmark kernels and compare them to corresponding message passing based codes. For the message-passing implementation we use MPI point-to-point and global communication routines. For the RMA based approach we consider two different libraries supporting this programming model. One is a shared memory parallelization library (SMPlib) developed at NASA Ames, the other is the MPI-2 extensions to the MPI Standard. We give timing comparisons for the different implementation strategies and discuss the performance.

  1. 75 FR 14467 - In the Matter of: Certain Dynamic Random Access Memory Semiconductors and Products Containing...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-03-25

    ... COMMISSION In the Matter of: Certain Dynamic Random Access Memory Semiconductors and Products Containing Same, Including Memory Modules; Notice of Investigation AGENCY: U.S. International Trade Commission. ACTION... random access memory semiconductors and products containing same, including memory modules, by reason...

  2. 76 FR 73676 - Certain Dynamic Random Access Memory Devices, and Products Containing Same; Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-11-29

    ... COMMISSION Certain Dynamic Random Access Memory Devices, and Products Containing Same; Receipt of Complaint... complaint entitled In Re Certain Dynamic Random Access Memory Devices, and Products Containing Same, DN 2859... within the United States after importation of certain dynamic random access memory devices, and...

  3. 76 FR 80964 - Certain Dynamic Random Access Memory Devices, and Products Containing Same; Institution of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-12-27

    ... COMMISSION Certain Dynamic Random Access Memory Devices, and Products Containing Same; Institution of... States after importation of certain dynamic random access memory devices, and products containing same by... dynamic random access memory devices, and products containing same that infringe one or more of claims...

  4. On the mechanisms of cation injection in conducting bridge memories: The case of HfO2 in contact with noble metal anodes (Au, Cu, Ag)

    NASA Astrophysics Data System (ADS)

    Saadi, M.; Gonon, P.; Vallée, C.; Mannequin, C.; Grampeix, H.; Jalaguier, E.; Jomni, F.; Bsiesy, A.

    2016-03-01

    Resistance switching is studied in HfO2 as a function of the anode metal (Au, Cu, and Ag) in view of its application to resistive memories (resistive random access memories, RRAM). Current-voltage (I-V) and current-time (I-t) characteristics are presented. For Au anodes, resistance transition is controlled by oxygen vacancies (oxygen-based resistive random access memory, OxRRAM). For Ag anodes, resistance switching is governed by cation injection (Conducting Bridge random access memory, CBRAM). Cu anodes lead to an intermediate case. I-t experiments are shown to be a valuable tool to distinguish between OxRRAM and CBRAM behaviors. A model is proposed to explain the high-to-low resistance transition in CBRAMs. The model is based on the theory of low-temperature oxidation of metals (Cabrera-Mott theory). Upon electron injection, oxygen vacancies and oxygen ions are generated in the oxide. Oxygen ions are drifted to the anode, and an interfacial oxide is formed at the HfO2/anode interface. If oxygen ion mobility is low in the interfacial oxide, a negative space charge builds-up at the HfO2/oxide interface. This negative space charge is the source of a strong electric field across the interfacial oxide thickness, which pulls out cations from the anode (CBRAM case). Inversely, if oxygen ions migration through the interfacial oxide is important (or if the anode does not oxidize such as Au), bulk oxygen vacancies govern resistance transition (OxRRAM case).

  5. Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order

    NASA Technical Reports Server (NTRS)

    Wulf, William A. (Inventor); McKee, Sally A. (Inventor); Klenke, Robert (Inventor); Schwab, Andrew J. (Inventor); Moyer, Stephen A. (Inventor); Aylor, James (Inventor); Hitchcock, Charles Young (Inventor)

    2000-01-01

    A data processing system is disclosed which comprises a data processor and memory control device for controlling the access of information from the memory. The memory control device includes temporary storage and decision ability for determining what order to execute the memory accesses. The compiler detects the requirements of the data processor and selects the data to stream to the memory control device which determines a memory access order. The order in which to access said information is selected based on the location of information stored in the memory. The information is repeatedly accessed from memory and stored in the temporary storage until all streamed information is accessed. The information is stored until required by the data processor. The selection of the order in which to access information maximizes bandwidth and decreases the retrieval time.

  6. A current access, self-structured, multilayered bubble domain memory

    NASA Technical Reports Server (NTRS)

    Stermer, R. L., Jr.; Kamin, M.; Tolman, C. H.; Torok, E. J.

    1980-01-01

    Preliminary experimental results are reported on a self-structured, multilayer bubble memory with buried data layer. Stripe domains are used to move carrier bubbles by magnetostatic coupling. An expression is derived for that coupling as a function of thickness of the GGG separation layer. Experimental values of coupling are given as a function of bias field. An expression for stripe curvature as a function of bias field is derived. The performance of seven different current access stripe propagation circuits is reported.

  7. Nonvolatile GaAs Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.; Stadler, Henry L.; Wu, Jiin-Chuan

    1994-01-01

    Proposed random-access integrated-circuit electronic memory offers nonvolatile magnetic storage. Bits stored magnetically and read out with Hall-effect sensors. Advantages include short reading and writing times and high degree of immunity to both single-event upsets and permanent damage by ionizing radiation. Use of same basic material for both transistors and sensors simplifies fabrication process, with consequent benefits in increased yield and reduced cost.

  8. /TiN Resistive RAM (RRAM) Cells

    NASA Astrophysics Data System (ADS)

    Chen, Z. X.; Fang, Z.; Wang, Y.; Yang, Y.; Kamath, A.; Wang, X. P.; Singh, N.; Lo, G.-Q.; Kwong, D.-L.; Wu, Y. H.

    2014-11-01

    We present a study of Ni silicide as the bottom electrode in HfO2-based resistive random-access memory cells. Various silicidation conditions were used for each device, yielding different Ni concentrations within the electrode. A higher concentration of Ni in the bottom electrode was found to cause a parasitic SET operation during certain RESET operation cycles, being attributed to field-assisted Ni cation migration creating a Ni filament. As such, the RESET is affected unless an appropriate RESET voltage is used. Bottom electrodes with lower concentrations of Ni were able to switch at ultralow currents (RESET current <1 nA) by using a low compliance current (<500 nA). The low current is attributed to the tunneling barrier formed by the native SiO2 at the Ni silicide/HfO2 interface.

  9. If memory serves, will language? Later verbal accessibility of early memories.

    PubMed

    Bauer, P J; Kroupina, M G; Schwade, J A; Dropik, P L; Wewerka, S S

    1998-01-01

    Of major interest to those concerned with early mnemonic process and function is the question of whether early memories likely encoded without the benefit of language later are accessible to verbal report. In the context of a controlled laboratory study, we examined this question in children who were 16 and 20 months at the time of exposure to specific target events and who subsequently were tested for their memories of the events after a delay of either 6 or 12 months (at 22-32 months) and then again at 3 years. At the first delayed-recall test, children evidenced memory both nonverbally and verbally. Nonverbal mnemonic expression was related to age at the time of test; verbal mnemonic expression was related to verbal fluency at the time of test. At the second delayed-recall test, children evidenced continued accessibility of their early memories. Verbal mnemonic expression was related to previous mnemonic expression, both nonverbal and verbal, each of which contributed unique variance. The relevance of these findings on memory for controlled laboratory events for issues of memory for traumatic experiences is discussed. PMID:9886220

  10. Point contact resistive switching memory based on self-formed interface of Al/ITO.

    PubMed

    Li, Qiuhong; Qiu, Linjun; Wei, Xianhua; Dai, Bo; Zeng, Huizhong

    2016-01-01

    Point contact resistive switching random access memory (RRAM) has been achieved by directly sputtering Al electrodes on indium tin oxide (ITO) conductive glasses. The room-temperature deposited Al/ITO shows an asymmetrical bipolar resistive switching (BRS) behavior after a process of initialization which induces a stable high resistive state (HRS). It might be caused by the in-situ formation of an ultra-thin layer (≈4 nm) at the interface. By comparison, the Al/ITO device after vacuum annealed exhibits typical symmetrical BRS without an initiation or electroforming process. This can be ascribed to the ex-situ thickening of the interfacial layer (≈9.2 nm) to achieve the stable HRS after heat treatment. This work suggests that the self-formed interface of active Al electrode/ITO would provide the simplest geometry to construct RRAM. PMID:27383005

  11. Detection of the insulating gap and conductive filament growth direction in resistive memories

    NASA Astrophysics Data System (ADS)

    Yalon, E.; Karpov, I.; Karpov, V.; Riess, I.; Kalaev, D.; Ritter, D.

    2015-09-01

    Filament growth is a key aspect in the operation of bipolar resistive random access memory (RRAM) devices, yet there are conflicting reports in the literature on the direction of growth of conductive filaments in valence change RRAM devices. We report here that an insulating gap between the filament and the semiconductor electrode can be detected by the metal-insulator-semiconductor bipolar transistor structure, and thus provide information on the filament growth direction. Using this technique, we show how voltage polarity and electrode chemistry control the filament growth direction during electro-forming. The experimental results and the nature of a gap between the filament and an electrode are discussed in light of possible models of filament formation.

  12. Study of multi-level characteristics for 3D vertical resistive switching memory.

    PubMed

    Bai, Yue; Wu, Huaqiang; Wu, Riga; Zhang, Ye; Deng, Ning; Yu, Zhiping; Qian, He

    2014-07-22

    Three-dimensional (3D) integration and multi-level cell (MLC) are two attractive technologies to achieve ultra-high density for mass storage applications. In this work, a three-layer 3D vertical AlOδ/Ta2O5-x/TaOy resistive random access memories were fabricated and characterized. The vertical cells in three layers show good uniformity and high performance (e.g. >1000X HRS/LRS windows, >10(10) endurance cycles, >10(4) s retention times at 125°C). Meanwhile, four level MLC is demonstrated with two operation strategies, current controlled scheme (CCS) and voltage controlled scheme (VCS). The switching mechanism of 3D vertical RRAM cells is studied based on temperature-dependent transport characteristics. Furthermore, the applicability of CCS and VCS in 3D vertical RRAM array is compared using resistor network circuit simulation.

  13. Point contact resistive switching memory based on self-formed interface of Al/ITO

    PubMed Central

    Li, Qiuhong; Qiu, Linjun; Wei, Xianhua; Dai, Bo; Zeng, Huizhong

    2016-01-01

    Point contact resistive switching random access memory (RRAM) has been achieved by directly sputtering Al electrodes on indium tin oxide (ITO) conductive glasses. The room-temperature deposited Al/ITO shows an asymmetrical bipolar resistive switching (BRS) behavior after a process of initialization which induces a stable high resistive state (HRS). It might be caused by the in-situ formation of an ultra-thin layer (≈4 nm) at the interface. By comparison, the Al/ITO device after vacuum annealed exhibits typical symmetrical BRS without an initiation or electroforming process. This can be ascribed to the ex-situ thickening of the interfacial layer (≈9.2 nm) to achieve the stable HRS after heat treatment. This work suggests that the self-formed interface of active Al electrode/ITO would provide the simplest geometry to construct RRAM. PMID:27383005

  14. Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory

    PubMed Central

    Bai, Yue; Wu, Huaqiang; Wu, Riga; Zhang, Ye; Deng, Ning; Yu, Zhiping; Qian, He

    2014-01-01

    Three-dimensional (3D) integration and multi-level cell (MLC) are two attractive technologies to achieve ultra-high density for mass storage applications. In this work, a three-layer 3D vertical AlOδ/Ta2O5-x/TaOy resistive random access memories were fabricated and characterized. The vertical cells in three layers show good uniformity and high performance (e.g. >1000X HRS/LRS windows, >1010 endurance cycles, >104 s retention times at 125°C). Meanwhile, four level MLC is demonstrated with two operation strategies, current controlled scheme (CCS) and voltage controlled scheme (VCS). The switching mechanism of 3D vertical RRAM cells is studied based on temperature-dependent transport characteristics. Furthermore, the applicability of CCS and VCS in 3D vertical RRAM array is compared using resistor network circuit simulation. PMID:25047906

  15. Point contact resistive switching memory based on self-formed interface of Al/ITO

    NASA Astrophysics Data System (ADS)

    Li, Qiuhong; Qiu, Linjun; Wei, Xianhua; Dai, Bo; Zeng, Huizhong

    2016-07-01

    Point contact resistive switching random access memory (RRAM) has been achieved by directly sputtering Al electrodes on indium tin oxide (ITO) conductive glasses. The room-temperature deposited Al/ITO shows an asymmetrical bipolar resistive switching (BRS) behavior after a process of initialization which induces a stable high resistive state (HRS). It might be caused by the in-situ formation of an ultra-thin layer (≈4 nm) at the interface. By comparison, the Al/ITO device after vacuum annealed exhibits typical symmetrical BRS without an initiation or electroforming process. This can be ascribed to the ex-situ thickening of the interfacial layer (≈9.2 nm) to achieve the stable HRS after heat treatment. This work suggests that the self-formed interface of active Al electrode/ITO would provide the simplest geometry to construct RRAM.

  16. Vortex-Core Reversal Dynamics: Towards Vortex Random Access Memory

    NASA Astrophysics Data System (ADS)

    Kim, Sang-Koog

    2011-03-01

    An energy-efficient, ultrahigh-density, ultrafast, and nonvolatile solid-state universal memory is a long-held dream in the field of information-storage technology. The magnetic random access memory (MRAM) along with a spin-transfer-torque switching mechanism is a strong candidate-means of realizing that dream, given its nonvolatility, infinite endurance, and fast random access. Magnetic vortices in patterned soft magnetic dots promise ground-breaking applications in information-storage devices, owing to the very stable twofold ground states of either their upward or downward core magnetization orientation and plausible core switching by in-plane alternating magnetic fields or spin-polarized currents. However, two technologically most important but very challenging issues --- low-power recording and reliable selection of each memory cell with already existing cross-point architectures --- have not yet been resolved for the basic operations in information storage, that is, writing (recording) and readout. Here, we experimentally demonstrate a magnetic vortex random access memory (VRAM) in the basic cross-point architecture. This unique VRAM offers reliable cell selection and low-power-consumption control of switching of out-of-plane core magnetizations using specially designed rotating magnetic fields generated by two orthogonal and unipolar Gaussian-pulse currents along with optimized pulse width and time delay. Our achievement of a new device based on a new material, that is, a medium composed of patterned vortex-state disks, together with the new physics on ultrafast vortex-core switching dynamics, can stimulate further fruitful research on MRAMs that are based on vortex-state dot arrays.

  17. Geometric conductive filament confinement by nanotips for resistive switching of HfO2-RRAM devices with high performance

    PubMed Central

    Niu, Gang; Calka, Pauline; Auf der Maur, Matthias; Santoni, Francesco; Guha, Subhajit; Fraschke, Mirko; Hamoumou, Philippe; Gautier, Brice; Perez, Eduardo; Walczyk, Christian; Wenger, Christian; Di Carlo, Aldo; Alff, Lambert; Schroeder, Thomas

    2016-01-01

    Filament-type HfO2-based RRAM has been considered as one of the most promising candidates for future non-volatile memories. Further improvement of the stability, particularly at the “OFF” state, of such devices is mainly hindered by resistance variation induced by the uncontrolled oxygen vacancies distribution and filament growth in HfO2 films. We report highly stable endurance of TiN/Ti/HfO2/Si-tip RRAM devices using a CMOS compatible nanotip method. Simulations indicate that the nanotip bottom electrode provides a local confinement for the electrical field and ionic current density; thus a nano-confinement for the oxygen vacancy distribution and nano-filament location is created by this approach. Conductive atomic force microscopy measurements confirm that the filaments form only on the nanotip region. Resistance switching by using pulses shows highly stable endurance for both ON and OFF modes, thanks to the geometric confinement of the conductive path and filament only above the nanotip. This nano-engineering approach opens a new pathway to realize forming-free RRAM devices with improved stability and reliability. PMID:27181525

  18. A flexible organic resistance memory device for wearable biomedical applications

    NASA Astrophysics Data System (ADS)

    Cai, Yimao; Tan, Jing; YeFan, Liu; Lin, Min; Huang, Ru

    2016-07-01

    Parylene is a Food and Drug Administration (FDA)-approved material which can be safely used within the human body and it is also offers chemically inert and flexible merits. Here, we present a flexible parylene-based organic resistive random access memory (RRAM) device suitable for wearable biomedical application. The proposed device is fabricated through standard lithography and pattern processes at room temperature, exhibiting the feasibility of integration with CMOS circuits. This organic RRAM device offers a high storage window (>104), superior retention ability and immunity to disturbing. In addition, brilliant mechanical and electrical stabilities of this device are demonstrated when under harsh bending (bending cycle >500, bending radius <10 mm). Finally, the underlying mechanism for resistance switching of this kind of device is discussed, and metallic conducting filament formation and annihilation related to oxidization/redox of Al and Al anions migrating in the parylene layer can be attributed to resistance switching in this device. These advantages reveal the significant potential of parylene-based flexible RRAM devices for wearable biomedical applications.

  19. A flexible organic resistance memory device for wearable biomedical applications.

    PubMed

    Cai, Yimao; Tan, Jing; YeFan, Liu; Lin, Min; Huang, Ru

    2016-07-01

    Parylene is a Food and Drug Administration (FDA)-approved material which can be safely used within the human body and it is also offers chemically inert and flexible merits. Here, we present a flexible parylene-based organic resistive random access memory (RRAM) device suitable for wearable biomedical application. The proposed device is fabricated through standard lithography and pattern processes at room temperature, exhibiting the feasibility of integration with CMOS circuits. This organic RRAM device offers a high storage window (>10(4)), superior retention ability and immunity to disturbing. In addition, brilliant mechanical and electrical stabilities of this device are demonstrated when under harsh bending (bending cycle >500, bending radius <10 mm). Finally, the underlying mechanism for resistance switching of this kind of device is discussed, and metallic conducting filament formation and annihilation related to oxidization/redox of Al and Al anions migrating in the parylene layer can be attributed to resistance switching in this device. These advantages reveal the significant potential of parylene-based flexible RRAM devices for wearable biomedical applications. PMID:27242345

  20. Complex dynamics of semantic memory access in reading.

    PubMed

    Baggio, Giosué; Fonseca, André

    2012-02-01

    Understanding a word in context relies on a cascade of perceptual and conceptual processes, starting with modality-specific input decoding, and leading to the unification of the word's meaning into a discourse model. One critical cognitive event, turning a sensory stimulus into a meaningful linguistic sign, is the access of a semantic representation from memory. Little is known about the changes that activating a word's meaning brings about in cortical dynamics. We recorded the electroencephalogram (EEG) while participants read sentences that could contain a contextually unexpected word, such as 'cold' in 'In July it is very cold outside'. We reconstructed trajectories in phase space from single-trial EEG time series, and we applied three nonlinear measures of predictability and complexity to each side of the semantic access boundary, estimated as the onset time of the N400 effect evoked by critical words. Relative to controls, unexpected words were associated with larger prediction errors preceding the onset of the N400. Accessing the meaning of such words produced a phase transition to lower entropy states, in which cortical processing becomes more predictable and more regular. Our study sheds new light on the dynamics of information flow through interfaces between sensory and memory systems during language processing.

  1. Administering an epoch initiated for remote memory access

    DOEpatents

    Blocksome, Michael A; Miller, Douglas R

    2014-03-18

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  2. Administering an epoch initiated for remote memory access

    DOEpatents

    Blocksome, Michael A; Miller, Douglas R

    2012-10-23

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  3. Administering an epoch initiated for remote memory access

    DOEpatents

    Blocksome, Michael A.; Miller, Douglas R.

    2013-01-01

    Methods, systems, and products are disclosed for administering an epoch initiated for remote memory access that include: initiating, by an origin application messaging module on an origin compute node, one or more data transfers to a target compute node for the epoch; initiating, by the origin application messaging module after initiating the data transfers, a closing stage for the epoch, including rejecting any new data transfers after initiating the closing stage for the epoch; determining, by the origin application messaging module, whether the data transfers have completed; and closing, by the origin application messaging module, the epoch if the data transfers have completed.

  4. Resistance controllability and variability improvement in a TaO{sub x}-based resistive memory for multilevel storage application

    SciTech Connect

    Prakash, A. E-mail: amit.knp02@gmail.com Song, J.; Hwang, H. E-mail: amit.knp02@gmail.com; Deleruyelle, D.; Bocquet, M.

    2015-06-08

    In order to obtain reliable multilevel cell (MLC) characteristics, resistance controllability between the different resistance levels is required especially in resistive random access memory (RRAM), which is prone to resistance variability mainly due to its intrinsic random nature of defect generation and filament formation. In this study, we have thoroughly investigated the multilevel resistance variability in a TaO{sub x}-based nanoscale (<30 nm) RRAM operated in MLC mode. It is found that the resistance variability not only depends on the conductive filament size but also is a strong function of oxygen vacancy concentration in it. Based on the gained insights through experimental observations and simulation, it is suggested that forming thinner but denser conductive filament may greatly improve the temporal resistance variability even at low operation current despite the inherent stochastic nature of resistance switching process.

  5. Efficient Memory Access with NumPy Global Arrays using Local Memory Access

    SciTech Connect

    Daily, Jeffrey A.; Berghofer, Dan C.

    2013-08-03

    This paper discusses the work completed working with Global Arrays of data on distributed multi-computer systems and improving their performance. The tasks completed were done at Pacific Northwest National Laboratory in the Science Undergrad Laboratory Internship program in the summer of 2013 for the Data Intensive Computing Group in the Fundamental and Computational Sciences DIrectorate. This work was done on the Global Arrays Toolkit developed by this group. This toolkit is an interface for programmers to more easily create arrays of data on networks of computers. This is useful because scientific computation is often done on large amounts of data sometimes so large that individual computers cannot hold all of it. This data is held in array form and can best be processed on supercomputers which often consist of a network of individual computers doing their computation in parallel. One major challenge for this sort of programming is that operations on arrays on multiple computers is very complex and an interface is needed so that these arrays seem like they are on a single computer. This is what global arrays does. The work done here is to use more efficient operations on that data that requires less copying of data to be completed. This saves a lot of time because copying data on many different computers is time intensive. The way this challenge was solved is when data to be operated on with binary operations are on the same computer, they are not copied when they are accessed. When they are on separate computers, only one set is copied when accessed. This saves time because of less copying done although more data access operations were done.

  6. Overview of emerging nonvolatile memory technologies.

    PubMed

    Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  7. Overview of emerging nonvolatile memory technologies

    PubMed Central

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  8. Spin-Hall-assisted magnetic random access memory

    SciTech Connect

    Brink, A. van den Swagten, H. J. M.; Koopmans, B.; Cosemans, S.; Manfrini, M.; Van Roy, W.; Min, T.; Cornelissen, S.; Vaysset, A.

    2014-01-06

    We propose a write scheme for perpendicular spin-transfer torque magnetoresistive random-access memory that significantly reduces the required tunnel current density and write energy. A sub-nanosecond in-plane polarized spin current pulse is generated using the spin-Hall effect, disturbing the stable magnetic state. Subsequent switching using out-of-plane polarized spin current becomes highly efficient. Through evaluation of the Landau-Lifshitz-Gilbert equation, we quantitatively assess the viability of this write scheme for a wide range of system parameters. A typical example shows an eight-fold reduction in tunnel current density, corresponding to a fifty-fold reduction in write energy, while maintaining a 1 ns write time.

  9. Complementary resistive switching behavior for conductive bridge random access memory

    NASA Astrophysics Data System (ADS)

    Zheng, Hao-Xuan; Chang, Ting-Chang; Chang, Kuan-Chang; Tsai, Tsung-Ming; Shih, Chih-Cheng; Zhang, Rui; Chen, Kai-Huang; Wang, Ming-Hui; Zheng, Jin-Cheng; Lo, Ikai; Wu, Cheng-Hsien; Tseng, Yi-Ting; Sze, Simon M.

    2016-06-01

    In this study, a structure of Pt/Cu18Si12O70/TiN has been investigated. By co-sputtering the Cu and SiO2 targets in the switching layer, we can measure the operation mechanism of complementary resistive switching (CRS). This differs from conventional conductive bridge random access memory (CBRAM) that tends to use Cu electrodes rather than Cu18Si12O70. By changing the voltage and compliance current, we can control device operating characteristics. Because Cu distributes differently in the device depending on this setting, the operating end can be located at either the top or bottom electrode. Device current-voltage (I-V) curves are used to demonstrate that the CRS in the CBRAM device is a double-electrode operation.

  10. Taxing Working Memory during Retrieval of Emotional Memories Does Not Reduce Memory Accessibility When Cued with Reminders

    PubMed Central

    van Schie, Kevin; Engelhard, Iris M.; van den Hout, Marcel A.

    2015-01-01

    Earlier studies have shown that when individuals recall an emotional memory while simultaneously doing a demanding dual-task [e.g., playing Tetris, mental arithmetic, making eye movements (EM)], this reduces self-reported vividness and emotionality of the memory. These effects have been found up to 1 week later, but have largely been confined to self-report ratings. This study examined whether this dual-tasking intervention reduces memory performance (i.e., accessibility of emotional memories). Undergraduates (N = 60) studied word-image pairs and rated the retrieved image on vividness and emotionality when cued with the word. Then they viewed the cues and recalled the images with or without making EM. Finally, they re-rated the images on vividness and emotionality. Additionally, fragments from images from all conditions were presented and participants identified which fragment was paired earlier with which cue. Findings showed no effect of the dual-task manipulation on self-reported ratings and latency responses. Several possible explanations for the lack of effects are discussed, but the cued recall procedure in our experiment seems to explain the absence of effects best. The study demonstrates boundaries to the effects of the “dual-tasking” procedure. PMID:25729370

  11. 75 FR 44989 - In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-07-30

    ... December 10, 2008, based on a complaint filed by Rambus, Inc. of Los Altos, California (``Rambus''). 73 FR... COMMISSION In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory... chips having synchronous dynamic random access memory controllers and product containing the same...

  12. 78 FR 25767 - Certain Static Random Access Memories and Products Containing Same; Commission Determination To...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-05-02

    ..., California (``Cypress''). 76 FR 45295 (July 28, 2011). The complaint alleged violations of section 337 of the... COMMISSION Certain Static Random Access Memories and Products Containing Same; Commission Determination To..., and the sale within the United States after importation of certain static random access memories...

  13. Accessibility versus Accuracy in Retrieving Spatial Memory: Evidence for Suboptimal Assumed Headings

    ERIC Educational Resources Information Center

    Yerramsetti, Ashok; Marchette, Steven A.; Shelton, Amy L.

    2013-01-01

    Orientation dependence in spatial memory has often been interpreted in terms of accessibility: Object locations are encoded relative to a reference orientation that affords the most accurate access to spatial memory. An open question, however, is whether people naturally use this "preferred" orientation whenever recalling the space. We…

  14. Optimizing NEURON Simulation Environment Using Remote Memory Access with Recursive Doubling on Distributed Memory Systems.

    PubMed

    Shehzad, Danish; Bozkuş, Zeki

    2016-01-01

    Increase in complexity of neuronal network models escalated the efforts to make NEURON simulation environment efficient. The computational neuroscientists divided the equations into subnets amongst multiple processors for achieving better hardware performance. On parallel machines for neuronal networks, interprocessor spikes exchange consumes large section of overall simulation time. In NEURON for communication between processors Message Passing Interface (MPI) is used. MPI_Allgather collective is exercised for spikes exchange after each interval across distributed memory systems. The increase in number of processors though results in achieving concurrency and better performance but it inversely affects MPI_Allgather which increases communication time between processors. This necessitates improving communication methodology to decrease the spikes exchange time over distributed memory systems. This work has improved MPI_Allgather method using Remote Memory Access (RMA) by moving two-sided communication to one-sided communication, and use of recursive doubling mechanism facilitates achieving efficient communication between the processors in precise steps. This approach enhanced communication concurrency and has improved overall runtime making NEURON more efficient for simulation of large neuronal network models. PMID:27413363

  15. Optimizing NEURON Simulation Environment Using Remote Memory Access with Recursive Doubling on Distributed Memory Systems

    PubMed Central

    Bozkuş, Zeki

    2016-01-01

    Increase in complexity of neuronal network models escalated the efforts to make NEURON simulation environment efficient. The computational neuroscientists divided the equations into subnets amongst multiple processors for achieving better hardware performance. On parallel machines for neuronal networks, interprocessor spikes exchange consumes large section of overall simulation time. In NEURON for communication between processors Message Passing Interface (MPI) is used. MPI_Allgather collective is exercised for spikes exchange after each interval across distributed memory systems. The increase in number of processors though results in achieving concurrency and better performance but it inversely affects MPI_Allgather which increases communication time between processors. This necessitates improving communication methodology to decrease the spikes exchange time over distributed memory systems. This work has improved MPI_Allgather method using Remote Memory Access (RMA) by moving two-sided communication to one-sided communication, and use of recursive doubling mechanism facilitates achieving efficient communication between the processors in precise steps. This approach enhanced communication concurrency and has improved overall runtime making NEURON more efficient for simulation of large neuronal network models. PMID:27413363

  16. Computer vector multiprocessing control with multiple access memory and priority conflict resolution method

    SciTech Connect

    Chen, S.S.; Schiffleger, A.J.

    1990-02-13

    This patent describes a multiprocessor memory system. It comprises: a central memory comprised of a plurality of independently addressable memory banks organized into a plurality of sections each accessible through a plurality of access paths; a plurality of processing machines; each of the processing machine including a plurality of ports for generating memory references to any one of the central memory sections; and conflict resolution means interfacing each of the ports to each of the central memory sections through the central memory access paths. The resolution means for receiving references from the ports and coordinating and controlling the procession of the references along to the access paths. The conflict resolution means comprising a plurality of conflict resolution circuits corresponding in number to the memory sections, each of the circuits receiving the references to its corresponding section from any one of the ports and selectively conveying the references to the access paths for the corresponding section. The circuits each including; means for checking the readiness of the memory banks to be referenced and holding a reference to a busy one of the banks until the bank is ready to be referenced; means for detecting when more than one of the references is pending to the same bank simultaneously and holding all but one of the simultaneously pending references; and means communicating with the ports and the other of the conflict resolution circuits to cause one of the ports referencing the memory to suspend generation of further references when a reference from the referencing port is being held.

  17. Working memory capacity and retrieval limitations from long-term memory: an examination of differences in accessibility.

    PubMed

    Unsworth, Nash; Spillers, Gregory J; Brewer, Gene A

    2012-01-01

    In two experiments, the locus of individual differences in working memory capacity and long-term memory recall was examined. Participants performed categorical cued and free recall tasks, and individual differences in the dynamics of recall were interpreted in terms of a hierarchical-search framework. The results from this study are in accordance with recent theorizing suggesting a strong relation between working memory capacity and retrieval from long-term memory. Furthermore, the results also indicate that individual differences in categorical recall are partially due to differences in accessibility. In terms of accessibility of target information, two important factors drive the difference between high- and low-working-memory-capacity participants. Low-working-memory-capacity participants fail to utilize appropriate retrieval strategies to access cues, and they also have difficulty resolving cue overload. Thus, when low-working-memory-capacity participants were given specific cues that activated a smaller set of potential targets, their recall performance was the same as that of high-working-memory-capacity participants. PMID:22800472

  18. Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests

    DOEpatents

    Gala, Alan; Ohmacht, Martin

    2014-09-02

    A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.

  19. Viable chemical approach for patterning nanoscale magnetoresistive random access memory

    SciTech Connect

    Kim, Taeseung; Kim, Younghee; Chen, Jack Kun-Chieh; Chang, Jane P.

    2015-03-15

    A reactive ion etching process with alternating Cl{sub 2} and H{sub 2} exposures has been shown to chemically etch CoFe film that is an integral component in magnetoresistive random access memory (MRAM). Starting with systematic thermodynamic calculations assessing various chemistries and reaction pathways leading to the highest possible vapor pressure of the etch products reactions, the potential chemical combinations were verified by etch rate investigation and surface chemistry analysis in plasma treated CoFe films. An ∼20% enhancement in etch rate was observed with the alternating use of Cl{sub 2} and H{sub 2} plasmas, in comparison with the use of only Cl{sub 2} plasma. This chemical combination was effective in removing metal chloride layers, thus maintaining the desired magnetic properties of the CoFe films. Scanning electron microscopy equipped with energy-dispersive x-ray spectroscopy showed visually and spectroscopically that the metal chloride layers generated by Cl{sub 2} plasma were eliminated with H{sub 2} plasma to yield a clean etch profile. This work suggests that the selected chemistries can be used to etch magnetic metal alloys with a smooth etch profile and this general strategy can be applied to design chemically based etch processes to enable the fabrication of highly integrated nanoscale MRAM devices.

  20. Flexible memristive memory array on plastic substrates.

    PubMed

    Kim, Seungjun; Jeong, Hu Young; Kim, Sung Kyu; Choi, Sung-Yool; Lee, Keon Jae

    2011-12-14

    The demand for flexible electronic systems such as wearable computers, E-paper, and flexible displays has recently increased due to their advantages over present rigid electronic systems. Flexible memory is an essential part of electronic systems for data processing, storage, and communication and thus a key element to realize such flexible electronic systems. Although several emerging memory technologies, including resistive switching memory, have been proposed, the cell-to-cell interference issue has to be overcome for flexible and high performance nonvolatile memory applications. This paper describes the development of NOR type flexible resistive random access memory (RRAM) with a one transistor-one memristor structure (1T-1M). By integration of a high-performance single crystal silicon transistor with a titanium oxide based memristor, random access to memory cells on flexible substrates was achieved without any electrical interference from adjacent cells. The work presented here can provide a new approach to high-performance nonvolatile memory for flexible electronic applications. PMID:22026616

  1. Multiple core computer processor with globally-accessible local memories

    DOEpatents

    Shalf, John; Donofrio, David; Oliker, Leonid

    2016-09-20

    A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

  2. 76 FR 45295 - In the Matter of Certain Static Random Access Memories and Products Containing Same; Notice of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-07-28

    ... COMMISSION In the Matter of Certain Static Random Access Memories and Products Containing Same; Notice of... importation, and the sale within the United States after importation of certain static random access memories... importation of certain static random access memories and products containing same that infringe one or more...

  3. Adult Age Differences in Accessing and Retrieving Information from Long-Term Memory.

    ERIC Educational Resources Information Center

    Petros, Thomas V.; And Others

    1983-01-01

    Investigated adult age differences in accessing and retrieving information from long-term memory. Results showed that older adults (N=26) were slower than younger adults (N=35) at feature extraction, lexical access, and accessing category information. The age deficit was proportionally greater when retrieval of category information was required.…

  4. Optimization of Pit Depth for Concurrent Read Only Memory-Random Access Memory Optical Disk

    NASA Astrophysics Data System (ADS)

    Aoyama, Nobuhide; Yamashita, Satoshi; Kunimatsu, Yasukiyo; Hosokawa, Tetsuo; Morimoto, Yasuaki; Suenaga, Masashi; Yoshihiro, Masafumi; Shimazaki, Katsusuke

    2004-06-01

    We have studied a concurrent read only memory-random access memory (ROM-RAM) optical disk system without laser feedback by optimizing pit depth. When the pit depth was 47 nm (optical depth about 1/11 λ) and the pit width 0.45 μm, about 8% jitter in both pit and magneto-optical (MO) signals was obtained with a 785 nm wavelength laser diode and 0.55 NA objective lens by employing magnetic-field-modulation (MFM) MO recording. Both pit data and MO data were recorded with eight to fourteen modulation (EFM) code with a minimum mark length of 0.83 μm and a track pitch of 1.6 μm and thus the areal density is comparable to 1.3 GB for φ 120 mm single sided disk. By the optimization of the pit depth, sufficient system margins for practical use were obtained without laser feed back for the simultaneous reproduction of both pit and MO signals.

  5. Improving resistance uniformity and endurance of resistive switching memory by accurately controlling the stress time of pulse program operation

    NASA Astrophysics Data System (ADS)

    Wang, Guoming; Long, Shibing; Yu, Zhaoan; Zhang, Meiyun; Ye, Tianchun; Li, Yang; Xu, Dinglin; Lv, Hangbing; Liu, Qi; Wang, Ming; Xu, Xiaoxin; Liu, Hongtao; Yang, Baohe; Suñé, Jordi; Liu, Ming

    2015-03-01

    In this letter, the impact of stress time of pulse program operation on the resistance uniformity and endurance of resistive random access memory (RRAM) is investigated. A width-adjusting pulse operation (WAPO) method which can accurately setup and measure switching time is proposed for improving the uniformity and endurance of RRAM. Different from the traditional single pulse operation (TSPO) method in which only one wide pulse is applied in each switching cycle, WAPO method utilizes a series of pulses with the width increased gradually until a set or reset switching process is completely finished and no excessive stress is produced. Our program/erase (P/E) method can exactly control the switching time and the final resistance and can significantly improve the uniformity, stability, and endurance of RRAM device. Improving resistance uniformity by WAPO compared with TSPO method is explained through the interdependence between resistance state and switching time. The endurance improvement by WAPO operation stems from the effective avoidance of the overstress-induced progressive-breakdown and even hard-breakdown to the conductive soft-breakdown path.

  6. Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes.

    PubMed

    Bai, Yue; Wu, Huaqiang; Wang, Kun; Wu, Riga; Song, Lin; Li, Tianyi; Wang, Jiangtao; Yu, Zhiping; Qian, He

    2015-01-01

    There are two critical challenges which determine the array density of 3D RRAM: 1) the scaling limit in both horizontal and vertical directions; 2) the integration of selector devices in 3D structure. In this work, we present a novel 3D RRAM structure using low-dimensional materials, including 2D graphene and 1D carbon nanotube (CNT), as the edge electrodes. A two-layer 3D RRAM with monolayer graphene as edge electrode is demonstrated. The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale. Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized. Furthermore, the discussion of high array density potential is presented.

  7. Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes

    NASA Astrophysics Data System (ADS)

    Bai, Yue; Wu, Huaqiang; Wang, Kun; Wu, Riga; Song, Lin; Li, Tianyi; Wang, Jiangtao; Yu, Zhiping; Qian, He

    2015-09-01

    There are two critical challenges which determine the array density of 3D RRAM: 1) the scaling limit in both horizontal and vertical directions; 2) the integration of selector devices in 3D structure. In this work, we present a novel 3D RRAM structure using low-dimensional materials, including 2D graphene and 1D carbon nanotube (CNT), as the edge electrodes. A two-layer 3D RRAM with monolayer graphene as edge electrode is demonstrated. The electrical results reveal that the RRAM devices could switch normally with this very thin edge electrode at nanometer scale. Meanwhile, benefited from the asymmetric carrier transport induced by Schottky barrier at metal/CNT and oxide/CNT interfaces, a selector built-in 3D RRAM structure using CNT as edge electrode is successfully fabricated and characterized. Furthermore, the discussion of high array density potential is presented.

  8. Predicting fluctuations in widespread interest: memory decay and goal-related memory accessibility in internet search trends.

    PubMed

    Masicampo, E J; Ambady, Nalini

    2014-02-01

    Memory and interest respond in similar ways to people's shifting needs and motivations. We therefore tested whether memory and interest might produce similar, observable patterns in people's responses over time. Specifically, the present studies examined whether fluctuations in widespread interest (as measured by Internet search trends) resemble two well-established memory patterns: memory decay and goal-related memory accessibility. We examined national and international events (e.g., Nobel Prize selections, holidays) that produced spikes in widespread interest in certain people and foods. When the events that triggered widespread interest were incidental (e.g., the death of a celebrity), widespread interest conformed to memory decay patterns: It rose quickly, fell slowly according to a power function, and was higher after the event than before it. When the events that triggered widespread interest were goal related (e.g., political elections), widespread interest conformed to patterns of goal-related memory accessibility: It rose slowly, fell quickly according to a sigmoid function, and was lower after the event than before it. Fluctuations in widespread interest over time are thus similar to standard memory patterns observed at the individual level due perhaps to common mechanisms and functions.

  9. Predicting fluctuations in widespread interest: memory decay and goal-related memory accessibility in internet search trends.

    PubMed

    Masicampo, E J; Ambady, Nalini

    2014-02-01

    Memory and interest respond in similar ways to people's shifting needs and motivations. We therefore tested whether memory and interest might produce similar, observable patterns in people's responses over time. Specifically, the present studies examined whether fluctuations in widespread interest (as measured by Internet search trends) resemble two well-established memory patterns: memory decay and goal-related memory accessibility. We examined national and international events (e.g., Nobel Prize selections, holidays) that produced spikes in widespread interest in certain people and foods. When the events that triggered widespread interest were incidental (e.g., the death of a celebrity), widespread interest conformed to memory decay patterns: It rose quickly, fell slowly according to a power function, and was higher after the event than before it. When the events that triggered widespread interest were goal related (e.g., political elections), widespread interest conformed to patterns of goal-related memory accessibility: It rose slowly, fell quickly according to a sigmoid function, and was lower after the event than before it. Fluctuations in widespread interest over time are thus similar to standard memory patterns observed at the individual level due perhaps to common mechanisms and functions. PMID:23127417

  10. Remote Memory Access Protocol Target Node Intellectual Property

    NASA Technical Reports Server (NTRS)

    Haddad, Omar

    2013-01-01

    The MagnetoSpheric Multiscale (MMS) mission had a requirement to use the Remote Memory Access Protocol (RMAP) over its SpaceWire network. At the time, no known intellectual property (IP) cores were available for purchase. Additionally, MMS preferred to implement the RMAP functionality with control over the low-level details of the design. For example, not all the RMAP standard functionality was needed, and it was desired to implement only the portions of the RMAP protocol that were needed. RMAP functionality had been previously implemented in commercial off-the-shelf (COTS) products, but the IP core was not available for purchase. The RMAP Target IP core is a VHDL (VHSIC Hardware Description Language description of a digital logic design suitable for implementation in an FPGA (field-programmable gate array) or ASIC (application-specific integrated circuit) that parses SpaceWire packets that conform to the RMAP standard. The RMAP packet protocol allows a network host to access and control a target device using address mapping. This capability allows SpaceWire devices to be managed in a standardized way that simplifies the hardware design of the device, as well as the development of the software that controls the device. The RMAP Target IP core has some features that are unique and not specified in the RMAP standard. One such feature is the ability to automatically abort transactions if the back-end logic does not respond to read/write requests within a predefined time. When a request times out, the RMAP Target IP core automatically retracts the request and returns a command response with an appropriate status in the response packet s header. Another such feature is the ability to control the SpaceWire node or router using RMAP transactions in the extended address range. This allows the SpaceWire network host to manage the SpaceWire network elements using RMAP packets, which reduces the number of protocols that the network host needs to support.

  11. RAPID: A random access picture digitizer, display, and memory system

    NASA Technical Reports Server (NTRS)

    Yakimovsky, Y.; Rayfield, M.; Eskenazi, R.

    1976-01-01

    RAPID is a system capable of providing convenient digital analysis of video data in real-time. It has two modes of operation. The first allows for continuous digitization of an EIA RS-170 video signal. Each frame in the video signal is digitized and written in 1/30 of a second into RAPID's internal memory. The second mode leaves the content of the internal memory independent of the current input video. In both modes of operation the image contained in the memory is used to generate an EIA RS-170 composite video output signal representing the digitized image in the memory so that it can be displayed on a monitor.

  12. Experimental study on radiation effects in floating gate read-only-memories and static random access memories

    NASA Astrophysics Data System (ADS)

    He, Chao-Hui; Li, Yong-Hong

    2007-09-01

    Radiation effects of the floating gate read-only-memory (FG ROM) and the static random access memory (SRAM) have been evaluated using the 14 MeV neutron and 31.9MeV proton beams and Co-60 γ-rays. The neutron fluence, when the first error occurs in the FG ROMs, is at least 5 orders of magnitude higher than that in the SRAMs, and the proton fluence, 4 orders of magnitude higher. The total dose threshold for Co-60 γ-ray irradiation is about 104 rad (Si) for both memories. The difference and similarity are attributed to the structure of the memory cells and the mechanism of radiation effects. It is concluded that the FG ROMs are more reliable as semiconductor memories for storing data than the SRAMs, when they are used in the satellites or space crafts exposed to high energy particle radiation.

  13. Development of Curie point switching for thin film, random access, memory device

    NASA Technical Reports Server (NTRS)

    Lewicki, G. W.; Tchernev, D. I.

    1967-01-01

    Managanese bismuthide films are used in the development of a random access memory device of high packing density and nondestructive readout capability. Memory entry is by Curie point switching using a laser beam. Readout is accomplished by microoptical or micromagnetic scanning.

  14. Control of Access to Memory: The Use of Task Interference as a Behavioral Probe

    ERIC Educational Resources Information Center

    Loft, Shayne; Humphreys, Michael S.; Whitney, Susannah J.

    2008-01-01

    Directed forgetting and prospective memory methods were combined to examine differences in the control of memory access. Between studying two lists of target words, participants were either instructed to forget the first list, or to continue remembering the first list. After study participants performed a lexical decision task with an additional…

  15. Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders

    NASA Astrophysics Data System (ADS)

    Shieh, Ming-Der; Fang, Shih-Hao; Tang, Shing-Chung; Yang, Der-Wei

    Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

  16. High speed magneto-resistive random access memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

    1992-01-01

    A high speed read MRAM memory element is configured from a sandwich of magnetizable, ferromagnetic film surrounding a magneto-resistive film which may be ferromagnetic or not. One outer ferromagnetic film has a higher coercive force than the other and therefore remains magnetized in one sense while the other may be switched in sense by a switching magnetic field. The magneto-resistive film is therefore sensitive to the amplitude of the resultant field between the outer ferromagnetic films and may be constructed of a high resistivity, high magneto-resistive material capable of higher sensing currents. This permits higher read voltages and therefore faster read operations. Alternate embodiments with perpendicular anisotropy, and in-plane anisotropy are shown, including an embodiment which uses high permeability guides to direct the closing flux path through the magneto-resistive material. High density, high speed, radiation hard, memory matrices may be constructed from these memory elements.

  17. A review of emerging non-volatile memory (NVM) technologies and applications

    NASA Astrophysics Data System (ADS)

    Chen, An

    2016-11-01

    This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

  18. Access ordering and coherence in shared-memory multi-processors

    SciTech Connect

    Scheurich, C.E.

    1989-01-01

    Shared memory forms a convenient communication medium in a multitasking multiprocessor system. However, different multiprocessors can execute the same program in different manners, possibly yielding incorrect results because the machines adhere to different rules. Differences in behavior are due to the varying approaches of designers to attack the shared memory access latency problem in multiprocessors. In particular, the manner in which multiple copies of data are controlled and the manner in which memory accesses are sequenced, propagated, and buffered has impact on the behavior of the multiprocessor. Three shared memory execution models, referred to as concurrency models, are defined. The precise properties of processors, memories, and interconnection networks are derived to comply to each of the concurrency models. The usefulness of these concurrency models is demonstrated by showing the simplicity with which their rules can be applied to allow buffering of memory accesses, implement combining networks, prove cache coherence protocols correct, and design lockup-free caches. Specific examples are provided, both of a cache-based multiprocessor potentially without bottlenecks and of a cache-based multiprocessor employing lockup-free caches which can continue to service the processor while concurrently servicing one of several access misses. The paradigms and associated conditions presented in this thesis form a set of powerful tools allowing multiprocessor designers to concentrate on functionality while being burdened less with side-effect analysis.

  19. Asymmetrical access to color and location in visual working memory.

    PubMed

    Rajsic, Jason; Wilson, Daryl E

    2014-10-01

    Models of visual working memory (VWM) have benefitted greatly from the use of the delayed-matching paradigm. However, in this task, the ability to recall a probed feature is confounded with the ability to maintain the proper binding between the feature that is to be reported and the feature (typically location) that is used to cue a particular item for report. Given that location is typically used as a cue-feature, we used the delayed-estimation paradigm to compare memory for location to memory for color, rotating which feature was used as a cue and which was reported. Our results revealed several novel findings: 1) the likelihood of reporting a probed object's feature was superior when reporting location with a color cue than when reporting color with a location cue; 2) location report errors were composed entirely of swap errors, with little to no random location reports; and 3) both colour and location reports greatly benefitted from the presence of nonprobed items at test. This last finding suggests that it is uncertainty over the bindings between locations and colors at memory retrieval that drive swap errors, not at encoding. We interpret our findings as consistent with a representational architecture that nests remembered object features within remembered locations. PMID:25190322

  20. Thermal effect on endurance performance of 3-dimensional RRAM crossbar array

    NASA Astrophysics Data System (ADS)

    Nianduan, Lu; Pengxiao, Sun; Ling, Li; Qi, Liu; Shibing, Long; Lv, Hangbing; Ming, Liu

    2016-05-01

    Three-dimensional (3D) crossbar array architecture is one of the leading candidates for future ultra-high density nonvolatile memory applications. To realize the technological potential, understanding the reliability mechanisms of the 3D RRAM array has become a field of intense research. In this work, the endurance performance of the 3D 1D1R crossbar array under the thermal effect is investigated in terms of numerical simulation. It is revealed that the endurance performance of the 3D 1D1R array would be seriously deteriorated under thermal effects as the feature size scales down to a relatively small value. A possible method to alleviate the thermal effects is provided and verified by numerical simulation. Project supported by the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, the National High Technology Research and Development Program of China (Grant No. 2014AA032901), the National Natural Science Foundation of China (Grant Nos. 61574166, 61334007, 61306117, 61322408, 61221004, and 61274091), Beijing Training Project for the Leading Talents in S&T, China (Grant No. Z151100000315008), and the CAEP Microsystem and THz Science and Technology Foundation, China (Grant No. CAEPMT201504).

  1. Phase-change Random Access Memory: A Scalable Technology

    SciTech Connect

    Raoux, S.; Burr, G; Breitwisch, M; Rettner, C; Chen, Y; Shelby, R; Salinga, M; Krebs, D; Chen, S; Lung, H

    2008-01-01

    Nonvolatile RAM using resistance contrast in phase-change materials [or phase-change RAM (PCRAM)] is a promising technology for future storage-class memory. However, such a technology can succeed only if it can scale smaller in size, given the increasingly tiny memory cells that are projected for future technology nodes (i.e., generations). We first discuss the critical aspects that may affect the scaling of PCRAM, including materials properties, power consumption during programming and read operations, thermal cross-talk between memory cells, and failure mechanisms. We then discuss experiments that directly address the scaling properties of the phase-change materials themselves, including studies of phase transitions in both nanoparticles and ultrathin films as a function of particle size and film thickness. This work in materials directly motivated the successful creation of a series of prototype PCRAM devices, which have been fabricated and tested at phase-change material cross-sections with extremely small dimensions as low as 3 nm x 20 nm. These device measurements provide a clear demonstration of the excellent scaling potential offered by this technology, and they are also consistent with the scaling behavior predicted by extensive device simulations. Finally, we discuss issues of device integration and cell design, manufacturability, and reliability.

  2. Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

    SciTech Connect

    Ando, K. Yuasa, S.; Fujita, S.; Ito, J.; Yoda, H.; Suzuki, Y.; Nakatani, Y.; Miyazaki, T.

    2014-05-07

    Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed.

  3. Optical interconnection network for parallel access to multi-rank memory in future computing systems.

    PubMed

    Wang, Kang; Gu, Huaxi; Yang, Yintang; Wang, Kun

    2015-08-10

    With the number of cores increasing, there is an emerging need for a high-bandwidth low-latency interconnection network, serving core-to-memory communication. In this paper, aiming at the goal of simultaneous access to multi-rank memory, we propose an optical interconnection network for core-to-memory communication. In the proposed network, the wavelength usage is delicately arranged so that cores can communicate with different ranks at the same time and broadcast for flow control can be achieved. A distributed memory controller architecture that works in a pipeline mode is also designed for efficient optical communication and transaction address processes. The scaling method and wavelength assignment for the proposed network are investigated. Compared with traditional electronic bus-based core-to-memory communication, the simulation results based on the PARSEC benchmark show that the bandwidth enhancement and latency reduction are apparent.

  4. Optical interconnection network for parallel access to multi-rank memory in future computing systems.

    PubMed

    Wang, Kang; Gu, Huaxi; Yang, Yintang; Wang, Kun

    2015-08-10

    With the number of cores increasing, there is an emerging need for a high-bandwidth low-latency interconnection network, serving core-to-memory communication. In this paper, aiming at the goal of simultaneous access to multi-rank memory, we propose an optical interconnection network for core-to-memory communication. In the proposed network, the wavelength usage is delicately arranged so that cores can communicate with different ranks at the same time and broadcast for flow control can be achieved. A distributed memory controller architecture that works in a pipeline mode is also designed for efficient optical communication and transaction address processes. The scaling method and wavelength assignment for the proposed network are investigated. Compared with traditional electronic bus-based core-to-memory communication, the simulation results based on the PARSEC benchmark show that the bandwidth enhancement and latency reduction are apparent. PMID:26367901

  5. Program partitioning for NUMA multiprocessor computer systems. [Nonuniform memory access

    SciTech Connect

    Wolski, R.M.; Feo, J.T. )

    1993-11-01

    Program partitioning and scheduling are essential steps in programming non-shared-memory computer systems. Partitioning is the separation of program operations into sequential tasks, and scheduling is the assignment of tasks to processors. To be effective, automatic methods require an accurate representation of the model of computation and the target architecture. Current partitioning methods assume today's most prevalent models -- macro dataflow and a homogeneous/two-level multicomputer system. Based on communication channels, neither model represents well the emerging class of NUMA multiprocessor computer systems consisting of hierarchical read/write memories. Consequently, the partitions generated by extant methods do not execute well on these systems. In this paper, the authors extend the conventional graph representation of the macro-dataflow model to enable mapping heuristics to consider the complex communication options supported by NUMA architectures. They describe two such heuristics. Simulated execution times of program graphs show that the model and heuristics generate higher quality program mappings than current methods for NUMA architectures.

  6. Electrical Evaluation of RCA MWS5501D Random Access Memory, Volume 2, Appendix a

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    The electrical characterization and qualification test results are presented for the RCA MWS5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. The address access time, address readout time, the data hold time, and the data setup time are some of the results surveyed.

  7. Boosting the FM-Index on the GPU: Effective Techniques to Mitigate Random Memory Access.

    PubMed

    Chacón, Alejandro; Marco-Sola, Santiago; Espinosa, Antonio; Ribeca, Paolo; Moure, Juan Carlos

    2015-01-01

    The recent advent of high-throughput sequencing machines producing big amounts of short reads has boosted the interest in efficient string searching techniques. As of today, many mainstream sequence alignment software tools rely on a special data structure, called the FM-index, which allows for fast exact searches in large genomic references. However, such searches translate into a pseudo-random memory access pattern, thus making memory access the limiting factor of all computation-efficient implementations, both on CPUs and GPUs. Here, we show that several strategies can be put in place to remove the memory bottleneck on the GPU: more compact indexes can be implemented by having more threads work cooperatively on larger memory blocks, and a k-step FM-index can be used to further reduce the number of memory accesses. The combination of those and other optimisations yields an implementation that is able to process about two Gbases of queries per second on our test platform, being about 8 × faster than a comparable multi-core CPU version, and about 3 × to 5 × faster than the FM-index implementation on the GPU provided by the recently announced Nvidia NVBIO bioinformatics library. PMID:26451818

  8. 78 FR 35645 - Certain Static Random Access Memories and Products Containing Same; Commission Determination...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-06-13

    ... Cypress Semiconductor Corporation of San Jose, California (``Cypress''). 76 FR 45295 (July 28, 2011). The..., 2013, the Commission determined to review the RID in part, i.e., with respect to invalidity. See 78 FR... COMMISSION Certain Static Random Access Memories and Products Containing Same; Commission...

  9. 76 FR 2336 - Dynamic Random Access Memory Semiconductors From the Republic of Korea: Final Results of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-01-13

    ... Access Memory Semiconductors from the Republic of Korea, 68 FR 47546 (August 11, 2003) (``CVD Order... the Republic of Korea: Preliminary Results of Countervailing Duty Administrative Review, 75 FR 55764..., 73 FR 57594 (October 3, 2008). As a result, CBP is no longer suspending liquidation for entries...

  10. 77 FR 26789 - Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-07

    ... violation of section 337 in the infringement of certain patents. 73 FR 75131. The principal respondent was... order. 75 FR 44989-90 (July 30, 2010). The Commission also issued cease and desist orders against those... COMMISSION Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers...

  11. Making Physical Activity Accessible to Older Adults with Memory Loss: A Feasibility Study

    ERIC Educational Resources Information Center

    Logsdon, Rebecca G.; McCurry, Susan M.; Pike, Kenneth C.; Teri, Linda

    2009-01-01

    Purpose: For individuals with mild cognitive impairment (MCI), memory loss may prevent successful engagement in exercise, a key factor in preventing additional disability. The Resources and Activities for Life Long Independence (RALLI) program uses behavioral principles to make exercise more accessible for these individuals. Exercises are broken…

  12. Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOEpatents

    Blocksome, Michael A; Mamidala, Amith R

    2014-02-11

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  13. Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOEpatents

    Blocksome, Michael A.; Mamidala, Amith R.

    2013-09-03

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  14. 75 FR 20564 - Dynamic Random Access Memory Semiconductors from the Republic of Korea: Extension of Time Limit...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-04-20

    ... Antidumping and Countervailing Duty Administrative Reviews and Requests for Revocation in Part, 74 FR 48224... International Trade Administration Dynamic Random Access Memory Semiconductors from the Republic of Korea... administrative review of the countervailing duty order on dynamic random access memory semiconductors from...

  15. Shared direct memory access on the Explorer 2-LX

    NASA Technical Reports Server (NTRS)

    Musgrave, Jeffrey L.

    1990-01-01

    Advances in Expert System technology and Artificial Intelligence have provided a framework for applying automated Intelligence to the solution of problems which were generally perceived as intractable using more classical approaches. As a result, hybrid architectures and parallel processing capability have become more common in computing environments. The Texas Instruments Explorer II-LX is an example of a machine which combines a symbolic processing environment, and a computationally oriented environment in a single chassis for integrated problem solutions. This user's manual is an attempt to make these capabilities more accessible to a wider range of engineers and programmers with problems well suited to solution in such an environment.

  16. Optical Shared Memory Computing and Multiple Access Protocols for Photonic Networks

    NASA Astrophysics Data System (ADS)

    Li, Kuang-Yu.

    In this research we investigate potential applications of optics in massively parallel computer systems, especially focusing on design issues in three-dimensional optical data storage and free-space photonic networks. An optical implementation of a shared memory uses a single photorefractive crystal and can realize the set of memory modules in a digital shared memory computer. A complete instruction set consists of R sc EAD, W sc RITE, S sc ELECTIVE E sc RASE, and R sc EFRESH, which can be applied to any memory module independent of (and in parallel with) instructions to the other memory modules. In addition, a memory module can execute a sequence of R sc EAD operations simultaneously with the execution of a W sc RITE operation to accommodate differences in optical recording and readout times common to optical volume storage media. An experimental shared memory system is demonstrated and its projected performance is analyzed. A multiplexing technique is presented to significantly reduce both grating- and beam-degeneracy crosstalk in volume holographic systems, by incorporating space, angle, and wavelength as the multiplexing parameters. In this approach, each hologram, which results from the interference between a single input node and an object array, partially overlaps with the other holograms in its neighborhood. This technique can offer improved interconnection density, optical throughput, signal fidelity, and space-bandwidth product utilization. Design principles and numerical simulation results are presented. A free-space photonic cellular hypercube parallel computer, with emphasis on the design of a collisionless multiple access protocol, is presented. This design incorporates wavelength-, space-, and time-multiplexing to achieve multiple access, wavelength reuse, dense connectivity, collisionless communications, and a simple control mechanism. Analytic models based on semi-Markov processes are employed to analyze this protocol. The performance of the

  17. Multilevel Cell Storage and Resistance Variability in Resistive Random Access Memory

    NASA Astrophysics Data System (ADS)

    Pantelis, D. I.; Karakizis, P. N.; Dragatogiannis, D. A.; Charitidis, C. A.

    2016-06-01

    Multilevel per cell (MLC) storage in resistive random access memory (ReRAM) is attractive in achieving high-density and low-cost memory and will be required in future. In this chapter, MLC storage and resistance variability and reliability of multilevel in ReRAM are discussed. Different MLC operation schemes with their physical mechanisms and a comprehensive analysis of resistance variability have been provided. Various factors that can induce variability and their effect on the resistance margin between the multiple resistance levels are assessed. The reliability characteristics and the impact on MLC storage have also been assessed.

  18. Multiple number and letter comparison: directionality and accessibility in numeric and alphabetic memories.

    PubMed

    Jou, Jerwen

    2003-01-01

    In 3 experiments, subjects made comparativejudgments on a set of 2 numbers or letters, 3 numbers or letters, or 5 numbers or letters. Numeric and alphabetic serial order memories were contrasted. Three aspects of serial order memory processes were identified: computational complexity, directionality, and accessibility. Computational complexity is the number of algorithmic steps involved in identifying a target. Directional bias is measured as the speed differences in identifying serial targets of equal computational complexity in a stimulus array. Memory accessibility is measured as the numeric and alphabetic serial position effects. Subjects had a slight directional bias favoring backward ordering for single digits but no bias in 2-digit number ordering, in contrast to a strong forward directional advantage in letter ordering. The speed of number access was found to steadily and evenly decrease along the numeric scale, in contrast to a systematic pattern of variations in alphabet access along the alphabetic scale. Finally, the middle item effect (the middle item in a multi-item array is identified most slowly) found in Jou's (1997) multiple-letter comparison study was generalized to numbers.

  19. Large Capacity of Conscious Access for Incidental Memories in Natural Scenes.

    PubMed

    Kaunitz, Lisandro N; Rowe, Elise G; Tsuchiya, Naotsugu

    2016-09-01

    When searching a crowd, people can detect a target face only by direct fixation and attention. Once the target is found, it is consciously experienced and remembered, but what is the perceptual fate of the fixated nontarget faces? Whereas introspection suggests that one may remember nontargets, previous studies have proposed that almost no memory should be retained. Using a gaze-contingent paradigm, we asked subjects to visually search for a target face within a crowded natural scene and then tested their memory for nontarget faces, as well as their confidence in those memories. Subjects remembered up to seven fixated, nontarget faces with more than 70% accuracy. Memory accuracy was correlated with trial-by-trial confidence ratings, which implies that the memory was consciously maintained and accessed. When the search scene was inverted, no more than three nontarget faces were remembered. These findings imply that incidental memory for faces, such as those recalled by eyewitnesses, is more reliable than is usually assumed. PMID:27507869

  20. Encapsulation layer design and scalability in encapsulated vertical 3D RRAM.

    PubMed

    Yu, Muxi; Fang, Yichen; Wang, Zongwei; Chen, Gong; Pan, Yue; Yang, Xue; Yin, Minghui; Yang, Yuchao; Li, Ming; Cai, Yimao; Huang, Ru

    2016-05-20

    Here we propose a novel encapsulated vertical 3D RRAM structure with each resistive switching cell encapsulated by dielectric layers, contributing to both the reliability improvement of individual cells and thermal disturbance reduction of adjacent cells due to the effective suppression of unwanted oxygen vacancy diffusion. In contrast to the traditional vertical 3D RRAM, encapsulated bar-electrodes are adopted in the proposed structure substituting the previous plane-electrodes, thus encapsulated resistive switching cells can be naturally formed by simply oxidizing the tip of the metal bar-electrodes. In this work, TaO x -based 3D RRAM devices with SiO2 and Si3N4 as encapsulation layers are demonstrated, both showing significant advantages over traditional unencapsulated vertical 3D RRAM. Furthermore, it was found thermal conductivity and oxygen blocking ability are two key parameters of the encapsulation layer design influencing the scalability of vertical 3D RRAM. Experimental and simulation data show that oxygen blocking ability is more critical for encapsulation layers in the relatively large scale, while thermal conductivity becomes dominant as the stacking layers scale to the sub-10 nm regime. Finally, based on the notable impacts of the encapsulation layer on 3D RRAM scaling, an encapsulation material with both excellent oxygen blocking ability and high thermal conductivity such as AlN is suggested to be highly desirable to maximize the advantages of the proposed encapsulated structure. The findings in this work could pave the way for reliable ultrahigh-density storage applications in the big data era. PMID:27044065

  1. Encapsulation layer design and scalability in encapsulated vertical 3D RRAM

    NASA Astrophysics Data System (ADS)

    Yu, Muxi; Fang, Yichen; Wang, Zongwei; Chen, Gong; Pan, Yue; Yang, Xue; Yin, Minghui; Yang, Yuchao; Li, Ming; Cai, Yimao; Huang, Ru

    2016-05-01

    Here we propose a novel encapsulated vertical 3D RRAM structure with each resistive switching cell encapsulated by dielectric layers, contributing to both the reliability improvement of individual cells and thermal disturbance reduction of adjacent cells due to the effective suppression of unwanted oxygen vacancy diffusion. In contrast to the traditional vertical 3D RRAM, encapsulated bar-electrodes are adopted in the proposed structure substituting the previous plane-electrodes, thus encapsulated resistive switching cells can be naturally formed by simply oxidizing the tip of the metal bar-electrodes. In this work, TaO x -based 3D RRAM devices with SiO2 and Si3N4 as encapsulation layers are demonstrated, both showing significant advantages over traditional unencapsulated vertical 3D RRAM. Furthermore, it was found thermal conductivity and oxygen blocking ability are two key parameters of the encapsulation layer design influencing the scalability of vertical 3D RRAM. Experimental and simulation data show that oxygen blocking ability is more critical for encapsulation layers in the relatively large scale, while thermal conductivity becomes dominant as the stacking layers scale to the sub-10 nm regime. Finally, based on the notable impacts of the encapsulation layer on 3D RRAM scaling, an encapsulation material with both excellent oxygen blocking ability and high thermal conductivity such as AlN is suggested to be highly desirable to maximize the advantages of the proposed encapsulated structure. The findings in this work could pave the way for reliable ultrahigh-density storage applications in the big data era.

  2. Design of Unstructured Adaptive (UA) NAS Parallel Benchmark Featuring Irregular, Dynamic Memory Accesses

    NASA Technical Reports Server (NTRS)

    Feng, Hui-Yu; VanderWijngaart, Rob; Biswas, Rupak; Biegel, Bryan (Technical Monitor)

    2001-01-01

    We describe the design of a new method for the measurement of the performance of modern computer systems when solving scientific problems featuring irregular, dynamic memory accesses. The method involves the solution of a stylized heat transfer problem on an unstructured, adaptive grid. A Spectral Element Method (SEM) with an adaptive, nonconforming mesh is selected to discretize the transport equation. The relatively high order of the SEM lowers the fraction of wall clock time spent on inter-processor communication, which eases the load balancing task and allows us to concentrate on the memory accesses. The benchmark is designed to be three-dimensional. Parallelization and load balance issues of a reference implementation will be described in detail in future reports.

  3. Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 5, Appendix D

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    The electrical characterization and qualification test results are presented for the RCA MWS 5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. Average input high current, worst case input high current, output low current, and data setup time are some of the results presented.

  4. Transistor-level characterization of static random access memory bit failures induced by random telegraph noise

    NASA Astrophysics Data System (ADS)

    Mizutani, Tomoko; Saraya, Takuya; Takeuchi, Kiyoshi; Kobayashi, Masaharu; Hiramoto, Toshiro

    2016-04-01

    Bit failure events induced by random telegraph noise (RTN) for silicon-on-thin-buried-oxide (SOTB) static random access memory (SRAM) cells were characterized by directly monitoring the storage node voltage of individual cells, using a device-matrix-array (DMA) test element group (TEG). Correlating the cell-level RTN and failure waveforms with the RTN waveforms of individual transistors that constitute the same cell, RTN of a specific transistor that causes the cell failure was identified.

  5. Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 4, Appendix C

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    The electrical characterization and qualification test results are presented for the RCA MWS5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. Statistical analysis data is supplied along with write pulse width, read cycle time, write cycle time, and chip enable time data.

  6. Immigration, language proficiency, and autobiographical memories: Lifespan distribution and second-language access.

    PubMed

    Esposito, Alena G; Baker-Ward, Lynne

    2016-08-01

    This investigation examined two controversies in the autobiographical literature: how cross-language immigration affects the distribution of autobiographical memories across the lifespan and under what circumstances language-dependent recall is observed. Both Spanish/English bilingual immigrants and English monolingual non-immigrants participated in a cue word study, with the bilingual sample taking part in a within-subject language manipulation. The expected bump in the number of memories from early life was observed for non-immigrants but not immigrants, who reported more memories for events surrounding immigration. Aspects of the methodology addressed possible reasons for past discrepant findings. Language-dependent recall was influenced by second-language proficiency. Results were interpreted as evidence that bilinguals with high second-language proficiency, in contrast to those with lower second-language proficiency, access a single conceptual store through either language. The final multi-level model predicting language-dependent recall, including second-language proficiency, age of immigration, internal language, and cue word language, explained ¾ of the between-person variance and (1)/5 of the within-person variance. We arrive at two conclusions. First, major life transitions influence the distribution of memories. Second, concept representation across multiple languages follows a developmental model. In addition, the results underscore the importance of considering language experience in research involving memory reports.

  7. Comprehension of Linguistic Dependencies: Speed-Accuracy Tradeoff Evidence for Direct-Access Retrieval From Memory

    PubMed Central

    Foraker, Stephani; McElree, Brian

    2012-01-01

    Comprehenders can rapidly and efficiently interpret expressions with various types of non-adjacent dependencies. In the sentence The boy that the teacher warned fell, boy is readily interpreted as the subject of the verb fall despite the fact that a relative clause, that the teacher warned, intervenes between the two dependent elements. We review research investigating three memory operations proposed for resolving this and other types of non-adjacent dependencies: serial search retrieval, in which the dependent constituent is recovered by a search process through representations in memory, direct-access retrieval in which the dependent constituent is recovered directly by retrieval cue operations without search, and active maintenance of the dependent constituent in focal attention. Studies using speed-accuracy tradeoff methodology to examine the full timecourse of interpreting a wide range of non-adjacent dependencies indicate that comprehenders retrieve dependent constituents with a direct-access operation, consistent with the claim that representations formed during comprehension are accessed with a cue-driven, content-addressable retrieval process. The observed timecourse profiles are inconsistent with a broad class of models based on several search operations for retrieval. The profiles are also inconsistent with active maintenance of a constituent while concurrently processing subsequent material, and suggest that, with few exceptions, direct-access retrieval is required to process non-adjacent dependencies. PMID:22448181

  8. Daily Access to Sucrose Impairs Aspects of Spatial Memory Tasks Reliant on Pattern Separation and Neural Proliferation in Rats

    ERIC Educational Resources Information Center

    Reichelt, Amy C.; Morris, Margaret J.; Westbrook, Reginald Frederick

    2016-01-01

    High sugar diets reduce hippocampal neurogenesis, which is required for minimizing interference between memories, a process that involves "pattern separation." We provided rats with 2 h daily access to a sucrose solution for 28 d and assessed their performance on a spatial memory task. Sucrose consuming rats discriminated between objects…

  9. 75 FR 44283 - In the Matter of Certain Dynamic Random Access Memory Semiconductors and Products Containing Same...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-07-28

    ... America Corp. of Milpitas, California (collectively ``complainants''). 75 FR 14467-68 (March 25, 2010... COMMISSION In the Matter of Certain Dynamic Random Access Memory Semiconductors and Products Containing Same, Including Memory Modules; Notice of a Commission Determination Not To Review an Initial...

  10. Encoding and Retrieval Processes Involved in the Access of Source Information in the Absence of Item Memory

    ERIC Educational Resources Information Center

    Ball, B. Hunter; DeWitt, Michael R.; Knight, Justin B.; Hicks, Jason L.

    2014-01-01

    The current study sought to examine the relative contributions of encoding and retrieval processes in accessing contextual information in the absence of item memory using an extralist cuing procedure in which the retrieval cues used to query memory for contextual information were "related" to the target item but never actually studied.…

  11. Nonlinear and multilevel resistive switching memory in Ni/Si3N4/Al2O3/TiN structures

    NASA Astrophysics Data System (ADS)

    Kim, Sungjun; Park, Byung-Gook

    2016-05-01

    In this letter, we extensively investigate the nonlinear resistive switching characteristics of Si3N4-based resistive random access memory (RRAM) devices that contain an Al2O3 tunnel barrier layer to alleviate sneak path currents in the cross-point array structure. When the compliance current (ICC) exceeds 1 mA, the Ni/Si3N4/TiN device shows both unipolar and bipolar switching with Ohmic characteristics in the low resistance state. Nonlinear resistive switching characteristics were observed for this device when ICC was ≤100 μA. We fabricated Si3N4/Al2O3 bilayer devices with different tunnel barrier layer thickness and characterized their nonlinear characteristics and failure resistance during the reset process. Furthermore, we obtained stable multiple resistance levels in the devices by varying ICC and the stop voltage for the set and reset switching, respectively. Our results suggest that an Al2O3 tunnel barrier layer embedded in Si3N4-based RRAM devices offers considerable potential to realize high-density cross-point memory array applications.

  12. Resistive switching memories based on metal oxides: mechanisms, reliability and scaling

    NASA Astrophysics Data System (ADS)

    Ielmini, Daniele

    2016-06-01

    With the explosive growth of digital data in the era of the Internet of Things (IoT), fast and scalable memory technologies are being researched for data storage and data-driven computation. Among the emerging memories, resistive switching memory (RRAM) raises strong interest due to its high speed, high density as a result of its simple two-terminal structure, and low cost of fabrication. The scaling projection of RRAM, however, requires a detailed understanding of switching mechanisms and there are potential reliability concerns regarding small device sizes. This work provides an overview of the current understanding of bipolar-switching RRAM operation, reliability and scaling. After reviewing the phenomenological and microscopic descriptions of the switching processes, the stability of the low- and high-resistance states will be discussed in terms of conductance fluctuations and evolution in 1D filaments containing only a few atoms. The scaling potential of RRAM will finally be addressed by reviewing the recent breakthroughs in multilevel operation and 3D architecture, making RRAM a strong competitor among future high-density memory solutions.

  13. Gate controllable resistive random access memory devices using reduced graphene oxide

    NASA Astrophysics Data System (ADS)

    Hazra, Preetam; Resmi, A. N.; Jinesh, K. B.

    2016-04-01

    The biggest challenge in the resistive random access memory (ReRAM) technology is that the basic operational parameters, such as the set and reset voltages, the current on-off ratios (hence the power), and their operational speeds, strongly depend on the active and electrode materials and their processing methods. Therefore, for its actual technological implementations, the unification of the operational parameters of the ReRAM devices appears to be a difficult task. In this letter, we show that by fabricating a resistive memory device in a thin film transistor configuration and thus applying an external gate bias, we can control the switching voltage very accurately. Taking partially reduced graphene oxide, the gate controllable switching is demonstrated, and the possible mechanisms are discussed.

  14. Bipolar resistive switching characteristics in tantalum nitride-based resistive random access memory devices

    SciTech Connect

    Kim, Myung Ju; Jeon, Dong Su; Park, Ju Hyun; Kim, Tae Geun

    2015-05-18

    This paper reports the bipolar resistive switching characteristics of TaN{sub x}-based resistive random access memory (ReRAM). The conduction mechanism is explained by formation and rupture of conductive filaments caused by migration of nitrogen ions and vacancies; this mechanism is in good agreement with either Ohmic conduction or the Poole-Frenkel emission model. The devices exhibit that the reset voltage varies from −0.82 V to −0.62 V, whereas the set voltage ranges from 1.01 V to 1.30 V for 120 DC sweep cycles. In terms of reliability, the devices exhibit good retention (>10{sup 5 }s) and pulse-switching endurance (>10{sup 6} cycles) properties. These results indicate that TaN{sub x}-based ReRAM devices have a potential for future nonvolatile memory devices.

  15. Extremely small test cell structure for resistive random access memory element with removable bottom electrode

    SciTech Connect

    Koh, Sang-Gyu; Kishida, Satoru; Kinoshita, Kentaro

    2014-02-24

    We established a method of preparing an extremely small memory cell by fabricating a resistive random access memory (ReRAM) structure on the tip of a cantilever of an atomic force microscope. This structure has the high robustness against the drift of the cantilever, and the effective cell size was estimated to be less than 10 nm in diameter due to the electric field concentration at the tip of the cantilever, which was confirmed using electric field simulation. The proposed structure, which has a removable bottom electrode, enables not only the preparation of a tiny ReRAM structure but also the performance of unique experiments, by making the most of its high robustness against the drift of the cantilever.

  16. High-density magnetoresistive random access memory operating at ultralow voltage at room temperature

    PubMed Central

    Hu, Jia-Mian; Li, Zheng; Chen, Long-Qing; Nan, Ce-Wen

    2011-01-01

    The main bottlenecks limiting the practical applications of current magnetoresistive random access memory (MRAM) technology are its low storage density and high writing energy consumption. Although a number of proposals have been reported for voltage-controlled memory device in recent years, none of them simultaneously satisfy the important device attributes: high storage capacity, low power consumption and room temperature operation. Here we present, using phase-field simulations, a simple and new pathway towards high-performance MRAMs that display significant improvements over existing MRAM technologies or proposed concepts. The proposed nanoscale MRAM device simultaneously exhibits ultrahigh storage capacity of up to 88 Gb inch−2, ultralow power dissipation as low as 0.16 fJ per bit and room temperature high-speed operation below 10 ns. PMID:22109527

  17. Effects of automatic/controlled access processes on semantic memory in Alzheimer's disease.

    PubMed

    Arroyo-Anlló, Eva M; Bellouard, Stéphanie; Ingrand, Pierre; Gil, Roger

    2011-01-01

    This study examines the impact of automatic/controlled access processes on the semantic network in 30 patients with Alzheimer's disease (AD). The AD group was compared with a control group using a battery of neuropsychological tests, a variation of Hodges's semantic testing battery, designed to assess semantic knowledge. The AD group had markedly lower scores than the normal group on each semantic test, but with a different degree of deterioration depending on the nature of the processes (controlled/automatic) in accessing the semantic network. AD patients had poorer performances on the explicit semantic tasks mainly involving controlled-process access (e.g., the WAIS Similarities Subtest) than those involving mainly automatic-process access (e.g., the Verbal Automatism test). Analyses of confidence intervals allowed a gradient of impaired performances in increasing order to be elaborated: a) the Verbal Automatism test, b) the WAIS Vocabulary Subtest, c) the WAIS Information Subtest, d) the Letter Fluency Task, e) Naming as a Response to Definition, f) the Category Fluency Task, g) the WAIS Similarities Subtest, and h) the Oral Denomination 80 Test. The results of our study suggest that explicit semantic tasks needing passive or automatic processes to access semantic memory would be better preserved in AD. PMID:21471640

  18. Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

    NASA Technical Reports Server (NTRS)

    Wu, Jiin C.; Katti, Romney R.; Stadler, Henry L.

    1991-01-01

    The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

  19. Analysis and modeling of resistive switching mechanisms oriented to resistive random-access memory

    NASA Astrophysics Data System (ADS)

    Huang, Da; Wu, Jun-Jie; Tang, Yu-Hua

    2013-03-01

    With the progress of the semiconductor industry, the resistive random-access memory (RAM) has drawn increasing attention. The discovery of the memristor has brought much attention to this study. Research has focused on the resistive switching characteristics of different materials and the analysis of resistive switching mechanisms. We discuss the resistive switching mechanisms of different materials in this paper and analyze the differences of those mechanisms from the view point of circuitry to establish their respective circuit models. Finally, simulations are presented. We give the prospect of using different materials in resistive RAM on account of their resistive switching mechanisms, which are applied to explain their resistive switchings.

  20. Random access memory immune to single event upset using a T-resistor

    DOEpatents

    Ochoa, Jr., Agustin

    1989-01-01

    In a random access memory cell, a resistance "T" decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell.

  1. A stochastic simulation method for the assessment of resistive random access memory retention reliability

    SciTech Connect

    Berco, Dan Tseng, Tseung-Yuen

    2015-12-21

    This study presents an evaluation method for resistive random access memory retention reliability based on the Metropolis Monte Carlo algorithm and Gibbs free energy. The method, which does not rely on a time evolution, provides an extremely efficient way to compare the relative retention properties of metal-insulator-metal structures. It requires a small number of iterations and may be used for statistical analysis. The presented approach is used to compare the relative robustness of a single layer ZrO{sub 2} device with a double layer ZnO/ZrO{sub 2} one, and obtain results which are in good agreement with experimental data.

  2. A random access memory immune to single event upset using a T-Resistor

    DOEpatents

    Ochoa, A. Jr.

    1987-10-28

    In a random access memory cell, a resistance ''T'' decoupling network in each leg of the cell reduces random errors caused by the interaction of energetic ions with the semiconductor material forming the cell. The cell comprises two parallel legs each containing a series pair of complementary MOS transistors having a common gate connected to the node between the transistors of the opposite leg. The decoupling network in each leg is formed by a series pair of resistors between the transistors together with a third resistor interconnecting the junction between the pair of resistors and the gate of the transistor pair forming the opposite leg of the cell. 4 figs.

  3. Spin-transfer-torque efficiency enhanced by edge-damage of perpendicular magnetic random access memories

    SciTech Connect

    Song, Kyungmi; Lee, Kyung-Jin

    2015-08-07

    We numerically investigate the effect of magnetic and electrical damages at the edge of a perpendicular magnetic random access memory (MRAM) cell on the spin-transfer-torque (STT) efficiency that is defined by the ratio of thermal stability factor to switching current. We find that the switching mode of an edge-damaged cell is different from that of an undamaged cell, which results in a sizable reduction in the switching current. Together with a marginal reduction of the thermal stability factor of an edge-damaged cell, this feature makes the STT efficiency large. Our results suggest that a precise edge control is viable for the optimization of STT-MRAM.

  4. Information matching the content of visual working memory is prioritized for conscious access.

    PubMed

    Gayet, Surya; Paffen, Chris L E; Van der Stigchel, Stefan

    2013-12-01

    Visual working memory (VWM) is used to retain relevant information for imminent goal-directed behavior. In the experiments reported here, we found that VWM helps to prioritize relevant information that is not yet available for conscious experience. In five experiments, we demonstrated that information matching VWM content reaches visual awareness faster than does information not matching VWM content. Our findings suggest a functional link between VWM and visual awareness: The content of VWM is recruited to funnel down the vast amount of sensory input to that which is relevant for subsequent behavior and therefore requires conscious access.

  5. One electron-controlled multiple-valued dynamic random-access-memory

    NASA Astrophysics Data System (ADS)

    Kye, H. W.; Song, B. N.; Lee, S. E.; Kim, J. S.; Shin, S. J.; Choi, J. B.; Yu, Y.-S.; Takahashi, Y.

    2016-02-01

    We propose a new architecture for a dynamic random-access-memory (DRAM) capable of storing multiple values by using a single-electron transistor (SET). The gate of a SET is designed to be connected to a plurality of DRAM unit cells that are arrayed at intersections of word lines and bitlines. In this SET-DRAM hybrid scheme, the multiple switching characteristics of SET enables multiple value data stored in a DRAM unit cell, and this increases the storage functionality of the device. Moreover, since refreshing data requires only a small amount of SET driving current, this enables device operating with low standby power consumption.

  6. Temperature effects on failure and annealing behavior in dynamic random access memories

    NASA Astrophysics Data System (ADS)

    Wilkin, N. D.; Self, C. T.

    1982-12-01

    Total dose failure levels and long time anneal characteristics of dynamic random access memories are measured while the devices are exercised under actual use conditions. These measurements were performed over the temperature range of -60 C to +70 C. The total dose failure levels are shown to decrease with increasing temperature. The anneal characteristics are shown to result in both an increase and decrease in the measured number of errors as a function of time. Finally a description of the test instrumentation and irradiation procedures are given.

  7. Microstructural Characterization in Reliability Measurement of Phase Change Random Access Memory

    NASA Astrophysics Data System (ADS)

    Bae, Junsoo; Hwang, Kyuman; Park, Kwangho; Jeon, Seongbu; Kang, Dae-hwan; Park, Soonoh; Ahn, Juhyeon; Kim, Seoksik; Jeong, Gitae; Chung, Chilhee

    2011-04-01

    The cell failures after cycling endurance in phase-change random access memory (PRAM) have been classified into three groups, which have been analyzed by transmission electron microscopy (TEM). Both stuck reset of the set state (D0) and stuck set of the reset state (D1) are due to a void created inside GeSbTe (GST) film or thereby lowering density of GST film. The decrease of the both set and reset resistances that leads to the tails from the reset distribution are induced from the Sb increase with cycles.

  8. 40-Gbit/s photonic random access memory for photonic packet-switched networks

    NASA Astrophysics Data System (ADS)

    Takahashi, Ryo; Nakahara, Tatsushi; Takahata, Kiyoto; Takenouchi, Hirokazu; Yasui, Takako; Kondo, Naoto; Suzuki, Hiroyuki

    2004-06-01

    We present a photonic random access memory (RAM) that can write and read high-speed asynchronous burst optical packets freely by specifying addresses. The photonic RAM consists of an optical clock-pulse generator, an all-optical serial-to-parallel converter, a photonic parallel-to-serial converter, all developed by us, and a CMOS RAM as a storage medium. Unlike conventional optical buffers, which merely function as optical delay lines, the photonic RAM provides various advantages, such as compactness, large capacity, long-term storage, and random access at an arbitrary timing for ultrafast asynchronous burst optical packets. We experimentally confirm its basic operation for 40-Gbit/s 16-bit optical packets.

  9. Highly-Ordered 3D Vertical Resistive Switching Memory Arrays with Ultralow Power Consumption and Ultrahigh Density.

    PubMed

    Al-Haddad, Ahmed; Wang, Chengliang; Qi, Haoyuan; Grote, Fabian; Wen, Liaoyong; Bernhard, Jörg; Vellacheri, Ranjith; Tarish, Samar; Nabi, Ghulam; Kaiser, Ute; Lei, Yong

    2016-09-01

    Resistive switching random access memories (RRAM) have attracted great scientific and industrial attention for next generation data storage because of their advantages of nonvolatile properties, high density, low power consumption, fast writing/erasing speed, good endurance, and simple and small operation system. Here, by using a template-assisted technique, we demonstrate a three-dimensional highly ordered vertical RRAM device array with density as high as that of the nanopores of the template (10(8)-10(9) cm(-2)), which can also be fabricated in large area. The high crystallinity of the materials, the large contact area and the intimate semiconductor/electrode interface (3 nm interfacial layer) make the ultralow voltage operation (millivolt magnitude) and ultralow power consumption (picowatt) possible. Our procedure for fabrication of the nanodevice arrays in large area can be used for producing many other different materials and such three-dimensional electronic device arrays with the capability to adjust the device densities can be extended to other applications of the next generation nanodevice technology. PMID:27525738

  10. Simulation of thermal reset transitions in resistive switching memories including quantum effects

    SciTech Connect

    Villena, M. A.; Jiménez-Molinos, F.; Roldán, J. B.; Suñé, J.; Miranda, E.; Romera, E.

    2014-06-07

    An in-depth study of reset processes in RRAMs (Resistive Random Access Memories) based on Ni/HfO{sub 2}/Si-n{sup +} structures has been performed. To do so, we have developed a physically based simulator where both ohmic and tunneling based conduction regimes are considered along with the thermal description of the devices. The devices under study have been successfully fabricated and measured. The experimental data are correctly reproduced with the simulator for devices with a single conductive filament as well as for devices including several conductive filaments. The contribution of each conduction regime has been explained as well as the operation regimes where these ohmic and tunneling conduction processes dominate.

  11. Analyzing the Energy and Power Consumption of Remote Memory Accesses in the OpenSHMEM Model

    SciTech Connect

    Jana, Siddhartha; Hernandez, Oscar R; Poole, Stephen W; Hsu, Chung-Hsing; Chapman, Barbara

    2014-01-01

    PGAS models like OpenSHMEM provide interfaces to explicitly initiate one-sided remote memory accesses among processes. In addition, the model also provides synchronizing barriers to ensure a consistent view of the distributed memory at different phases of an application. The incorrect use of such interfaces affects the scalability achievable while using a parallel programming model. This study aims at understanding the effects of these constructs on the energy and power consumption behavior of OpenSHMEM applications. Our experiments show that cost incurred in terms of the total energy and power consumed depends on multiple factors across the software and hardware stack. We conclude that there is a significant impact on the power consumed by the CPU and DRAM due to multiple factors including the design of the data transfer patterns within an application, the design of the communication protocols within a middleware, the architectural constraints laid by the interconnect solutions, and also the levels of memory hierarchy within a compute node. This work motivates treating energy and power consumption as important factors while designing compute solutions for current and future distributed systems.

  12. Multiple social identities and stereotype threat: imbalance, accessibility, and working memory.

    PubMed

    Rydell, Robert J; McConnell, Allen R; Beilock, Sian L

    2009-05-01

    In 4 experiments, the authors showed that concurrently making positive and negative self-relevant stereotypes available about performance in the same ability domain can eliminate stereotype threat effects. Replicating past work, the authors demonstrated that introducing negative stereotypes about women's math performance activated participants' female social identity and hurt their math performance (i.e., stereotype threat) by reducing working memory. Moving beyond past work, it was also demonstrated that concomitantly presenting a positive self-relevant stereotype (e.g., college students are good at math) increased the relative accessibility of females' college student identity and inhibited their gender identity, eliminating attendant working memory deficits and contingent math performance decrements. Furthermore, subtle manipulations in questions presented in the demographic section of a math test eliminated stereotype threat effects that result from women reporting their gender before completing the test. This work identifies the motivated processes through which people's social identities became active in situations in which self-relevant stereotypes about a stigmatized group membership and a nonstigmatized group membership were available. In addition, it demonstrates the downstream consequences of this pattern of activation on working memory and performance.

  13. Making working memory work: The effects of extended practice on focus capacity and the processes of updating, forward access, and random access

    PubMed Central

    Price, John M.; Colflesh, Gregory J. H.; Cerella, John; Verhaeghen, Paul

    2014-01-01

    We investigated the effects of 10 hours of practice on variations of the N-Back task to investigate the processes underlying possible expansion of the focus of attention within working memory. Using subtractive logic, we showed that random access (i.e., Sternberg-like search) yielded a modest effect (a 50% increase in speed) whereas the processes of forward access (i.e., retrieval in order, as in a standard N-Back task) and updating (i.e., changing the contents of working memory) were executed about 5 times faster after extended practice. We additionally found that extended practice increased working memory capacity as measured by the size of the focus of attention for the forward-access task, but not for variations where probing was in random order. This suggests that working memory capacity may depend on the type of search process engaged, and that certain working-memory-related cognitive processes are more amenable to practice than others. PMID:24486803

  14. Response of the Ubiquitin-Proteasome System to Memory Retrieval After Extended-Access Cocaine or Saline Self-Administration.

    PubMed

    Werner, Craig T; Milovanovic, Mike; Christian, Daniel T; Loweth, Jessica A; Wolf, Marina E

    2015-12-01

    The ubiquitin-proteasome system (UPS) has been implicated in the retrieval-induced destabilization of cocaine- and fear-related memories in Pavlovian paradigms. However, nothing is known about its role in memory retrieval after self-administration of cocaine, an operant paradigm, or how the length of withdrawal from cocaine may influence retrieval mechanisms. Here, we examined UPS activity after an extended-access cocaine self-administration regimen that leads to withdrawal-dependent incubation of cue-induced cocaine craving. Controls self-administered saline. In initial experiments, memory retrieval was elicited via a cue-induced seeking/retrieval test on withdrawal day (WD) 50-60, when craving has incubated. We found that retrieval of cocaine- and saline-associated memories produced similar increases in polyubiquitinated proteins in the nucleus accumbens (NAc), compared with rats that did not undergo a seeking/retrieval test. Measures of proteasome catalytic activity confirmed similar activation of the UPS after retrieval of saline and cocaine memories. However, in a subsequent experiment in which testing was conducted on WD1, proteasome activity in the NAc was greater after retrieval of cocaine memory than saline memory. Analysis of other brain regions confirmed that effects of cocaine memory retrieval on proteasome activity, relative to saline memory retrieval, depend on withdrawal time. These results, combined with prior studies, suggest that the relationship between UPS activity and memory retrieval depends on training paradigm, brain region, and time elapsed between training and retrieval. The observation that mechanisms underlying cocaine memory retrieval change depending on the age of the memory has implications for development of memory destabilization therapies for cue-induced relapse in cocaine addicts.

  15. TiO2 based nanostructured memristor for RRAM and neuromorphic applications: a simulation approach

    NASA Astrophysics Data System (ADS)

    Dongale, T. D.; Patil, P. J.; Desai, N. K.; Chougule, P. P.; Kumbhar, S. M.; Waifalkar, P. P.; Patil, P. B.; Vhatkar, R. S.; Takale, M. V.; Gaikwad, P. K.; Kamat, R. K.

    2016-07-01

    We report simulation of nanostructured memristor device using piecewise linear and nonlinear window functions for RRAM and neuromorphic applications. The linear drift model of memristor has been exploited for the simulation purpose with the linear and non-linear window function as the mathematical and scripting basis. The results evidences that the piecewise linear window function can aptly simulate the memristor characteristics pertaining to RRAM application. However, the nonlinear window function could exhibit the nonlinear phenomenon in simulation only at the lower magnitude of control parameter. This has motivated us to propose a new nonlinear window function for emulating the simulation model of the memristor. Interestingly, the proposed window function is scalable up to f( x) = 1 and exhibits the nonlinear behavior at higher magnitude of control parameter. Moreover, the simulation results of proposed nonlinear window function are encouraging and reveals the smooth nonlinear change from LRS to HRS and vice versa and therefore useful for the neuromorphic applications.

  16. Synergistic effects of total ionizing dose on single event upset sensitivity in static random access memory under proton irradiation

    NASA Astrophysics Data System (ADS)

    Xiao, Yao; Guo, Hong-Xia; Zhang, Feng-Qi; Zhao, Wen; Wang, Yan-Ping; Zhang, Ke-Ying; Ding, Li-Li; Fan, Xue; Luo, Yin-Hong; Wang, Yuan-Ming

    2014-11-01

    Synergistic effects of the total ionizing dose (TID) on the single event upset (SEU) sensitivity in static random access memories (SRAMs) were studied by using protons. The total dose was cumulated with high flux protons during the TID exposure, and the SEU cross section was tested with low flux protons at several cumulated dose steps. Because of the radiation-induced off-state leakage current increase of the CMOS transistors, the noise margin became asymmetric and the memory imprint effect was observed.

  17. Novel Circuitry Configuration with Paired-Cell Erase Operation for High-Density 90-nm Embedded Resistive Random Access Memory

    NASA Astrophysics Data System (ADS)

    Sato, Yoshihiro; Tsunoda, Koji; Aoki, Masaki; Sugiyama, Yoshihiro

    2009-04-01

    We propose a novel circuitry configuration for high-density 90-nm embedded resistive random access memory (ReRAM). The memory cells are operated at 2 V, and a small memory cell size of 6F2 consisting of a 1.2-V standard transistor and a resistive junction (1T-1R) is designed, where F is the feature size. The unique circuitry configuration is that each pair of source-lines connects to each source-line selective gate. Therefore, erasing is done by a pair of cells in turn in the whole sector, while the reading or programming is done by a random accessing operation. We simulated the ReRAM circuit for read and write operations with SPICE. As a result, we found that 5-ns high-speed read access was obtained in the 256-word lines (WLs) × 256-bit lines (BLs) and that the SET/RESET operation was stable.

  18. Improvement of performances HfO2-based RRAM from elementary cell to 16 kb demonstrator by introduction of thin layer of Al2O3

    NASA Astrophysics Data System (ADS)

    Azzaz, M.; Benoist, A.; Vianello, E.; Garbin, D.; Jalaguier, E.; Cagli, C.; Charpin, C.; Bernasconi, S.; Jeannot, S.; Dewolf, T.; Audoit, G.; Guedj, C.; Denorme, S.; Candelier, P.; Fenouillet-Beranger, C.; Perniola, L.

    2016-11-01

    In this article, the reliability of HfO2-based RRAM devices integrated in an advanced 28 nm CMOS 16 kbit demonstrator is presented. In order to improve the memory performance, a thin Al2O3 layer is inserted in the HfO2-based memory stack (TiN/Ti/HfO2/Al2O3/TiN). Thanks to extensive electrical characterizations on both single layer HfO2 and bilayer HfO2/Al2O3 memory stacks at device and array levels, the potential of the bilayer is put forward. From the experimental results, the thin Al2O3 layer has allowed to improve the endurance (memory window of about one decade after 1 M cycles) and data retention (both the low and the high resistance states are stable after 6 h at 200 °C). Finally, thanks to our 3D model based on calculation of the Conductive Filament resistance using trap assisted tunneling (TAT) the role of Al2O3 as series resistance is highlighted.

  19. Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operation

    NASA Astrophysics Data System (ADS)

    Huh, In; Cheon, Woo Young; Choi, Woo Young

    2016-04-01

    A subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory (SAT RAM) has been proposed and fabricated for low-power nonvolatile memory applications. The proposed SAT RAM cell demonstrates adjustable subthreshold swing (SS) depending on stored information: small SS in the erase state ("1" state) and large SS in the program state ("0" state). Thus, SAT RAM cells can achieve low read voltage (Vread) with a large memory window in addition to the effective suppression of ambipolar behavior. These unique features of the SAT RAM are originated from the locally stored charge, which modulates the tunneling barrier width (Wtun) of the source-to-channel tunneling junction.

  20. Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors

    NASA Astrophysics Data System (ADS)

    Yang, Jyun-Bao; Chang, Ting-Chang; Huang, Jheng-Jie; Chen, Yu-Chun; Chen, Yu-Ting; Tseng, Hsueh-Chih; Chu, Ann-Kuo; Sze, Simon M.

    2014-04-01

    In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

  1. Dual operation characteristics of resistance random access memory in indium-gallium-zinc-oxide thin film transistors

    SciTech Connect

    Yang, Jyun-Bao; Chen, Yu-Ting; Chu, Ann-Kuo; Chang, Ting-Chang; Huang, Jheng-Jie; Chen, Yu-Chun; Tseng, Hsueh-Chih; Sze, Simon M.

    2014-04-14

    In this study, indium-gallium-zinc-oxide thin film transistors can be operated either as transistors or resistance random access memory devices. Before the forming process, current-voltage curve transfer characteristics are observed, and resistance switching characteristics are measured after a forming process. These resistance switching characteristics exhibit two behaviors, and are dominated by different mechanisms. The mode 1 resistance switching behavior is due to oxygen vacancies, while mode 2 is dominated by the formation of an oxygen-rich layer. Furthermore, an easy approach is proposed to reduce power consumption when using these resistance random access memory devices with the amorphous indium-gallium-zinc-oxide thin film transistor.

  2. Voltage induced magnetostrictive switching of nanomagnets: Strain assisted strain transfer torque random access memory

    SciTech Connect

    Khan, Asif Nikonov, Dmitri E.; Manipatruni, Sasikanth; Ghani, Tahir; Young, Ian A.

    2014-06-30

    A spintronic device, called the “strain assisted spin transfer torque (STT) random access memory (RAM),” is proposed by combining the magnetostriction effect and the spin transfer torque effect which can result in a dramatic improvement in the energy dissipation relative to a conventional STT-RAM. Magnetization switching in the device which is a piezoelectric-ferromagnetic heterostructure via the combined magnetostriction and STT effect is simulated by solving the Landau-Lifshitz-Gilbert equation incorporating the influence of thermal noise. The simulations show that, in such a device, each of these two mechanisms (magnetostriction and spin transfer torque) provides in a 90° rotation of the magnetization leading a deterministic 180° switching with a critical current significantly smaller than that required for spin torque alone. Such a scheme is an attractive option for writing magnetic RAM cells.

  3. Voltage induced magnetostrictive switching of nanomagnets: Strain assisted strain transfer torque random access memory

    NASA Astrophysics Data System (ADS)

    Khan, Asif; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Ghani, Tahir; Young, Ian A.

    2014-06-01

    A spintronic device, called the "strain assisted spin transfer torque (STT) random access memory (RAM)," is proposed by combining the magnetostriction effect and the spin transfer torque effect which can result in a dramatic improvement in the energy dissipation relative to a conventional STT-RAM. Magnetization switching in the device which is a piezoelectric-ferromagnetic heterostructure via the combined magnetostriction and STT effect is simulated by solving the Landau-Lifshitz-Gilbert equation incorporating the influence of thermal noise. The simulations show that, in such a device, each of these two mechanisms (magnetostriction and spin transfer torque) provides in a 90° rotation of the magnetization leading a deterministic 180° switching with a critical current significantly smaller than that required for spin torque alone. Such a scheme is an attractive option for writing magnetic RAM cells.

  4. Precessional reversal in orthogonal spin transfer magnetic random access memory devices

    NASA Astrophysics Data System (ADS)

    Liu, H.; Bedau, D.; Backes, D.; Katine, J. A.; Kent, A. D.

    2012-07-01

    Single-shot time-resolved resistance measurements have been used to determine the magnetization reversal mechanisms of orthogonal spin transfer magnetic random access memory (OST-MRAM) devices at nanosecond time scales. There is a strong asymmetry between antiparallel (AP) to parallel (P) and P to AP transitions under the same pulse conditions. P to AP transitions are shown to occur by precession of the free layer magnetization, while the AP to P transition is typically direct, occurring in less than 200 ps. We associate the asymmetry with spin torques perpendicular to the plane of the free layer, an important characteristic of OST-MRAM bit cells that can be used to optimize device performance.

  5. Manufacturable High-Density 8 Mbit One Transistor-One Capacitor Embedded Ferroelectric Random Access Memory

    NASA Astrophysics Data System (ADS)

    Udayakumar, K. R.; Moise, T. S.; Summerfelt, S. R.; Boku, K.; Remack, K.; Rodriguez, J.; Arendt, M.; Shinn, G.; Eliason, J.; Bailey, R.; Staubs, P.

    2008-04-01

    Enhanced yield and reliability through process improvements, leading to a manufacturable process for a full-bit functional 8 Mbit one transitor-one capacitor (1T-1C) embedded ferroelectric random access memory (eFRAM) fabricated within a low-leakage 130 nm, 5 lm Cu/fluorosilicate glass (FSG) interconnect complementary metal oxide semiconductor (CMOS) logic process, are described. Higher signal margins are further enabled by the single-bit substitution methodology that replaces bits at the low-end of the original distribution with redundant elements. Retention tests on wafers with signal margins above a threshold value for screen show no bit fails for bakes extending up to 1000 h, suggesting retention lifetimes of more than 10 years at 85 °C. Using the qualified process reported in this paper, commercial products are being routinely produced in our fabrication facilities.

  6. False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

    NASA Astrophysics Data System (ADS)

    Sawada, Takuya; Takata, Hidehiro; Nii, Koji; Nagata, Makoto

    2013-04-01

    Static random access memory (SRAM) cores exhibit susceptibility against power supply voltage variation. False operation is investigated among SRAM cells under sinusoidal voltage variation on power lines introduced by direct RF power injection. A standard SRAM core of 16 kbyte in a 90 nm 1.5 V technology is diagnosed with built-in self test and on-die noise monitor techniques. The sensitivity of bit error rate is shown to be high against the frequency of injected voltage variation, while it is not greatly influenced by the difference in frequency and phase against SRAM clocking. It is also observed that the distribution of false bits is substantially random in a cell array.

  7. Understanding Electrical Conduction States in WO3 Thin Films Applied for Resistive Random-Access Memory

    NASA Astrophysics Data System (ADS)

    Ta, Thi Kieu Hanh; Pham, Kim Ngoc; Dao, Thi Bang Tam; Tran, Dai Lam; Phan, Bach Thang

    2016-05-01

    The electrical conduction and associated resistance switching mechanism of top electrode/WO3/bottom electrode devices [top electrode (TE): Ag, Ti; bottom electrode (BE): Pt, fluorine-doped tin oxide] have been investigated. The direction of switching and switching ability depended on both the top and bottom electrode material. Multiple electrical conduction mechanisms control the leakage current of such switching devices, including trap-controlled space-charge, ballistic, Ohmic, and Fowler-Nordheim tunneling effects. The transition between electrical conduction states is also linked to the switching (SET-RESET) process. This is the first report of ballistic conduction in research into resistive random-access memory. The associated resistive switching mechanisms are also discussed.

  8. Low-energy Resistive Random Access Memory Devices with No Need for a Compliance Current

    PubMed Central

    Xu, Zedong; Yu, Lina; Wu, Yong; Dong, Chang; Deng, Ning; Xu, Xiaoguang; Miao, J.; Jiang, Yong

    2015-01-01

    A novel resistive random access memory device is designed with SrTiO3/ La2/3Sr1/3MnO3 (LSMO)/MgAl2O4 (MAO)/Cu structure, in which metallic epitaxial LSMO is employed as the bottom electrode rather than traditional metal materials. In this device, the critical external compliance current is no longer necessary due to the high self-resistance of LSMO. The LMSO bottom electrode can act as a series resistor to offer a compliance current during the set process. Besides, the device also has excellent switching features which are originated in the formation of Cu filaments under external voltage. Therefore it provides the possibility of reducing power consumption and accelerating the commercialization of resistive switching devices. PMID:25982101

  9. Microstructural transitions in resistive random access memory composed of molybdenum oxide with copper during switching cycles.

    PubMed

    Arita, Masashi; Ohno, Yuuki; Murakami, Yosuke; Takamizawa, Keisuke; Tsurumaki-Fukuchi, Atsushi; Takahashi, Yasuo

    2016-08-21

    The switching operation of a Cu/MoOx/TiN resistive random access memory (ReRAM) device was investigated using in situ transmission electron microscopy (TEM), where the TiN surface was slightly oxidized (ox-TiN). The relationship between the switching properties and the dynamics of the ReRAM microstructure was confirmed experimentally. The growth and/or shrinkage of the conductive filament (CF) can be classified into two set modes and two reset modes. These switching modes depend on the device's switching history, factors such as the amount of Cu inclusions in the MoOx layer and the CF geometry. High currents are needed to produce an observable change in the CF. However, sharp and stable switching behaviour can be achieved without requiring such a major change. The local region around the CF is thought to contribute to the ReRAM switching process. PMID:27456192

  10. Low-energy Resistive Random Access Memory Devices with No Need for a Compliance Current

    NASA Astrophysics Data System (ADS)

    Xu, Zedong; Yu, Lina; Wu, Yong; Dong, Chang; Deng, Ning; Xu, Xiaoguang; Miao, J.; Jiang, Yong

    2015-05-01

    A novel resistive random access memory device is designed with SrTiO3/ La2/3Sr1/3MnO3 (LSMO)/MgAl2O4 (MAO)/Cu structure, in which metallic epitaxial LSMO is employed as the bottom electrode rather than traditional metal materials. In this device, the critical external compliance current is no longer necessary due to the high self-resistance of LSMO. The LMSO bottom electrode can act as a series resistor to offer a compliance current during the set process. Besides, the device also has excellent switching features which are originated in the formation of Cu filaments under external voltage. Therefore it provides the possibility of reducing power consumption and accelerating the commercialization of resistive switching devices.

  11. Detection mechanisms employing single event upsets in dynamic random access memories used as radiation sensors

    NASA Astrophysics Data System (ADS)

    Darambara, D. G.; Spyrou, N. M.

    1994-12-01

    A hardware system is being designed and constructed for the detection of neutrons, with a view to using it in neutron imaging and elemental analysis. A feasibility study was initially carried out to demonstrate that dynamic Random Access Memories (dRAMs) can be used as heavy charged particle detectors and furthermore be made sensitive to neutrons. We are interested, however, in constructing a detector that will be position sensitive, and hence carried out experiments to investigate the relative sensitivity of specific elements within the dRAM chips. The findings from these initial system tests highlight the usefulness of such a device as a position sensitive radiation detector. This paper aims to explain and give a review of most aspects concerning the soft error (SE) performance using dRAM as a radiation sensor.

  12. Electrical Characterization of the RCA CDP1822SD Random Access Memory, Volume 1, Appendix a

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    Electrical characteristization tests were performed on 35 RCA CDP1822SD, 256-by-4-bit, CMOS, random access memories. The tests included three functional tests, AC and DC parametric tests, a series of schmoo plots, rise/fall time screening, and a data retention test. All tests were performed on an automated IC test system with temperatures controlled by a thermal airstream unit. All the functional tests, the data retention test, and the AC and DC parametric tests were performed at ambient temperatures of 25 C, -20 C, -55 C, 85 C, and 125 C. The schmoo plots were performed at ambient temperatures of 25 C, -55 C, and 125 C. The data retention test was performed at 25 C. Five devices failed one or more functional tests and four of these devices failed to meet the expected limits of a number of AC parametric tests. Some of the schmoo plots indicated a small degree of interaction between parameters.

  13. Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

    NASA Astrophysics Data System (ADS)

    Ohsawa, Takashi; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

    2014-01-01

    Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell’s design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 × 103 cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70 mA averaged in 15 ns write cycles at Vdd = 0.9 V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells’ subthreshold leakage.

  14. Conductive-bridging random access memory: challenges and opportunity for 3D architecture.

    PubMed

    Jana, Debanjan; Roy, Sourav; Panja, Rajeswar; Dutta, Mrinmoy; Rahaman, Sheikh Ziaur; Mahapatra, Rajat; Maikap, Siddheswar

    2015-01-01

    The performances of conductive-bridging random access memory (CBRAM) have been reviewed for different switching materials such as chalcogenides, oxides, and bilayers in different structures. The structure consists of an inert electrode and one oxidized electrode of copper (Cu) or silver (Ag). The switching mechanism is the formation/dissolution of a metallic filament in the switching materials under external bias. However, the growth dynamics of the metallic filament in different switching materials are still debated. All CBRAM devices are switching under an operation current of 0.1 μA to 1 mA, and an operation voltage of ±2 V is also needed. The device can reach a low current of 5 pA; however, current compliance-dependent reliability is a challenging issue. Although a chalcogenide-based material has opportunity to have better endurance as compared to an oxide-based material, data retention and integration with the complementary metal-oxide-semiconductor (CMOS) process are also issues. Devices with bilayer switching materials show better resistive switching characteristics as compared to those with a single switching layer, especially a program/erase endurance of >10(5) cycles with a high speed of few nanoseconds. Multi-level cell operation is possible, but the stability of the high resistance state is also an important reliability concern. These devices show a good data retention of >10(5) s at >85°C. However, more study is needed to achieve a 10-year guarantee of data retention for non-volatile memory application. The crossbar memory is benefited for high density with low power operation. Some CBRAM devices as a chip have been reported for proto-typical production. This review shows that operation current should be optimized for few microamperes with a maintaining speed of few nanoseconds, which will have challenges and also opportunities for three-dimensional (3D) architecture. PMID:25977660

  15. Metal oxide resistive random access memory based synaptic devices for brain-inspired computing

    NASA Astrophysics Data System (ADS)

    Gao, Bin; Kang, Jinfeng; Zhou, Zheng; Chen, Zhe; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan

    2016-04-01

    The traditional Boolean computing paradigm based on the von Neumann architecture is facing great challenges for future information technology applications such as big data, the Internet of Things (IoT), and wearable devices, due to the limited processing capability issues such as binary data storage and computing, non-parallel data processing, and the buses requirement between memory units and logic units. The brain-inspired neuromorphic computing paradigm is believed to be one of the promising solutions for realizing more complex functions with a lower cost. To perform such brain-inspired computing with a low cost and low power consumption, novel devices for use as electronic synapses are needed. Metal oxide resistive random access memory (ReRAM) devices have emerged as the leading candidate for electronic synapses. This paper comprehensively addresses the recent work on the design and optimization of metal oxide ReRAM-based synaptic devices. A performance enhancement methodology and optimized operation scheme to achieve analog resistive switching and low-energy training behavior are provided. A three-dimensional vertical synapse network architecture is proposed for high-density integration and low-cost fabrication. The impacts of the ReRAM synaptic device features on the performances of neuromorphic systems are also discussed on the basis of a constructed neuromorphic visual system with a pattern recognition function. Possible solutions to achieve the high recognition accuracy and efficiency of neuromorphic systems are presented.

  16. Does the mismatch negativity operate on a consciously accessible memory trace?

    PubMed

    Dykstra, Andrew R; Gutschalk, Alexander

    2015-11-01

    The extent to which the contents of short-term memory are consciously accessible is a fundamental question of cognitive science. In audition, short-term memory is often studied via the mismatch negativity (MMN), a change-related component of the auditory evoked response that is elicited by violations of otherwise regular stimulus sequences. The prevailing functional view of the MMN is that it operates on preattentive and even preconscious stimulus representations. We directly examined the preconscious notion of the MMN using informational masking and magnetoencephalography. Spectrally isolated and otherwise suprathreshold auditory oddball sequences were occasionally random rendered inaudible by embedding them in random multitone masker "clouds." Despite identical stimulation/task contexts and a clear representation of all stimuli in auditory cortex, MMN was only observed when the preceding regularity (that is, the standard stream) was consciously perceived. The results call into question the preconscious interpretation of MMN and raise the possibility that it might index partial awareness in the absence of overt behavior.

  17. Does the mismatch negativity operate on a consciously accessible memory trace?

    PubMed Central

    Dykstra, Andrew R.; Gutschalk, Alexander

    2015-01-01

    The extent to which the contents of short-term memory are consciously accessible is a fundamental question of cognitive science. In audition, short-term memory is often studied via the mismatch negativity (MMN), a change-related component of the auditory evoked response that is elicited by violations of otherwise regular stimulus sequences. The prevailing functional view of the MMN is that it operates on preattentive and even preconscious stimulus representations. We directly examined the preconscious notion of the MMN using informational masking and magnetoencephalography. Spectrally isolated and otherwise suprathreshold auditory oddball sequences were occasionally random rendered inaudible by embedding them in random multitone masker “clouds.” Despite identical stimulation/task contexts and a clear representation of all stimuli in auditory cortex, MMN was only observed when the preceding regularity (that is, the standard stream) was consciously perceived. The results call into question the preconscious interpretation of MMN and raise the possibility that it might index partial awareness in the absence of overt behavior. PMID:26702432

  18. Microstructural transitions in resistive random access memory composed of molybdenum oxide with copper during switching cycles

    NASA Astrophysics Data System (ADS)

    Arita, Masashi; Ohno, Yuuki; Murakami, Yosuke; Takamizawa, Keisuke; Tsurumaki-Fukuchi, Atsushi; Takahashi, Yasuo

    2016-08-01

    The switching operation of a Cu/MoOx/TiN resistive random access memory (ReRAM) device was investigated using in situ transmission electron microscopy (TEM), where the TiN surface was slightly oxidized (ox-TiN). The relationship between the switching properties and the dynamics of the ReRAM microstructure was confirmed experimentally. The growth and/or shrinkage of the conductive filament (CF) can be classified into two set modes and two reset modes. These switching modes depend on the device's switching history, factors such as the amount of Cu inclusions in the MoOx layer and the CF geometry. High currents are needed to produce an observable change in the CF. However, sharp and stable switching behaviour can be achieved without requiring such a major change. The local region around the CF is thought to contribute to the ReRAM switching process.The switching operation of a Cu/MoOx/TiN resistive random access memory (ReRAM) device was investigated using in situ transmission electron microscopy (TEM), where the TiN surface was slightly oxidized (ox-TiN). The relationship between the switching properties and the dynamics of the ReRAM microstructure was confirmed experimentally. The growth and/or shrinkage of the conductive filament (CF) can be classified into two set modes and two reset modes. These switching modes depend on the device's switching history, factors such as the amount of Cu inclusions in the MoOx layer and the CF geometry. High currents are needed to produce an observable change in the CF. However, sharp and stable switching behaviour can be achieved without requiring such a major change. The local region around the CF is thought to contribute to the ReRAM switching process. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr02602h

  19. Context controls access to working and reference memory in the pigeon (Columba livia).

    PubMed

    Roberts, William A; Macpherson, Krista; Strang, Caroline

    2016-01-01

    The interaction between working and reference memory systems was examined under conditions in which salient contextual cues were presented during memory retrieval. Ambient colored lights (red or green) bathed the operant chamber during the presentation of comparison stimuli in delayed matching-to-sample training (working memory) and during the presentation of the comparison stimuli as S+ and S- cues in discrimination training (reference memory). Strong competition between memory systems appeared when the same contextual cue appeared during working and reference memory training. When different contextual cues were used, however, working memory was completely protected from reference memory interference.

  20. Memory

    MedlinePlus

    ... it has to decide what is worth remembering. Memory is the process of storing and then remembering this information. There are different types of memory. Short-term memory stores information for a few ...

  1. Evaluation of Data Retention Characteristics for Ferroelectric Random Access Memories (FRAMs)

    NASA Technical Reports Server (NTRS)

    Sharma, Ashok K.; Teverovsky, Alexander

    2001-01-01

    Data retention and fatigue characteristics of 64 Kb lead zirconate titanate (PZT)-based Ferroelectric Random Access Memories (FRAMs) microcircuits manufactured by Ramtron were examined over temperature range from -85 C to +310 C for ceramic packaged parts and from -85 C to +175 C for plastic parts, during retention periods up to several thousand hours. Intrinsic failures, which were caused by a thermal degradation of the ferroelectric cells, occurred in ceramic parts after tens or hundreds hours of aging at temperatures above 200 C. The activation energy of the retention test failures was 1.05 eV and the extrapolated mean-time-to-failure (MTTF) at room temperature was estimated to be more than 280 years. Multiple write-read cycling (up to 3x10(exp 7)) during the fatigue testing of plastic and ceramic parts did not result in any parametric or functional failures. However, operational currents linearly decreased with the logarithm of number of cycles thus indicating fatigue process in PZT films. Plastic parts, that had more recent date code as compared to ceramic parts, appeared to be using die with improved process technology and showed significantly smaller changes in operational currents and data access times.

  2. Frontal activations associated with accessing and evaluating information in working memory: an fMRI study.

    PubMed

    Zhang, John X; Leung, Hoi-Chung; Johnson, Marcia K

    2003-11-01

    To investigate the involvement of frontal cortex in accessing and evaluating information in working memory, we used a variant of a Sternberg paradigm and compared brain activations between positive and negative responses (known to differentially tax access/evaluation processes). Participants remembered two trigrams in each trial and were then cued to discard one of them and maintain the other one as the target set. After a delay, a probe letter was presented and participants made decisions about whether or not it was in the target set. Several frontal areas--anterior cingulate (BA32), middle frontal gyrus (bilateral BA9, right BA10, and right BA46), and left inferior frontal gyrus (BA44/45)--showed increased activity when participants made correct negative responses relative to when they made correct positive responses. No areas activated significantly more for the positive responses than for the negative responses. It is suggested that the multiple frontal areas involved in the test phase of this task may reflect several component processes that underlie more general frontal functions. PMID:14642465

  3. Frontal activations associated with accessing and evaluating information in working memory: an fMRI study.

    PubMed

    Zhang, John X; Leung, Hoi-Chung; Johnson, Marcia K

    2003-11-01

    To investigate the involvement of frontal cortex in accessing and evaluating information in working memory, we used a variant of a Sternberg paradigm and compared brain activations between positive and negative responses (known to differentially tax access/evaluation processes). Participants remembered two trigrams in each trial and were then cued to discard one of them and maintain the other one as the target set. After a delay, a probe letter was presented and participants made decisions about whether or not it was in the target set. Several frontal areas--anterior cingulate (BA32), middle frontal gyrus (bilateral BA9, right BA10, and right BA46), and left inferior frontal gyrus (BA44/45)--showed increased activity when participants made correct negative responses relative to when they made correct positive responses. No areas activated significantly more for the positive responses than for the negative responses. It is suggested that the multiple frontal areas involved in the test phase of this task may reflect several component processes that underlie more general frontal functions.

  4. Three-Year-Old Children Can Access Their Own Memory to Guide Responses on a Visual Matching Task

    ERIC Educational Resources Information Center

    Balcomb, Frances K.; Gerken, LouAnn

    2008-01-01

    Many models of learning rely on accessing internal knowledge states. Yet, although infants and young children are recognized to be proficient learners, the ability to act on metacognitive information is not thought to develop until early school years. In the experiments reported here, 3.5-year-olds demonstrated memory-monitoring skills by…

  5. Concept of rewritable organic ferroelectric random access memory in two lateral transistors-in-one cell architecture

    NASA Astrophysics Data System (ADS)

    Kim, Min-Hoi; Lee, Gyu Jeong; Keum, Chang-Min; Lee, Sin-Doo

    2014-02-01

    We propose a concept of rewritable ferroelectric random access memory (RAM) with two lateral organic transistors-in-one cell architecture. Lateral integration of a paraelectric organic field-effect transistor (OFET), being a selection transistor, and a ferroelectric OFET as a memory transistor is realized using a paraelectric depolarizing layer (PDL) which is patterned on a ferroelectric insulator by transfer-printing. For the selection transistor, the key roles of the PDL are to reduce the dipolar strength and the surface roughness of the gate insulator, leading to the low memory on-off ratio and the high switching on-off current ratio. A new driving scheme preventing the crosstalk between adjacent memory cells is also demonstrated for the rewritable operation of the ferroelectric RAM.

  6. Memory.

    ERIC Educational Resources Information Center

    McKean, Kevin

    1983-01-01

    Discusses current research (including that involving amnesiacs and snails) into the nature of the memory process, differentiating between and providing examples of "fact" memory and "skill" memory. Suggests that three brain parts (thalamus, fornix, mammilary body) are involved in the memory process. (JN)

  7. Status and Prospects of ZnO-Based Resistive Switching Memory Devices.

    PubMed

    Simanjuntak, Firman Mangasa; Panda, Debashis; Wei, Kung-Hwa; Tseng, Tseung-Yuen

    2016-12-01

    In the advancement of the semiconductor device technology, ZnO could be a prospective alternative than the other metal oxides for its versatility and huge applications in different aspects. In this review, a thorough overview on ZnO for the application of resistive switching memory (RRAM) devices has been conducted. Various efforts that have been made to investigate and modulate the switching characteristics of ZnO-based switching memory devices are discussed. The use of ZnO layer in different structure, the different types of filament formation, and the different types of switching including complementary switching are reported. By considering the huge interest of transparent devices, this review gives the concrete overview of the present status and prospects of transparent RRAM devices based on ZnO. ZnO-based RRAM can be used for flexible memory devices, which is also covered here. Another challenge in ZnO-based RRAM is that the realization of ultra-thin and low power devices. Nevertheless, ZnO not only offers decent memory properties but also has a unique potential to be used as multifunctional nonvolatile memory devices. The impact of electrode materials, metal doping, stack structures, transparency, and flexibility on resistive switching properties and switching parameters of ZnO-based resistive switching memory devices are briefly compared. This review also covers the different nanostructured-based emerging resistive switching memory devices for low power scalable devices. It may give a valuable insight on developing ZnO-based RRAM and also should encourage researchers to overcome the challenges. PMID:27541816

  8. Status and Prospects of ZnO-Based Resistive Switching Memory Devices

    NASA Astrophysics Data System (ADS)

    Simanjuntak, Firman Mangasa; Panda, Debashis; Wei, Kung-Hwa; Tseng, Tseung-Yuen

    2016-08-01

    In the advancement of the semiconductor device technology, ZnO could be a prospective alternative than the other metal oxides for its versatility and huge applications in different aspects. In this review, a thorough overview on ZnO for the application of resistive switching memory (RRAM) devices has been conducted. Various efforts that have been made to investigate and modulate the switching characteristics of ZnO-based switching memory devices are discussed. The use of ZnO layer in different structure, the different types of filament formation, and the different types of switching including complementary switching are reported. By considering the huge interest of transparent devices, this review gives the concrete overview of the present status and prospects of transparent RRAM devices based on ZnO. ZnO-based RRAM can be used for flexible memory devices, which is also covered here. Another challenge in ZnO-based RRAM is that the realization of ultra-thin and low power devices. Nevertheless, ZnO not only offers decent memory properties but also has a unique potential to be used as multifunctional nonvolatile memory devices. The impact of electrode materials, metal doping, stack structures, transparency, and flexibility on resistive switching properties and switching parameters of ZnO-based resistive switching memory devices are briefly compared. This review also covers the different nanostructured-based emerging resistive switching memory devices for low power scalable devices. It may give a valuable insight on developing ZnO-based RRAM and also should encourage researchers to overcome the challenges.

  9. Exploration of perpendicular magnetic anisotropy material system for application in spin transfer torque - Random access memory

    NASA Astrophysics Data System (ADS)

    Natarajarathinam, Anusha

    Perpendicular magnetic anisotropy (PMA) materials have unique advantages when used in magnetic tunnel junctions (MTJ) which are the most critical part of spin-torque transfer random access memory devices (STT-RAMs) that are being researched intensively as future non-volatile memory technology. They have high magnetoresistance which improves their sensitivity. The STT-RAM has several advantages over competing technologies, for instance, low power consumption, non-volatility, ultra-fast read and write speed and high endurance. In personal computers, it can replace SRAM for high-speed applications, Flash for non-volatility, and PSRAM and DRAM for high-speed program execution. The main aim of this research is to identify and optimize the best perpendicular magnetic anisotropy (PMA) material system for application to STT-RAM technology. Preliminary search for perpendicular magnetic anisotropy (PMA) materials for pinned layer for MTJs started with the exploration and optimization of crystalline alloys such as Co50Pd50 alloy, Mn50Al50 and amorphous alloys such as Tb21Fe72Co7 and are first presented in this work. Further optimization includes the study of Co/[Pd/Pt]x multilayers (ML), and the development of perpendicular synthetic antiferromagnets (SAF) utilizing these multilayers. Focused work on capping and seed layers to evaluate interfacial perpendicular anisotropy in free layers for pMTJs is then discussed. Optimization of the full perpendicular magnetic tunnel junction (pMTJ) includes the CoFeB/MgO/CoFeB trilayer coupled to a pinned/pinning layer with perpendicular Co/[Pd/Pt]x SAF and a thin Ta seeded CoFeB free layer. Magnetometry, simulations, annealing studies, transport measurements and TEM analysis on these samples will then be presented.

  10. Colossal Electroresistive Properties Of CSD Grown Pr{sub 0.7}Ca{sub 0.3}MnO{sub 3} Films For Nonvolatile Memory Applications

    SciTech Connect

    Bhavsar, K. H.; Joshi, U. S.

    2010-12-01

    Colossal electroresistance effects upon application of electric field in perovskite oxide Pr{sub 0.7}Ca{sub 0.3}MnO{sub 3}(PCMO) thin films, which is a promising candidate for resistance random access memory (RRAM) device have been investigated. Nanocrystalline PCMO films were grown on SiO{sub 2} substrates by chemical solution deposition and crystallized at 700 deg. C under different gas atmospheres. Four terminal current voltage characteristics of Ag/PCMO/Ag planar geometry exhibited a sharp transition from a low resistance state (LRS) to a high resistance state (HRS) with a resistance switching ratio of as high as 1100% at room temperature. Nonvolatility and high retention was confirmed by electric pulse induced resistive switching measurements. The resistance switching ratios were found to depend on the annealing conditions, suggesting an interaction between the nonlattice oxygen and oxygen vacancies and/or the cationic vacancy.

  11. Solution-processed carbon nanotube thin-film complementary static random access memory

    NASA Astrophysics Data System (ADS)

    Geier, Michael L.; McMorrow, Julian J.; Xu, Weichao; Zhu, Jian; Kim, Chris H.; Marks, Tobin J.; Hersam, Mark C.

    2015-11-01

    Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties, making them one of the most promising candidates for solution-processable, high-performance integrated circuits. In particular, advances in the enrichment of high-purity semiconducting SWCNTs have enabled recent circuit demonstrations including synchronous digital logic, flexible electronics and high-frequency applications. However, due to the stringent requirements of the transistors used in complementary metal-oxide-semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.

  12. Multilevel Thermally Assisted Magnetoresistive Random-Access Memory Based on Exchange-Biased Vortex Configurations

    NASA Astrophysics Data System (ADS)

    de Araujo, C. I. L.; Alves, S. G.; Buda-Prejbeanu, L. D.; Dieny, B.

    2016-08-01

    A concept of multilevel thermally assisted magnetoresistive random-access memory is proposed and investigated by micromagnetic simulations. The storage cells are magnetic tunnel junctions in which the storage layer is exchange biased and in a vortex configuration. The reference layer is an unpinned soft magnetic layer. The stored information is encoded via the position of the vortex core in the storage layer. This position can be varied along two degrees of freedom: the radius and the in-plane angle. The information is read out from the amplitude and phase of the tunnel magnetoresistance signal obtained by applying a rotating field on the cell without heating the cell. Various configurations are compared in which the soft reference layer consists of either a simple ferromagnetic layer or a synthetic antiferromagnetic sandwich (SAF). Among those, the most practical one comprises a SAF reference layer in which the magnetostatic interaction between the SAF and storage layer is minimized. This type of cell should allow one to store at least 40 different states per cell representing more than five bits per cell.

  13. Solution-processed carbon nanotube thin-film complementary static random access memory.

    PubMed

    Geier, Michael L; McMorrow, Julian J; Xu, Weichao; Zhu, Jian; Kim, Chris H; Marks, Tobin J; Hersam, Mark C

    2015-11-01

    Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties, making them one of the most promising candidates for solution-processable, high-performance integrated circuits. In particular, advances in the enrichment of high-purity semiconducting SWCNTs have enabled recent circuit demonstrations including synchronous digital logic, flexible electronics and high-frequency applications. However, due to the stringent requirements of the transistors used in complementary metal-oxide-semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. PMID:26344184

  14. Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 1

    NASA Technical Reports Server (NTRS)

    Klute, A.

    1979-01-01

    Electrical characterization and qualification tests were performed on the RCA MWS5001D, 1024 by 1-bit, CMOS, random access memory. Characterization tests were performed on five devices. The tests included functional tests, AC parametric worst case pattern selection test, determination of worst-case transition for setup and hold times and a series of schmoo plots. The qualification tests were performed on 32 devices and included a 2000 hour burn in with electrical tests performed at 0 hours and after 168, 1000, and 2000 hours of burn in. The tests performed included functional tests and AC and DC parametric tests. All of the tests in the characterization phase, with the exception of the worst-case transition test, were performed at ambient temperatures of 25, -55 and 125 C. The worst-case transition test was performed at 25 C. The preburn in electrical tests were performed at 25, -55, and 125 C. All burn in endpoint tests were performed at 25, -40, -55, 85, and 125 C.

  15. Flexible conductive-bridging random-access-memory cell vertically stacked with top Ag electrode, PEO, PVK, and bottom Pt electrode.

    PubMed

    Seung, Hyun-Min; Kwon, Kyoung-Cheol; Lee, Gon-Sub; Park, Jea-Gun

    2014-10-31

    Flexible conductive-bridging random-access-memory (RAM) cells were fabricated with a cross-bar memory cell stacked with a top Ag electrode, conductive polymer (poly(n-vinylcarbazole): PVK), electrolyte (polyethylene oxide: PEO), bottom Pt electrode, and flexible substrate (polyethersulfone: PES), exhibiting the bipolar switching behavior of resistive random access memory (ReRAM). The cell also exhibited bending-fatigue-free nonvolatile memory characteristics: i.e., a set voltage of 1.0 V, a reset voltage of -1.6 V, retention time of >1 × 10(5) s with a memory margin of 9.2 × 10(5), program/erase endurance cycles of >10(2) with a memory margin of 8.4 × 10(5), and bending-fatigue-free cycles of ∼1 × 10(3) with a memory margin (I(on)/I(off)) of 3.3 × 10(5). PMID:25297517

  16. Flexible conductive-bridging random-access-memory cell vertically stacked with top Ag electrode, PEO, PVK, and bottom Pt electrode

    NASA Astrophysics Data System (ADS)

    Seung, Hyun-Min; Kwon, Kyoung-Cheol; Lee, Gon-Sub; Park, Jea-Gun

    2014-10-01

    Flexible conductive-bridging random-access-memory (RAM) cells were fabricated with a cross-bar memory cell stacked with a top Ag electrode, conductive polymer (poly(n-vinylcarbazole): PVK), electrolyte (polyethylene oxide: PEO), bottom Pt electrode, and flexible substrate (polyethersulfone: PES), exhibiting the bipolar switching behavior of resistive random access memory (ReRAM). The cell also exhibited bending-fatigue-free nonvolatile memory characteristics: i.e., a set voltage of 1.0 V, a reset voltage of -1.6 V, retention time of >1 × 105 s with a memory margin of 9.2 × 105, program/erase endurance cycles of >102 with a memory margin of 8.4 × 105, and bending-fatigue-free cycles of ˜1 × 103 with a memory margin (Ion/Ioff) of 3.3 × 105.

  17. High-performance bilayer flexible resistive random access memory based on low-temperature thermal atomic layer deposition

    PubMed Central

    2013-01-01

    We demonstrated a flexible resistive random access memory device through a low-temperature atomic layer deposition process. The device is composed of an HfO2/Al2O3-based functional stack on an indium tin oxide-coated polyethylene terephthalate substrate. After the initial reset operation, the device exhibits a typical bipolar, reliable, and reproducible resistive switching behavior. After a 104-s retention time, the memory window of the device is still in accordance with excellent thermal stability, and a 10-year usage is still possible with the resistance ratio larger than 10 at room temperature and at 85°C. In addition, the operation speed of the device was estimated to be 500 ns for the reset operation and 800 ns for the set operation, which is fast enough for the usage of the memories in flexible circuits. Considering the excellent performance of the device fabricated by low-temperature atomic layer deposition, the process may promote the potential applications of oxide-based resistive random access memory in flexible integrated circuits. PMID:23421424

  18. Encoding and retrieval processes involved in the access of source information in the absence of item memory.

    PubMed

    Ball, B Hunter; DeWitt, Michael R; Knight, Justin B; Hicks, Jason L

    2014-09-01

    The current study sought to examine the relative contributions of encoding and retrieval processes in accessing contextual information in the absence of item memory using an extralist cuing procedure in which the retrieval cues used to query memory for contextual information were related to the target item but never actually studied. In Experiments 1 and 2, participants studied 1 category member (e.g., onion) from a variety of different categories and at test were presented with an unstudied category label (e.g., vegetable) to probe memory for item and source information. In Experiments 3 and 4, 1 member of unidirectional (e.g., credit or card) or bidirectional (e.g., salt or pepper) associates was studied, whereas the other unstudied member served as a test probe. When recall failed, source information was accessible only when items were processed deeply during encoding (Experiments 1 and 2) and when there was strong forward associative strength between the retrieval cue and target (Experiments 3 and 4). These findings suggest that a retrieval probe diagnostic of semantically related item information reinstantiates information bound in memory during encoding that results in reactivation of associated contextual information, contingent upon sufficient learning of the item itself and the association between the item and its context information.

  19. ViSA: a neurodynamic model for visuo-spatial working memory, attentional blink, and conscious access.

    PubMed

    Simione, Luca; Raffone, Antonino; Wolters, Gezinus; Salmas, Paola; Nakatani, Chie; Belardinelli, Marta Olivetti; van Leeuwen, Cees

    2012-10-01

    Two separate lines of study have clarified the role of selectivity in conscious access to visual information. Both involve presenting multiple targets and distracters: one simultaneously in a spatially distributed fashion, the other sequentially at a single location. To understand their findings in a unified framework, we propose a neurodynamic model for Visual Selection and Awareness (ViSA). ViSA supports the view that neural representations for conscious access and visuo-spatial working memory are globally distributed and are based on recurrent interactions between perceptual and access control processors. Its flexible global workspace mechanisms enable a unitary account of a broad range of effects: It accounts for the limited storage capacity of visuo-spatial working memory, attentional cueing, and efficient selection with multi-object displays, as well as for the attentional blink and associated sparing and masking effects. In particular, the speed of consolidation for storage in visuo-spatial working memory in ViSA is not fixed but depends adaptively on the input and recurrent signaling. Slowing down of consolidation due to weak bottom-up and recurrent input as a result of brief presentation and masking leads to the attentional blink. Thus, ViSA goes beyond earlier 2-stage and neuronal global workspace accounts of conscious processing limitations.

  20. Towards developing a compact model for magnetization switching in straintronics magnetic random access memory devices

    NASA Astrophysics Data System (ADS)

    Barangi, Mahmood; Erementchouk, Mikhail; Mazumder, Pinaki

    2016-08-01

    Strain-mediated magnetization switching in a magnetic tunneling junction (MTJ) by exploiting a combination of piezoelectricity and magnetostriction has been proposed as an energy efficient alternative to spin transfer torque (STT) and field induced magnetization switching methods in MTJ-based magnetic random access memories (MRAM). Theoretical studies have shown the inherent advantages of strain-assisted switching, and the dynamic response of the magnetization has been modeled using the Landau-Lifshitz-Gilbert (LLG) equation. However, an attempt to use LLG for simulating dynamics of individual elements in large-scale simulations of multi-megabyte straintronics MRAM leads to extremely time-consuming calculations. Hence, a compact analytical solution, predicting the flipping delay of the magnetization vector in the nanomagnet under stress, combined with a liberal approximation of the LLG dynamics in the straintronics MTJ, can lead to a simplified model of the device suited for fast large-scale simulations of multi-megabyte straintronics MRAMs. In this work, a tensor-based approach is developed to study the dynamic behavior of the stressed nanomagnet. First, using the developed method, the effect of stress on the switching behavior of the magnetization is investigated to realize the margins between the underdamped and overdamped regimes. The latter helps the designer realize the oscillatory behavior of the magnetization when settling along the minor axis, and the dependency of oscillations on the stress level and the damping factor. Next, a theoretical model to predict the flipping delay of the magnetization vector is developed and tested against LLG-based numerical simulations to confirm the accuracy of findings. Lastly, the obtained delay is incorporated into the approximate solutions of the LLG dynamics, in order to create a compact model to liberally and quickly simulate the magnetization dynamics of the MTJ under stress. Using the developed delay equation, the

  1. Evaluating OpenSHMEM Explicit Remote Memory Access Operations and Merged Requests

    SciTech Connect

    Boehm, Swen; Pophale, Swaroop S; Gorentla Venkata, Manjunath

    2016-01-01

    The OpenSHMEM Library Specification has evolved consid- erably since version 1.0. Recently, non-blocking implicit Remote Memory Access (RMA) operations were introduced in OpenSHMEM 1.3. These provide a way to achieve better overlap between communication and computation. However, the implicit non-blocking operations do not pro- vide a separate handle to track and complete the individual RMA opera- tions. They are guaranteed to be completed after either a shmem quiet(), shmem barrier() or a shmem barrier all() is called. These are global com- pletion and synchronization operations. Though this semantic is expected to achieve a higher message rate for the applications, the drawback is that it does not allow fine-grained control over the completion of RMA operations. In this paper, first, we introduce non-blocking RMA operations with requests, where each operation has an explicit request to track and com- plete the operation. Second, we introduce interfaces to merge multiple requests into a single request handle. The merged request tracks multiple user-selected RMA operations, which provides the flexibility of tracking related communication operations with one request handle. Lastly, we explore the implications in terms of performance, productivity, usability and the possibility of defining different patterns of communication via merging of requests. Our experimental results show that a well designed and implemented OpenSHMEM stack can hide the overhead of allocating and managing the requests. The latency of RMA operations with requests is similar to blocking and implicit non-blocking RMA operations. We test our implementation with the Scalable Synthetic Compact Applications (SSCA #1) benchmark and observe that using RMA operations with requests and merging of these requests outperform the implementation using blocking RMA operations and implicit non-blocking operations by 49% and 74% respectively.

  2. PREFACE: Emerging non-volatile memories: magnetic and resistive technologies Emerging non-volatile memories: magnetic and resistive technologies

    NASA Astrophysics Data System (ADS)

    Dieny, B.; Jagadish, Chennupati

    2013-02-01

    In 2010, the International Technology Roadmap for Semiconductors (ITRS) published an assessment of the potential and maturity of selected emerging research on memory technologies. Eight different technologies of non-volatile memories were compared (ferroelectric gate field-effect transistor, nano-electro-mechanical switch, spin-transfer torque random access memories (STTRAM), various types of resistive RAM, in particular redox RAM, nanothermal phase change RAM, electronic effects RAM, macromolecular memories and molecular RAM). In this report, spin-transfer torque MRAM and redox RRAM were identified as two emerging memory technologies recommended for accelerated research and development leading to scaling and commercialization of non-volatile RAM to and beyond the 16nm generation. Nowadays, there is an intense research and development effort in microelectronics on these two technologies, one based on spintronic phenomena (tunnel magnetoresistance and spin-transfer torque), the other based on migration of vacancies or ions in an insulating matrix driven by oxydo-reduction potentials. Both technologies could be used for standalone or embedded applications. In this context, it appeared timely to publish a cluster of review articles related to these two technologies. In this cluster, the first two articles introduce the general principles of spin-transfer torque RAM and of thermally assisted RAM. The third presents a broader range of applications for this integrated CMOS/magnetic tunnel junction technology for low-power electronics. The fourth paper presents more advanced research on voltage control of magnetization switching with the aim of dramatically reducing the write energy in MRAM. The last two papers deal with two categories of resistive RAM, one based on the migration of cations, the other one based on nanowires. We thank all the authors and reviewers for their contribution to this cluster issue. Our special thanks are due to Dr Olivia Roche, Publisher, and Dr

  3. Organizational Factors in Human Memory: Implications for Library Organization and Access Systems.

    ERIC Educational Resources Information Center

    Najarian, Suzanne E.

    1981-01-01

    Examines psychological studies on memory and learning for what they reveal about human categorizing processes and the organizing principles and limitations of human memory. Findings suggest considerations for the design of information systems that would take conceptual organization of knowledge into account. (FM)

  4. Contexts and Control Operations Used in Accessing List-Specific, Generalized, and Semantic Memories

    ERIC Educational Resources Information Center

    Humphreys, Michael S.; Murray, Krista L.; Maguire, Angela M.

    2009-01-01

    The human ability to focus memory retrieval operations on a particular list, episode or memory structure has not been fully appreciated or documented. In Experiment 1-3, we make it increasingly difficult for participants to switch between a less recent list (multiple study opportunities), and a more recent list (single study opportunity). Task…

  5. Retrieval practice enhances the accessibility but not the quality of memory.

    PubMed

    Sutterer, David W; Awh, Edward

    2016-06-01

    Numerous studies have demonstrated that retrieval from long-term memory (LTM) can enhance subsequent memory performance, a phenomenon labeled the retrieval practice effect. However, the almost exclusive reliance on categorical stimuli in this literature leaves open a basic question about the nature of this improvement in memory performance. It has not yet been determined whether retrieval practice improves the probability of successful memory retrieval or the quality of the retrieved representation. To answer this question, we conducted three experiments using a mixture modeling approach (Zhang & Luck, 2008) that provides a measure of both the probability of recall and the quality of the recalled memories. Subjects attempted to memorize the color of 400 unique shapes. After every 10 images were presented, subjects either recalled the last 10 colors (the retrieval practice condition) by clicking on a color wheel with each shape as a retrieval cue or they participated in a control condition that involved no further presentations (Experiment 1) or restudy of the 10 shape/color associations (Experiments 2 and 3). Performance in a subsequent delayed recall test revealed a robust retrieval practice effect. Subjects recalled a significantly higher proportion of items that they had previously retrieved relative to items that were untested or that they had restudied. Interestingly, retrieval practice did not elicit any improvement in the precision of the retrieved memories. The same empirical pattern also was observed following delays of greater than 24 hours. Thus, retrieval practice increases the probability of successful memory retrieval but does not improve memory quality.

  6. Speed and Accuracy of Accessing Information in Working Memory: An Individual Differences Investigation of Focus Switching

    ERIC Educational Resources Information Center

    Unsworth, Nash; Engle, Randall W.

    2008-01-01

    Three experiments examined the nature of individual differences in switching the focus of attention in working memory. Participants performed 3 versions of a continuous counting task that required successive updating and switching between counts. Across all 3 experiments, individual differences in working memory span and fluid intelligence were…

  7. CMOS Interface Circuits for Spin Tunneling Junction Based Magnetic Random Access Memories

    SciTech Connect

    Ganesh Saripalli

    2002-12-31

    Magneto resistive memories (MRAM) are non-volatile memories which use magnetic instead of electrical structures to store data. These memories, apart from being non-volatile, offer a possibility to achieve densities better than DRAMs and speeds faster than SRAMs. MRAMs could potentially replace all computer memory RAM technologies in use today, leading to future applications like instan-on computers and longer battery life for pervasive devices. Such rapid development was made possible due to the recent discovery of large magnetoresistance in Spin tunneling junction devices. Spin tunneling junctions (STJ) are composite structures consisting of a thin insulating layer sandwiched between two magnetic layers. This thesis research is targeted towards these spin tunneling junction based Magnetic memories. In any memory, some kind of an interface circuit is needed to read the logic states. In this thesis, four such circuits are proposed and designed for Magnetic memories (MRAM). These circuits interface to the Spin tunneling junctions and act as sense amplifiers to read their magnetic states. The physical structure and functional characteristics of these circuits are discussed in this thesis. Mismatch effects on the circuits and proper design techniques are also presented. To demonstrate the functionality of these interface structures, test circuits were designed and fabricated in TSMC 0.35{micro} CMOS process. Also circuits to characterize the process mismatches were fabricated and tested. These results were then used in Matlab programs to aid in design process and to predict interface circuit's yields.

  8. Towards Terabit Memories

    NASA Astrophysics Data System (ADS)

    Hoefflinger, Bernd

    Memories have been the major yardstick for the continuing validity of Moore's law. In single-transistor-per-Bit dynamic random-access memories (DRAM), the number of bits per chip pretty much gives us the number of transistors. For decades, DRAM's have offered the largest storage capacity per chip. However, DRAM does not scale any longer, both in density and voltage, severely limiting its power efficiency to 10 fJ/b. A differential DRAM would gain four-times in density and eight-times in energy. Static CMOS RAM (SRAM) with its six transistors/cell is gaining in reputation because it scales well in cell size and operating voltage so that its fundamental advantage of speed, non-destructive read-out and low-power standby could lead to just 2.5 electrons/bit in standby and to a dynamic power efficiency of 2aJ/b. With a projected 2020 density of 16 Gb/cm², the SRAM would be as dense as normal DRAM and vastly better in power efficiency, which would mean a major change in the architecture and market scenario for DRAM versus SRAM. Non-volatile Flash memory have seen two quantum jumps in density well beyond the roadmap: Multi-Bit storage per transistor and high-density TSV (through-silicon via) technology. The number of electrons required per Bit on the storage gate has been reduced since their first realization in 1996 by more than an order of magnitude to 400 electrons/Bit in 2010 for a complexity of 32Gbit per chip at the 32 nm node. Chip stacking of eight chips with TSV has produced a 32GByte solid-state drive (SSD). A stack of 32 chips with 2 b/cell at the 16 nm node will reach a density of 2.5 Terabit/cm². Non-volatile memory with a density of 10 × 10 nm²/Bit is the target for widespread development. Phase-change memory (PCM) and resistive memory (RRAM) lead in cell density, and they will reach 20 Gb/cm² in 2D and higher with 3D chip stacking. This is still almost an order-of-magnitude less than Flash. However, their read-out speed is ~10-times faster, with as yet

  9. Oxide Defect Engineering Methods for Valence Change (VCM) Resistive Random Access Memories

    NASA Astrophysics Data System (ADS)

    Capulong, Jihan O.

    Electrical switching requirements for resistive random access memory (ReRAM) devices are multifaceted, based on device application. Thus, it is important to obtain an understanding of these switching properties and how they relate to the oxygen vacancy concentration and oxygen vacancy defects. Oxygen vacancy defects in the switching oxide of valence-change-based ReRAM (VCM ReRAM) play a significant role in device switching properties. Oxygen vacancies facilitate resistive switching as they form the conductive filament that changes the resistance state of the device. This dissertation will present two methods of modulating the defect concentration in VCM ReRAM composed of Pt/HfOx/Ti stack: 1) rapid thermal annealing (RTA) in Ar using different temperatures, and 2) doping using ion implantation under different dose levels. Metrology techniques such as x-ray diffractometry (XRD), x-ray photoelectron spectroscopy (XPS), and photoluminescence (PL) spectroscopy were utilized to characterize the HfOx switching oxide, which provided insight on the material properties and oxygen vacancy concentration in the oxide that was used to explain the changes in the electrical properties of the ReRAM devices. The resulting impact on the resistive switching characteristics of the devices, such as the forming voltage, set and reset threshold voltages, ON and OFF resistances, resistance ratio, and switching dispersion or uniformity were explored and summarized. Annealing in Ar showed significant impact on the forming voltage, with as much as 45% (from 22V to 12 V) of improvement, as the annealing temperature was increased. However, drawbacks of a higher oxide leakage and worse switching uniformity were seen with increasing annealing temperature. Meanwhile, doping the oxide by ion implantation showed significant effects on the resistive switching characteristics. Ta doping modulated the following switching properties with increasing dose: a) the reduction of the forming voltage, and Vset

  10. Effect of embedded metal nanocrystals on the resistive switching characteristics in NiN-based resistive random access memory cells

    SciTech Connect

    Yun, Min Ju; Kim, Hee-Dong; Man Hong, Seok; Hyun Park, Ju; Su Jeon, Dong; Geun Kim, Tae

    2014-03-07

    The metal nanocrystals (NCs) embedded-NiN-based resistive random access memory cells are demonstrated using several metal NCs (i.e., Pt, Ni, and Ti) with different physical parameters in order to investigate the metal NC's dependence on resistive switching (RS) characteristics. First, depending on the electronegativity of metal, the size of metal NCs is determined and this affects the operating current of memory cells. If metal NCs with high electronegativity are incorporated, the size of the NCs is reduced; hence, the operating current is reduced owing to the reduced density of the electric field around the metal NCs. Second, the potential wells are formed by the difference of work function between the metal NCs and active layer, and the barrier height of the potential wells affects the level of operating voltage as well as the conduction mechanism of metal NCs embedded memory cells. Therefore, by understanding these correlations between the active layer and embedded metal NCs, we can optimize the RS properties of metal NCs embedded memory cells as well as predict their conduction mechanisms.

  11. Set statistics in conductive bridge random access memory device with Cu/HfO{sub 2}/Pt structure

    SciTech Connect

    Zhang, Meiyun; Long, Shibing Wang, Guoming; Xu, Xiaoxin; Li, Yang; Liu, Qi; Lv, Hangbing; Liu, Ming; Lian, Xiaojuan; Miranda, Enrique; Suñé, Jordi

    2014-11-10

    The switching parameter variation of resistive switching memory is one of the most important challenges in its application. In this letter, we have studied the set statistics of conductive bridge random access memory with a Cu/HfO{sub 2}/Pt structure. The experimental distributions of the set parameters in several off resistance ranges are shown to nicely fit a Weibull model. The Weibull slopes of the set voltage and current increase and decrease logarithmically with off resistance, respectively. This experimental behavior is perfectly captured by a Monte Carlo simulator based on the cell-based set voltage statistics model and the Quantum Point Contact electron transport model. Our work provides indications for the improvement of the switching uniformity.

  12. Development, Demonstration, and Device Physics of Fet-Accessed One-Transistor Gallium Arsenide Dynamic Memory Technologies

    NASA Astrophysics Data System (ADS)

    Neudeck, Philip Gerold

    The introduction of digital GaAs into modern high -speed computing systems has led to an increasing demand for high-density memory in these GaAs technologies. To date, most of the memory development efforts in GaAs have been directed toward four- and six-transistor static RAM's, which consume substantial chip area and dissipate much static power resulting in limited single-chip GaAs storage capacities. As it has successfully done in silicon, a one-transistor dynamic RAM approach could alleviate these problems making higher density GaAs memories possible. This dissertation discusses theoretical and experimental work that presents the possibility for a high-speed, low-power, one-transistor dynamic RAM technology in GaAs. The two elements of the DRAM cell, namely the charge storage capacitor and the access field-effect transistor have been studied in detail. Isolated diode junction charge storage capacitors have demonstrated 30 minutes of storage time at room temperature with charge densities comparable to those obtained in planar silicon DRAM capacitors. GaAs JFET and MESFET technologies have been studied, and with careful device design and choice of proper operating voltages experimental results show that both can function as acceptable access transistors. One-transistor MESFET- and JFET-accessed DRAM cells have been fabricated and operated at room temperature and above with a standby power dissipation that is only a small fraction of the power dissipated by the best commercial GaAs static RAM cells. A 2 x 2 bit demonstration array was built and successfully operated at room temperature to demonstrate the addressable read/write capability of this new technology.

  13. Stream specificity and asymmetries in feature binding and content-addressable access in visual encoding and memory.

    PubMed

    Huynh, Duong L; Tripathy, Srimant P; Bedell, Harold E; Ögmen, Haluk

    2015-01-01

    Human memory is content addressable-i.e., contents of the memory can be accessed using partial information about the bound features of a stored item. In this study, we used a cross-feature cuing technique to examine how the human visual system encodes, binds, and retains information about multiple stimulus features within a set of moving objects. We sought to characterize the roles of three different features (position, color, and direction of motion, the latter two of which are processed preferentially within the ventral and dorsal visual streams, respectively) in the construction and maintenance of object representations. We investigated the extent to which these features are bound together across the following processing stages: during stimulus encoding, sensory (iconic) memory, and visual short-term memory. Whereas all features examined here can serve as cues for addressing content, their effectiveness shows asymmetries and varies according to cue-report pairings and the stage of information processing and storage. Position-based indexing theories predict that position should be more effective as a cue compared to other features. While we found a privileged role for position as a cue at the stimulus-encoding stage, position was not the privileged cue at the sensory and visual short-term memory stages. Instead, the pattern that emerged from our findings is one that mirrors the parallel processing streams in the visual system. This stream-specific binding and cuing effectiveness manifests itself in all three stages of information processing examined here. Finally, we find that the Leaky Flask model proposed in our previous study is applicable to all three features.

  14. Stream specificity and asymmetries in feature binding and content-addressable access in visual encoding and memory.

    PubMed

    Huynh, Duong L; Tripathy, Srimant P; Bedell, Harold E; Ögmen, Haluk

    2015-01-01

    Human memory is content addressable-i.e., contents of the memory can be accessed using partial information about the bound features of a stored item. In this study, we used a cross-feature cuing technique to examine how the human visual system encodes, binds, and retains information about multiple stimulus features within a set of moving objects. We sought to characterize the roles of three different features (position, color, and direction of motion, the latter two of which are processed preferentially within the ventral and dorsal visual streams, respectively) in the construction and maintenance of object representations. We investigated the extent to which these features are bound together across the following processing stages: during stimulus encoding, sensory (iconic) memory, and visual short-term memory. Whereas all features examined here can serve as cues for addressing content, their effectiveness shows asymmetries and varies according to cue-report pairings and the stage of information processing and storage. Position-based indexing theories predict that position should be more effective as a cue compared to other features. While we found a privileged role for position as a cue at the stimulus-encoding stage, position was not the privileged cue at the sensory and visual short-term memory stages. Instead, the pattern that emerged from our findings is one that mirrors the parallel processing streams in the visual system. This stream-specific binding and cuing effectiveness manifests itself in all three stages of information processing examined here. Finally, we find that the Leaky Flask model proposed in our previous study is applicable to all three features. PMID:26382005

  15. Asymmetric dual-gate-structured one-transistor dynamic random access memory cells for retention characteristics improvement

    NASA Astrophysics Data System (ADS)

    Kim, Hyungjin; Lee, Jong-Ho; Park, Byung-Gook

    2016-08-01

    One of the major concerns of one-transistor dynamic random access memory (1T-DRAM) is poor retention time. In this letter, a 1T-DRAM cell with two separated asymmetric gates was fabricated and evaluated to improve sensing margin and retention characteristics. It was observed that significantly enhanced sensing margin and retention time over 1 s were obtained using a negatively biased second gate and trapped electrons in the nitride layer because of increased hole capacity in the floating body. These findings indicate that the proposed device could serve as a promising candidate for overcoming retention issues of 1T-DRAM cells.

  16. Towards scalable parellelism in Monte Carlo particle transport codes using remote memory access

    SciTech Connect

    Romano, Paul K; Brown, Forrest B; Forget, Benoit

    2010-01-01

    One forthcoming challenge in the area of high-performance computing is having the ability to run large-scale problems while coping with less memory per compute node. In this work, they investigate a novel data decomposition method that would allow Monte Carlo transport calculations to be performed on systems with limited memory per compute node. In this method, each compute node remotely retrieves a small set of geometry and cross-section data as needed and remotely accumulates local tallies when crossing the boundary of the local spatial domain. initial results demonstrate that while the method does allow large problems to be run in a memory-limited environment, achieving scalability may be difficult due to inefficiencies in the current implementation of RMA operations.

  17. HfO2/Al2O3 multilayer for RRAM arrays: a technique to improve tail-bit retention.

    PubMed

    Huang, Xueyao; Wu, Huaqiang; Bin Gao; Sekar, Deepak C; Dai, Lingjun; Kellam, Mark; Bronner, Gary; Deng, Ning; Qian, He

    2016-09-30

    In this work, the HfO2/Al2O3 multilayer structure is applied for RRAM arrays. Compared to HfO2 RRAM, the data retention failure of tail bits is suppressed significantly, especially for the high resistance state (HRS). The retention of tail bits is studied in detail by temperature simulation and crystallization analysis. We attribute the improvement of tail-bit retention to the decreased oxygen ion diffusivity caused by the Al2O3 layer. Furthermore, the HfO2/Al2O3 multilayer structure exhibits higher crystallization temperature, thus leading to fewer grain boundaries around the filament during the operations. With fewer grain boundaries, oxygen ion diffusion is suppressed, leading to fewer tail bits and better retention. PMID:27537613

  18. HfO2/Al2O3 multilayer for RRAM arrays: a technique to improve tail-bit retention

    NASA Astrophysics Data System (ADS)

    Huang, Xueyao; Wu, Huaqiang; Gao, Bin; Sekar, Deepak C.; Dai, Lingjun; Kellam, Mark; Bronner, Gary; Deng, Ning; Qian, He

    2016-09-01

    In this work, the HfO2/Al2O3 multilayer structure is applied for RRAM arrays. Compared to HfO2 RRAM, the data retention failure of tail bits is suppressed significantly, especially for the high resistance state (HRS). The retention of tail bits is studied in detail by temperature simulation and crystallization analysis. We attribute the improvement of tail-bit retention to the decreased oxygen ion diffusivity caused by the Al2O3 layer. Furthermore, the HfO2/Al2O3 multilayer structure exhibits higher crystallization temperature, thus leading to fewer grain boundaries around the filament during the operations. With fewer grain boundaries, oxygen ion diffusion is suppressed, leading to fewer tail bits and better retention.

  19. Perpendicular spin transfer torque magnetic random access memories with high spin torque efficiency and thermal stability for embedded applications (invited)

    SciTech Connect

    Thomas, Luc Jan, Guenole; Zhu, Jian; Liu, Huanlong; Lee, Yuan-Jen; Le, Son; Tong, Ru-Ying; Pi, Keyu; Wang, Yu-Jen; Shen, Dongna; He, Renren; Haq, Jesmin; Teng, Jeffrey; Lam, Vinh; Huang, Kenlin; Zhong, Tom; Torng, Terry; Wang, Po-Kang

    2014-05-07

    Magnetic random access memories based on the spin transfer torque phenomenon (STT-MRAMs) have become one of the leading candidates for next generation memory applications. Among the many attractive features of this technology are its potential for high speed and endurance, read signal margin, low power consumption, scalability, and non-volatility. In this paper, we discuss our recent results on perpendicular STT-MRAM stack designs that show STT efficiency higher than 5 k{sub B}T/μA, energy barriers higher than 100 k{sub B}T at room temperature for sub-40 nm diameter devices, and tunnel magnetoresistance higher than 150%. We use both single device data and results from 8 Mb array to demonstrate data retention sufficient for automotive applications. Moreover, we also demonstrate for the first time thermal stability up to 400 °C exceeding the requirement of Si CMOS back-end processing, thus opening the realm of non-volatile embedded memory to STT-MRAM technology.

  20. Magnetoelectric assisted 180° magnetization switching for electric field addressable writing in magnetoresistive random-access memory.

    PubMed

    Wang, Zhiguang; Zhang, Yue; Wang, Yaojin; Li, Yanxi; Luo, Haosu; Li, Jiefang; Viehland, Dwight

    2014-08-26

    Magnetization-based memories, e.g., hard drive and magnetoresistive random-access memory (MRAM), use bistable magnetic domains in patterned nanomagnets for information recording. Electric field (E) tunable magnetic anisotropy can lower the energy barrier between two distinct magnetic states, promising reduced power consumption and increased recording density. However, integration of magnetoelectric heterostructure into MRAM is a highly challenging task owing to the particular architecture requirements of each component. Here, we show an epitaxial growth of self-assembled CoFe2O4 nanostripes with bistable in-plane magnetizations on Pb(Mg,Nb)O3-PbTiO3 (PMN-PT) substrates, where the magnetic switching can be triggered by E-induced elastic strain effect. An unprecedented magnetic coercive field change of up to 600 Oe was observed with increasing E. A near 180° magnetization rotation can be activated by E in the vicinity of the magnetic coercive field. These findings might help to solve the 1/2-selection problem in traditional MRAM by providing reduced magnetic coercive field in E field selected memory cells. PMID:25093903

  1. Perpendicular spin transfer torque magnetic random access memories with high spin torque efficiency and thermal stability for embedded applications (invited)

    NASA Astrophysics Data System (ADS)

    Thomas, Luc; Jan, Guenole; Zhu, Jian; Liu, Huanlong; Lee, Yuan-Jen; Le, Son; Tong, Ru-Ying; Pi, Keyu; Wang, Yu-Jen; Shen, Dongna; He, Renren; Haq, Jesmin; Teng, Jeffrey; Lam, Vinh; Huang, Kenlin; Zhong, Tom; Torng, Terry; Wang, Po-Kang

    2014-05-01

    Magnetic random access memories based on the spin transfer torque phenomenon (STT-MRAMs) have become one of the leading candidates for next generation memory applications. Among the many attractive features of this technology are its potential for high speed and endurance, read signal margin, low power consumption, scalability, and non-volatility. In this paper, we discuss our recent results on perpendicular STT-MRAM stack designs that show STT efficiency higher than 5 kBT/μA, energy barriers higher than 100 kBT at room temperature for sub-40 nm diameter devices, and tunnel magnetoresistance higher than 150%. We use both single device data and results from 8 Mb array to demonstrate data retention sufficient for automotive applications. Moreover, we also demonstrate for the first time thermal stability up to 400 °C exceeding the requirement of Si CMOS back-end processing, thus opening the realm of non-volatile embedded memory to STT-MRAM technology.

  2. [Co/Ni]-CoFeB hybrid free layer stack materials for high density magnetic random access memory applications

    NASA Astrophysics Data System (ADS)

    Liu, E.; Swerts, J.; Couet, S.; Mertens, S.; Tomczak, Y.; Lin, T.; Spampinato, V.; Franquet, A.; Van Elshocht, S.; Kar, G.; Furnemont, A.; De Boeck, J.

    2016-03-01

    Alternative free layer materials with high perpendicular anisotropy are researched to provide spin-transfer-torque magnetic random access memory stacks' sufficient thermal stability at critical dimensions of 20 nm and below. We demonstrate a high tunnel magetoresistance (TMR) MgO-based magnetic tunnel junction stack with a hybrid free layer design made of a [Co/Ni] multilayer and CoFeB. The seed material on which the [Co/Ni] multilayer is deposited determines its switching characteristics. When deposited on a Pt seed layer, soft magnetic switching behavior with high squareness is obtained. When deposited on a NiCr seed, the perpendicular anisotropy remains high, but the squareness is low and coercivity exceeds 1000 Oe. Interdiffusion of the seed material with the [Co/Ni] multilayers is found to be responsible for the different switching characteristics. In optimized stacks, a TMR of 165% and low resistance-area (RA) product of 7.0 Ω μm2 are attained for free layers with an effective perpendicular magnetic anisotropy energy of 1.25 erg/cm2, which suggests that the hybrid free layer materials may be a viable candidate for high density magnetic random access memory applications.

  3. Respecting Relations: Memory Access and Antecedent Retrieval in Incremental Sentence Processing

    ERIC Educational Resources Information Center

    Kush, Dave W.

    2013-01-01

    This dissertation uses the processing of anaphoric relations to probe how linguistic information is encoded in and retrieved from memory during real-time sentence comprehension. More specifically, the dissertation attempts to resolve a tension between the demands of a linguistic processor implemented in a general-purpose cognitive architecture and…

  4. Memory Retrieval Given Two Independent Cues: Cue Selection or Parallel Access?

    ERIC Educational Resources Information Center

    Rickard, Timothy C.; Bajic, Daniel

    2004-01-01

    A basic but unresolved issue in the study of memory retrieval is whether multiple independent cues can be used concurrently (i.e., in parallel) to recall a single, common response. A number of empirical results, as well as potentially applicable theories, suggest that retrieval can proceed in parallel, though Rickard (1997) set forth a model that…

  5. Hyperlink Format, Categorization Abilities and Memory Span as Contributors to Deaf Users Hypertext Access

    ERIC Educational Resources Information Center

    Farjardo, Inmaculada; Arfe, Barbara; Benedetti, Patrizia; Altoe, Gianmarco

    2008-01-01

    Sixty deaf and hearing students were asked to search for goods in a Hypertext Supermarket with either graphical or textual links of high typicality, frequency, and familiarity. Additionally, they performed a picture and word categorization task and two working memory span tasks (spatial and verbal). Results showed that deaf students were faster in…

  6. Cost-effective, transfer-free, flexible resistive random access memory using laser-scribed reduced graphene oxide patterning technology.

    PubMed

    Tian, He; Chen, Hong-Yu; Ren, Tian-Ling; Li, Cheng; Xue, Qing-Tang; Mohammad, Mohammad Ali; Wu, Can; Yang, Yi; Wong, H-S Philip

    2014-06-11

    Laser scribing is an attractive reduced graphene oxide (rGO) growth and patterning technology because the process is low-cost, time-efficient, transfer-free, and flexible. Various laser-scribed rGO (LSG) components such as capacitors, gas sensors, and strain sensors have been demonstrated. However, obstacles remain toward practical application of the technology where all the components of a system are fabricated using laser scribing. Memory components, if developed, will substantially broaden the application space of low-cost, flexible electronic systems. For the first time, a low-cost approach to fabricate resistive random access memory (ReRAM) using laser-scribed rGO as the bottom electrode is experimentally demonstrated. The one-step laser scribing technology allows transfer-free rGO synthesis directly on flexible substrates or non-flat substrates. Using this time-efficient laser-scribing technology, the patterning of a memory-array area up to 100 cm(2) can be completed in 25 min. Without requiring the photoresist coating for lithography, the surface of patterned rGO remains as clean as its pristine state. Ag/HfOx/LSG ReRAM using laser-scribing technology is fabricated in this work. Comprehensive electrical characteristics are presented including forming-free behavior, stable switching, reasonable reliability performance and potential for 2-bit storage per memory cell. The results suggest that laser-scribing technology can potentially produce more cost-effective and time-effective rGO-based circuits and systems for practical applications.

  7. Memories.

    ERIC Educational Resources Information Center

    Brand, Judith, Ed.

    1998-01-01

    This theme issue of the journal "Exploring" covers the topic of "memories" and describes an exhibition at San Francisco's Exploratorium that ran from May 22, 1998 through January 1999 and that contained over 40 hands-on exhibits, demonstrations, artworks, images, sounds, smells, and tastes that demonstrated and depicted the biological,…

  8. An energy-efficient SIMD DSP with multiple VLIW configurations and an advanced memory access unit for LTE-A modem LSIs

    NASA Astrophysics Data System (ADS)

    Tomono, Mitsuru; Ito, Makiko; Nomura, Yoshitaka; Mouri, Makoto; Hirose, Yoshio

    2015-12-01

    Energy efficiency is the most important factor in the design of wireless modem LSIs for mobile handset systems. We have developed an energy-efficient SIMD DSP for LTE-A modem LSIs. Our DSP has mainly two hardware features in order to reduce energy consumption. The first one is multiple VLIW configurations to minimize accesses to instruction memories. The second one is an advanced memory access unit to realize complex memory accesses required for wireless baseband processing. With these features, performance of our DSP is about 1.7 times faster than a base DSP on average for standard LTE-A Libraries. Our DSP achieves about 20% improvement in energy efficiency compared to a base DSP for LTE-A modem LSIs.

  9. An Account of Performance in Accessing Information Stored in Long-Term Memory. A Fixed-Links Model Approach

    ERIC Educational Resources Information Center

    Altmeyer, Michael; Schweizer, Karl; Reiss, Siegbert; Ren, Xuezhu; Schreiner, Michael

    2013-01-01

    Performance in working memory and short-term memory tasks was employed for predicting performance in a long-term memory task in order to find out about the underlying processes. The types of memory were represented by versions of the Posner Task, the Backward Counting Task and the Sternberg Task serving as measures of long-term memory, working…

  10. Access to Attitude-Relevant Information in Memory as a Determinant of Attitude-Behavior Consistency.

    ERIC Educational Resources Information Center

    Kallgren, Carl A.; Wood, Wendy

    Recent reserach has attempted to determine systematically how attitudes influence behavior. This research examined whether access to attitude-relevant beliefs and prior experiences would mediate the relation between attitudes and behavior. Subjects were 49 college students with a mean age of 27 who did not live with their parents or in…

  11. 75 FR 16507 - In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-04-01

    ..., California (``Rambus''). 73 FR 75131-2. The complaint, as amended and supplemented, alleges violations of... Commission's action. See Presidential Memorandum of July 21, 2005, 70 FR 43251 (July 26, 2005). During this... COMMISSION In the Matter of Certain Semiconductor Chips Having Synchronous Dynamic Random Access...

  12. A Symptom-Focused Hypnotic Approach to Accessing and Processing Previously Repressed/Dissociated Memories.

    ERIC Educational Resources Information Center

    Ratican, Kathleen L.

    1996-01-01

    The kinesthetic track back technique accesses the origins of current symptoms and may uncover previously repressed/dissociated material, if such material exists in the client's unconscious mind, is relevant to the symptoms, and is ready to be processed consciously. Case examples are given to illustrate proper use of this technique. (LSR)

  13. Glprof: A Gprof inspired, Callgraph-oriented Per-Object Disseminating Memory Access Multi-Cache Profiler

    SciTech Connect

    Janjusic, Tommy; Kartsaklis, Christos

    2015-01-01

    Application analysis is facilitated through a number of program profiling tools. The tools vary in their complexity, ease of deployment, design, and profiling detail. Specifically, understand- ing, analyzing, and optimizing is of particular importance for scientific applications where minor changes in code paths and data-structure layout can have profound effects. Understanding how intricate data-structures are accessed and how a given memory system responds is a complex task. In this paper we describe a trace profiling tool, Glprof, specifically aimed to lessen the burden of the programmer to pin-point heavily involved data-structures during an application's run-time, and understand data-structure run-time usage. Moreover, we showcase the tool's modularity using additional cache simulation components. We elaborate on the tool's design, and features. Finally we demonstrate the application of our tool in the context of Spec bench- marks using the Glprof profiler and two concurrently running cache simulators, PPC440 and AMD Interlagos.

  14. Improved characteristics of amorphous indium-gallium-zinc-oxide-based resistive random access memory using hydrogen post-annealing

    NASA Astrophysics Data System (ADS)

    Kang, Dae Yun; Lee, Tae-Ho; Kim, Tae Geun

    2016-08-01

    The authors report an improvement in resistive switching (RS) characteristics of amorphous indium-gallium-zinc-oxide (a-IGZO)-based resistive random access memory devices using hydrogen post-annealing. Because this a-IGZO thin film has oxygen off-stoichiometry in the form of deficient and excessive oxygen sites, the film properties can be improved by introducing hydrogen atoms through the annealing process. After hydrogen post-annealing, the device exhibited a stable bipolar RS, low-voltage set and reset operation, long retention (>105 s), good endurance (>106 cycles), and a narrow distribution in each current state. The effect of hydrogen post-annealing is also investigated by analyzing the sample surface using X-ray photon spectroscopy and atomic force microscopy.

  15. Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOEpatents

    Blocksome, Michael A.; Mamidala, Amith R.

    2015-07-14

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  16. Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer

    DOEpatents

    Blocksome, Michael A.; Mamidala, Amith R.

    2015-07-07

    Fencing direct memory access (`DMA`) data transfers in a parallel active messaging interface (`PAMI`) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.

  17. Brain potentials reflect access to visual and emotional memories for faces.

    PubMed

    Bobes, Maria A; Quiñonez, Ileana; Perez, Jhoanna; Leon, Inmaculada; Valdés-Sosa, Mitchell

    2007-05-01

    Familiar faces convey different types of information, unlocking memories related to social-emotional significance. Here, the availability over time of different types of memory was evaluated using the time-course of P3 event related potentials. Two oddball paradigms were employed, both using unfamiliar faces as standards. The infrequent targets were, respectively, artificially-learned faces (devoid of social-emotional content) and faces of acquaintances. Although in both tasks targets were detected accurately, the corresponding time-course and scalp distribution of the P3 responses differed. Artificially-learned and acquaintance faces both elicited a P3b, maximal over centro-parietal sites, and a latency of 500ms. Faces of acquaintances elicited an additional component, an early P3 maximal over frontal sites: with a latency of 350ms. This suggests that visual familiarity can only trigger the overt recognition processes leading to the slower P3b, whereas emotional-social information can also elicit fast and automatic assessments (indexed by the frontal-P3) crucial for successful social interactions. PMID:17350154

  18. Impact of adolescent sucrose access on cognitive control, recognition memory, and parvalbumin immunoreactivity

    PubMed Central

    Killcross, Simon; Hambly, Luke D.; Morris, Margaret J.; Westbrook, R. Fred

    2015-01-01

    In this study we sought to determine the effect of daily sucrose consumption in young rats on their subsequent performance in tasks that involve the prefrontal cortex and hippocampus. High levels of sugar consumption have been associated with the development of obesity, however less is known about how sugar consumption influences behavioral control and high-order cognitive processes. Of particular concern is the fact that sugar intake is greatest in adolescence, an important neurodevelopmental period. We provided sucrose to rats when they were progressing through puberty and adolescence. Cognitive performance was assessed in adulthood on a task related to executive function, a rodent analog of the Stroop task. We found that sucrose-exposed rats failed to show context-appropriate responding during incongruent stimulus compounds presented at test, indicative of impairments in prefrontal cortex function. Sucrose exposed rats also showed deficits in an on object-in-place recognition memory task, indicating that both prefrontal and hippocampal function was impaired. Analysis of brains showed a reduction in expression of parvalbumin-immunoreactive GABAergic interneurons in the hippocampus and prefrontal cortex, indicating that sucrose consumption during adolescence induced long-term pathology, potentially underpinning the cognitive deficits observed. These results suggest that consumption of high levels of sugar-sweetened beverages by adolescents may also impair neurocognitive functions affecting decision-making and memory, potentially rendering them at risk for developing mental health disorders. PMID:25776039

  19. Brain potentials reflect access to visual and emotional memories for faces.

    PubMed

    Bobes, Maria A; Quiñonez, Ileana; Perez, Jhoanna; Leon, Inmaculada; Valdés-Sosa, Mitchell

    2007-05-01

    Familiar faces convey different types of information, unlocking memories related to social-emotional significance. Here, the availability over time of different types of memory was evaluated using the time-course of P3 event related potentials. Two oddball paradigms were employed, both using unfamiliar faces as standards. The infrequent targets were, respectively, artificially-learned faces (devoid of social-emotional content) and faces of acquaintances. Although in both tasks targets were detected accurately, the corresponding time-course and scalp distribution of the P3 responses differed. Artificially-learned and acquaintance faces both elicited a P3b, maximal over centro-parietal sites, and a latency of 500ms. Faces of acquaintances elicited an additional component, an early P3 maximal over frontal sites: with a latency of 350ms. This suggests that visual familiarity can only trigger the overt recognition processes leading to the slower P3b, whereas emotional-social information can also elicit fast and automatic assessments (indexed by the frontal-P3) crucial for successful social interactions.

  20. Evolution of conductive filament and its impact on reliability issues in oxide-electrolyte based resistive random access memory

    PubMed Central

    Lv, Hangbing; Xu, Xiaoxin; Liu, Hongtao; Liu, Ruoyu; Liu, Qi; Banerjee, Writam; Sun, Haitao; Long, Shibing; Li, Ling; Liu, Ming

    2015-01-01

    The electrochemical metallization cell, also referred to as conductive bridge random access memory, is considered to be a promising candidate or complementary component to the traditional charge based memory. As such, it is receiving additional focus to accelerate the commercialization process. To create a successful mass product, reliability issues must first be rigorously solved. In-depth understanding of the failure behavior of the ECM is essential for performance optimization. Here, we reveal the degradation of high resistance state behaves as the majority cases of the endurance failure of the HfO2 electrolyte based ECM cell. High resolution transmission electron microscopy was used to characterize the change in filament nature after repetitive switching cycles. The result showed that Cu accumulation inside the filament played a dominant role in switching failure, which was further supported by measuring the retention of cycle dependent high resistance state and low resistance state. The clarified physical picture of filament evolution provides a basic understanding of the mechanisms of endurance and retention failure, and the relationship between them. Based on these results, applicable approaches for performance optimization can be implicatively developed, ranging from material tailoring to structure engineering and algorithm design. PMID:25586207

  1. Thin Co/Ni-based bottom pinned spin-transfer torque magnetic random access memory stacks with high annealing tolerance

    NASA Astrophysics Data System (ADS)

    Tomczak, Y.; Swerts, J.; Mertens, S.; Lin, T.; Couet, S.; Liu, E.; Sankaran, K.; Pourtois, G.; Kim, W.; Souriau, L.; Van Elshocht, S.; Kar, G.; Furnemont, A.

    2016-01-01

    Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as a replacement for next generation embedded and stand-alone memory applications. One of the main challenges in the STT-MRAM stack development is the compatibility of the stack with CMOS process flows in which thermal budgets up to 400 °C are applied. In this letter, we report on a perpendicularly magnetized MgO-based tunnel junction (p-MTJ) on a thin Co/Ni perpendicular synthetic antiferromagnetic layer with high annealing tolerance. Tunnel magneto resistance (TMR) loss after annealing occurs when the reference layer loses its perpendicular magnetic anisotropy due to reduction of the CoFeB/MgO interfacial anisotropy. A stable Co/Ni based p-MTJ stack with TMR values of 130% at resistance-area products of 9 Ω μm2 after 400 °C anneal is achieved via moment control of the Co/Ta/CoFeB reference layer. Thinning of the CoFeB polarizing layer down to 0.8 nm is the key enabler to achieve 400 °C compatibility with limited TMR loss. Thinning the Co below 0.6 nm leads to a loss of the antiferromagnetic interlayer exchange coupling strength through Ru. Insight into the thickness and moment engineering of the reference layer is displayed to obtain the best magnetic properties and high thermal stability for thin Co/Ni SAF-based STT-MRAM stacks.

  2. Radiation immune RAM semiconductor technology for the 80's. [Random Access Memory

    NASA Technical Reports Server (NTRS)

    Hanna, W. A.; Panagos, P.

    1983-01-01

    This paper presents current and short term future characteristics of RAM semiconductor technologies which were obtained by literature survey and discussions with cognizant Government and industry personnel. In particular, total ionizing dose tolerance and high energy particle susceptibility of the technologies are addressed. Technologies judged compatible with spacecraft applications are ranked to determine the best current and future technology for fast access (less than 60 ns), radiation tolerant RAM.

  3. Characterization of Magnetic Tunnel Junctions For Spin Transfer Torque Magnetic Random Access Memory

    NASA Astrophysics Data System (ADS)

    Dill, Joshua Luchay

    This thesis details two experimental methods for quantifying magnetic tunnel junction behavior, namely write error rates and field modulated spin-torque ferromagnetic resonance. The former examines how reliably an applied spin-transfer torque can excite magnetization dynamics that lead to a reversal of magnetization direction while the latter studies steady state dynamics provided by an oscillating spin-transfer torque. These characterization techniques reveal write error rate behavior for a particular composition magnetic tunnel junction that qualitatively deviates from theoretical predictions. Possible origins of this phenomenon are also investigated with the field modulated spin-torque ferromagnetic resonance technique. By understanding the dynamics of magnetic moments predicted by theory, one can experimentally confirm or disprove these theories in order to accurately model and predict tunnel junction behavior. By having a better model for what factors are important in magnetization dynamics, one can optimize these factors in terms of improving magnetic tunnel junctions for their use as computer memory.

  4. Access to long-term optical memories using photon echoes retrieved from semiconductor spins

    NASA Astrophysics Data System (ADS)

    Langer, L.; Poltavtsev, S. V.; Yugova, I. A.; Salewski, M.; Yakovlev, D. R.; Karczewski, G.; Wojtowicz, T.; Akimov, I. A.; Bayer, M.

    2014-11-01

    The ability to store optical information is important for both classical and quantum communication. Achieving this in a comprehensive manner (converting the optical field into material excitation, storing this excitation, and releasing it after a controllable time delay) is greatly complicated by the many, often conflicting, properties of the material. More specifically, optical resonances in semiconductor quantum structures with high oscillator strength are inevitably characterized by short excitation lifetimes (and, therefore, short optical memory). Here, we present a new experimental approach to stimulated photon echoes by transferring the information contained in the optical field into a spin system, where it is decoupled from the optical vacuum field and may persist much longer. We demonstrate this for an n-doped CdTe/(Cd,Mg)Te quantum well, the storage time of which could be increased by more than three orders of magnitude, from the picosecond range up to tens of nanoseconds.

  5. Distribution of nanoscale nuclei in the amorphous dome of a phase change random access memory

    SciTech Connect

    Lee, Bong-Sub Darmawikarta, Kristof; Abelson, John R.; Raoux, Simone; Shih, Yen-Hao; Zhu, Yu

    2014-02-17

    The nanoscale crystal nuclei in an amorphous Ge{sub 2}Sb{sub 2}Te{sub 5} bit in a phase change memory device were evaluated by fluctuation transmission electron microscopy. The quench time in the device (∼10 ns) afforded more and larger nuclei in the melt-quenched state than in the as-deposited state. However, nuclei were even more numerous and larger in a test structure with a longer quench time (∼100 ns), verifying the prediction of nucleation theory that slower cooling produces more nuclei. It also demonstrates that the thermal design of devices will strongly influence the population of nuclei, and thus the speed and data retention characteristics.

  6. Robust Three-Metallization Back End of Line Process for 0.18 μm Embedded Ferroelectric Random Access Memory

    NASA Astrophysics Data System (ADS)

    Kang, Seung-Kuk; Rhie, Hyoung-Seub; Kim, Hyun-Ho; Koo, Bon-Jae; Joo, Heung-Jin; Park, Jung-Hun; Kang, Young-Min; Choi, Do-Hyun; Lee, Sung-Young; Jeong, Hong-Sik; Kim, Kinam

    2005-04-01

    We developed ferroelectric random access memory (FRAM)-embedded smartcards in which FRAM replaces electrically erasable PROM (EEPROM) and static random access memory (SRAM) to improve the read/write cycle time and endurance of data memories during operation, in which the main time delay retardation observed in EEPROM embedded smartcards occurs because of slow data update time. EEPROM-embedded smartcards have EEPROM, ROM, and SRAM. To utilize FRAM-embedded smartcards, we should integrate submicron ferroelectric capacitors into embedded logic complementary metal oxide semiconductor (CMOS) without the degradation of the ferroelectric properties. We resolved this process issue from the viewpoint of the back end of line (BEOL) process. As a result, we realized a highly reliable sensing window for FRAM-embedded smartcards that were realized by novel integration schemes such as tungsten and barrier metal (BM) technology, multilevel encapsulating (EBL) layer scheme and optimized intermetallic dielectrics (IMD) technology.

  7. Substrate and underlayer dependence of sub-32nm e-beam HSQ pillar patterning process for RRAM application

    NASA Astrophysics Data System (ADS)

    Chen, Wei-Su; Chen, Peng-Sheng; Wei, Hung-Wen; Chen, Frederick T.; Tsai, Ming-Jinn; Ku, Tzu-Kun

    2012-03-01

    High AR bi-layer resist (BLR) pillar with organic underlayer (UL) is inevitable for etching of thick RRAM film stacking considering etch selectivity to avoid collapse. Selection of UL is a key factor to determine the AR of BLR pillar and selectivity during etching of hard mask (HM) and RRAM film stacking. In this work, e-beam patterning of HSQ pillar under various e-beam dose conditions, pattern density and HSQ thicknesses are studied on carbon highly contained UL TBLC-100PM. Hard mask layer of low temperature nitride (LTN) or oxide (LTO) above TiN/Ti/HfOx RRAM film stacking are also studied for achieving highest HSQ CD resolution by reducing e-beam proximity effect. Fogging effect is studied with various e-beam dose of the L/S=1/20 isolated pillar array which is far from the other arrays of 36 μm. Experimental results are summarized below. Etch rates (etch resistance) of TBLC-100PM UL under fluorine or chlorine-based plasmas are lower (higher) than that of AR3-600 UL with low carbon contained. Thicker LTN HM is necessary for higher HSQ pillar CD resolution. HSQ pillar CD resolution on LTO HM is higher than that on LTN HM. Smallest CD of HSQ pillar is 23.1 nm. Fogging effect is strong for TBLC-100PM where e-beam dose could affect the shape of HSQ pillar of neighboring array. This is not observed for AR3-600 UL. HSQ pillar CD resolution is highest for HSQ coated at 2000 rpm. Small change of HSQ coating speed could degrade CD resolution and imaging contrast drastically which may come from the fogging effect.

  8. Novel Field Effect Diode Type Vertical Capacitorless One Transistor Dynamic Random Access Memory Cell with Negative Hold Bit Line Bias Scheme for Improving the Hold Characteristics

    NASA Astrophysics Data System (ADS)

    Imamoto, Takuya; Endoh, Tetsuo

    2013-04-01

    In this paper, the novel field effect diode (FED) type vertical capacitorless one transistor dynamic random access memory (1T-DRAM) cell with negative hold bit line (BL) voltage (VBL) scheme is proposed. In comparison with the conventional planar type, the proposed vertical type with negative hold VBL scheme shows excellent static and disturb retention time. The proposed vertical type memory cell with negative hold VBL scheme achieves 1,000 times longer static retention time and 104 times longer BL disturb retention time at 85 °C than that of the conventional planar type. Furthermore, the proposed vertical type memory cell has a small cell size of 4F2 due to its stacked vertical structure. The proposed FED type vertical capacitorless 1T-DRAM cell with negative hold VBL scheme is shown to be an excellent candidate for stand-alone and embedded memory applications and extends scaling limitations.

  9. A new parameter to characterize the charge transport regime in Ni/HfO2/Si-n+-based RRAMs

    NASA Astrophysics Data System (ADS)

    Villena, M. A.; Roldán, J. B.; González, M. B.; González-Rodelas, P.; Jiménez-Molinos, F.; Campabadal, F.; Barrera, D.

    2016-04-01

    In this work, a new parameter is defined to describe the charge transport regime and to understand the physics behind the operation of Ni/HfO2/Si-n+-based RRAMs. An extraction process of the parameter from experimental reset I-V curves is proposed. The new parameter allows to know the relative importance of the two main transport mechanisms involved in the charge conduction in the low resistance state of the device: a tunneling current through a potential barrier and an ohmic component. A complete simulation study on this issue is provided. Furthermore, the reset voltage can be estimated using this new parameter.

  10. Impacts of Ion Irradiation on Hafnium oxide-based Resistive Random Access Memory Devices

    NASA Astrophysics Data System (ADS)

    He, Xiaoli

    The impacts of ion irradiation on so-called vacancy-change mechanism (VCM) and electrochemical-metallization mechanism (ECM) ReRAM devices based on HfO2 are investigated using various ion sources: H + (1 MeV), He+ (1 MeV), N+ (1 MeV), Ne+ (1.6 MeV) and Ar+ (2.75 MeV) over a range of total doses (105 -- 1011 rad(Si)) and fluences (1012 -- 1015 cm-2). VCM-ReRAM devices show robust resistive switching function after all irradiation experiments. VCM resistive switching parameters including set voltage (V set), reset voltage (Vreset), on-state resistance (R on) and off-state resistance (Roff) exhibited, in most cases, modest changes after irradiation. Decreases in forming voltage (Vf) and initial resistance (Rfresh) of fresh devices were observed after all irradiation experiments on VCM-ReRAM devices with the exception of Ar+ irradiation at the highest fluence (10 15 cm-2). In that case Rfresh increased by an order of magnitude. For VCM-ReRAM devices it was also observed that irradiation beyond a dose threshold of approximately 5 Grad(Si) could induce off-to-on state transition events. This behavior could lead to errors in a VCM-ReRAM memory system. ECM-ReRAM devices (based on HfO2) were also subjected to ion irradiation. Under proton irradiation ECM-ReRAM devices remained functional, but with relatively large positive variations (20-40%) in Vset, Vreset and Ron and large negative variations (˜ -60%) in Roff. In contrast to VCM HfO2-ReRAMs, ECM-based devices exhibited increased V f after irradiation, and no off-to-on transitions were observed. Interestingly, for ECM-ReRAM devices, high-fluence Ar irradiation resulted in a transition of the electrical conduction mechanism associated with the conductive filament forming process from a Poole-Frenkel conduction mechanism (pre-irradiation) to ionic conduction (post-Ar irradiation). ECM-ReRAM devices irradiated with lighter ions did not exhibit this effect. The different ion irradiation responses of the two types of HfO2-Re

  11. The rules of the resistive switching operation parameters based on Ta/Ta2O5 RRAM device

    NASA Astrophysics Data System (ADS)

    Li, Haitao; Richter, Curt; Kirillov, Oleg; Yuan, Hui; Zhu, Hao; Ioannou, Dimitris; Li, Qiliang; Dept. ECE, George Mason University Team; Semiconductor and Dimensional Metrology Division, NIST Team

    2013-03-01

    The resistive switching (RS) of the TaOx based RRAM has been widely studied due to its excellent endurance and thermal stability. The RS mechanism is generally understood as the formation and dissolution of nanometer-size conductive filament (CF) formed in set and reset process, respectively. However the exact process of dielectric break down remains unknown. In this work we studied the RS of the Ta/Ta2O5 based RRAM devices from the dependences of operation parameters Vset, ICC, Vreset, and Ireset on device resistance. From statistical analysis of variation in the threshold parameters, we found that the set process is mainly determined by the voltage stress on the device, instead of current. The first forming process is different from the following set process. The forming voltage exponentially depends on the pristine resistance. The forming process gives a smallest low resistance (RLRS) for each device. As a result change in compliance current (ICC) has no obvious effects on this low resistance state. Supported by Virginia Microelectronics Consortium Research Funding

  12. Calculation of energy-barrier lowering by incoherent switching in spin-transfer torque magnetoresistive random-access memory

    SciTech Connect

    Munira, Kamaram; Visscher, P. B.

    2015-05-07

    To make a useful spin-transfer torque magnetoresistive random-access memory (STT-MRAM) device, it is necessary to be able to calculate switching rates, which determine the error rates of the device. In a single-macrospin model, one can use a Fokker-Planck equation to obtain a low-current thermally activated rate ∝exp(−E{sub eff}/k{sub B}T). Here, the effective energy barrier E{sub eff} scales with the single-macrospin energy barrier KV, where K is the effective anisotropy energy density and V the volume. A long-standing paradox in this field is that the actual energy barrier appears to be much smaller than this. It has been suggested that incoherent motions may lower the barrier, but this has proved difficult to quantify. In the present paper, we show that the coherent precession has a magnetostatic instability, which allows quantitative estimation of the energy barrier and may resolve the paradox.

  13. Energetics of intrinsic defects in NiO and the consequences for its resistive random access memory performance

    NASA Astrophysics Data System (ADS)

    Dawson, J. A.; Guo, Y.; Robertson, J.

    2015-09-01

    Energetics for a variety of intrinsic defects in NiO are calculated using state-of-the-art ab initio hybrid density functional theory calculations. At the O-rich limit, Ni vacancies are the lowest cost defect for all Fermi energies within the gap, in agreement with the well-known p-type behaviour of NiO. However, the ability of the metal electrode in a resistive random access memory metal-oxide-metal setup to shift the oxygen chemical potential towards the O-poor limit results in unusual NiO behaviour and O vacancies dominating at lower Fermi energy levels. Calculated band diagrams show that O vacancies in NiO are positively charged at the operating Fermi energy giving it the advantage of not requiring a scavenger metal layer to maximise drift. Ni and O interstitials are generally found to be higher in energy than the respective vacancies suggesting that significant recombination of O vacancies and interstitials does not take place as proposed in some models of switching behaviour.

  14. Vividness of Visual Imagery and Incidental Recall of Verbal Cues, When Phenomenological Availability Reflects Long-Term Memory Accessibility

    PubMed Central

    D’Angiulli, Amedeo; Runge, Matthew; Faulkner, Andrew; Zakizadeh, Jila; Chan, Aldrich; Morcos, Selvana

    2013-01-01

    The relationship between vivid visual mental images and unexpected recall (incidental recall) was replicated, refined, and extended. In Experiment 1, participants were asked to generate mental images from imagery-evoking verbal cues (controlled on several verbal properties) and then, on a trial-by-trial basis, rate the vividness of their images; 30 min later, participants were surprised with a task requiring free recall of the cues. Higher vividness ratings predicted better incidental recall of the cues than individual differences (whose effect was modest). Distributional analysis of image latencies through ex-Gaussian modeling showed an inverse relation between vividness and latency. However, recall was unrelated to image latency. The follow-up Experiment 2 showed that the processes underlying trial-by-trial vividness ratings are unrelated to the Vividness of Visual Imagery Questionnaire (VVIQ), as further supported by a meta-analysis of a randomly selected sample of relevant literature. The present findings suggest that vividness may act as an index of availability of long-term sensory traces, playing a non-epiphenomenal role in facilitating the access of those memories. PMID:23382719

  15. Energetics of intrinsic defects in NiO and the consequences for its resistive random access memory performance

    SciTech Connect

    Dawson, J. A. Guo, Y.; Robertson, J.

    2015-09-21

    Energetics for a variety of intrinsic defects in NiO are calculated using state-of-the-art ab initio hybrid density functional theory calculations. At the O-rich limit, Ni vacancies are the lowest cost defect for all Fermi energies within the gap, in agreement with the well-known p-type behaviour of NiO. However, the ability of the metal electrode in a resistive random access memory metal-oxide-metal setup to shift the oxygen chemical potential towards the O-poor limit results in unusual NiO behaviour and O vacancies dominating at lower Fermi energy levels. Calculated band diagrams show that O vacancies in NiO are positively charged at the operating Fermi energy giving it the advantage of not requiring a scavenger metal layer to maximise drift. Ni and O interstitials are generally found to be higher in energy than the respective vacancies suggesting that significant recombination of O vacancies and interstitials does not take place as proposed in some models of switching behaviour.

  16. Finding Oxygen Reservoir by Using Extremely Small Test Cell Structure for Resistive Random Access Memory with Replaceable Bottom Electrode

    PubMed Central

    Kinoshita, Kentaro; Koh, Sang-Gyu; Moriyama, Takumi; Kishida, Satoru

    2015-01-01

    Although the presence of an oxygen reservoir (OR) is assumed in many models that explain resistive switching of resistive random access memory (ReRAM) with electrode/metal oxide (MO)/electrode structures, the location of OR is not clear. We have previously reported a method, which involved the use of an AFM cantilever, for preparing an extremely small ReRAM cell that has a removable bottom electrode (BE). In this study, we used this cell structure to specify the location of OR. Because an anode is often assumed to work as OR, we investigated the effect of changing anodes without changing the MO layer and the cathode on the occurrence of reset. It was found that the reset occurred independently of the catalytic ability and Gibbs free energy (ΔG) of the anode. Our proposed structure enabled to determine that the reset was caused by repairing oxygen vacancies of which a filament consists due to the migration of oxygen ions from the surrounding area when high ΔG anode metal is used, whereas by oxidizing the anode due to the migration of oxygen ions from the MO layer when low ΔG anode metal is used, suggesting the location of OR depends on ΔG of the anode. PMID:26689682

  17. Low leakage ZrO2 based capacitors for sub 20 nm dynamic random access memory technology nodes

    NASA Astrophysics Data System (ADS)

    Pešić, Milan; Knebel, Steve; Geyer, Maximilian; Schmelzer, Sebastian; Böttger, Ulrich; Kolomiiets, Nadiia; Afanas'ev, Valeri V.; Cho, Kyuho; Jung, Changhwa; Chang, Jaewan; Lim, Hanjin; Mikolajick, Thomas; Schroeder, Uwe

    2016-02-01

    During dynamic random access memory (DRAM) capacitor scaling, a lot of effort was put searching for new material stacks to overcome the scaling limitations of the current material stack, such as leakage and sufficient capacitance. In this study, very promising results for a SrTiO3 based capacitor with a record low capacitance equivalent thickness value of 0.2 nm at target leakage current are presented. Due to the material properties of SrTiO3 films (high vacancy concentration and low band gap), which are leading to an increased leakage current, a physical thickness of at least 8 nm is required at target leakage specifications. However, this physical thickness would not fit into an 18 nm DRAM structure. Therefore, two different new approaches to develop a new ZrO2 based DRAM capacitor stack by changing the inter-layer material from Al2O3 to SrO and the exchange of the top electrode material from TiN to Pt are presented. A combination of these two approaches leads to a capacitance equivalent thickness value of 0.47 nm. Most importantly, the physical thickness of <5 nm for the dielectric stack is in accordance with the target specifications. Detailed evaluation of the leakage current characteristics leads to a capacitor model which allows the prediction of the electrical behavior with thickness scaling.

  18. Switching characteristics for ferroelectric random access memory based on RC model in poly(vinylidene fluoride-trifluoroethylene) ultrathin films

    NASA Astrophysics Data System (ADS)

    Liu, ChangLi; Wang, XueJun; Zhang, XiuLi; Du, XiaoLi; Xu, HaiSheng

    2016-05-01

    The switching characteristic of the poly(vinylidene fluoride-trifluoroethlene) (P(VDF-TrFE)) films have been studied at different ranges of applied electric field. It is suggest that the increase of the switching speed upon nucleation protocol and the deceleration of switching could be related to the presence of a non-ferroelectric layer. Remarkably, a capacitor and resistor (RC) links model plays significant roles in the polarization switching dynamics of the thin films. For P(VDF-TrFE) ultrathin films with electroactive interlayer, it is found that the switching dynamic characteristics are strongly affected by the contributions of resistor and non-ferroelectric (non-FE) interface factors. A corresponding experiment is designed using poly(3,4-ethylene dioxythiophene):poly(styrene sulfonic) (PEDOT-PSSH) as interlayer with different proton concentrations, and the testing results show that the robust switching is determined by the proton concentration in interlayer and lower leakage current in circuit to reliable applications of such polymer films. These findings provide a new feasible method to enhance the polarization switching for the ferroelectric random access memory.

  19. Total ionizing dose effect of γ-ray radiation on the switching characteristics and filament stability of HfOx resistive random access memory

    SciTech Connect

    Fang, Runchen; Yu, Shimeng; Gonzalez Velo, Yago; Chen, Wenhao; Holbert, Keith E.; Kozicki, Michael N.; Barnaby, Hugh

    2014-05-05

    The total ionizing dose (TID) effect of gamma-ray (γ-ray) irradiation on HfOx based resistive random access memory was investigated by electrical and material characterizations. The memory states can sustain TID level ∼5.2 Mrad (HfO{sub 2}) without significant change in the functionality or the switching characteristics under pulse cycling. However, the stability of the filament is weakened after irradiation as memory states are more vulnerable to flipping under the electrical stress. X-ray photoelectron spectroscopy was performed to ascertain the physical mechanism of the stability degradation, which is attributed to the Hf-O bond breaking by the high-energy γ-ray exposure.

  20. Spike-timing dependent plasticity in a transistor-selected resistive switching memory.

    PubMed

    Ambrogio, S; Balatti, S; Nardi, F; Facchinetti, S; Ielmini, D

    2013-09-27

    In a neural network, neuron computation is achieved through the summation of input signals fed by synaptic connections. The synaptic activity (weight) is dictated by the synchronous firing of neurons, inducing potentiation/depression of the synaptic connection. This learning function can be supported by the resistive switching memory (RRAM), which changes its resistance depending on the amplitude, the pulse width and the bias polarity of the applied signal. This work shows a new synapse circuit comprising a MOS transistor as a selector and a RRAM as a variable resistance, displaying spike-timing dependent plasticity (STDP) similar to the one originally experienced in biological neural networks. We demonstrate long-term potentiation and long-term depression by simulations with an analytical model of resistive switching. Finally, the experimental demonstration of the new STDP scheme is presented. PMID:23999495

  1. Electrode-induced digital-to-analog resistive switching in TaO x -based RRAM devices.

    PubMed

    Li, Xinyi; Wu, Huaqiang; Bin Gao; Wu, Wei; Wu, Dong; Deng, Ning; Cai, Jian; Qian, He

    2016-07-29

    In RRAM devices, electrodes play a significant role during the switching process. In this paper, different top electrodes are used for TaO y /Ta2O5-x /AlO σ triple-oxide-layer devices. Top electrode-induced digital resistive switching to analog resistive switching was observed. For Pt top electrode (TE) devices, abrupt digital resistive switching behavior was observed, while Al TE devices showed gradual analog resistive switching behavior. Devices with various AlO σ thicknesses and sizes were fabricated and characterized to evaluate the reliability of the analog resistive switching. The physical mechanisms responsible for this electrode-induced resistive switching behavior were discussed. PMID:27302281

  2. Engineering of the chemical reactivity of the Ti/HfO₂ interface for RRAM: experiment and theory.

    PubMed

    Calka, Pauline; Sowinska, Malgorzata; Bertaud, Thomas; Walczyk, Damian; Dabrowski, Jarek; Zaumseil, Peter; Walczyk, Christian; Gloskovskii, Andrei; Cartoixà, Xavier; Suñé, Jordi; Schroeder, Thomas

    2014-04-01

    The Ti/HfO2 interface plays a major role for resistance switching performances. However, clear interface engineering strategies to achieve reliable and reproducible switching have been poorly investigated. For this purpose, we present a comprehensive study of the Ti/HfO2 interface by a combined experimental-theoretical approach. Based on the use of oxygen-isotope marked Hf*O2, the oxygen scavenging capability of the Ti layer is clearly proven. More importantly, in line with ab initio theory, the combined HAXPES-Tof-SIMS study of the thin films deposited by MBE clearly establishes a strong impact of the HfO2 thin film morphology on the Ti/HfO2 interface reactivity. Low-temperature deposition is thus seen as a RRAM processing compatible way to establish the critical amount of oxygen vacancies to achieve reproducible and reliable resistance switching performances.

  3. An in-depth study of thermal effects in reset transitions in HfO2 based RRAMs

    NASA Astrophysics Data System (ADS)

    Villena, M. A.; González, M. B.; Roldán, J. B.; Campabadal, F.; Jiménez-Molinos, F.; Gómez-Campos, F. M.; Suñé, J.

    2015-09-01

    Reset transitions in HfO2 based RRAMs operated at different temperatures have been studied. Ni/HfO2/Si-n+ devices were fabricated and measured at temperatures ranging from 233 K to 473 K to characterize their reset features. In addition, a simulator including several coupled conductive filaments, series resistance and quantum effects was employed to analyze the same devices. The experimental results were correctly reproduced. It was found that the reset voltage and current show slight temperature dependence. To explain this fact, the roles of the out-diffusion of metallic species from the conductive filament and its conductance temperature dependence have been studied by simulation. The different conductive filament resistance components are also analyzed in the temperature range employed in our study. Finally, the thermal change in the energy barrier linked to quantum effects in the transport properties in the filament is modeled.

  4. Implementation of nitrogen-doped titanium-tungsten tunable heater in phase change random access memory and its effects on device performance

    SciTech Connect

    Tan, Chun Chia; Zhao, Rong Chong, Tow Chong; Shi, Luping

    2014-10-13

    Nitrogen-doped titanium-tungsten (N-TiW) was proposed as a tunable heater in Phase Change Random Access Memory (PCRAM). By tuning N-TiW's material properties through doping, the heater can be tailored to optimize the access speed and programming current of PCRAM. Experiments reveal that N-TiW's resistivity increases and thermal conductivity decreases with increasing nitrogen-doping ratio, and N-TiW devices displayed (∼33% to ∼55%) reduced programming currents. However, there is a tradeoff between the current and speed for heater-based PCRAM. Analysis of devices with different N-TiW heaters shows that N-TiW doping levels could be optimized to enable low RESET currents and fast access speeds.

  5. Detrimental effect of interfacial Dzyaloshinskii-Moriya interaction on perpendicular spin-transfer-torque magnetic random access memory

    SciTech Connect

    Jang, Peong-Hwa; Lee, Seo-Won E-mail: kj-lee@korea.ac.kr; Song, Kyungmi; Lee, Seung-Jae; Lee, Kyung-Jin E-mail: kj-lee@korea.ac.kr

    2015-11-16

    Interfacial Dzyaloshinskii-Moriya interaction in ferromagnet/heavy metal bilayers is recently of considerable interest as it offers an efficient control of domain walls and the stabilization of magnetic skyrmions. However, its effect on the performance of perpendicular spin transfer torque memory has not been explored yet. We show based on numerical studies that the interfacial Dzyaloshinskii-Moriya interaction decreases the thermal energy barrier while increases the switching current. As high thermal energy barrier as well as low switching current is required for the commercialization of spin torque memory, our results suggest that the interfacial Dzyaloshinskii-Moriya interaction should be minimized for spin torque memory applications.

  6. Memory protection

    NASA Technical Reports Server (NTRS)

    Denning, Peter J.

    1988-01-01

    Accidental overwriting of files or of memory regions belonging to other programs, browsing of personal files by superusers, Trojan horses, and viruses are examples of breakdowns in workstations and personal computers that would be significantly reduced by memory protection. Memory protection is the capability of an operating system and supporting hardware to delimit segments of memory, to control whether segments can be read from or written into, and to confine accesses of a program to its segments alone. The absence of memory protection in many operating systems today is the result of a bias toward a narrow definition of performance as maximum instruction-execution rate. A broader definition, including the time to get the job done, makes clear that cost of recovery from memory interference errors reduces expected performance. The mechanisms of memory protection are well understood, powerful, efficient, and elegant. They add to performance in the broad sense without reducing instruction execution rate.

  7. Novel Vertical 3D Structure of TaOx-based RRAM with Self-localized Switching Region by Sidewall Electrode Oxidation

    PubMed Central

    Yu, Muxi; Cai, Yimao; Wang, Zongwei; Fang, Yichen; Liu, Yefan; Yu, Zhizhen; Pan, Yue; Zhang, Zhenxing; Tan, Jing; Yang, Xue; Li, Ming; Huang, Ru

    2016-01-01

    A novel vertical 3D RRAM structure with greatly improved reliability behavior is proposed and experimentally demonstrated through basically compatible process featuring self-localized switching region by sidewall electrode oxidation. Compared with the conventional structure, due to the effective confinement of the switching region, the newly-proposed structure shows about two orders higher endurance (>108 without verification operation) and better retention (>180h@150 °C), as well as high uniformity. Corresponding model is put forward, on the base of which thorough theoretical analysis and calculations are conducted as well, demonstrating that, resulting from the physically-isolated switching from neighboring cells, the proposed structure exhibits dramatically improved reliability due to effective suppression of thermal effects and oxygen vacancies diffusion interference, indicating that this novel structure is very promising for future high density 3D RRAM application. PMID:26884054

  8. Quantifying data retention of perpendicular spin-transfer-torque magnetic random access memory chips using an effective thermal stability factor method

    SciTech Connect

    Thomas, Luc Jan, Guenole; Le, Son; Wang, Po-Kang

    2015-04-20

    The thermal stability of perpendicular Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) devices is investigated at chip level. Experimental data are analyzed in the framework of the Néel-Brown model including distributions of the thermal stability factor Δ. We show that in the low error rate regime important for applications, the effect of distributions of Δ can be described by a single quantity, the effective thermal stability factor Δ{sub eff}, which encompasses both the median and the standard deviation of the distributions. Data retention of memory chips can be assessed accurately by measuring Δ{sub eff} as a function of device diameter and temperature. We apply this method to show that 54 nm devices based on our perpendicular STT-MRAM design meet our 10 year data retention target up to 120 °C.

  9. Investigation of thermal resistance and power consumption in Ga-doped indium oxide (In{sub 2}O{sub 3}) nanowire phase change random access memory

    SciTech Connect

    Jin, Bo; Lee, Jeong-Soo E-mail: ljs6951@postech.ac.kr; Lim, Taekyung; Ju, Sanghyun; Latypov, Marat I.; Pi, Dong-Hai; Seop Kim, Hyoung; Meyyappan, M. E-mail: ljs6951@postech.ac.kr

    2014-03-10

    The resistance stability and thermal resistance of phase change memory devices using ∼40 nm diameter Ga-doped In{sub 2}O{sub 3} nanowires (Ga:In{sub 2}O{sub 3} NW) with different Ga-doping concentrations have been investigated. The estimated resistance stability (R(t)/R{sub 0} ratio) improves with higher Ga concentration and is dependent on annealing temperature. The extracted thermal resistance (R{sub th}) increases with higher Ga-concentration and thus the power consumption can be reduced by ∼90% for the 11.5% Ga:In{sub 2}O{sub 3} NW, compared to the 2.1% Ga:In{sub 2}O{sub 3} NW. The excellent characteristics of Ga-doped In{sub 2}O{sub 3} nanowire devices offer an avenue to develop low power and reliable phase change random access memory applications.

  10. Is external memory memory? Biological memory and extended mind.

    PubMed

    Michaelian, Kourken

    2012-09-01

    Clark and Chalmers (1998) claim that an external resource satisfying the following criteria counts as a memory: (1) the agent has constant access to the resource; (2) the information in the resource is directly available; (3) retrieved information is automatically endorsed; (4) information is stored as a consequence of past endorsement. Research on forgetting and metamemory shows that most of these criteria are not satisfied by biological memory, so they are inadequate. More psychologically realistic criteria generate a similar classification of standard putative external memories, but the criteria still do not capture the function of memory. An adequate account of memory function, compatible with its evolution and its roles in prospection and imagination, suggests that external memory performs a function not performed by biological memory systems. External memory is thus not memory. This has implications for: extended mind theorizing, ecological validity of memory research, the causal theory of memory.

  11. 39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme

    NASA Astrophysics Data System (ADS)

    Yamamoto, Yasue; Moriwaki, Shinichi; Kawasumi, Atsushi; Miyano, Shinji; Shinohara, Hirofumi

    2016-04-01

    We propose novel circuit techniques for 1 clock (1CLK) 1 read/1 write (1R/1W) 2-port static random-access memories (SRAMs) to improve read access time (tAC) and write margins at low voltages. Two-stage read boost (TSR-BST) and write word line boost (WWL-BST) after the read sensing schemes have been proposed. TSR-BST reduces the worst read bit line (RBL) delay by 61% and RBL amplitude by 10% at V DD = 0.5 V, which improves tAC by 39% and reduces energy dissipation by 11% at V DD = 0.55 V. WWL-BST after read sensing scheme improves minimum operating voltage (V min) by 140 mV. A 32 kbit 1CLK 1R/1W 2-port SRAM with TSR-BST and WWL-BST has been developed using a 40 nm CMOS.

  12. Reducing operation voltages by introducing a low-k switching layer in indium–tin-oxide-based resistance random access memory

    NASA Astrophysics Data System (ADS)

    Jin, Fu-Yuan; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Pan, Chih-Hung; Lin, Chih-Yang; Chen, Po-Hsun; Chen, Min-Chen; Huang, Hui-Chun; Lo, Ikai; Zheng, Jin-Cheng; Sze, Simon M.

    2016-06-01

    In this letter, we inserted a low dielectric constant (low-k) or high dielectric constant (high-k) material as a switching layer in indium–tin-oxide-based resistive random-access memory. After measuring the two samples, we found that the low-k material device has very low operating voltages (‑80 and 110 mV for SET and RESET operations, respectively). Current fitting results were then used with the COMSOL software package to simulate electric field distribution in the layers. After combining the electrical measurement results with simulations, a conduction model was proposed to explain resistance switching behaviors in the two structures.

  13. Dependence of reactive metal layer on resistive switching in a bi-layer structure Ta/HfOx filament type resistive random access memory

    NASA Astrophysics Data System (ADS)

    Lee, Daeseok; Woo, Jiyong; Park, Sangsu; Cha, Euijun; Lee, Sangheon; Hwang, Hyunsang

    2014-02-01

    The dependence of reactive metal layer on resistive switching characteristics is investigated in a bi-layer structural Ta/HfOx filament type resistive random access memory (ReRAM). By increasing the oxygen absorption rate of the reactive metal layer, formation of an induced resistive switching region that led to significant changes in the resistive switching characteristics of the ReRAM was observed. Electrical and physical analyses showed that the induced TaOx-resistive switching region can result in self-compliance behavior, uniform resistive switching, and a gradual set process, which can be utilized for low power and analog operations.

  14. Reducing operation voltages by introducing a low-k switching layer in indium-tin-oxide-based resistance random access memory

    NASA Astrophysics Data System (ADS)

    Jin, Fu-Yuan; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Pan, Chih-Hung; Lin, Chih-Yang; Chen, Po-Hsun; Chen, Min-Chen; Huang, Hui-Chun; Lo, Ikai; Zheng, Jin-Cheng; Sze, Simon M.

    2016-06-01

    In this letter, we inserted a low dielectric constant (low-k) or high dielectric constant (high-k) material as a switching layer in indium-tin-oxide-based resistive random-access memory. After measuring the two samples, we found that the low-k material device has very low operating voltages (-80 and 110 mV for SET and RESET operations, respectively). Current fitting results were then used with the COMSOL software package to simulate electric field distribution in the layers. After combining the electrical measurement results with simulations, a conduction model was proposed to explain resistance switching behaviors in the two structures.

  15. Device and Circuit Modeling and Development of a Non-Volatile Random Access Memory Cell, Utilizing AN Amorphous Silicon Thin-Film Floating-Gate Transistor Based Technology.

    NASA Astrophysics Data System (ADS)

    Riggio, Salvatore Richard, Jr.

    1994-01-01

    High density storage mechanisms are generally created using either magnetic or optical implementation techniques. Both of these techniques require mechanical transport of the medium and, therefore, have low reliability factors. These devices also generate unwanted low level ambient noise, which is of particular concern when considering modern quiet office standards. Additionally, optical techniques tend to be read-only in nature. Both mechanisms exhibit random access times that are measured in milli-seconds, rather than in micro-seconds. Therefore, the creation of a non-volatile random access memory as a replacement for the above mentioned storage techniques would be of great advantage in terms of access time, reliability, and ambient noise level. Described within are the device and circuit modeling and fabrication techniques used to develop a non-volatile random access memory cell from an amorphous silicon thin -film transistor based technology. Amorphous silicon thin-film transistors are fabricated by depositing the metal, the insulator and the semiconductor materials with a sputtering mechanism in a vacuum at 220 degrees centigrade, rather than by diffusion at 2000 degrees centigrade, as is done with crystalline silicon. By depositing a metal in the insulator, which is located between the gate and the channel, and by using an insulator material with extremely high resistivity, one can store charge in the gate region for a long period of time without external power. For example, this period of time can be as little as one week or as long as over one year. With a periodic refresh, one can extend the memory time of this storage mechanism indefinitely. Thin-film transistors can be deposited on a variety of materials such as glass, quartz or plastic by means of a stationary or continuous motion fabrication system. This material can be either rigid or flexible, and can be comparatively large in size. This allows for much greater circuit density than a standard

  16. Excellent scalability including self-heating phenomena of vertical-channel field-effect-diode type capacitor-less one transistor dynamic random access memory cell

    NASA Astrophysics Data System (ADS)

    Imamoto, Takuya; Endoh, Tetsuo

    2014-01-01

    The scalability study and the impact of the self-heating effect (SHE) on memory operation of the bulk vertical-channel field effect diode (FED) type capacitorless one transistor (1T) dynamic random access memory (DRAM) cell are investigated via device simulator for the first time. The vertical-channel FED type 1T-DRAM cell shows the excellent hold characteristics (100 ms at 358 K of ambient temperature) with large enough read current margin (1 µA/cell) even when silicon pillar diameter (D) is scaled down from 20 to 12 nm. It is also shown that by employing the vertical-channel FED type, maximum lattice temperature in the memory cell due to SHE (T_{\\text{L}}^{\\text{Max}}) can be suppressed to a negligible small value and only reach 300.6 from 300 K ambient temperature due to the low lateral electric field, while the vertical-channel bipolar junction transistor (BJT) type 1T-DRAM shows significant SHE (T_{\\text{L}}^{\\text{Max}} = 330.6 K). Moreover, this excellent thermal characteristic can be maintained even when D is scaled down from 20 to 12 nm.

  17. CONDENSED MATTER: STRUCTURE, THERMAL AND MECHANICAL PROPERTIES: Study on the dose rate upset effect of partially depleted silicon-on-insulator static random access memory

    NASA Astrophysics Data System (ADS)

    Zhao, Fa-Zhan; Liu, Meng-Xin; Guo, Tian-Lei; Liu, Gang; Hai, Chao-He; Han, Zheng-Sheng; Yang, Shan-Chao; Li, Rui-Bin; Lin, Dong-Sheng; Chen, Wei

    2008-12-01

    This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM (Partially Depleted Silicon-On-Insulator Static Random Access Memory) with the Qiangguang-I accelerator in Northwest Institute of Nuclear Technology. The SRAM (Static Random Access Memory) chips are developed by the Institute of Microelectronics of Chinese Academy of Sciences. It uses the full address test mode to determine the upset mechanisms. A specified address test is taken in the same time. The test results indicate that the upset threshold of the PDSOI SRAM is about 1×108 Gy(Si)/s. However, there are a few bits upset when the dose rate reaches up to 1.58 × 109 Gy(Si)/s. The SRAM circuit can still work after the high level γ ray pulse. Finally, the upset mechanism is determined to be the rail span collapse by comparing the critical charge with the collected charge after γ ray pulse. The physical locations of upset cells are plotted in the layout of the SRAM to investigate the layout defect. Then, some layout optimizations are made to improve the dose rate hardened performance of the PDSOI SRAM.

  18. Materials, technologies, and circuit concepts for nanocrossbar-based bipolar RRAM

    NASA Astrophysics Data System (ADS)

    Kügeler, Carsten; Rosezin, Roland; Linn, Eike; Bruchhaus, Rainer; Waser, Rainer

    2011-03-01

    The paper reports on the characterization of bipolar resistive switching materials and their integration into nanocrossbar structures, as well as on different memory operation schemes in terms of memory density and the challenging problem of sneak paths. TiO2, WO3, GeSe, SiO2 and MSQ thin films were integrated into nanojunctions of 100×100 nm2. The variation between inert Pt and Cu or Ag top electrodes leads to valence change (VCM) switching or electrochemical metallization (ECM) switching and has significant impact on the resistive properties. All materials showed promising characteristics with switching speeds down to 10 ns, multilevel switching, good endurance and retention. Nanoimprint lithography was found to be a suitable tool for processing crossbar arrays down to a feature size of 50 nm and 3D stacking was demonstrated. The inherent occurrence of current sneak paths in passive crossbar arrays can be circumvented by the implementation of complementary resistive switching (CRS) cells. The comparison with other operation schemes shows that the CRS concept dramatically increases the addressable memory size to about 1010 bit.

  19. Ease of Access to List Items in Short-Term Memory Depends on the Order of the Recognition Probes

    ERIC Educational Resources Information Center

    Lange, Elke B.; Cerella, John; Verhaeghen, Paul

    2011-01-01

    We report data from 4 experiments using a recognition design with multiple probes to be matched to specific study positions. Items could be accessed rapidly, independent of set size, when the test order matched the study order (forward condition). When the order of testing was random, backward, or in a prelearned irregular sequence (reordered…

  20. ViSA: A Neurodynamic Model for Visuo-Spatial Working Memory, Attentional Blink, and Conscious Access

    ERIC Educational Resources Information Center

    Simione, Luca; Raffone, Antonino; Wolters, Gezinus; Salmas, Paola; Nakatani, Chie; Belardinelli, Marta Olivetti; van Leeuwen, Cees

    2012-01-01

    Two separate lines of study have clarified the role of selectivity in conscious access to visual information. Both involve presenting multiple targets and distracters: one "simultaneously" in a spatially distributed fashion, the other "sequentially" at a single location. To understand their findings in a unified framework, we propose a…

  1. Closed-form analytical model of static noise margin for ultra-low voltage eight-transistor tunnel FET static random access memory

    NASA Astrophysics Data System (ADS)

    Fuketa, Hiroshi; O'uchi, Shin-ichi; Fukuda, Koichi; Mori, Takahiro; Morita, Yukinori; Masahara, Meishoku; Matsukawa, Takashi

    2016-04-01

    Variations of eight-transistor (8T) tunnel FET (TFET) static random access memory (SRAM) cells at ultra-low supply voltage (V DD) of 0.3 V are discussed. A closed-form analytical model for the static noise margin (SNM) of the TFET SRAM cells is proposed to clarify the dependence of SNM on device parameters and is verified by simulations. The SNM variations caused by process variations are investigated using the proposed model, and we show a requirement for the threshold voltage (V TH) variation in the TFET SRAM design, which indicates that the V TH variation must be reduced as the subthreshold swing becomes steeper. In addition, a feasibility of the TFET SRAM cells operating at V DD = 0.3 V in two different process technologies is evaluated using the proposed model.

  2. Low leakage Ru-strontium titanate-Ru metal-insulator-metal capacitors for sub-20 nm technology node in dynamic random access memory

    SciTech Connect

    Popovici, M. Swerts, J.; Redolfi, A.; Kaczer, B.; Aoulaiche, M.; Radu, I.; Clima, S.; Everaert, J.-L.; Van Elshocht, S.; Jurczak, M.

    2014-02-24

    Improved metal-insulator-metal capacitor (MIMCAP) stacks with strontium titanate (STO) as dielectric sandwiched between Ru as top and bottom electrode are shown. The Ru/STO/Ru stack demonstrates clearly its potential to reach sub-20 nm technology nodes for dynamic random access memory. Downscaling of the equivalent oxide thickness, leakage current density (J{sub g}) of the MIMCAPs, and physical thickness of the STO have been realized by control of the Sr/Ti ratio and grain size using a heterogeneous TiO{sub 2}/STO based nanolaminate stack deposition and a two-step crystallization anneal. Replacement of TiN with Ru as both top and bottom electrodes reduces the amount of electrically active defects and is essential to achieve a low leakage current in the MIM capacitor.

  3. Evaluation of in-plane local stress distribution in stacked IC chip using dynamic random access memory cell array for highly reliable three-dimensional IC

    NASA Astrophysics Data System (ADS)

    Tanikawa, Seiya; Kino, Hisashi; Fukushima, Takafumi; Koyanagi, Mitsumasa; Tanaka, Tetsu

    2016-04-01

    As three-dimensional (3D) ICs have many advantages, IC performances can be enhanced without scaling down of transistor size. However, 3D IC has mechanical stresses inside Si substrates owing to its 3D stacking structure, which induces negative effects on transistor performances such as carrier mobility changes. One of the mechanical stresses is local bending stress due to organic adhesive shrinkage among stacked IC chips. In this paper, we have proposed an evaluation method for in-plane local stress distribution in the stacked IC chips using retention time modulation of a dynamic random access memory (DRAM) cell array. We fabricated a test structure composed of a DRAM chip bonded on a Si interposer with dummy Cu/Sn microbumps. As a result, we clarified that the DRAM cell array can precisely evaluate the in-plane local stress distribution in the stacked IC chips.

  4. Comparing implicit and explicit semantic access of direct and indirect word pairs in schizophrenia to evaluate models of semantic memory.

    PubMed

    Neill, Erica; Rossell, Susan Lee

    2013-02-28

    Semantic memory deficits in schizophrenia (SZ) are profound, yet there is no research comparing implicit and explicit semantic processing in the same participant sample. In the current study, both implicit and explicit priming are investigated using direct (LION-TIGER) and indirect (LION-STRIPES; where tiger is not displayed) stimuli comparing SZ to healthy controls. Based on a substantive review (Rossell and Stefanovic, 2007) and meta-analysis (Pomarol-Clotet et al., 2008), it was predicted that SZ would be associated with increased indirect priming implicitly. Further, it was predicted that SZ would be associated with abnormal indirect priming explicitly, replicating earlier work (Assaf et al., 2006). No specific hypotheses were made for implicit direct priming due to the heterogeneity of the literature. It was hypothesised that explicit direct priming would be intact based on the structured nature of this task. The pattern of results suggests (1) intact reaction time (RT) and error performance implicitly in the face of abnormal direct priming and (2) impaired RT and error performance explicitly. This pattern confirms general findings regarding implicit/explicit memory impairments in SZ whilst highlighting the unique pattern of performance specific to semantic priming. Finally, priming performance is discussed in relation to thought disorder and length of illness.

  5. Correlative transmission electron microscopy and electrical properties study of switchable phase-change random access memory line cells

    SciTech Connect

    Oosthoek, J. L. M.; Kooi, B. J.; Voogt, F. C.; Attenborough, K.; Verheijen, M. A.; Hurkx, G. A. M.; Gravesteijn, D. J.

    2015-02-14

    Phase-change memory line cells, where the active material has a thickness of 15 nm, were prepared for transmission electron microscopy (TEM) observation such that they still could be switched and characterized electrically after the preparation. The result of these observations in comparison with detailed electrical characterization showed (i) normal behavior for relatively long amorphous marks, resulting in a hyperbolic dependence between SET resistance and SET current, indicating a switching mechanism based on initially long and thin nanoscale crystalline filaments which thicken gradually, and (ii) anomalous behavior, which holds for relatively short amorphous marks, where initially directly a massive crystalline filament is formed that consumes most of the width of the amorphous mark only leaving minor residual amorphous regions at its edges. The present results demonstrate that even in (purposely) thick TEM samples, the TEM sample preparation hampers the probability to observe normal behavior and it can be debated whether it is possible to produce electrically switchable TEM specimen in which the memory cells behave the same as in their original bulk embedded state.

  6. Spatially resolved TiOx phases in switched RRAM devices using soft X-ray spectromicroscopy

    NASA Astrophysics Data System (ADS)

    Carta, D.; Hitchcock, A. P.; Guttmann, P.; Regoutz, A.; Khiat, A.; Serb, A.; Gupta, I.; Prodromakis, T.

    2016-02-01

    Reduction in metal-oxide thin films has been suggested as the key mechanism responsible for forming conductive phases within solid-state memory devices, enabling their resistive switching capacity. The quantitative spatial identification of such conductive regions is a daunting task, particularly for metal-oxides capable of exhibiting multiple phases as in the case of TiOx. Here, we spatially resolve and chemically characterize distinct TiOx phases in localized regions of a TiOx–based memristive device by combining full-field transmission X-ray microscopy with soft X-ray spectroscopic analysis that is performed on lamella samples. We particularly show that electrically pre-switched devices in low-resistive states comprise reduced disordered phases with O/Ti ratios around 1.37 that aggregate in a ~100 nm highly localized region electrically conducting the top and bottom electrodes of the devices. We have also identified crystalline rutile and orthorhombic-like TiO2 phases in the region adjacent to the main reduced area, suggesting that the temperature increases locally up to 1000 K, validating the role of Joule heating in resistive switching. Contrary to previous studies, our approach enables to simultaneously investigate morphological and chemical changes in a quantitative manner without incurring difficulties imposed by interpretation of electron diffraction patterns acquired via conventional electron microscopy techniques.

  7. Spatially resolved TiOx phases in switched RRAM devices using soft X-ray spectromicroscopy.

    PubMed

    Carta, D; Hitchcock, A P; Guttmann, P; Regoutz, A; Khiat, A; Serb, A; Gupta, I; Prodromakis, T

    2016-01-01

    Reduction in metal-oxide thin films has been suggested as the key mechanism responsible for forming conductive phases within solid-state memory devices, enabling their resistive switching capacity. The quantitative spatial identification of such conductive regions is a daunting task, particularly for metal-oxides capable of exhibiting multiple phases as in the case of TiOx. Here, we spatially resolve and chemically characterize distinct TiOx phases in localized regions of a TiOx-based memristive device by combining full-field transmission X-ray microscopy with soft X-ray spectroscopic analysis that is performed on lamella samples. We particularly show that electrically pre-switched devices in low-resistive states comprise reduced disordered phases with O/Ti ratios around 1.37 that aggregate in a ~100 nm highly localized region electrically conducting the top and bottom electrodes of the devices. We have also identified crystalline rutile and orthorhombic-like TiO2 phases in the region adjacent to the main reduced area, suggesting that the temperature increases locally up to 1000 K, validating the role of Joule heating in resistive switching. Contrary to previous studies, our approach enables to simultaneously investigate morphological and chemical changes in a quantitative manner without incurring difficulties imposed by interpretation of electron diffraction patterns acquired via conventional electron microscopy techniques. PMID:26891776

  8. Spatially resolved TiOx phases in switched RRAM devices using soft X-ray spectromicroscopy

    PubMed Central

    Carta, D.; Hitchcock, A. P.; Guttmann, P.; Regoutz, A.; Khiat, A.; Serb, A.; Gupta, I.; Prodromakis, T.

    2016-01-01

    Reduction in metal-oxide thin films has been suggested as the key mechanism responsible for forming conductive phases within solid-state memory devices, enabling their resistive switching capacity. The quantitative spatial identification of such conductive regions is a daunting task, particularly for metal-oxides capable of exhibiting multiple phases as in the case of TiOx. Here, we spatially resolve and chemically characterize distinct TiOx phases in localized regions of a TiOx–based memristive device by combining full-field transmission X-ray microscopy with soft X-ray spectroscopic analysis that is performed on lamella samples. We particularly show that electrically pre-switched devices in low-resistive states comprise reduced disordered phases with O/Ti ratios around 1.37 that aggregate in a ~100 nm highly localized region electrically conducting the top and bottom electrodes of the devices. We have also identified crystalline rutile and orthorhombic-like TiO2 phases in the region adjacent to the main reduced area, suggesting that the temperature increases locally up to 1000 K, validating the role of Joule heating in resistive switching. Contrary to previous studies, our approach enables to simultaneously investigate morphological and chemical changes in a quantitative manner without incurring difficulties imposed by interpretation of electron diffraction patterns acquired via conventional electron microscopy techniques. PMID:26891776

  9. Retracing Memories

    ERIC Educational Resources Information Center

    Harrison, David L.

    2005-01-01

    There are plenty of paths to poetry but few are as accessible as retracing ones own memories. When students are asked to write about something they remember, they are given them the gift of choosing from events that are important enough to recall. They remember because what happened was funny or scary or embarrassing or heartbreaking or silly.…

  10. Correlation of anomalous write error rates and ferromagnetic resonance spectrum in spin-transfer-torque-magnetic-random-access-memory devices containing in-plane free layers

    SciTech Connect

    Evarts, Eric R.; Rippard, William H.; Pufall, Matthew R.; Heindl, Ranko

    2014-05-26

    In a small fraction of magnetic-tunnel-junction-based magnetic random-access memory devices with in-plane free layers, the write-error rates (WERs) are higher than expected on the basis of the macrospin or quasi-uniform magnetization reversal models. In devices with increased WERs, the product of effective resistance and area, tunneling magnetoresistance, and coercivity do not deviate from typical device properties. However, the field-swept, spin-torque, ferromagnetic resonance (FS-ST-FMR) spectra with an applied DC bias current deviate significantly for such devices. With a DC bias of 300 mV (producing 9.9 × 10{sup 6} A/cm{sup 2}) or greater, these anomalous devices show an increase in the fraction of the power present in FS-ST-FMR modes corresponding to higher-order excitations of the free-layer magnetization. As much as 70% of the power is contained in higher-order modes compared to ≈20% in typical devices. Additionally, a shift in the uniform-mode resonant field that is correlated with the magnitude of the WER anomaly is detected at DC biases greater than 300 mV. These differences in the anomalous devices indicate a change in the micromagnetic resonant mode structure at high applied bias.

  11. Forming-free, bipolar resistivity switching characteristics of fully transparent resistive random access memory with IZO/α-IGZO/ITO structure

    NASA Astrophysics Data System (ADS)

    Lo, Chun-Chieh; Hsieh, Tsung-Eong

    2016-09-01

    Fully transparent resistive random access memory (TRRAM) containing amorphous indium gallium zinc oxide as the resistance switching (RS) layer and transparent conducting oxides (indium zinc oxide and indium tin oxide) as the electrodes was prepared. Optical measurement indicated the transmittance of device exceeds 80% in visible-light wavelength range. TRRAM samples exhibited the forming-free feature and the best electrical performance (V SET  =  0.61 V V RESET  =  -0.76 V R HRS/R LRS (i.e. the R-ratio)  >103) was observed in the device subject to a post-annealing at 300 °C for 1 hr in atmospheric ambient. Such a sample also exhibited satisfactory endurance and retention properties at 85 °C as revealed by the reliability tests. Electrical measurement performed in vacuum ambient indicated that the RS mechanism correlates with the charge trapping/de-trapping process associated with oxygen defects in the RS layer.

  12. Switching operation and degradation of resistive random access memory composed of tungsten oxide and copper investigated using in-situ TEM

    PubMed Central

    Arita, Masashi; Takahashi, Akihito; Ohno, Yuuki; Nakane, Akitoshi; Tsurumaki-Fukuchi, Atsushi; Takahashi, Yasuo

    2015-01-01

    In-situ transmission electron microscopy (in-situ TEM) was performed to investigate the switching operation of a resistive random access memory (ReRAM) made of copper, tungsten oxide and titanium nitride (Cu/WOx/TiN). In the first Set (Forming) operation to initialize the device, precipitation appeared inside the WOx layer. It was presumed that a Cu conducting filament was formed, lowering the resistance (on-state). The Reset operation induced a higher resistance (the off-state). No change in the microstructure was identified in the TEM images. Only when an additional Reset current was applied after switching to the off-state could erasure of the filament be seen (over-Reset). Therefore, it was concluded that structural change relating to the resistance switch was localized in a very small area around the filament. With repeated switching operations and increasing operational current, the WOx/electrode interfaces became indistinct. At the same time, the resistance of the off-state gradually decreased. This is thought to be caused by Cu condensation at the interfaces because of leakage current through the area other than through the filament. This will lead to device degradation through mechanisms such as endurance failure. This is the first accelerated aging test of ReRAM achieved using in-situ TEM. PMID:26611856

  13. Forming-free, bipolar resistivity switching characteristics of fully transparent resistive random access memory with IZO/α-IGZO/ITO structure

    NASA Astrophysics Data System (ADS)

    Lo, Chun-Chieh; Hsieh, Tsung-Eong

    2016-09-01

    Fully transparent resistive random access memory (TRRAM) containing amorphous indium gallium zinc oxide as the resistance switching (RS) layer and transparent conducting oxides (indium zinc oxide and indium tin oxide) as the electrodes was prepared. Optical measurement indicated the transmittance of device exceeds 80% in visible-light wavelength range. TRRAM samples exhibited the forming-free feature and the best electrical performance (V SET  =  0.61 V V RESET  =  ‑0.76 V R HRS/R LRS (i.e. the R-ratio)  >103) was observed in the device subject to a post-annealing at 300 °C for 1 hr in atmospheric ambient. Such a sample also exhibited satisfactory endurance and retention properties at 85 °C as revealed by the reliability tests. Electrical measurement performed in vacuum ambient indicated that the RS mechanism correlates with the charge trapping/de-trapping process associated with oxygen defects in the RS layer.

  14. Sustained Resistive Switching in a Single Cu:7,7,8,8-tetracyanoquinodimethane Nanowire: A Promising Material for Resistive Random Access Memory

    NASA Astrophysics Data System (ADS)

    Basori, Rabaya; Kumar, Manoranjan; Raychaudhuri, Arup K.

    2016-06-01

    We report a new type of sustained and reversible unipolar resistive switching in a nanowire device made from a single strand of Cu:7,7,8,8-tetracyanoquinodimethane (Cu:TCNQ) nanowire (diameter <100 nm) that shows high ON/OFF ratio (~103), low threshold voltage of switching (~3.5 V) and large cycling endurance (>103). This indicates a promising material for high density resistive random access memory (ReRAM) device integration. Switching is observed in Cu:TCNQ single nanowire devices with two different electrode configuration: symmetric (C-Pt/Cu:TCNQ/C-Pt) and asymmetric (Cu/Cu:TCNQ/C-Pt), where contacts connecting the nanowire play an important role. This report also developed a method of separating out the electrode and material contributions in switching using metal-semiconductor-metal (MSM) device model along with a direct 4-probe resistivity measurement of the nanowire in the OFF as well as ON state. The device model was followed by a phenomenological model of current transport through the nanowire device which shows that lowering of potential barrier at the contacts likely occur due to formation of Cu filaments in the interface between nanowire and contact electrodes. We obtain quantitative agreement of numerically analyzed results with the experimental switching data.

  15. Sustained Resistive Switching in a Single Cu:7,7,8,8-tetracyanoquinodimethane Nanowire: A Promising Material for Resistive Random Access Memory.

    PubMed

    Basori, Rabaya; Kumar, Manoranjan; Raychaudhuri, Arup K

    2016-01-01

    We report a new type of sustained and reversible unipolar resistive switching in a nanowire device made from a single strand of Cu:7,7,8,8-tetracyanoquinodimethane (Cu:TCNQ) nanowire (diameter <100 nm) that shows high ON/OFF ratio (~10(3)), low threshold voltage of switching (~3.5 V) and large cycling endurance (>10(3)). This indicates a promising material for high density resistive random access memory (ReRAM) device integration. Switching is observed in Cu:TCNQ single nanowire devices with two different electrode configuration: symmetric (C-Pt/Cu:TCNQ/C-Pt) and asymmetric (Cu/Cu:TCNQ/C-Pt), where contacts connecting the nanowire play an important role. This report also developed a method of separating out the electrode and material contributions in switching using metal-semiconductor-metal (MSM) device model along with a direct 4-probe resistivity measurement of the nanowire in the OFF as well as ON state. The device model was followed by a phenomenological model of current transport through the nanowire device which shows that lowering of potential barrier at the contacts likely occur due to formation of Cu filaments in the interface between nanowire and contact electrodes. We obtain quantitative agreement of numerically analyzed results with the experimental switching data. PMID:27245099

  16. Investigation of Cr0.06(Sb4Te)0.94 alloy for high-speed and high-data-retention phase change random access memory applications

    NASA Astrophysics Data System (ADS)

    Li, Le; Song, Sannian; Zhang, Zhonghua; Song, Zhitang; Cheng, Yan; Lv, Shilong; Wu, Liangcai; Liu, Bo; Feng, Songlin

    2015-08-01

    The effects of Cr doping on the structural and electrical properties of Cr x (Sb4Te)1- x materials have been investigated in order to solve the contradiction between thermal stability and fast crystallization speed of Sb4Te alloys. Cr0.06(Sb4Te)0.94 alloy is considered to be a potential candidate for phase change random access memory (PCM), as evidenced by a higher crystallization temperature (204 °C), a better data retention ability (137.6 °C for 10 years), a lower melting point (558 °C), a lower energy consumption, and a faster switching speed in comparison with those of Ge2Sb2Te5. A reversible switching between set and reset states can be realized by an electric pulse as short as 5 ns for Cr0.06(Sb4Te)0.94-based PCM cell. In addition, Cr0.06(Sb4Te)0.94 shows good endurance up to 1.1 × 104 cycles with a resistance ratio of about two orders of magnitude.

  17. Interfacial Electrode-Driven Enhancement of the Switching Parameters of a Copper Oxide-Based Resistive Random-Access Memory Device

    NASA Astrophysics Data System (ADS)

    Sangani, L. D. Varma; Kumar, Ch. Ravi; Krishna, M. Ghanashyam

    2016-01-01

    The characteristics of an Au/Cu x O/Au bipolar resistive random-access memory device are reported. It is demonstrated that switching parameters of this device structure can be enhanced by introducing an interfacial Al layer between the Au top electrode and the Cu x O-based dielectric layer. The set and reset voltages are, respectively, between -2.5 V to -6.0 V and +1.2 V to +3.0 V for the Al-based device. In contrast, the range of values are -0.5 V to -2.5 V and +0.5 V to +1.5 V for the set and reset voltages in the absence of Al. The Al-based device has a higher low resistance state value of 5-6 KΩ as compared to the 0.3-0.5 KΩ for the Au-based device, which leads to a 12 times lower power dissipation factor and lower reset current of 370 μA. Endurance studies carried out over 50 switching cycles show less than 2% variation in both the low resistance and high resistance values. The conduction is ohmic at low values of bias and non-ohmic at higher bias voltage which shows that the enhanced behaviour is a result of the formation of an insulating aluminum oxide layer at the Al-Cu x O interface.

  18. Sustained Resistive Switching in a Single Cu:7,7,8,8-tetracyanoquinodimethane Nanowire: A Promising Material for Resistive Random Access Memory

    PubMed Central

    Basori, Rabaya; Kumar, Manoranjan; Raychaudhuri, Arup K.

    2016-01-01

    We report a new type of sustained and reversible unipolar resistive switching in a nanowire device made from a single strand of Cu:7,7,8,8-tetracyanoquinodimethane (Cu:TCNQ) nanowire (diameter <100 nm) that shows high ON/OFF ratio (~103), low threshold voltage of switching (~3.5 V) and large cycling endurance (>103). This indicates a promising material for high density resistive random access memory (ReRAM) device integration. Switching is observed in Cu:TCNQ single nanowire devices with two different electrode configuration: symmetric (C-Pt/Cu:TCNQ/C-Pt) and asymmetric (Cu/Cu:TCNQ/C-Pt), where contacts connecting the nanowire play an important role. This report also developed a method of separating out the electrode and material contributions in switching using metal-semiconductor-metal (MSM) device model along with a direct 4-probe resistivity measurement of the nanowire in the OFF as well as ON state. The device model was followed by a phenomenological model of current transport through the nanowire device which shows that lowering of potential barrier at the contacts likely occur due to formation of Cu filaments in the interface between nanowire and contact electrodes. We obtain quantitative agreement of numerically analyzed results with the experimental switching data. PMID:27245099

  19. Distributed multiport memory architecture

    NASA Technical Reports Server (NTRS)

    Kohl, W. H. (Inventor)

    1983-01-01

    A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

  20. Influence of cooling rate in planar thermally assisted magnetic random access memory: Improved writeability due to spin-transfer-torque influence

    SciTech Connect

    Chavent, A.; Ducruet, C.; Portemont, C.; Creuzet, C.; Alvarez-Hérault, J.; Vila, L.; Sousa, R. C.; Prejbeanu, I. L.; Dieny, B.

    2015-09-14

    This paper investigates the effect of a controlled cooling rate on magnetic field reversal assisted by spin transfer torque (STT) in thermally assisted magnetic random access memory. By using a gradual linear decrease of the voltage at the end of the write pulse, the STT decays more slowly or at least at the same rate as the temperature. This condition is necessary to make sure that the storage layer magnetization remains in the desired written direction during cooling of the cell. The influence of the write current pulse decay rate was investigated on two exchange biased synthetic ferrimagnet (SyF) electrodes. For a NiFe based electrode, a significant improvement in writing reproducibility was observed using a gradual linear voltage transition. The write error rate decreases by a factor of 10 when increasing the write pulse fall-time from ∼3 ns to 70 ns. For comparison, a second CoFe/NiFe based electrode was also reversed by magnetic field assisted by STT. In this case, no difference between sharp and linear write pulse fall shape was observed. We attribute this observation to the higher thermal stability of the CoFe/NiFe electrode during cooling. In real-time measurements of the magnetization reversal, it was found that Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling in the SyF electrode vanishes for the highest pulse voltages that were used due to the high temperature reached during write. As a result, during the cooling phase, the final state is reached through a spin-flop transition of the SyF storage layer.

  1. Influence of cooling rate in planar thermally assisted magnetic random access memory: Improved writeability due to spin-transfer-torque influence

    NASA Astrophysics Data System (ADS)

    Chavent, A.; Ducruet, C.; Portemont, C.; Creuzet, C.; Vila, L.; Alvarez-Hérault, J.; Sousa, R. C.; Prejbeanu, I. L.; Dieny, B.

    2015-09-01

    This paper investigates the effect of a controlled cooling rate on magnetic field reversal assisted by spin transfer torque (STT) in thermally assisted magnetic random access memory. By using a gradual linear decrease of the voltage at the end of the write pulse, the STT decays more slowly or at least at the same rate as the temperature. This condition is necessary to make sure that the storage layer magnetization remains in the desired written direction during cooling of the cell. The influence of the write current pulse decay rate was investigated on two exchange biased synthetic ferrimagnet (SyF) electrodes. For a NiFe based electrode, a significant improvement in writing reproducibility was observed using a gradual linear voltage transition. The write error rate decreases by a factor of 10 when increasing the write pulse fall-time from ˜3 ns to 70 ns. For comparison, a second CoFe/NiFe based electrode was also reversed by magnetic field assisted by STT. In this case, no difference between sharp and linear write pulse fall shape was observed. We attribute this observation to the higher thermal stability of the CoFe/NiFe electrode during cooling. In real-time measurements of the magnetization reversal, it was found that Ruderman-Kittel-Kasuya-Yosida (RKKY) coupling in the SyF electrode vanishes for the highest pulse voltages that were used due to the high temperature reached during write. As a result, during the cooling phase, the final state is reached through a spin-flop transition of the SyF storage layer.

  2. Improved Writing-Conductor Designs For Magnetic Memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1994-01-01

    Writing currents reduced to practical levels. Improved conceptual designs for writing conductors in micromagnet/Hall-effect random-access integrated-circuit memory reduces electrical current needed to magnetize micromagnet in each memory cell. Basic concept of micromagnet/Hall-effect random-access memory presented in "Magnetic Analog Random-Access Memory" (NPO-17999).

  3. Memory beyond expression.

    PubMed

    Delorenzi, A; Maza, F J; Suárez, L D; Barreiro, K; Molina, V A; Stehberg, J

    2014-01-01

    The idea that memories are not invariable after the consolidation process has led to new perspectives about several mnemonic processes. In this framework, we review our studies on the modulation of memory expression during reconsolidation. We propose that during both memory consolidation and reconsolidation, neuromodulators can determine the probability of the memory trace to guide behavior, i.e. they can either increase or decrease its behavioral expressibility without affecting the potential of persistent memories to be activated and become labile. Our hypothesis is based on the findings that positive modulation of memory expression during reconsolidation occurs even if memories are behaviorally unexpressed. This review discusses the original approach taken in the studies of the crab Neohelice (Chasmagnathus) granulata, which was then successfully applied to test the hypothesis in rodent fear memory. Data presented offers a new way of thinking about both weak trainings and experimental amnesia: memory retrieval can be dissociated from memory expression. Furthermore, the strategy presented here allowed us to show in human declarative memory that the periods in which long-term memory can be activated and become labile during reconsolidation exceeds the periods in which that memory is expressed, providing direct evidence that conscious access to memory is not needed for reconsolidation. Specific controls based on the constraints of reminders to trigger reconsolidation allow us to distinguish between obliterated and unexpressed but activated long-term memories after amnesic treatments, weak trainings and forgetting. In the hypothesis discussed, memory expressibility--the outcome of experience-dependent changes in the potential to behave--is considered as a flexible and modulable attribute of long-term memories. Expression seems to be just one of the possible fates of re-activated memories.

  4. Quantum memory Quantum memory

    NASA Astrophysics Data System (ADS)

    Le Gouët, Jean-Louis; Moiseev, Sergey

    2012-06-01

    Interaction of quantum radiation with multi-particle ensembles has sparked off intense research efforts during the past decade. Emblematic of this field is the quantum memory scheme, where a quantum state of light is mapped onto an ensemble of atoms and then recovered in its original shape. While opening new access to the basics of light-atom interaction, quantum memory also appears as a key element for information processing applications, such as linear optics quantum computation and long-distance quantum communication via quantum repeaters. Not surprisingly, it is far from trivial to practically recover a stored quantum state of light and, although impressive progress has already been accomplished, researchers are still struggling to reach this ambitious objective. This special issue provides an account of the state-of-the-art in a fast-moving research area that makes physicists, engineers and chemists work together at the forefront of their discipline, involving quantum fields and atoms in different media, magnetic resonance techniques and material science. Various strategies have been considered to store and retrieve quantum light. The explored designs belong to three main—while still overlapping—classes. In architectures derived from photon echo, information is mapped over the spectral components of inhomogeneously broadened absorption bands, such as those encountered in rare earth ion doped crystals and atomic gases in external gradient magnetic field. Protocols based on electromagnetic induced transparency also rely on resonant excitation and are ideally suited to the homogeneous absorption lines offered by laser cooled atomic clouds or ion Coulomb crystals. Finally off-resonance approaches are illustrated by Faraday and Raman processes. Coupling with an optical cavity may enhance the storage process, even for negligibly small atom number. Multiple scattering is also proposed as a way to enlarge the quantum interaction distance of light with matter. The

  5. Working memory capacity and controlled serial memory search.

    PubMed

    Mızrak, Eda; Öztekin, Ilke

    2016-08-01

    The speed-accuracy trade-off (SAT) procedure was used to investigate the relationship between working memory capacity (WMC) and the dynamics of temporal order memory retrieval. High- and low-span participants (HSs, LSs) studied sequentially presented five-item lists, followed by two probes from the study list. Participants indicated the more recent probe. Overall, accuracy was higher for HSs compared to LSs. Crucially, in contrast to previous investigations that observed no impact of WMC on speed of access to item information in memory (e.g., Öztekin & McElree, 2010), recovery of temporal order memory was slower for LSs. While accessing an item's representation in memory can be direct, recovery of relational information such as temporal order information requires a more controlled serial memory search. Collectively, these data indicate that WMC effects are particularly prominent during high demands of cognitive control, such as serial search operations necessary to access temporal order information from memory. PMID:27135712

  6. Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Sims, W. Herb; Varnavas, Kosta A.; Ho, Fat D.

    2011-01-01

    NASA is planning on going beyond Low Earth orbit with manned exploration missions. The radiation environment for most Low Earth orbit missions is harsher than at the Earth's surface but much less harsh than deep space. Development of new electronics is needed to meet the requirements of high performance, radiation tolerance, and reliability. The need for both Volatile and Non-volatile memory has been identified. Emerging Non-volatile memory technologies (FRAM, C-RAM,M-RAM, R-RAM, Radiation Tolerant FLASH, SONOS, etc.) need to be investigated for use in Space missions. An opportunity arose to fly a small memory experiment on a high inclination satellite (FASTSAT). An off-the-shelf 512K Ramtron FRAM was chosen to be tested in the experiment.

  7. Memory for Traumatic Experiences in Early Childhood

    ERIC Educational Resources Information Center

    Cordon, Ingrid M.; Pipe, Margaret-Ellen; Sayfan, Liat; Melinder, Annika; Goodman, Gail S.

    2004-01-01

    Traumatic experiences in early childhood raise important questions about memory development in general and about the durability and accessibility of memories for traumatic events in particular. We discuss memory for early childhood traumatic events, from a developmental perspective, focusing on those factors that may equally influence memories for…

  8. Autosuggestibility in memory development.

    PubMed

    Brainerd, C J; Reyna, V F

    1995-02-01

    Autosuggestibility is a potentially common source of false memories in children. We studied a form of autosuggestibility in which children's answers to memory tests were shifted in the direction of their illogical solutions to reasoning problems. In Experiments 1 and 2, illogic-consistent shifts were identified in children's memories of the numerical inputs on class-inclusion problems. The magnitudes of the shifts declined with age, and they appeared to be due to the intrusion of inappropriate gist on memory probes rather than retroactive interference from illogical reasoning. A model of how gist intrusion causes autosuggestibility was investigated in Experiments 3-5. The model assumes that children retrieve and process inappropriate gist when memory tests supply cues that are inadequate to permit access to verbatim memories.

  9. Mechanical memory

    DOEpatents

    Gilkey, Jeffrey C.; Duesterhaus, Michelle A.; Peter, Frank J.; Renn, Rosemarie A.; Baker, Michael S.

    2006-08-15

    A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.

  10. Mechanical memory

    DOEpatents

    Gilkey, Jeffrey C.; Duesterhaus, Michelle A.; Peter, Frank J.; Renn, Rosemarie A.; Baker, Michael S.

    2006-05-16

    A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.

  11. Confirmation of filament dissolution behavior by analyzing electrical field effect during reset process in oxide-based RRAM

    NASA Astrophysics Data System (ADS)

    Pan, Chih-Hung; Chang, Ting-Chang; Tsai, Tsung-Ming; Chang, Kuan-Chang; Chu, Tian-Jian; Lin, Wen-Yan; Chen, Min-Chen; Sze, Simon M.

    2016-09-01

    In this letter, we demonstrate completely different characteristics with different operating modes and analyze the electrical field effect to confirm the filament dissolution behavior. The device exhibited a larger memory window when using a single voltage sweep method during reset process rather than the traditional double sweep method. The phenomenon was verified by using fast I-V measurement to simulate the two operating methods. A better high resistance state (HRS) will be obtained with a very short rising time pulse, but quite notably, lower power consumption was needed. We proposed the electrical field effect to explain the phenomenon and demonstrate distribution by COMSOL simulation.

  12. Bipartite memory network architectures for parallel processing

    SciTech Connect

    Smith, W.; Kale, L.V. . Dept. of Computer Science)

    1990-01-01

    Parallel architectures are boradly classified as either shared memory or distributed memory architectures. In this paper, the authors propose a third family of architectures, called bipartite memory network architectures. In this architecture, processors and memory modules constitute a bipartite graph, where each processor is allowed to access a small subset of the memory modules, and each memory module allows access from a small set of processors. The architecture is particularly suitable for computations requiring dynamic load balancing. The authors explore the properties of this architecture by examining the Perfect Difference set based topology for the graph. Extensions of this topology are also suggested.

  13. Challenges toward gigabit-scale spin-transfer torque random access memory and beyond for normally off, green information technology infrastructure (Invited)

    NASA Astrophysics Data System (ADS)

    Kawahara, Takayuki

    2011-04-01

    If spin-transfer torque RAM (SPRAM) technology is used as a true nonvolatile RAM, it will be able to provide normally "off" and instant "on" functions. This would drastically reduce the power consumption of information technology (IT) equipment and its infrastructure while preserving high performance, thus leading to a green IT infrastructure. This paper describes the design issues and solutions for creating a Gb-scale SPRAM; scaling in memory cell current (∝F, F: feature size) and the tunneling magnetoresistive (TMR) device's write current (∝F2), the maximum voltage applicable to a TMR device (TMR ratio and resistance area product are considered); and the thermal stability of the TMR device (depending on the operation mode and density). Moreover, the cell and array configurations and an indispensable disruptive reading operation are shown for 4F2DDRx compatible operations. SPRAM can cover a system composed of a DRAM region. Finally, the potential of a multibit memory structure that covers the area of a not-and flash memory is discussed.

  14. Plated wire memory subsystem

    NASA Technical Reports Server (NTRS)

    Reynolds, L.; Tweed, H.

    1972-01-01

    The work performed entailed the design, development, construction and testing of a 4000 word by 18 bit random access, NDRO plated wire memory for use in conjunction with a spacecraft imput/output unit and central processing unit. The primary design parameters, in order of importance, were high reliability, low power, volume and weight. A single memory unit, referred to as a qualification model, was delivered.

  15. Plated wire memory subsystem

    NASA Technical Reports Server (NTRS)

    Carpenter, K. H.

    1974-01-01

    The design, construction, and test history of a 4096 word by 18 bit random access NDRO Plated Wire Memory for use in conjunction with a spacecraft input/output and central processing unit is reported. A technical and functional description is given along with diagrams illustrating layout and systems operation. Test data is shown on the procedures and results of system level and memory stack testing, and hybrid circuit screening. A comparison of the most significant physical and performance characteristics of the memory unit versus the specified requirements is also included.

  16. CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Simulation of SET Operation in Phase-Change Random Access Memories with Heater Addition and Ring-Type Contactor for Low-Power Consumption by Finite Element Modeling

    NASA Astrophysics Data System (ADS)

    Gong, Yue-Feng; Song, Zhi-Tang; Ling, Yun; Liu, Yan; Feng, Song-Lin

    2009-11-01

    A three-dimensional finite element model for phase change random access memory (PCRAM) is established for comprehensive electrical and thermal analysis during SET operation. The SET behaviours of the heater addition structure (HS) and the ring-type contact in bottom electrode (RIB) structure are compared with each other. There are two ways to reduce the RESET current, applying a high resistivity interfacial layer and building a new device structure. The simulation results indicate that the variation of SET current with different power reduction ways is little. This study takes the RESET and SET operation current into consideration, showing that the RIB structure PCRAM cell is suitable for future devices with high heat efficiency and high-density, due to its high heat efficiency in RESET operation.

  17. Influence of carbon content on the copper-telluride phase formation and on the resistive switching behavior of carbon alloyed Cu-Te conductive bridge random access memory cells

    SciTech Connect

    Devulder, Wouter De Schutter, Bob; Detavernier, Christophe; Opsomer, Karl; Franquet, Alexis; Meersschaut, Johan; Muller, Robert; Van Elshocht, Sven; Jurczak, Malgorzata; Goux, Ludovic; Belmonte, Attilio

    2014-02-07

    In this paper, we investigate the influence of the carbon content on the Cu-Te phase formation and on the resistive switching behavior in carbon alloyed Cu{sub 0.6}Te{sub 0.4} based conductive bridge random access memory (CBRAM) cells. Carbon alloying of copper-tellurium inhibits the crystallization, while attractive switching behavior is preserved when using the material as Cu-supply layer in CBRAM cells. The phase formation is first investigated in a combinatorial way. With increasing carbon content, an enlargement of the temperature window in which the material stays amorphous was observed. Moreover, if crystalline phases are formed, subsequent phase transformations are inhibited. The electrical switching behavior of memory cells with different carbon contents is then investigated by implementing them in 580 μm diameter dot TiN/Cu{sub 0.6}Te{sub 0.4}-C/Al{sub 2}O{sub 3}/Si memory cells. Reliable switching behavior is observed for carbon contents up to 40 at. %, with a resistive window of more than 2 orders of magnitude, whereas for 50 at. % carbon, a higher current in the off state and only a small resistive window are present after repeated cycling. This degradation can be ascribed to the higher thermal and lower drift contribution to the reset operation due to a lower Cu affinity towards the supply layer, leading cycle-after-cycle to an increasing amount of Cu in the switching layer, which contributes to the current. The thermal diffusion of Cu into Al{sub 2}O{sub 3} under annealing also gives an indication of the Cu affinity of the source layer. Time of flight secondary ion mass spectroscopy was used to investigate this migration depth in Al{sub 2}O{sub 3} before and after annealing, showing a higher Cu, Te, and C migration for high carbon contents.

  18. Memory hierarchy using row-based compression

    DOEpatents

    Loh, Gabriel H.; O'Connor, James M.

    2016-10-25

    A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.

  19. Effect of annealing treatment on the electrical characteristics of Pt/Cr-embedded ZnO/Pt resistance random access memory devices

    SciTech Connect

    Chang, Li-Chun; Kao, Hsuan-Ling; Liu, Keng-Hao

    2014-03-15

    ZnO/Cr/ZnO trilayer films sandwiched with Pt electrodes were prepared for nonvolatile resistive memory applications. The threshold voltage of a ZnO device embedded with a 3-nm Cr interlayer was approximately 50% lower than that of a ZnO monolayer device. This study investigated threshold voltage as a function of Cr thickness. Both the ZnO monolayer device and the Cr-embedded ZnO device structures exhibited resistance switching under electrical bias both before and after rapid thermal annealing (RTA) treatment, but resistive switching effects in the two cases exhibited distinct characteristics. Compared with the as-fabricated device, the memory cell after RTA demonstrated remarkable device parameter improvements, including a lower threshold voltage, a lower write current, and a higher R{sub off}/R{sub on} ratio. Both transmission electron microscope observations and Auger electron spectroscopy revealed that the Cr charge trapping layer in Cr-embedded ZnO dispersed uniformly into the storage medium after RTA, and x-ray diffraction and x-ray photoelectron spectroscopy analyses demonstrated that the Cr atoms lost electrons to become Cr{sup 3+} ions after dispersion. These results indicated that the altered status of Cr in ZnO/Cr/ZnO trilayer films during RTA treatment was responsible for the switching mechanism transition.

  20. O-doped Si2Sb2Te5 nano-composite phase change material for application of chalcogenide random access memory.

    PubMed

    Zhang, Ting; Song, Zhitang; Liu, Bo; Wang, Feng; Feng, Songlin

    2009-02-01

    A method to prepare nano-composite phase change material was proposed and demonstrated by oxygen doping into Si2Sb2Te5 material. According to transmission electron microscope images, Si-Sb-Te-rich domains are separated from each other by SiOx-rich domains within the material. A proper dose of O-doping into Si2Sb2Te5 significantly reduces the grain size of the phase change material. Average size of Si-Sb-Te-rich domains is about 10 nm. Such separation will limit the phase-change to a relatively small volume. The reduction of grain size further results in the promotion of data retention and thermal stability of the material. Memory device based on O-doped Si2Sb2Te5 nano-composite phase change material, with a bottom electrode contact of 260 nm in diameter, was fabricated and characterized. The memory cell shows a better electrical performance compared with the Ge2Sb2Te5 based one.

  1. Memory Matters

    MedlinePlus

    ... different parts. Some of them are important for memory. The hippocampus (say: hih-puh-KAM-pus) is one of the more important parts of the brain that processes memories. Old information and new information, or memories, are ...

  2. Demystifying the Beginnings of Memory

    ERIC Educational Resources Information Center

    Howe, Mark L.; Courage, Mary L.

    2004-01-01

    A longstanding issue in psychology has been, When does human memory begin? More particularly, when do we begin to remember personal experiences in a way that makes them accessible to recollection later in life? Current popular and scientific thinking would have us believe that memories are possible not only at the time of our birth, but also in…

  3. When Forgetting Preserves Memory

    PubMed Central

    Hupbach, Almut

    2013-01-01

    There has been a resurgence of interest in defining the circumstances leading to memory modifications. Studies have shown that reactivating a supposedly stable memory re-introduces a time-limited window of plasticity during which presentation of interfering material can cause long-term memory changes. The present study asks whether such memory changes can be prevented if people are instructed to forget the memory before the new material is encoded. Participants learned a set of objects. After 48 h, they were reminded of this learning episode, and learned another set of objects. Again 48 h later, they recalled the first (Exp. 1) or second set (Exp. 3). As shown previously, a reminder caused intrusions from the second set into recall of the first set. Here I show that the instruction to forget the first set significantly diminished intrusions from the second set, especially when the instruction was given before the new set was encoded in the second session. Experiment 2 suggests that the reduced intrusions were due to list segregation/isolation, rather than temporarily inhibited access to Set 1. Taken together, the study shows that the attempt to forget a memory can immunize it such that the presentation of interfering material has limited effects, and the memory can be recalled unchanged in the future. This is important when veridical memory is essential, such as in eyewitness testimonies. PMID:23382724

  4. Low-power and controllable memory window in Pt/Pr0.7Ca0.3MnO3/yttria-stabilized zirconia/W resistive random-access memory devices.

    PubMed

    Liu, Xinjun; Biju, Kuyyadi P; Park, Jubong; Park, Sangsu; Shin, Jungho; Kim, Insung; Md Sadaf, Sharif; Hwang, Hyunsang

    2012-04-01

    Yttria-stabilized zirconia (YSZ) layers of various thicknesses were designed and introduced before Pr0.7Ca0.3MnO3 (PCMO) film was deposited on W bottom electrodes with a submicron via-hole structure. By changing the thickness of the YSZ barrier layer (3, 5, 9, and 13 nm), a tunable memory window can be realized while low power consumption (P(max) < 4 microW) is maintained. Resistive switching (RS) in a Pt/PCMO/YSZ/W stack with a thin YSZ layer can be ascribed to an oxidation/reduction reaction caused by a ring-type PCMO/W contact, while RS with a thick YSZ layer may be related to oxygen migration across the YSZ layer between the PCMO film and the W bottom electrode and the increase (decrease) of the effective tunnel barrier height of the YSZ layer. Excellent RS behavior characteristics, such as a large R(HRS)/R(LRS) ratio (> 10(3)), die-to-die uniformity, sweeping endurance, and a retention time of more than 10(3) s, can be obtained by optimizing the thickness of YSZ layer.

  5. Memory Loss and Retrieval

    ERIC Educational Resources Information Center

    Reid, Ian

    2016-01-01

    Underlying the generally oblivious attitude of teachers and learners towards the past is insufficient respect for the role of memory in giving meaning to experience and access to knowledge. We shape our identity by making sense of our past and its relationship to present and future selves, a process that should be intensively cultivated when we…

  6. Memory Palaces

    ERIC Educational Resources Information Center

    Wood, Marianne

    2007-01-01

    This article presents a lesson called Memory Palaces. A memory palace is a memory tool used to remember information, usually as visual images, in a sequence that is logical to the person remembering it. In his book, "In the Palaces of Memory", George Johnson calls them "...structure(s) for arranging knowledge. Lots of connections to language arts,…

  7. Blanket Gate Would Address Blocks Of Memory

    NASA Technical Reports Server (NTRS)

    Lambe, John; Moopenn, Alexander; Thakoor, Anilkumar P.

    1988-01-01

    Circuit-chip area used more efficiently. Proposed gate structure selectively allows and restricts access to blocks of memory in electronic neural-type network. By breaking memory into independent blocks, gate greatly simplifies problem of reading from and writing to memory. Since blocks not used simultaneously, share operational amplifiers that prompt and read information stored in memory cells. Fewer operational amplifiers needed, and chip area occupied reduced correspondingly. Cost per bit drops as result.

  8. Implementing a bubble memory hierarchy system

    NASA Technical Reports Server (NTRS)

    Segura, R.; Nichols, C. D.

    1979-01-01

    This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

  9. Prospective memory in the rat

    PubMed Central

    Wilson, A. George; Crystal, Jonathon D.

    2011-01-01

    The content of prospective memory is comprised of representations of an action to perform in the future. When people form prospective memories, they temporarily put the memory representation in an inactive state while engaging in other activities, and then activate the representation in the future. Ultimately, successful activation of the memory representation yields an action at an appropriate, but temporally distant, time. A hallmark of prospective memory is that activation of the memory representation has a deleterious effect on current ongoing activity. Recent evidence suggests that scrub jays and non-human primates, but not other species, are capable of future planning. We hypothesized that prospective memory produces a selective deficit in performance at the time when rats access a memory representation but not when the memory representation is inactive. Rats were trained in a temporal bisection task (90 min/day). Immediately after the bisection task, half of the rats received an 8-g meal (meal group) and the other rats received no additional food (no-meal group). Sensitivity to time in the bisection task was reduced as the 90-min interval elapsed for the meal group but not for the no-meal group. This time-based prospective-memory effect was not based on response competition, an attentional limit, anticipatory contrast, or fatigue. Our results suggest that rats form prospective memories, which produces a negative side effect on ongoing activity. PMID:21922257

  10. A Pilot Memory Café for People with Learning Disabilities and Memory Difficulties

    ERIC Educational Resources Information Center

    Kiddle, Hannah; Drew, Neil; Crabbe, Paul; Wigmore, Jonathan

    2016-01-01

    Memory cafés have been found to normalise experiences of dementia and provide access to an accepting social network. People with learning disabilities are at increased risk of developing dementia, but the possible benefits of attending a memory café are not known. This study evaluates a 12-week pilot memory café for people with learning…

  11. Neural Correlates of Conceptual Implicit Memory and Their Contamination of Putative Neural Correlates of Explicit Memory

    ERIC Educational Resources Information Center

    Voss, Joel L.; Paller, Ken A.

    2007-01-01

    During episodic recognition tests, meaningful stimuli such as words can engender both conscious retrieval (explicit memory) and facilitated access to meaning that is distinct from the awareness of remembering (conceptual implicit memory). Neuroimaging investigations of one type of memory are frequently subject to the confounding influence of the…

  12. Bubble memory module for spacecraft application

    NASA Technical Reports Server (NTRS)

    Hayes, P. J.; Looney, K. T.; Nichols, C. D.

    1985-01-01

    Bubble domain technology offers an all-solid-state alternative for data storage in onboard data systems. A versatile modular bubble memory concept was developed. The key module is the bubble memory module which contains all of the storage devices and circuitry for accessing these devices. This report documents the bubble memory module design and preliminary hardware designs aimed at memory module functional demonstration with available commercial bubble devices. The system architecture provides simultaneous operation of bubble devices to attain high data rates. Banks of bubble devices are accessed by a given bubble controller to minimize controller parts. A power strobing technique is discussed which could minimize the average system power dissipation. A fast initialization method using EEPROM (electrically erasable, programmable read-only memory) devices promotes fast access. Noise and crosstalk problems and implementations to minimize these are discussed. Flight memory systems which incorporate the concepts and techniques of this work could now be developed for applications.

  13. 0.6-1.0 V operation set/reset voltage (3 V) generator for three-dimensional integrated resistive random access memory and NAND flash hybrid solid-state drive

    NASA Astrophysics Data System (ADS)

    Tanaka, Masahiro; Hachiya, Shogo; Ishii, Tomoya; Ning, Sheyang; Tsurumi, Kota; Takeuchi, Ken

    2016-04-01

    A 0.6-1.0 V, 25.9 mm2 boost converter is proposed to generate resistive random access memory (ReRAM) write (set/reset) voltage for three-dimensional (3D) integrated ReRAM and NAND flash hybrid solid-state drive (SSD). The proposed boost converter uses an integrated area-efficient V BUF generation circuit to obtain short ReRAM sector write time, small circuit size, and small energy consumption simultaneously. In specific, the proposed boost converter reduces ReRAM sector write time by 65% compared with a conventional one-stage boost converter (Conventional 1) which uses 1.0 V operating voltage. On the other hand, by using the same ReRAM sector write time, the proposed boost converter reduces 49% circuit area and 46% energy consumption compared with a conventional two-stage boost converter (Conventional 2). In addition, by using the proposed boost converter, the operating voltage, V DD, can be reduced to 0.6 V. The lowest 159 nJ energy consumption can be obtained when V DD is 0.7 V.

  14. Vicarious memories.

    PubMed

    Pillemer, David B; Steiner, Kristina L; Kuwabara, Kie J; Thomsen, Dorthe Kirkegaard; Svob, Connie

    2015-11-01

    People not only have vivid memories of their own personal experiences, but also vicarious memories of events that happened to other people. To compare the phenomenological and functional qualities of personal and vicarious memories, college students described a specific past event that they had recounted to a parent or friend, and also an event that a friend or parent had recounted to them. Although ratings of memory vividness, emotional intensity, visualization, and physical reactions were higher for personal than for vicarious memories, the overall pattern of ratings was similar. Participants' ratings also indicated that vicarious memories serve many of the same life functions as personal memories, although at lower levels of intensity. The findings suggest that current conceptions of autobiographical memory, which focus on past events that happened directly to the self, should be expanded to include detailed mental representations of specific past events that happened to other people.

  15. Multiprocessor memory contention

    SciTech Connect

    Knadler, C.E. Jr.

    1989-01-01

    Caches are frequently incorporated in processor architectures to increase the effective memory speed and to reduce memory contention. However, task switches and the coherency problems of large n-way, mainframe-class multiprocessors lessen the effectiveness of cache architectures for general-purpose applications. A proposed alternative approach is to increase the effective memory bandwidth and decrease memory-access delays through instruction prefetch, operand buffering, highly interleave memory, and multiple-word width processor-memory data paths. This approach was evaluated by comparing cache and noncache system performance, using discrete-event simulation. Since the performance of a multiprocessor architecture is a function of its operating environment was well as its design, the system workload was defined. General-purpose applications, running under multitasking operating systems, were characterized with respect to addressing patterns, paging rates, and frequency of input/output operations. The proposed noncache architecture was found to have performance comparable to that of the cache architectures and obviated then need to solve the cache coherency problem.

  16. Memory Dysfunction

    PubMed Central

    Matthews, Brandy R.

    2015-01-01

    Purpose of Review: This article highlights the dissociable human memory systems of episodic, semantic, and procedural memory in the context of neurologic illnesses known to adversely affect specific neuroanatomic structures relevant to each memory system. Recent Findings: Advances in functional neuroimaging and refinement of neuropsychological and bedside assessment tools continue to support a model of multiple memory systems that are distinct yet complementary and to support the potential for one system to be engaged as a compensatory strategy when a counterpart system fails. Summary: Episodic memory, the ability to recall personal episodes, is the subtype of memory most often perceived as dysfunctional by patients and informants. Medial temporal lobe structures, especially the hippocampal formation and associated cortical and subcortical structures, are most often associated with episodic memory loss. Episodic memory dysfunction may present acutely, as in concussion; transiently, as in transient global amnesia (TGA); subacutely, as in thiamine deficiency; or chronically, as in Alzheimer disease. Semantic memory refers to acquired knowledge about the world. Anterior and inferior temporal lobe structures are most often associated with semantic memory loss. The semantic variant of primary progressive aphasia (svPPA) is the paradigmatic disorder resulting in predominant semantic memory dysfunction. Working memory, associated with frontal lobe function, is the active maintenance of information in the mind that can be potentially manipulated to complete goal-directed tasks. Procedural memory, the ability to learn skills that become automatic, involves the basal ganglia, cerebellum, and supplementary motor cortex. Parkinson disease and related disorders result in procedural memory deficits. Most memory concerns warrant bedside cognitive or neuropsychological evaluation and neuroimaging to assess for specific neuropathologies and guide treatment. PMID:26039844

  17. Encoding and Retrieval in Visual Memory Tasks

    ERIC Educational Resources Information Center

    Frost, Nancy

    1972-01-01

    It was concluded that pictures are encoded differently depending on task expectation. Parallel access of visual and semantic memory codes occurs; but when recognition is expected, a visual cue provides faster access, and when expecting recall, verbal access is more efficient. (Author)

  18. Declarative memory.

    PubMed

    Riedel, Wim J; Blokland, Arjan

    2015-01-01

    Declarative Memory consists of memory for events (episodic memory) and facts (semantic memory). Methods to test declarative memory are key in investigating effects of potential cognition-enhancing substances--medicinal drugs or nutrients. A number of cognitive performance tests assessing declarative episodic memory tapping verbal learning, logical memory, pattern recognition memory, and paired associates learning are described. These tests have been used as outcome variables in 34 studies in humans that have been described in the literature in the past 10 years. Also, the use of episodic tests in animal research is discussed also in relation to the drug effects in these tasks. The results show that nutritional supplementation of polyunsaturated fatty acids has been investigated most abundantly and, in a number of cases, but not all, show indications of positive effects on declarative memory, more so in elderly than in young subjects. Studies investigating effects of registered anti-Alzheimer drugs, cholinesterase inhibitors in mild cognitive impairment, show positive and negative effects on declarative memory. Studies mainly carried out in healthy volunteers investigating the effects of acute dopamine stimulation indicate enhanced memory consolidation as manifested specifically by better delayed recall, especially at time points long after learning and more so when drug is administered after learning and if word lists are longer. The animal studies reveal a different picture with respect to the effects of different drugs on memory performance. This suggests that at least for episodic memory tasks, the translational value is rather poor. For the human studies, detailed parameters of the compositions of word lists for declarative memory tests are discussed and it is concluded that tailored adaptations of tests to fit the hypothesis under study, rather than "off-the-shelf" use of existing tests, are recommended. PMID:25977084

  19. Multilevel resistive information storage and retrieval

    DOEpatents

    Lohn, Andrew; Mickel, Patrick R.

    2016-08-09

    The present invention relates to resistive random-access memory (RRAM or ReRAM) systems, as well as methods of employing multiple state variables to form degenerate states in such memory systems. The methods herein allow for precise write and read steps to form multiple state variables, and these steps can be performed electrically. Such an approach allows for multilevel, high density memory systems with enhanced information storage capacity and simplified information retrieval.

  20. Implementation of Ferroelectric Memories for Space Applications

    NASA Technical Reports Server (NTRS)

    Philpy, Stephen C.; Derbenwick, Gary F.; Kamp, David A.; Isaacson, Alan F.

    2000-01-01

    Ferroelectric random access semiconductor memories (FeRAMs) are an ideal nonvolatile solution for space applications. These memories have low power performance, high endurance and fast write times. By combining commercial ferroelectric memory technology with radiation hardened CMOS technology, nonvolatile semiconductor memories for space applications can be attained. Of the few radiation hardened semiconductor manufacturers, none have embraced the development of radiation hardened FeRAMs, due a limited commercial space market and funding limitations. Government funding may be necessary to assure the development of radiation hardened ferroelectric memories for space applications.

  1. Accessibility Videos.

    PubMed

    Kurppa, Ari; Nordlund, Marika

    2016-01-01

    It can be difficult to understand accessibility, if you do not have the personal experience. The Accessibility Centre ESKE produced short videos which demonstrate the meaning of accessibility in different situations. Videos will raise accessibility awareness of architects, other planners and professionals in the construction field and maintenance. PMID:27534282

  2. Three dimensional magnetic abacus memory

    NASA Astrophysics Data System (ADS)

    Zhang, Shilei; Zhang, Jingyan; Baker, Alexander; Wang, Shouguo; Yu, Guanghua; Hesjedal, Thorsten

    2015-03-01

    Stacking nonvolatile memory cells into a three-dimensional matrix represents a powerful solution for the future of magnetic memory. However, it is technologically challenging to access the individual data in the storage medium if large numbers of bits are stacked on top of each other. Here we introduce a new type of multilevel, nonvolatile magnetic memory concept, the magnetic abacus. Instead of storing information in individual magnetic layers, thereby having to read out each magnetic layer separately, the magnetic abacus adopts a new encoding scheme which envisages a classical abacus with the beads operated by electron spins. It is inspired by the idea of second quantization, dealing with the memory state of the entire stack simultaneously. Direct read operations are implemented by measuring the artificially engineered `quantized' Hall voltage, representing a count of the spin-up and spin-down layers in the stack. This concept of `second quantization of memory' realizes the 3D memory architecture with superior reading and operation efficiency, thus is a promising approach for future nonvolatile magnetic random access memory.

  3. Virtual memory

    NASA Technical Reports Server (NTRS)

    Denning, P. J.

    1986-01-01

    Virtual memory was conceived as a way to automate overlaying of program segments. Modern computers have very large main memories, but need automatic solutions to the relocation and protection problems. Virtual memory serves this need as well and is thus useful in computers of all sizes. The history of the idea is traced, showing how it has become a widespread, little noticed feature of computers today.

  4. A Quantitative Measure of Memory Reference Regularity

    SciTech Connect

    Mohan, T; de Supinski, B R; McKee, S A; Mueller, F; Yoo, A

    2001-10-01

    The memory performance of applications on existing architectures depends significantly on hardware features like prefetching and caching that exploit the locality of the memory accesses. The principle of locality has guided the design of many key micro-architectural features, including cache hierarchies, TLBs, and branch predictors. Quantitative measures of spatial and temporal locality have been useful for predicting the performance of memory hierarchy components. Unfortunately, the concept of locality is constrained to capturing memory access patterns characterized by proximity, while sophisticated memory systems are capable of exploiting other predictable access patterns. Here, we define the concepts of spatial and temporal regularity, and introduce a measure of spatial access regularity to quantify some of this predictability in access patterns. We present an efficient online algorithm to dynamically determine the spatial access regularity in an application's memory references, and demonstrate its use on a set of regular and irregular codes. We find that the use of our algorithm, with its associated overhead of trace generation, slows typical applications by a factor of 50-200, which is at least an order of magnitude better than traditional full trace generation approaches. Our approach can be applied to the characterization of program access patterns and in the implementation of sophisticated, software-assisted prefetching mechanisms, and its inherently parallel nature makes it well suited for use with multi-threaded programs.

  5. Three-dimensional two-photon memory materials and systems

    NASA Astrophysics Data System (ADS)

    Ford, Joseph E.; Hunter, Susan; Piyaket, Ram; Fainman, Yeshaiahu; Esener, Sadik C.; Dvornikov, Alexander S.; Rentzepis, Peter M.

    1993-04-01

    We have been developing a two-photon 3-D memory expected to provide a Tbit storage capacity and a 1 ms access time for secondary storage. Even with this new technology, there still exists a four order of magnitude gap in access times between electronic RAMS and secondary storage. In addition to the existing permanent storage approach, we have begun working on systems, key components, and materials for a dynamic parallel-access 3-D two photon memories that will bridge the gap in primary memory technologies. Over the past three years our team has been developing a write-once mass-storage memory based on two-photon bond dissociation of spirobenzopyran molecules for long lifetime storage. A cache memory must have fast write-erase capability. To achieve this we are beginning to investigate highly sensitive two-photon materials which spontaneous decay (self-erase) to the off state. These materials will be incorporated into dynamic memory systems which continually refresh the memory contents, as in an electronic DRAM. The resulting memory is expected to provide a data capacity of 1 Gbit/cm3 with a 10 ns to 1 microsecond(s) access time and a 10 Tbit/s data rate. In this presentation the latest results of the parallel-access 3-D volume memory using two-photon storage is discussed. We cover material and system considerations for both types of parallel-access memories: fast-access primary storage and large-capacity secondary storage.

  6. CCD Memory

    NASA Technical Reports Server (NTRS)

    Janesick, James R.; Elliot, Tom; Norris, Dave; Vescelus, Fred

    1987-01-01

    CCD memory device yields over 6.4 x 10 to the eighth power levels of information on single chip. Charge-coupled device (CCD) demonstrated to operate as either read-only-memory (ROM) or photon-programmable memory with capacity of 640,000 bits, with each bit capable of being weighted to more than 1,000 discrete analog levels. Larger memory capacities now possible using proposed approach in conjunction with CCD's now being fabricated, which yield over 4 x 10 to the ninth power discrete levels of information on single chip.

  7. Investigation of resistive switching in Cu-doped HfO2 thin film for multilevel non-volatile memory applications

    NASA Astrophysics Data System (ADS)

    Wang, Yan; Liu, Qi; Long, Shibing; Wang, Wei; Wang, Qin; Zhang, Manhong; Zhang, Sen; Li, Yingtao; Zuo, Qingyun; Yang, Jianhong; Liu, Ming

    2010-01-01

    In this paper, the resistive switching characteristics in a Cu/HfO2:Cu/Pt sandwiched structure is investigated for multilevel non-volatile memory applications. The device shows excellent resistive switching performance, including good endurance, long retention time, fast operation speed and a large storage window (ROFF/RON>107). Based on the temperature-dependent test results, the formation of Cu conducting filaments is believed to be the reason for the resistance switching from the OFF state to the ON state. By integrating the resistive switching mechanism study and the device fabrication, different resistance values are achieved using different compliance currents in the program process. These resistance values can be easily distinguished in a large temperature range, and can be maintained over 10 years by extrapolating retention data at room temperature. The integrated experiment and mechanism studies set up the foundation for the development of high-performance multilevel RRAM.

  8. Neural correlates of conceptual implicit memory and their contamination of putative neural correlates of explicit memory.

    PubMed

    Voss, Joel L; Paller, Ken A

    2007-04-01

    During episodic recognition tests, meaningful stimuli such as words can engender both conscious retrieval (explicit memory) and facilitated access to meaning that is distinct from the awareness of remembering (conceptual implicit memory). Neuroimaging investigations of one type of memory are frequently subject to the confounding influence of the other type of memory, thus posing a serious impediment to theoretical advances in this area. We used minimalist visual shapes (squiggles) to attempt to overcome this problem. Subjective ratings of squiggle meaningfulness varied idiosyncratically, and behavioral indications of conceptual implicit memory were evident only for stimuli given higher ratings. These effects did not result from perceptual-based fluency or from explicit remembering. Distinct event-related brain potentials were associated with conceptual implicit memory and with explicit memory by virtue of contrasts based on meaningfulness ratings and memory judgments, respectively. Frontal potentials from 300 to 500 msec after the onset of repeated squiggles varied systematically with perceived meaningfulness. Explicit memory was held constant in this contrast, so these potentials were taken as neural correlates of conceptual implicit memory. Such potentials can contaminate putative neural correlates of explicit memory, in that they are frequently attributed to the expression of explicit memory known as familiarity. These findings provide the first neural dissociation of these two memory phenomena during recognition testing and underscore the necessity of taking both types of memory into account in order to obtain valid neural correlates of specific memory functions. PMID:17412965

  9. Direct memory access transfer completion notification

    DOEpatents

    Archer, Charles J.; Blocksome, Michael A.; Parker, Jeffrey J.

    2010-08-17

    Methods, apparatus, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA engine on an origin compute node in an injection FIFO buffer, a data descriptor for an application message to be transferred to a target compute node on behalf of an application on the origin compute node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying an address of a completion notification field in application storage for the application; transferring, by the origin DMA engine to the target compute node, the message in dependence upon the data descriptor; and notifying, by the origin DMA engine, the application that the transfer of the message is complete, including performing a local direct put operation to store predesignated notification data at the address of the completion notification field.

  10. Direct memory access transfer completion notification

    DOEpatents

    Archer, Charles J. , Blocksome; Michael A. , Parker; Jeffrey J.

    2011-02-15

    Methods, systems, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA on an origin node in an origin injection FIFO, a data descriptor for an application message; inserting, by the origin DMA, a reflection descriptor in the origin injection FIFO, the reflection descriptor specifying a remote get operation for injecting a completion notification descriptor in a reflection injection FIFO on a reflection node; transferring, by the origin DMA to a target node, the message in dependence upon the data descriptor; in response to completing the message transfer, transferring, by the origin DMA to the reflection node, the completion notification descriptor in dependence upon the reflection descriptor; receiving, by the origin DMA from the reflection node, a completion packet; and notifying, by the origin DMA in response to receiving the completion packet, the origin node's processing core that the message transfer is complete.

  11. Direct memory access digital events analyzer

    NASA Astrophysics Data System (ADS)

    Basano, L.; Ottonello, P.

    1989-06-01

    We present a random-point-process multifunction analyzer in which a long sequence of interpulse intervals are recorded in the RAM bank of a personal computer, through a suitably designed front end attached to a commercial DMA interface. Laser light scattered by ground-glass disks and by aqueous suspensions of polystyrene latex spheres has been used to test the performance of the device that may be employed in a broad range of applications.

  12. Multiferroic YCrO3 thin films grown on glass substrate: Resistive switching characteristics

    NASA Astrophysics Data System (ADS)

    Seo, Jeongdae; Ahn, Yoonho; Son, Jong Yeog

    2016-01-01

    Polycrystalline YCrO3 thin films were deposited on (111) Pt/Ta/glass substrates by pulsed laser deposition. The YCrO3 thin films exhibited good ferroelectric properties with remnant polarization of about 5 µC/cm2. Large leakage current was observed by I- V curve and ferroelectric hysteresis loop. The YCrO3 resistive random access memory (RRAM) capacitor showed unipolar switching behaviors with SET and RESET voltages higher than those of general NiO RRAM capacitors. [Figure not available: see fulltext.

  13. 32-Bit-Wide Memory Tolerates Failures

    NASA Technical Reports Server (NTRS)

    Buskirk, Glenn A.

    1990-01-01

    Electronic memory system of 32-bit words corrects bit errors caused by some common type of failures - even failure of entire 4-bit-wide random-access-memory (RAM) chip. Detects failure of two such chips, so user warned that ouput of memory may contain errors. Includes eight 4-bit-wide DRAM's configured so each bit of each DRAM assigned to different one of four parallel 8-bit words. Each DRAM contributes only 1 bit to each 8-bit word.

  14. Runtime and Programming Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory

    SciTech Connect

    Mills, Richard T; Yue, Chuan; Andreas, Stathopoulos; Nikolopoulos, Dimitrios S

    2007-01-01

    The ever increasing memory demands of many scientific applications and the complexity of today's shared computational resources still require the occasional use of virtual memory, network memory, or even out-of-core implementations, with well known drawbacks in performance and usability. In Mills et al. (Adapting to memory pressure from within scientific applications on multiprogrammed COWS. In: International Parallel and Distributed Processing Symposium, IPDPS, Santa Fe, NM, 2004), we introduced a basic framework for a runtime, user-level library, MMlib, in which DRAM is treated as a dynamic size cache for large memory objects residing on local disk. Application developers can specify and access these objects through MMlib, enabling their application to execute optimally under variable memory availability, using as much DRAM as fluctuating memory levels will allow. In this paper, we first extend our earlier MMlib prototype from a proof of concept to a usable, robust, and flexible library. We present a general framework that enables fully customizable memory malleability in a wide variety of scientific applications. We provide several necessary enhancements to the environment sensing capabilities of MMlib, and introduce a remote memory capability, based on MPI communication of cached memory blocks between 'compute nodes' and designated memory servers. The increasing speed of interconnection networks makes a remote memory approach attractive, especially at the large granularity present in large scientific applications. We show experimental results from three important scientific applications that require the general MMlib framework. The memory-adaptive versions perform nearly optimally under constant memory pressure and execute harmoniously with other applications competing for memory, without thrashing the memory system. Under constant memory pressure, we observe execution time improvements of factors between three and

  15. Towards leakage resiliency: memristor-based AES design for differential power attack mitigation

    NASA Astrophysics Data System (ADS)

    Khedkar, Ganesh; Donahue, Colin; Kudithipudi, Dhireesha

    2014-05-01

    Side-channel attacks (SCAs), specifically differential power attacks (DPA), target hardware vulnerabilities of cryptosystems. Next generation computing systems, integrated with emerging technologies such as RRAM, offer unique opportunities to mitigate DPAs with their inherent device characteristics. We propose two different approaches to mitigate DPA attacks using memristive hardware. The first approach, obfuscates the power profile using dual RRAM modules. The power profile stays almost uniform for any given data access. This is achieved by realizing a memory and its complementary module in RRAM hardware. Balancing logic, which ensures the parallel access, is implemented in CMOS. The power consumed with the dual-RRAM balancing is an order lower than the corresponding pure CMOS implementation. The second exploratory approach, uses a novel neuromemristive architecture to compute an AES transformation and mitigate DPAs. Both the proposed approaches were tested on a 128-bit AES algorithm. A customized simulation framework, integrating CAD tools, is developed to mount the DPA attacks. In both the designs, the attack mounted on the baseline architectures (CMOS only) was successful and full key was recovered. However, DPA attacks mounted on the dual RRAM modules and neuromemristive hardware modules of an AES cryptoprocessor yielded no successful keys, demonstrating their resiliency to DPA attacks.

  16. Memory systems.

    PubMed

    Eichenbaum, Howard

    2010-07-01

    The idea that there are multiple memory systems can be traced to early philosophical considerations and introspection. However, the early experimental work considered memory a unitary phenomenon and focused on finding the mechanism upon which memory is based. A full reconciliation of debates about that mechanism, and a coincidental rediscovery of the idea of multiple memory systems, emerged from studies in the cognitive neuroscience of memory. This research has identified three major forms of memory that have distinct operating principles and are supported by different brain systems. These include: (1) a cortical-hippocampal circuit that mediates declarative memory, our capacity to recollect facts and events; (2) procedural memory subsystems involving a cortical-striatal circuit that mediates habit formation and a brainstem-cerebellar circuit that mediates sensorimotor adaptations; and (3) a circuit involving subcortical and cortical pathways through the amygdala that mediates the attachment of affective status and emotional responses to previously neutral stimuli. Copyright © 2010 John Wiley & Sons, Ltd. For further resources related to this article, please visit the WIREs website.

  17. Collaging Memories

    ERIC Educational Resources Information Center

    Wallach, Michele

    2011-01-01

    Even middle school students can have memories of their childhoods, of an earlier time. The art of Romare Bearden and the writings of Paul Auster can be used to introduce ideas about time and memory to students and inspire works of their own. Bearden is an exceptional role model for young artists, not only because of his astounding art, but also…

  18. Episodic Memories

    ERIC Educational Resources Information Center

    Conway, Martin A.

    2009-01-01

    An account of episodic memories is developed that focuses on the types of knowledge they represent, their properties, and the functions they might serve. It is proposed that episodic memories consist of "episodic elements," summary records of experience often in the form of visual images, associated to a "conceptual frame" that provides a…

  19. Vector computer memory bank contention

    SciTech Connect

    Bailey, D.H.

    1987-03-01

    A number of recent vector supercomputer designs have featured main memories with very large capacities, and presumably even larger memories are planned for future generations. While the memory chips used in these computers can store much larger amounts of data than before, their operation speeds are rather slow when compared to the significantly faster CPU (central processing unit) circuitry in new supercomputer designs. A consequence of this speed disparity between CPU's and main memory is that memory access times and memory bank reservation times (as measured in CPU ticks) are sharply increased from previous generations. While it has been recognized that these longer memory operation times will reduce scalar performance, it has not been generally realized that vector performance could suffer as well, due to a sharp increase in memory bank contention. This paper examines this phenomenon using both a Markov chain mathematical model and a Monte Carlo simulation program. The potential for performance reduction is described and techniques for ameliorating this reduction are proposed.

  20. Entorhinal cortex and consolidated memory.

    PubMed

    Takehara-Nishiuchi, Kaori

    2014-07-01

    The entorhinal cortex is thought to support rapid encoding of new associations by serving as an interface between the hippocampus and neocortical regions. Although the entorhinal-hippocampal interaction is undoubtedly essential for initial memory acquisition, the entorhinal cortex contributes to memory retrieval even after the hippocampus is no longer necessary. This suggests that during memory consolidation additional synaptic reinforcement may take place within the cortical network, which may change the connectivity of entorhinal cortex with cortical regions other than the hippocampus. Here, I outline behavioral and physiological findings which collectively suggest that memory consolidation involves the gradual strengthening of connection between the entorhinal cortex and the medial prefrontal/anterior cingulate cortex (mPFC/ACC), a region that may permanently store the learned association. This newly formed connection allows for close interaction between the entorhinal cortex and the mPFC/ACC, through which the mPFC/ACC gains access to neocortical regions that store the content of memory. Thus, the entorhinal cortex may serve as a gatekeeper of cortical memory network by selectively interacting either with the hippocampus or mPFC/ACC depending on the age of memory. This model provides a new framework for a modification of cortical memory network during systems consolidation, thereby adding a fresh dimension to future studies on its biological mechanism.

  1. The nature of early memory.

    PubMed

    Nelson, C A

    1998-01-01

    Despite tremendous gains in our understanding of the development of memory during the infancy period, relatively little is known about the neural bases of early memory. This is unfortunate, as elucidating the neurobiological mechanisms that mediate changes in memory would likely yield important insight into the concept of infantile amnesia, that is, the inability to recall those events that occur during the first 3-4 years of life. This paper begins by describing the major types of memory adults are capable of and the corresponding neural substrate of each type. A brief exposition of the neural bases of memory development is then provided, including a description of recent work that examines long-term memory in infancy. It is concluded that maturation of cortical areas in the temporal and frontal cortices that transpires between the ages of 1 and 4 years likely accounts for our lack of access to our earliest memories. It is also argued that the examination of the electrophysiological correlates of memory development may shed light on these cortical changes.

  2. Eye movement monitoring of memory.

    PubMed

    Ryan, Jennifer D; Riggs, Lily; McQuiggan, Douglas A; McQuiggan, Doug

    2010-08-15

    Explicit (often verbal) reports are typically used to investigate memory (e.g. "Tell me what you remember about the person you saw at the bank yesterday."), however such reports can often be unreliable or sensitive to response bias, and may be unobtainable in some participant populations. Furthermore, explicit reports only reveal when information has reached consciousness and cannot comment on when memories were accessed during processing, regardless of whether the information is subsequently accessed in a conscious manner. Eye movement monitoring (eye tracking) provides a tool by which memory can be probed without asking participants to comment on the contents of their memories, and access of such memories can be revealed on-line. Video-based eye trackers (either head-mounted or remote) use a system of cameras and infrared markers to examine the pupil and corneal reflection in each eye as the participant views a display monitor. For head-mounted eye trackers, infrared markers are also used to determine head position to allow for head movement and more precise localization of eye position. Here, we demonstrate the use of a head-mounted eye tracking system to investigate memory performance in neurologically-intact and neurologically-impaired adults. Eye movement monitoring procedures begin with the placement of the eye tracker on the participant, and setup of the head and eye cameras. Calibration and validation procedures are conducted to ensure accuracy of eye position recording. Real-time recordings of X,Y-coordinate positions on the display monitor are then converted and used to describe periods of time in which the eye is static (i.e. fixations) versus in motion (i.e., saccades). Fixations and saccades are time-locked with respect to the onset/offset of a visual display or another external event (e.g. button press). Experimental manipulations are constructed to examine how and when patterns of fixations and saccades are altered through different types of prior

  3. Memory conformity affects inaccurate memories more than accurate memories.

    PubMed

    Wright, Daniel B; Villalba, Daniella K

    2012-01-01

    After controlling for initial confidence, inaccurate memories were shown to be more easily distorted than accurate memories. In two experiments groups of participants viewed 50 stimuli and were then presented with these stimuli plus 50 fillers. During this test phase participants reported their confidence that each stimulus was originally shown. This was followed by computer-generated responses from a bogus participant. After being exposed to this response participants again rated the confidence of their memory. The computer-generated responses systematically distorted participants' responses. Memory distortion depended on initial memory confidence, with uncertain memories being more malleable than confident memories. This effect was moderated by whether the participant's memory was initially accurate or inaccurate. Inaccurate memories were more malleable than accurate memories. The data were consistent with a model describing two types of memory (i.e., recollective and non-recollective memories), which differ in how susceptible these memories are to memory distortion.

  4. Amnesia is a deficit in relational memory.

    PubMed

    Ryan, J D; Althoff, R R; Whitlow, S; Cohen, N J

    2000-11-01

    Eye movements were monitored to assess memory for scenes indirectly (implicitly). Two eye movement-based memory phenomena were observed: (a) the repetition effect, a decrease in sampling of previously viewed scenes compared with new scenes, reflecting memory for those scenes, and (b) the relational manipulation effect, an increase in viewing of the regions where manipulations of relations among scene elements had occurred. In normal control subjects, the relational manipulation effect was expressed only in the absence of explicit awareness of the scene manipulations. Thus, memory representations of scenes contain information about relations among elements of the scenes, at least some of which is not accessible to verbal report. But amnesic patients with severe memory impairment failed to show the relational manipulation effect. Their failure to show any demonstrable memory for relations among the constituent elements of scenes suggests that amnesia involves a fundamental deficit in relational (declarative) memory processing.

  5. Kanerva's sparse distributed memory: An associative memory algorithm well-suited to the Connection Machine

    NASA Technical Reports Server (NTRS)

    Rogers, David

    1988-01-01

    The advent of the Connection Machine profoundly changes the world of supercomputers. The highly nontraditional architecture makes possible the exploration of algorithms that were impractical for standard Von Neumann architectures. Sparse distributed memory (SDM) is an example of such an algorithm. Sparse distributed memory is a particularly simple and elegant formulation for an associative memory. The foundations for sparse distributed memory are described, and some simple examples of using the memory are presented. The relationship of sparse distributed memory to three important computational systems is shown: random-access memory, neural networks, and the cerebellum of the brain. Finally, the implementation of the algorithm for sparse distributed memory on the Connection Machine is discussed.

  6. Three dimensional magnetic abacus memory

    NASA Astrophysics Data System (ADS)

    Zhang, Shilei; Zhang, Jingyan; Baker, Alexander A.; Wang, Shouguo; Yu, Guanghua; Hesjedal, Thorsten

    2014-08-01

    Stacking nonvolatile memory cells into a three-dimensional matrix represents a powerful solution for the future of magnetic memory. However, it is technologically challenging to access the data in the storage medium if large numbers of bits are stacked on top of each other. Here we introduce a new type of multilevel, nonvolatile magnetic memory concept, the magnetic abacus. Instead of storing information in individual magnetic layers, thereby having to read out each magnetic layer separately, the magnetic abacus adopts a new encoding scheme. It is inspired by the idea of second quantisation, dealing with the memory state of the entire stack simultaneously. Direct read operations are implemented by measuring the artificially engineered `quantised' Hall voltage, each representing a count of the spin-up and spin-down layers in the stack. This new memory system further allows for both flexible scaling of the system and fast communication among cells. The magnetic abacus provides a promising approach for future nonvolatile 3D magnetic random access memory.

  7. Three dimensional magnetic abacus memory.

    PubMed

    Zhang, ShiLei; Zhang, JingYan; Baker, Alexander A; Wang, ShouGuo; Yu, GuangHua; Hesjedal, Thorsten

    2014-08-22

    Stacking nonvolatile memory cells into a three-dimensional matrix represents a powerful solution for the future of magnetic memory. However, it is technologically challenging to access the data in the storage medium if large numbers of bits are stacked on top of each other. Here we introduce a new type of multilevel, nonvolatile magnetic memory concept, the magnetic abacus. Instead of storing information in individual magnetic layers, thereby having to read out each magnetic layer separately, the magnetic abacus adopts a new encoding scheme. It is inspired by the idea of second quantisation, dealing with the memory state of the entire stack simultaneously. Direct read operations are implemented by measuring the artificially engineered 'quantised' Hall voltage, each representing a count of the spin-up and spin-down layers in the stack. This new memory system further allows for both flexible scaling of the system and fast communication among cells. The magnetic abacus provides a promising approach for future nonvolatile 3D magnetic random access memory.

  8. Fully Si compatible SiN resistive switching memory with large self-rectification ratio

    NASA Astrophysics Data System (ADS)

    Kim, Sungjun; Cho, Seongjae; Park, Byung-Gook

    2016-01-01

    In this letter, we report unique unipolar resistive switching memory behaviors in the Ni/Si3N4/p-Si structure by controlling the impurity concentration of Si bottom electrode. It is found that we can decrease the reset current drastically by reducing dopant concentration by reducing dopant concentration, which helps low-power operation in the high density resistive switching memory array. Also, the samples with high impurity concentration exhibited ohmic conduction in the low-resistance state (LRS) while those with low dopant concentration below 1018 cm-3 showed a remarkable self-rectifying behavior. The nonlinear metal-insulator-semiconductor (MIS) diode characteristics in the samples with low doping concentration (˜1018 cm-3) are explained by the formation of Schottky barrier at the metal and semiconductor interface. As a result, we demonstrate high rectification ratio (>105) between forward and reverse currents along with the robust nonvolatile properties including endurance cycles and retention from the devices with large self-rectification ratio. The high self-rectifying characteristics of Si3N4-based RRAM cell would be one of the most virtuous merits in the high-density crossbar array.

  9. A calendar savant with episodic memory impairments.

    PubMed

    Olson, Ingrid R; Berryhill, Marian E; Drowos, David B; Brown, Lawrence; Chatterjee, Anjan

    2010-06-01

    Patients with memory disorders have severely restricted learning and memory. For instance, patients with anterograde amnesia can learn motor procedures and retain some restricted ability to learn new words and factual information. However, such learning is inflexible and frequently inaccessible to conscious awareness. Here we present a case of patient AC596, a 25-year-old male with severe episodic memory impairments, presumably due to anoxia during a preterm birth. In contrast to his poor episodic memory, he exhibits savant-like memory for calendar information that can be flexibly accessed by day, month, and year cues. He also has the ability to recollect the exact date of a wide range of personal experiences over the past 20 years. The patient appears to supplement his generally poor episodic memory by using memorized calendar information as a retrieval cue for autobiographical events. These findings indicate that islands of preserved memory functioning, such as a highly developed semantic memory system, can exist in individuals with severely impaired episodic memory systems. In this particular case, our patient's memory for dates far outstripped that of normal individuals and served as a keen retrieval cue, allowing him to access information that was otherwise unavailable.

  10. A Calendar Savant with Episodic Memory Impairments

    PubMed Central

    Olson, Ingrid R.; Berryhill, Marian E.; Drowos, David B.; Brown, Lawrence; Chatterjee, Anjan

    2010-01-01

    Patients with memory disorders have severely restricted learning and memory. For instance, patients with anterograde amnesia can learn motor procedures as well as retaining some restricted ability to learn new words and factual information. However, such learning is inflexible and frequently inaccessible to conscious awareness. Here we present a case of patient AC596, a 25-year old male with severe episodic memory impairments, presumably due to anoxia during a preterm birth. In contrast to his poor episodic memory, he exhibits savant-like memory for calendar information that can be flexibly accessed by day, month, and year cues. He also has the ability to recollect the exact date of a wide range of personal experiences over the past 20 years. The patient appears to supplement his generally poor episodic memory by using memorized calendar information as a retrieval cue for autobiographical events. These findings indicate that islands of preserved memory functioning, such as a highly developed semantic memory system, can exist in individuals with severely impaired episodic memory systems. In this particular case, our patient’s memory for dates far outstripped that of normal individuals and served as a keen retrieval cue, allowing him to access information that was otherwise unavailable. PMID:20104390

  11. Model of current-limited negative differential resistance in oxide-based resistance-switching devices

    NASA Astrophysics Data System (ADS)

    Chen, Frederick T.

    2015-01-01

    Resistance-switching devices such as resistive random access memories (RRAMs) exhibit the ability to rapidly reduce resistance upon exceeding a threshold voltage, as part of the SET operation. For oxide-based RRAMs, the progressive generation of defects during SET requires strict regulation of the current, e.g., by a transistor, in order to avoid irreversible breakdown. In doing so, the current-limiting device itself takes some voltage burden. The observed negative differential resistance for both the initial (forming) and regular SET operations can be analytically explained with a basic circuit model for the current-limited switching element, linking the voltage transfer to the current-limiting device with the degree of current rise. Consequently, it is found that RRAM operation current is a vital consideration for the reliability of the current-limiting device.

  12. Observation of indium ion migration-induced resistive switching in Al/Mg0.5Ca0.5TiO3/ITO

    NASA Astrophysics Data System (ADS)

    Lin, Zong-Han; Wang, Yeong-Her

    2016-08-01

    Understanding switching mechanisms is very important for resistive random access memory (RRAM) applications. This letter reports an investigation of Al/Mg0.5Ca0.5TiO3 (MCTO)/ITO RRAM, which exhibits bipolar resistive switching behavior. The filaments that connect Al electrodes with indium tin oxide electrodes across the MCTO layer at a low-resistance state are identified. The filaments composed of In2O3 crystals are observed through energy-dispersive X-ray spectroscopy, high-resolution transmission electron microscopy, nanobeam diffraction, and comparisons of Joint Committee on Powder Diffraction Standards (JCPDS) cards. Finally, a switching mechanism resulting from an electrical field induced by In3+ ion migration is proposed. In3+ ion migration forms/ruptures the conductive filaments and sets/resets the RRAM device.

  13. Shared memory for a fault-tolerant computer

    NASA Technical Reports Server (NTRS)

    Gilley, G. C. (Inventor)

    1976-01-01

    A system is described for sharing a memory in a fault-tolerant computer. The memory is under the direct control and monitoring of error detecting and error diagnostic units in the fault-tolerant computer. This computer verifies that data to and from the memory is legally encoded and verifies that words read from the memory at a desired address are, in fact, actually delivered from that desired address. The means are provided for a second processor, which is independent of the direct control and monitoring of the error checking and diagnostic units of the fault-tolerant computer, and to share the memory of the fault-tolerant computer. Circuitry is included to verify that: (1) the processor has properly accessed a desired memory location in the memory; (2) a data word read-out from the memory is properly coded; and (3) no inactive memory was erroneously outputting data onto the shared memory bus.

  14. Staging memory for massively parallel processor

    NASA Technical Reports Server (NTRS)

    Batcher, Kenneth E. (Inventor)

    1988-01-01

    The invention herein relates to a computer organization capable of rapidly processing extremely large volumes of data. A staging memory is provided having a main stager portion consisting of a large number of memory banks which are accessed in parallel to receive, store, and transfer data words simultaneous with each other. Substager portions interconnect with the main stager portion to match input and output data formats with the data format of the main stager portion. An address generator is coded for accessing the data banks for receiving or transferring the appropriate words. Input and output permutation networks arrange the lineal order of data into and out of the memory banks.

  15. Web Accessibility and Accessibility Instruction

    ERIC Educational Resources Information Center

    Green, Ravonne A.; Huprich, Julia

    2009-01-01

    Section 508 of the Americans with Disabilities Act (ADA) mandates that programs and services be accessible to people with disabilities. While schools of library and information science (SLIS*) and university libraries should model accessible Web sites, this may not be the case. This article examines previous studies about the Web accessibility of…

  16. Basic memory module

    NASA Technical Reports Server (NTRS)

    Tietze, F. C.

    1974-01-01

    Construction and electrical characterization of the 4096 x 2-bit Basic Memory Module (BMM) are reported for the Space Ultrareliable Modular Computer (SUMC) program. The module uses four 2K x 1-bit N-channel FET, random access memory chips, called array chips, and two sense amplifier chips, mounted and interconnected on a ceramic substrate. Four 5% tolerance power supplies are required. At the Module, the address, chip select, and array select lines require a 0-8.5 V MOS signal level. The data output, read-strobe, and write-enable lines operate at TTl levels. Although the module is organized as 4096 x 2 bits, it can be used in a 8196 x 1-bit application with appropriate external connections. A 4096 x 1-bit organization can be obtained by depopulating chips.

  17. Misaligned feeding impairs memories

    PubMed Central

    Loh, Dawn H; Jami, Shekib A; Flores, Richard E; Truong, Danny; Ghiani, Cristina A; O’Dell, Thomas J; Colwell, Christopher S

    2015-01-01

    Robust sleep/wake rhythms are important for health and cognitive function. Unfortunately, many people are living in an environment where their circadian system is challenged by inappropriate meal- or work-times. Here we scheduled food access to the sleep time and examined the impact on learning and memory in mice. Under these conditions, we demonstrate that the molecular clock in the master pacemaker, the suprachiasmatic nucleus (SCN), is unaltered while the molecular clock in the hippocampus is synchronized by the timing of food availability. This chronic circadian misalignment causes reduced hippocampal long term potentiation and total CREB expression. Importantly this mis-timed feeding resulted in dramatic deficits in hippocampal-dependent learning and memory. Our findings suggest that the timing of meals have far-reaching effects on hippocampal physiology and learned behaviour. DOI: http://dx.doi.org/10.7554/eLife.09460.001 PMID:26652002

  18. Misaligned feeding impairs memories.

    PubMed

    Loh, Dawn H; Jami, Shekib A; Flores, Richard E; Truong, Danny; Ghiani, Cristina A; O'Dell, Thomas J; Colwell, Christopher S

    2015-01-01

    Robust sleep/wake rhythms are important for health and cognitive function. Unfortunately, many people are living in an environment where their circadian system is challenged by inappropriate meal- or work-times. Here we scheduled food access to the sleep time and examined the impact on learning and memory in mice. Under these conditions, we demonstrate that the molecular clock in the master pacemaker, the suprachiasmatic nucleus (SCN), is unaltered while the molecular clock in the hippocampus is synchronized by the timing of food availability. This chronic circadian misalignment causes reduced hippocampal long term potentiation and total CREB expression. Importantly this mis-timed feeding resulted in dramatic deficits in hippocampal-dependent learning and memory. Our findings suggest that the timing of meals have far-reaching effects on hippocampal physiology and learned behaviour. PMID:26652002

  19. System and method for programmable bank selection for banked memory subsystems

    DOEpatents

    Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

    2010-09-07

    A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

  20. A multilevel nonvolatile magnetoelectric memory

    PubMed Central

    Shen, Jianxin; Cong, Junzhuang; Shang, Dashan; Chai, Yisheng; Shen, Shipeng; Zhai, Kun; Sun, Young

    2016-01-01

    The coexistence and coupling between magnetization and electric polarization in multiferroic materials provide extra degrees of freedom for creating next-generation memory devices. A variety of concepts of multiferroic or magnetoelectric memories have been proposed and explored in the past decade. Here we propose a new principle to realize a multilevel nonvolatile memory based on the multiple states of the magnetoelectric coefficient (α) of multiferroics. Because the states of α depends on the relative orientation between magnetization and polarization, one can reach different levels of α by controlling the ratio of up and down ferroelectric domains with external electric fields. Our experiments in a device made of the PMN-PT/Terfenol-D multiferroic heterostructure confirm that the states of α can be well controlled between positive and negative by applying selective electric fields. Consequently, two-level, four-level, and eight-level nonvolatile memory devices are demonstrated at room temperature. This kind of multilevel magnetoelectric memory retains all the advantages of ferroelectric random access memory but overcomes the drawback of destructive reading of polarization. In contrast, the reading of α is nondestructive and highly efficient in a parallel way, with an independent reading coil shared by all the memory cells. PMID:27681812

  1. An empirical hierarchical memory model based on hardware performance counters

    SciTech Connect

    Lubeck, O.M.; Luo, Y.; Wasserman, H.; Bassetti, F.

    1998-09-01

    In this paper, the authors characterize application performance with a memory-centric view. Using a simple strategy and performance data measured by on-chip hardware performance counters, they model the performance of a simple memory hierarchy and infer the contribution of each level in the memory system to an application`s overall cycles per instruction (cpi). They account for the overlap of processor execution with memory accesses--a key parameter not directly measurable on most systems. They infer the separate contributions of three major architecture features in the memory subsystem of the Origin 2000: cache size, outstanding loads-under-miss, and memory latency.

  2. Fear Memory.

    PubMed

    Izquierdo, Ivan; Furini, Cristiane R G; Myskiw, Jociane C

    2016-04-01

    Fear memory is the best-studied form of memory. It was thoroughly investigated in the past 60 years mostly using two classical conditioning procedures (contextual fear conditioning and fear conditioning to a tone) and one instrumental procedure (one-trial inhibitory avoidance). Fear memory is formed in the hippocampus (contextual conditioning and inhibitory avoidance), in the basolateral amygdala (inhibitory avoidance), and in the lateral amygdala (conditioning to a tone). The circuitry involves, in addition, the pre- and infralimbic ventromedial prefrontal cortex, the central amygdala subnuclei, and the dentate gyrus. Fear learning models, notably inhibitory avoidance, have also been very useful for the analysis of the biochemical mechanisms of memory consolidation as a whole. These studies have capitalized on in vitro observations on long-term potentiation and other kinds of plasticity. The effect of a very large number of drugs on fear learning has been intensively studied, often as a prelude to the investigation of effects on anxiety. The extinction of fear learning involves to an extent a reversal of the flow of information in the mentioned structures and is used in the therapy of posttraumatic stress disorder and fear memories in general. PMID:26983799

  3. Fear Memory.

    PubMed

    Izquierdo, Ivan; Furini, Cristiane R G; Myskiw, Jociane C

    2016-04-01

    Fear memory is the best-studied form of memory. It was thoroughly investigated in the past 60 years mostly using two classical conditioning procedures (contextual fear conditioning and fear conditioning to a tone) and one instrumental procedure (one-trial inhibitory avoidance). Fear memory is formed in the hippocampus (contextual conditioning and inhibitory avoidance), in the basolateral amygdala (inhibitory avoidance), and in the lateral amygdala (conditioning to a tone). The circuitry involves, in addition, the pre- and infralimbic ventromedial prefrontal cortex, the central amygdala subnuclei, and the dentate gyrus. Fear learning models, notably inhibitory avoidance, have also been very useful for the analysis of the biochemical mechanisms of memory consolidation as a whole. These studies have capitalized on in vitro observations on long-term potentiation and other kinds of plasticity. The effect of a very large number of drugs on fear learning has been intensively studied, often as a prelude to the investigation of effects on anxiety. The extinction of fear learning involves to an extent a reversal of the flow of information in the mentioned structures and is used in the therapy of posttraumatic stress disorder and fear memories in general.

  4. Access Denied

    ERIC Educational Resources Information Center

    Villano, Matt

    2008-01-01

    Building access control (BAC)--a catchall phrase to describe the systems that control access to facilities across campus--has traditionally been handled with remarkably low-tech solutions: (1) manual locks; (2) electronic locks; and (3) ID cards with magnetic strips. Recent improvements have included smart cards and keyless solutions that make use…

  5. Open Access

    ERIC Educational Resources Information Center

    Suber, Peter

    2012-01-01

    The Internet lets us share perfect copies of our work with a worldwide audience at virtually no cost. We take advantage of this revolutionary opportunity when we make our work "open access": digital, online, free of charge, and free of most copyright and licensing restrictions. Open access is made possible by the Internet and copyright-holder…

  6. Working Memory at Work: How the Updating Process Alters the Nature of Working Memory Transfer

    PubMed Central

    Zhang, Yanmin; Verhaeghen, Paul; Cerella, John

    2011-01-01

    In three N-Back experiments, we investigated components of the process of working memory (WM) updating, more specifically access to items stored outside the focus of attention and transfer from the focus to the region of WM outside the focus. We used stimulus complexity as a marker. We found that when WM transfer occurred under full attention, it was slow and highly sensitive to stimulus complexity, much more so than WM access. When transfer occurred in conjunction with access, however, it was fast and no longer sensitive to stimulus complexity. Thus the updating context altered the nature of WM processing: The dual-task situation (transfer in conjunction with access) drove memory transfer into a more efficient mode, indifferent to stimulus complexity. In contrast, access times consistently increased with complexity, unaffected by the processing context. This study reinforces recent reports that retrieval is a (perhaps the) key component of working memory functioning. PMID:22105718

  7. Sparse distributed memory: Principles and operation

    NASA Technical Reports Server (NTRS)

    Flynn, M. J.; Kanerva, P.; Bhadkamkar, N.

    1989-01-01

    Sparse distributed memory is a generalized random access memory (RAM) for long (1000 bit) binary words. Such words can be written into and read from the memory, and they can also be used to address the memory. The main attribute of the memory is sensitivity to similarity, meaning that a word can be read back not only by giving the original write address but also by giving one close to it as measured by the Hamming distance between addresses. Large memories of this kind are expected to have wide use in speech recognition and scene analysis, in signal detection and verification, and in adaptive control of automated equipment, in general, in dealing with real world information in real time. The memory can be realized as a simple, massively parallel computer. Digital technology has reached a point where building large memories is becoming practical. Major design issues were resolved which were faced in building the memories. The design is described of a prototype memory with 256 bit addresses and from 8 to 128 K locations for 256 bit words. A key aspect of the design is extensive use of dynamic RAM and other standard components.

  8. Vertically Integrated Nanowire-Based Unified Memory.

    PubMed

    Lee, Byung-Hyun; Ahn, Dae-Chul; Kang, Min-Ho; Jeon, Seung-Bae; Choi, Yang-Kyu

    2016-09-14

    A vertically integrated nanowire-based device for multifunctional unified memory that combine dynamic random access memory (DRAM) and flash memory in a single transistor is demonstrated for the first time. The device utilizes a gate-all-around (GAA) structure that completely surrounds the nanowire; the structure is built on a bulk silicon wafer. A vertically integrated unified memory (VIUM) device composed of five-story channels was fabricated via the one-route all-dry etching process (ORADEP) with reliable reproducibility, stiction-free stability, and high uniformity. In each DRAM and flash memory operation, the five-story VIUM showed a remarkably enhanced sensing current drivability compared with one-story unified memory (UM) characteristics. In addition to each independent memory mode, the switching endurance of the VIUM was evaluated in the unified mode, which alternatively activates two memory modes, resulting in an even higher sensing memory window than that of the UM. In addition to our previous work on a logic transistor joining high performance with good scalability, this work describes a novel memory hierarchy design with high functionality for system-on-chip (SoC) architectures, demonstrating the practicality and versatility of the vertically integrated nanowire configuration for use in various applications.

  9. Vertically Integrated Nanowire-Based Unified Memory.

    PubMed

    Lee, Byung-Hyun; Ahn, Dae-Chul; Kang, Min-Ho; Jeon, Seung-Bae; Choi, Yang-Kyu

    2016-09-14

    A vertically integrated nanowire-based device for multifunctional unified memory that combine dynamic random access memory (DRAM) and flash memory in a single transistor is demonstrated for the first time. The device utilizes a gate-all-around (GAA) structure that completely surrounds the nanowire; the structure is built on a bulk silicon wafer. A vertically integrated unified memory (VIUM) device composed of five-story channels was fabricated via the one-route all-dry etching process (ORADEP) with reliable reproducibility, stiction-free stability, and high uniformity. In each DRAM and flash memory operation, the five-story VIUM showed a remarkably enhanced sensing current drivability compared with one-story unified memory (UM) characteristics. In addition to each independent memory mode, the switching endurance of the VIUM was evaluated in the unified mode, which alternatively activates two memory modes, resulting in an even higher sensing memory window than that of the UM. In addition to our previous work on a logic transistor joining high performance with good scalability, this work describes a novel memory hierarchy design with high functionality for system-on-chip (SoC) architectures, demonstrating the practicality and versatility of the vertically integrated nanowire configuration for use in various applications. PMID:27579769

  10. Sparse distributed memory prototype: Principles of operation

    NASA Technical Reports Server (NTRS)

    Flynn, Michael J.; Kanerva, Pentti; Ahanin, Bahram; Bhadkamkar, Neal; Flaherty, Paul; Hickey, Philip

    1988-01-01

    Sparse distributed memory is a generalized random access memory (RAM) for long binary words. Such words can be written into and read from the memory, and they can be used to address the memory. The main attribute of the memory is sensitivity to similarity, meaning that a word can be read back not only by giving the original right address but also by giving one close to it as measured by the Hamming distance between addresses. Large memories of this kind are expected to have wide use in speech and scene analysis, in signal detection and verification, and in adaptive control of automated equipment. The memory can be realized as a simple, massively parallel computer. Digital technology has reached a point where building large memories is becoming practical. The research is aimed at resolving major design issues that have to be faced in building the memories. The design of a prototype memory with 256-bit addresses and from 8K to 128K locations for 256-bit words is described. A key aspect of the design is extensive use of dynamic RAM and other standard components.

  11. Fueling Memories

    PubMed Central

    Powell, Jonathan D.; Pollizzi, Kristen

    2012-01-01

    A hallmark of the adaptive immune response is rapid and robust activation upon rechallenge. In the current issue of Immunity van der Windt et al. (2012) provide an important link between mitochondrial respiratory capacity and the development of CD8+ T cell memory. PMID:22284413

  12. Memory Loss

    ERIC Educational Resources Information Center

    Cassebaum, Anne

    2011-01-01

    In four decades of teaching college English, the author has watched many good teaching jobs morph into second-class ones. Worse, she has seen the memory and then the expectation of teaching jobs with decent status, security, and salary depart along with principles and collegiality. To help reverse this downward spiral, she contends that what is…

  13. Gaining Access.

    ERIC Educational Resources Information Center

    Kennedy, Mike

    2000-01-01

    Discusses issues schools and universities have encountered in complying with the Americans with Disabilities Act (ADA) and making their facilities more accessible to the disabled. The ADA's vagueness and the architect's need for understanding the regulations is highlighted. (GR)

  14. Equal Access.

    ERIC Educational Resources Information Center

    De Patta, Joe

    2003-01-01

    Presents an interview with Stephen McCarthy, co-partner and president of Equal Access ADA Consulting Architects of San Diego, California, about designing schools to naturally integrate compliance with the Americans with Disabilities Act (ADA). (EV)

  15. Capital access.

    PubMed

    Towne, Jennifer

    2004-06-01

    To maintain their viability, hospitals are being compelled to invest in big capital projects such as information technology and renovation and construction. This gatefold examines the trends in credit and capital, and how they affect hospitals' access to money.

  16. Portal aspects of memory overlay in psychoanalysis. An object relations contribution to screen memory phenomena.

    PubMed

    Spero, M H

    1990-01-01

    Distortion in screen memories illustrates the unique manner in which part-object representations unite perceptions from different temporal periods. "Portal" aspects of a given source memory designate anachronistic distortions borrowed from perceptions at a subsequent time when the source memory and its full emotional significance attempted access to consciousness. The unconscious perception of recall at the subsequent occasion is represented by the appearance of portal details in the source dream. The portal concept is related to object relations theory and the psychology of memory.

  17. 32-Bit computer for large memory applications on FASTBUS

    SciTech Connect

    Blossom, J.M.; Hong, J.P.; Kellner, R.G.

    1985-01-01

    A FASTBUS based 32-bit computer is being built at Los Alamos National Laboratory for use in systems requiring large fast memory in the FASTBUS environment. A separate local execution bus allows data reduction to proceed concurrently with other FASTBUS operations. The computer, which can operate in either master or slave mode, includes the National Semiconductor NS32032 chip set with demand paged memory management, floating point slave processor, interrupt control unit, timers, and time-of-day clock. The 16.0 megabytes of random access memory are interleaved to allow windowed direct memory access on and off the FASTBUS at 80 megabytes per second.

  18. Short-term memory to long-term memory transition in a nanoscale memristor.

    PubMed

    Chang, Ting; Jo, Sung-Hyun; Lu, Wei

    2011-09-27

    "Memory" is an essential building block in learning and decision-making in biological systems. Unlike modern semiconductor memory devices, needless to say, human memory is by no means eternal. Yet, forgetfulness is not always a disadvantage since it releases memory storage for more important or more frequently accessed pieces of information and is thought to be necessary for individuals to adapt to new environments. Eventually, only memories that are of significance are transformed from short-term memory into long-term memory through repeated stimulation. In this study, we show experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems. By stimulating the memristor with repeated voltage pulses, we observe an effect analogous to memory transition in biological systems with much improved retention time accompanied by additional structural changes in the memristor. We verify that not only the shape or the total number of stimuli is influential, but also the time interval between stimulation pulses (i.e., the stimulation rate) plays a crucial role in determining the effectiveness of the transition. The memory enhancement and transition of the memristor device was explained from the microscopic picture of impurity redistribution and can be qualitatively described by the same equations governing biological memories.

  19. Integrated Vertical Bloch Line (VBL) memory

    NASA Technical Reports Server (NTRS)

    Katti, R. R.; Wu, J. C.; Stadler, H. L.

    1991-01-01

    Vertical Bloch Line (VBL) Memory is a recently conceived, integrated, solid state, block access, VLSI memory which offers the potential of 1 Gbit/sq cm areal storage density, data rates of hundreds of megabits/sec, and submillisecond average access time simultaneously at relatively low mass, volume, and power values when compared to alternative technologies. VBLs are micromagnetic structures within magnetic domain walls which can be manipulated using magnetic fields from integrated conductors. The presence or absence of BVL pairs are used to store binary information. At present, efforts are being directed at developing a single chip memory using 25 Mbit/sq cm technology in magnetic garnet material which integrates, at a single operating point, the writing, storage, reading, and amplification functions needed in a memory. The current design architecture, functional elements, and supercomputer simulation results are described which are used to assist the design process.

  20. Hemodialysis access - self care

    MedlinePlus

    Kidney failure - chronic-hemodialysis access; Renal failure - chronic-hemodialysis access; Chronic renal insufficiency - hemodialysis access; Chronic kidney failure - hemodialysis access; Chronic renal failure - hemodialysis access; dialysis - hemodialysis access

  1. Memory-assisted measurement-device-independent quantum key distribution

    NASA Astrophysics Data System (ADS)

    Panayi, Christiana; Razavi, Mohsen; Ma, Xiongfeng; Lütkenhaus, Norbert

    2014-04-01

    A protocol with the potential of beating the existing distance records for conventional quantum key distribution (QKD) systems is proposed. It borrows ideas from quantum repeaters by using memories in the middle of the link, and that of measurement-device-independent QKD, which only requires optical source equipment at the user's end. For certain memories with short access times, our scheme allows a higher repetition rate than that of quantum repeaters with single-mode memories, thereby requiring lower coherence times. By accounting for various sources of nonideality, such as memory decoherence, dark counts, misalignment errors, and background noise, as well as timing issues with memories, we develop a mathematical framework within which we can compare QKD systems with and without memories. In particular, we show that with the state-of-the-art technology for quantum memories, it is potentially possible to devise memory-assisted QKD systems that, at certain distances of practical interest, outperform current QKD implementations.

  2. Autobiographical memory specificity in dissociative identity disorder.

    PubMed

    Huntjens, Rafaële J C; Wessel, Ineke; Hermans, Dirk; van Minnen, Agnes

    2014-05-01

    A lack of adequate access to autobiographical knowledge has been related to psychopathology. More specifically, patients suffering from depression or a history of trauma have been found to be characterized by overgeneral memory, in other words, they show a relative difficulty in retrieving a specific event from memory located in time and place. Previous studies of overgeneral memory have not included patients with dissociative disorders. These patients are interesting to consider, as they are hypothesized to have the ability to selectively compartmentalize information linked to negative emotions. This study examined avoidance and overgeneral memory in patients with dissociative identity disorder (DID; n = 12). The patients completed the autobiographical memory test (AMT). Their performance was compared with control groups of posttraumatic stress disorder (PTSD) patients (n = 26), healthy controls (n = 29), and DID simulators (n = 26). Specifically, we compared the performance of separate identity states in DID hypothesized to diverge in the use of avoidance as a coping strategy to deal with negative affect. No significant differences in memory specificity were found between the separate identities in DID. Irrespective of identity state, DID patients were characterized by a lack of memory specificity, which was similar to the lack of memory specificity found in PTSD patients. The converging results for DID and PTSD patients add empirical evidence for the role of overgeneral memory involved in the maintenance of posttraumatic psychopathology. PMID:24886016

  3. Autobiographical memory specificity in dissociative identity disorder.

    PubMed

    Huntjens, Rafaële J C; Wessel, Ineke; Hermans, Dirk; van Minnen, Agnes

    2014-05-01

    A lack of adequate access to autobiographical knowledge has been related to psychopathology. More specifically, patients suffering from depression or a history of trauma have been found to be characterized by overgeneral memory, in other words, they show a relative difficulty in retrieving a specific event from memory located in time and place. Previous studies of overgeneral memory have not included patients with dissociative disorders. These patients are interesting to consider, as they are hypothesized to have the ability to selectively compartmentalize information linked to negative emotions. This study examined avoidance and overgeneral memory in patients with dissociative identity disorder (DID; n = 12). The patients completed the autobiographical memory test (AMT). Their performance was compared with control groups of posttraumatic stress disorder (PTSD) patients (n = 26), healthy controls (n = 29), and DID simulators (n = 26). Specifically, we compared the performance of separate identity states in DID hypothesized to diverge in the use of avoidance as a coping strategy to deal with negative affect. No significant differences in memory specificity were found between the separate identities in DID. Irrespective of identity state, DID patients were characterized by a lack of memory specificity, which was similar to the lack of memory specificity found in PTSD patients. The converging results for DID and PTSD patients add empirical evidence for the role of overgeneral memory involved in the maintenance of posttraumatic psychopathology.

  4. Shifting self, shifting memory: testing the self-memory system model with hypnotic identity delusions.

    PubMed

    Cox, Rochelle E; Barnier, Amanda J

    2013-01-01

    According to Conway's self-memory system (SMS) model, autobiographical memories may be facilitated, inhibited, or misremembered to be consistent with current self. In 3 experiments, the authors tested this by hypnotically suggesting an identity delusion and indexing whether this shift in self produced a corresponding shift in autobiographical memory. High hypnotizable participants displayed a compelling identity delusion and elicited specific autobiographical events that they could justify when challenged. These memories were reinterpretations of previous experiences that supported the suggested identity. Importantly, autobiographical memories that were no longer consistent with the hypnotically deluded self were less accessible than other memories. The authors discuss these findings in the context of Conway's SMS model and propose 2 accounts of autobiographical remembering during hypnotic and clinical delusions.

  5. Vertical bloch line memory

    NASA Technical Reports Server (NTRS)

    Katti, R.; Wu, J.; Stadler, H.

    1990-01-01

    Vertical Bloch Line (VBL) memory is a recently conceived, integrated, solid-state, block-access, VLSI memory which offers the potential of 1Gbit/sq cm real storage density, gigabit per second data rates, and sub-millisecond average access times simultaneously at relatively low mass, volume, and power values when compared to alternative technologies. VBL's are micromagnetic structures within magnetic domain walls which can be manipulated using magnetic fields from integrated conductors. The presence or absence of VBL pairs are used to store binary information. At present, efforts are being directed at developing a single-chip memory using 25Mbit/sq cm technology in magnetic garnet material which integrates, at a single operating point, the writing, storage, reading, and amplification functions needed in a memory. This paper describes the current design architecture, functional elements, and supercomputer simulation results which are used to assist the design process. The current design architecture uses three metal layers, two ion implantation steps for modulating the thickness of the magnetic layer, one ion implantation step for assisting propagation in the major line track, one NiFe soft magnetic layer, one CoPt hard magnetic layer, and one reflective Cr layer for facilitating magneto-optic observation of magnetic structure. Data are stored in a series of elongated magnetic domains, called stripes, which serve as storage sites for arrays of VBL pairs. The ends of these stripes are placed near conductors which serve as VBL read/write gates. A major line track is present to provide a source and propagation path for magnetic bubbles. Writing and reading, respectively, are achieved by converting magnetic bubbles to VBL's and vice versa. The output function is effected by stretching a magnetic bubble and detecting it magnetoresistively. Experimental results from the past design cycle created four design goals for the current design cycle. First, the bias field ranges

  6. Radiation Tolerant Intelligent Memory Stack (RTIMS)

    NASA Technical Reports Server (NTRS)

    Ng, Tak-kwong; Herath, Jeffrey A.

    2006-01-01

    The Radiation Tolerant Intelligent Memory Stack (RTIMS), suitable for both geostationary and low earth orbit missions, has been developed. The memory module is fully functional and undergoing environmental and radiation characterization. A self-contained flight-like module is expected to be completed in 2006. RTIMS provides reconfigurable circuitry and 2 gigabits of error corrected or 1 gigabit of triple redundant digital memory in a small package. RTIMS utilizes circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuitries are stacked into a module of 42.7mm x 42.7mm x 13.00mm. Triple module redundancy, current limiting, configuration scrubbing, and single event function interrupt detection are employed to mitigate radiation effects. The mitigation techniques significantly simplify system design. RTIMS is well suited for deployment in real-time data processing, reconfigurable computing, and memory intensive applications.

  7. Adiabatic quantum optimization for associative memory recall

    SciTech Connect

    Seddiqi, Hadayat; Humble, Travis S.

    2014-12-22

    Hopfield networks are a variant of associative memory that recall patterns stored in the couplings of an Ising model. Stored memories are conventionally accessed as fixed points in the network dynamics that correspond to energetic minima of the spin state. We show that memories stored in a Hopfield network may also be recalled by energy minimization using adiabatic quantum optimization (AQO). Numerical simulations of the underlying quantum dynamics allow us to quantify AQO recall accuracy with respect to the number of stored memories and noise in the input key. We investigate AQO performance with respect to how memories are stored in the Ising model according to different learning rules. Our results demonstrate that AQO recall accuracy varies strongly with learning rule, a behavior that is attributed to differences in energy landscapes. Consequently, learning rules offer a family of methods for programming adiabatic quantum optimization that we expect to be useful for characterizing AQO performance.

  8. Adiabatic quantum optimization for associative memory recall

    DOE PAGES

    Seddiqi, Hadayat; Humble, Travis S.

    2014-12-22

    Hopfield networks are a variant of associative memory that recall patterns stored in the couplings of an Ising model. Stored memories are conventionally accessed as fixed points in the network dynamics that correspond to energetic minima of the spin state. We show that memories stored in a Hopfield network may also be recalled by energy minimization using adiabatic quantum optimization (AQO). Numerical simulations of the underlying quantum dynamics allow us to quantify AQO recall accuracy with respect to the number of stored memories and noise in the input key. We investigate AQO performance with respect to how memories are storedmore » in the Ising model according to different learning rules. Our results demonstrate that AQO recall accuracy varies strongly with learning rule, a behavior that is attributed to differences in energy landscapes. Consequently, learning rules offer a family of methods for programming adiabatic quantum optimization that we expect to be useful for characterizing AQO performance.« less

  9. SODR Memory Control Buffer Control ASIC

    NASA Technical Reports Server (NTRS)

    Hodson, Robert F.

    1994-01-01

    The Spacecraft Optical Disk Recorder (SODR) is a state of the art mass storage system for future NASA missions requiring high transmission rates and a large capacity storage system. This report covers the design and development of an SODR memory buffer control applications specific integrated circuit (ASIC). The memory buffer control ASIC has two primary functions: (1) buffering data to prevent loss of data during disk access times, (2) converting data formats from a high performance parallel interface format to a small computer systems interface format. Ten 144 p in, 50 MHz CMOS ASIC's were designed, fabricated and tested to implement the memory buffer control function.

  10. Programming distributed memory architectures using Kali

    NASA Technical Reports Server (NTRS)

    Mehrotra, Piyush; Vanrosendale, John

    1990-01-01

    Programming nonshared memory systems is more difficult than programming shared memory systems, in part because of the relatively low level of current programming environments for such machines. A new programming environment is presented, Kali, which provides a global name space and allows direct access to remote data values. In order to retain efficiency, Kali provides a system on annotations, allowing the user to control those aspects of the program critical to performance, such as data distribution and load balancing. The primitives and constructs provided by the language is described, and some of the issues raised in translating a Kali program for execution on distributed memory systems are also discussed.

  11. Radiation Test Challenges for Scaled Commerical Memories

    NASA Technical Reports Server (NTRS)

    LaBel, Kenneth A.; Ladbury, Ray L.; Cohn, Lewis M.; Oldham, Timothy

    2007-01-01

    As sub-100nm CMOS technologies gather interest, the radiation effects performance of these technologies provide a significant challenge. In this talk, we shall discuss the radiation testing challenges as related to commercial memory devices. The focus will be on complex test and failure modes emerging in state-of-the-art Flash non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs), which are volatile. Due to their very high bit density, these device types are highly desirable for use in the natural space environment. In this presentation, we shall discuss these devices with emphasis on considerations for test and qualification methods required.

  12. Easy Access

    ERIC Educational Resources Information Center

    Gettelman, Alan

    2009-01-01

    School and university restrooms, locker and shower rooms have specific ADA accessibility requirements that serve the needs of staff, students and campus visitors who are disabled as a result of injury, illness or age. Taking good care of them is good for the reputation of a sensitive community institution, and fosters positive public relations.…

  13. Access Denied

    ERIC Educational Resources Information Center

    Raths, David

    2012-01-01

    As faculty members add online and multimedia elements to their courses, colleges and universities across the country are realizing that there is a lot of work to be done to ensure that disabled students (and employees) have equal access to course material and university websites. Unfortunately, far too few schools consider the task a top priority.…

  14. Expanding Access

    ERIC Educational Resources Information Center

    Roach, Ronald

    2007-01-01

    There is no question that the United States lags behind most industrialized nations in consumer access to broadband Internet service. For many policy makers and activists, this shortfall marks the latest phase in the struggle to overcome the digital divide. To remedy this lack of broadband affordability and availability, one start-up firm--with…

  15. Age, memory type, and the phenomenology of autobiographical memory: findings from an Italian sample.

    PubMed

    Montebarocci, Ornella; Luchetti, Martina; Sutin, Angelina R

    2014-01-01

    The present research explored differences in phenomenology between two types of memories, a general self-defining memory and an earliest childhood memory. A sample of 76 Italian participants were selected and categorised into two age groups: 20-30 years and 31-40 years. The Memory Experiences Questionnaire (MEQ) was administered, taking note of latency and duration times of the narratives. Consistent with the literature, the self-defining memory differed significantly from the earliest childhood memory in terms of phenomenology, with the recency of the memory associated with more intense phenomenological experience. The self-defining memory took longer to retrieve and narrate than the earliest childhood memory. Meaningful differences also emerged between the two age groups: Participants in their 30s rated their self-defining memory as more vivid, coherent, and accessible than participants in their 20s. According to latency findings, these differences suggest an expanded period of identity consolidation for younger adults. Further applications of the MEQ should be carried out to replicate these results with other samples of young adults.

  16. Memory-intensive benchmarks: IRAM vs. cache-based machines

    SciTech Connect

    Gaeke, Brian G.; Husbands, Parry; Kim, Hyun Jin; Li, Xiaoye S.; Moon, Hyun Jin; Oliker, Leonid; Yelick, Katherine A.; Biswas, Rupak

    2001-09-29

    The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we explore the performance of a set of memory-intensive benchmarks and use them to compare the performance of conventional cache-based microprocessors to a mixed logic and DRAM processor called VIRAM. The benchmarks are based on problem statements, rather than specific implementations, and in each case we explore the fundamental hardware requirements of the problem, as well as alternative algorithms and data structures that can help expose fine-grained parallelism or simplify memory access patterns. The benchmarks are characterized by their memory access patterns, their basic structures, and the ratio of computation to memory operation.

  17. Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines

    NASA Technical Reports Server (NTRS)

    Biswas, Rupak; Gaeke, Brian R.; Husbands, Parry; Li, Xiaoye S.; Oliker, Leonid; Yelick, Katherine A.; Biegel, Bryan (Technical Monitor)

    2002-01-01

    The increasing gap between processor and memory performance has lead to new architectural models for memory-intensive applications. In this paper, we explore the performance of a set of memory-intensive benchmarks and use them to compare the performance of conventional cache-based microprocessors to a mixed logic and DRAM processor called VIRAM. The benchmarks are based on problem statements, rather than specific implementations, and in each case we explore the fundamental hardware requirements of the problem, as well as alternative algorithms and data structures that can help expose fine-grained parallelism or simplify memory access patterns. The benchmarks are characterized by their memory access patterns, their basic control structures, and the ratio of computation to memory operation.

  18. Improved Readout For Micromagnet/Hall-Effect Memories

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1993-01-01

    Two improved readout circuits for micromagnet/Hall-effect random-access memories designed to eliminate current shunts introducing errors into outputs of older readout circuits. Incorporate additional switching transistors to isolate Hall sensors as needed.

  19. Multilayer self-structured bubble memories

    NASA Technical Reports Server (NTRS)

    Kamin, M.; Krawczak, J. A.; Lins, S. J.; Torok, E. J.; Stermer, R. L., Jr.

    1979-01-01

    Research work on multilayer self-structured bubble memories is at an early stage. The coupling of bubbles to stripes is investigated theoretically and experimentally and shown to be adequate for propagation. Propagation of stripes is demonstrated both by current access and field access techniques. These propagation techniques are of prime interest because they can eliminate most photographic features from the storage area. Multilayer films offer great promise for higher-capacity higher-density memories in which most of the photolithography has been eliminated and the minimum feature size of much of the remaining has been increased. Furthermore, stripe propagation can be carried out with current access, providing a significant reduction in packaging cost and power consumption over field access devices.

  20. Hemispheric Differences in the Organization of Memory for Text Ideas

    ERIC Educational Resources Information Center

    Long, Debra L.; Johns, Clinton L.; Jonathan, Eunike

    2012-01-01

    The goal of this study was to examine hemispheric asymmetries in episodic memory for discourse. Access to previously comprehended information is essential for mapping incoming information to representations of "who did what to whom" in memory. An item-priming-in-recognition paradigm was used to examine differences in how the hemispheres represent…