Science.gov

Sample records for advanced integrated circuits

  1. SEU In An Advanced Bipolar Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Zoutendyk, John A.; Secrest, Elaine C.; Berndt, Dale F.

    1989-01-01

    Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

  2. Monolithic microwave integrated circuit technology for advanced space communication

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Romanofsky, Robert R.

    1988-01-01

    Future Space Communications subsystems will utilize GaAs Monolithic Microwave Integrated Circuits (MMIC's) to reduce volume, weight, and cost and to enhance system reliability. Recent advances in GaAs MMIC technology have led to high-performance devices which show promise for insertion into these next generation systems. The status and development of a number of these devices operating from Ku through Ka band will be discussed along with anticipated potential applications.

  3. Advanced polymer systems for optoelectronic integrated circuit applications

    NASA Astrophysics Data System (ADS)

    Eldada, Louay A.; Stengel, Kelly M. T.; Shacklette, Lawrence W.; Norwood, Robert A.; Xu, Chengzeng; Wu, Chengjiu; Yardley, James T.

    1997-01-01

    An advanced versatile low-cost polymeric waveguide technology is proposed for optoelectronic integrated circuit applications. We have developed high-performance organic polymeric materials that can be readily made into both multimode and single-mode optical waveguide structures of controlled numerical aperture (NA) and geometry. These materials are formed from highly crosslinked acrylate monomers with specific linkages that determine properties such as flexibility, toughness, loss, and stability against yellowing and humidity. These monomers are intermiscible, providing for precise adjustment of the refractive index from 1.30 to 1.60. Waveguides are formed photolithographically, with the liquid monomer mixture polymerizing upon illumination in the UV via either mask exposure or laser direct-writing. A wide range of rigid and flexible substrates can be used, including glass, quartz, oxidized silicon, glass-filled epoxy printed circuit board substrate, and flexible polyimide film. We discuss the use of these materials on chips and on multi-chip modules (MCMs), specifically in transceivers where we adaptively produced waveguides on vertical-cavity surface-emitting lasers (VCSELs) embedded in transmitter MCMs and on high- speed photodetector chips in receiver MCMs. Light coupling from and to chips is achieved by cutting 45 degree mirrors using excimer laser ablation. The fabrication of our polymeric structures directly on the modules provides for stability, ruggedness, and hermeticity in packaging.

  4. Three-Dimensional Integration Technology for Advanced Focal Planes and Integrated Circuits

    SciTech Connect

    Keast, Craig

    2007-02-28

    Over the last five years MIT Lincoln Laboratory (MIT-LL) has developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. Advanced focal plane arrays have been the first applications to exploit the benefits of this 3D integration technology because the massively parallel information flow present in 2D imaging arrays maps very nicely into a 3D computational structure as information flows from circuit-tier to circuit-tier in the z-direction. To date, the MIT-LL 3D integration technology has been used to fabricate four different focal planes including: a 2-tier 64 x 64 imager with fully parallel per-pixel A/D conversion; a 3-tier 640 x 480 imager consisting of an imaging tier, an A/D conversion tier, and a digital signal processing tier; a 2-tier 1024 x 1024 pixel, 4-side-abutable imaging modules for tiling large mosaic focal planes, and a 3-tier Geiger-mode avalanche photodiode (APD) 3-D LIDAR array, using a 30 volt APD tier, a 3.3 volt CMOS tier, and a 1.5 volt CMOS tier. Recently, the 3D integration technology has been made available to the circuit design research community through DARPA-sponsored Multiproject fabrication runs. The first Multiproject Run (3DL1) completed fabrication in early 2006 and included over 30 different circuit designs from 21 different research groups. 3D circuit concepts explored in this run included stacked memories, field programmable gate arrays (FPGAs), and mixed-signal circuits. The second Multiproject Run (3DM2) is currently in fabrication and includes particle detector readouts designed by Fermilab. This talk will provide a brief overview of MIT-LL's 3D-integration process, discuss some of the focal plane applications where the technology is being applied, and provide a summary of some of the Multiproject Run circuit results.

  5. Advances in the modeling of single electron transistors for the design of integrated circuit.

    PubMed

    Chi, Yaqing; Sui, Bingcai; Yi, Xun; Fang, Liang; Zhou, Hailiang

    2010-09-01

    Single electron transistor (SET) has become a promising candidate for the key device of logic circuit in the near future. The advances of recent 5 years in the modeling of SETs are reviewed for the simulation of SET/hybrid CMOS-SET integrated circuit. Three dominating SET models, Monte Carlo model, master equation model and macro model, are analyzed, tested and compared on their principles, characteristics, applicability and development trend. The Monte Carlo model is suitable for SET structure research and simulation of small scale SET circuit, while the analytical model based on combination with master equation and macro model is suitable to simulate the SET circuit at balanceable efficiency and accuracy.

  6. Thermionic integrated circuits

    SciTech Connect

    MacRoberts, M.; Brown, D.R.; Dooley, R.; Lemons, R.; Lynn, D.; McCormick, B.; Mombourquette, C.; Sinah, D.

    1986-01-01

    Thermionic integrated circuits combine vacuum-tube technology with integrated-circuit techniques to form integrated vacuum circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments.

  7. Polymer planar lightwave circuit based hybrid-integrated coherent receiver for advanced modulation signals

    NASA Astrophysics Data System (ADS)

    Wang, Jin; Han, Yang; Liang, Zhongcheng; Chen, Yongjin

    2012-11-01

    Applying coherent detection technique to advanced modulation formats makes it possible to electronically compensate the signal impairments. A key issue for a successful deployment of coherent detection technique is the availability of cost-efficient and compact integrated receivers, which are composed of an optical 90° hybrid mixer and four photodiodes (PDs). In this work, three different types of optical hybrids are fabricated with polymer planar lightwave circuit (PLC), and hybridly integrated with four vertical backside illuminated III-V PDs. Their performances, such as the insertion loss, the transmission imbalance, the polarization dependence and the phase deviation of 90° hybrid will be discussed.

  8. Photonic Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Merritt, Scott; Krainak, Michael

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  9. Linear integrated circuits

    NASA Astrophysics Data System (ADS)

    Young, T.

    This book is intended to be used as a textbook in a one-semester course at a variety of levels. Because of self-study features incorporated, it may also be used by practicing electronic engineers as a formal and thorough introduction to the subject. The distinction between linear and digital integrated circuits is discussed, taking into account digital and linear signal characteristics, linear and digital integrated circuit characteristics, the definitions for linear and digital circuits, applications of digital and linear integrated circuits, aspects of fabrication, packaging, and classification and numbering. Operational amplifiers are considered along with linear integrated circuit (LIC) power requirements and power supplies, voltage and current regulators, linear amplifiers, linear integrated circuit oscillators, wave-shaping circuits, active filters, DA and AD converters, demodulators, comparators, instrument amplifiers, current difference amplifiers, analog circuits and devices, and aspects of troubleshooting.

  10. Advances in gallium arsenide monolithic microwave integrated-circuit technology for space communications systems

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Connolly, D. J.

    1986-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. In this paper, current developments in GaAs MMIC technology are described, and the status and prospects of the technology are assessed.

  11. Advances in gallium arsenide monolithic microwave integrated-circuit technology for space communications systems

    NASA Astrophysics Data System (ADS)

    Bhasin, K. B.; Connolly, D. J.

    1986-10-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. In this paper, current developments in GaAs MMIC technology are described, and the status and prospects of the technology are assessed.

  12. Leveraging advanced data analytics, machine learning, and metrology models to enable critical dimension metrology solutions for advanced integrated circuit nodes

    NASA Astrophysics Data System (ADS)

    Rana, Narender; Zhang, Yunlin; Kagalwala, Taher; Bailey, Todd

    2014-10-01

    Integrated circuit (IC) technology is changing in multiple ways: 193i to extreme ultraviolet exposure, planar to nonplanar device architecture, from single exposure lithography to multiple exposure and directed self-assembly (DSA) patterning, and so on. Critical dimension (CD) control requirement is becoming stringent and more exhaustive: CD and process windows are shrinking, three-sigma CD control of <2 nm is required in complex geometries, and a metrology uncertainty of <0.2 nm is required to achieve the target CD control for advanced IC nodes (e.g., 14, 10, and 7 nm nodes). There are fundamental capability and accuracy limits in all the metrology techniques that are detrimental to the success of advanced IC nodes. Reference or physical CD metrology is provided by atomic force microscopy (CD-AFM) and TEM while workhorse metrology is provided by CD-SEM, scatterometry, and model-based infrared reflectrometry (MBIR). Precision alone is not sufficient for moving forward. No single technique is sufficient to ensure the required accuracy of patterning. The accuracy of CD-AFM is ˜1 nm and the precision in TEM is poor due to limited statistics. CD scanning electron microscopy (CD-SEM), scatterometry, and MBIR need to be calibrated by reference measurements for ensuring the accuracy of patterned CDs and patterning models. There is a dire need for a measurement with <0.5 nm accuracy and the industry currently does not have that capability with inline measurements. Being aware of the capability gaps for various metrology techniques, we have employed data processing techniques and predictive data analytics, along with patterning simulation and metrology models and data integration techniques to selected applications demonstrating the potential solution and practicality of such an approach to enhance CD metrology accuracy. Data from multiple metrology techniques have been analyzed in multiple ways to extract information with associated uncertainties and integrated to extract

  13. Monolithic microwave integrated circuits

    NASA Astrophysics Data System (ADS)

    Pucel, R. A.

    Monolithic microwave integrated circuits (MMICs), a new microwave technology which is expected to exert a profound influence on microwave circuit designs for future military systems as well as for the commercial and consumer markets, is discussed. The book contains an historical discussion followed by a comprehensive review presenting the current status in the field. The general topics of the volume are: design considerations, materials and processing considerations, monolithic circuit applications, and CAD, measurement, and packaging techniques. All phases of MMIC technology are covered, from design to testing.

  14. Integrated circuit reliability testing

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G. (Inventor); Sayah, Hoshyar R. (Inventor)

    1990-01-01

    A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

  15. Integrated circuit reliability testing

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G. (Inventor); Sayah, Hoshyar R. (Inventor)

    1988-01-01

    A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

  16. Bioluminescent bioreporter integrated circuit

    DOEpatents

    Simpson, Michael L.; Sayler, Gary S.; Paulus, Michael J.

    2000-01-01

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

  17. Pulse advancement and delay in an integrated-optical two-port ring-resonator circuit: direct experimental observations.

    PubMed

    Uranus, H P; Zhuang, L; Roeloffzen, C G H; Hoekstra, H J W M

    2007-09-01

    We report experimental observations of the negative-group-velocity (v(g)) phenomenon in an integrated-optical two-port ring-resonator circuit. We demonstrate that when the v(g) is negative, the (main) peak of output pulse appears earlier than the peak of a reference pulse, while for a positive v(g), the situation is the other way around. We observed that a pulse splitting phenomenon occurs in the neighborhood of the critical-coupling point. This pulse splitting limits the maximum achievable delay and advancement of a single device as well as facilitating a smooth transition from highly advanced to highly delayed pulse, and vice versa, across the critical-coupling point.

  18. Integrated Circuit Immunity

    NASA Technical Reports Server (NTRS)

    Sketoe, J. G.; Clark, Anthony

    2000-01-01

    This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

  19. Monolithic Optoelectronic Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Bhasin, Kul B.; Walters, Wayne; Gustafsen, Jerry; Bendett, Mark

    1990-01-01

    Monolithic optoelectronic integrated circuit (OEIC) receives single digitally modulated input light signal via optical fiber and converts it into 16-channel electrical output signal. Potentially useful in any system in which digital data must be transmitted serially at high rates, then decoded into and used in parallel format at destination. Applications include transmission and decoding of control signals to phase shifters in phased-array antennas and also communication of data between computers and peripheral equipment in local-area networks.

  20. ELECTRONIC INTEGRATING CIRCUIT

    DOEpatents

    Englemann, R.H.

    1963-08-20

    An electronic integrating circuit using a transistor with a capacitor connected between the emitter and collector through which the capacitor discharges at a rate proportional to the input current at the base is described. Means are provided for biasing the base with an operating bias and for applying a voltage pulse to the capacitor for charging to an initial voltage. A current dividing diode is connected between the base and emitter of the transistor, and signal input terminal means are coupled to the juncture of the capacitor and emitter and to the base of the transistor. At the end of the integration period, the residual voltage on said capacitor is less by an amount proportional to the integral of the input signal. Either continuous or intermittent periods of integration are provided. (AEC)

  1. Digital integrated circuits

    NASA Astrophysics Data System (ADS)

    Polasek, P.; Halamik, J.

    1984-05-01

    The term semicustom designed integrated circuits denotes integrated circuits of an all purpose character in which the production of chips is completed by using one to three custom design stencil type exposure masks. This involves in most cases interconnecting masks that are used to devise the circuit function desired by the customer. Silicon plates with an all purpose gate matrix are produced up to the interconnection level and can be kept at this phase in storage, after which a customer's specific demands can be met very expediently. All purpose logic fields containing 200 logic gates on a chip and an all purpose chip to be expanded to 1,000 logic gates are discussed. The technology facilitates the devising of fast gates with a delay of approximately 5 ns and power dissipation of 1 mW. In assembly it will be possible to make use of the entire assortment of the currently used casings with 16, 18, 20, 24, 28 and 40 outlets. In addition to the development of the mentioned technology, a general methodology for design of the mentioned gate fields is currently under way.

  2. Integrated circuit cell library

    NASA Technical Reports Server (NTRS)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  3. Development of 3D integrated circuits for HEP

    SciTech Connect

    Yarema, R.; /Fermilab

    2006-09-01

    Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented.

  4. Integrated Circuit Computer Analysis.

    DTIC Science & Technology

    information on this topic. The most important findings were the method used to identify combinational circuits ( Quine - McCluskey algorithm) and a clearly...defined set of limits on the problem of identifying sequential circuits. Since the Quine - McCluskey algorithm works only for combinational circuits, an

  5. Potential for integrated optical circuits in advanced aircraft with fiber optic control and monitoring systems

    NASA Technical Reports Server (NTRS)

    Baumbick, Robert

    1991-01-01

    The current Fiber Optic Control System Integration (FOCSI) program is reviewed and the potential role of IOCs in FOCSI applications is described. The program is intended for building, environmentally testing, and demonstrating operation in piggyback flight tests (no active control with optical sensors) of a representative sensor system for propulsion and flight control. The optical sensor systems are to be designed to fit alongside the bill-of-materials sensors for comparison. The sensors are to be connected to electrooptic architecture cards which will contain the optical sources and detectors to recover and process the modulated optical signals. The FOCSI program is to collect data on the behavior of passive optical sensor systems in a flight environment and provide valuable information on installation amd maintenance problems for this technology, as well as component survivability (light sources, connectors, optical fibers, etc.).

  6. Recent Advances In Cryogenic Monolithic Millimeter-wave Integrated Circuit (MMIC) Low Noise Amplifiers For Astrophysical Observations

    NASA Astrophysics Data System (ADS)

    Samoska, Lorene; Church, S.; Cleary, K.; Gaier, T.; Gawande, R.; Kangaslahti, P.; Lawrence, C.; Readhead, A.; Reeves, R.; Seiffert, M.; Sieth, M.; Varonen, M.; Voll, P.

    2012-05-01

    In this work, we discuss advances in high electron mobility transistor (HEMT) low noise amplifier (LNA) monolithic millimeter-wave integrated circuits (MMICs) for use as front end amplifiers in ultra-low noise receivers. Applications include focal plane arrays for studying the polarization of the cosmic microwave background radiation and foreground separation, receiver arrays for molecular spectroscopy, and high redshift CO surveys for probing the epoch of reionization. Recent results and a summary of best indium phosphide (InP) low noise amplifier data will be presented. Cryogenic MMIC LNAs using state-of-the-art InP technology have achieved record performance, and have advantages over other detectors in the 30-300 GHz range. InP MMIC LNAs operate at room temperature and may achieve near-optimum performance at 20K, a temperature readily achieved with modern cryo-coolers. In addition, wide-bandwidth LNAs are suitable for heterodyne applications as well as direct detector applications. Recent results include Ka-band MMICs with 15K noise temperature performance, and Q-Band MMICs with on-wafer measured cryogenic noise of 12K at 38 GHz. In addition, W-Band amplifiers with 25K noise temperature at 95 GHz will be presented, as well as wide-band LNAs with noise temperature below 45K up to 116 GHz. At higher frequencies, we will discuss progress on MMIC LNAs and receiver modules in G-Band (140-220 GHz), where our group has achieved less than 60K receiver noise temperature at 166 GHz. We will address extending the high performance of these MMIC LNAs to even higher frequencies for spectroscopic surveys, and make projections on future performance given current trends. These MMIC amplifiers can play a key role in future ground-based and space-based instruments for astrophysical observations.

  7. Microfluidic photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Cho, Sung Hwan; Godin, Jessica; Chen, Chun Hao; Tsai, Frank S.; Lo, Yu-Hwa

    2008-11-01

    We report on the development of an inexpensive, portable lab-on-a-chip flow cytometer system in which microfluidics, photonics, and acoustics are integrated together to work synergistically. The system relies on fluid-filled twodimensional on-chip photonic components such as lenses, apertures, and slab waveguides to allow for illumination laser beam shaping, light scattering and fluorescence signal detection. Both scattered and fluorescent lights are detected by photodetectors after being collected and guided by the on-chip optics components (e.g. lenses and waveguides). The detected light signal is imported and amplified in real time and triggers the piezoelectric actuator so that the targeted samples are directed into desired reservoir for subsequent advanced analysis. The real-time, closed-loop control system is developed with field-programmable-gate-array (FPGA) implementation. The system enables high-throughput (1- 10kHz operation), high reliability and low-powered (<1mW) fluorescence activated cell sorting (FACS) on a chip. The microfabricated flow cytometer can potentially be used as a portable, inexpensive point-of-care device in resource poor environments.

  8. Microwave integrated circuits for space applications

    NASA Technical Reports Server (NTRS)

    Leonard, Regis F.; Romanofsky, Robert R.

    1991-01-01

    Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

  9. Variational integrators for electric circuits

    SciTech Connect

    Ober-Blöbaum, Sina; Tao, Molei; Cheng, Mulin; Owhadi, Houman; Marsden, Jerrold E.

    2013-06-01

    In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator.

  10. Displacement Damage in Bipolar Linear Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Rax, B. G.; Johnston, A. H.; Miyahira, T.

    2000-01-01

    Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

  11. Solution methods for very highly integrated circuits.

    SciTech Connect

    Nong, Ryan; Thornquist, Heidi K.; Chen, Yao; Mei, Ting; Santarelli, Keith R.; Tuminaro, Raymond Stephen

    2010-12-01

    While advances in manufacturing enable the fabrication of integrated circuits containing tens-to-hundreds of millions of devices, the time-sensitive modeling and simulation necessary to design these circuits poses a significant computational challenge. This is especially true for mixed-signal integrated circuits where detailed performance analyses are necessary for the individual analog/digital circuit components as well as the full system. When the integrated circuit has millions of devices, performing a full system simulation is practically infeasible using currently available Electrical Design Automation (EDA) tools. The principal reason for this is the time required for the nonlinear solver to compute the solutions of large linearized systems during the simulation of these circuits. The research presented in this report aims to address the computational difficulties introduced by these large linearized systems by using Model Order Reduction (MOR) to (i) generate specialized preconditioners that accelerate the computation of the linear system solution and (ii) reduce the overall dynamical system size. MOR techniques attempt to produce macromodels that capture the desired input-output behavior of larger dynamical systems and enable substantial speedups in simulation time. Several MOR techniques that have been developed under the LDRD on 'Solution Methods for Very Highly Integrated Circuits' will be presented in this report. Among those presented are techniques for linear time-invariant dynamical systems that either extend current approaches or improve the time-domain performance of the reduced model using novel error bounds and a new approach for linear time-varying dynamical systems that guarantees dimension reduction, which has not been proven before. Progress on preconditioning power grid systems using multi-grid techniques will be presented as well as a framework for delivering MOR techniques to the user community using Trilinos and the Xyce circuit simulator

  12. Vertically Integrated Circuits at Fermilab

    SciTech Connect

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2010-01-01

    The exploration of vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning, and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. For the first time, Fermilab has organized a 3D MPW run, to which more than 25 different designs have been submitted by the consortium.

  13. Vertically Integrated Circuits at Fermilab

    SciTech Connect

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  14. MOS integrated circuit fault modeling

    NASA Technical Reports Server (NTRS)

    Sievers, M.

    1985-01-01

    Three digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.

  15. Development of CMOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  16. Delay locked loop integrated circuit.

    SciTech Connect

    Brocato, Robert Wesley

    2007-10-01

    This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.

  17. Enhancements to - and Submillimetre - Integrated Circuit Receivers.

    NASA Astrophysics Data System (ADS)

    Veidt, Bruce George

    1995-01-01

    An important area of radio astronomy instrumentation is the development of sensitive receivers at millimetre - and submillimetre-wavelengths. Over the last decade, there has been steady progress in advancing the technology from using receivers based on mechanically machined waveguides and horn antennas to transmission lines and antennas fabricated using integrated circuit techniques. The motivation has been to simplify the fabrication of the receivers through the use of photolithography and etching. It is hoped that this will eventually lead to the development of focal plane arrays, which have many elements placed side-by-side forming a radio camera. The first part of this thesis addresses one of the problems with the integrated circuit technology, namely the fixed nature of the circuits, by examining one type of electrically-adjustable tuning. In those experiments, the bias voltage was modulated across the active device so as to change its tuning. Unfortunately the tuning effect was severely limited by the electrical nonlinearity of the device. Another part of this thesis builds upon the integrated nature of modern receivers by adding what, up until now, has been an external component: the Josephson effect suppression electromagnet. This technique will allow the receiving elements to be much simpler and smaller than would otherwise be the case. Finally, the last part of this thesis examines another method of constructing antennas and transmission lines using integrated circuit techniques. This work shows the feasibility of integrating a waveguide fabricated with integrated circuit technology with a diagonal horn antenna. This technique will provide another option for receiver designers.

  18. Integrated circuits, and design and manufacture thereof

    DOEpatents

    Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

    2006-04-18

    A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

  19. Integrated acoustooptic circuits and applications.

    PubMed

    Tsai, C S

    1992-01-01

    The recent development of titanium-indiffusion proton-exchange (TIPE) microlenses and lens arrays has made possible the construction of a variety of single- and multichannel integrated acoustooptic (AO) and acoustooptic-electrooptic (EO) circuits in LiNbO(3) channel-planar waveguides 0.1x1.0x2.0 cm(3) in size. These hybrid AO and AO-EO circuits can be fabricated through compatible and well-established technologies. The most recent realization of ion-milled microlenses and lens arrays together with the recent development of gigahertz AO Bragg modulators and EO Bragg modulator arrays have also paved the way for construction of similar but monolithic AO and AO-EO GaAs/GaAlAs waveguides of comparable size. Both types of integrated AO and AO-EO circuits suggest versatile applications in communications signal processing, and computing. Efficient and simultaneous excitation of the channel waveguide array using an ion-milled planar microlens array has facilitated the demonstration of some of these applications.

  20. Parallelism in integrated fluidic circuits

    NASA Astrophysics Data System (ADS)

    Bousse, Luc J.; Kopf-Sill, Anne R.; Parce, J. W.

    1998-04-01

    Many research groups around the world are working on integrated microfluidics. The goal of these projects is to automate and integrate the handling of liquid samples and reagents for measurement and assay procedures in chemistry and biology. Ultimately, it is hoped that this will lead to a revolution in chemical and biological procedures similar to that caused in electronics by the invention of the integrated circuit. The optimal size scale of channels for liquid flow is determined by basic constraints to be somewhere between 10 and 100 micrometers . In larger channels, mixing by diffusion takes too long; in smaller channels, the number of molecules present is so low it makes detection difficult. At Caliper, we are making fluidic systems in glass chips with channels in this size range, based on electroosmotic flow, and fluorescence detection. One application of this technology is rapid assays for drug screening, such as enzyme assays and binding assays. A further challenge in this area is to perform multiple functions on a chip in parallel, without a large increase in the number of inputs and outputs. A first step in this direction is a fluidic serial-to-parallel converter. Fluidic circuits will be shown with the ability to distribute an incoming serial sample stream to multiple parallel channels.

  1. Removing Bonded Integrated Circuits From Boards

    NASA Technical Reports Server (NTRS)

    Rice, John T.

    1989-01-01

    Small resistance heater makes it easier, faster, and cheaper to remove integrated circuit from hybrid-circuit board, package, or other substrate for rework. Heater, located directly in polymeric bond interface or on substrate under integrated-circuit chip, energized when necessary to remove chip. Heat generated softens adhesive or solder that bonds chip to substrate. Chip then lifted easily from substrate.

  2. Advanced Imaging of Elementary Circuits

    ERIC Educational Resources Information Center

    Baird, William H.; Richards, Caleb; Godbole, Pranav

    2012-01-01

    Students commonly find the second semester of introductory physics to be more challenging than the first, probably due to the mechanical intuition we acquire just by moving around. For most students, there is no similar comfort with electricity or magnetism. In an effort to combat this confusion, we decided to examine simple electric circuits with…

  3. Graphene radio frequency receiver integrated circuit.

    PubMed

    Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

    2014-01-01

    Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

  4. Scaling of graphene integrated circuits

    NASA Astrophysics Data System (ADS)

    Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A.; Pop, Eric; Sordan, Roman

    2015-04-01

    The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing. Electronic supplementary information (ESI) available: Discussions on the cutoff frequency fT, the maximum frequency of oscillation fmax, and the intrinsic gate delay CV/I. See DOI: 10.1039/c5nr01126d

  5. Wafer-scale graphene integrated circuit.

    PubMed

    Lin, Yu-Ming; Valdes-Garcia, Alberto; Han, Shu-Jen; Farmer, Damon B; Meric, Inanc; Sun, Yanning; Wu, Yanqing; Dimitrakopoulos, Christos; Grill, Alfred; Avouris, Phaedon; Jenkins, Keith A

    2011-06-10

    A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

  6. Analog VLSI neural network integrated circuits

    NASA Technical Reports Server (NTRS)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  7. Integrated-Circuit Pseudorandom-Number Generator

    NASA Technical Reports Server (NTRS)

    Steelman, James E.; Beasley, Jeff; Aragon, Michael; Ramirez, Francisco; Summers, Kenneth L.; Knoebel, Arthur

    1992-01-01

    Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

  8. Reusable vibration resistant integrated circuit mounting socket

    DOEpatents

    Evans, Craig N.

    1995-01-01

    This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and holds it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

  9. Reusable vibration resistant integrated circuit mounting socket

    SciTech Connect

    Evans, C.N.

    1993-12-31

    This invention discloses a novel form of socket for integrated circuits to be mounted on printed circuit boards. The socket uses a novel contact which is fabricated out of a bimetallic strip with a shape which makes the end of the strip move laterally as temperature changes. The end of the strip forms a barb which digs into an integrated circuit lead at normal temperatures and hold it firmly in the contact, preventing loosening and open circuits from vibration. By cooling the contact containing the bimetallic strip the barb end can be made to release so that the integrated circuit lead can be removed from the socket without damage either to the lead or to the socket components.

  10. Reverse engineering of integrated circuits

    DOEpatents

    Chisholm, Gregory H.; Eckmann, Steven T.; Lain, Christopher M.; Veroff, Robert L.

    2003-01-01

    Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

  11. Circulators for microwave and millimeter-wave integrated circuits

    NASA Astrophysics Data System (ADS)

    Schloemann, Ernst F.

    1988-02-01

    The requirements for circulators for use in combination with microwave and millimeter-wave integrated circuits are reviewed, with special emphasis on modules for phased-array antennas. Recent advances in broadbanding and in miniaturization are summarized. Novel types of circulators that are fabricated by attaching a ferrite disc and a suitable coupling structure to the surface of a dielectric or semiconductor substrate ('quasi-monolithic' integration) are described. Methods for achieving complete monolithic integration are also discussed.

  12. Research in computer simulation of integrated circuits

    NASA Astrophysics Data System (ADS)

    Newton, A. R.; Pdederson, D. O.

    1983-07-01

    The performance of the new LSI simulator CLASSIE is evaluated on several circuits with a few hundred to over one thousand semiconductor devices. A more accurate run time prediction formula has been found to be appropriate for circuit simulators. The design decisions for optimal performance under the constraints of the hardware (CRAY-1) are presented. Vector computers have an increased potential for fast, accurate simulation at the transistor level of Large-Scale-Integrated Circuits. Design considerations for a new circuit simulator are developed based on the specifics of the vector computer architecture and of LSI circuits. The simulation of Large-Scale-Integrated (LSI) circuits requires very long run time on conventional circuit analysis programs such as SPICE2 and super-mini computers. A new simulator for LSI circuits, CLASSIE, which takes advantage of circuit hierarchy and repetitiveness, and array processors capable of high-speed floating-point computation are a promising combination. While a large number of powerful design verfication tools have been developed for IC design at the transistor and logic gate levels, there are very few silicon-oriented tools for architectural design and evaluation.

  13. Chain Of Test Contacts For Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Lieneweg, Udo

    1989-01-01

    Test structure forms chain of "cross" contacts fabricated together with large-scale integrated circuits. If necessary, number of such chains incorporated at suitable locations in integrated-circuit wafer for determination of fabrication yield of contacts. In new structure, resistances of individual contacts determined: In addition to making it possible to identify local defects, enables generation of statistical distributions of contact resistances for prediction of "parametric" contact yield of fabrication process.

  14. Integrated Circuit Stellar Magnitude Simulator

    ERIC Educational Resources Information Center

    Blackburn, James A.

    1978-01-01

    Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

  15. Handbook of microwave integrated circuits

    NASA Astrophysics Data System (ADS)

    Hoffmann, Reinmut K.

    The design and operation of ICs for use in the 0.5-20-GHz range are described in an introductory and reference work for industrial engineers. Chapters are devoted to an overview of microwave IC (MIC) technology, general stripline characteristics, microwave transmission line (MTL) parameters for microstrips with isotropic dielectric substrates, higher-order modes on a microstrip, the effects of metallic enclosure on MTL transmission parameters, losses in microstrips, the measurement of MTL parameters, and MTLs on anisotropic dielectric substrates. Consideration is given to coupled microstrips on dielectric substrates, microstrip discontinuities, radiation from microstrip circuits, MTL variations, coplanar MTLs, slotlines, and spurious modes in MTL circuits. Diagrams, drawings, graphs, and a glossary of symbols are provided.

  16. Progress in organic integrated circuit manufacture

    NASA Astrophysics Data System (ADS)

    Taylor, D. Martin

    2016-02-01

    This review article focuses on the development of processes for the manufacture of organic electronic circuits. Beginning with the first report of an organic transistor it highlights the key developments leading to the successful manufacture of microprocessors and other complex circuits incorporating organic transistors. Both batch processing (based on silicon integrated circuit technology) as well as mass-printing, roll-to-roll (R2R) approaches are discussed. Currently, the best circuit performances are achieved using batch processing. It is suggested that an emerging, large mass-market for electronic tags may dictate that R2R manufacture will likely be required to meet the high throughput rates needed. However, significant improvements in resolution and registration are necessary to achieve increased circuit operating speeds.

  17. Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

    NASA Technical Reports Server (NTRS)

    1975-01-01

    Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

  18. Polysilicon photoconductor for integrated circuits

    DOEpatents

    Hammond, Robert B.; Bowman, Douglas R.

    1990-01-01

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

  19. Polysilicon photoconductor for integrated circuits

    DOEpatents

    Hammond, R.B.; Bowman, D.R.

    1989-04-11

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

  20. Polysilicon photoconductor for integrated circuits

    DOEpatents

    Hammond, Robert B.; Bowman, Douglas R.

    1989-01-01

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response.

  1. Maximum Temperature Detection System for Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Frankiewicz, Maciej; Kos, Andrzej

    2015-03-01

    The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

  2. Layout techniques for integrated circuits

    SciTech Connect

    Tsay, C.Y.

    1986-01-01

    Several techniques are presented for solving circuit-layout problems. In particular, a channel-placement algorithm is first introduced to reduce the channel density (d) so that a channel router can complete the routing requirements in fewer tracks. A 4-layer channel-routing model is then formulated so that a general channel routing problem (CRP) with cyclic conflicts and long critical paths can be completed with d/2. Finally, the 4-layer, 2-dimensional switchbox routing problem needed to enhance the channel routing in general circuit layout is investigated from the graph-theoretical viewpoint. The channel-placement technique consists of two phases. Using the principle of decomposition, the initial placement phase effectively reduces the complexity of the problem and, therefore, improves the efficiency of the second phase, which is called the iterative improvement placement. The main feature of this phase is its hill-climbing ability to avoid being trapped at local minima. The combination of these two phases leads to an efficient technique for standard cell placement. To utilize multi-layer technology, a new 4-layer channel routing model is introduced to minimize the channel width of more-generalized CRP's. The 2-dimensional switchbox routing problem is transformed to an equivalent graph-theoretical problem.

  3. Package for integrated optic circuit and method

    DOEpatents

    Kravitz, S.H.; Hadley, G.R.; Warren, M.E.; Carson, R.F.; Armendariz, M.G.

    1998-08-04

    A structure and method are disclosed for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package. 6 figs.

  4. Package for integrated optic circuit and method

    DOEpatents

    Kravitz, Stanley H.; Hadley, G. Ronald; Warren, Mial E.; Carson, Richard F.; Armendariz, Marcelino G.

    1998-01-01

    A structure and method for packaging an integrated optic circuit. The package comprises a first wall having a plurality of microlenses formed therein to establish channels of optical communication with an integrated optic circuit within the package. A first registration pattern is provided on an inside surface of one of the walls of the package for alignment and attachment of the integrated optic circuit. The package in one embodiment may further comprise a fiber holder for aligning and attaching a plurality of optical fibers to the package and extending the channels of optical communication to the fibers outside the package. In another embodiment, a fiber holder may be used to hold the fibers and align the fibers to the package. The fiber holder may be detachably connected to the package.

  5. Millimeter And Submillimeter-Wave Integrated Circuits On Quartz

    NASA Technical Reports Server (NTRS)

    Mehdi, Imran; Mazed, Mohammad; Siegel, Peter; Smith, R. Peter

    1995-01-01

    Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

  6. Laboratory experiments in integrated circuit fabrication

    NASA Technical Reports Server (NTRS)

    Jenkins, Thomas J.; Kolesar, Edward S.

    1993-01-01

    The objectives of the experiment are fourfold: to provide practical experience implementing the fundamental processes and technology associated with the science and art of integrated circuit (IC) fabrication; to afford the opportunity for the student to apply the theory associated with IC fabrication and semiconductor device operation; to motivate the student to exercise engineering decisions associated with fabricating integrated circuits; and to complement the theory of n-channel MOS and diffused devices that are presented in the classroom by actually fabricating and testing them. Therefore, a balance between theory and practice can be realized in the education of young engineers, whose education is often criticized as lacking sufficient design and practical content.

  7. Test Structures For Bumpy Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.; Sayah, Hoshyar R.

    1989-01-01

    Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

  8. Microwave integrated circuit for Josephson voltage standards

    NASA Technical Reports Server (NTRS)

    Holdeman, L. B.; Toots, J.; Chang, C. C. (Inventor)

    1980-01-01

    A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

  9. Package Holds Five Monolithic Microwave Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

    1996-01-01

    Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

  10. Integrated Circuits in the Introductory Electronics Laboratory

    ERIC Educational Resources Information Center

    English, Thomas C.; Lind, David A.

    1973-01-01

    Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

  11. Designing Test Chips for Custom Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buehler, M. G.; Griswold, T. W.; Pina, C. A.; Timoc, C. C.

    1985-01-01

    Collection of design and testing procedures partly automates development of built-in test chips for CMOS integrated circuits. Testchip methodology intended especially for users of custom integratedcircuit wafers. Test-Chip Designs and Testing Procedures (including datareduction procedures) generated automatically by computer from programed design and testing rules and from information supplied by user.

  12. Integrated Circuit Failure Analysis Hypertext Help System

    SciTech Connect

    Henderson, Christopher L.; Barton, Daniel L.; Campbell, Ann N.; Cole, Edward I; Mikawa, Russell E.; Peterson, Kenneth A.; Rife, James L.; Soden, Jerry M.

    1995-02-23

    This software assists a failure analyst performing failure analysis on integrated circuits. The software can also be used to train inexperienced failure analysts. The software also provides a method for storing information and making it easily available to experienced failure analysts.

  13. Heat-Transfer Microstructures for Integrated Circuits

    DTIC Science & Technology

    2007-11-02

    fatigue failure curves for silicon mounted on molybdenum or copper (from Lang et a[ [75]). Microcapillary thermal interface concept. a) Tunnels...Coolant Figure of Merit Complementary Metal-Oxide-Semiconductor Emitter- Coupled Logic Integrated Circuit Metal-Oxide-Semiconductor Median Time to...nominally independent devices; for example, electromagnetic coupling (crosstalk) between adjacent long, parallel wires on an IC, especially when a ground

  14. Bioluminescent bioreporter integrated circuit detection methods

    SciTech Connect

    Simpson, Michael L.; Paulus, Michael J.; Sayler, Gary S.; Applegate, Bruce M.; Ripp, Steven A.

    2005-06-14

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for detection of particular analytes, including ammonia and estrogen compounds.

  15. Optoelectronic Integrated Circuits For Neural Networks

    NASA Technical Reports Server (NTRS)

    Psaltis, D.; Katz, J.; Kim, Jae-Hoon; Lin, S. H.; Nouhi, A.

    1990-01-01

    Many threshold devices placed on single substrate. Integrated circuits containing optoelectronic threshold elements developed for use as planar arrays of artificial neurons in research on neural-network computers. Mounted with volume holograms recorded in photorefractive crystals serving as dense arrays of variable interconnections between neurons.

  16. All-ion-implantation process for integrated circuits

    NASA Technical Reports Server (NTRS)

    Woo, D. S.

    1979-01-01

    Simpler than diffusion fabrication, ion bombardment produces complementary-metal-oxide-semiconductor / silicon-on-sapphire (CMOS/SOS) circuits that are one-third faster. Ion implantation simplifies the integrated circuit fabrication procedure and produces circuits with uniform characteristics.

  17. Integrated-Circuit Active Digital Filter

    NASA Technical Reports Server (NTRS)

    Nathan, R.

    1986-01-01

    Pipeline architecture with parallel multipliers and adders speeds calculation of weighted sums. Picture-element values and partial sums flow through delay-adder modules. After each cycle or time unit of calculation, each value in filter moves one position right. Digital integrated-circuit chips with pipeline architecture rapidly move 35 X 35 two-dimensional convolutions. Need for such circuits in image enhancement, data filtering, correlation, pattern extraction, and synthetic-aperture-radar image processing: all require repeated calculations of weighted sums of values from images or two-dimensional arrays of data.

  18. Applying analog integrated circuits for HERO protection

    NASA Technical Reports Server (NTRS)

    Willis, Kenneth E.; Blachowski, Thomas J.

    1994-01-01

    One of the most efficient methods for protecting electro-explosive devices (EED's) from HERO and ESD is to shield the EED in a conducting shell (Faraday cage). Electrical energy is transferred to the bridge by means of a magnetic coupling which passes through a portion of the conducting shell that is made from a magnetically permeable but electrically conducting material. This technique was perfected by ML Aviation, a U.K. company, in the early 80's, and was called a Radio Frequency Attenuation Connector (RFAC). It is now in wide use in the U.K. Previously, the disadvantage of RFAC over more conventional methods was its relatively high cost, largely driven by a thick film hybrid circuit used to switch the primary of the transformer. Recently, through a licensing agreement, this technology has been transferred to the U.S. and significant cost reductions and performance improvements have been achieved by the introduction of analog integrated circuits. An integrated circuit performs the following functions: (1) Chops the DC input to a signal suitable for driving the primary of the transformer; (2) Verifies the input voltage is above a threshold; (3) Verifies the input voltage is valid for a pre set time before enabling the device; (4) Provides thermal protection of the circuit; and (5) Provides an external input for independent logic level enabling of the power transfer mechanism. This paper describes the new RFAC product and its applications.

  19. Photonic circuits integrated with CMOS compatible photodetectors

    NASA Astrophysics Data System (ADS)

    Cristea, Dana; Craciunoiu, F.; Modreanu, M.; Caldararu, M.; Cernica, I.

    2001-06-01

    This paper presents the integration of photodetectors and photonic circuits (waveguides and interferometers, coupling elements and chemo-optical transducing layer) on one silicon chip. Different materials: silicon, doped or undoped silica, SiO xN y, polymers, and different technologies: LPCVD, APCVD, sol-gel, spinning, micromachining have been used to realize the photonic and micromechanical components and the transducers. Also, MOS compatible processes have been used for optoelectronic circuits. The attention was focused on the matching of all the involved technologies, to allow the monolithic integration of all components, and also on the design and fabrication of special structures of photodetectors. Two types of high responsivity photodetectors, a photo-FET and a bipolar NPN phototransistor, with modified structures that allow the optical coupling to the waveguides have been designed and experimented. An original 3-D model was developed for the system: opto-FET-coupler-waveguide. A test circuit for sensor applications was experimented. All the components of the test circuits, photodetectors, waveguides, couplers, were obtained using CMOS-compatible processes. The aim of our research activity was to obtain microsensors with optical read-out.

  20. Integrated Circuit Radar And Radiometric Sensors

    NASA Astrophysics Data System (ADS)

    Seashore, C. R.

    1985-10-01

    The use of integrated circuit techniques for millimeter wave transducers has now moved from a research curiosity to an engineering discipline. Microstrip is the preferred transmission media to demonstrate a wide variety of RF component functions. For applications involving precision weapon systems, a soft substrate is preferred since it provides lower cost, improved survivability, and functional versatility when compared with the traditional hard candidates such as quartz. The MESFET is rapidly emerging as a key building block for monolithic supercomponents up to a frequency of approximately 40 GHz. Both planar and conformal antennas are being developed again based on a soft substrate with photolithographic processing. The marriage of planar integrated circuit transceivers with thin, planar antennas is providing a new generation of low cost, producible and miniature millimeter wave transducers for demanding systems requirements.

  1. Development of beam lead RF integrated circuits

    NASA Technical Reports Server (NTRS)

    Kline, A. J.; Kermode, A. W.

    1975-01-01

    This paper describes the design and development of a set of multifunction VHF/UHF integrated circuits aimed at providing a major improvement in spacecraft radio reliability through low stress operation and the processing of these circuits in beam-lead form. The methods evolved for the high frequency characterization of the devices are discussed together with the design of suitable test fixtures. Typical test results and the distribution of test parameters are presented. A unique carrier for beam-lead devices is described, and the need for such a device is discussed. The application of the carrier to device screening, burn-in and drift measurements is discussed together with the incentives for providing these capabilities. An overview of the integration of the devices into the spacecraft radio is given and candidate assembly processes are discussed. The technology impact of this approach upon future spacecraft radio systems is qualitatively examined.

  2. Viewing Integrated-Circuit Interconnections By SEM

    NASA Technical Reports Server (NTRS)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  3. Progress in radiation immune thermionic integrated circuits

    SciTech Connect

    Lynn, D.K.; McCormick, J.B.

    1985-08-01

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

  4. Distributed Amplifier Monolithic Microwave Integrated Circuit (MMIC) Design

    DTIC Science & Technology

    2012-10-01

    Distributed Amplifier Monolithic Microwave Integrated Circuit (MMIC) Design by John E. Penn ARL-TR-6237 October 2012...Distributed Amplifier Monolithic Microwave Integrated Circuit (MMIC) Design John E. Penn Sensors and Electron Devices Directorate, ARL...TITLE AND SUBTITLE Distributed Amplifier Monolithic Microwave Integrated Circuit (MMIC) Design 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c

  5. Power system with an integrated lubrication circuit

    SciTech Connect

    Hoff, Brian D.; Akasam, Sivaprasad; Algrain, Marcelo C.; Johnson, Kris W.; Lane, William H.

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  6. Silicon photonic devices for optoelectronic integrated circuits

    NASA Astrophysics Data System (ADS)

    Tien, Ming-Chun

    Electronic and photonic integrated circuits use optics to overcome bottlenecks of microelectronics in bandwidth and power consumption. Silicon photonic devices such as optical modulators, filters, switches, and photodetectors have being developed for integration with electronics based on existing complementary metal-oxide-semiconductor (CMOS) circuits. An important building block of photonic devices is the optical microresonator. On-chip whispering-gallery-mode optical resonators such as microdisks, microtoroids, and microrings have very small footprint, and thus are suitable for large scale integration. Micro-electro-mechanical system (MEMS) technology enables dynamic control and tuning of optical functions. In this dissertation, microring resonators with tunable power coupling ratio using MEMS electrostatic actuators are demonstrated. The fabrication is compatible with CMOS. By changing the physical gap spacing between the waveguide coupler and the microring, the quality factor of the microring can be tuned from 16,300 to 88,400. Moreover, we have demonstrated optical switches and tunable optical add-drop filters with an optical bandwidth of 10 GHz and an extinction ratio of 20 dB. Potentially, electronic control circuits can also be integrated. To realize photonic integrated circuits on silicon, electrically-pumped silicon lasers are desirable. However, because of the indirect bandgap, silicon is a poor material for light emission compared with direct-bandgap III-V compound semiconductors. Heterogeneous integration of III-V semiconductor lasers on silicon is an alternative to provide on-chip light sources. Using a room-temperature, post-CMOS optofluidic assembly technique, we have experimentally demonstrated an InGaAsP microdisk laser integrated with silicon waveguides. Pre-fabricated InGaAsP microdisk lasers were fluidically assembled and aligned to the silicon waveguides on silicon-on-insulator (SOI) with lithographic alignment accuracy. The assembled

  7. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  8. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    NASA Technical Reports Server (NTRS)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMICs to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMICs is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  9. Vacuum die attach for integrated circuits

    DOEpatents

    Schmitt, E.H.; Tuckerman, D.B.

    1991-09-10

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

  10. Vacuum die attach for integrated circuits

    DOEpatents

    Schmitt, Edward H.; Tuckerman, David B.

    1991-01-01

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required.

  11. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    SciTech Connect

    Clark, Lawrence T.; McIver, III, John K.

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  12. An integrator circuit in cerebellar cortex.

    PubMed

    Maex, Reinoud; Steuber, Volker

    2013-09-01

    The brain builds dynamic models of the body and the outside world to predict the consequences of actions and stimuli. A well-known example is the oculomotor integrator, which anticipates the position-dependent elasticity forces acting on the eye ball by mathematically integrating over time oculomotor velocity commands. Many models of neural integration have been proposed, based on feedback excitation, lateral inhibition or intrinsic neuronal nonlinearities. We report here that a computational model of the cerebellar cortex, a structure thought to implement dynamic models, reveals a hitherto unrecognized integrator circuit. In this model, comprising Purkinje cells, molecular layer interneurons and parallel fibres, Purkinje cells were able to generate responses lasting more than 10 s, to which both neuronal and network mechanisms contributed. Activation of the somatic fast sodium current by subthreshold voltage fluctuations was able to maintain pulse-evoked graded persistent activity, whereas lateral inhibition among Purkinje cells via recurrent axon collaterals further prolonged the responses to step and sine wave stimulation. The responses of Purkinje cells decayed with a time-constant whose value depended on their baseline spike rate, with integration vanishing at low (< 1 per s) and high rates (> 30 per s). The model predicts that the apparently fast circuit of the cerebellar cortex may control the timing of slow processes without having to rely on sensory feedback. Thus, the cerebellar cortex may contain an adaptive temporal integrator, with the sensitivity of integration to the baseline spike rate offering a potential mechanism of plasticity of the response time-constant.

  13. Integrated circuit tester using interferometric imaging

    SciTech Connect

    Donaldson, W.R.; Michaels, E.M.R.; Akowuah, K.

    1997-04-01

    An interferometric imaging technique can provide time-resolved diagnostics of semiconductor integrated circuits. The semiconductor device is placed in one arm of an interferometer and illuminated with a picosecond pulse from a sub-bandgap infrared laser. As the laser passes through the semiconductor, it samples local variations in the index of refraction. These variations are caused by a number of physical phenomena including dopants in the material such as those used to form device structures, heating due to the flow of electrical currents, and changes in carrier concentration due to injection. These variations have both static and dynamic components. The dynamic components are associated with the normal device operation and are the most interesting. To separate the components, the device is first imaged in a quiescent state, and then a second image is taken after the device enters a known voltage state. Differences between the two images determine where the local index of refraction has changed and by how much. A third image taken with the reference arm of the interferometer blocked, allows device structures to be associated with particular changes in the index of refraction. Activation of the voltage state is synchronized with the pulsed illumination source, and the time delay between the application of the voltage and the laser probe pulse allows us to take a series of images that map the time evolution of the interferogram. This technique offers an exciting new diagnostic for semiconductor integrated circuits. The technique is noninvasive and compatible with high-speed operation of integrated circuits. The picosecond resolution enables us to either characterize specific logic states or watch an individual device turn on. This imaging technique is sensitive to all of the index of refraction changes that can be associated with IC`s. These include heating due to current flowing through narrow wires and charge injection into the depletion region of a transistor.

  14. Electro-optical Probing Of Terahertz Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Romanofsky, R.; Whitaker, J. F.; Valdmanis, J. A.; Mourou, G.; Jackson, T. A.

    1990-01-01

    Electro-optical probe developed to perform noncontact, nondestructive, and relatively noninvasive measurements of electric fields over broad spectrum at millimeter and shorter wavelengths in integrated circuits. Manipulated with conventional intregrated-circuit-wafer-probing equipment and operated without any special preparation of integrated circuits. Tip of probe small electro-optical crystal serving as proximity electric-field sensor.

  15. Accelerating functional verification of an integrated circuit

    SciTech Connect

    Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

    2015-10-27

    Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

  16. Tool For Tinning Integrated-Circuit Leads

    NASA Technical Reports Server (NTRS)

    Prosser, Gregory N.

    1988-01-01

    As many as eight flatpacks held. Tool made of fiberglass boards. Clamps row of flatpacks by their leads so leads on opposite side of packages dipped. After dipping, nuts on boards loosened, flatpacks turned around, nuts retightened, and untinned leads dipped. Strips of magnetic material grip leads of flatpacks (made of Kovar, magnetic iron/nickel/cobalt alloy) while boards repositioned. Micrometerlike screw used to adjust exposed width of magnetic strip to suit dimensions of flatpacks. Holds flatpack integrated circuits so leads tinned. Accommodates several flatpacks for simultaneous dipping of leads in molten solder. Adjusts to accept flatpacks in range of sizes.

  17. Integrated-Circuit Broadband Infrared Sources

    NASA Technical Reports Server (NTRS)

    Lamb, G.; Jhabvala, M.; Burgess, A.

    1989-01-01

    Microscopic devices consume less power, run hotter, and are more reliable. Simple, compact, lightweight, rapidly-responding reference sources of broadband infrared radiation made available by integrated-circuit technology. Intended primarily for use in calibration of remote-sensing infrared instruments, devices eventually replace conventional infrared sources. New devices also replace present generation of miniature infrared sources. Self-passivating nature of poly-crystalline silicon adds to reliability of devices. Maximum operating temperature is 1,000 K, and power dissipation is only one-fourth that of prior devices.

  18. An integrated circuit floating point accumulator

    NASA Technical Reports Server (NTRS)

    Goldsmith, T. C.

    1977-01-01

    Goddard Space Flight Center has developed a large scale integrated circuit (type 623) which can perform pulse counting, storage, floating point compression, and serial transmission, using a single monolithic device. Counts of 27 or 19 bits can be converted to transmitted values of 12 or 8 bits respectively. Use of the 623 has resulted in substantial savaings in weight, volume, and dollar resources on at least 11 scientific instruments to be flown on 4 NASA spacecraft. The design, construction, and application of the 623 are described.

  19. 3D packaging for integrated circuit systems

    SciTech Connect

    Chu, D.; Palmer, D.W.

    1996-11-01

    A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

  20. Testing Fixture For Microwave Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Romanofsky, Robert; Shalkhauser, Kurt

    1989-01-01

    Testing fixture facilitates radio-frequency characterization of microwave and millimeter-wave integrated circuits. Includes base onto which two cosine-tapered ridge waveguide-to-microstrip transitions fastened. Length and profile of taper determined analytically to provide maximum bandwidth and minimum insertion loss. Each cosine taper provides transformation from high impedance of waveguide to characteristic impedance of microstrip. Used in conjunction with automatic network analyzer to provide user with deembedded scattering parameters of device under test. Operates from 26.5 to 40.0 GHz, but operation extends to much higher frequencies.

  1. Automatic Parametric Testing Of Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Jennings, Glenn A.; Pina, Cesar A.

    1989-01-01

    Computer program for parametric testing saves time and effort in research and development of integrated circuits. Software system automatically assembles various types of test structures and lays them out on silicon chip, generates sequency of test instructions, and interprets test data. Employs self-programming software; needs minimum of human intervention. Adapted to needs of different laboratories and readily accommodates new test structures. Program codes designed to be adaptable to most computers and test equipment now in use. Written in high-level languages to enhance transportability.

  2. Computer Aided Engineering of Semiconductor Integrated Circuits

    DTIC Science & Technology

    1976-04-01

    transistor opera tion; (4) theoretical invest! jations of carrifr mobli *!;y *"« inversion layer of an MOSFET; (5) mathematical investigations for high...satisfactory greLnt «Lh experiment. In time, the rapid groWth of se.r- oonduotor integrated circuit (IC, technology created ^ ^ °n" £or which this theory was...and Technology of Semiconductor Devices, John Wiley and Sons, Inc., N.Y. (1967). [2] S. K. Ghandi, The Theory and Practice of

  3. SiGe/Si Monolithically Integrated Amplifier Circuits

    NASA Technical Reports Server (NTRS)

    Katehi, Linda P. B.; Bhattacharya, Pallab

    1998-01-01

    With recent advance in the epitaxial growth of silicon-germanium heterojunction, Si/SiGe HBTs with high f(sub max) and f(sub T) have received great attention in MMIC applications. In the past year, technologies for mesa-type Si/SiGe HBTs and other lumped passive components with high resonant frequencies have been developed and well characterized for circuit applications. By integrating the micromachined lumped passive elements into HBT fabrication, multi-stage amplifiers operating at 20 GHz have been designed and fabricated.

  4. Recent advances in PLC hybrid integration technology

    NASA Astrophysics Data System (ADS)

    Ogawa, Ikuo; Kitagawa, Takeshi

    2003-07-01

    Opto-electronic hybrid integraiton using a silica-based planar lightwave circuit (PLC) platform is an attractive way to realize the various kinds of opto-electronic components required for future photonic networks. This paper briefly introduces the concept and basic techniques used for PLC hybrid integration, and describes recent advances in this field. We also report on several high-performance optical devices that we recently developed using this technology.

  5. Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

    PubMed

    Reagor, James A; Holt, David W

    2016-03-01

    Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

  6. Next-generation integrated microfluidic circuits.

    PubMed

    Mosadegh, Bobak; Bersano-Begey, Tommaso; Park, Joong Yull; Burns, Mark A; Takayama, Shuichi

    2011-09-07

    This mini-review provides a brief overview of recent devices that use networks of elastomeric valves to minimize or eliminate the need for interconnections between microfluidic chips and external instruction lines that send flow control signals. Conventional microfluidic control mechanisms convey instruction signals in a parallel manner such that the number of instruction lines must increase as the number of independently operated valves increases. The devices described here circumvent this "tyranny of microfluidic interconnects" by the serial encoding of information to enable instruction of an arbitrary number of independent valves with a set number of control lines, or by the microfluidic circuit-embedded encoding of instructions to eliminate control lines altogether. Because the parallel instruction chips are the most historical and straightforward to design, they are still the most commonly used approach today. As requirements for instruction complexity, chip-to-chip communication, and real-time on-chip feedback flow control arise, the next generation of integrated microfluidic circuits will need to incorporate these latest interconnect flow control approaches.

  7. Test Diagnostics of RF Effects in Integrated Circuits

    DTIC Science & Technology

    1990-02-01

    RADC-TR-89-355 Final Technical Report February 1990AD-A219 737 TEST DIAGNOSTICS OF RF EFFECTS IN INTEGRATED CIRCUITS Martin Marietta Space Systems...DIAGNOSTICS OF RF EFFECTS IN INTEGRATED CIRCUITS 12 PERSONAL AUTHOR(S) David D. Wilson, Stan Epshtein, Mark G. Rossi, Christine L. Proffitt 13a. TYPE...presents "he results of an effort to measure the RF upset susceptibilities of CMOS and low power Schottky integrated circuits and to demonstrate a

  8. Photonic integrated circuits: new challenges for lithography

    NASA Astrophysics Data System (ADS)

    Bolten, Jens; Wahlbrink, Thorsten; Prinzen, Andreas; Porschatis, Caroline; Lerch, Holger; Giesecke, Anna Lena

    2016-10-01

    In this work routes towards the fabrication of photonic integrated circuits (PICs) and the challenges their fabrication poses on lithography, such as large differences in feature dimension of adjacent device features, non-Manhattan-type features, high aspect ratios and significant topographic steps as well as tight lithographic requirements with respect to critical dimension control, line edge roughness and other key figures of merit not only for very small but also for relatively large features, are highlighted. Several ways those challenges are faced in today's low-volume fabrication of PICs, including the concept multi project wafer runs and mix and match approaches, are presented and possible paths towards a real market uptake of PICs are discussed.

  9. Monolithic microwave integrated circuit water vapor radiometer

    NASA Technical Reports Server (NTRS)

    Sukamto, L. M.; Cooley, T. W.; Janssen, M. A.; Parks, G. S.

    1991-01-01

    A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valuable for meteorological applications as well as for determination of signal path delays due to water vapor in the atmosphere. The high cost and large size of existing WVR instruments motivate the development of miniature MMIC WVR's, which have great potential for low cost mass production. The miniaturization of WVR components allows large scale deployment of WVR's for Earth environment and meteorological applications. Small WVR's can also result in improved thermal stability, resulting in improved calibration stability. Described here is the design and fabrication of a 31.4 GHz MMIC radiometer as one channel of a thermally stable WVR as a means of assessing MMIC technology feasibility.

  10. Post irradiation effects (PIE) in integrated circuits

    NASA Technical Reports Server (NTRS)

    Shaw, D. C.; Lowry, L.; Barnes, C.; Zakharia, M.; Agarwal, S.; Rax, B.

    1991-01-01

    Post-irradiation effects (PIE) ranging from normal recovery to catastrophic failure have been observed in integrated circuits during the PIE period. Data presented show failure due to rebound after a 10 krad(Si) dose. In particular, five device types are investigated with varying PIE response. Special attention has been given to the HI1-507A analog multiplexer because its PIE response is extreme. X-ray diffraction has been uniquely employed to measure physical stress in the HI1-507A metallization. An attempt has been made to show a relationship between stress relaxation and radiation effects. All data presented support the current MIL-STD Method 1019.4 but demonstrate the importance of performing PIE measurements, even when mission doses are as low as 10 krad(Si).

  11. Monolithic Lumped Element Integrated Circuit (M2LEIC) Transistors.

    DTIC Science & Technology

    INTEGRATED CIRCUITS, *MONOLITHIC STRUCTURES(ELECTRONICS), *TRANSISTORS, CHIPS(ELECTRONICS), FABRICATION, EPITAXIAL GROWTH, ULTRAHIGH FREQUENCY, POLYSILICONS, PHOTOLITHOGRAPHY, RADIOFREQUENCY POWER, IMPEDANCE MATCHING .

  12. Integrated photo-responsive metal oxide semiconductor circuit

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzban D. (Inventor); Dargo, David R. (Inventor); Lyons, John C. (Inventor)

    1987-01-01

    An infrared photoresponsive element (RD) is monolithically integrated into a source follower circuit of a metal oxide semiconductor device by depositing a layer of a lead chalcogenide as a photoresistive element forming an ohmic bridge between two metallization strips serving as electrodes of the circuit. Voltage from the circuit varies in response to illumination of the layer by infrared radiation.

  13. W88 integrated circuit shelf life program

    SciTech Connect

    Soden, J.M.; Anderson, R.E.

    1998-01-01

    The W88 Integrated Circuit Shelf Life Program was created to monitor the long term performance, reliability characteristics, and technological status of representative WR ICs manufactured by the Allied Signal Albuquerque Microelectronics Operation (AMO) and by Harris Semiconductor Custom Integrated Circuits Division. Six types of ICs were used. A total of 272 ICs entered two storage temperature environments. Electrical testing and destructive physical analysis were completed in 1995. During each year of the program, the ICs were electrically tested and samples were selected for destructive physical analysis (DPA). ICs that failed electrical tests or DPA criteria were analyzed. Fifteen electrical failures occurred, with two dominant failure modes: electrical overstress (EOS) damage involving the production test programs and electrostatic discharge (ESD) damage during analysis. Because of the extensive handling required during multi-year programs like this, it is not unusual for EOS and ESD failures to occur even though handling and testing precautions are taken. The clustering of the electrical test failures in a small subset of the test operations supports the conclusion that the test operation itself was responsible for many of the failures and is suspected to be responsible for the others. Analysis of the electrical data for the good ICs found no significant degradation trends caused by the storage environments. Forty-six ICs were selected for DPA with findings primarily in two areas: wire bonding and die processing. The wire bonding and die processing findings are not surprising since these technology conditions had been documented during manufacturing and were determined to present acceptable risk. The current reliability assessment of the W88 stockpile assemblies employing these and related ICs is reinforced by the results of this shelf life program. Data from this program will aid future investigation of 4/3 micron or MNOS IC technology failure modes.

  14. Ge/Si Integrated Circuit For Infrared Imaging

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.

    1990-01-01

    Proposed integrated circuit consists of focal-plane array of metal/germanium Schottky-barrier photodetectors on same chip with silicon-based circuits that processes signals from photodetectors. Made compatible with underlying silicon-based circuitry by growing germanium epitaxially on silicon circuit wafers. Metal deposited in ultrahigh vacuum immediately after growth of germanium. Combination of described techniques results in high-resolution infrared-imaging circuits of superior performance.

  15. Shielded silicon gate complementary MOS integrated circuit.

    NASA Technical Reports Server (NTRS)

    Lin, H. C.; Halsor, J. L.; Hayes, P. J.

    1972-01-01

    An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

  16. InP-based three-dimensional photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Tsou, Diana; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

    2001-10-01

    Fast-growing internet traffic volumes require high data communication bandwidth over longer distances than short wavelength (850 nm) multi-mode fiber systems can provide. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low cost, high-speed laser modules at 1310 and 1550 nm wavelengths are required. The great success of GaAs 850 nm VCSELs for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with available intrinsic materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits, which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits (PICs) have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform for fabricating InP-based photonic integrated circuits compatible with surface-emitting laser technology. Employing InP transparency at 1310 and 1550 nm wavelengths, we have created 3-D photonic integrated circuits (PICs) by utilizing light beams in both surface normal and in-plane directions within the InP-based structure

  17. GaAs Optoelectronic Integrated-Circuit Neurons

    NASA Technical Reports Server (NTRS)

    Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

    1992-01-01

    Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

  18. Adaptive Voltage Management Enabling Energy Efficiency in Nanoscale Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Shapiro, Alexander E.

    Battery powered devices emphasize energy efficiency in modern sub-22 nm CMOS microprocessors rendering classic power reduction solutions not sufficient. Classical solutions that reduce power consumption in high performance integrated circuits are superseded with novel and enhanced power reduction techniques to enable the greater energy efficiency desired in modern microprocessors and emerging mobile platforms. Dynamic power consumption is reduced by operating over a wide range of supply voltages. This region of operation is enabled by a high speed and power efficient level shifter which translates low voltage digital signals to higher voltages (and vice versa), a key component that enables communication among circuits operating at different voltage levels. Additionally, optimizing the wide supply voltage range of signals propagating across long interconnect enables greater energy savings. A closed-form delay model supporting wide voltage range is developed to enable this capability. The model supports an ultra-wide voltage range from nominal voltages to subthreshold voltages, and a wide range of repeater sizes. To mitigate the drawback of lower operating speed at reduced supply voltages, the high performance exhibited by MOS current mode logic technology is exploited. High performance and energy efficient circuits are enabled by combining this logic style with power efficient near threshold circuits. Many-core systems that operate at high frequencies and process highly parallel workloads benefit from this combination of MCML with NTC. Due to aggressive scaling, static power consumption can in some cases overshadow dynamic power. Techniques to lower leakage power have therefore become an important objective in modern microprocessors. To address this issue, an adaptive power gating technique is proposed. This technique utilizes high levels of granularity to save additional leakage power when a circuit is active as opposed to standard power gating that saves static

  19. Recent advances on integrated quantum communications

    NASA Astrophysics Data System (ADS)

    Orieux, Adeline; Diamanti, Eleni

    2016-08-01

    In recent years, the use of integrated technologies for applications in the field of quantum information processing and communications has made great progress. The resulting devices feature valuable characteristics such as scalability, reproducibility, low cost and interconnectivity, and have the potential to revolutionize our computation and communication practices in the future, much in the way that electronic integrated circuits have drastically transformed our information processing capacities since the last century. Among the multiple applications of integrated quantum technologies, this review will focus on typical components of quantum communication systems and on overall integrated system operation characteristics. We are interested in particular in the use of photonic integration platforms for developing devices necessary in quantum communications, including sources, detectors and both passive and active optical elements. We also illustrate the challenges associated with performing quantum communications on chip, by using the case study of quantum key distribution—the most advanced application of quantum information science. We conclude with promising perspectives in this field.

  20. Advanced Integrated Traction System

    SciTech Connect

    Greg Smith; Charles Gough

    2011-08-31

    The United States Department of Energy elaborates the compelling need for a commercialized competitively priced electric traction drive system to proliferate the acceptance of HEVs, PHEVs, and FCVs in the market. The desired end result is a technically and commercially verified integrated ETS (Electric Traction System) product design that can be manufactured and distributed through a broad network of competitive suppliers to all auto manufacturers. The objectives of this FCVT program are to develop advanced technologies for an integrated ETS capable of 55kW peak power for 18 seconds and 30kW of continuous power. Additionally, to accommodate a variety of automotive platforms the ETS design should be scalable to 120kW peak power for 18 seconds and 65kW of continuous power. The ETS (exclusive of the DC/DC Converter) is to cost no more than $660 (55kW at $12/kW) to produce in quantities of 100,000 units per year, should have a total weight less than 46kg, and have a volume less than 16 liters. The cost target for the optional Bi-Directional DC/DC Converter is $375. The goal is to achieve these targets with the use of engine coolant at a nominal temperature of 105C. The system efficiency should exceed 90% at 20% of rated torque over 10% to 100% of maximum speed. The nominal operating system voltage is to be 325V, with consideration for higher voltages. This project investigated a wide range of technologies, including ETS topologies, components, and interconnects. Each technology and its validity for automotive use were verified and then these technologies were integrated into a high temperature ETS design that would support a wide variety of applications (fuel cell, hybrids, electrics, and plug-ins). This ETS met all the DOE 2010 objectives of cost, weight, volume and efficiency, and the specific power and power density 2015 objectives. Additionally a bi-directional converter was developed that provides charging and electric power take-off which is the first step

  1. Securing health sensing using integrated circuit metric.

    PubMed

    Tahir, Ruhma; Tahir, Hasan; McDonald-Maier, Klaus

    2015-10-20

    Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric) that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware "fingerprints". The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner.

  2. Optical Integrated Circuits Theory and Design

    NASA Astrophysics Data System (ADS)

    Li, Xiangshan

    1995-01-01

    The first part of this work describes the main theory required for the analysis and design of optical integrated circuits which have the purpose of processing light signals carried on fiber optic cables. For ease of fabrication it is advantageous to design the light processing channels in a planar geometry. The analysis of the resulting dielectric structures requires computations of both the propagation constants of the modes of the structures and the inherent energy losses resulting from the geometry of the light guiding channels. The latter losses have two primary sources, (1) radiation losses due to leakage out of the guiding channels into the supporting substrates, and (2) curvature losses due to the necessary bending of the guiding channels required to separate the light signals. The results of this work is a computer program for the design of a computer generated CAD lithographic mask that can be used to fabricate a multiple channel waveguiding structure capable of dividing an input light signal into a set number of output channels carrying designated fractions of the input energy. In the last part of this thesis we then apply the theory developed in first part to the design of a TE -TM polarization splitter. The resulting design represents an improvement over previous design suggested by other groups, and makes it possible to obtain a nearly 100% separation between the two orthogonal polarization states of the fields in a waveguide. All of the work of this thesis has potential applications in the construction of the superhighway.

  3. Securing Health Sensing Using Integrated Circuit Metric

    PubMed Central

    Tahir, Ruhma; Tahir, Hasan; McDonald-Maier, Klaus

    2015-01-01

    Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric) that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware “fingerprints”. The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner. PMID:26492250

  4. Ultraviolet integrated photonic circuits (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Fanto, Michael L.; Steidle, Jeffrey A.; Lu, Tsung-Ju; Preble, Stefan F.; Englund, Dirk R.; Tison, Christopher C.; Smith, Amos M.; Howland, Gregory A.; Soderberg, Kathy-Anne; Alsing, Paul M.

    2016-10-01

    Quantum information processing relies on the fundamental property of quantum interference, where the quality of the interference directly correlates to the indistinguishability of the interacting particles. The creation of these indistinguishable particles, photons in this case, has conventionally been accomplished with nonlinear crystals and optical filters to remove spectral distinguishability, albeit sacrificing the number of photons. This research describes the use of an integrated aluminum nitride microring resonator circuit to selectively generate photon pairs at the narrow cavity transmissions, thereby producing spectrally indistinguishable photons. These spectrally indistinguishable photons can then be routed through optical waveguide circuitry, concatenated interferometers, to manipulate and entangle the photons into the desired quantum states. Photon sources and circuitry are only two of the three required pieces of the puzzle. The final piece which this research is aimed at interfacing with are trapped ion quantum memories, based on trapped Ytterbium ions. These ions serve as very long lived and stable quantum memories with storage times on the order of 10's of minutes, compared with photonic quantum memories which are limited to 10-6 to 10-3 seconds. The caveat with trapped ions is the interaction wavelength of the photons is 369.5nm and therefore the goal of this research is to develop entangled photon sources and circuitry in that wavelength regime to interact directly with the trapped ions and bypass the need for frequency conversion.

  5. Applications of carbon nanotubes on integrated circuits

    NASA Astrophysics Data System (ADS)

    Zhang, Min

    The microelectronics technology falls within the boundaries of that definition. Carbon nanotube (CNT) is a promising alternative material for the future nanoelectronics. Owing to the unique properties of CNTs and the maturity of CMOS IC technology, the integration of the two technologies will take advantages of both. In this work, we demonstrate a new local silicon-gate carbon nanotube field-effect transistor (CNFET) by combining the in situ CNT growth technology and the SOI technology. The proposed CNFET structure has realized individual device operation, batch fabrication, low parasitics and better compatibility to the CMOS process at the same time. The configuration proposes a feasible approach to integrate the CNTs to CMOS platform for the first time, which makes CNT a step closer to application. The CNFETs show advanced DC characteristics. The ambipolar conductance and the scaling effect of the CNFETs have been analyzed based on the SB modulated conductance mechanism. Investigation of radio-frequency (RF) characteristics of CNTs is essential for their application. RF transmission characteristics of the semiconducting and metallic CNTs are investigated to the frequency of 12 GHz using the full two-port S-parameter methodology for the first time. Without the effect of the parasitics, the signal transmission capability of the CNTs maintains at a constant level and shows no degeneration even at a high frequency of 12 GHz. An empirical RLC element model has been proposed to fit the RF response of the CNT array. Capacitive contact is reported between the CNTs and the metal electrodes. We also explore the high-frequency properties of the local silicon-gate CNFET as an active device by measuring its S parameters using a common-source configuration. In addition, we demonstrate the application of CNT as via/contact filler to solve the problems of copper vias used in ICs nowadays. We have optimized the fabrication process for the CNT via integration. The CNT vias with

  6. 77 FR 33486 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-06

    ... COMMISSION Certain Integrated Circuit Packages Provided With Multiple Heat- Conducting Paths and Products.... International Trade Commission has received a complaint entitled Certain Integrated Circuit Packages Provided... sale within the United States after importation of certain integrated circuit packages provided...

  7. 76 FR 76434 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-12-07

    ... COMMISSION Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions, Receipt... Commission has received a complaint entitled In Re Certain Integrated Circuits, Chipsets, And Products... importation of certain integrated circuits, chipsets, and products containing same including televisions....

  8. 77 FR 35426 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-06-13

    ... COMMISSION Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of... within the United States after importation of certain radio frequency integrated circuits and devices... after importation of certain radio frequency integrated circuits and devices containing same...

  9. 76 FR 41521 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-07-14

    ... COMMISSION In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including... integrated circuits, chipsets, and products containing same including televisions by reason of infringement... integrated circuits, chipsets, and products containing same including televisions that infringe one or...

  10. The Effects of Space Radiation on Linear Integrated Circuit

    NASA Technical Reports Server (NTRS)

    Johnston, A.

    2000-01-01

    Permanent and transient effects are discussed that are induced in linear integrated circuits by space radiation. Recent developments include enhanced damage at low dose rate, increased damage from protons due to displacement effects, and transients in digital comparators that can cause circuit malfunctions.

  11. 35 GHz integrated circuit rectifying antenna with 33 percent efficiency

    NASA Technical Reports Server (NTRS)

    Yoo, T.-W.; Chang, K.

    1991-01-01

    A 35 GHz integrated circuit rectifying antenna (rectenna) has been developed using a microstrip dipole antenna and beam-lead mixer diode. Greater than 33 percent conversion efficiency has been achieved. The circuit should have applications in microwave/millimeter-wave power transmission and detection.

  12. Long-wavelength photonic integrated circuits and avalanche photodetectors

    NASA Astrophysics Data System (ADS)

    Tsou, Yi-Jen D.; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

    2001-10-01

    Fast-growing internet traffic volume require high data communication bandwidth over longer distances. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low-cost, high-speed laser modules at 1310 to 1550 nm wavelengths and avalanche photodetectors are required. The great success of GaAs 850nm VCSEls for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits (PICs), which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform of InP-based PICs compatible with surface-emitting laser technology, as well as a high data rate externally modulated laser module. Avalanche photodetectors (APDs) are the key component in the receiver to achieve high data rate over long transmission distance because of their high sensitivity and large gain- bandwidth product. We have used wafer fusion technology to achieve In

  13. LEC GaAs for integrated circuit applications

    NASA Technical Reports Server (NTRS)

    Kirkpatrick, C. G.; Chen, R. T.; Homes, D. E.; Asbeck, P. M.; Elliott, K. R.; Fairman, R. D.; Oliver, J. D.

    1984-01-01

    Recent developments in liquid encapsulated Czochralski techniques for the growth of semiinsulating GaAs for integrated circuit applications have resulted in significant improvements in the quality and quantity of GaAs material suitable for device processing. The emergence of high performance GaAs integrated circuit technologies has accelerated the demand for high quality, large diameter semiinsulating GaAs substrates. The new device technologies, including digital integrated circuits, monolithic microwave integrated circuits and charge coupled devices have largely adopted direct ion implantation for the formation of doped layers. Ion implantation lends itself to good uniformity and reproducibility, high yield and low cost; however, this technique also places stringent demands on the quality of the semiinsulating GaAs substrates. Although significant progress was made in developing a viable planar ion implantation technology, the variability and poor quality of GaAs substrates have hindered progress in process development.

  14. Chemical etching for automatic processing of integrated circuits

    NASA Technical Reports Server (NTRS)

    Kennedy, B. W.

    1981-01-01

    Chemical etching for automatic processing of integrated circuits is discussed. The wafer carrier and loading from a receiving air track into automatic furnaces and unloading onto a sending air track are included.

  15. 75 FR 51843 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-08-23

    ... Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products Containing the Same... certain large scale integrated circuit semiconductor chips and products containing same by reason...

  16. Vertically integrated circuit development at Fermilab for detectors

    NASA Astrophysics Data System (ADS)

    Yarema, R.; Deptuch, G.; Hoff, J.; Khalid, F.; Lipton, R.; Shenai, A.; Trimpl, M.; Zimmerman, T.

    2013-01-01

    Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

  17. Radiation-hardened transistor and integrated circuit

    DOEpatents

    Ma, Kwok K.

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  18. Addressable-Matrix Integrated-Circuit Test Structure

    NASA Technical Reports Server (NTRS)

    Sayah, Hoshyar R.; Buehler, Martin G.

    1991-01-01

    Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

  19. Isolation of Battery Chargers Integrated Into Printed Circuit Boards

    SciTech Connect

    Sullivan, James S.

    2013-11-21

    Present test procedures developed by the Federal Government (10 CFR Part 430 “Energy Conservation Program for Consumer Products”) to measure the energy consumption of battery chargers provide no method for the isolation of input power for battery chargers that have been integrated into printed circuit boards internal to electronic equipment. This prevents the measurement of Standby and Off Mode energy consumption. As a result, the energy consumption of battery chargers integrated into the printed circuit board cannot be measured.

  20. Control of exciton fluxes in an excitonic integrated circuit.

    PubMed

    High, Alex A; Novitskaya, Ekaterina E; Butov, Leonid V; Hanson, Micah; Gossard, Arthur C

    2008-07-11

    Efficient signal communication uses photons. Signal processing, however, uses an optically inactive medium, electrons. Therefore, an interconnection between electronic signal processing and optical communication is required at the integrated circuit level. We demonstrated control of exciton fluxes in an excitonic integrated circuit. The circuit consists of three exciton optoelectronic transistors and performs operations with exciton fluxes, such as directional switching and merging. Photons transform into excitons at the circuit input, and the excitons transform into photons at the circuit output. The exciton flux from the input to the output is controlled by a pattern of the electrode voltages. The direct coupling of photons, used in communication, to excitons, used as the device-operation medium, may lead to the development of efficient exciton-based optoelectronic devices.

  1. Analog integrated circuits design for processing physiological signals.

    PubMed

    Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

    2010-01-01

    Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

  2. Computer Aided Design of Integrated Circuit Fabrication Processes for VLSI Devices

    DTIC Science & Technology

    1980-01-01

    modeling capability. This requires the investigation of tile latest technological advances and their incorporation in the present process modeling program... Technology /Transient Process Kinetics In integrated circuits processing the annealing steps associated with ion implantation are poorly understood...experiments which will utilize this technology for characterization of transient process kinetics. References [7] Ref. [10] from "Recoil Range

  3. Secondary Side CMOS Feedback Control Integrated Circuit

    DTIC Science & Technology

    1990-06-01

    Temperature ( Celc ~us) Figure 5.1: Experimental Temperature Dependence cf Untrimmed Bandgap Circuit 104 1. I I ’ - ’ 0 0.9 . -0-0 Ouput Voit -ge ---.o M...Schlecht and L.F. Casey, "Comparison of the Square-Wave and Quasi- Resonant Topologies," IEEE PESC Record, 1987, pp. 124-134. 132

  4. Processing of Image Data by Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Armstrong, R. W.

    1985-01-01

    Sensors combined with logic and memory circuitry. Cross-correlation of two inputs accomplished by transversal filter. Position of image taken to point where image and template data yield maximum value correlation function. Circuit used for controlling robots, medical-image analysis, automatic vehicle guidance, and precise pointing of scientific cameras.

  5. Laser rapid prototyping of photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Eldada, Louay A.; Levy, Miguel; Scarmozzino, Robert; Osgood, Richard M., Jr.

    1994-07-01

    In this paper, we will describe our work at Columbia in developing a laser prototyping system, in conjunction with computer simulation, to design, fabricate, and test novel waveguide circuits. The system is also useful for manufacturing small-run circuit designs. The fundamental technique uses a laser-induced photoelectrochemical process for etching GaAs and other III-V compounds. The technique is maskless and discretionary. The computer-controlled apparatus can be programmed with any desired circuit pattern, and prototype waveguide circuits can be produced within a day. The waveguides and passive components produced with this technique include linear waveguides, tapered waveguides, abrupt and smoothly curved bends, Y-branches, asymmetric splitters, directional couplers, and optical delay lines. The passive devices are single-mode and low-loss. The technique also has the ability to vary the effective index of refraction along the device by grading the etch depth. In addition to passive devices, we have recently shown that active switching components can be prototyped by combining passive structures with laser-patterned metal electrodes. These electrodes are produced masklessly using standard metal deposition techniques coupled with laser- patterning of photoresist. In addition, metal can be deposited directly using laser-induced selective metallorgainic CVD.

  6. Hybrid and monolithic integration of planar lightwave circuits (PLCs)

    NASA Astrophysics Data System (ADS)

    Chen, Ray T.

    2008-02-01

    In this paper, we review the status of monolithic and hybrid integration of planar lightwave circuits (PLCs). Building blocks needed for system integration based on polymeric materials, III-V semiconductor materials, LiNbO 3 and SOI on Silicon are summarized with pros and cons. Due to the maturity of silicon CMOS technology, silicon becomes the platform of choice for optical application specific integrated circuits (OASICs). However, the indirect bandgap of silicon makes the formation of electrically pumped silicon laser a remote plausibility which requires hybrid integration of laser sources made out of III-V compound semicouductor.

  7. Microwave GaAs Integrated Circuits On Quartz Substrates

    NASA Technical Reports Server (NTRS)

    Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

    1994-01-01

    Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

  8. Integrated Circuit For Simulation Of Neural Network

    NASA Technical Reports Server (NTRS)

    Thakoor, Anilkumar P.; Moopenn, Alexander W.; Khanna, Satish K.

    1988-01-01

    Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

  9. Research in Computer Simulation of Integrated Circuits.

    DTIC Science & Technology

    1983-07-31

    bwadeid a -’. ate dew’.d or "mom 1640e 4 4 4 4.5 he ham ala ker 27601 519 6145 2549 "and 3.2 1.5 2.2 34 4230 TAME 4 A,4er Stsmao m CLAS From the show...from SPICEV it is expected that the speedup is Larger for t.(As) 4 4 4 4 6 the adder circuits compared to the filters. A first observe- iter 352 27601

  10. Multi-channel detector readout method and integrated circuit

    DOEpatents

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2004-05-18

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  11. Multi-channel detector readout method and integrated circuit

    SciTech Connect

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2006-12-12

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  12. Advanced integrated safeguards at Barnwell

    SciTech Connect

    Bambas, K.J.; Barnes, L.D.

    1980-06-01

    The development and initial performance testing of an advanced integrated safeguards system at the Barnwell Nuclear Fuel Plant (BNFP) is described. The program concentrates on the integration and coordination of physical security and nuclear materials control and accounting at a single location. Hardware and software for this phase have been installed and are currently being evaluated. The AGNS/DOE program is now in its third year of development at the BNFP.

  13. Monolithic microwave integrated circuits: Technology and design

    NASA Astrophysics Data System (ADS)

    Goyal, Ravender

    Theoretical and practical aspects of MMIC design are examined in a textbook intended for a senior or graduate engineering laboratory course. The individual chapters are contributed by specialists and cover fundamental MMIC characteristics and applications, the theory of microwave transmission, MMIC material and manufacturing technology, device modeling, amplifier design, nonlinear and control circuits, the TV-receive-only chip as a typical MMIC-based subsystem, design automation tools, on-wafer testing, MMIC packaging, and MMIC reliability. Extensive diagrams, drawings, graphs, photographs, and tables of numerical data are provided.

  14. Hybrid CMOS/Nanodevice Integrated Circuits Design and Fabrication

    DTIC Science & Technology

    2008-08-25

    This approach combines a semiconductor transistor system with a nanowire crossbar, with simple two-terminal nanodevices self-assembled at each...hybrid CMOS/nanodevice integrated circuits [10-12]. Such circuit combines a semiconductor transistors system with a nanowire crossbar, with simple two...both with and without embedded metallic clusters), self-assembled molecular monolayers, and thin chalcogenide and crystalline perovskite layers [20

  15. Development of integrated thermionic circuits for high-temperature applications

    NASA Technical Reports Server (NTRS)

    Mccormick, J. B.; Wilde, D.; Depp, S.; Hamilton, D. J.; Kerwin, W.; Derouin, C.; Roybal, L.; Wooley, R.

    1981-01-01

    Integrated thermionic circuits (ITC) capable of extended operation in ambient temperatures up to 500 C are studied. A set of practical design and performance equations is demonstrated. Experimental results are discussed in which both devices and simple circuits were successfully operated in 5000 C environments for extended periods. It is suggested that ITC's may become an important technology for high temperature instrumentation and control systems in geothermal and other high temperature environments.

  16. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    1984-01-01

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  17. Radiation Effects in 3D Integrated SOl SRAM Circuits

    DTIC Science & Technology

    2011-08-23

    Comparing Neutrons and Protons Data Monoenergetic neutrons and protons are used to characterize single event effects in electronics circuits, and are...for proton irradiation with energies between 4.8 and 500 MeV. Results are compared with 14-MeV neutron irradiation. Single event upset cross-section...fabricating circuits for space applications. singIe event effects, SOl, fully depleted, 3D integration, neutron , protons, upset cross-section U U U U SAR

  18. System-Level Integrated Circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  19. System-level integrated circuit (SLIC) development for phased array antenna applications

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Raquet, C. A.

    1991-01-01

    A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed.

  20. Single Event Transients in Linear Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buchner, Stephen; McMorrow, Dale

    2005-01-01

    On November 5, 2001, a processor reset occurred on board the Microwave Anisotropy Probe (MAP), a NASA mission to measure the anisotropy of the microwave radiation left over from the Big Bang. The reset caused the spacecraft to enter a safehold mode from which it took several days to recover. Were that to happen regularly, the entire mission would be compromised, so it was important to find the cause of the reset and, if possible, to mitigate it. NASA assembled a team of engineers that included experts in radiation effects to tackle the problem. The first clue was the observation that the processor reset occurred during a solar event characterized by large increases in the proton and heavy ion fluxes emitted by the sun. To the radiation effects engineers on the team, this strongly suggested that particle radiation might be the culprit, particularly when it was discovered that the reset circuit contained three voltage comparators (LM139). Previous testing revealed that large voltage transients, or glitches appeared at the output of the LM139 when it was exposed to a beam of heavy ions [NI96]. The function of the reset circuit was to monitor the supply voltage and to issue a reset command to the processor should the voltage fall below a reference of 2.5 V [PO02]. Eventually, the team of engineers concluded that ionizing particle radiation from the solar event produced a negative voltage transient on the output of one of the LM139s sufficiently large to reset the processor on MAP. Fortunately, as of the end of 2004, only two such resets have occurred. The reset on MAP was not the first malfunction on a spacecraft attributed to a transient. That occurred shortly after the launch of NASA s TOPEX/Poseidon satellite in 1992. It was suspected, and later confirmed, that an anomaly in the Earth Sensor was caused by a transient in an operational amplifier (OP-15) [KO93]. Over the next few years, problems on TDRS, CASSINI, [PR02] SOHO [HA99,HA01] and TERRA were also attributed

  1. Integrated circuit for SAW and MEMS sensors

    NASA Astrophysics Data System (ADS)

    Fischer, Wolf-Joachim; Koenig, Peter; Ploetner, Matthias; Hermann, Rudiger; Stab, Helmut

    2001-11-01

    The sensor processor circuit has been developed for hand-held devices used in industrial and environmental applications, such as on-line process monitoring. Thereby devices with SAW sensors or MEMS resonators will benefit from this processor especially. Up to 8 sensors can be connected to the circuit as multisensors or sensor arrays. Two sensor processors SP1 and SP2 for different applications are presented in this paper. The SP-1 chip has a PCMCIA interface which can be used for the program and data transfer. SAW sensors which are working in the frequency range from 80 MHz to 160 MHz can be connected to the processor directly. It is possible to use the new SP-2 chip fabricated in a 0.5(mu) CMOS process for SAW devices with a maximum frequency of 600 MHz. An on-chip analog-digital-converter (ADC) and 6 PWM modules support the development of high-miniaturized intelligent sensor systems We have developed a multi-SAW sensor system with this ASIC that manages the requirements on control as well as signal generation and storage and provides an interface to the PC and electronic devices on the board. Its low power consumption and its PCMCIA plug fulfil the requirements of small size and mobility. For this application sensors have been developed to detect hazardous gases in ambient air. Sensors with differently modified copper-phthalocyanine films are capable of detecting NO2 and O3, whereas those with a hyperbranched polyester film respond to NH3.

  2. Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

    PubMed

    Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

    2012-10-21

    Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

  3. Silica Integrated Optical Circuits Based on Glass Photosensitivity

    NASA Technical Reports Server (NTRS)

    Abushagur, Mustafa A. G.

    1999-01-01

    Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

  4. Self-integration of nanowires into circuits via guided growth.

    PubMed

    Schvartzman, Mark; Tsivion, David; Mahalu, Diana; Raslin, Olga; Joselevich, Ernesto

    2013-09-17

    The ability to assemble discrete nanowires (NWs) with nanoscale precision on a substrate is the key to their integration into circuits and other functional systems. We demonstrate a bottom-up approach for massively parallel deterministic assembly of discrete NWs based on surface-guided horizontal growth from nanopatterned catalyst. The guided growth and the catalyst nanopattern define the direction and length, and the position of each NW, respectively, both with unprecedented precision and yield, without the need for postgrowth assembly. We used these highly ordered NW arrays for the parallel production of hundreds of independently addressable single-NW field-effect transistors, showing up to 85% yield of working devices. Furthermore, we applied this approach for the integration of 14 discrete NWs into an electronic circuit operating as a three-bit address decoder. These results demonstrate the feasibility of massively parallel "self-integration" of NWs into electronic circuits and functional systems based on guided growth.

  5. Photonic integrated circuits based on silica and polymer PLC

    NASA Astrophysics Data System (ADS)

    Izuhara, T.; Fujita, J.; Gerhardt, R.; Sui, B.; Lin, W.; Grek, B.

    2013-03-01

    Various methods of hybrid integration of photonic circuits are discussed focusing on merits and challenges. Material platforms discussed in this report are mainly polymer and silica. We categorize the hybridization methods using silica and polymer waveguides into two types, chip-to-chip and on-chip integration. General reviews of these hybridization technologies from the past works are reviewed. An example for each method is discussed in details. We also discuss current status of our silica PLC hybrid integration technology.

  6. A new low drift integrator system for the Experiment Advanced Superconductor Tokamak.

    PubMed

    Liu, D M; Wan, B N; Wang, Y; Wu, Y C; Shen, B; Ji, Z S; Luo, J R

    2009-05-01

    A new type of the integrator system with the low drift characteristic has been developed to accommodate the long pulse plasma discharges on Experiment Advanced Superconductor Tokamak (EAST). The integrator system is composed of the Ethernet control module and the integral module which includes one integrator circuit, followed by two isolation circuits and two program-controlled amplifier circuits. It compensates automatically integration drift and is applied in real-time control. The performance test and the experimental results in plasma discharges show that the developed integrator system can meet the requirements of plasma control on the accuracy and noise level of the integrator in long pulse discharges.

  7. Recent advances in integrated photonic sensors.

    PubMed

    Passaro, Vittorio M N; de Tullio, Corrado; Troia, Benedetto; La Notte, Mario; Giannoccaro, Giovanni; De Leonardis, Francesco

    2012-11-09

    Nowadays, optical devices and circuits are becoming fundamental components in several application fields such as medicine, biotechnology, automotive, aerospace, food quality control, chemistry, to name a few. In this context, we propose a complete review on integrated photonic sensors, with specific attention to materials, technologies, architectures and optical sensing principles. To this aim, sensing principles commonly used in optical detection are presented, focusing on sensor performance features such as sensitivity, selectivity and rangeability. Since photonic sensors provide substantial benefits regarding compatibility with CMOS technology and integration on chips characterized by micrometric footprints, design and optimization strategies of photonic devices are widely discussed for sensing applications. In addition, several numerical methods employed in photonic circuits and devices, simulations and design are presented, focusing on their advantages and drawbacks. Finally, recent developments in the field of photonic sensing are reviewed, considering advanced photonic sensor architectures based on linear and non-linear optical effects and to be employed in chemical/biochemical sensing, angular velocity and electric field detection.

  8. Recent Advances in Integrated Photonic Sensors

    PubMed Central

    Passaro, Vittorio M. N.; de Tullio, Corrado; Troia, Benedetto; La Notte, Mario; Giannoccaro, Giovanni; De Leonardis, Francesco

    2012-01-01

    Nowadays, optical devices and circuits are becoming fundamental components in several application fields such as medicine, biotechnology, automotive, aerospace, food quality control, chemistry, to name a few. In this context, we propose a complete review on integrated photonic sensors, with specific attention to materials, technologies, architectures and optical sensing principles. To this aim, sensing principles commonly used in optical detection are presented, focusing on sensor performance features such as sensitivity, selectivity and rangeability. Since photonic sensors provide substantial benefits regarding compatibility with CMOS technology and integration on chips characterized by micrometric footprints, design and optimization strategies of photonic devices are widely discussed for sensing applications. In addition, several numerical methods employed in photonic circuits and devices, simulations and design are presented, focusing on their advantages and drawbacks. Finally, recent developments in the field of photonic sensing are reviewed, considering advanced photonic sensor architectures based on linear and non-linear optical effects and to be employed in chemical/biochemical sensing, angular velocity and electric field detection. PMID:23202223

  9. Thermally-induced voltage alteration for integrated circuit analysis

    DOEpatents

    Cole, Jr., Edward I.

    2000-01-01

    A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

  10. Practical applications of digital integrated circuits. Part 3: Practical sequential theory and synchronous circuits

    NASA Technical Reports Server (NTRS)

    1973-01-01

    Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.

  11. Integrated logic circuits using single-atom transistors.

    PubMed

    Mol, J A; Verduijn, J; Levine, R D; Remacle, F; Rogge, S

    2011-08-23

    Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal-oxide-semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch.

  12. Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs

    NASA Astrophysics Data System (ADS)

    Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.

    2015-03-01

    This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.

  13. Printed organic thin-film transistor-based integrated circuits

    NASA Astrophysics Data System (ADS)

    Mandal, Saumen; Noh, Yong-Young

    2015-06-01

    Organic electronics is moving ahead on its journey towards reality. However, this technology will only be possible when it is able to meet specific criteria including flexibility, transparency, disposability and low cost. Printing is one of the conventional techniques to deposit thin films from solution-based ink. It is used worldwide for visual modes of information, and it is now poised to enter into the manufacturing processes of various consumer electronics. The continuous progress made in the field of functional organic semiconductors has achieved high solubility in common solvents as well as high charge carrier mobility, which offers ample opportunity for organic-based printed integrated circuits. In this paper, we present a comprehensive review of all-printed organic thin-film transistor-based integrated circuits, mainly ring oscillators. First, the necessity of all-printed organic integrated circuits is discussed; we consider how the gap between printed electronics and real applications can be bridged. Next, various materials for printed organic integrated circuits are discussed. The features of these circuits and their suitability for electronics using different printing and coating techniques follow. Interconnection technology is equally important to make this product industrially viable; much attention in this review is placed here. For high-frequency operation, channel length should be sufficiently small; this could be achievable with a combination of surface treatment-assisted printing or laser writing. Registration is also an important issue related to printing; the printed gate should be perfectly aligned with the source and drain to minimize parasitic capacitances. All-printed organic inverters and ring oscillators are discussed here, along with their importance. Finally, future applications of all-printed organic integrated circuits are highlighted.

  14. Modular packaging technique for combining integrated circuits and discrete components

    NASA Technical Reports Server (NTRS)

    Lacchia, J. F.

    1969-01-01

    Technique for packaging electronic modules interconnects integrated circuits and discrete components by means of beryllium-copper strips in a molded diallyphthalate tray. Simple girder-like construction provides ease of assembly, high rigidity, excellent vibration resistance, and good heat dissipation characteristics.

  15. 1998 technology roadmap for integrated circuits used in critical applications

    SciTech Connect

    Dellin, T.A.

    1998-09-01

    Integrated Circuits (ICs) are being extensively used in commercial and government applications that have extreme consequences of failure. The rapid evolution of the commercial microelectronics industry presents serious technical and supplier challenges to this niche critical IC marketplace. This Roadmap was developed in conjunction with the Using ICs in Critical Applications Workshop which was held in Albuquerque, NM, November 11--12, 1997.

  16. FASTHELP. Integrated Circuit Failure Analysis Hypertext Help System

    SciTech Connect

    Henderson, C; Barton, D; Campbell, A; Cole, E; Mikawa, R E; Peterson, K A; Rife, J L; Soden, J M

    1994-09-30

    This software assists a failure analyst performing failure analysis on integrated circuits. The software can also be used to train inexperienced failure analysts. The software also provides a method for storing information and making it easily available to experienced failure analysts.

  17. Integrated circuit with dissipative layer for photogenerated carriers

    DOEpatents

    Myers, D.R.

    1989-09-12

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

  18. Integrated circuit with dissipative layer for photogenerated carriers

    DOEpatents

    Myers, David R.

    1989-01-01

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissi The U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

  19. Bioluminescent bioreporter integrated circuit devices and methods for detecting ammonia

    DOEpatents

    Simpson, Michael L [Knoxville, TN; Paulus, Michael J [Knoxville, TN; Sayler, Gary S [Blaine, TN; Applegate, Bruce M [West Lafayette, IN; Ripp, Steven A [Knoxville, TN

    2007-04-24

    Monolithic bioelectronic devices for the detection of ammonia includes a microorganism that metabolizes ammonia and which harbors a lux gene fused with a heterologous promoter gene stably incorporated into the chromosome of the microorganism and an Optical Application Specific Integrated Circuit (OASIC). The microorganism is generally a bacterium.

  20. Integrated circuit with dissipative layer for photogenerated carriers

    DOEpatents

    Myers, D.R.

    1988-04-20

    The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissipative layer of silicon nitride between a silicon substrate and the active device. Free carriers generated in the substrate are dissipated by the layer before they can build up charge on the active device. 1 fig.

  1. Chemical vapor deposition for automatic processing of integrated circuits

    NASA Technical Reports Server (NTRS)

    Kennedy, B. W.

    1980-01-01

    Chemical vapor deposition for automatic processing of integrated circuits including the wafer carrier and loading from a receiving air track into automatic furnaces and unloading on to a sending air track is discussed. Passivation using electron beam deposited quartz is also considered.

  2. Evaluation performance of digital integrated circuits while exposed to radiation

    NASA Astrophysics Data System (ADS)

    Barbashov, V. M.; Trushkin, N. S.

    2016-10-01

    The methods of functional-logical simulation of digital integrated circuits (ICs) exposed to radiation are observed. It is shown that in a number of cases functional and electrical deterioration of ICs performances have both deterministic and non-deterministic nature. Methods for simulating IC failure exposed to radiation based on the model of fuzzy digital machine and Brauer probabilistic reliability machine are proposed.

  3. Flexible circuits with integrated switches for robotic shape sensing

    NASA Astrophysics Data System (ADS)

    Harnett, C. K.

    2016-05-01

    Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

  4. Quantum dot rolled-up microtube optoelectronic integrated circuit.

    PubMed

    Bhowmick, Sishir; Frost, Thomas; Bhattacharya, Pallab

    2013-05-15

    A rolled-up microtube optoelectronic integrated circuit operating as a phototransceiver is demonstrated. The microtube is made of a InGaAs/GaAs strained bilayer with InAs self-organized quantum dots inserted in the GaAs layer. The phototransceiver consists of an optically pumped microtube laser and a microtube photoconductive detector connected by an a-Si/SiO2 waveguide. The loss in the waveguide and responsivity of the entire phototransceiver circuit are 7.96 dB/cm and 34 mA/W, respectively.

  5. Modeling of single-event upset in bipolar integrated circuits

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.

    1983-01-01

    The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

  6. Transmission line for millimeter-wave integrated circuits

    NASA Astrophysics Data System (ADS)

    Komar, G. I.; Shestopalov, V. P.

    The advantages of the miniature wideband slotted mirror line (SML) for millimeter-wave integrated circuits is described. It is shown that the SML has the same order of losses in the mm-range as the stripline in the cm-range. In addition, the SML makes possible the planar design of a wide range of functional components and units, and provides for the complex miniaturization of closed antenna-feed systems in the mm-range, which makes it possible to avoid the use of several types of sections in a single circuit. Forms of cross sections of the SML are presented.

  7. Microwave monolithic integrated circuit-related metrology at the National Institute of Standards and Technology

    NASA Astrophysics Data System (ADS)

    Reeve, Gerome; Marks, Roger; Blackburn, David

    1990-12-01

    How the National Institute of Standards and Technology (NIST) interacts with the GaAs community and the Defense Advanced Research Projects Agency microwave monolithic integrated circuit (MMIC) initiative is described. The organization of a joint industry and government laboratory consortium for MMIC-related metrology research is described along with some of the initial technical developments at NIST done in support of the consortium.

  8. Advanced Integration Matrix Education Outreach

    NASA Technical Reports Server (NTRS)

    Paul Heather L.

    2004-01-01

    The Advanced Integration Matrix (AIM) will design a ground-based test facility for developing revolutionary integrated systems for joint human-robotic missions in order to study and solve systems-level integration issues for exploration missions beyond Low Earth Orbit (LEO). This paper describes development plans for educational outreach activities related to technological and operational integration scenarios similar to the challenges that will be encountered through this project. The education outreach activities will provide hands-on, interactive exercises to allow students of all levels to experience design and operational challenges similar to what NASA deals with everyday in performing the integration of complex missions. These experiences will relate to and impact students everyday lives by demonstrating how their interests in science and engineering can develop into future careers, and reinforcing the concepts of teamwork and conflict resolution. Allowing students to experience and contribute to real-world development, research, and scientific studies of ground-based simulations for complex exploration missions will stimulate interest in the space program, and bring NASA's challenges to the student level. By enhancing existing educational programs and developing innovative activities and presentations, AIM will support NASA s endeavor to "inspire the next generation of explorers.. .as only NASA can."

  9. Millimeter-wave and terahertz integrated circuit antennas

    NASA Technical Reports Server (NTRS)

    Rebeiz, Gabriel M.

    1992-01-01

    This paper presents a comprehensive review of integrated circuit antennas suitable for millimeter and terahertz applications. A great deal of research was done on integrated circuit antennas in the last decade and many of the problems associated with electrically thick dielectric substrates, such as substrate modes and poor radiation patterns, have been understood and solved. Several new antennas, such as the integrated horn antenna, the dielectric-filled parabola, the Fresnel plate antenna, the dual-slot antenna, and the log-periodic and spiral antennas on extended hemispherical lenses, have resulted in excellent performance at millimeter-wave frequencies, and are covered in detail in this paper. Also, a review of the efficiency definitions used with planar antennas is given in detail in the appendix.

  10. Monolithic Microwave Integrated Circuit (MMIC) Phased Array Demonstrated With ACTS

    NASA Technical Reports Server (NTRS)

    1996-01-01

    Monolithic Microwave Integrated Circuit (MMIC) arrays developed by the NASA Lewis Research Center and the Air Force Rome Laboratory were demonstrated in aeronautical terminals and in mobile or fixed Earth terminals linked with NASA's Advanced Communications Technology Satellite (ACTS). Four K/Ka-band experimental arrays were demonstrated between May 1994 and May 1995. Each array had GaAs MMIC devices at each radiating element for electronic beam steering and distributed power amplification. The 30-GHz transmit array used in uplinks to ACTS was developed by Lewis and Texas Instruments. The three 20-GHz receive arrays used in downlinks from ACTS were developed in cooperation with the Air Force Rome Laboratory, taking advantage of existing Air Force integrated-circuit, active-phased-array development contracts with the Boeing Company and Lockheed Martin Corporation. Four demonstrations, each related to an application of high interest to both commercial and Department of Defense organizations, were conducted. The location, type of link, and the data rate achieved for each of the applications is shown. In one demonstration-- an aeronautical terminal experiment called AERO-X--a duplex voice link between an aeronautical terminal on the Lewis Learjet and ACTS was achieved. Two others demonstrated duplex voice links (and in one case, interactive video links as well) between ACTS and an Army high-mobility, multipurpose wheeled vehicle (HMMWV, or "humvee"). In the fourth demonstration, the array was on a fixed mount and was electronically steered toward ACTS. Lewis served as project manager for all demonstrations and as overall system integrator. Lewis engineers developed the array system including a controller for open-loop tracking of ACTS during flight and HMMWV motion, as well as a laptop data display and recording system used in all demonstrations. The Jet Propulsion Laboratory supported the AERO-X program, providing elements of the ACTS Mobile Terminal. The successful

  11. Laser-Controlled Rapid Prototyping of Photonic Integrated Circuits.

    NASA Astrophysics Data System (ADS)

    Eldada, Louay A.

    1994-01-01

    Photonic integrated circuits offer important cost and environmental advantages over circuits composed of discrete components. However, the design and fabrication of complex, large-area photonic integrated circuits (PICs) is severely limited by the lack of prototyping tools as well as the appropriate device structures. This thesis describes the use of a novel laser fabrication process for the rapid prototyping of integrated optical circuits in compound semiconductor substrates. The fabrication is based on a type of laser direct photoelectrochemical etching process that uses a focused laser beam which is scanned under computer control to form micrometer-scale grooves, thereby patterning rib-like optical waveguide structures. The computer-controlled apparatus can be programmed with any desired circuit pattern, and prototype waveguide circuits can be produced within a day. The technique does not require the use of a mask; thus, the etching can be done in a single step. In the first part of this thesis, the technique of micrometer-scale photoelectrochemical etching of GaAs is described. The use of this technique for the fabrication of several passive integrated optical devices in GaAs is then presented. These "building block" devices include linear waveguides, bends, Y-branches, and tapers. From these, we were able to form simple passive devices such as splitters and directional couplers. These devices have low optical loss, are single-mode, and can be accurately modeled using effective index calculations. The usefulness of this technique as a prototyping tool is then demonstrated by its use in the fabrication of the first sub-Angstrom integrated channel-dropping filter. After the presentation of the passive devices results, the use of this technique to fabricate several active devices is discussed. These electrooptic devices include a polarization modulator, an integrated amplitude modulator consisting of a polarization modulator and an on-chip polarizer, and an

  12. Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

    NASA Astrophysics Data System (ADS)

    Geier, Michael

    Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and

  13. Attachment method for stacked integrated circuit (IC) chips

    DOEpatents

    Bernhardt, Anthony F.; Malba, Vincent

    1999-01-01

    An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

  14. Attachment method for stacked integrated circuit (IC) chips

    DOEpatents

    Bernhardt, A.F.; Malba, V.

    1999-08-03

    An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

  15. Trends in integrated circuit design for particle physics experiments

    NASA Astrophysics Data System (ADS)

    Atkin, E. V.

    2017-01-01

    Integrated circuits are one of the key complex units available to designers of multichannel detector setups. A whole number of factors makes Application Specific Integrated Circuits (ASICs) valuable for Particle Physics and Astrophysics experiments. Among them the most important ones are: integration scale, low power dissipation, radiation tolerance. In order to make possible future experiments in the intensity, cosmic, and energy frontiers today ASICs should provide new level of functionality at a new set of constraints and trade-offs, like low-noise high-dynamic range amplification and pulse shaping, high-speed waveform sampling, low power digitization, fast digital data processing, serialization and data transmission. All integrated circuits, necessary for physical instrumentation, should be radiation tolerant at an earlier not reached level (hundreds of Mrad) of total ionizing dose and allow minute almost 3D assemblies. The paper is based on literary source analysis and presents an overview of the state of the art and trends in nowadays chip design, using partially own ASIC lab experience. That shows a next stage of ising micro- and nanoelectronics in physical instrumentation.

  16. Organic printed photonics: From microring lasers to integrated circuits.

    PubMed

    Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

    2015-09-01

    A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 10(5), which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

  17. Organic printed photonics: From microring lasers to integrated circuits

    PubMed Central

    Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

    2015-01-01

    A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices. PMID:26601256

  18. Advanced packaging for Integrated Micro-Instruments

    NASA Technical Reports Server (NTRS)

    Lyke, James L.

    1995-01-01

    The relationship between packaging, microelectronics, and micro-electrical-mechanical systems (MEMS) is an important one, particularly when the edges of performance boundaries are pressed, as in the case of miniaturized systems. Packaging is a sort of physical backbone that enables the maximum performance of these systems to be realized, and the penalties imposed by conventional packing approaches is particularly limiting for MEMS devices. As such, advanced packaging approaches, such as multi-chip modules (MCM's) have been touted as a true means of electronic 'enablement' for a variety of application domains. Realizing an optimum system of packaging, however, in not as simple as replacing a set of single chip packages with a substrate of interconnections. Research at Phillips Laboratory has turned up a number of integrating options in the two- and three-dimensional rending of miniature systems with physical interconnection structures with intrinsically high performance. Not only do these structures motivate the redesign of integrated circuits (IC's) for lower power, but they possess interesting features that provide a framework for the direct integration of MEMS devices. Cost remains a barrier to the application of MEMS devices, even in space systems. Several innovations are suggested that will result in lower cost and more rapid cycle time. First, the novelty of a 'constant floor plan' MCM which encapsulates a variety of commonly used components into a stockable, easily customized assembly is discussed. Next, the use of low-cost substrates is examined. The anticipated advent of ultra-high density interconnect (UHDI) is suggested as the limit argument of advanced packaging. Finally, the concept of a heterogeneous 3-D MCM system is outlined that allows for the combination of different compatible packaging approaches into a uniformly dense structure that could also include MEMS-based sensors.

  19. 77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-03-29

    ... Certain Semiconductor Integrated Circuit Devices and Products Containing Same, DN 2888; the Commission is... importation of certain semiconductor integrated circuit devices and products containing same. The complaint...] [FR Doc No: 2012-7567] INTERNATIONAL TRADE COMMISSION [DN 2888] Certain Semiconductor...

  20. 76 FR 34101 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-06-10

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including... integrated circuits, chipsets, and products containing same including televisions, media players, and...

  1. 77 FR 74027 - Certain Integrated Circuit Packages Provided with Multiple Heat-Conducting Paths and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-12-12

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Integrated Circuit Packages Provided with Multiple Heat- Conducting Paths and Products... integrated circuit packages provided with multiple heat-conducting paths and products containing same...

  2. 75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-12-06

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing... United States after importation of certain semiconductor integrated circuits using tungsten...

  3. Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

    NASA Technical Reports Server (NTRS)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2012-01-01

    Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

  4. Integrated circuit generating 3- and 5-scroll attractors

    NASA Astrophysics Data System (ADS)

    Trejo-Guerra, R.; Tlelo-Cuautle, E.; Jiménez-Fuentes, J. M.; Sánchez-López, C.; Muñoz-Pacheco, J. M.; Espinosa-Flores-Verdad, G.; Rocha-Pérez, J. M.

    2012-11-01

    This paper introduces the experimental realization of the first integrated circuit of a multi-scroll continuous chaotic oscillator showing 3- and 5-scroll attractors. It is based on a variant of the Chua's system. The most relevant issue is the implementation of a saw-tooth-like nonlinear function, which is designed by using floating gate MOS (FGMOS) transistors. Therefore, the realization of a voltage-to-current nonlinear cell by a piecewise-linear approach allows us to have only two external control inputs instead of numerous external voltage references, as usually done in current circuit realizations. Experimental results of the proposed integrated multi-scroll oscillator along with its corner analysis are provided.

  5. Broadband opto-mechanical phase shifter for photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Guo, Xiang; Zou, Chang-Ling; Ren, Xi-Feng; Sun, Fang-Wen; Guo, Guang-Can

    2012-08-01

    A broadband opto-mechanical phase shifter for photonic integrated circuits is proposed and numerically investigated. The structure consists of a mode-carrying waveguide and a deformable non-mode-carrying nanostring, which are parallel with each other. Since the nanostring can be deflected by the optical gradient force between the waveguide and the nanostring, the effective refractive indices of the waveguide will be changed and a phase shift will be generated. The phase shift under different geometry sizes, launched powers and boundary conditions are calculated and the dynamical properties as well as the thermal noise's effect are also discussed. It is demonstrated that a π phase shift can be realized with only about 0.64 mW launched power and 50 μm long nanostring. The proposed phase shifter may find potential usage in future investigation of photonic integrated circuits.

  6. Radiation Testing and Evaluation Issues for Modern Integrated Circuits

    NASA Technical Reports Server (NTRS)

    LaBel, Kenneth A.; Cohn, Lew M.

    2005-01-01

    Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

  7. Transplanted embryonic neurons integrate into adult neocortical circuits.

    PubMed

    Falkner, Susanne; Grade, Sofia; Dimou, Leda; Conzelmann, Karl-Klaus; Bonhoeffer, Tobias; Götz, Magdalena; Hübener, Mark

    2016-11-10

    The ability of the adult mammalian brain to compensate for neuronal loss caused by injury or disease is very limited. Transplantation aims to replace lost neurons, but the extent to which new neurons can integrate into existing circuits is unknown. Here, using chronic in vivo two-photon imaging, we show that embryonic neurons transplanted into the visual cortex of adult mice mature into bona fide pyramidal cells with selective pruning of basal dendrites, achieving adult-like densities of dendritic spines and axonal boutons within 4-8 weeks. Monosynaptic tracing experiments reveal that grafted neurons receive area-specific, afferent inputs matching those of pyramidal neurons in the normal visual cortex, including topographically organized geniculo-cortical connections. Furthermore, stimulus-selective responses refine over the course of many weeks and finally become indistinguishable from those of host neurons. Thus, grafted neurons can integrate with great specificity into neocortical circuits that normally never incorporate new neurons in the adult brain.

  8. Aperture efficiency of integrated-circuit horn antennas

    NASA Technical Reports Server (NTRS)

    Guo, Yong; Lee, Karen; Stimson, Philip; Potter, Kent; Rutledge, David

    1991-01-01

    The aperture efficiency of silicon integrated-circuit horn antennas has been improved by optimizing the length of the dipole probes and by coating the entire horn walls with gold. To make these measurements, a new thin-film power-density meter was developed for measuring power density with accuracies better than 5 percent. The measured aperture efficiency improved from 44 percent to 72 percent at 93 GHz. This is sufficient for use in many applications which now use machined waveguide horns.

  9. Computer-Aided Engineering of Semiconductor Integrated Circuits

    DTIC Science & Technology

    1979-07-01

    growth and the resulting electrical properties are critical if reproducible device performance is to be achieved. Despite the fact that thermally grown... properties is the continuing decrease in active device This work represents a joint effort by the Stanford University Integrated Circuits Laboratory, Fairchild...goals will allow accurate prediction of oxide and surface properties and the influence of oxidation on other processes for an arbitrary device

  10. Extended life testing evaluation of complementary MOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Brosnan, T. E.

    1972-01-01

    The purpose of the extended life testing evaluation of complementary MOS integrated circuits was twofold: (1) To ascertain the long life capability of complementary MOS devices. (2) To assess the objectivity and reliability of various accelerated life test methods as an indication or prediction tool. In addition, the determination of a suitable life test sequence for these devices was of importance. Conclusions reached based on the parts tested and the test results obtained was that the devices were not acceptable.

  11. Laser Integration on Silicon Photonic Circuits Through Transfer Printing

    DTIC Science & Technology

    2017-03-10

    AFRL-AFOSR-UK-TR-2017-0019 Laser integration on silicon photonic circuits through transfer printing Gunther Roelkens UNIVERSITEIT GENT VZW Final...Form ApprovedOMB No. 0704-0188 The public reporting burden for this collection of information is estimated to average 1 hour per response, including...collection of information . Send comments regarding this burden estimate or   any other aspect of this collection of information , including suggestions

  12. Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit.

    PubMed

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

    2016-12-21

    Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10(-9) is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers.

  13. Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

    NASA Astrophysics Data System (ADS)

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J.; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

    2016-12-01

    Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10-9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers.

  14. Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

    PubMed Central

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J.; Galili, Michael; Morioka, Toshio; Oxenløwe, Leif Katsuo

    2016-01-01

    Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7 × 7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than −30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing switching is demonstrated successfully. Bit error rate performance below 10−9 is obtained for all spatial channels with low power penalty. The proposed design can be easily upgraded to reconfigurable optical add/drop multiplexer capable of switching several multicore fibers. PMID:28000735

  15. 77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-01

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of... the sale within the United States after importation of certain semiconductor integrated circuit... semiconductor integrated circuit devices and products containing same that infringe one or more of claims 1,...

  16. 75 FR 43553 - In the Matter of Certain Encapsulated Integrated Circuit Devices and Products Containing Same...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-07-26

    ... COMMISSION In the Matter of Certain Encapsulated Integrated Circuit Devices and Products Containing Same..., and sale within the United States after importation of certain encapsulated integrated circuit devices... encapsulated integrated circuit devices and products contains same in connection with claims 1- 4, 7, 17,...

  17. 75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-02-04

    ... COMMISSION In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice... importation, and sale within the United States after importation of certain semiconductor integrated circuits... infringement certain LSI integrated circuits, as well as certain Seagate hard disk drives that contain...

  18. 77 FR 64826 - Certain Integrated Circuit Chips and Products Containing the Same; Institution of Investigation...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-10-23

    ... COMMISSION Certain Integrated Circuit Chips and Products Containing the Same; Institution of Investigation... integrated circuit chips and products containing the same by reason of infringement of certain claims of U.S... importation of certain integrated circuit chips and products containing the same that infringe one or more...

  19. 77 FR 1505 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-01-10

    ... COMMISSION Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice... importation, and the sale within the United States after importation of certain integrated circuits, chipsets... importation, or the sale within the United States after importation of certain integrated circuits,...

  20. 78 FR 10635 - Certain Integrated Circuit Devices and Products Containing the Same; Notice of Receipt of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-02-14

    ... COMMISSION Certain Integrated Circuit Devices and Products Containing the Same; Notice of Receipt of... received a complaint entitled Certain Integrated Circuit Devices and Products Containing the Same, DN 2938..., and the sale within the United States after importation of certain integrated circuit devices...

  1. 75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-05-05

    ... COMMISSION In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products... the sale within the United States after importation of certain large scale integrated circuit... certain large scale integrated circuit semiconductor chips or products containing the same that...

  2. Monolithic Microwave Integrated Circuit (MMIC) Frequency Doublers - 2nd Pass Correction

    DTIC Science & Technology

    2013-09-01

    Monolithic Microwave Integrated Circuit (MMIC) Frequency Doublers—2nd Pass Correction by John E. Penn ARL-TN-0580 September 2013...September 2013 Monolithic Microwave Integrated Circuit (MMIC) Frequency Doublers—2nd Pass Correction John E. Penn Sensors and Electron...COVERED (From - To) 4. TITLE AND SUBTITLE Monolithic Microwave Integrated Circuit (MMIC) Frequency Doublers–2nd Pass Correction 5a. CONTRACT NUMBER

  3. Advances by the Integral Fast Reactor Program

    SciTech Connect

    Lineberry, M.J.; Pedersen, D.R.; Walters, L.C.; Cahalan, J.E.

    1991-01-01

    The advances by the Integral Fast Reactor Program at Argonne National Laboratory are the subject of this paper. The Integral Fast Reactor (IFR) is an advanced liquid-metal-cooled reactor concept being developed at Argonne National Laboratory. The advances stressed in the paper include fuel irradiation performance, improved passive safety, and the development of a prototype fuel cycle facility. 14 refs.

  4. Photonic-integrated circuit for continuous-wave THz generation.

    PubMed

    Theurer, Michael; Göbel, Thorsten; Stanze, Dennis; Troppenz, Ute; Soares, Francisco; Grote, Norbert; Schell, Martin

    2013-10-01

    We demonstrate a photonic-integrated circuit for continuous-wave (cw) terahertz (THz) generation. By comprising two lasers and an optical phase modulator on a single chip, the full control of the THz signal is enabled via a unique bidirectional operation technique. Integrated heaters allow for continuous tuning of the THz frequency over 570 GHz. Applied to a coherent cw THz photomixing system operated at 1.5 μm optical wavelength, we reach a signal-to-noise ratio of 44 dB at 1.25 THz, which is identical to the performance of a standard system based on discrete components.

  5. Diamond electro-optomechanical resonators integrated in nanophotonic circuits

    SciTech Connect

    Rath, P.; Ummethala, S.; Pernice, W. H. P.; Diewald, S.; Lewes-Malandrakis, G.; Brink, D.; Heidrich, N.; Nebel, C.

    2014-12-22

    Diamond integrated photonic devices are promising candidates for emerging applications in nanophotonics and quantum optics. Here, we demonstrate active modulation of diamond nanophotonic circuits by exploiting mechanical degrees of freedom in free-standing diamond electro-optomechanical resonators. We obtain high quality factors up to 9600, allowing us to read out the driven nanomechanical response with integrated optical interferometers with high sensitivity. We are able to excite higher order mechanical modes up to 115 MHz and observe the nanomechanical response also under ambient conditions.

  6. Advanced integrated solvent extraction systems

    SciTech Connect

    Horwitz, E.P.; Dietz, M.L.; Leonard, R.A.

    1997-10-01

    Advanced integrated solvent extraction systems are a series of novel solvent extraction (SX) processes that will remove and recover all of the major radioisotopes from acidic-dissolved sludge or other acidic high-level wastes. The major focus of this effort during the last 2 years has been the development of a combined cesium-strontium extraction/recovery process, the Combined CSEX-SREX Process. The Combined CSEX-SREX Process relies on a mixture of a strontium-selective macrocyclic polyether and a novel cesium-selective extractant based on dibenzo 18-crown-6. The process offers several potential advantages over possible alternatives in a chemical processing scheme for high-level waste treatment. First, if the process is applied as the first step in chemical pretreatment, the radiation level for all subsequent processing steps (e.g., transuranic extraction/recovery, or TRUEX) will be significantly reduced. Thus, less costly shielding would be required. The second advantage of the Combined CSEX-SREX Process is that the recovered Cs-Sr fraction is non-transuranic, and therefore will decay to low-level waste after only a few hundred years. Finally, combining individual processes into a single process will reduce the amount of equipment required to pretreat the waste and therefore reduce the size and cost of the waste processing facility. In an ongoing collaboration with Lockheed Martin Idaho Technology Company (LMITCO), the authors have successfully tested various segments of the Advanced Integrated Solvent Extraction Systems. Eichrom Industries, Inc. (Darien, IL) synthesizes and markets the Sr extractant and can supply the Cs extractant on a limited basis. Plans are under way to perform a test of the Combined CSEX-SREX Process with real waste at LMITCO in the near future.

  7. Universal discrete Fourier optics RF photonic integrated circuit architecture.

    PubMed

    Hall, Trevor J; Hasan, Mehedi

    2016-04-04

    This paper describes a coherent electro-optic circuit architecture that generates a frequency comb consisting of N spatially separated orders using a generalised Mach-Zenhder interferometer (MZI) with its N × 1 combiner replaced by an optical N × N Discrete Fourier Transform (DFT). Advantage may be taken of the tight optical path-length control, component and circuit symmetries and emerging trimming algorithms offered by photonic integration in any platform that offers linear electro-optic phase modulation such as LiNbO3, silicon, III-V or hybrid technology. The circuit architecture subsumes all MZI-based RF photonic circuit architectures in the prior art given an appropriate choice of output port(s) and dimension N although the principal application envisaged is phase correlated subcarrier generation for all optical orthogonal frequency division multiplexing. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. Implementation is found to be practical.

  8. Pneumatic oscillator circuits for timing and control of integrated microfluidics.

    PubMed

    Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

    2013-11-05

    Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

  9. Integrated Circuit-Based Biofabrication with Common Biomaterials for Probing Cellular Biomechanics.

    PubMed

    Sung, Chun-Yen; Yang, Chung-Yao; Yeh, J Andrew; Cheng, Chao-Min

    2016-02-01

    Recent advances in bioengineering have enabled the development of biomedical tools with modifiable surface features (small-scale architecture) to mimic extracellular matrices and aid in the development of well-controlled platforms that allow for the application of mechanical stimulation for studying cellular biomechanics. An overview of recent developments in common biomaterials that can be manufactured using integrated circuit-based biofabrication is presented. Integrated circuit-based biofabrication possesses advantages including mass and diverse production capacities for fabricating in vitro biomedical devices. This review highlights the use of common biomaterials that have been most frequently used to study cellular biomechanics. In addition, the influence of various small-scale characteristics on common biomaterial surfaces for a range of different cell types is discussed.

  10. Hybrid III-V/silicon SOA for photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Kaspar, P.; Brenot, R.; Le Liepvre, A.; Accard, A.; Make, D.; Levaufre, G.; Girard, N.; Lelarge, F.; Duan, G.-H.; Olivier, S.; Jany, Christophe; Kopp, C.; Menezo, S.

    2014-11-01

    Silicon photonics has reached a considerable level of maturity, and the complexity of photonic integrated circuits (PIC) is steadily increasing. As the number of components in a PIC grows, loss management becomes more and more important. Integrated semiconductor optical amplifiers (SOA) will be crucial components in future photonic systems for loss compensation. In addition, there are specific applications, where SOAs can play a key role beyond mere loss compensation, such as modulated reflective SOAs in carrier distributed passive optical networks or optical gates in packet switching. It is, therefore, highly desirable to find a generic integration platform that includes the possibility of integrating SOAs on silicon. Various methods are currently being developed to integrate light emitters on silicon-on-insulator (SOI) waveguide circuits. Many of them use III-V materials for the hybrid integration on SOI. Various types of lasers have been demonstrated by several groups around the globe. In some of the integration approaches, SOAs can be implemented using essentially the same technology as for lasers. In this paper we will focus on SOA devices based on a hybrid integration approach where III-V material is bonded on SOI and a vertical optical mode transfer is used to couple light between SOI waveguides and guides formed in bonded III-V semiconductor layers. In contrast to evanescent coupling schemes, this mode transfer allows for a higher confinement factor in the gain material and thus for efficient light amplification over short propagation distances. We will outline the fabrication process of our hybrid components and present some of the most interesting results from a fabricated and packaged hybrid SOA.

  11. Design and status of the RF-digitizer integrated circuit

    NASA Technical Reports Server (NTRS)

    Rayhrer, B.; Lam, B.; Young, L. E.; Srinivasan, J. M.; Thomas, J. B.

    1991-01-01

    An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

  12. Design automation for integrated nonlinear logic circuits (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

    2016-05-01

    A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

  13. Synthetic circuits integrating logic and memory in living cells.

    PubMed

    Siuti, Piro; Yazbek, John; Lu, Timothy K

    2013-05-01

    Logic and memory are essential functions of circuits that generate complex, state-dependent responses. Here we describe a strategy for efficiently assembling synthetic genetic circuits that use recombinases to implement Boolean logic functions with stable DNA-encoded memory of events. Application of this strategy allowed us to create all 16 two-input Boolean logic functions in living Escherichia coli cells without requiring cascades comprising multiple logic gates. We demonstrate long-term maintenance of memory for at least 90 cell generations and the ability to interrogate the states of these synthetic devices with fluorescent reporters and PCR. Using this approach we created two-bit digital-to-analog converters, which should be useful in biotechnology applications for encoding multiple stable gene expression outputs using transient inputs of inducers. We envision that this integrated logic and memory system will enable the implementation of complex cellular state machines, behaviors and pathways for therapeutic, diagnostic and basic science applications.

  14. Advanced optical manufacturing digital integrated system

    NASA Astrophysics Data System (ADS)

    Tao, Yizheng; Li, Xinglan; Li, Wei; Tang, Dingyong

    2012-10-01

    It is necessarily to adapt development of advanced optical manufacturing technology with modern science technology development. To solved these problems which low of ration, ratio of finished product, repetition, consistent in big size and high precision in advanced optical component manufacturing. Applied business driven and method of Rational Unified Process, this paper has researched advanced optical manufacturing process flow, requirement of Advanced Optical Manufacturing integrated System, and put forward architecture and key technology of it. Designed Optical component core and Manufacturing process driven of Advanced Optical Manufacturing Digital Integrated System. the result displayed effective well, realized dynamic planning Manufacturing process, information integration improved ratio of production manufactory.

  15. Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

    PubMed

    Ng, Kian Ann; Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V

    2016-01-01

    Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

  16. Integrated circuits: Resistless processing simplifies production and cuts costs

    NASA Astrophysics Data System (ADS)

    Weiner, K.

    1993-03-01

    Reducing the complexity and cost of producing deep-submicrometer integrated circuits (IC's) will soon be possible using a revolutionary approach being developed at the Lawrence Livermore National Laboratory (LLNL). Resistless Projection Doping (RPD) will eliminate the need for photoresist processing during the impurity doping step. This single innovation will reduce the doping sequence from 13 steps to 1 and eliminate the need for five pieces of capital equipment costing more than $5 million. The overall cost of high-volume wafer fabrication will be reduced by more than 10 percent. In addition, the LLNL RPD machine is compact and modular, minimizing facilities costs when compared to today's industry-standard doping equipment. These physical characteristics of the machine also allow the RPD process to be easily incorporated into single-wafer, 'cluster' processing tools. When integrated with existing deposition, etching, and annealing steps and developing lithography techniques, the LLNL doping process completes the technology set required to produce a flexible fabrication facility of the future. At one-fifth the cost of current mega-fabrication facilities, the availability of these compact, low-volume, smart factories will give US manufacturers a substantial competitive advantage in the world-wide marketplace for high-value custom and semi-custom integrated circuits.

  17. Implantable neurotechnologies: a review of integrated circuit neural amplifiers

    PubMed Central

    Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V.

    2016-01-01

    Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification. PMID:26798055

  18. SEM-contour shape analysis based on circuit structure for advanced systematic defect inspection

    NASA Astrophysics Data System (ADS)

    Toyoda, Yasutaka; Shindo, Hiroyuki; Hojo, Yutaka; Fuchimoto, Daisuke

    2014-04-01

    We have developed a practicable measurement technique that can help to achieve reliable inspections for systematic defects in advanced semiconductor devices. Systematic defects occurring in the design and mask processes are a dominant component of integrated circuit yield loss in nano-scaled technologies. Therefore, it is essential to ensure systematic defects are detected at an early stage of wafer fabrication. In the past, printed pattern shapes have been evaluated by human eyes or by taking manual critical dimension (CD) measurements. However, these operations are sometimes unstable and inaccurate. Last year, we proposed a new technique for taking measurements by using a SEM contour [1]. This technique enables a highly precise quantification of various complex 2D shaped patterns by comparing a contour extracted from a SEM image using a CD measurement algorithm and an ideal pattern. We improved this technique to enable the carrying out of inspections suitable for every pattern structure required for minimizing the process margin. This technique quantifies a pattern shape of a target-layer pattern using information on a multi-layered circuit structure. This enabled it to confirm the existence of a critical defect in a circuit connecting upper/lower-layers. This paper describes the improved technique and the evaluation results obtained in evaluating it in detail.

  19. Universal nondestructive mm-wave integrated circuit test fixture

    NASA Technical Reports Server (NTRS)

    Romanofsky, Robert R. (Inventor); Shalkhauser, Kurt A. (Inventor)

    1990-01-01

    Monolithic microwave integrated circuit (MMIC) test includes a bias module having spring-loaded contacts which electrically engage pads on a chip carrier disposed in a recess of a base member. RF energy is applied to and passed from the chip carrier by chamfered edges of ridges in the waveguide passages of housings which are removably attached to the base member. Thru, Delay, and Short calibration standards having dimensions identical to those of the chip carrier assure accuracy and reliability of the test. The MMIC chip fits in an opening in the chip carrier with the boundaries of the MMIC lying on movable reference planes thereby establishing accuracy and flexibility.

  20. Cycles of self-pulsations in a photonic integrated circuit.

    PubMed

    Karsaklian Dal Bosco, Andreas; Kanno, Kazutaka; Uchida, Atsushi; Sciamanna, Marc; Harayama, Takahisa; Yoshimura, Kazuyuki

    2015-12-01

    We report experimentally on the bifurcation cascade leading to the appearance of self-pulsation in a photonic integrated circuit in which a laser diode is subjected to delayed optical feedback. We study the evolution of the self-pulsing frequency with the increase of both the feedback strength and the injection current. Experimental observations show good qualitative accordance with numerical results carried out with the Lang-Kobayashi rate equation model. We explain the mechanism underlying the self-pulsations by a phenomenon of beating between successive pairs of external cavity modes and antimodes.

  1. Light-induced voltage alteration for integrated circuit analysis

    DOEpatents

    Cole, Jr., Edward I.; Soden, Jerry M.

    1995-01-01

    An apparatus and method are described for analyzing an integrated circuit (IC), The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC, The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs.

  2. Light-induced voltage alteration for integrated circuit analysis

    DOEpatents

    Cole, E.I. Jr.; Soden, J.M.

    1995-07-04

    An apparatus and method are described for analyzing an integrated circuit (IC). The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC. The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs. 18 figs.

  3. Method for deposition of a conductor in integrated circuits

    DOEpatents

    Creighton, J. Randall; Dominguez, Frank; Johnson, A. Wayne; Omstead, Thomas R.

    1997-01-01

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

  4. Method for deposition of a conductor in integrated circuits

    DOEpatents

    Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

    1997-09-02

    A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

  5. State-transfer simulation in integrated waveguide circuits

    NASA Astrophysics Data System (ADS)

    Latmiral, L.; Di Franco, C.; Mennea, P. L.; Kim, M. S.

    2015-08-01

    Spin-chain models have been widely studied in terms of quantum information processes, for instance for the faithful transmission of quantum states. Here, we investigate the limitations of mapping this process to an equivalent one through a bosonic chain. In particular, we keep in mind experimental implementations, which the progress in integrated waveguide circuits could make possible in the very near future. We consider the feasibility of exploiting the higher dimensionality of the Hilbert space of the chain elements for the transmission of a larger amount of information, and the effects of unwanted excitations during the process. Finally, we exploit the information-flux method to provide bounds to the transfer fidelity.

  6. Stainless Steel NaK Circuit Integration and Fill Submission

    NASA Technical Reports Server (NTRS)

    Garber, Anne E.

    2006-01-01

    The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed to hold a eutectic mixture of sodium potassium (NaK), was redesigned to hold lithium; but due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature loop include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This document summarizes the integration and fill of the pumped liquid metal NaK flow circuit.

  7. Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

    PubMed

    Nakazato, Kazuo

    2014-03-28

    By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor.

  8. Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit

    PubMed Central

    Nakazato, Kazuo

    2014-01-01

    By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor. PMID:24567475

  9. Bipolar integrated circuits in SiC for extreme environment operation

    NASA Astrophysics Data System (ADS)

    Zetterling, Carl-Mikael; Hallén, Anders; Hedayati, Raheleh; Kargarrazi, Saleh; Lanni, Luigia; Malm, B. Gunnar; Mardani, Shabnam; Norström, Hans; Rusu, Ana; Saveda Suvanam, Sethu; Tian, Ye; Östling, Mikael

    2017-03-01

    Silicon carbide (SiC) integrated circuits have been suggested for extreme environment operation. The challenge of a new technology is to develop process flow, circuit models and circuit designs for a wide temperature range. A bipolar technology was chosen to avoid the gate dielectric weakness and low mobility drawback of SiC MOSFETs. Higher operation temperatures and better radiation hardness have been demonstrated for bipolar integrated circuits. Both digital and analog circuits have been demonstrated in the range from room temperature to 500 °C. Future steps are to demonstrate some mixed signal circuits of greater complexity. There are remaining challenges in contacting, metallization, packaging and reliability.

  10. Development of optical packet and circuit integrated ring network testbed.

    PubMed

    Furukawa, Hideaki; Harai, Hiroaki; Miyazawa, Takaya; Shinada, Satoshi; Kawasaki, Wataru; Wada, Naoya

    2011-12-12

    We developed novel integrated optical packet and circuit switch-node equipment. Compared with our previous equipment, a polarization-independent 4 × 4 semiconductor optical amplifier switch subsystem, gain-controlled optical amplifiers, and one 100 Gbps optical packet transponder and seven 10 Gbps optical path transponders with 10 Gigabit Ethernet (10GbE) client-interfaces were newly installed in the present system. The switch and amplifiers can provide more stable operation without equipment adjustments for the frequent polarization-rotations and dynamic packet-rate changes of optical packets. We constructed an optical packet and circuit integrated ring network testbed consisting of two switch nodes for accelerating network development, and we demonstrated 66 km fiber transmission and switching operation of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10GbE frames. Error-free (frame error rate < 1×10(-4)) operation was achieved with optical packets of various packet lengths and packet rates, and stable operation of the network testbed was confirmed. In addition, 4K uncompressed video streaming over OPS links was successfully demonstrated.

  11. Integrated circuit amplifiers for multi-electrode intracortical recording.

    PubMed

    Jochum, Thomas; Denison, Timothy; Wolf, Patrick

    2009-02-01

    Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

  12. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  13. Graphene/Si CMOS hybrid hall integrated circuits.

    PubMed

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-07

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  14. Control technology for integrated circuit fabrication at Micro-Circuit Engineering, Incorporated, West Palm Beach, Florida

    NASA Astrophysics Data System (ADS)

    Mihlan, G. I.; Mitchell, R. I.; Smith, R. K.

    1984-07-01

    A survey to assess control technology for integrated circuit fabrication was conducted. Engineering controls included local and general exhaust ventilation, shielding, and personal protective equipment. Devices or work stations that contained toxic materials that were potentially dangerous were controlled by local exhaust ventilation. Less hazardous areas were controlled by general exhaust ventilation. Process isolation was used in the plasma etching, low pressure chemical vapor deposition, and metallization operations. Shielding was used in ion implantation units to control X-ray emissions, in contact mask alignes to limit ultraviolet (UV) emissions, and in plasma etching units to control radiofrequency and UV emissions. Most operations were automated. Use of personal protective equipment varied by job function.

  15. Wafer-scale boundary value integrated circuit architecture

    SciTech Connect

    Delgado-Frias, J.G.

    1986-01-01

    Wafer scale integration (WSI) technology offers the potential for improving speed and reliability of a large integrated circuit system. An architecture is presented for a boundary value integrated circuit engine which lends itself to implementation in WSI. The philosophy underpinning this architecture includes local communication, cell regularity, and fault tolerance. The research described here proposes, investigates, and simulates this computer architecture and its flaw avoidance schemes for a WSI implementation. Boundary value differential equation computations are utilized in a number of scientific and engineering applications. A boundary value machine is ideally suited for solutions of finite difference and finite element problems with specified boundary values. The architecture is a 2-D array of computational cells. Each basic cell has four bit serial processing elements (PEs) and a local memory. Most communications is limited to transfer between adjacent PEs to reduce complexity, avoid long delays, and localize the effects of silicon flaws. Memory access time is kept short by restricting memory service to PEs in the same cell. I/O operation is performed by means of a row multiple single line I/O bus, which allows fast, reliable and independent data transference. WSI yield losses are due to gross defects and random defects. Gross defects which affect large portions of the wafer are usually fatal for any WSI implementation. Overcoming random defects which cover either a small area or points is achieved by defect avoidance schemes that are developed for this architecture. Those schemes are provided at array, cell, and communication level. Capabilities and limitations of the proposed WSI architecture can be observed through the simulations. Speed degradation of the array and the PE due to silicon defects is observed by means of simulation. Also, module and bus utilization are computed and presented.

  16. In-plant testing of a novel coal cleaning circuit using advanced technologies, Quarterly report, March 1 - May 31, 1996

    SciTech Connect

    Honaker, R.Q.; Reed, S.; Mohanty, M.K.

    1996-12-31

    Research conducted at Southern Illinois University at Carbondale over the past two years has identified highly efficient methods for treating fine coal (i.e., -28 mesh). In this study, a circuit comprised of the three advanced fine coal cleaning technologies is being tested in an operating preparation plant to evaluate circuit performance and to compare the performance with the current technologies used to treat -16 mesh fine coal. The circuit integrated a Floatex hydrosizer, a Falcon concentrator and a Jameson froth flotation cell. The Floatex hydrosizer is being used as a primary cleaner for the nominally -16 mesh Illinois No. 5 fine coal circuit feed. The overflow of the Floatex is screened at 48 mesh using a Sizetec vibratory screen to produce a clean coal product from the screen overflow. The screen overflow is further treated by the Falcon and Jameson Cell. During this reporting period, tests were initiated on the fine coal circuit installed at the Kerr-McGee Galatia preparation plant. The circuit was found to reduce both the ash content and the pyritic sulfur content. Additional in-plant circuitry tests are ongoing.

  17. 77 FR 57589 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-09-18

    ... COMMISSION Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions... found that those Zoran products that were adjudicated in Integrated Circuits I are precluded under the... recommended a limited exclusion order barring entry of Zoran's and MediaTek's infringing integrated...

  18. Novel technique for reliability testing of silicon integrated circuits

    NASA Astrophysics Data System (ADS)

    LeMinh, Phuong; Wallinga, H.; Woerlee, P. H.; van den Berg, Albert; Holleman, J.

    2001-04-01

    We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon dioxide capacitors of 5 X 5 and 10 X 10 micrometer2 in sizes. Both positive and quasi-negative photoresists were employed. The resultant products are holes in the developed positive photoresist layer and mushroom- shaped spots in the quasi-negative one. Based on the photoresist decomposition energy dose, we could approximately calculate the light emitting power in the near UV range. Due to the proximity between the layer and the light source, the power is interpreted on a more accurate basis, which was a difficult task in previous research. The product sizes, dependent on the light emitting currents and exposure time, establish the core for a rough model that can be used for further application of this technique as a reliability analysis tool. One potential application is to detect and characterize regions of hot carriers on a VLSI circuit under operation for design improvement purpose.

  19. Investigation of failure mechanisms in integrated vacuum circuits

    NASA Technical Reports Server (NTRS)

    Rosengreen, A.

    1972-01-01

    The fabrication techniques of integrated vacuum circuits are described in detail. Data obtained from a specially designed test circuit are presented. The data show that the emission observed in reverse biased devices is due to cross-talk between the devices and can be eliminated by electrostatic shielding. The lifetime of the cathodes has been improved by proper activation techniques. None of the cathodes on life test has shown any sign of failure after more than 3500 hours. Life tests of triodes show a decline of anode current by a factor of two to three after a few days. The current recovers when the large positive anode voltage (100 V) has been removed for a few hours. It is suggested that this is due to trapped charges in the sapphire substrate. Evidence of the presence of such charges is given, and a model of the charge distribution is presented consistent with the measurements. Solution of the problem associated with the decay of triode current may require proper treatment of the sapphire surface and/or changes in the deposition technique of the thin metal films.

  20. Germanium on silicon to enable integrated photonic circuits

    NASA Astrophysics Data System (ADS)

    Hopkins, F. Kenneth; Walsh, Kevin M.; Benken, Alexander; Jones, John; Averett, Kent; Diggs, Darnell E.; Tan, Loon-Seng; Mou, Shin; Grote, James G.

    2013-09-01

    Electronic circuits alone cannot fully meet future requirements for speed, size, and weight of many sensor systems, such as digital radar technology and as a result, interest in integrated photonic circuits (IPCs) and the hybridization of electronics with photonics is growing. However, many IPC components such as photodetectors are not presently ideal, but germanium has many advantages to enable higher performance designs that can be better incorporated into an IPC. For example, Ge photodetectors offer an enormous responsivity to laser wavelengths near 1.55μm at high frequencies to 40GHz, and they can be easily fabricated as part of a planar silicon processing schedule. At the same time, germanium has enormous potential for enabling 1.55 micron lasers on silicon and for enhancing the performance of silicon modulators. Our new effort has begun by studying the deposition of germanium on silicon and beginning to develop methods for processing these films. In initial experiments comparing several common chemical solutions for selective etching under patterned positive photoresist, it was found that hydrogen peroxide (H2O2) at or below room temperature (20 C) produced the sharpest patterns in the Ge films; H2O2 at a higher temperature (50 C) resulted in the greatest lateral etching.

  1. Wireless multichannel biopotential recording using an integrated FM telemetry circuit.

    PubMed

    Mohseni, Pedram; Najafi, Khalil; Eliades, Steven J; Wang, Xiaoqin

    2005-09-01

    This paper presents a four-channel telemetric microsystem featuring on-chip alternating current amplification, direct current baseline stabilization, clock generation, time-division multiplexing, and wireless frequency-modulation transmission of microvolt- and millivolt-range input biopotentials in the very high frequency band of 94-98 MHz over a distance of approximately 0.5 m. It consists of a 4.84-mm2 integrated circuit, fabricated using a 1.5-microm double-poly double-metal n-well standard complementary metal-oxide semiconductor process, interfaced with only three off-chip components on a custom-designed printed-circuit board that measures 1.7 x 1.2 x 0.16 cm3, and weighs 1.1 g including two miniature 1.5-V batteries. We characterize the microsystem performance, operating in a truly wireless fashion in single-channel and multichannel operation modes, via extensive benchtop and in vitro tests in saline utilizing two different micromachined neural recording microelectrodes, while dissipating approximately 2.2 mW from a 3-V power supply. Moreover, we demonstrate successful wireless in vivo recording of spontaneous neural activity at 96.2 MHz from the auditory cortex of an awake marmoset monkey at several transmission distances ranging from 10 to 50 cm with signal-to-noise ratios in the range of 8.4-9.5 dB.

  2. Minimizing the area required for time constants in integrated circuits

    NASA Technical Reports Server (NTRS)

    Lyons, J. C.

    1972-01-01

    When a medium- or large-scale integrated circuit is designed, efforts are usually made to avoid the use of resistor-capacitor time constant generators. The capacitor needed for this circuit usually takes up more surface area on the chip than several resistors and transistors. When the use of this network is unavoidable, the designer usually makes an effort to see that the choice of resistor and capacitor combinations is such that a minimum amount of surface area is consumed. The optimum ratio of resistance to capacitance that will result in this minimum area is equal to the ratio of resistance to capacitance which may be obtained from a unit of surface area for the particular process being used. The minimum area required is a function of the square root of the reciprocal of the products of the resistance and capacitance per unit area. This minimum occurs when the area required by the resistor is equal to the area required by the capacitor.

  3. Integrated circuit for processing a low-frequency signal from a seismic detector

    SciTech Connect

    Malashevich, N. I.; Roslyakov, A. S.; Polomoshnov, S. A. Fedorov, R. A.

    2011-12-15

    Specific features for the detection and processing of a low-frequency signal from a seismic detector are considered in terms of an integrated circuit based on a large matrix crystal of the 5507 series. This integrated circuit is designed for the detection of human movements. The specific features of the information signal, obtained at the output of the seismic detector, and the main characteristics of the integrated circuit and its structure are reported.

  4. Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

    PubMed

    Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

    2015-04-06

    Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

  5. IRIS (Integrity and Reliability in Integrated Circuits) Test Article Generation (ITAG)

    DTIC Science & Technology

    2015-03-31

    Projects Agency Microsystems Technology Office (MTO) Administrative Point of Contact Ms. Brigidann Cooper, brigidannc@usc.edu University of Southern...lifespan of these components. DARPA’s Microelectronics Technology Office established the Integrity and Reliability in Integrated Circuits (IRIS...in a cost-effective manner on State of the Art (SoA) process technologies 15. SUBJECT TERMS 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF 18

  6. Monolithic microwave integrated circuit devices for active array antennas

    NASA Technical Reports Server (NTRS)

    Mittra, R.

    1984-01-01

    Two different aspects of active antenna array design were investigated. The transition between monolithic microwave integrated circuits and rectangular waveguides was studied along with crosstalk in multiconductor transmission lines. The boundary value problem associated with a discontinuity in a microstrip line is formulated. This entailed, as a first step, the derivation of the propagating as well as evanescent modes of a microstrip line. The solution is derived to a simple discontinuity problem: change in width of the center strip. As for the multiconductor transmission line problem. A computer algorithm was developed for computing the crosstalk noise from the signal to the sense lines. The computation is based on the assumption that these lines are terminated in passive loads.

  7. Uncertain behaviours of integrated circuits improve computational performance

    PubMed Central

    Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

    2015-01-01

    Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance. PMID:26586362

  8. Apparatus and method for defect testing of integrated circuits

    SciTech Connect

    Cole, E.I. Jr.; Soden, J.M.

    2000-02-29

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V(DD), to an IC under test and measures a transient voltage component, V(DDT), signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V(DDT) signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V(DDT) signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  9. Wireless Neural Recording With Single Low-Power Integrated Circuit

    PubMed Central

    Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

    2010-01-01

    We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

  10. Plasmonic nanopatch array for optical integrated circuit applications

    PubMed Central

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

  11. Plasmonic nanopatch array for optical integrated circuit applications

    NASA Astrophysics Data System (ADS)

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-11-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

  12. Plasmonic nanopatch array for optical integrated circuit applications.

    PubMed

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-11-08

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

  13. Apparatus and method for defect testing of integrated circuits

    DOEpatents

    Cole, Jr., Edward I.; Soden, Jerry M.

    2000-01-01

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  14. Development of a plan for automating integrated circuit processing

    NASA Technical Reports Server (NTRS)

    1971-01-01

    The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

  15. Infrared transparent graphene heater for silicon photonic integrated circuits.

    PubMed

    Schall, Daniel; Mohsin, Muhammad; Sagade, Abhay A; Otto, Martin; Chmielak, Bartos; Suckow, Stephan; Giesecke, Anna Lena; Neumaier, Daniel; Kurz, Heinrich

    2016-04-18

    Thermo-optical tuning of the refractive index is one of the pivotal operations performed in integrated silicon photonic circuits for thermal stabilization, compensation of fabrication tolerances, and implementation of photonic operations. Currently, heaters based on metal wires provide the temperature control in the silicon waveguide. The strong interaction of metal and light, however, necessitates a certain gap between the heater and the photonic structure to avoid significant transmission loss. Here we present a graphene heater that overcomes this constraint and enables an energy efficient tuning of the refractive index. We achieve a tuning power as low as 22 mW per free spectral range and fast response time of 3 µs, outperforming metal based waveguide heaters. Simulations support the experimental results and suggest that for graphene heaters the spacing to the silicon can be further reduced yielding the best possible energy efficiency and operation speed.

  16. Integrated Sagnac loop mirror circuit for fiber laser

    NASA Astrophysics Data System (ADS)

    Lee, Tae Ho; Kim, Chang-Seok; Jeong, Myung Yung

    2007-02-01

    Broadband reflection mirror is an important optical device to make a wide resonance bandwidth of the multi-wavelength fiber laser cavity including fiber Bragg grating mirrors. Though a chirped fiber Bragg grating has been used for broadband reflection mirror device, it still requires more improvements in the control of reflection wavelength bandwidth and reflection ratio, which are key design parameters of broadband reflection mirror. In this research, we propose an integrated mirror circuit based on polarization-maintaining fiber Sagnac loop interferometer to utilize for tunable resonance cavity of fiber laser with semiconductor optical amplifier. It is available to control both resonance bandwidth by varying the length of polarization-maintaining fiber and reflection ratio by tuning the polarization state of Sagnac loop. Broad resonance bandwidth of 40 nm could be obtained from Sagnac mirror with thes 0.15 m length of polarization-maintaining fiber.

  17. Design and testing of integrated circuits for reactor protection channels

    SciTech Connect

    Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.; Rana, I.

    1995-06-01

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing.

  18. Design and testing of integrated circuits for reactor protection channels

    SciTech Connect

    Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.

    1995-06-01

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. The purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing. A demonstration model for protection system of PWR reactor has been designed and built.

  19. Methods of fabricating applique circuits

    DOEpatents

    Dimos, Duane B.; Garino, Terry J.

    1999-09-14

    Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

  20. Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space

    NASA Technical Reports Server (NTRS)

    Johnston, Allan H.; Rax, Bernard G.

    2006-01-01

    This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.

  1. Intelligent switches of integrated lightwave circuits with core telecommunication functions

    NASA Astrophysics Data System (ADS)

    Izhaky, Nahum; Duer, Reuven; Berns, Neil; Tal, Eran; Vinikman, Shirly; Schoenwald, Jeffrey S.; Shani, Yosi

    2001-05-01

    We present a brief overview of a promising switching technology based on Silica on Silicon thermo-optic integrated circuits. This is basically a 2D solid-state optical device capable of non-blocking switching operation. Except of its excellent performance (insertion loss<5dB, switching time<2ms...), the switch enables additional important build-in functionalities. It enables single-to- single channel switching and single-to-multiple channel multicasting/broadcasting. In addition, it has the capability of channel weighting and variable output power control (attenuation), for instance, to equalize signal levels and compensate for unbalanced different optical input powers, or to equalize unbalanced EDFA gain curve. We examine the market segments appropriate for the switch size and technology, followed by a discussion of the basic features of the technology. The discussion is focused on important requirements from the switch and the technology (e.g., insertion loss, power consumption, channel isolation, extinction ratio, switching time, and heat dissipation). The mechanical design is also considered. It must take into account integration of optical fiber, optical planar wafer, analog electronics and digital microprocessor controls, embedded software, and heating power dissipation. The Lynx Photon.8x8 switch is compared to competing technologies, in terms of typical market performance requirements.

  2. Automatic visual inspection of integrated circuits using an SEM

    SciTech Connect

    Kayaalp, A.E.

    1988-01-01

    The author investigates the complex problem of designing an integrated-circuit inspection system that will be used in controlling an automated semiconductor manufacturing facility. To satisfy the accuracy requirements, he proposes a system that integrates information supplied by multiple intelligent (virtual) sensors. Most of his work concentrated on the design of two scanning-electron-microscope (SEM)-based, intelligent sensors. One of them extracts 3D IC surface-topography information using computer stereo-vision techniques, and the other identifies shape defects in IC patterns using the IC design file as the reference. Both of these problems are viewed as constrained contour-matching problems. In stereo matching, feature contours extracted from the left and right stereo images are matched, where in pattern-shape inspection, pattern boundary contours extracted from the image and the IC design file are matched. An optimization technique is presented for solving the matching problem that results in both cases. This general approach simplifies the task of transforming the specifications of a physical problem into a computational form and results in a modular system.

  3. SDN architecture for optical packet and circuit integrated networks

    NASA Astrophysics Data System (ADS)

    Furukawa, Hideaki; Miyazawa, Takaya

    2016-02-01

    We have been developing an optical packet and circuit integrated (OPCI) network, which realizes dynamic optical path, high-density packet multiplexing, and flexible wavelength resource allocation. In the OPCI networks, a best-effort service and a QoS-guaranteed service are provided by employing optical packet switching (OPS) and optical circuit switching (OCS) respectively, and users can select these services. Different wavelength resources are assigned for OPS and OCS links, and the amount of their wavelength resources are dynamically changed in accordance with the service usage conditions. To apply OPCI networks into wide-area (core/metro) networks, we have developed an OPCI node with a distributed control mechanism. Moreover, our OPCI node works with a centralized control mechanism as well as a distributed one. It is therefore possible to realize SDN-based OPCI networks, where resource requests and a centralized configuration are carried out. In this paper, we show our SDN architecture for an OPS system that configures mapping tables between IP addresses and optical packet addresses and switching tables according to the requests from multiple users via a web interface. While OpenFlow-based centralized control protocol is coming into widespread use especially for single-administrative, small-area (LAN/data-center) networks. Here, we also show an interworking mechanism between OpenFlow-based networks (OFNs) and the OPCI network for constructing a wide-area network, and a control method of wavelength resource selection to automatically transfer diversified flows from OFNs to the OPCI network.

  4. Silicon hybrid Wafer Scale Integration (WSI) used to fabricate a Hilbert transform integrated circuit module

    NASA Astrophysics Data System (ADS)

    Gaughan, Daniel J.

    1990-12-01

    This research was performed in order to develop a superior processing schedule for fabricating wafer-scale integration (WSI) circuit modules. This technology allows the design of circuitry that spans the entire surface of a silicon substrate wafer. The circuit element employed in this research was the Hilbert transform, a digital phase-shifting circuit. The transform was incorporated into a three integrated circuit (IC) die package that consisted of a mechanically supportive silicon wafer, three IC die, and a planarizing silicon wafer. The die were epoxied into this wafer using a Teflon block as a flat, and the combination was epoxied onto the substrate wafer, forming the IC module. The original design goals of this research were to keep the IC die and wafer planar and to electrically characterize of the module's interconnections. The first goal was met; the resultant process uses a low temperature (50 C) cure to achieve die-to-wafer planarity of within 5 microns. The second was not met due to the inability to pattern the chosen photosensitive dielectric material. Recommendations for further research included the need to use a stable non-stick surface as a epoxy cure fixture and the need to investigate the photopatternable dielectric material.

  5. A technique for modelling p- n junction depletion capacitance of multiple doping regions in integrated circuits

    NASA Astrophysics Data System (ADS)

    Pinkham, Raymond; Anderson, Daniel F.

    1986-08-01

    The continuing advancements in integrated circuit technology have placed new burdons on the circuit design engineer, who must rely extensively upon computer simulation to correctly predict circuit behavior. One challenge is to develop better modelling techniques to more accurately deal with complex p- n junction structures often used in modern VLSI designs. This paper presents an easily implemented method for deriving parameters which accurately model the behavior of MOS VLSI structures containing complex p- n junction capacitance components. The methodology is applicable to both planar and laterally diffused junctions, whether formed by direct ion implantation or by diffusion from a finite or infinite source. The theories behind the equations used and results of the application of this new technique are discussed. A flow chart for a fitter program based on the new method is presented and described. The corresponding program written for the TI-59 scientific programmable calculator is available. Final model parameters are given and are shown to produce a numerical capacitance model which is accurate to within 2%.

  6. 77 FR 39510 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-07-03

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not... the sale within the United States after importation of certain semiconductor integrated...

  7. 76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-03-17

    ... From the Federal Register Online via the Government Publishing Office ] INTERNATIONAL TRADE COMMISSION In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products... the sale within the United States after importation of certain large scale integrated...

  8. 77 FR 66481 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-11-05

    ... COMMISSION Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice..., and the sale within the United States after importation of certain integrated circuits, chipsets, and... collectively filed a motion to stay the procedural schedule pending the completion of Certain...

  9. 78 FR 16533 - Certain Integrated Circuit Devices and Products Containing the Same; Institution of Investigation...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-03-15

    ... COMMISSION Certain Integrated Circuit Devices and Products Containing the Same; Institution of Investigation... importation, or the sale within the United States after importation of certain integrated circuit devices and... sale for importation, and/or the sale within the United States after importation of certain...

  10. 77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-10-04

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of... importation, and the sale within the United States after importation of certain semiconductor integrated circuit devices and products containing same by reason of infringement of certain claims of U.S....

  11. 75 FR 65654 - In the Matter of: Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-10-26

    ... COMMISSION In the Matter of: Certain Integrated Circuits, Chipsets, and Products Containing Same Including... sale for importation, and the sale within the United States after importation of certain integrated circuits, chipsets, and products containing same including televisions, media players, and cameras...

  12. 75 FR 49524 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-08-13

    ... COMMISSION In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including... sale for importation, and the sale within the United States after importation of certain integrated circuits, chipsets, and products containing same including televisions, media players, and cameras...

  13. Exploitation of parallelism and ultraspeed integrated circuits in the next generation of distributed super signal processors

    SciTech Connect

    Gilbert, B.K.; Naused, B.A.; Hartley, S.M.; Vannurden, W.K.; Deming, R.

    1983-10-01

    The emerging application of gallium arsenide digital integrated circuits to signal processing problems will require the development of architectures tuned to its special characteristics. Chip design methods may be similar to those used for silicon very high-speed integrated circuit (VHSIC) components, but system design constraints will be unique to GAAS. 8 references.

  14. 76 FR 58041 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-09-19

    ... COMMISSION Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice... 1930, as amended, 19 U.S.C. 1337, on behalf of Renesas Electronics Corporation of Japan and 511... certain digital televisions containing integrated circuit devices and components thereof by reason...

  15. Advanced Studies of Integrable Systems.

    DTIC Science & Technology

    1986-12-18

    Fluctuations in Magnetized Plasmas (Phys. Fluids 27, 1169-75 (1984)] (coauthored with S.N. Antani) The nonlinear interactions of whistler waves with density... Dynamica Problems in Soliton Systems, pp 12-22. ed. S. Takeno, Springer-Verlag, NY (1985)]. S 11. Forced Integrable Systems - An Overview, D. J. Kaup...Kaup, P.J. Hansen, S. Roy Choudhury and Gary E. Thomas (accepted for publication in Phys. Fluids ). A singular perturbation method is used to solve this

  16. Advanced Wireless Integrated Navy Network

    DTIC Science & Technology

    2005-03-01

    Basing visualization of wireless technologies, Ad Hoc networks , network protocols, real-time resource allocation, Ultra Wideband (UWB) communications...4.1 TIP #1: Distributed MIMO UWB sensor networks incorporating software radio 67 4.2 TIP #2: Close-in UWB wireless with applications to Sea- Basing 68...4.3 TIP #3: Secure Ad Hoc Networks 73 4.4 TIP #4: Integration of Close-in UWB wireless with ESM crane for Sea Basing applications 75 5. FINANCIAL REPORT

  17. Tunable quantum interference in a 3D integrated circuit.

    PubMed

    Chaboyer, Zachary; Meany, Thomas; Helt, L G; Withford, Michael J; Steel, M J

    2015-04-27

    Integrated photonics promises solutions to questions of stability, complexity, and size in quantum optics. Advances in tunable and non-planar integrated platforms, such as laser-inscribed photonics, continue to bring the realisation of quantum advantages in computation and metrology ever closer, perhaps most easily seen in multi-path interferometry. Here we demonstrate control of two-photon interference in a chip-scale 3D multi-path interferometer, showing a reduced periodicity and enhanced visibility compared to single photon measurements. Observed non-classical visibilities are widely tunable, and explained well by theoretical predictions based on classical measurements. With these predictions we extract Fisher information approaching a theoretical maximum. Our results open a path to quantum enhanced phase measurements.

  18. Design structure for in-system redundant array repair in integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

    2008-11-25

    A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  19. Bulk CMOS VLSI Technology Studies. Part 5. The Design and Implementation of a High Speed Integrated Circuit Functional Tester.

    DTIC Science & Technology

    2014-09-26

    A,D-A1l-B 371 BULK CMOS VLSI TECHNOLOGY STUDIES PART 5 THE DESIGN AND J/2 IPLEMENTATION OF..(U) MISSISSIPPI STATE UNIV MISSISSIPPI STATE DEPT OF...SPEED INTEGRATED CIRCUIT FUNCTIONAL TESTER It Principal Investi-s tar J. Donald Trotter Associate Investigator Boyle Dwayne Robbins Mississippi State ...University Department of Electrical Engineering Mississippi State , Mississippi 39762 for Defense Advance Research Projects Agency 1400 Wilson Ave. Ci

  20. High-speed coherent silicon modulator module using photonic integrated circuits: from circuit design to packaged module

    NASA Astrophysics Data System (ADS)

    Bernabé, S.; Olivier, S.; Myko, A.; Fournier, M.; Blampey, B.; Abraham, A.; Menezo, S.; Hauden, J.; Mottet, A.; Frigui, K.; Ngoho, S.; Frigui, B.; Bila, S.; Marris-Morini, D.; Pérez-Galacho, D.; Brindel, P.; Charlet, G.

    2016-05-01

    Silicon photonics technology is an enabler for the integration of complex circuits on a single chip, for various optical link applications such as routing, optical networks on chip, short range links and long haul transmitters. Quadrature Phase Shift Keying (QPSK) transmitters is one of the typical circuits that can be achieved using silicon photonics integrated circuits. The achievement of 25GBd QPSK transmitter modules requires several building blocks to be optimized: the pn junction used to build a BPSK (Binary Shift Phase Keying) modulator, the RF access and the optical interconnect at the package level. In this paper, we describe the various design steps of a BPSK module and the related tests that are needed at every stage of the fabrication process.

  1. Advanced MOSFET technologies for high-speed circuits and EPROM

    SciTech Connect

    Wu, A.T.T.

    1987-01-01

    In the first part of the thesis, two novel source-side injection EPROM (SI-EPROM) devices capable of 5-volt only, high-speed programming are studied. Both devices are asymmetrical n-channel stacked-gate MOSFETs, each with a short weak gate-control channel region introduced close to the source. Under high gate bias, a strong-channel electric field for hot-electron generation is created in this local region even at a relatively low drain voltage. Furthermore, the gate oxide field in this region is highly favorable for hot-electron injection into the floating-gate. As a results, a programming speed of 10..mu..s at a drain voltage of 5 volts was demonstrated with one of the SI-EPROM devices fabricated. In the second part of the thesis, technology design considerations accompanying MOSFET scaling are studied for high-speed analog circuits and densely packed digital circuits. It is shown that for sub-micron technologies, especially those for CMOS, the drain/source junction capacitances dominate device parasitic capacitances in digital applications. A novel MOS device structure that employs the COO and DOO schemes is described.

  2. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  3. High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip

    PubMed Central

    Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

    2010-01-01

    A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

  4. High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip.

    PubMed

    Issadore, David; Franke, Thomas; Brown, Keith A; Hunt, Thomas P; Westervelt, Robert M

    2009-12-01

    A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm(2) in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip's surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications.

  5. Tunable hollow optical waveguides for photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Koyama, Fumio

    2004-10-01

    We propose a tunable hollow optical waveguide with a variable air core toward a new class of photonic integrated circuits. We present various unique features in hollow waveguides and the combination with microelectro-mechanical system (MEMS) will gives us widely tunable waveguide devices. We presente the design and fabrication of a tunable hollow waveguide with a variable air core. We describe the full-vectorial modeling of 3D and slab hollow waveguides with a variable air core, which is also supported by experiments. We demonstrated low loss and polarization insensitive waveguiding in an air core with optimized multilayer coating. The result shows a possibility of a large change of ~3% in propagation constant with a variable air core. We will present a wide variety of device applications based on hollow waveguides, which include tunable grating demultiplexers, variable attenuators, optical switches, tunable Bragg reflectors, tunable dispersion compensators and tunable lasers. The device structure can be formed by fully planar fabrication processes based on lithography and etching. The proposed concept may open up a new class of various tunable optical devices, which give us unique features of wide tunability, compact size and temperature insensitivity.

  6. An integrated modelling framework for neural circuits with multiple neuromodulators

    PubMed Central

    Vemana, Vinith

    2017-01-01

    Neuromodulators are endogenous neurochemicals that regulate biophysical and biochemical processes, which control brain function and behaviour, and are often the targets of neuropharmacological drugs. Neuromodulator effects are generally complex partly owing to the involvement of broad innervation, co-release of neuromodulators, complex intra- and extrasynaptic mechanism, existence of multiple receptor subtypes and high interconnectivity within the brain. In this work, we propose an efficient yet sufficiently realistic computational neural modelling framework to study some of these complex behaviours. Specifically, we propose a novel dynamical neural circuit model that integrates the effective neuromodulator-induced currents based on various experimental data (e.g. electrophysiology, neuropharmacology and voltammetry). The model can incorporate multiple interacting brain regions, including neuromodulator sources, simulate efficiently and easily extendable to large-scale brain models, e.g. for neuroimaging purposes. As an example, we model a network of mutually interacting neural populations in the lateral hypothalamus, dorsal raphe nucleus and locus coeruleus, which are major sources of neuromodulator orexin/hypocretin, serotonin and norepinephrine/noradrenaline, respectively, and which play significant roles in regulating many physiological functions. We demonstrate that such a model can provide predictions of systemic drug effects of the popular antidepressants (e.g. reuptake inhibitors), neuromodulator antagonists or their combinations. Finally, we developed user-friendly graphical user interface software for model simulation and visualization for both fundamental sciences and pharmacological studies. PMID:28100828

  7. Wireless Amperometric Neurochemical Monitoring Using an Integrated Telemetry Circuit

    PubMed Central

    Roham, Masoud; Halpern, Jeffrey M.; Martin, Heidi B.; Chiel, Hillel J.

    2015-01-01

    An integrated circuit for wireless real-time monitoring of neurochemical activity in the nervous system is described. The chip is capable of conducting high-resolution amperometric measurements in four settings of the input current. The chip architecture includes a first-order ΔΣ modulator (ΔΣM) and a frequency-shift-keyed (FSK) voltage-controlled oscillator (VCO) operating near 433 MHz. It is fabricated using the AMI 0.5 μm double-poly triple-metal n-well CMOS process, and requires only one off-chip component for operation. Measured dc current resolutions of ~250 fA, ~1.5 pA, ~4.5 pA, and ~17 pA were achieved for input currents in the range of ±5, ±37, ±150, and ±600 nA, respectively. The chip has been interfaced with a diamond-coated, quartz-insulated, microneedle, tungsten electrode, and successfully recorded dopamine concentration levels as low as 0.5 μM wirelessly over a transmission distance of ~0.5 m in flow injection analysis experiments. PMID:18990633

  8. Scheduling revisited workstations in integrated-circuit fabrication

    NASA Technical Reports Server (NTRS)

    Kline, Paul J.

    1992-01-01

    The cost of building new semiconductor wafer fabrication factories has grown rapidly, and a state-of-the-art fab may cost 250 million dollars or more. Obtaining an acceptable return on this investment requires high productivity from the fabrication facilities. This paper describes the Photo Dispatcher system which was developed to make machine-loading recommendations on a set of key fab machines. Dispatching policies that generally perform well in job shops (e.g., Shortest Remaining Processing Time) perform poorly for workstations such as photolithography which are visited several times by the same lot of silicon wafers. The Photo Dispatcher evaluates the history of workloads throughout the fab and identifies bottleneck areas. The scheduler then assigns priorities to lots depending on where they are headed after photolithography. These priorities are designed to avoid starving bottleneck workstations and to give preference to lots that are headed to areas where they can be processed with minimal waiting. Other factors considered by the scheduler to establish priorities are the nearness of a lot to the end of its process flow and the time that the lot has already been waiting in queue. Simulations that model the equipment and products in one of Texas Instrument's wafer fabs show the Photo Dispatcher can produce a 10 percent improvement in the time required to fabricate integrated circuits.

  9. An automatic detection system for flatness of integrated circuit pins

    NASA Astrophysics Data System (ADS)

    Deng, Shichao; Liu, Tiegen; Xiao, Zexin; Li, Xiuyan

    2008-12-01

    The flatness of pins is an important quality indicator for integrated circuit packaging. Almost all of the detection methods which are currently used can't be successful on efficiency and precision. In this system, the image of IC pins was captured by an properly optical systems and corresponding CCD sensor. To detect the edge of each pin, traditional algorithmic, such as Sobel operator and Roberts operator, have some disadvantages: the edge is too thick for system to accurately measure and the edge show directional character. An image segmentation and border extracting algorithm focus on the extreme of neighborhood image intensity change was adopted. The advantage of this algorithm was each pixel's neighborhood image intensity information was considered, so the algorithm is more suitable for accurately measure. After edge was extracted, how to identify the useful spots is cast as a binary classification task. The support vector machine (SVM) would be used to identify pin's spots. After proper image characteristics are obtained and a certain amount of training, SVM provides higher discrimination ratio to distinguish spots of the IC pins. To measure the flatness of pin, a particular line which can be identified easily should be put in the image as a baseline. Through calculating the distance between the pins spot and baseline, the flatness of pins is obtained accurately. In this system, the flatness of IC pins can be accurately and quickly measured, which is worthy of broad application prospect in IC packaging.

  10. PETRIC - A positron emission tomography readout integrated circuit

    SciTech Connect

    Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

    2000-11-05

    We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

  11. Novel immunoassay formats for integrated microfluidic circuits: diffusion immunoassays (DIA)

    NASA Astrophysics Data System (ADS)

    Weigl, Bernhard H.; Hatch, Anson; Kamholz, Andrew E.; Yager, Paul

    2000-03-01

    Novel designs of integrated fluidic microchips allow separations, chemical reactions, and calibration-free analytical measurements to be performed directly in very small quantities of complex samples such as whole blood and contaminated environmental samples. This technology lends itself to applications such as clinical diagnostics, including tumor marker screening, and environmental sensing in remote locations. Lab-on-a-Chip based systems offer many *advantages over traditional analytical devices: They consume extremely low volumes of both samples and reagents. Each chip is inexpensive and small. The sampling-to-result time is extremely short. They perform all analytical functions, including sampling, sample pretreatment, separation, dilution, and mixing steps, chemical reactions, and detection in an integrated microfluidic circuit. Lab-on-a-Chip systems enable the design of small, portable, rugged, low-cost, easy to use, yet extremely versatile and capable diagnostic instruments. In addition, fluids flowing in microchannels exhibit unique characteristics ('microfluidics'), which allow the design of analytical devices and assay formats that would not function on a macroscale. Existing Lab-on-a-chip technologies work very well for highly predictable and homogeneous samples common in genetic testing and drug discovery processes. One of the biggest challenges for current Labs-on-a-chip, however, is to perform analysis in the presence of the complexity and heterogeneity of actual samples such as whole blood or contaminated environmental samples. Micronics has developed a variety of Lab-on-a-Chip assays that can overcome those shortcomings. We will now present various types of novel Lab- on-a-Chip-based immunoassays, including the so-called Diffusion Immunoassays (DIA) that are based on the competitive laminar diffusion of analyte molecules and tracer molecules into a region of the chip containing antibodies that target the analyte molecules. Advantages of this

  12. Remote sensing of microbial volatile organic compounds with a bioluminescent bioreporter integrated circuit

    NASA Astrophysics Data System (ADS)

    Ripp, Steven A.; Daumer, Kathleen A.; Garland, Jay L.; Simpson, Michael L.; Sayler, Gary S.

    2004-03-01

    As a means towards advanced, early-warning detection of microbial growth in enclosed structures, we have constructed a bioluminescent bioreporter for the detection of the microbial volatile organic compound (MVOC) p-cymene. MVOCs are produced as metabolic by-products of bacteria and fungi and are detectable before any visible signs of microbial growth appear, thereby serving as very early indicators of potential biocontamination problems. The bioreporter, designated Pseudomonas putida UT93, contains a Vibrio fischeri luxCDABE gene fusion to a p-cymene/p-cumate inducible promoter. Exposure of strain UT93 to p-cymene from approximately 0.02 to 850 ppm produced self-generated bioluminescence in less than 1.5 hours. The bioreporter was also interfaced with an integrated circuit microluminometer to create a miniaturized hybrid sensor for remote monitoring of p-cymene signatures. This bioluminescent bioreporter integrated circuit (BBIC) device was capable of detecting fungal presence within approximately 3.5 hours of initial exposure to Penicillium roqueforti.

  13. Variable Time Base Integrator Circuit for Buffet Signal Measurements

    NASA Technical Reports Server (NTRS)

    Batts, Colossie N.

    1973-01-01

    A measurement circuit to obtain buffet data from wind tunnel models wherein a signal proportional to the average RMS value of buffet data is produced for subsequent recording. Feedback means are employed to suppress the D.C. portion of signals developed by the strain gages during dynamic testing. Automatic recording of gain settings of amplifiers employed in the circuit is also provided.

  14. Hot-carrier reliability assessment in CMOS digital integrated circuits

    NASA Astrophysics Data System (ADS)

    Jiang, Wenjie

    As VLSI technologies scale to deep submicron region, the DC device-based hot-carrier criterion is no longer practical for predicting hot-carrier reliability. Understanding the AC hot-carrier degradation of MOSFETs in actual circuit environment and their corresponding impact on circuit performance becomes increasingly important. The purpose of this research is to contribute to the assessment of hot-carrier reliability in digital CMOS circuits. Several critical issues that face circuit- level hot-carrier reliability evaluation are investigated, including AC hot-carrier test circuit design and characterization, AC hot-carrier degradation model calibration, the major factors determining circuit- level hot-carrier reliability, and the trade-offs between circuit-level hot-carrier lifetime underestimation and the amount of information required. In the area of experimental assessment of AC hot-carrier reliability, this thesis provides a comprehensive understanding of the key issues in designing and characterizing hot-carrier reliability test circuits. Test circuits that can provide realistic stress voltage waveforms, allow access to the internal device nodes, and provide insight about circuit performance sensitivity to hot-carrier damage are presented. New insights about previous test circuit designs are presented and additional test circuit designs are demonstrated. The design trade-offs between realistic waveform generation and internal device accessibility are analyzed and clarified. Recommendations for optimal test-circuit design for hot-carrier reliability characterization and model calibration are proposed. In the area of circuit-level hot-carrier reliability simulation, this thesis examines key issues involved in the calibration and verification of the hot-carrier degradation models that are used for AC hot-carrier reliability simulation. The need to account for the stress oxide-field dependence of the degradation model coefficients is demonstrated. The statistical

  15. High-resolution non-destructive three-dimensional imaging of integrated circuits.

    PubMed

    Holler, Mirko; Guizar-Sicairos, Manuel; Tsai, Esther H R; Dinapoli, Roberto; Müller, Elisabeth; Bunk, Oliver; Raabe, Jörg; Aeppli, Gabriel

    2017-03-15

    Modern nanoelectronics has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography-a high-resolution coherent diffractive imaging technique-can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques. Foreseeable developments in X-ray sources, optics and detectors, as well as adoption of an instrument geometry optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

  16. High-resolution non-destructive three-dimensional imaging of integrated circuits

    NASA Astrophysics Data System (ADS)

    Holler, Mirko; Guizar-Sicairos, Manuel; Tsai, Esther H. R.; Dinapoli, Roberto; Müller, Elisabeth; Bunk, Oliver; Raabe, Jörg; Aeppli, Gabriel

    2017-03-01

    Modern nanoelectronics has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography—a high-resolution coherent diffractive imaging technique—can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques. Foreseeable developments in X-ray sources, optics and detectors, as well as adoption of an instrument geometry optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

  17. Monolithic microwave integrated circuits for sensors, radar, and communications systems; Proceedings of the Meeting, Orlando, FL, Apr. 2-4, 1991

    NASA Technical Reports Server (NTRS)

    Leonard, Regis F. (Editor); Bhasin, Kul B. (Editor)

    1991-01-01

    Consideration is given to MMICs for airborne phased arrays, monolithic GaAs integrated circuit millimeter wave imaging sensors, accurate design of multiport low-noise MMICs up to 20 GHz, an ultralinear low-noise amplifier technology for space communications, variable-gain MMIC module for space applications, a high-efficiency dual-band power amplifier for radar applications, a high-density circuit approach for low-cost MMIC circuits, coplanar SIMMWIC circuits, recent advances in monolithic phased arrays, and system-level integrated circuit development for phased-array antenna applications. Consideration is also given to performance enhancement in future communications satellites with MMIC technology insertion, application of Ka-band MMIC technology for an Orbiter/ACTS communications experiment, a space-based millimeter wave debris tracking radar, low-noise high-yield octave-band feedback amplifiers to 20 GHz, quasi-optical MESFET VCOs, and a high-dynamic-range mixer using novel balun structure.

  18. Assembly and Integration of Superconductive Measurement Circuits for a Spaceflight Experiment

    NASA Technical Reports Server (NTRS)

    Wise, Stephanie A.; Hopson, Purnell, Jr.; Mau, Johnny C.

    1998-01-01

    Hybrid microelectronics containing both conventional electronic components and high-temperature superconductive films have been designed, fabricated, and tested. The devices operate from room temperature to 75K and perform d.c. four-probe resistance measurements on six superconductive specimens resident on each circuit. Four of these hybrid circuits were incorporated into the Materials In Devices As Superconductors (MIDAS) spaceflight experiment and evaluated over a 90-day period on the Mir space station. Prior to launch, comprehensive testing of the flight circuits was performed to determine the effects of thermal cycling, vibration loads, and long-term operation on circuit performance. This report describes the fabrication and assembly procedures used to produce the hybrid circuits, the techniques used to integrate the circuits into the MIDAS hardware system, and the results of pre-flight evaluations which verified circuit functionality.

  19. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    NASA Astrophysics Data System (ADS)

    Heck, Martijn J. R.

    2016-06-01

    Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  20. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    NASA Astrophysics Data System (ADS)

    Heck, Martijn J. R.

    2017-01-01

    Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  1. From The Lab to The Fab: Transistors to Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Huff, Howard R.

    2003-09-01

    Transistor action was experimentally observed by John Bardeen and Walter Brattain in n-type polycrystalline germanium on December 16, 1947 (and subsequently polycrystalline silicon) as a result of the judicious placement of gold-plated probe tips in nearby single crystal grains of the polycrystalline material (i.e., the point-contact semiconductor amplifier, often referred to as the point-contact transistor).The device configuration exploited the inversion layer as the channel through which most of the emitted (minority) carriers were transported from the emitter to the collector. The point-contact transistor was manufactured for ten years starting in 1951 by the Western Electric Division of AT&T. The a priori tuning of the point-contact transistor parameters, however, was not simple inasmuch as the device was dependent on the detailed surface structure and, therefore, very sensitive to humidity and temperature as well as exhibiting high noise levels. Accordingly, the devices differed significantly in their characteristics and electrical instabilities leading to "burnout" were not uncommon. With the implementation of crystalline semiconductor materials in the early 1950s, however, p-n junction (bulk) transistors began replacing the point-contact transistor, silicon began replacing germanium and the transfer of transistor technology from the lab to the lab accelerated. We shall review the historical route by which single crystalline materials were developed and the accompanying methodologies of transistor fabrication, leading to the onset of the Integrated Circuit (IC) era. Finally, highlights of the early years of the IC era will be reviewed from the 256 bit through the 4M DRAM. Elements of IC scaling and the role of Moore's Law in setting the parameters by which the IC industry's growth was monitored will be discussed.

  2. Radiation-hardened CMOS integrated circuit development for space nuclear power applications

    NASA Astrophysics Data System (ADS)

    Gover, J. E.; Gregory, B. L.

    Examination of the types of systems required for space nuclear power applications suggests a need for microelectronics technology that can function during and after exposure to radiation levels exceeding 1 x 10 to the 16th neutrons/sq cm and gamma ray doses in excess of 1 x 10 to the 7th rad(Si). Radiation-hardened Complimentary Metal Oxide Silicon and Silicon Nitride Oxide Silicon (SNOS) ICs presently in development at Sandia National Laboratories' Center for Radiation-Hardened Microelectronics satisfy these radiation requirements. Future integrated circuit development will further advance the radiation hardness capabilities while extending the IC technology to 32-bit enhanced microprocessors and 1-Mbyte SNOS EEPROM memories.

  3. Advanced Wireless Integrated Navy Network - AWINN

    DTIC Science & Technology

    2005-09-30

    progress report No. 3 on AWINN hardware and software configurations of smart, wideband, multi-function antennas , secure configurable platform, close-in...and Robust Networks Visualization of Wireless Technology and Ad Hoc Networks Technology Integration Projects The Advanced Antennas Group has completed a...comprehensive investigation of Wideband and Ultra Wideband (UWB) antennas for the AWINN projects. The investigation concluded that Tapered Slot

  4. Fully Integrated Biochip Platforms for Advanced Healthcare

    PubMed Central

    Carrara, Sandro; Ghoreishizadeh, Sara; Olivo, Jacopo; Taurino, Irene; Baj-Rossi, Camilla; Cavallini, Andrea; de Beeck, Maaike Op; Dehollain, Catherine; Burleson, Wayne; Moussy, Francis Gabriel; Guiseppi-Elie, Anthony; De Micheli, Giovanni

    2012-01-01

    Recent advances in microelectronics and biosensors are enabling developments of innovative biochips for advanced healthcare by providing fully integrated platforms for continuous monitoring of a large set of human disease biomarkers. Continuous monitoring of several human metabolites can be addressed by using fully integrated and minimally invasive devices located in the sub-cutis, typically in the peritoneal region. This extends the techniques of continuous monitoring of glucose currently being pursued with diabetic patients. However, several issues have to be considered in order to succeed in developing fully integrated and minimally invasive implantable devices. These innovative devices require a high-degree of integration, minimal invasive surgery, long-term biocompatibility, security and privacy in data transmission, high reliability, high reproducibility, high specificity, low detection limit and high sensitivity. Recent advances in the field have already proposed possible solutions for several of these issues. The aim of the present paper is to present a broad spectrum of recent results and to propose future directions of development in order to obtain fully implantable systems for the continuous monitoring of the human metabolism in advanced healthcare applications. PMID:23112644

  5. Advances in Current Rating Techniques for Flexible Printed Circuits

    NASA Technical Reports Server (NTRS)

    Hayes, Ron

    2014-01-01

    Twist Capsule Assemblies are power transfer devices commonly used in spacecraft mechanisms that require electrical signals to be passed across a rotating interface. Flexible printed circuits (flex tapes, see Figure 2) are used to carry the electrical signals in these devices. Determining the current rating for a given trace (conductor) size can be challenging. Because of the thermal conditions present in this environment the most appropriate approach is to assume that the only means by which heat is removed from the trace is thru the conductor itself, so that when the flex tape is long the temperature rise in the trace can be extreme. While this technique represents a worst-case thermal situation that yields conservative current ratings, this conservatism may lead to overly cautious designs when not all traces are used at their full rated capacity. A better understanding of how individual traces behave when they are not all in use is the goal of this research. In the testing done in support of this paper, a representative flex tape used for a flight Solar Array Drive Assembly (SADA) application was tested by energizing individual traces (conductors in the tape) in a vacuum chamber and the temperatures of the tape measured using both fine-gauge thermocouples and infrared thermographic imaging. We find that traditional derating schemes used for bundles of wires do not apply for the configuration tested. We also determine that single active traces located in the center of a flex tape operate at lower temperatures than those on the outside edges.

  6. Method for producing a hybridization of detector array and integrated circuit for readout

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Grunthaner, Frank J. (Inventor)

    1993-01-01

    A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

  7. Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

    PubMed

    Lu, Huihui; Lee, Jun Su; Zhao, Yan; Scarcella, Carmelo; Cardile, Paolo; Daly, Aidan; Ortsiefer, Markus; Carroll, Lee; O'Brien, Peter

    2016-07-25

    In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler.

  8. Advanced active quenching circuits for single-photon avalanche photodiodes

    NASA Astrophysics Data System (ADS)

    Stipčević, M.; Christensen, B. G.; Kwiat, P. G.; Gauthier, D. J.

    2016-05-01

    Commercial photon-counting modules, often based on actively quenched solid-state avalanche photodiode sensors, are used in wide variety of applications. Manufacturers characterize their detectors by specifying a small set of parameters, such as detection efficiency, dead time, dark counts rate, afterpulsing probability and single photon arrival time resolution (jitter), however they usually do not specify the conditions under which these parameters are constant or present a sufficient description. In this work, we present an in-depth analysis of the active quenching process and identify intrinsic limitations and engineering challenges. Based on that, we investigate the range of validity of the typical parameters used by two commercial detectors. We identify an additional set of imperfections that must be specified in order to sufficiently characterize the behavior of single-photon counting detectors in realistic applications. The additional imperfections include rate-dependence of the dead time, jitter, detection delay shift, and "twilighting." Also, the temporal distribution of afterpulsing and various artifacts of the electronics are important. We find that these additional non-ideal behaviors can lead to unexpected effects or strong deterioration of the system's performance. Specifically, we discuss implications of these new findings in a few applications in which single-photon detectors play a major role: the security of a quantum cryptographic protocol, the quality of single-photon-based random number generators and a few other applications. Finally, we describe an example of an optimized avalanche quenching circuit for a high-rate quantum key distribution system based on time-bin entangled photons.

  9. Probing Phase Transformations and Microstructural Evolutions at the Small Scales: Synchrotron X-ray Microdiffraction for Advanced Applications in 3D IC (Integrated Circuits) and Solar PV (Photovoltaic) Devices

    NASA Astrophysics Data System (ADS)

    Radchenko, I.; Tippabhotla, S. K.; Tamura, N.; Budiman, A. S.

    2016-12-01

    Synchrotron x-ray microdiffraction (μ {XRD}) allows characterization of a crystalline material in small, localized volumes. Phase composition, crystal orientation and strain can all be probed in few-second time scales. Crystalline changes over a large areas can be also probed in a reasonable amount of time with submicron spatial resolution. However, despite all the listed capabilities, μ {XRD} is mostly used to study pure materials but its application in actual device characterization is rather limited. This article will explore the recent developments of the μ {XRD} technique illustrated with its advanced applications in microelectronic devices and solar photovoltaic systems. Application of μ {XRD} in microelectronics will be illustrated by studying stress and microstructure evolution in Cu TSV (through silicon via) during and after annealing. The approach allowing study of the microstructural evolution in the solder joint of crystalline Si solar cells due to thermal cycling will be also demonstrated.

  10. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    ERIC Educational Resources Information Center

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  11. Low-power integrated-circuit driver for ferrite-memory word lines

    NASA Technical Reports Server (NTRS)

    Katz, S.

    1970-01-01

    Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

  12. Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

    PubMed Central

    Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

    2016-01-01

    The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (<100 Hz) with a capacitor of merely 6 fF, which is hosted in an FG metal-oxide-semiconductor field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

  13. Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator.

    PubMed

    Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

    2016-01-01

    The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (<100 Hz) with a capacitor of merely 6 fF, which is hosted in an FG metal-oxide-semiconductor field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex.

  14. Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

    NASA Technical Reports Server (NTRS)

    Alt, Shannon

    2016-01-01

    Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

  15. SEMICONDUCTOR INTEGRATED CIRCUITS: A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth

    NASA Astrophysics Data System (ADS)

    Tao, Tong; Baoyong, Chi; Ziqiang, Wang; Ying, Zhang; Hanjun, Jiang; Zhihua, Wang

    2010-05-01

    A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth in 0.35 μm CMOS is presented. The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF). The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption, the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application. Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN, 8.9 mW for WCDMA and only 6.5 mW for Bluetooth, all with a 3 V power supply. The analog baseband circuit could provide -10 to +40 dB variable gain, third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth, fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN, respectively.

  16. Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liang-Yu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2016-01-01

    This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over approximately 1-micrometer scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

  17. Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2016-01-01

    This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

  18. Integrating Advanced Molecular Technologies into Public Health.

    PubMed

    Gwinn, Marta; MacCannell, Duncan R; Khabbaz, Rima F

    2017-03-01

    Advances in laboratory and information technologies are transforming public health microbiology. High-throughput genome sequencing and bioinformatics are enhancing our ability to investigate and control outbreaks, detect emerging infectious diseases, develop vaccines, and combat antimicrobial resistance, all with increased accuracy, timeliness, and efficiency. The Advanced Molecular Detection (AMD) initiative has allowed the Centers for Disease Control and Prevention (CDC) to provide leadership and coordination in integrating new technologies into routine practice throughout the U.S. public health laboratory system. Collaboration and partnerships are the key to navigating this transition and to leveraging the next generation of methods and tools most effectively for public health.

  19. 77 FR 67833 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-11-14

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission Determination Not To Review an Initial Determination Terminating the Investigation in its Entirety AGENCY:...

  20. 77 FR 40381 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-07-09

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice of Commission Determination Not To Review an Initial Determination Terminating the Investigation...

  1. An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

    ERIC Educational Resources Information Center

    Muyskens, Mark A.

    1997-01-01

    Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

  2. A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

    PubMed

    Close, Gael F; Yasuda, Shinichi; Paul, Bipul; Fujita, Shinobu; Wong, H-S Philip

    2008-02-01

    Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

  3. RNA signal amplifier circuit with integrated fluorescence output.

    PubMed

    Akter, Farhima; Yokobayashi, Yohei

    2015-05-15

    We designed an in vitro signal amplification circuit that takes a short RNA input that catalytically activates the Spinach RNA aptamer to produce a fluorescent output. The circuit consists of three RNA strands: an internally blocked Spinach aptamer, a fuel strand, and an input strand (catalyst), as well as the Spinach aptamer ligand 3,5-difluoro-4-hydroxylbenzylidene imidazolinone (DFHBI). The input strand initially displaces the internal inhibitory strand to activate the fluorescent aptamer while exposing a toehold to which the fuel strand can bind to further displace and recycle the input strand. Under a favorable condition, one input strand was able to activate up to five molecules of the internally blocked Spinach aptamer in 185 min at 30 °C. The simple RNA circuit reported here serves as a model for catalytic activation of arbitrary RNA effectors by chemical triggers.

  4. The circuit of polychromator for Experimental Advanced Superconducting Tokamak edge Thomson scattering diagnostic

    SciTech Connect

    Zang, Qing; Zhao, Junyu; Chen, Hui; Li, Fengjuan; Hsieh, C. L.

    2013-09-15

    The detector circuit is the core component of filter polychromator which is used for scattering light analysis in Thomson scattering diagnostic, and is responsible for the precision and stability of a system. High signal-to-noise and stability are primary requirements for the diagnostic. Recently, an upgraded detector circuit for weak light detecting in Experimental Advanced Superconducting Tokamak (EAST) edge Thomson scattering system has been designed, which can be used for the measurement of large electron temperature (T{sub e}) gradient and low electron density (n{sub e}). In this new circuit, a thermoelectric-cooled avalanche photodiode with the aid circuit is involved for increasing stability and enhancing signal-to-noise ratio (SNR), especially the circuit will never be influenced by ambient temperature. These features are expected to improve the accuracy of EAST Thomson diagnostic dramatically. Related mechanical construction of the circuit is redesigned as well for heat-sinking and installation. All parameters are optimized, and SNR is dramatically improved. The number of minimum detectable photons is only 10.

  5. Noise analysis for infrared focal plane arrays CMOS readout integrated circuit

    NASA Astrophysics Data System (ADS)

    Lin, Jiamu; Ding, Ruijun; Chen, Honglei; Shen, Xiao; Liu, Fei

    2008-12-01

    With the development of the infrared focal plane detectors, the internal noises in the infrared focal plane arrays (IRFPAs) CMOS readout integrated circuit gradually became an important factor of the development of the IRFPAs. The internal noises in IRFPAs CMOS readout integrated circuit are researched in this work. Part of the motivation for this work is to analyze the mechanism and influence of the internal noises in readout integrated circuit. And according to the signal transporting process, many kinds of internal noises are analyzed. According to the results of theory analysis, it is shown that 1/f noise, KTC noise and pulse switch noise have greater amplitude in frequency domain. These noises have seriously affected the performance of output signal. Also this work has frequency test on the signals of a readout integrated circuit chip which is using DI readout mode. After analyzing the frequency test results, it is shown that 1/f noises and pulse switch noises are the main components of the internal noises in IRFPAS CMOS readout integrated circuit and they are the noises which give a major impact to the output signal. In accordance with the type of noise, some design methods for noise suppression are put forward. And after the simulation of these methods with EDA software, the results show that noises have been reduced. The results of this work gave the referenced gist for improving the noise suppression design of IRFPAs CMOS readout integrated circuit.

  6. Computer-aided prediction of high-frequency performance limits in silicon bipolar integrated circuits

    NASA Technical Reports Server (NTRS)

    Burns, J. L.; Choma, J., Jr.

    1982-01-01

    A circuit model for an existing silicon integrated bipolar junction transistor (IBJT) is used to evaluate presently achievable high frequency circuit performance. The relationship between circuit model and processing parameters are semi-quantitatively explored to make predictions on the frequency response, which can be achieved through realistic device fabrication modifications. A new figure of merit is introduced, which is defined as the signal frequency at which an integrated bipolar junction transistor can deliver a power gain of G. The most sensitive parameter influencing attainable high frequency IBJT performance is base resistance.

  7. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicron devices and integrated circuits using aligned nanotubes

    NASA Astrophysics Data System (ADS)

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Zhou, Chongwu

    2009-03-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration / assembly challenge for future beyond-silicon nanoelectronics. We report our recent advance on full wafer-scale processing of massively aligned carbon nanotube arrays for high performance submicron channel transistors and integrated nanotube circuits, including the following essential components. 1) The massively highly aligned nanotubes were successfully grown on 4 inch quartz and sapphire wafers via meticulous temperature control, and then transferred onto Si/SiO2 wafers using our facile transfer printing method. 2) Wafer-scale device fabrication was performed on 4 inch Si/SiO2 wafer to yield submicron channel transistors and circuits with high on-current density ˜ 20 μA/μm and good on/off ratio. 3) Chemical doping methods were successfully demonstrated to get CMOS inverters with a gain ˜5. 4) Defect-tolerant circuit design for NAND and NOR was proposed and demonstrated to guarantee the correct operation of logic circuit, regardless of the presence of mis-aligned or mis-positioned nanotubes.

  8. Integrated-Circuit Controller For Brushless dc Motor

    NASA Technical Reports Server (NTRS)

    Le, Dong Tuan

    1994-01-01

    Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

  9. Memory-Based Structured Application Specific Integrated Circuit (ASIC) Study

    DTIC Science & Technology

    2008-10-01

    phase switching technique," Electronics Letters, vol. 37, no. 14, pp. 875-877, Jul 2001. [10] W. Dally and B. Towles , Principles and Practices of...and A. Alvandpour, "A six-port 57gb/s double-pumped nonblocking router core," VLSI Circuits, 2005. Digest of Technical Papers . 2005 Symposium on, pp

  10. Active parallel redundancy for electronic integrator-type control circuits

    NASA Technical Reports Server (NTRS)

    Peterson, R. A.

    1971-01-01

    Circuit extends concept of redundant feedback control from type-0 to type-1 control systems. Inactive channels are slaves to the active channel, if latter fails, it is rejected and slave channel is activated. High reliability and elimination of single-component catastrophic failure are important in closed-loop control systems.

  11. Process development of beam-lead silicon-gate COS/MOS integrated circuits

    NASA Technical Reports Server (NTRS)

    Baptiste, B.; Boesenberg, W.

    1974-01-01

    Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

  12. Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

    NASA Technical Reports Server (NTRS)

    Burns, Bradley M.; Blalock, Norman N.

    2010-01-01

    A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the

  13. Development of plasmonic isolator for integration into photonic integrated circuits (Presentation Recording)

    NASA Astrophysics Data System (ADS)

    Zayets, Vadym; Saito, Hidekazu; Ando, Koji; Yuasa, Shinji

    2015-09-01

    An optical isolator is an important component of an optical network. At present, there is a significant commercial demand for an optical isolator, which can be integrated into the Photonic Integrated Circuits (PIC). A new design of an integrated optical isolator, which utilizes unique non-reciprocal properties of surface plasmons, has been proposed [1]. The main obstacle for a practical realization of the proposed design is a substantial propagation loss of the surface plasmons in structures containing a ferromagnetic metal. The reduction of the propagation loss of a surface plasmon is the key to make the plasmonic isolator competitive with other designs of the integrated isolator. We studied experimentally optical and magneto-optical properties of a Fe plasmonic waveguide integrated with an AlGaAs rib waveguides and a Co plasmonic waveguide integrated with Si nanowire waveguides. It was demonstrated experimentally that by utilizing a double-dielectric plasmonic waveguide it is possible to reduce significantly the optical loss in a plasmonic waveguide. For Fe/SiO2/AlGaAs double-dielectric plasmonic waveguide the low optical loss of 0.03 dB/um is obtained. As far as we know at present it is a lowest optical loss demonstrated for a plasmon propagating at a surface of a ferromagnetic metal. For Co/Ti2O3/SiO2 double-dielectric plasmonic waveguide integrated with a Si nanowire waveguide on a Si substrate the optical loss of 0.7 dB/um was demonstrated. The designs of the plasmonic isolator utilizing a ring resonator or a non-reciprocal coupler were studied. [1] V. Zayets, H. Saito, S. Yuasa, and K. Ando,, Materials 5, 857 (2012).

  14. The stabilized supralinear network: a unifying circuit motif underlying multi-input integration in sensory cortex.

    PubMed

    Rubin, Daniel B; Van Hooser, Stephen D; Miller, Kenneth D

    2015-01-21

    Neurons in sensory cortex integrate multiple influences to parse objects and support perception. Across multiple cortical areas, integration is characterized by two neuronal response properties: (1) surround suppression--modulatory contextual stimuli suppress responses to driving stimuli; and (2) "normalization"--responses to multiple driving stimuli add sublinearly. These depend on input strength: for weak driving stimuli, contextual influences facilitate or more weakly suppress and summation becomes linear or supralinear. Understanding the circuit operations underlying integration is critical to understanding cortical function and disease. We present a simple, general theory. A wealth of integrative properties, including the above, emerge robustly from four cortical circuit properties: (1) supralinear neuronal input/output functions; (2) sufficiently strong recurrent excitation; (3) feedback inhibition; and (4) simple spatial properties of intracortical connections. Integrative properties emerge dynamically as circuit properties, with excitatory and inhibitory neurons showing similar behaviors. In new recordings in visual cortex, we confirm key model predictions.

  15. Buffer direct injection readout integrated circuit design for dual band infrared focal plane array detector

    NASA Astrophysics Data System (ADS)

    Sun, Tai-Ping; Lu, Yi-Chuan; Shieh, Hsiu-Li; Tang, Shiang-Feng; Lin, Wen-Jen

    2013-05-01

    This paper proposes dual-mode buffer direct injection (BDI) and direct injection (DI) readout circuit design. The DI readout circuit has the advantage of being a simple circuit, requiring a small layout area, and low power consumption. The internal resistance of the photodetector will affect the photocurrent injection efficiency. We used a buffer amplifier to design the BDI readout circuit since it would reduce the input impedance and raise the injection efficiency. This paper will discuss and analyze the power consumption, injection efficiency, layout area, and circuit noise. The circuit is simulated using a TSMC 0.35 um Mixed Signal 2P4M CMOS 5 V process. The dimension of the pixel area is 30×30 μm. We have designed a 10×8 array for the readout circuit of the interlaced columns. The input current ranges from 1 nA to 10 nA, when the measurement current is 10 pA to 10 nA. The integration time was varied. The circuit output swing was 2 V. The total root mean square noise voltage was 4.84 mV. The signal to noise ratio was 52 dB, and the full chip circuit power consumption was 9.94 mW.

  16. Processing, Fabrication, and Demonstration of HTS Integrated Microwave Circuits

    DTIC Science & Technology

    1993-10-24

    circuit design software Touchstone and later adjusted using the electromagnetic analysis software emTm, from Sonnet . rhe analyzed performance is shown in...Design and Sonnet analysis of the tandem coupler performance. !5 previously reported in our interim report covering the period between July 1991 and...explained in our last quarterly report. A design procedure is being developed in which Sonnet is included in the design loop. Although the procedure is not

  17. Integrating Optogenetic and Pharmacological Approaches to Study Neural Circuit Function: Current Applications and Future Directions

    PubMed Central

    Mason, Alex O.

    2013-01-01

    Optogenetic strategies to control genetically distinct populations of neurons with light have been rapidly evolving and widely adopted by the neuroscience community as one of the most important tool sets to study neural circuit function. Although optogenetics have already reshaped neuroscience by allowing for more precise control of circuit function compared with traditional techniques, current limitations of these approaches should be considered. Here, we discuss several strategies that combine optogenetic and contemporary pharmacological techniques to further increase the specificity of neural circuit manipulation. We also discuss recent advances that allow for the selective modulation of cellular function and gene expression with light. In addition, we outline a novel application of optogenetic circuit analysis for causally addressing the role of pathway-specific neural activity in mediating alterations in postsynaptic transcriptional processing in genetically defined neurons. By determining how optogenetic activation of specific neural circuits causally contributes to alterations in gene expression in a high-throughput fashion, novel biologic targets for future pharmacological intervention may be uncovered. Lastly, extending this experimental pipeline to selectively target pharmacotherapies to genetically defined neuronal populations or circuits will not only provide more selective control of neural circuits, but also may lead to the development of neural circuit specific pharmacological therapeutics. PMID:23319548

  18. Fabrication of multijunction high voltage concentrator solar cells by integrated circuit technology

    NASA Technical Reports Server (NTRS)

    Valco, G. J.; Kapoor, V. J.; Evans, J. C., Jr.; Chai, A.-T.

    1981-01-01

    Standard integrated circuit technology has been developed for the design and fabrication of planar multijunction (PMJ) solar cell chips. Each 1 cm x 1 cm solar chip consisted of six n(+)/p, back contacted, internally series interconnected unit cells. These high open circuit voltage solar cells were fabricated on 2 ohm-cm, p-type 75 microns thick, silicon substrates. A five photomask level process employing contact photolithography was used to pattern for boron diffusions, phorphorus diffusions, and contact metallization. Fabricated devices demonstrated an open circuit voltage of 3.6 volts and a short circuit current of 90 mA at 80 AMl suns. An equivalent circuit model of the planar multi-junction solar cell was developed.

  19. Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

    NASA Technical Reports Server (NTRS)

    Buehler, M. G. (Inventor)

    1985-01-01

    An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

  20. Advanced integrated life support system update

    NASA Technical Reports Server (NTRS)

    Whitley, Phillip E.

    1994-01-01

    The Advanced Integrated Life Support System Program (AILSS) is an advanced development effort to integrate the life support and protection requirements using the U.S. Navy's fighter/attack mission as a starting point. The goal of AILSS is to optimally mate protection from altitude, acceleration, chemical/biological agent, thermal environment (hot, cold, and cold water immersion) stress as well as mission enhancement through improved restraint, night vision, and head-mounted reticules and displays to ensure mission capability. The primary emphasis to date has been to establish garment design requirements and tradeoffs for protection. Here the garment and the human interface are treated as a system. Twelve state-off-the-art concepts from government and industry were evaluated for design versus performance. On the basis of a combination of centrifuge, thermal manikin data, thermal modeling, and mobility studies, some key design parameters have been determined. Future efforts will concentrate on the integration of protection through garment design and the use of a single layer, multiple function concept to streamline the garment system.

  1. System-Level Integrated Circuit (SLIC) Technology Development for Phased Array Antenna Applications

    NASA Technical Reports Server (NTRS)

    Windyka, John A.; Zablocki, Ed G.

    1997-01-01

    This report documents the efforts and progress in developing a 'system-level' integrated circuit, or SLIC, for application in advanced phased array antenna systems. The SLIC combines radio-frequency (RF) microelectronics, digital and analog support circuitry, and photonic interfaces into a single micro-hybrid assembly. Together, these technologies provide not only the amplitude and phase control necessary for electronic beam steering in the phased array, but also add thermally-compensated automatic gain control, health and status feedback, bias regulation, and reduced interconnect complexity. All circuitry is integrated into a compact, multilayer structure configured for use as a two-by-four element phased array module, operating at 20 Gigahertz, using a Microwave High-Density Interconnect (MHDI) process. The resultant hardware is constructed without conventional wirebonds, maintains tight inter-element spacing, and leads toward low-cost mass production. The measured performances and development issues associated with both the two-by-four element module and the constituent elements are presented. Additionally, a section of the report describes alternative architectures and applications supported by the SLIC electronics. Test results show excellent yield and performance of RF circuitry and full automatic gain control for multiple, independent channels. Digital control function, while suffering from lower manufacturing yield, also proved successful.

  2. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    SciTech Connect

    Yin, Lan; Harburg, Daniel V.; Rogers, John A.; Bozler, Carl; Omenetto, Fiorenzo

    2015-01-05

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  3. Technology characteristics and concerns arising in the design and fabrication of an entire signal processor using gallium arsenide integrated circuits

    NASA Astrophysics Data System (ADS)

    Naused, Barbara A.; Samson, Mark L.; Schwab, Daniel J.; Gilbert, Barry K.

    Various GaAs transistor and gate technologies that have been developed since 1980 are analyzed. The characteristics of GaAs logic gates and ICs and the buffered FET logic, Shottky diode FET logic, direct coupled FET logic, and heterojunction integrated injection logic used to implement GaAs gate arrays of LSI complexity are described. The use of digital GaAs in a complex target signal processor, the Advanced Onboard Signal Processor (AOSP), is studied. Data from the testing of GaAs components for the AOSP at the wafer probe, package, and assembled circuit board levels are examined.

  4. Plasmonic and electronic device-based integrated circuits and their characteristics

    NASA Astrophysics Data System (ADS)

    Sakai, H.; Okahisa, S.; Nakayama, Y.; Nakayama, K.; Fukuhara, M.; Kimura, Y.; Ishii, Y.; Fukuda, M.

    2016-11-01

    This paper presents a plasmonic circuit that has been monolithically integrated with electronic devices on a silicon substrate and then discusses the concept behind this circuit. To form the proposed circuit, two plasmonic waveguides and a detector are integrated with metal-oxide-semiconductor field-effect transistors (MOSFETs) on the substrate. In the circuit, intensity signals or coherent plasmonic signals are generated by coherent light at an operating wavelength at which silicon is transparent, and these signals propagate along the waveguides before they are converted into electrical signals by the detector. These electrical intensity and coherent signals then drive the MOSFETs during both DC and AC operation. The measured performances of the devices indicate that surface plasmon polaritons propagate on the metal surface at the speed of light and drive the electronic devices without any absorption in the silicon.

  5. Guided Wave Interactions in Millimeter-Wave Integrated Circuits.

    DTIC Science & Technology

    1988-01-15

    on a sustrate which is in turn inserted into a TEI{) waveguide along its E-plane. One end of the stub is connected to the top or bottom wall of the... waveguide whereas another end does not reach the opposite wall. This element can be used as a transition from a waveguide to a printed circuit and as a...touching E-plane fin is located in the waveguide below cutoff. With this configuration, an evanescent mode filter can be formed. The evanescent

  6. Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.

    PubMed

    LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J

    2014-06-02

    We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.

  7. External electro-optic probing of millimeter-wave integrated circuits

    NASA Technical Reports Server (NTRS)

    Whitaker, J. F.; Valdmanis, J. A.; Jackson, T. A.; Bhasin, K. B.; Romanofsky, Robert R.; Mourou, G. A.

    1989-01-01

    An external, noncontact electro-optic measurement system, designed to operate at the wafer level with conventional wafer probing equipment and without any special circuit preparation, has been developed. Measurements have demonstrated the system's ability to probe continuous and pulsed signals on microwave integrated circuits on arbitrary substrates with excellent spatial resolution. Experimental measurements on a variety of digital and analog circuits, including a GaAs selectively-doped heterostructure transistor prescaler, an NMOS silicon multiplexer, and a GaAs power amplifier MMIC are reported.

  8. Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

    NASA Technical Reports Server (NTRS)

    Woo, D. S.

    1980-01-01

    The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

  9. A circuit method to integrate metamaterial and graphene in absorber design

    NASA Astrophysics Data System (ADS)

    Wang, Zuojia; Zhou, Min; Lin, Xiao; Liu, Huixia; Wang, Huaping; Yu, Faxin; Lin, Shisheng; Li, Erping; Chen, Hongsheng

    2014-10-01

    We theoretically investigate a circuit analog approach to integrate graphene and metamaterial in electromagnetic wave absorber design. In multilayer graphene-metamaterial (GM) absorbers, ultrathin metamaterial elements are theoretically modeled as equivalent loads which attached to the junctions between two transmission lines. Combining with the benefits of tunable chemical potential in graphene, an optimized GM absorber is proposed as a proof of the circuit method. Numerical simulation results demonstrate the effectiveness of the circuit analytical model. The operating frequency of the GM absorber can be varied in terahertz frequency, indicating the potential applications of the GM absorber in sensors, modulators, and filters.

  10. The single-event effect evaluation technology for nano integrated circuits

    NASA Astrophysics Data System (ADS)

    Hongchao, Zheng; Yuanfu, Zhao; Suge, Yue; Long, Fan; Shougang, Du; Maoxin, Chen; Chunqing, Yu

    2015-11-01

    Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test technology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present understanding of the mechanisms for SEEs, which have been well verified experimentally.

  11. PECASE: All-Optical Photonic Integrated Circuits in Silicon

    DTIC Science & Technology

    2011-01-14

    elements for dense integrated photonics . Figure 33 The cross sections of the simulated electric energy distributions of (a) the 1st and (b) the 2nd...Soltani, and A. Adibi, “High Quality Planar Silicon Nitride Microdisk Resonators for Integrated Photonics in the Visible Wavelength Range,” Optics...Soltani, and A. Adibi, “High quality planar silicon nitride microdisk resonators for integrated photonics in the visible wavelength range,” Opt. Express

  12. Advanced Integrated Optical Signal Processing Components.

    NASA Astrophysics Data System (ADS)

    Rastani, Kasra

    This research was aimed at the development of advanced integrated optical components suitable for devices capable of processing multi-dimensional inputs. In such processors, densely packed waveguide arrays with low crosstalk are needed to provide dissection of the information that has been partially processed. Waveguide arrays also expand the information in the plane of the processor while maintaining its coherence. Rib waveguide arrays with low loss, high mode confinement and highly uniform surface quality (660 elements, 8 μm wide, 1 μm high, and 1 cm long with 2 mu m separations) were fabricated on LiNbO _3 substrates through the ion beam milling technique. A novel feature of the multi-dimensional IO processor architecture proposed herein is the implementation of large area uniform outcoupling (with low to moderate outcoupling efficiencies) from rib waveguide arrays in order to access the third dimension of the processor structure. As a means of outcoupling, uniform surface gratings (2 μm and 4 μm grating periods, 0.05 μm high and 1 mm long) with low outcoupling efficiencies (of approximately 2-18%/mm) were fabricated on the nonuniform surface of the rib waveguide arrays. As a practical technique of modulating the low outcoupling efficiencies of the surface gratings, it was proposed to alter the period of the grating as a function of position along each waveguide. Large aperture (2.5 mm) integrated lenses with short positive focal lengths (1.2-2.5 cm) were developed through a modification of the titanium-indiffused proton exchanged (TIPE) technique. Such integrated lenses were fabricated by increasing the refractive index of the slab waveguides by the TIPE process while maintaining the refractive index of the lenses at the lower level of Ti:LiNbO _3 waveguide. By means of curvature reversal of the integrated lenses, positive focal length lenses have been fabricated while providing high mode confinement for the slab waveguide. The above elements performed as

  13. Monolithical integration of polymer-based microfluidic structures on application-specific integrated circuits

    NASA Astrophysics Data System (ADS)

    Chemnitz, Steffen; Schafer, Heiko; Schumacher, Stephanie; Koziy, Volodymyr; Fischer, Alexander; Meixner, Alfred J.; Ehrhardt, Dietmar; Bohm, Markus

    2003-04-01

    In this paper, a concept for a monolithically integrated chemical lab on microchip is presented. It contains an ASIC (Application Specific Integrated Circuit), an interface to the polymer based microfluidic layer and a Pyrex glass cap. The top metal layer of the ASIC is etched off and replaced by a double layer metallization, more suitable to microfluidic and electrophoresis systems. The metallization consists of an approximately 50 nm gold layer and a 10 nm chromium layer, acting as adhesion promoter. A necessary prerequisite is a planarized ASIC topography. SU-8 is used to serve as microfluidic structure because of its excellent aspect ratio. This polymer layer contains reservoirs, channels, mixers and electrokinetic micro pumps. The typical channel cross section is 10μm"10μm. First experimental results on a microfluidic pump, consisting of pairs of interdigitated electrodes on the bottom of the channel and without any moving parts show a flow of up to 50μm per second for low AC-voltages in the range of 5 V for aqueous fluids. The microfluidic system is irreversibly sealed with a 150μm thick Pyrex glass plate bonded to the SU-8-layer, supported by oxygen plasma. Due to capillary forces and surfaces properties of the walls the system is self-priming. The technologies for the fabrication of the microfluidic system and the preparation of the interface between the lab layer and the ASIC are presented.

  14. Dictionary-based image reconstruction for superresolution in integrated circuit imaging.

    PubMed

    Cilingiroglu, T Berkin; Uyar, Aydan; Tuysuzoglu, Ahmet; Karl, W Clem; Konrad, Janusz; Goldberg, Bennett B; Ünlü, M Selim

    2015-06-01

    Resolution improvement through signal processing techniques for integrated circuit imaging is becoming more crucial as the rapid decrease in integrated circuit dimensions continues. Although there is a significant effort to push the limits of optical resolution for backside fault analysis through the use of solid immersion lenses, higher order laser beams, and beam apodization, signal processing techniques are required for additional improvement. In this work, we propose a sparse image reconstruction framework which couples overcomplete dictionary-based representation with a physics-based forward model to improve resolution and localization accuracy in high numerical aperture confocal microscopy systems for backside optical integrated circuit analysis. The effectiveness of the framework is demonstrated on experimental data.

  15. Method and apparatus for in-system redundant array repair on integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

    2008-07-08

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  16. Method and apparatus for in-system redundant array repair on integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

    2008-07-29

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  17. Method and apparatus for in-system redundant array repair on integrated circuits

    DOEpatents

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

    2007-12-18

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  18. Selective Processing Techniques for Electronics and Opto-Electronic Applications: Quantum-Well Devices and Integrated Optic Circuits

    DTIC Science & Technology

    1993-02-10

    new technology is to have sufficient control of processing to *- describable by an appropriate elecromagnetic model . build useful devices. For example...3. W aveguide Modulators .................................. 7 B. Integrated Optical Device and Circuit Modeling ... ................... .. 10 C...following categories: A. Integrated Optical Devices and Technology B. Integrated Optical Device and Circuit Modeling C. Cryogenic Etching for Low

  19. A compact picosecond pulsed laser source using a fully integrated CMOS driver circuit

    NASA Astrophysics Data System (ADS)

    He, Yuting; Li, Yuhua; Yadid-Pecht, Orly

    2016-03-01

    Picosecond pulsed laser source have applications in areas such as optical communications, biomedical imaging and supercontinuum generation. Direct modulation of a laser diode with ultrashort current pulses offers a compact and efficient approach to generate picosecond laser pulses. A fully integrated complementary metaloxide- semiconductor (CMOS) driver circuit is designed and applied to operate a 4 GHz distributed feedback laser (DFB). The CMOS driver circuit combines sub-circuits including a voltage-controlled ring oscillator, a voltagecontrolled delay line, an exclusive-or (XOR) circuit and a current source circuit. Ultrashort current pulses are generated by the XOR circuit when the delayed square wave is XOR'ed with the original square wave from the on-chip oscillator. Circuit post-layout simulation shows that output current pulses injected into an equivalent circuit load of the laser have a pulse full width at half maximum (FWHM) of 200 ps, a peak current of 80 mA and a repetition rate of 5.8 MHz. This driver circuit is designed in a 0.13 μm CMOS process and taped out on a 0.3 mm2 chip area. This CMOS chip is packaged and interconnected with the laser diode on a printed circuit board (PCB). The optical output waveform from the laser source is captured by a 5 GHz bandwidth photodiode and an 8 GHz bandwidth oscilloscope. Measured results show that the proposed laser source can output light pulses with a pulse FWHM of 151 ps, a peak power of 6.4 mW (55 mA laser peak forward current) and a repetition rate of 5.3 MHz.

  20. Electromagnetic Interactions in High-Speed Integrated Electronic Circuits

    DTIC Science & Technology

    1989-03-31

    Sommerfeld integrals using the fast Fourier transform ," Nat. Radio Science (USNC/URSI) Meeting, University of Colorado, Boulder, CO, digest p. 73, Jan...p. 180, Jan. 1989. 3 [12] B. Drachman, M. Cloud, and D. Nyquist, "Accurate evaluation of Sommerfeld integrals using the fast Fourier transform ," to...leads to the transform -domain Hertz potential maintained by currents immersed in the tri-layered environment. The space-domain electric field is recovered

  1. Integrated silicon and silicon nitride photonic circuits on flexible substrates.

    PubMed

    Chen, Yu; Li, Mo

    2014-06-15

    Flexible integrated photonic devices based on crystalline materials on plastic substrates have a promising potential in many unconventional applications. In this Letter, we demonstrate a fully integrated photonic system including ring resonators and grating couplers, based on both crystalline silicon and silicon nitride, on flexible plastic substrate by using the stamping-transfer method. A high yield has been achieved by a simple, yet reliable transfer method without significant performance degradation.

  2. Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits

    DOEpatents

    Campbell, A.N.; Anderson, R.E.; Cole, E.I. Jr.

    1995-11-07

    A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits are disclosed. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits. 17 figs.

  3. Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits

    DOEpatents

    Campbell, Ann. N.; Anderson, Richard E.; Cole, Jr., Edward I.

    1995-01-01

    A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits.

  4. Compact beam splitters with deep gratings for miniature photonic integrated circuits: design and implementation aspects.

    PubMed

    Chen, Chin-Hui; Klamkin, Jonathan; Nicholes, Steven C; Johansson, Leif A; Bowers, John E; Coldren, Larry A

    2009-09-01

    We present an extensive study of an ultracompact grating-based beam splitter suitable for photonic integrated circuits (PICs) that have stringent density requirements. The 10 microm long beam splitter exhibits equal splitting, low insertion loss, and also provides a high extinction ratio in an integrated coherent balanced receiver. We further present the design strategies for avoiding mode distortion in the beam splitter and discuss optimization of the widths of the detectors to improve insertion loss and extinction ratio of the coherent receiver circuit. In our study, we show that the grating-based beam splitter is a competitive technology having low fabrication complexity for ultracompact PICs.

  5. Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

    SciTech Connect

    Lashin, A. V. Kozyrev, A. V.

    2015-09-15

    One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.

  6. System and method for interfacing large-area electronics with integrated circuit devices

    DOEpatents

    Verma, Naveen; Glisic, Branko; Sturm, James; Wagner, Sigurd

    2016-07-12

    A system and method for interfacing large-area electronics with integrated circuit devices is provided. The system may be implemented in an electronic device including a large area electronic (LAE) device disposed on a substrate. An integrated circuit IC is disposed on the substrate. A non-contact interface is disposed on the substrate and coupled between the LAE device and the IC. The non-contact interface is configured to provide at least one of a data acquisition path or control path between the LAE device and the IC.

  7. An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits

    NASA Technical Reports Server (NTRS)

    Lubecke, Victor M.; Mcgrath, William R.; Rutledge, David B.

    1991-01-01

    Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

  8. Automatic layout of integrated-optic time-of-flight circuits

    NASA Astrophysics Data System (ADS)

    Fogg, Ruth D.

    1996-11-01

    This work describes the architecture and algorithms used in the computer-aided design tool developed for the automatic layout of integrated-optic, time-of-flight circuit designs. As in VLSI circuit layout, total wire length and chip area minimization are the goals in the layout of time-of-flight circuits. However, there are two major differences between the layout of time of flight circuits and VLSI circuits. First, the interconnection lengths of time-of-flight designs are exactly specified in order to achieve the necessary delays for signal synchronization. SEcondly, the switching elements are 120 times longer than they are wide. This highly astigmatic aspect ratio causes severe constraints on how and where the switches are placed. Assuming the continued development of corner turning mirrors allows the use of a parallel, row-based device placement architecture and a rectangular, fixed-grid track system for the connecting paths. The layout process proceeds in two steps. The first step involves the use of a partial circuit graph representation to place the elements in rows, oriented in the direction of the signal flow. After iterative improvement of the placement, the second step proceeds with the routing of the connecting paths. The main problem in the automatic layout of time-of-flight circuits is achieving the correct path lengths without overlapping previously routed paths. This problem is solved by taking advantage of a certain degree of variability present in each path, allowing the use of simple heuristics to circumvent previously routed paths.

  9. Detection of orbital angular momentum using a photonic integrated circuit.

    PubMed

    Rui, Guanghao; Gu, Bing; Cui, Yiping; Zhan, Qiwen

    2016-06-20

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector is achieved by applying voltage to the GeSe film to form gratings with alternate states. The resonant wavelength for arbitrary OAM state is demonstrated to be tunable in a quasi-linear manner through adjusting the duty cycle of the gratings. This work provides a viable approach for the realization of a compact integrated OAM detection device with enhanced functionality that may find important applications in optical communications and information processing with OAM states.

  10. Detection of orbital angular momentum using a photonic integrated circuit

    PubMed Central

    Rui, Guanghao; Gu, Bing; Cui, Yiping; Zhan, Qiwen

    2016-01-01

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector is achieved by applying voltage to the GeSe film to form gratings with alternate states. The resonant wavelength for arbitrary OAM state is demonstrated to be tunable in a quasi-linear manner through adjusting the duty cycle of the gratings. This work provides a viable approach for the realization of a compact integrated OAM detection device with enhanced functionality that may find important applications in optical communications and information processing with OAM states. PMID:27321916

  11. The stabilized supralinear network: A unifying circuit motif underlying multi-input integration in sensory cortex

    PubMed Central

    Rubin, Daniel B.; Van Hooser, Stephen D.; Miller, Kenneth D.

    2014-01-01

    Summary Neurons in sensory cortex integrate multiple influences to parse objects and support perception. Across multiple cortical areas, integration is characterized by two neuronal response properties: (1) surround suppression: modulatory contextual stimuli suppress responses to driving stimuli; (2) “normalization”: responses to multiple driving stimuli add sublinearly. These properties depend on input strength: for weak driving stimuli, contextual influences more weakly suppress or facilitate and summation becomes linear or supralinear. Understanding the circuit operations underlying integration is critical to understanding cortical function and disease. We present a simple, general theory. A wealth of integrative properties including the above emerge robustly from four properties of cortical circuitry: (1) supralinear neuronal input/output functions; (2) sufficiently strong recurrent excitation; (3) feedback inhibition; (4) simple spatial properties of intracortical connections. Integrative properties emerge dynamically as circuit properties, with excitatory and inhibitory neurons showing similar behaviors. In new recordings in visual cortex, we confirm key model predictions. PMID:25611511

  12. Built-In Test from the chip up - Self-testing integrated circuit design methodologies

    NASA Astrophysics Data System (ADS)

    Ferrell, John

    1988-09-01

    Design techniques for implementing BIT on the integrated circuit level are described, along with the voting circuitry and BIT functions. It is pointed out that the application of BITE on a chip level offers the potential of significantly reducing repair time, increasing maintainability, and increasing system reliability. BIT on IC substrates can be easily implemented using component redundant circuits and an appropriate voting circuit. A simple binary comparator can be used to compare outputs from digital logic circuits, and a window comparator can be used to compare analog paths. It is suggested that the application of nonvolatile memory and system status communication circuitry can extend the usefulness of the reconfigurable analog fault-tolerant IC architecture.

  13. A UVLO Circuit in SiC Compatible with Power MOSFET Integration (pending entry)

    SciTech Connect

    Ericson, Milton Nance; Frank, Steven Shane; Glover, Dr. Michael; Britton, Charles; Francis, Dr. Matt; Mantooth, Alan; Marlino, Laura D; Mcnutt, Tyler; Mudholkar, Dr. Mihir; Shepherd, Dr. Paul; Whitaker, Mr. Bret; Barkley, Dr. Adam; Lotstetter, Alex

    2014-01-01

    The design and test of the first undervoltage lock-out circuit implemented in a low-voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between 0 C and 200 C. Captured data show the circuit to be functional over a temperature range from -55 C to 300 C. The design of the circuit and test results is presented.

  14. A UVLO Circuit in SiC Compatible with Power MOSFET Integration

    SciTech Connect

    Glover, Michael; Shepherd, Paul; Francis, Matt; Mudholkar, Dr. Mihir; Mantooth, Alan; Ericson, Milton Nance; Frank, Steven; Britton Jr, Charles L; Marlino, Laura D; Mcnutt, Tyler; Barkley, Dr. Adam; Whitaker, Mr. Bret; Lostetter, Dr. Alex

    2014-01-01

    The design and test of the first undervoltage lock-out circuit implemented in a low voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between 0 C and 200 C. Captured data shows the circuit to be functional over a temperature range from -55 C to 300 C. The design of the circuit and test results is presented.

  15. Integrated circuit failure analysis by low-energy charge-induced voltage alteration

    DOEpatents

    Cole, Jr., Edward I.

    1996-01-01

    A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs.

  16. Integrated circuit failure analysis by low-energy charge-induced voltage alteration

    DOEpatents

    Cole, E.I. Jr.

    1996-06-04

    A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs. 5 figs.

  17. High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Li, K.; Shih, Y. C.

    1992-01-01

    Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

  18. Corrosion of silicon integrated circuits and lifetime predictions in implantable electronic devices

    NASA Astrophysics Data System (ADS)

    Vanhoestenberghe, A.; Donaldson, N.

    2013-06-01

    Corrosion is a prime concern for active implantable devices. In this paper we review the principles underlying the concepts of hermetic packages and encapsulation, used to protect implanted electronics, some of which remain widely overlooked. We discuss how technological advances have created a need to update the way we evaluate the suitability of both protection methods. We demonstrate how lifetime predictability is lost for very small hermetic packages and introduce a single parameter to compare different packages, with an equation to calculate the minimum sensitivity required from a test method to guarantee a given lifetime. In the second part of this paper, we review the literature on the corrosion of encapsulated integrated circuits (ICs) and, following a new analysis of published data, we propose an equation for the pre-corrosion lifetime of implanted ICs, and discuss the influence of the temperature, relative humidity, encapsulation and field-strength. As any new protection will be tested under accelerated conditions, we demonstrate the sensitivity of acceleration factors to some inaccurately known parameters. These results are relevant for any application of electronics working in a moist environment. Our comparison of encapsulation and hermetic packages suggests that both concepts may be suitable for future implants.

  19. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    SciTech Connect

    Arefin, Md Shamsul Redoute, Jean-Michel; Rasit Yuce, Mehmet; Bulut Coskun, M.; Alan, Tuncay; Neild, Adrian

    2014-06-02

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0–5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  20. Analysis of the possibility of a PGA309 integrated circuit application in pressure sensors

    NASA Astrophysics Data System (ADS)

    Walendziuk, Wojciech; Baczewski, Michal; Idzkowski, Adam

    2016-09-01

    This article present the results of research concerning the analysis of the possibilities of applying a PGA309 integrated circuit in transducers used for pressure measurement. The experiments were done with the use of a PGA309EVM-USB evaluation circuit with a BD|SENSORS pressure sensor. A specially prepared MATLAB script was used in the process of the calibration setting choice and the results analysis. The article discusses the worked out algorithm that processes the measurement results, i.e. the algorithm which calculates the desired gain and the offset adjustment voltage of the transducer measurement bridge in relation to the input signal range of the integrated circuit and the temperature of the environment (temperature compensation). The checking procedure was conducted in a measurement laboratory and the obtained result were analyzed and discussed.

  1. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    NASA Astrophysics Data System (ADS)

    Arefin, Md Shamsul; Bulut Coskun, M.; Alan, Tuncay; Redoute, Jean-Michel; Neild, Adrian; Rasit Yuce, Mehmet

    2014-06-01

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0-5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  2. (DCT) A Reconfigurable RF Photonics Unit Cell For Integrated Circuits

    DTIC Science & Technology

    2012-08-10

    shown in Figure 1.6. The phased array tapered slot antenna integrated with QDMLLs is fabricated to perform beam - steering by manipulating the...at multiple QDMLL harmonics are presented in detail. Moreover, an example of achieving beam - steering using a two-element QDMLL-LTSA phased array by... array system without the use of phase shifters. Reconfigurable , Quantum Dot Mode Locked Lasers, antennas , RF/Photonics Department of

  3. Development of processing procedures for advanced silicon solar cells. [antireflection coatings and short circuit currents

    NASA Technical Reports Server (NTRS)

    Scott-Monck, J. A.; Stella, P. M.; Avery, J. E.

    1975-01-01

    Ten ohm-cm silicon solar cells, 0.2 mm thick, were produced with short circuit current efficiencies up to thirteen percent and using a combination of recent technical advances. The cells were fabricated in conventional and wraparound contact configurations. Improvement in cell collection efficiency from both the short and long wavelengths region of the solar spectrum was obtained by coupling a shallow junction and an optically transparent antireflection coating with back surface field technology. Both boron diffusion and aluminum alloying techniques were evaluated for forming back surface field cells. The latter method is less complicated and is compatible with wraparound cell processing.

  4. In-plant testing of a novel coal cleaning circuit using advanced technologies. Final technical report, September 1, 1995--August 31, 1996

    SciTech Connect

    Honaker, R.Q.; Reed, S.; Mohanty, M.K.

    1997-05-01

    A circuit comprised of advanced fine coal cleaning technologies was evaluated in an operating preparation plant to determine circuit performance and to compare the performance with current technologies used to treat -16 mesh fine coal. The circuit integrated a Floatex hydrosizer, a Falcon enhanced gravity concentrator and a Jameson flotation cell. A Packed-Column was used to provide additional reductions in the pyritic sulfur and ash contents by treatment of the Floatex-Falcon-Jameson circuit product. For a low sulfur Illinois No. 5 coal, the pyritic sulfur content was reduced from 0.67% to 0.34% at a combustible recovery of 93.2%. The ash content was decreased from 27.6% to 5.84%, which equates to an organic efficiency of 95% according to gravity-based washability data. The separation performance achieved on a high sulfur Illinois No. 5 coal resulted in the rejection of 72.7% of the pyritic sulfur and 82.3% of the ash-forming material at a recovery of 8 1 %. Subsequent pulverization of the cleaned product and retreatment in a Falcon concentrator and Packed-Column resulted in overall circuit ash and pyritic sulfur rejections of 89% and 93%, respectively, which yielded a pyritic sulfur content reduction from 2.43% to 0.30%. This separation reduced the sulfur dioxide emission rating of an Illinois No. 5 coal from 6.21 to 1.75 lbs SO{sub 2}/MBTU, which is Phase I compliance coal. A comparison of the results obtained from the Floatex-Falcon-Jameson circuit with those of the existing circuit revealed that the novel fine coal circuit provides 10% to 20% improvement in mass yield to the concentrate while rejecting greater amounts of ash and pyritic sulfur.

  5. Fully integrated quantum photonic circuit with an electrically driven light source

    NASA Astrophysics Data System (ADS)

    Khasminskaya, Svetlana; Pyatkov, Felix; Słowik, Karolina; Ferrari, Simone; Kahl, Oliver; Kovalyuk, Vadim; Rath, Patrik; Vetter, Andreas; Hennrich, Frank; Kappes, Manfred M.; Gol'Tsman, G.; Korneev, A.; Rockstuhl, Carsten; Krupke, Ralph; Pernice, Wolfram H. P.

    2016-11-01

    Photonic quantum technologies allow quantum phenomena to be exploited in applications such as quantum cryptography, quantum simulation and quantum computation. A key requirement for practical devices is the scalable integration of single-photon sources, detectors and linear optical elements on a common platform. Nanophotonic circuits enable the realization of complex linear optical systems, while non-classical light can be measured with waveguide-integrated detectors. However, reproducible single-photon sources with high brightness and compatibility with photonic devices remain elusive for fully integrated systems. Here, we report the observation of antibunching in the light emitted from an electrically driven carbon nanotube embedded within a photonic quantum circuit. Non-classical light generated on chip is recorded under cryogenic conditions with waveguide-integrated superconducting single-photon detectors, without requiring optical filtering. Because exclusively scalable fabrication and deposition methods are used, our results establish carbon nanotubes as promising nanoscale single-photon emitters for hybrid quantum photonic devices.

  6. Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

    ERIC Educational Resources Information Center

    Aziz, Syed Mahfuzul; Sicard, Etienne; Ben Dhia, Sonia

    2010-01-01

    This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied…

  7. Integrated Circuit Electromagnetic Susceptibility Investigation - Phase 2. Bipolar NAND Gate Study

    DTIC Science & Technology

    1974-07-26

    INTEGRATED CIRCUIT SUSCEPTIBILITY MOC El 123 26 JULY 1974 II 100 POtER ABSORBED - mW 1000 FIGURE 51 CHARACTERISTICS OF R FOR THE OUTPUT PARASITIC...87117 Commanding Officer, Harry Diamond Laboratory Attn: J. Sweton W. L. Vault H. Dropkin Washington, D. C. 20438 Commander, Naval Electronics

  8. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    PubMed Central

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  9. Ultraprecise phase manipulation in integrated photonic quantum circuits with generalized directional couplers

    SciTech Connect

    Heilmann, R.; Keil, R.; Gräfe, M.; Nolte, S.; Szameit, A.

    2014-08-11

    We present an innovative approach for ultra-precise phase manipulation in integrated photonic quantum circuits. To this end, we employ generalized directional couplers that utilize a detuning of the propagation constant in optical waveguides by the overlap of adjacent waveguide modes. We demonstrate our findings in experiments with classical as well as quantum light.

  10. NV-based quantum memories coupled to photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Mouradian, Sara; Schröder, Tim; Zheng, Jiabao; Lu, Tsung-Ju; Choi, Hyeongrak; Wan, Noel; Walsh, Michael; Bersin, Eric; Englund, Dirk

    2016-09-01

    The negatively charged nitrogen vacancy (NV) center in diamond is a promising solid-state quantum memory. However, developing networks comprising such quantum memories is limited by the fabrication yield of the quantum nodes and the collection efficiency of indistinguishable photons. In this letter, we report on advances on a hybrid quantum system that allows for scalable production of networks, even with low-yield node fabrication. Moreover, an NV center in a simple single mode diamond waveguide is shown in simulation and experiment to couple well to a single mode SiN waveguide with a simple adiabatic taper for optimal mode transfer. In addition, cavity enhancement of the zero phonon line of the NV center with a resonance coupled to the waveguide mode allows a simulated <1800 fold increase in the collection of photon states coherent with the state of the NV center into a single frequency and spatial mode.

  11. Study of waveguide crosstalk in silicon photonics integrated circuits

    NASA Astrophysics Data System (ADS)

    Donzella, Valentina; Talebi Fard, Sahba; Chrostowski, Lukas

    2013-10-01

    Silicon photonics is going trough a terrific expansion driven by several applications, from chip wiring to integrated sensors and telecommunications. Some applications, e.g. intra and inter chip connections and sensing, require long parallel waveguides for wiring or for connecting grating couplers (GCs) to devices situated in sensing micro-channels. In well packed photonics chips there are often long wiring waveguides parallel for several mm, so loss can be caused by light coupled back and forth between them (cross-talk), by scattering, wall roughness, mode mismatch, etc. This work aims to investigate cross-talk for long parallel waveguides, and to propose methods to reduce cross-talk loss when high integration density is required. We have designed and fabricated about 200 testing structures exploiting e-beam on silicon on insulator (SOI) chip, in order to test several parameters and to find out dominant loss mechanisms. All devices have been tested and measured using an automatic optical bench, in the wavelength range between 1500-1600 nm. Achieved results are promising, since they allow for comparing cross-talk for short as well as long interaction lengths (up to 5 mm), different waveguide width pairs, several separation distances, and for TE and TM polarization. For smaller gaps, having not symmetric pair of waveguides is very beneficial, since it results in a lower power coupling, e.g. about 20/14 dB of crosstalk reduction for TE/TM waveguides after 5 mm of propagation and gap of 0.5 μm. This can be very useful for the design of integrated photonics chips requiring high-density packaging of devices and waveguides.

  12. Theoretical aspects of VLSI (Very Large Scale Integration) circuit design

    NASA Astrophysics Data System (ADS)

    Leighton, F. T.

    1986-01-01

    During the period covered by the grant, two books and ten research papers were written under grant sponsorship. In addition nineteen of the research papers were written and published in conference proceeding. Ten other research manuscripts are now nearing completion. Titles of some of the completed work include: Eigenvalues and Expanders, A Framework of Solving VLSI Graph Layout Problems, Tight Bounds on the Complexity of Parallel Sorting, Wafer-Scale Integration of Systolic Arrays, and The Average Case Analysis of Some On-Line Algorithms for Bin Packing.

  13. Hybrid integration platform based on silica-on-silicon planar lightwave circuit

    NASA Astrophysics Data System (ADS)

    Lin, Wenhua; Sun, C. Jacob; Schmidt, Kevin M.

    2007-02-01

    While silica waveguide PLC products have been deployed in various systems and applications, hybrid integration of semiconductor opto-electronic devices on silica-based planar lightwave circuit (PLC) has become the mainstream platform for small form factor, low-cost and high volume integrated transceiver modules. One of the main benefits of hybrid integration is the wafer-scale process, which greatly reduces chip/module size and assembly cost. This paper reviews the development of this technology, and as an example, presents a hybrid integrated transmitter with four wavelengths on silica PLC chip for LX4 and 10GbE applications.

  14. CMOS-based carbon nanotube pass-transistor logic integrated circuits.

    PubMed

    Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

    2012-02-14

    Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

  15. A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit.

    PubMed

    Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

    2016-06-18

    This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of -50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor's output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments.

  16. A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit

    PubMed Central

    Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

    2016-01-01

    This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of −50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor’s output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments. PMID:27322288

  17. Automatic layout of integrated-optics time-of-flight circuits

    NASA Astrophysics Data System (ADS)

    Kennett-Fogg, Ruth D.

    1995-04-01

    This work describes the architecture and algorithms used in the computer aided design tool developed for the automatic layout of integrated optic, time of flight circuit designs. This is similar to the layout of electronic VLSI circuits, where total wire length and chip area minimization are the major goals. Likewise, total wire length and chip area minimization are also the goals in the layout of time of flight circuits. However, there are two major differences between the layout of time of flight circuits and VLSI circuits. First, the interconnection lengths of time of flight designs are exactly specified in order to achieve the necessary delays for signal synchronization. Secondly, the switching elements are 120 times longer than they are wide. This highly astigmatic aspect ratio causes severe constraints on how and where the switches are placed. The assumed development of integrated corner turning mirrors allows the use of a parallel, row based device placement architecture and a rectangular, fixed grid track system for the connecting paths. The layout process proceeds in two steps. The first step involves the use of a partial circuit graph representation to place the elements in rows, oriented in the direction of the signal flow. After iterative improvement of the placement, the second step proceeds with the routing of the connecting paths. The main problem in the automatic layout of time of flight circuits is achieving the correct path lengths without overlapping previously routed paths. This problem is solved by taking advantage of a certain degree of variability present in each path, allowing the use of simple heuristics to circumvent previously routed paths.

  18. High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

    PubMed

    Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

    2017-03-29

    Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

  19. 76 FR 19174 - In the Matter of Circuit Systems, Inc., Global Energy Group, Inc., Integrated Medical Resources...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-04-06

    ... COMMISSION File No. 500-1 In the Matter of Circuit Systems, Inc., Global Energy Group, Inc., Integrated... information concerning the securities of Circuit Systems, Inc. because it has not filed any periodic reports... securities of Integrated Medical Resources, Inc. because it has not filed any periodic reports since...

  20. Power Management Integrated Circuit for Indoor Photovoltaic Energy Harvesting System

    NASA Astrophysics Data System (ADS)

    Jain, Vipul

    In today's world, power dissipation is a main concern for battery operated mobile devices. Key design decisions are being governed by power rather than area/delay because power requirements are growing more stringent every year. Hence, a hybrid power management system is proposed, which uses both a solar panel to harvest energy from indoor lighting and a battery to power the load. The system tracks the maximum power point of the solar panel and regulates the battery and microcontroller output load voltages through the use of an on-chip switched-capacitor DC-DC converter. System performance is verified through simulation at the 180nm technology node and is made to be integrated on-chip with 0.25 second startup time, 79% efficiency, --8/+14% ripple on the load, an average 1micro A of quiescent current (3.7micro W of power) and total on-chip area of 1.8mm2 .

  1. Integrating advanced facades into high performance buildings

    SciTech Connect

    Selkowitz, Stephen E.

    2001-05-01

    Glass is a remarkable material but its functionality is significantly enhanced when it is processed or altered to provide added intrinsic capabilities. The overall performance of glass elements in a building can be further enhanced when they are designed to be part of a complete facade system. Finally the facade system delivers the greatest performance to the building owner and occupants when it becomes an essential element of a fully integrated building design. This presentation examines the growing interest in incorporating advanced glazing elements into more comprehensive facade and building systems in a manner that increases comfort, productivity and amenity for occupants, reduces operating costs for building owners, and contributes to improving the health of the planet by reducing overall energy use and negative environmental impacts. We explore the role of glazing systems in dynamic and responsive facades that provide the following functionality: Enhanced sun protection and cooling load control while improving thermal comfort and providing most of the light needed with daylighting; Enhanced air quality and reduced cooling loads using natural ventilation schemes employing the facade as an active air control element; Reduced operating costs by minimizing lighting, cooling and heating energy use by optimizing the daylighting-thermal tradeoffs; Net positive contributions to the energy balance of the building using integrated photovoltaic systems; Improved indoor environments leading to enhanced occupant health, comfort and performance. In addressing these issues facade system solutions must, of course, respect the constraints of latitude, location, solar orientation, acoustics, earthquake and fire safety, etc. Since climate and occupant needs are dynamic variables, in a high performance building the facade solution have the capacity to respond and adapt to these variable exterior conditions and to changing occupant needs. This responsive performance capability

  2. Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

    NASA Technical Reports Server (NTRS)

    Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

    2002-01-01

    We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

  3. Escherichia coli Flagellar Genes as Target Sites for Integration and Expression of Genetic Circuits

    PubMed Central

    Juhas, Mario; Evans, Lewis D. B.; Frost, Joe; Davenport, Peter W.; Yarkoni, Orr; Fraser, Gillian M.; Ajioka, James W.

    2014-01-01

    E. coli is a model platform for engineering microbes, so genetic circuit design and analysis will be greatly facilitated by simple and effective approaches to introduce genetic constructs into the E. coli chromosome at well-characterised loci. We combined the Red recombinase system of bacteriophage λ and Isothermal Gibson Assembly for rapid integration of novel DNA constructs into the E. coli chromosome. We identified the flagellar region as a promising region for integration and expression of genetic circuits. We characterised integration and expression at four candidate loci, fliD, fliS, fliT, and fliY, of the E. coli flagellar region 3a. The integration efficiency and expression from the four integrations varied considerably. Integration into fliD and fliS significantly decreased motility, while integration into fliT and fliY had only a minor effect on the motility. None of the integrations had negative effects on the growth of the bacteria. Overall, we found that fliT was the most suitable integration site. PMID:25350000

  4. Escherichia coli flagellar genes as target sites for integration and expression of genetic circuits.

    PubMed

    Juhas, Mario; Evans, Lewis D B; Frost, Joe; Davenport, Peter W; Yarkoni, Orr; Fraser, Gillian M; Ajioka, James W

    2014-01-01

    E. coli is a model platform for engineering microbes, so genetic circuit design and analysis will be greatly facilitated by simple and effective approaches to introduce genetic constructs into the E. coli chromosome at well-characterised loci. We combined the Red recombinase system of bacteriophage λ and Isothermal Gibson Assembly for rapid integration of novel DNA constructs into the E. coli chromosome. We identified the flagellar region as a promising region for integration and expression of genetic circuits. We characterised integration and expression at four candidate loci, fliD, fliS, fliT, and fliY, of the E. coli flagellar region 3a. The integration efficiency and expression from the four integrations varied considerably. Integration into fliD and fliS significantly decreased motility, while integration into fliT and fliY had only a minor effect on the motility. None of the integrations had negative effects on the growth of the bacteria. Overall, we found that fliT was the most suitable integration site.

  5. Integrating advanced mobility into lunar surface exploration

    NASA Astrophysics Data System (ADS)

    Schlutz, Juergen; Messerschmid, Ernst

    2012-06-01

    With growing knowledge of the lunar surface environment from recent robotic missions, further assessment of human lunar infrastructures and operational aspects for surface exploration become possible. This is of particular interest for the integration of advanced mobility assets, where path planning, balanced energy provision and consumption as well as communication coverage grow in importance with the excursion distance. The existing modeling and simulation tools for the lunar surface environment have therefore been revisited and extended to incorporate aspects of mobile exploration. An extended analysis of the lunar topographic models from past and ongoing lunar orbital missions has resulted in the creation of a tool to calculate and visualize slope angles in selected lunar regions. This allows for the identification of traversable terrain with respect to the mobile system capabilities. In a next step, it is combined with the analysis of the solar illumination conditions throughout this terrain to inform system energy budgets in terms of electrical power availability and thermal control requirements. The combination of the traversability analysis together with a time distributed energy budget assessment then allows for a path planning and optimization for long range lunar surface mobility assets, including manned excursions as well as un-crewed relocation activities. The above mentioned tools are used for a conceptual analysis of the international lunar reference architecture, developed in the frame of the International Architecture Working Group (IAWG) of the International Space Exploration Coordination Group (ISECG). Its systems capabilities are evaluated together with the planned surface exploration range and paths in order to analyze feasibility of the architecture and to identify potential areas of optimization with respect to time-based and location-based integration of activities.

  6. A power-efficient analog integrated circuit for amplification and detection of neural signals.

    PubMed

    Borghi, T; Bonfanti, A; Gusmeroli, R; Zambra, G; Spinelli, A S

    2008-01-01

    We present a neural amplifier that optimizes the trade-off between power consumption and noise performance down to the best so far reported. In the perspective of realizing a fully autonomous implantable system we also address the problem of spike detection by using a new simple algorithm and we discuss the implementation with analog integrated circuits. Implemented in 0.35-microm CMOS technology and with total current consumption of about 20 microA, the whole circuit occupies an area of 0.18 mm(2). Reduced power consumption and small area make it suited to be used in chronic multichannel recording systems for neural prosthetics and neuroscience experiments.

  7. 4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

    NASA Technical Reports Server (NTRS)

    Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

    2015-01-01

    Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

  8. The use of multiple oxygen implants for fabrication of bipolar silicon-on-insulator integrated circuits

    NASA Astrophysics Data System (ADS)

    Platteter, Dale G.; Cheek, Tom F., Jr.

    1988-12-01

    A description is given of the radiation improvements obtained by fabricating bipolar integrated circuits on oxygen-implanted silicon-on-insulator substrates that were manufactured with multiple (low-dose) implants. Bipolar 74ALSOO gates fabricated on these substrates showed an improvement in total dose and dose-rate radiation response over identical circuits fabricated in bulk silicon. Defects in SIMOX material were reduced by over four orders of magnitude. The results demonstrate that bipolar devices, fabricated on multiple-implant SIMOX substrates, can compete with conventional dielectric isolation for many radiation-hardened system applications.

  9. Measurements of complex impedance in microwave high power systems with a new bluetooth integrated circuit.

    PubMed

    Roussy, Georges; Dichtel, Bernard; Chaabane, Haykel

    2003-01-01

    By using a new integrated circuit, which is marketed for bluetooth applications, it is possible to simplify the method of measuring the complex impedance, complex reflection coefficient and complex transmission coefficient in an industrial microwave setup. The Analog Devices circuit AD 8302, which measures gain and phase up to 2.7 GHz, operates with variable level input signals and is less sensitive to both amplitude and frequency fluctuations of the industrial magnetrons than are mixers and AM crystal detectors. Therefore, accurate gain and phase measurements can be performed with low stability generators. A mechanical setup with an AD 8302 is described; the calibration procedure and its performance are presented.

  10. Enhancing and inhibiting stimulated Brillouin scattering in photonic integrated circuits

    PubMed Central

    Merklein, Moritz; Kabakova, Irina V.; Büttner, Thomas F. S.; Choi, Duk-Yong; Luther-Davies, Barry; Madden, Stephen J.; Eggleton, Benjamin J.

    2015-01-01

    On-chip nonlinear optics is a thriving research field, which creates transformative opportunities for manipulating classical or quantum signals in small-footprint integrated devices. Since the length scales are short, nonlinear interactions need to be enhanced by exploiting materials with large nonlinearity in combination with high-Q resonators or slow-light structures. This, however, often results in simultaneous enhancement of competing nonlinear processes, which limit the efficiency and can cause signal distortion. Here, we exploit the frequency dependence of the optical density-of-states near the edge of a photonic bandgap to selectively enhance or inhibit nonlinear interactions on a chip. We demonstrate this concept for one of the strongest nonlinear effects, stimulated Brillouin scattering using a narrow-band one-dimensional photonic bandgap structure: a Bragg grating. The stimulated Brillouin scattering enhancement enables the generation of a 15-line Brillouin frequency comb. In the inhibition case, we achieve stimulated Brillouin scattering free operation at a power level twice the threshold. PMID:25736909

  11. Impact-Based Area Allocation for Yield Optimization in Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Abraham, Billion; Widodo, Arif; Chen, Poki

    2016-06-01

    In analog integrated circuit (IC) layout, area allocation is a very important issue for achieving good mismatch cancellation. However, most IC layout papers focus only on layout strategy to reduce systematic mismatch. In 2006, an outstanding paper presenting area allocation strategy was published to introduce technique for random mismatch reduction. Instead of using general theoretical study to prove the strategy, this research presented close-to-optimum simulations only on case-bycase basis. The impact-based area allocation for yield optimization in integrated circuits is proposed in this chapter. To demonstrate the corresponding strategy, not only a theoretical analysis but also an integral nonlinearity-based yield simulation will be given to derive optimum area allocation for binary weighted current steering digital-to-analog converter (DAC). The result will be concluded to convince IC designers how to allocate area for critical devices in an optimum way.

  12. Moving the boundary between wavelength resources in optical packet and circuit integrated ring network.

    PubMed

    Furukawa, Hideaki; Miyazawa, Takaya; Wada, Naoya; Harai, Hiroaki

    2014-01-13

    Optical packet and circuit integrated (OPCI) networks provide both optical packet switching (OPS) and optical circuit switching (OCS) links on the same physical infrastructure using a wavelength multiplexing technique in order to deal with best-effort services and quality-guaranteed services. To immediately respond to changes in user demand for OPS and OCS links, OPCI networks should dynamically adjust the amount of wavelength resources for each link. We propose a resource-adjustable hybrid optical packet/circuit switch and transponder. We also verify that distributed control of resource adjustments can be applied to the OPCI ring network testbed we developed. In cooperation with the resource adjustment mechanism and the hybrid switch and transponder, we demonstrate that automatically allocating a shared resource and moving the wavelength resource boundary between OPS and OCS links can be successfully executed, depending on the number of optical paths in use.

  13. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

    PubMed Central

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-01-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80–100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes. PMID:28145513

  14. CMOS Integrated Lock-in Readout Circuit for FET Terahertz Detectors

    NASA Astrophysics Data System (ADS)

    Domingues, Suzana; Perenzoni, Daniele; Perenzoni, Matteo; Stoppa, David

    2017-02-01

    In this paper, a switched-capacitor readout circuit topology integrated with a THz antenna and field-effect transistor detector is analyzed, designed, and fabricated in a 0.13-μm standard CMOS technology. The main objective is to perform amplification and filtering of the signal, as well as subtraction of background in case of modulated source, in order to avoid the need for an external lock-in amplifier, in a compact implementation. A maximum responsivity of 139.7 kV/W, and a corresponding minimum NEP of 2.2 nW/√Hz, was obtained with a two-stage readout circuit at 1 kHz modulation frequency. The presented switched-capacitor circuit is suitable for implementation in pixel arrays due to its compact size and power consumption (0.014 mm2 and 36 μW).

  15. Test and verification of a reactor protection system application-specific integrated circuit

    SciTech Connect

    Battle, R.E.; Turner, G.W.; Vandermolen, R.I.; Vitalbo, C.; Naser, J.

    1997-03-01

    Application-specific integrated circuits (ASICs) were utilized in the design of nuclear plant safety systems because they have certain advantages over software-based systems and analog-based systems. An advantage they have over software-based systems is that an ASIC design can be simple enough to not include branch statements and also can be thoroughly tested. A circuit card on which an ASIC is mounted can be configured to replace various versions of older analog equipment with fewer design types required. The approach to design and testing of ASICs for safety system applications is discussed in this paper. Included are discussions of the ASIC architecture, how it is structured to assist testing, and of the functional and enhanced circuit testing.

  16. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

    NASA Astrophysics Data System (ADS)

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-02-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80–100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

  17. Integrated circuit design considerations for spacecraft VLSI implemented in standard CMOS processes

    NASA Astrophysics Data System (ADS)

    Martin, Mark Noel

    2000-10-01

    In this dissertation I will examine issues concerning the use of custom Application Specific Integrated Circuits (ASIC)s, fabricated at commercial foundries, for use in spacecraft. I will examine this subject from the fabrication, device, circuit and system level. I begin with an overview of integrated circuit fabrication and post processing technology used to physically alter the circuit and enhance its electrical performance. I examine the MOS transistor and its variant the Floating-Gate MOS transistor from a device perspective. I discuss a model, derived from the electrostatics of the MOS structure, that is continuous over the entire region of operation while maintaining a small set of physical parameters. Secondly, the operation of the Floating-Gate MOSFET, a device finding increasing usage in adaptive systems, will be presented. The model is then expanded to include the effects of exposure to ionizing radiation on MOSFETs. From a circuit perspective, I will examine the issue of power and energy usage in a digital system. The current-mode design approach will be reviewed as an introduction to Current-Mode-Differential-Logic, a low energy logic family. I will discuss Floating-Gate-Logic, an application of floating-gate transistors to solve the low-power problem by adjusting device thresholds. The second half of the dissertation will be focused on radiation effects in MOS devices. I begin by describing the, rather unpleasant, environment that spacecraft operate in. I continue with a discussion on two main effects of radiation exposure that engineers need to contend with, radiation induced latchup and total-dose exposure. I will provide results from different experiments designed to evaluate a commercial CMOS process's usability for a space application. Finally I describe an application that utilizes the negative effects of radiation on floating-gate MOS devices, an integrated, electronic micro-dosimeter.

  18. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

    PubMed

    Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Cheng, K-T; Strukov, D B

    2017-02-14

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

  19. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

    NASA Astrophysics Data System (ADS)

    Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

    2017-02-01

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

  20. Translational use of event-related potentials to assess circuit integrity in ASD.

    PubMed

    Modi, Meera E; Sahin, Mustafa

    2017-03-01

    Deficits in social cognition are the defining characteristic of autism spectrum disorder (ASD). Social cognition requires the integration of several neural circuits in a time-sensitive fashion, so impairments in social interactions could arise as a result of alterations in network connectivity. Electroencephalography (EEG) has revealed abnormalities in event related potentials (ERPs) evoked by auditory and visual sensory stimuli in humans with ASD, indicating disruption of neural connectivity. Similar abnormalities in sensory-evoked ERPs have been observed in animal models of ASD, suggesting that ERPs have the potential to provide a translational biomarker of the disorder. People with ASD also have abnormal ERPs in response to auditory and visual social stimuli, demonstrating functional disruption of the social circuit. To assess the integrity of the social circuit and characterize biomarkers of circuit dysfunction, novel EEG paradigms that use social stimuli to induce ERPs should be developed for use in animal models. The identification of a socially-relevant ERP that is consistent in animal models and humans would facilitate the development of pharmacological treatment strategies for the social impairments in ASD and other neuropsychiatric disorders.

  1. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

    PubMed Central

    Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

    2017-01-01

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

  2. Design and fabrication of an implantable cortical semiconductor integrated circuit electrode array

    NASA Astrophysics Data System (ADS)

    Lefevre, Pierre K.

    1990-12-01

    This research furthered the processing steps of the AFIT 16 by 16 implantable cortical semiconductor integrated circuit electrode array, or brain chip. The areas of interest include the brain chip electronics, metallization, ionic permeation, and implantation. The electronics and metallization are heavily covered. A high speed, single clock divide-by-two circuit was modified with a reset transistor and cascaded to form a ripple counter. This device had stable operation at specific source voltage and clock voltage and frequency. A 7-stage inverter with 10 unmodified divide-by-two circuits cascaded operated between 1.7 and 8 volts, and between 39 KHz and 1 MHz, respectively. The metallization process refers to coating Au/Ni or Pt onto exposed aluminum areas (pads) of a CMOS integrated circuit. Sputtering was used to coat the chip. And an Au/Ni etchant or Pt peel-off technique was used. The Au/Ni etchant used was iodine, potassium iodide, and deionized water solution.

  3. Monolithic microwave integrated circuits for sensors, radar, and communications systems; Proceedings of the Meeting, Orlando, FL, Apr. 2-4, 1991

    NASA Astrophysics Data System (ADS)

    Leonard, Regis F.; Bhasin, Kul B.

    Consideration is given to MMICs for airborne phased arrays, monolithic GaAs integrated circuit millimeter wave imaging sensors, accurate design of multiport low-noise MMICs up to 20 GHz, an ultralinear low-noise amplifier technology for space communications, variable-gain MMIC module for space applications, a high-efficiency dual-band power amplifier for radar applications, a high-density circuit approach for low-cost MMIC circuits, coplanar SIMMWIC circuits, recent advances in monolithic phased arrays, and system-level integrated circuit development for phased-array antenna applications. Consideration is also given to performance enhancement in future communications satellites with MMIC technology insertion, application of Ka-band MMIC technology for an Orbiter/ACTS communications experiment, a space-based millimeter wave debris tracking radar, low-noise high-yield octave-band feedback amplifiers to 20 GHz, quasi-optical MESFET VCOs, and a high-dynamic-range mixer using novel balun structure. (For individual items see A93-25777 to A93-25814)

  4. Towards Photonic-Plasmonic Integrated Circuits: Study and Fabrication Of Electrically-Pumped Plasmonic Nano-Laser

    NASA Astrophysics Data System (ADS)

    Hseih, Chunhan Michael

    For the next generation of optical communication, Photonic Integrated Circuits (PIC) and optoelectronic integrated circuits has been of great interest because of the possibility of integrating multiple optical components and electronics together to give high performance opto-electronic system on a small chip that can be produced cost-effectively. Integrated semiconductor laser, as the main light source for generating signals in optical communications, is one of the most important function on a photonic integrated circuit. In the recent advancements in nanophotonics, strong confinement of light in strongly-guiding optical waveguide structure comparing to conventional structures, has been used to improve certain performances of on-chip semiconductor lasers and miniaturize the laser device sizes. However, compared to electronics, even with use of nanophotonic device technology, optoelectronic device footprints are still relatively large due to the diffraction limit of light, which poses a limit on the sizes of optoelectronic devices. Plasmonic photonic device area has been an intensive field of research that utilizes plamonic photonic waveguides to confine light smaller than the diffraction limit through the effect of surface plasmon polariton, a coupling between photons and plasmon along a metal-dielectric interface. In this dissertation, an electrically pumped Plasmonic nanolaser has been designed using 2D-FDTD simulation. The nanolaser has the potential of lasing utilizing achievable optical gain in the typical compound (group III-V) semiconductor materials. The laser electrical pumping structure is compatible with device integration on silicon photonics platform utilizing silicon-on-insulator (SOI) substrate. Electrically pumped thin film based laser structure is shown to be realizable with the use of TCO material as transparent electrodes on the waveguide cladding. Indium oxide (In2O3) and Zinc-Indium-Tin-Oxide (ZITO) deposited by ion-beam-assisted deposition

  5. Heavy-ion induced single-event upset in integrated circuits

    NASA Technical Reports Server (NTRS)

    Zoutendyk, J. A.

    1991-01-01

    The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

  6. A multi-ring optical packet and circuit integrated network with optical buffering.

    PubMed

    Furukawa, Hideaki; Shinada, Satoshi; Miyazawa, Takaya; Harai, Hiroaki; Kawasaki, Wataru; Saito, Tatsuhiko; Matsunaga, Koji; Toyozumi, Tatuya; Wada, Naoya

    2012-12-17

    We newly developed a 3 × 3 integrated optical packet and circuit switch-node. Optical buffers and burst-mode erbium-doped fiber amplifiers with the gain flatness are installed in the 3 × 3 switch-node. The optical buffer can prevent packet collisions and decrease packet loss. We constructed a multi-ring optical packet and circuit integrated network testbed connecting two single-ring networks and a client network by the 3 × 3 switch-node. For the first time, we demonstrated 244 km fiber transmission and 5-node hopping of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10 Gigabit Ethernet frames on the testbed. Error-free (frame error rate < 1 × 10(-4)) operation was achieved with optical packets of various packet lengths. In addition, successful avoidance of packet collisions by optical buffers was confirmed.

  7. A CMOS readout integrated circuit with automatic deselecting function for IRFPA

    NASA Astrophysics Data System (ADS)

    Liu, Shanshan; Ding, Ruijun; Pang, Yulin; Chen, Zhe

    2009-11-01

    In this paper, a readout integrated circuit (ROIC) is presented for improving the operability of the LWIR arrays by using a super-pixel detector format scheme, identifying and deselecting the bad elements automatically. This ROIC features an input stage based on buffered direct injection (BDI) structure, which uses a differential stage to provide the inverting gain to improve linearity and to provide tight control of the detector bias. The threshold voltage of bad element de-selection is adjustable and the circuit could de-select the bad element automatically. The simulation result show that the bad sub-element de-selection precision is up to nearly 0.2nA when the threshold current is about 590.8nA. We analyze the errors affecting the precision and the calculated precision is 2nA. Finally, we discuss the bad sub-element de-selection precision in different integrating time.

  8. Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

    PubMed

    Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

    2016-09-19

    Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

  9. Correlation of total dose damage in capacitors and transistors to 1. 25 micron integrated circuits

    SciTech Connect

    Zietlow, T.C.; Morse, T.C.; Urquhart, K.C.; Wilson, K.T.; Aukerman, L.W.; Barnes, C.E.

    1987-12-01

    Parametric data taken from the irradiation of transistors and capacitors has been correlated with integrated circuit response in 1.25 micron technology. Data taken on worst case biased test transistors (+5 V static gate bias for n-channel, 0 V p-channel) accurately predicts worst case propagation delay changes in an irradiated ALU. Dynamically biased test transistors successfully model the access time delay of a RAM and a ROM after irradiation. The results indicate that worst case bias conditions for an integrated circuit during irradiation depend on the the pathway measured and that test transistors provide a better measure of worst case total dose hardness of an IC rather than direct irradiation of the part itself.

  10. Photonic crystal ring resonator based optical filters for photonic integrated circuits

    SciTech Connect

    Robinson, S.

    2014-10-15

    In this paper, a two Dimensional (2D) Photonic Crystal Ring Resonator (PCRR) based optical Filters namely Add Drop Filter, Bandpass Filter, and Bandstop Filter are designed for Photonic Integrated Circuits (PICs). The normalized output response of the filters is obtained using 2D Finite Difference Time Domain (FDTD) method and the band diagram of periodic and non-periodic structure is attained by Plane Wave Expansion (PWE) method. The size of the device is minimized from a scale of few tens of millimeters to the order of micrometers. The overall size of the filters is around 11.4 μm × 11.4 μm which is highly suitable of photonic integrated circuits.

  11. Integrated circuit package with lead structure and method of preparing the same

    NASA Technical Reports Server (NTRS)

    Kennedy, B. W. (Inventor)

    1973-01-01

    A beam-lead integrated circuit package assembly including a beam-lead integrated circuit chip, a lead frame array bonded to projecting fingers of the chip, a rubber potting compound disposed around the chip, and an encapsulating molded plastic is described. The lead frame array is prepared by photographically printing a lead pattern on a base metal sheet, selectively etching to remove metal between leads, and plating with gold. Joining of the chip to the lead frame array is carried out by thermocompression bonding of mating goldplated surfaces. A small amount of silicone rubber is then applied to cover the chip and bonded joints, and the package is encapsulated with epoxy resin, applied by molding.

  12. Basic Mechanisms of Radiation Effects on Electronic Materials, Devices, and Integrated Circuits

    DTIC Science & Technology

    1982-08-01

    such changes on de’ ice properties. To gain detailed insight regarding the effects that occur when an integrated circuit is placed in a radiation...the interaction produces energetic free elec- trons. The energy range in which photoelectr~ ic collisions dominate depends on the atomic number Z of...neutron energy dependent, as discussed in Sec- ticn 3.0, this makes it difficult to compare directly results obtained by workers using different radiation

  13. Evolution of the Department of Defense Millimeter and Microwave Monolithic Integrated Circuit Program

    DTIC Science & Technology

    2007-02-01

    Dertouzos, Michael; Lester, Richard K.; Solow , Robert M.; Thorow, Lester C., “Toward a New Industrial America Scientific American, June 1989, pp...Vladimir Gelnovatch, Director of the U.S. Army Electronics Technology and Devices Laboratory; and Robert Heaston, Office of Under Secretary of Defense...Jack S. Kilby and Robert N. Noyce shared honors for the achievement. Hybrid microwave and millimeter wave integrated circuits achieved greater

  14. Protecting integrated circuits from excessive charge accumulation during plasma cleaning of multichip modules

    SciTech Connect

    Rodenbeck, Christopher T; Girardi, Michael

    2015-04-21

    Internal nodes of a constituent integrated circuit (IC) package of a multichip module (MCM) are protected from excessive charge during plasma cleaning of the MCM. The protected nodes are coupled to an internal common node of the IC package by respectively associated discharge paths. The common node is connected to a bond pad of the IC package. During MCM assembly, and before plasma cleaning, this bond pad receives a wire bond to a ground bond pad on the MCM substrate.

  15. Scalable, Lightweight, Integrated and Quick-to-Assemble (SLIQ) Hyperdrives for Functional Circuit Dissection.

    PubMed

    Liang, Li; Oline, Stefan N; Kirk, Justin C; Schmitt, Lukas Ian; Komorowski, Robert W; Remondes, Miguel; Halassa, Michael M

    2017-01-01

    Independently adjustable multielectrode arrays are routinely used to interrogate neuronal circuit function, enabling chronic in vivo monitoring of neuronal ensembles in freely behaving animals at a single-cell, single spike resolution. Despite the importance of this approach, its widespread use is limited by highly specialized design and fabrication methods. To address this, we have developed a Scalable, Lightweight, Integrated and Quick-to-assemble multielectrode array platform. This platform additionally integrates optical fibers with independently adjustable electrodes to allow simultaneous single unit recordings and circuit-specific optogenetic targeting and/or manipulation. In current designs, the fully assembled platforms are scalable from 2 to 32 microdrives, and yet range 1-3 g, light enough for small animals. Here, we describe the design process starting from intent in computer-aided design, parameter testing through finite element analysis and experimental means, and implementation of various applications across mice and rats. Combined, our methods may expand the utility of multielectrode recordings and their continued integration with other tools enabling functional dissection of intact neural circuits.

  16. Self-contained sub-millimeter wave rectifying antenna integrated circuit

    NASA Technical Reports Server (NTRS)

    Siegel, Peter H. (Inventor)

    2004-01-01

    The invention is embodied in a monolithic semiconductor integrated circuit in which is formed an antenna, such as a slot dipole antenna, connected across a rectifying diode. In the preferred embodiment, the antenna is tuned to received an electromagnetic wave of about 2500 GHz so that the device is on the order of a wavelength in size, or about 200 microns across and 30 microns thick. This size is ideal for mounting on a microdevice such as a microrobot for example. The antenna is endowed with high gain in the direction of the incident radiation by providing a quarter-wavelength (30 microns) thick resonant cavity below the antenna, the cavity being formed as part of the monolithic integrated circuit. Preferably, the integrated circuit consists of a thin gallium arsenide membrane overlying the resonant cavity and supporting an epitaxial Gallium Arsenide semiconductor layer. The rectifying diode is a Schottky diode formed in the GaAs semiconductor layer and having an area that is a very small fraction of the wavelength of the 2500 GHz incident radiation. The cavity provides high forward gain in the antenna and isolation from surrounding structure.

  17. Multi-level interconnects for heterojunction bipolar transistor integrated circuit technologies

    SciTech Connect

    Patrizi, G.A.; Lovejoy, M.L.; Schneider, R.P. Jr.; Hou, H.Q.; Enquist, P.M.

    1995-12-31

    Heterojunction bipolar transistors (HBTs) are mesa structures which present difficult planarization problems in integrated circuit fabrication. The authors report a multilevel metal interconnect technology using Benzocyclobutene (BCB) to implement high-speed, low-power photoreceivers based on InGaAs/InP HBTs. Processes for patterning and dry etching BCB to achieve smooth via holes with sloped sidewalls are presented. Excellent planarization of 1.9 {micro}m mesa topographies on InGaAs/InP device structures is demonstrated using scanning electron microscopy (SEM). Additionally, SEM cross sections of both the multi-level metal interconnect via holes and the base emitter via holes required in the HBT IC process are presented. All via holes exhibit sloped sidewalls with slopes of 0.4 {micro}m/{micro}m to 2 {micro}m/{micro}m which are needed to realize a robust interconnect process. Specific contact resistances of the interconnects are found to be less than 6 {times} 10{sup {minus}8} {Omega}cm{sup 2}. Integrated circuits utilizing InGaAs/InP HBTs are fabricated to demonstrate the applicability and compatibility of the multi-level interconnect technology with integrated circuit processing.

  18. Scalable, Lightweight, Integrated and Quick-to-Assemble (SLIQ) Hyperdrives for Functional Circuit Dissection

    PubMed Central

    Liang, Li; Oline, Stefan N.; Kirk, Justin C.; Schmitt, Lukas Ian; Komorowski, Robert W.; Remondes, Miguel; Halassa, Michael M.

    2017-01-01

    Independently adjustable multielectrode arrays are routinely used to interrogate neuronal circuit function, enabling chronic in vivo monitoring of neuronal ensembles in freely behaving animals at a single-cell, single spike resolution. Despite the importance of this approach, its widespread use is limited by highly specialized design and fabrication methods. To address this, we have developed a Scalable, Lightweight, Integrated and Quick-to-assemble multielectrode array platform. This platform additionally integrates optical fibers with independently adjustable electrodes to allow simultaneous single unit recordings and circuit-specific optogenetic targeting and/or manipulation. In current designs, the fully assembled platforms are scalable from 2 to 32 microdrives, and yet range 1–3 g, light enough for small animals. Here, we describe the design process starting from intent in computer-aided design, parameter testing through finite element analysis and experimental means, and implementation of various applications across mice and rats. Combined, our methods may expand the utility of multielectrode recordings and their continued integration with other tools enabling functional dissection of intact neural circuits. PMID:28243194

  19. Molten-Caustic-Leaching (Gravimelt) System Integration Project, Phase 2. Topical report for test circuit operation

    SciTech Connect

    Not Available

    1993-02-01

    The objective of the task (Task 6) covered in this document was to operate the refurbished/modified test circuit of the Gravimeh Process in a continuous integrated manner to obtain the engineering and operational data necessary to assess the technical performance and reliability of the circuit. This data is critical to the development of this technology as a feasible means of producing premium clean burning fuels that meet New Source Performance Standards (NSPS). Significant refurbishments and design modifications had been made to the facility (in particular to the vacuum filtration and evaporation units) during Tasks 1 and 2, followed by off-line testing (Task 3). Two weeks of continuous around-the-clock operation of the refurbished/modified MCL test circuit were performed. During the second week of testing, all sections of the plant were operated in an integrated fashion for an extended period of time, including a substantial number of hours of on-stream time for the vacuum filters and the caustic evaporation unit. A new process configuration was tested in which centrate from the acid wash train (without acid addition) was used as the water makeup for the water wash train, thus-eliminating the one remaining process waste water stream. A 9-inch centrifuge was tested at various solids loadings and at flow rates up to 400 lbs/hr of coal feed to obtain a twenty-fold scaleup factor over the MCL integrated test facility centrifuge performance data.

  20. Three-dimensional integration (3DI) of semiconductor circuit layers: New devices and fabrication process

    NASA Astrophysics Data System (ADS)

    Sehari, Babak E.

    1998-12-01

    The device density of Integrated Circuits (ICs) manufactured by current VLSI technology is reaching its theoretical limit. Nevertheless, the demand for integration of more devices per chip is growing. To accommodate this need three main possibilities can be explored: Wafer Scale Integration (WSI), Ultra Large Scale Integration (ULSI), and Three Dimensional Integration (3DI). A brief review of these techniques along with their comparative advantages and disadvantages is presented. It has been concluded that 3DI technology is superior to others. Therefore, an attempt is made to develop a viable fabrication process for this technology. This is done by first reviewing the current technologies that are utilized for fabrication of Integrated Circuits (ICs) and their compatibility with 3DI stringent requirements. Based on this review, a set of fabrication procedure for realization of 3DI technology, are presented in chapter 3. In Chapter 1 the compatibility of the currently used devices, such as BJTs and FETs, with 3DI technology is examined. Moreover, a new active device is developed for 3DI technology to replace BJTs and FETs in circuits. This new device is more compatible to the constrains of 3DI technology. Chapter 2 is devoted to solving the overall problems of 3DI circuits. The problem of heat and power dispassion and signal coupling (Cross-Talk) between the layers are reviewed, and an inter-layer shield is proposed to overcome these problems. The effectiveness of such a thin shield is considered theoretically. In Chapter 3 a fabrication process for 3DI technology is proposed. This is done after a short analysis of previous attempts in developing 3DI technologies. Chapter 4 focuses on analog extension of 3DI technology. Moreover, in this chapter microwave 3DI circuits or 3DI MMIC is investigated. Practical considerations in choice of material for the proposed device is the subject of study in Chapter 5. Low temperature ohmic contact and utilization of metal

  1. Integrated Flight and Propulsion Controls for Advanced Aircraft Configurations

    NASA Technical Reports Server (NTRS)

    Merrill, Walter; Garg, Sanjay

    1995-01-01

    The research vision of the NASA Lewis Research Center in the area of integrated flight and propulsion controls technologies is described. In particular the Integrated Method for Propulsion and Airframe Controls developed at the Lewis Research Center is described including its application to an advanced aircraft configuration. Additionally, future research directions in integrated controls are described.

  2. Integrated Cryogenic Electronics Testbed (ICE-T) for Evaluation of Superconductor and Cryo-Semiconductor Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Dotsenko, V. V.; Sahu, A.; Chonigman, B.; Tang, J.; Lehmann, A. E.; Gupta, V.; Talalevskii, A.; Ruotolo, S.; Sarwana, S.; Webber, R. J.; Gupta, D.

    2017-02-01

    Research and development of cryogenic application-specific integrated circuits (ASICs), such as high-frequency (tens of GHz) semiconductor and superconductor mixed-signal circuits and large-scale (>10,000 Josephson Junctions) superconductor digital circuits, have long been hindered by the absence of specialized cryogenic test apparatus. During their iterative development phase, most ASICs require many additional input-output lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. We are developing a full suite of modular test apparatus based on cryocoolers that do not consume liquid helium, and support extensive electrical interfaces to standard and custom test equipment. Our design separates the cryogenics from electrical connections, allowing even inexperienced users to conduct testing by simply mounting their ASIC on a removable electrical insert. Thermal connections between the cold stages and the inserts are made with robust thermal links. ICE-T accommodates two independent electrical inserts at the same time. We have designed various inserts, such as universal ones with all 40 or 80 coaxial cables and those with customized wiring and temperature-controlled stages. ICE-T features fast thermal cycling for rapid testing, enables detailed testing over long periods (days to months, if necessary), and even supports automated testing of digital ICs with modular additions.

  3. Dielectric Spectroscopic Detection of Early Failures in 3-D Integrated Circuits

    PubMed Central

    Okoro, C. A.; Ahn, Jung-Joon; You, Lin; Kopanski, Joseph J.

    2015-01-01

    The commercial introduction of three dimensional integrated circuits (3D-ICs) has been hindered by reliability challenges, such as stress related failures, resistivity changes, and unexplained early failures. In this paper, we discuss a new RF-based metrology, based on dielectric spectroscopy, for detecting and characterizing electrically active defects in fully integrated 3D devices. These defects are traceable to the chemistry of the insolation dielectrics used in the through silicon via (TSV) construction. We show that these defects may be responsible for some of the unexplained early reliability failures observed in TSV enabled 3D devices. PMID:26664695

  4. Hybrid-integrated coherent receiver using silica-based planar lightwave circuit technology

    NASA Astrophysics Data System (ADS)

    Kim, Jong-Hoi; Choe, Joong-Seon; Choi, Kwang-Seong; Youn, Chun-Ju; Kim, Duk-Jun; Jang, Sun-Hyok; Kwon, Yong-Hwan; Nam, Eun-Soo

    2011-12-01

    A hybrid-integrated coherent receiver module has been achieved using flip-chip bonding technology, consisting of a silica-based 90°-hybrid planar lightwave circuit (PLC) platform, a spot-size converter integrated waveguide photodiode (SSC-WG-PD), and a dual-channel transimpedance amplifier (TIA). The receiver module shows error-free operation up to 40Gb/s and OSNR sensitivity of 11.5 dB for BER = 10-3 at 25 Gb/s.

  5. Comparison of a new integrated current source with the modified Howland circuit for EIT applications.

    PubMed

    Hong, Hongwei; Rahal, Mohamad; Demosthenous, Andreas; Bayford, Richard H

    2009-10-01

    Multi-frequency electrical impedance tomography (MF-EIT) systems require current sources that are accurate over a wide frequency range (1 MHz) and with large load impedance variations. The most commonly employed current source design in EIT systems is the modified Howland circuit (MHC). The MHC requires tight matching of resistors to achieve high output impedance and may suffer from instability over a wide frequency range in an integrated solution. In this paper, we introduce a new integrated current source design in CMOS technology and compare its performance with the MHC. The new integrated design has advantages over the MHC in terms of power consumption and area. The output current and the output impedance of both circuits were determined through simulations and measurements over the frequency range of 10 kHz to 1 MHz. For frequencies up to 1 MHz, the measured maximum variation of the output current for the integrated current source is 0.8% whereas for the MHC the corresponding value is 1.5%. Although the integrated current source has an output impedance greater than 1 MOmega up to 1 MHz in simulations, in practice, the impedance is greater than 160 kOmega up to 1 MHz due to the presence of stray capacitance.

  6. Design, Fabrication and Integration of a NaK-Cooled Circuit

    NASA Technical Reports Server (NTRS)

    Garber, Anne; Godfroy, Thomas

    2006-01-01

    The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed for use with a eutectic mixture of sodium potassium (NaK), was redesigned to for use with lithium. Due to a shi$ in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature circuit include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a fill design) was selected for fabrication and test. This paper summarizes the integration and preparations for the fill of the pumped liquid metal NaK flow circuit.

  7. Layout-aware simulation of soft errors in sub-100 nm integrated circuits

    NASA Astrophysics Data System (ADS)

    Balbekov, A.; Gorbunov, M.; Bobkov, S.

    2016-12-01

    Single Event Transient (SET) caused by charged particle traveling through the sensitive volume of integral circuit (IC) may lead to different errors in digital circuits in some cases. In technologies below 180 nm, a single particle can affect multiple devices causing multiple SET. This fact adds the complexity to fault tolerant devices design, because the schematic design techniques become useless without their layout consideration. The most common layout mitigation technique is a spatial separation of sensitive nodes of hardened circuits. Spatial separation decreases the circuit performance and increases power consumption. Spacing should thus be reasonable and its scaling follows the device dimensions' scaling trend. This paper presents the development of the SET simulation approach comprised of SPICE simulation with "double exponent" current source as SET model. The technique uses layout in GDSII format to locate nearby devices that can be affected by a single particle and that can share the generated charge. The developed software tool automatizes multiple simulations and gathers the produced data to present it as the sensitivity map. The examples of conducted simulations of fault tolerant cells and their sensitivity maps are presented in this paper.

  8. Design, Fabrication and Integration of a NaK-Cooled Circuit

    SciTech Connect

    Garber, Anne; Godfroy, Thomas

    2006-07-01

    The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed for use with a eutectic mixture of sodium potassium (NaK), was redesigned for use with lithium. Due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature circuit include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This paper summarizes the integration and preparations for the fill of the pumped NaK circuit. (authors)

  9. Erbium-doped zinc-oxide waveguide amplifiers for hybrid photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    O'Neal, Lawrence; Anthony, Deion; Bonner, Carl; Geddis, Demetris

    2016-02-01

    CMOS logic circuits have entered the sub-100nm regime, and research is on-going to investigate the quantum effects that are apparent at this dimension. To avoid some of the constraints imposed by fabrication, entropy, energy, and interference considerations for nano-scale devices, many have begun designing hybrid and/or photonic integrated circuits. These circuits consist of transistors, light emitters, photodetectors, and electrical and optical waveguides. As attenuation is a limiting factor in any communications system, it is advantageous to integrate a signal amplifier. There are numerous examples of electrical amplifiers, but in order to take advantage of the benefits provided by optically integrated systems, optical amplifiers are necessary. The erbium doped fiber amplifier is an example of an optical amplifier which is commercially available now, but the distance between the amplifier and the device benefitting from amplification can be decreased and provide greater functionality by providing local, on-chip amplification. Zinc oxide is an attractive material due to its electrical and optical properties. Its wide bandgap (≍3.4 eV) and high refractive index (≍2) make it an excellent choice for integrated optics systems. Moreover, erbium doped zinc oxide (Er:ZnO) is a suitable candidate for optical waveguide amplifiers because of its compatibility with semiconductor processing technology, 1.54 μm luminescence, transparency, low resistivity, and amplification characteristics. This research presents the characterization of radio frequency magnetron sputtered Er:ZnO, the design and fabrication of integrated waveguide amplifiers, and device analysis.

  10. Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

    PubMed Central

    Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

    2013-01-01

    A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

  11. 6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.; Prokop, Norman F.

    2008-01-01

    The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the approximately 300 degrees Centigrade effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation in such harsh environments. This paper reports on the fabrication and long-term 500 degrees Centigrade operation of 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs have now demonstrated thousands of hours of continuous 500 degrees Centigrade operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Electrical characterization and modeling of transistors and circuits at temperatures from 24 degrees Centigrade to 500 degrees Centigrade is also described. Desired analog and digital IC functionality spanning this temperature range was demonstrated without changing the input signals or power supply voltages.

  12. A combined noise analysis and power supply current based testing of CMOS analog integrated circuits

    NASA Astrophysics Data System (ADS)

    Srivastava, Ashok; Pulendra, Vani K.; Yellampalli, Siva

    2005-05-01

    A technique integrating the noise analysis based testing and the conventional power supply current testing of CMOS analog integrated circuits is presented for bridging type faults due to manufacturing defects. The circuit under test (CUT) is a CMOS amplifier designed for operation at +/- 2.5 V and implemented in 1.5 μm CMOS process. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. The amplifier circuit is analyzed and simulated in SPICE for its performance with and without fault injections. The faults in the CUT are identified by observing the variation in the equivalent noise voltage at the output of CUT. In power supply current testing, the current (IPS) through the power supply voltage, VDD is measured under the application of an AC input stimulus. The effect of parametric variation is taken into consideration by determining the tolerance limit using the Monte-Carlo analysis. The fault is identified if the power supply current, IPS lies outside the deviation given by Monte-Carlo analysis. Simulation results are in close agreement with the corresponding experimental values.

  13. A contact lens with integrated telecommunication circuit and sensors for wireless and continuous tear glucose monitoring

    NASA Astrophysics Data System (ADS)

    Yao, H.; Liao, Y.; Lingley, A. R.; Afanasiev, A.; Lähdesmäki, I.; Otis, B. P.; Parviz, B. A.

    2012-07-01

    We present an integrated functional contact lens, composed of a differential glucose sensor module, metal interconnects, sensor read-out circuit, antenna and telecommunication circuit, to monitor tear glucose levels wirelessly, continuously and non-invasively. The electrochemical differential sensor module is based on immobilization of activated and de-activated glucose oxidase. We characterized the sensor on a model polymer eye and determined that it showed good repeatability, molecular interference rejection and linearity in the range of 0-2 mM glucose, covering normal tear glucose concentrations (0.1-0.6 mM). We also report the temperature, ageing and protein-fouling sensitivity of the sensor. We report the design and implementation of a low-power (3 µW) sensor read-out and telecommunication circuit to deliver wireless power and transmit data for the sensor module. Using this small chip (0.36 mm2), we produced an integrated contact lens with sensors and demonstrated wireless operation of the system and glucose read-out over the distance of several centimeters.

  14. Development of a universal serial bus interface circuit for ion beam current integrators.

    PubMed

    Suresh, K; Panigrahi, B K; Nair, K G M

    2007-08-01

    A universal serial bus (USB) interface circuit has been developed to enable easy interfacing of commercial as well as custom-built ion beam current integrators to personal computer (PC) based automated experimental setups. Built using the popular PIC16F877A reduced instruction set computer and a USB-universal asynchronous receiver-transmitter/first in, first out controller, DLP2232, this USB interface circuit virtually emulates the ion beam current integrators on a host PC and uses USB 2.0 protocol to implement high speed bidirectional data transfer. Using this interface, many tedious and labor intensive ion beam irradiation and characterization experiments can be redesigned into PC based automated ones with advantages of improved accuracy, rapidity, and ease of use and control. This interface circuit was successfully used in carrying out online in situ resistivity measurement of 70 keV O(+) ion irradiated tin thin films using four probe method. In situ electrical resistance measurement showed the formation of SnO(2) phase during ion implantation.

  15. The neural circuits of innate fear: detection, integration, action, and memorization.

    PubMed

    Silva, Bianca A; Gross, Cornelius T; Gräff, Johannes

    2016-10-01

    How fear is represented in the brain has generated a lot of research attention, not only because fear increases the chances for survival when appropriately expressed but also because it can lead to anxiety and stress-related disorders when inadequately processed. In this review, we summarize recent progress in the understanding of the neural circuits processing innate fear in rodents. We propose that these circuits are contained within three main functional units in the brain: a detection unit, responsible for gathering sensory information signaling the presence of a threat; an integration unit, responsible for incorporating the various sensory information and recruiting downstream effectors; and an output unit, in charge of initiating appropriate bodily and behavioral responses to the threatful stimulus. In parallel, the experience of innate fear also instructs a learning process leading to the memorization of the fearful event. Interestingly, while the detection, integration, and output units processing acute fear responses to different threats tend to be harbored in distinct brain circuits, memory encoding of these threats seems to rely on a shared learning system.

  16. The neural circuits of innate fear: detection, integration, action, and memorization

    PubMed Central

    Silva, Bianca A.; Gross, Cornelius T.

    2016-01-01

    How fear is represented in the brain has generated a lot of research attention, not only because fear increases the chances for survival when appropriately expressed but also because it can lead to anxiety and stress-related disorders when inadequately processed. In this review, we summarize recent progress in the understanding of the neural circuits processing innate fear in rodents. We propose that these circuits are contained within three main functional units in the brain: a detection unit, responsible for gathering sensory information signaling the presence of a threat; an integration unit, responsible for incorporating the various sensory information and recruiting downstream effectors; and an output unit, in charge of initiating appropriate bodily and behavioral responses to the threatful stimulus. In parallel, the experience of innate fear also instructs a learning process leading to the memorization of the fearful event. Interestingly, while the detection, integration, and output units processing acute fear responses to different threats tend to be harbored in distinct brain circuits, memory encoding of these threats seems to rely on a shared learning system. PMID:27634145

  17. The advanced microgrid. Integration and interoperability

    SciTech Connect

    Bower, Ward Isaac; Ton, Dan T.; Guttromson, Ross; Glover, Steven F; Stamp, Jason Edwin; Bhatnagar, Dhruv; Reilly, Jim

    2014-02-01

    This white paper focuses on "advanced microgrids," but sections do, out of necessity, reference today's commercially available systems and installations in order to clearly distinguish the differences and advances. Advanced microgrids have been identified as being a necessary part of the modern electrical grid through a two DOE microgrid workshops, the National Institute of Standards and Technology, Smart Grid Interoperability Panel and other related sources. With their grid-interconnectivity advantages, advanced microgrids will improve system energy efficiency and reliability and provide enabling technologies for grid-independence to end-user sites. One popular definition that has been evolved and is used in multiple references is that a microgrid is a group of interconnected loads and distributed-energy resources within clearly defined electrical boundaries that acts as a single controllable entity with respect to the grid. A microgrid can connect and disconnect from the grid to enable it to operate in both grid-connected or island-mode. Further, an advanced microgrid can then be loosely defined as a dynamic microgrid.

  18. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

    PubMed Central

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-01

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits. PMID:24463956

  19. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

    NASA Astrophysics Data System (ADS)

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-01

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

  20. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

    PubMed

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-27

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

  1. A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip.

    PubMed

    Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

    2011-01-01

    A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

  2. Neural CMOS-integrated circuit and its application to data classification.

    PubMed

    Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

    2012-05-01

    Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

  3. Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

    PubMed

    Chen, Guanyu; Yu, Yu; Zhang, Xinliang

    2016-08-01

    We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers.

  4. 60-GHz integrated-circuit high data rate quadriphase shift keying exciter and modulator

    NASA Technical Reports Server (NTRS)

    Grote, A.; Chang, K.

    1984-01-01

    An integrated-circuit quadriphase shift keying (QPSK) exciter and modulator have demonstrated excellent performance directly modulating a carrier frequency of 60 GHz with an output phase error of less than 3 degrees and maximum amplitude error of 0.5 dB. The circuit consists of a 60-GHz Gunn VCO phase-locked to a low-frequency reference source, a 4th subharmonic mixer, and a QPSK modlator packaged into a small volume of 1.8 x 2.5 x 0.35 in. The use of microstrip has the advantages of small size, light-weight, and low-cost fabrication. The unit has the potential for multigigabit data rate applications.

  5. Basic dynamics from a pulse-coupled network of autonomous integrate-and-fire chaotic circuits.

    PubMed

    Nakano, H; Saito, T

    2002-01-01

    This paper studies basic dynamics from a novel pulse-coupled network (PCN). The unit element of the PCN is an integrate-and-fire circuit (IFC) that exhibits chaos. We an give an iff condition for the chaos generation. Using two IFC, we construct a master-slave PCN. It exhibits interesting chaos synchronous phenomena and their breakdown phenomena. We give basic classification of the phenomena and their existence regions can be elucidated in the parameter space. We then construct a ring-type PCN and elucidate that the PCN exhibits interesting grouping phenomena based on the chaos synchronization patterns. Using a simple test circuit, some of typical phenomena can be verified in the laboratory.

  6. Fiber optic gyroscope using an eight-component LiNbO3 integrated optic circuit

    NASA Technical Reports Server (NTRS)

    Minford, W. J.; Stone, F. T.; Youmans, B. R.; Bartman, R. K.

    1990-01-01

    A LiNbO3 integrated optic circuit (IOC) containing eight optical functions has been successfully incorporated into an interferometric fiber optic gyroscope. The IOC has the minimum configuration optical functions (a phase modulator, a polarizer, and two beam splitters) and Jet Propulsion Laboratory's novel beat detection circuit (a phase modulator, two optical taps, and a beam splitter) which provides a means of directly reading angular position and rotation rate. The optical subsystem consisting of the fiber-pigtailed IOC and a sensing coil of 945 meters of polarization-maintaining fiber has a loss of 18.7dB, which includes 9dB due to the architecture and unpolarized source. A random walk coefficient was measured using an edge-emitting LED as the source.

  7. Grounding positions of superconducting layer for effective magnetic isolation in Josephson integrated circuits

    NASA Astrophysics Data System (ADS)

    Mizugaki, Yoshinao; Kashiwa, Ryuta; Moriya, Masataka; Usami, Kouichi; Kobayashi, Tadayuki

    2007-06-01

    Mutual inductances between two superconducting strip lines coupled through a grounded shield layer are evaluated by both experiments and numerical calculation. A conventional superconducting quantum interference device method on a Nb Josephson integrated circuit chip is employed for experiments. Four test circuits are designed to investigate the effects of ground contacts. Grounding the shield layer at one point or at two points located perpendicular to the line direction does not improve the shielding effect, whereas grounding at two points located parallel to the line direction reduced the mutual inductance by 67%. Mutual inductances calculated using an inductance extraction program, FASTHENRY, agree with the experimental results. Numerical results of current distributions in the shield layers demonstrate that the enhanced shielding current improves the magnetic isolation.

  8. Single-Event Upset and Snapback in Silicon-on-Insulator Devices and Integrated Circuits

    SciTech Connect

    DODD,PAUL E.; SHANEYFELT,MARTY R.; WALSH,DAVID S.; SCHWANK,JAMES R.; HASH,GERALD L.; LOEMKER,RHONDA ANN; DRAPER,BRUCE L.; WINOKUR,PETER S.

    2000-08-15

    The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-Dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMS, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMS is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

  9. A Zinc Oxide Nanorod Ammonia Microsensor Integrated with a Readout Circuit on-a-Chip

    PubMed Central

    Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

    2011-01-01

    A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature. PMID:22247656

  10. Microwave integrated circuit radiometer front-ends for the Push Broom Microwave Radiometer

    NASA Technical Reports Server (NTRS)

    Harrington, R. F.; Hearn, C. P.

    1982-01-01

    Microwave integrated circuit front-ends for the L-band, S-band and C-band stepped frequency null-balanced noise-injection Dicke-switched radiometer to be installed in the NASA Langley airborne prototype Push Broom Microwave Radiometer (PBMR) are described. These front-ends were developed for the fixed frequency of 1.413 GHz and the variable frequencies of 1.8-2.8 GHz and 3.8-5.8 GHz. Measurements of the noise temperature of these units were made at 55.8 C, and the results of these tests are given. While the overall performance was reasonable, improvements need to be made in circuit losses and noise temperatures, which in the case of the C-band were from 1000 to 1850 K instead of the 500 K specified. Further development of the prototypes is underway to improve performance and extend the frequency range.

  11. A SQUID gradiometer module with wire-wound pickup antenna and integrated voltage feedback circuit

    NASA Astrophysics Data System (ADS)

    Zhang, Guofeng; Zhang, Yi; Zhang, Shulin; Krause, Hans-Joachim; Wang, Yongliang; Liu, Chao; Zeng, Jia; Qiu, Yang; Kong, Xiangyan; Dong, Hui; Xie, Xiaoming; Offenhäusser, Andreas; Jiang, Mianheng

    2012-10-01

    The performance of the direct readout schemes for dc SQUID, Additional Positive Feedback (APF), noise cancellation (NC) and SQUID bootstrap circuit (SBC), have been studied in conjunction with planar SQUID magnetometers. In this paper, we examine the NC technique applied to a niobium SQUID gradiometer module with an Nb wire-wound antenna connecting to a dual-loop SQUID chip with an integrated voltage feedback circuit for suppression of the preamplifier noise contribution. The sensitivity of the SQUID gradiometer module is measured to be about 1 fT/(cm √Hz) in the white noise range in a magnetically shielded room. Using such gradiometer, both MCG and MEG signals are recorded.

  12. A prediction technique for single-event effects on complex integrated circuits

    NASA Astrophysics Data System (ADS)

    Yuanfu, Zhao; Chunqing, Yu; Long, Fan; Suge, Yue; Maoxin, Chen; Shougang, Du; Hongchao, Zheng

    2015-11-01

    The sensitivity of complex integrated circuits to single-event effects is investigated. Sensitivity depends not only on the cross section of physical modules but also on the behavior of data patterns running on the system. A method dividing the main functional modules is proposed. The intrinsic cross section and the duty cycles of different sensitive modules are obtained during the execution of data patterns. A method for extracting the duty cycle is presented and a set of test patterns with different duty cycles are implemented experimentally. By combining the intrinsic cross section and the duty cycle of different sensitive modules, a universal method to predict SEE sensitivities of different test patterns is proposed, which is verified by experiments based on the target circuit of a microprocessor. Experimental results show that the deviation between prediction and experiment is less than 20%.

  13. Charge Yield at Low Electric Fields: Considerations for Bipolar Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2013-01-01

    A significant reduction in total dose damage is observed when bipolar integrated circuits are irradiated at low temperature. This can be partially explained by the Onsager theory of recombination, which predicts a strong temperature dependence for charge yield under low-field conditions. Reduced damage occurs for biased as well as unbiased devices because the weak fringing field in thick bipolar oxides only affects charge yield near the Si/SiO2 interface, a relatively small fraction of the total oxide thickness. Lowering the temperature of bipolar ICs - either continuously, or for time periods when they are exposed to high radiation levels - provides an additional degree of freedom to improve total dose performance of bipolar circuits, particularly in space applications.

  14. Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith Roger D.; Ferrier, Terry L.; Krasowski, Michael J.; Prokop, Norman F.

    2008-01-01

    NASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

  15. Theoretical investigation of a class of new planar transmission lines from microwave and millimeter-wave integrated circuits

    NASA Astrophysics Data System (ADS)

    Hsu, Pang-Cheng; Nguyen, Cam

    1995-10-01

    New planar transmission lines employing multilayer structures are examined for possible applications in microwave and millimeter-wave integrated circuits. Detailed investigations are presented through numerical results calculated using the spectral domain technique. The newly proposed transmission lines have many attractive features such as large impedance ranges, flexibility and the ability to realize complicated, densely packed integrated circuits, as well as miniaturization through the use of thin dielectric layers.

  16. Cascade photonic integrated circuit architecture for electro-optic in-phase quadrature/single sideband modulation or frequency conversion.

    PubMed

    Hasan, Mehedi; Hall, Trevor

    2015-11-01

    A photonic integrated circuit architecture for implementing frequency upconversion is proposed. The circuit consists of a 1×2 splitter and 2×1 combiner interconnected by two stages of differentially driven phase modulators having 2×2 multimode interference coupler between the stages. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. The intrinsic conversion efficiency of the proposed design is improved by 6 dB over the alternative functionally equivalent circuit based on dual parallel Mach-Zehnder modulators known in the prior art. A two-tone analysis is presented to study the linearity of the proposed circuit, and a comparison is provided over the alternative. The proposed circuit is suitable for integration in any platform that offers linear electro-optic phase modulation such as LiNbO(3), silicon, III-V, or hybrid technology.

  17. A 200 C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

    SciTech Connect

    Tolbert, Leon M; Huque, Mohammad A; Islam, Syed K; Blalock, Benjamin J

    2012-01-01

    High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 C. This new gate driver prototype has been designed and implemented in a 0.8 {micro}m, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature ({ge}220 C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 {micro}W for operating temperature up to 200 C.

  18. Integrating Language Lab Materials into Advanced Russian.

    ERIC Educational Resources Information Center

    Allar, Gregory

    1986-01-01

    Describes the use of language lab materials supplied by the pedagogical journal "Russkij Jazyk Za Rubezom" in an advanced Russian-language class. Each week students were given a relevant picture and vocabulary list prior to listening to a taped story. The story was used as the basis for conversation. (LMO)

  19. Modeling and profile simulation of silicon and metal etching in integrated circuit manufacturing

    NASA Astrophysics Data System (ADS)

    Zheng, Jie

    1998-12-01

    Plasma etching is one of the semiconductor processing technologies, which has advanced tremendously over the last decade in order to meet the demands of ever increasing density of devices manufacturable in integrated circuits. A plasma etch process is usually based on a combination of chemical and physical mechanisms and has to be developed case by case in order to meet the specific demands of a process flow. Most of these processes have been accomplished by using low pressure discharge plasma systems. However, because of the complexities of such systems and our limited understanding of the many types of discharge plasmas and plasma surface interactions, a good amount of the process development work has been done on an empirical basis. This thesis is built upon the development and applications of SPEEDIE, the Stanford etching and deposition profile simulator, which is aimed at helping process engineers to develop and understand plasma etch processes. It starts with an introduction to semiconductor processing, which focuses on etching and discusses about the many requirements a good etching process has to meet. A detailed description of etching plasmas and the etching plasma systems follows after this introduction. We then give an overview of the SPEEDIE program, which covers the flow structure, the physics and the mathematics behind the basic part of the codes and the surface movement algorithm. The rest of the thesis is a demonstration of how SPEEDIE can be applied to various cases such as silicon and metal etching. These applications have lead to the discovery of the effect of the pre-sheath of a discharge plasma on the ion angular and energy distributions at the wafer surface. We have also clarified a few concepts associated with energetic ion assisted surface reactions. We have found that the surface catalyzed reactive species recombination is crucial to explain the strong aspect ratio dependency during metal etching. SPEEDIE is shown here to produce many

  20. Open access to technology platforms for InP-based photonic integrated circuits

    NASA Astrophysics Data System (ADS)

    Ławniczuk, Katarzyna; Augustin, Luc M.; Grote, Norbert; Wale, Michael J.; Smit, Meint K.; Williams, Kevin A.

    2015-04-01

    Open access to generic technology platforms for photonic integrated circuit manufacturing enables low-cost development of application-specific photonic chips for novel or improved products. It brings photonic ICs within reach for many industrial users and research institutes, by moving toward a fabless business model. In the current status, InP-based open access manufacturing services are offered through multi-project wafer runs by Fraunhofer Heinrich Hertz Institut, SMART Photonics, and Oclaro. In this paper, we review state-of-the-art InP photonic integration technology platforms, present examples of complex InP photonic ICs developed in the generic technologies, and give a prospect for further development of these photonic integration platforms.