Dielectric collapse at the LaAlO 3/SrTiO 3 (001) heterointerface under applied electric field

DOE PAGES

Minohara, M.; Hikita, Y.; Bell, C.; ...

2017-08-25

The fascinating interfacial transport properties at the LaAlO 3/SrTiO 3 heterointerface have led to intense investigations of this oxide system. Exploiting the large dielectric constant of SrTiO 3 at low temperatures, tunability in the interfacial conductivity over a wide range has been demonstrated using a back-gate device geometry. In order to understand the effect of back-gating, it is crucial to assess the interface band structure and its evolution with external bias. In this study, we report measurements of the gate-bias dependent interface band alignment, especially the confining potential profile, at the conducting LaAlO 3/SrTiO 3 (001) heterointerface using soft andmore » hard x-ray photoemission spectroscopy in conjunction with detailed model simulations. Depth-profiling analysis incorporating the electric field dependent dielectric constant in SrTiO 3 reveals that a significant potential drop on the SrTiO 3 side of the interface occurs within ~2 nm of the interface under negative gate-bias. These results demonstrate gate control of the collapse of the dielectric permittivity at the interface, and explain the dramatic loss of electron mobility with back-gate depletion.« less

Electrical characterization of amorphous Al2O3 dielectric films on n-type 4H-SiC

NASA Astrophysics Data System (ADS)

Khosa, R. Y.; Thorsteinsson, E. B.; Winters, M.; Rorsman, N.; Karhu, R.; Hassan, J.; Sveinbjörnsson, E. Ö.

2018-02-01

We report on the electrical properties of Al2O3 films grown on 4H-SiC by successive thermal oxidation of thin Al layers at low temperatures (200°C - 300°C). MOS capacitors made using these films contain lower density of interface traps, are more immune to electron injection and exhibit higher breakdown field (5MV/cm) than Al2O3 films grown by atomic layer deposition (ALD) or rapid thermal processing (RTP). Furthermore, the interface state density is significantly lower than in MOS capacitors with nitrided thermal silicon dioxide, grown in N2O, serving as the gate dielectric. Deposition of an additional SiO2 film on the top of the Al2O3 layer increases the breakdown voltage of the MOS capacitors while maintaining low density of interface traps. We examine the origin of negative charges frequently encountered in Al2O3 films grown on SiC and find that these charges consist of trapped electrons which can be released from the Al2O3 layer by depletion bias stress and ultraviolet light exposure. This electron trapping needs to be reduced if Al2O3 is to be used as a gate dielectric in SiC MOS technology.

Reduced electron back-injection in Al2O3/AlOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Min Kim, Sung; Lee, Youngmin; Seo, David H.; Seo, Sunae; Wang, Kang L.

2012-12-01

A graphene charge-trap memory is devised using a single-layer graphene channel with an Al2O3/AlOx/Al2O3 oxide stack, where the ion-bombarded AlOx layer is intentionally added to create an abundance of charge-trap sites. The low dielectric constant of AlOx compared to Al2O3 reduces the potential drop in the control oxide Al2O3 and suppresses the electron back-injection from the gate to the charge-storage layer, allowing the memory window of the device to be further extended. This shows that the usage of a lower dielectric constant in the charge-storage layer compared to that of the control oxide layer improves the memory performance for graphene charge-trap memories.

Impact of oxygen precursor flow on the forward bias behavior of MOCVD-Al2O3 dielectrics grown on GaN

NASA Astrophysics Data System (ADS)

Chan, Silvia H.; Bisi, Davide; Liu, Xiang; Yeluri, Ramya; Tahhan, Maher; Keller, Stacia; DenBaars, Steven P.; Meneghini, Matteo; Mishra, Umesh K.

2017-11-01

This paper investigates the effects of the oxygen precursor flow supplied during metalorganic chemical vapor deposition (MOCVD) of Al2O3 films on the forward bias behavior of Al2O3/GaN metal-oxide-semiconductor capacitors. The low oxygen flow (100 sccm) delivered during the in situ growth of Al2O3 on GaN resulted in films that exhibited a stable capacitance under forward stress, a lower density of stress-generated negative fixed charges, and a higher dielectric breakdown strength compared to Al2O3 films grown under high oxygen flow (480 sccm). The low oxygen grown Al2O3 dielectrics exhibited lower gate current transients in stress/recovery measurements, providing evidence of a reduced density of trap states near the GaN conduction band and an enhanced robustness under accumulated gate stress. This work reveals oxygen flow variance in MOCVD to be a strategy for controlling the dielectric properties and performance.

Dependence of electrical and time stress in organic field effect transistor with low temperature forming gas treated Al2O3 gate dielectrics.

PubMed

Lee, Sunwoo; Chung, Keum Jee; Park, In-Sung; Ahn, Jinho

2009-12-01

We report the characteristics of the organic field effect transistor (OFET) after electrical and time stress. Aluminum oxide (Al2O3) was used as a gate dielectric layer. The surface of the gate oxide layer was treated with hydrogen (H2) and nitrogen (N2) mixed gas to minimize the dangling bond at the interface layer of gate oxide. According to the two stress parameters of electrical and time stress, threshold voltage shift was observed. In particular, the mobility and subthreshold swing of OFET were significantly decreased due to hole carrier localization and degradation of the channel layer between gate oxide and pentacene by electrical stress. Electrical stress is a more critical factor in the degradation of mobility than time stress caused by H2O and O2 in the air.

Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics.

PubMed

Alshammari, Fwzah H; Nayak, Pradipta K; Wang, Zhenwei; Alshareef, Husam N

2016-09-07

We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm(2) V(-1) s(-1), but increased to 13.3 cm(2) V(-1) s(-1) using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance.

Titanium-tungsten nanocrystals embedded in a SiO(2)/Al(2)O(3) gate dielectric stack for low-voltage operation in non-volatile memory.

PubMed

Yang, Shiqian; Wang, Qin; Zhang, Manhong; Long, Shibing; Liu, Jing; Liu, Ming

2010-06-18

Titanium-tungsten nanocrystals (NCs) were fabricated by a self-assembly rapid thermal annealing (RTA) process. Well isolated Ti(0.46)W(0.54) NCs were embedded in the gate dielectric stack of SiO(2)/Al(2)O(3). A metal-oxide-semiconductor (MOS) capacitor was fabricated to investigate its application in a non-volatile memory (NVM) device. It demonstrated a large memory window of 6.2 V in terms of flat-band voltage (V(FB)) shift under a dual-directional sweeping gate voltage of - 10 to 10 V. A 1.1 V V(FB) shift under a low dual-directional sweeping gate voltage of - 4 to 4 V was also observed. The retention characteristic of this MOS capacitor was demonstrated by a 0.5 V memory window after 10(4) s of elapsed time at room temperature. The endurance characteristic was demonstrated by a program/erase cycling test.

Improved dc and power performance of AlGaN/GaN high electron mobility transistors with Sc 2O 3 gate dielectric or surface passivation

NASA Astrophysics Data System (ADS)

Luo, B.; Mehandru, R.; Kim, Jihyun; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R. C.; Moser, N.; Gillespie, J. K.; Jessen, G. H.; Jenkins, T. J.; Yannuzi, M. J.; Via, G. D.; Crespo, A.

2003-10-01

The dc and power characteristics of AlGaN/GaN MOS-HEMTs with Sc 2O 3 gate dielectrics were compared with that of conventional metal-gate HEMTs fabricated on the same material. The MOS-HEMT shows higher saturated drain-source current (˜0.75 A/mm) and significantly better power-added efficiency (PAE, 27%) relative to the HEMT (˜0.6 A/mm and ˜5%). The Sc 2O 3 also provides effective surface passivation, with higher drain current, lower leakage currents and higher three-terminal breakdown voltage in passivated devices relative to unpassivated devices. The PAE also increases (from ˜5% to 12%) on the surface passivated HEMTs, showing that Sc 2O 3 is an attractive option for reducing gate and surface leakage in AlGaN/GaN heterostructure transistors.

High-performance enhancement-mode Al2O3/InAlGaN/GaN MOS high-electron mobility transistors with a self-aligned gate recessing technology

NASA Astrophysics Data System (ADS)

Zhang, Kai; Kong, Cen; Zhou, Jianjun; Kong, Yuechan; Chen, Tangsheng

2017-02-01

The paper reports high-performance enhancement-mode MOS high-electron mobility transistors (MOS-HEMTs) based on a quaternary InAlGaN barrier. Self-aligned gate technology is used for gate recessing, dielectric deposition, and gate electrode formation. An improved digital recessing process is developed, and an Al2O3 gate dielectric grown with O2 plasma is used. Compared to results with AlGaN barrier, the fabricated E-mode MOS-HEMT with InAlGaN barrier delivers a record output current density of 1.7 A/mm with a threshold voltage (V TH) of 1.5 V, and a small on-resistance (R on) of 2.0 Ω·mm. Excellent V TH hysteresis and greatly improved gate leakage characteristics are also demonstrated.

Investigating compositional effects of atomic layer deposition ternary dielectric Ti-Al-O on metal-insulator-semiconductor heterojunction capacitor structure for gate insulation of InAlN/GaN and AlGaN/GaN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Colon, Albert; Stan, Liliana; Divan, Ralu

Gate insulation/surface passivation in AlGaN/GaN and InAlN/GaN heterojunction field-effect transistors is a major concern for passivation of surface traps and reduction of gate leakage current. However, finding the most appropriate gate dielectric materials is challenging and often involves a compromise of the required properties such as dielectric constant, conduction/valence band-offsets, or thermal stability. Creating a ternary compound such as Ti-Al-O and tailoring its composition may result in a reasonably good gate material in terms of the said properties. To date, there is limited knowledge of the performance of ternary dielectric compounds on AlGaN/GaN and even less on InAlN/GaN. To approachmore » this problem, the authors fabricated metal-insulator-semiconductor heterojunction (MISH) capacitors with ternary dielectrics Ti-Al-O of various compositions, deposited by atomic layer deposition (ALD). The film deposition was achieved by alternating cycles of TiO2 and Al2O3 using different ratios of ALD cycles. TiO2 was also deposited as a reference sample. The electrical characterization of the MISH capacitors shows an overall better performance of ternary compounds compared to the pure TiO2. The gate leakage current density decreases with increasing Al content, being similar to 2-3 orders of magnitude lower for a TiO2:Al2O3 cycle ratio of 2:1. Although the dielectric constant has the highest value of 79 for TiO2 and decreases with increasing the number of Al2O3 cycles, it is maintaining a relatively high value compared to an Al2O3 film. Capacitance voltage sweeps were also measured in order to characterize the interface trap density. A decreasing trend in the interface trap density was found while increasing Al content in the film. In conclusion, our study reveals that the desired high-kappa properties of TiO2 can be adequately maintained while improving other insulator performance factors. The ternary compounds may be an excellent choice as a gate material

Atomic-layer-deposited Al2O3-HfO2-Al2O3 dielectrics for metal-insulator-metal capacitor applications

NASA Astrophysics Data System (ADS)

Ding, Shi-Jin; Zhu, Chunxiang; Li, Ming-Fu; Zhang, David Wei

2005-08-01

Atomic-layer-deposited Al2O3-HfO2-Al2O3 dielectrics have been investigated to replace conventional silicon oxide and nitride for radio frequency and analog metal-insulator-metal capacitors applications. In the case of 1-nm-Al2O3, sufficiently good electrical performances are achieved, including a high dielectric constant of ˜17, a small dissipation factor of 0.018 at 100kHz, an extremely low leakage current of 7.8×10-9A/cm2 at 1MV/cm and 125°C, perfect voltage coefficients of capacitance (74ppm/V2 and 10ppm/V). The quadratic voltage coefficient of capacitance decreases with the applied frequency due to the change of relaxation time with different carrier mobility in insulator, and correlates with the dielectric composition and thickness, which is of intrinsic property owing to electric field polarization. Furthermore, the conduction mechanism of the AHA dielectrics is also discussed, indicating the Schottky emission dominated at room temperature.

AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

DOE Office of Scientific and Technical Information (OSTI.GOV)

Guo, Y.; Li, H.; Robertson, J.

2016-05-28

AlN and Al oxy-nitride dielectric layers are proposed instead of Al{sub 2}O{sub 3} as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al{sub 2}O{sub 3}, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al{sub 2}O{sub 3} is attributed tomore » its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.« less

HIGH-k GATE DIELECTRIC: AMORPHOUS Ta/La2O3 FILMS GROWN ON Si AT LOW PRESSURE

NASA Astrophysics Data System (ADS)

Bahari, Ali; Khorshidi, Zahra

2014-09-01

In the present study, Ta/La2O3 films (La2O3 doped with Ta2O5) as a gate dielectric were prepared using a sol-gel method at low pressure. Ta/La2O3 film has some hopeful properties as a gate dielectric of logic device. The structure and morphology of Ta/La2O3 films were studied using X-ray diffraction (XRD), atomic force microscopy (AFM) and scanning electron microscopy (SEM). Electrical properties of films were performed using capacitance-voltage (C-V) and current density-voltage (J-V) measurements. The optical bandgap of samples was studied by UV-visible optical absorbance measurement. The optical bandgap, Eopt, is determined from the absorbance spectra. The obtained results show that Ta/La2O3 film as a good gate dielectric has amorphous structure, good thermal stability, high dielectric constant (≈ 25), low leakage current and wide bandgap (≈ 4.7 eV).

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

NASA Astrophysics Data System (ADS)

Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

2018-04-01

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

Diamond field effect transistors with a high-dielectric constant Ta2O5 as gate material

NASA Astrophysics Data System (ADS)

Liu, J.-W.; Liao, M.-Y.; Imura, M.; Watanabe, E.; Oosato, H.; Koide, Y.

2014-06-01

A Ta2O5/Al2O3 bilayer gate oxide with a high-dielectric constant (high-k) has been successfully applied to a hydrogenated-diamond (H-diamond) metal-insulator-semiconductor field effect transistor (MISFET). The Ta2O5 layer is prepared by a sputtering-deposition (SD) technique on the Al2O3 buffer layer fabricated by an atomic layer deposition (ALD) technique. The ALD-Al2O3 plays an important role to eliminate plasma damage for the H-diamond surface during SD-Ta2O5 deposition. The dielectric constants of the SD-Ta2O5/ALD-Al2O3 bilayer and single SD-Ta2O5 are as large as 12.7 and 16.5, respectively. The k value of the single SD-Ta2O5 in this study is in good agreement with that of the SD-Ta2O5 on oxygen-terminated diamond. The capacitance-voltage characteristic suggests low interfacial trapped charge density for the SD-Ta2O5/ALD-Al2O3/H-diamond MIS diode. The MISFET with a gate length of 4 µm has a drain current maximum and an extrinsic transconductance of -97.7 mA mm-1 (normalized by gate width) and 31.0 ± 0.1 mS mm-1, respectively. The effective mobility in the H-diamond channel layer is found to be 70.1 ± 0.5 cm2 V-1 s-1.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer

PubMed Central

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J.

2016-01-01

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack. PMID:27279454

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

PubMed

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

2016-06-09

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Band Offsets and Interfacial Properties of HfAlO Gate Dielectric Grown on InP by Atomic Layer Deposition.

PubMed

Yang, Lifeng; Wang, Tao; Zou, Ying; Lu, Hong-Liang

2017-12-01

X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy have been used to determine interfacial properties of HfO 2 and HfAlO gate dielectrics grown on InP by atomic layer deposition. An undesirable interfacial InP x O y layer is easily formed at the HfO 2 /InP interface, which can severely degrade the electrical performance. However, an abrupt interface can be achieved when the growth of the HfAlO dielectric on InP starts with an ultrathin Al 2 O 3 layer. The valence and conduction band offsets for HfAlO/InP heterojunctions have been determined to be 1.87 ± 0.1 and 2.83 ± 0.1 eV, respectively. These advantages make HfAlO a potential dielectric for InP MOSFETs.

Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta2O5)x(Al2O3)1-x as potential gate dielectrics for GaN/AlxGa1-xN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Partida-Manzanera, T.; Roberts, J. W.; Bhat, T. N.; Zhang, Z.; Tan, H. R.; Dolmanan, S. B.; Sedghi, N.; Tripathy, S.; Potter, R. J.

2016-01-01

This paper describes a method to optimally combine wide band gap Al2O3 with high dielectric constant (high-κ) Ta2O5 for gate dielectric applications. (Ta2O5)x(Al2O3)1-x thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped AlxGa1-xN/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta2O5 molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al2O3 to 4.6 eV for pure Ta2O5. The dielectric constant calculated from capacitance-voltage measurements also increases linearly from 7.8 for Al2O3 up to 25.6 for Ta2O5. The effect of post-deposition annealing in N2 at 600 °C on the interfacial properties of undoped Al2O3 and Ta-doped (Ta2O5)0.12(Al2O3)0.88 films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al2O3/GaN-HEMT and (Ta2O5)0.16(Al2O3)0.84/GaN-HEMT samples increased by ˜1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al2O3 can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents.

Microwave dielectric properties of CaCu3Ti4O12-Al2O3 composite

NASA Astrophysics Data System (ADS)

Rahman, Mohd Fariz Ab; Abu, Mohamad Johari; Karim, Saniah Ab; Zaman, Rosyaini Afindi; Ain, Mohd Fadzil; Ahmad, Zainal Arifin; Mohamed, Julie Juliewatty

2016-07-01

(1-x)CaCu3Ti4O12 + (x)Al2O3 composite (0 ≤ x ≤0.25) was prepared via conventional solid-state reaction method. The fabrication of sample was started with synthesizing stoichiometric CCTO from CaCO3, CuO and TiO2 powders, then wet-mixed in deionized water for 24 h. The process was continued with calcined CCTO powder at 900 °C for 12 h before sintered at 1040 °C for 10 h. Next, the calcined CCTO powder with different amount of Al2O3 were mixed for 24 h, then palletized and sintered at 1040 °C for 10. X-ray diffraction analysis on the sintered samples showed that CCTO powder was in a single phase, meanwhile the trace of secondary peaks which belong to CaAl2O4 and Corundum (Al2O3) could be observed in the other samples Scanning electron microscopy analysis showed that the grain size of the sample is firstly increased with addition of Al2O3 (x = 0.01), then become smaller with the x > 0.01. Microwave dielectric properties showed that the addition of Al2O3 (x = 0.01) was remarkably reduced the dielectric loss while slightly increased the dielectric permittivity. However, further addition of Al2O3 was reduced both dielectric loss and permittivity at least for an order of magnitude.

Temperature dependence of the dielectric response of anodized Al-Al2O3-metal capacitors

NASA Astrophysics Data System (ADS)

Hickmott, T. W.

2003-03-01

The temperature dependence of capacitance, CM, and conductance, GM, of Al-Al2O3-metal capacitors with Cu, Ag, and Au electrodes has been measured between 100 and 340 K at seven frequencies between 10 kHz and 1 MHz. Al2O3 films between 15 and 64 nm thick were formed by anodizing evaporated Al films in borate-glycol or borate-H2O electrolyte. The interface capacitance at the Al2O3-metal interface, CI, which is in series with the capacitance CD due to the Al2O3 dielectric, is determined from plots of 1/CM versus insulator thickness. CI is not fixed for a given metal-insulator interface but depends on the vacuum system used to deposit the metal electrode. CI is nearly temperature independent. When CI is taken into account the dielectric constant of Al2O3 determined from capacitance measurements is ˜8.3 at 295 K. The dielectric constant does not depend on anodizing electrolyte, insulator thickness, metal electrode, deposition conditions for the metal electrode or measurement frequency. By contrast, GM of Al-Al2O3-metal capacitors depends on both the deposition conditions of the metal and on the metal. For Al-Al2O3-Cu capacitors, GM is larger for capacitors with large values of 1/CI that result when Cu is evaporated in an oil-pumped vacuum system. For Al-Al2O3-Ag capacitors, GM does not depend on the Ag deposition conditions.

An Al2O3 Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials

PubMed Central

Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Zhang, Xueao

2017-01-01

We fabricated 70 nm Al2O3 gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al2O3/Si substrate is superior to that on a traditional 300 nm SiO2/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al2O3/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS2, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices. PMID:28937619

Remote interfacial dipole scattering and electron mobility degradation in Ge field-effect transistors with GeO x /Al2O3 gate dielectrics

NASA Astrophysics Data System (ADS)

Wang, Xiaolei; Xiang, Jinjuan; Wang, Shengkai; Wang, Wenwu; Zhao, Chao; Ye, Tianchun; Xiong, Yuhua; Zhang, Jing

2016-06-01

Remote Coulomb scattering (RCS) on electron mobility degradation is investigated experimentally in Ge-based metal-oxide-semiconductor field-effect-transistors (MOSFETs) with GeO x /Al2O3 gate stacks. It is found that the mobility increases with greater GeO x thickness (7.8-20.8 Å). The physical origin of this mobility dependence on GeO x thickness is explored. The following factors are excluded: Coulomb scattering due to interfacial traps at GeO x /Ge, phonon scattering, and surface roughness scattering. Therefore, the RCS from charges in gate stacks is studied. The charge distributions in GeO x /Al2O3 gate stacks are evaluated experimentally. The bulk charges in Al2O3 and GeO x are found to be negligible. The density of the interfacial charge is  +3.2  ×  1012 cm-2 at the GeO x /Ge interface and  -2.3  ×  1012 cm-2 at the Al2O3/GeO x interface. The electric dipole at the Al2O3/GeO x interface is found to be  +0.15 V, which corresponds to an areal charge density of 1.9  ×  1013 cm-2. The origin of this mobility dependence on GeO x thickness is attributed to the RCS due to the electric dipole at the Al2O3/GeO x interface. This remote dipole scattering is found to play a significant role in mobility degradation. The discovery of this new scattering mechanism indicates that the engineering of the Al2O3/GeO x interface is key for mobility enhancement and device performance improvement. These results are helpful for understanding and engineering Ge mobility enhancement.

Nanoindentation investigation of HfO2 and Al2O3 films grown by atomic layer deposition

Treesearch

K. Tapily; Joseph E. Jakes; D. S. Stone; P. Shrestha; D. Gu; H. Baumgart; A. A. Elmustafa

2008-01-01

The challenges of reducing gate leakage current and dielectric breakdown beyond the 45 nm technology node have shifted engineers’ attention from the traditional and proven dielectric SiO2 to materials of higher dielectric constant also known as high-k materials such as hafnium oxide (HfO2) and aluminum oxide (Al2O3). These high-k materials are projected to...

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors

PubMed Central

2013-01-01

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric. PMID:23294730

Structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics for a-IGZO thin-film transistors.

PubMed

Chen, Fa-Hsyang; Her, Jim-Long; Shao, Yu-Hsuan; Matsuda, Yasuhiro H; Pan, Tung-Ming

2013-01-08

In this letter, we investigated the structural and electrical characteristics of high-κ Er2O3 and Er2TiO5 gate dielectrics on the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices. Compared with the Er2O3 dielectric, the a-IGZO TFT device incorporating an Er2TiO5 gate dielectric exhibited a low threshold voltage of 0.39 V, a high field-effect mobility of 8.8 cm2/Vs, a small subthreshold swing of 143 mV/decade, and a high Ion/Ioff current ratio of 4.23 × 107, presumably because of the reduction in the oxygen vacancies and the formation of the smooth surface roughness as a result of the incorporation of Ti into the Er2TiO5 film. Furthermore, the reliability of voltage stress can be improved using an Er2TiO5 gate dielectric.

Time-dependent dielectric breakdown of atomic-layer-deposited Al2O3 films on GaN

NASA Astrophysics Data System (ADS)

Hiraiwa, Atsushi; Sasaki, Toshio; Okubo, Satoshi; Horikawa, Kiyotaka; Kawarada, Hiroshi

2018-04-01

Atomic-layer-deposited (ALD) Al2O3 films are the most promising surface passivation and gate insulation layers in non-Si semiconductor devices. Here, we carried out an extensive study on the time-dependent dielectric breakdown characteristics of ALD-Al2O3 films formed on homo-epitaxial GaN substrates using two different oxidants at two different ALD temperatures. The breakdown times were approximated by Weibull distributions with average shape parameters of 8 or larger. These values are reasonably consistent with percolation theory predictions and are sufficiently large to neglect the wear-out lifetime distribution in assessing the long-term reliability of the Al2O3 films. The 63% lifetime of the Al2O3 films increases exponentially with a decreasing field, as observed in thermally grown SiO2 films at low fields. This exponential relationship disproves the correlation between the lifetime and the leakage current. Additionally, the lifetime decreases with measurement temperature with the most remarkable reduction observed in high-temperature (450 °C) O3-grown films. This result agrees with that from a previous study, thereby ruling out high-temperature O3 ALD as a gate insulation process. When compared at 200 °C under an equivalent SiO2 field of 4 MV/cm, which is a design guideline for thermal SiO2 on Si, high-temperature H2O-grown Al2O3 films have the longest lifetimes, uniquely achieving the reliability target of 20 years. However, this target is accomplished by a relatively narrow margin and, therefore, improvements in the lifetime are expected to be made, along with efforts to decrease the density of extrinsic Al2O3 defects, if any, to promote the practical use of ALD Al2O3 films.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

An “ohmic-first” self-terminating gate-recess technique for normally-off Al2O3/GaN MOSFET

NASA Astrophysics Data System (ADS)

Wang, Hongyue; Wang, Jinyan; Li, Mengjun; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang; Zhou, Yang; Dai, Gang

2018-04-01

In this article, an ohmic-first AlGaN/GaN self-terminating gate-recess etching technique was demonstrated where ohmic contact formation is ahead of gate-recess-etching/gate-dielectric-deposition (GRE/GDD) process. The ohmic contact exhibits few degradations after the self-terminating gate-recess process. Besides, when comparing with that using the conventional fabrication process, the fabricated device using the ohmic-first fabrication process shows a better gate dielectric quality in terms of more than 3 orders lower forward gate leakage current, more than twice higher reverse breakdown voltage as well as better stability. Based on this proposed technique, the normally-off Al2O3/GaN MOSFET exhibits a threshold voltage (V th) of ˜1.8 V, a maximum drain current of ˜328 mA/mm, a forward gate leakage current of ˜10-6 A/mm and an off-state breakdown voltage of 218 V at room temperature. Meanwhile, high temperature characteristics of the device was also evaluated and small variations (˜7.6%) of the threshold voltage was confirmed up to 300 °C.

Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta{sub 2}O{sub 5}){sub x}(Al{sub 2}O{sub 3}){sub 1−x} as potential gate dielectrics for GaN/Al{sub x}Ga{sub 1−x}N/GaN high electron mobility transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Partida-Manzanera, T., E-mail: sgtparti@liv.ac.uk; Institute of Materials Research and Engineering, A*STAR; Roberts, J. W.

2016-01-14

This paper describes a method to optimally combine wide band gap Al{sub 2}O{sub 3} with high dielectric constant (high-κ) Ta{sub 2}O{sub 5} for gate dielectric applications. (Ta{sub 2}O{sub 5}){sub x}(Al{sub 2}O{sub 3}){sub 1−x} thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped Al{sub x}Ga{sub 1−x}N/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta{sub 2}O{sub 5} molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al{sub 2}O{sub 3} to 4.6 eV for pure Ta{sub 2}O{sub 5}. The dielectric constant calculated from capacitance-voltage measurementsmore » also increases linearly from 7.8 for Al{sub 2}O{sub 3} up to 25.6 for Ta{sub 2}O{sub 5}. The effect of post-deposition annealing in N{sub 2} at 600 °C on the interfacial properties of undoped Al{sub 2}O{sub 3} and Ta-doped (Ta{sub 2}O{sub 5}){sub 0.12}(Al{sub 2}O{sub 3}){sub 0.88} films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al{sub 2}O{sub 3}/GaN-HEMT and (Ta{sub 2}O{sub 5}){sub 0.16}(Al{sub 2}O{sub 3}){sub 0.84}/GaN-HEMT samples increased by ∼1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al{sub 2}O{sub 3} can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents.« less

Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al{sub 2}O{sub 3} gate dielectric

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, Yu-Hong; Yu, Ming-Jiue; Lin, Ruei-Ping

2016-01-18

Low-temperature atomic layer deposition (ALD) was employed to deposit Al{sub 2}O{sub 3} as a gate dielectric in amorphous In–Ga–Zn–O thin-film transistors fabricated at temperatures below 120 °C. The devices exhibited a negligible threshold voltage shift (ΔV{sub T}) during negative bias stress, but a more pronounced ΔV{sub T} under positive bias stress with a characteristic turnaround behavior from a positive ΔV{sub T} to a negative ΔV{sub T}. This abnormal positive bias instability is explained using a two-process model, including both electron trapping and hydrogen release and migration. Electron trapping induces the initial positive ΔV{sub T}, which can be fitted using the stretchedmore » exponential function. The breakage of residual AlO-H bonds in low-temperature ALD Al{sub 2}O{sub 3} is triggered by the energetic channel electrons. The hydrogen atoms then diffuse toward the In–Ga–Zn–O channel and induce the negative ΔV{sub T} through electron doping with power-law time dependence. A rapid partial recovery of the negative ΔV{sub T} after stress is also observed during relaxation.« less

Processing of Al2O3/SrTiO3/PDMS Composites With Low Dielectric Loss

NASA Astrophysics Data System (ADS)

Yao, J. L.; Guo, M. J.; Qi, Y. B.; Zhu, H. X.; Yi, R. Y.; Gao, L.

2018-05-01

Polydimethylsiloxane (PDMS) is widely used in the electrical and electronic industries due to its excellent electrical insulation and biocompatible characteristics. However, the dielectric constant of pure PDMS is very low which restricts its applications. Herein, we report a series of PDMS/Al2O3/strontium titanate (ST) composites with high dielectric constant and low loss prepared by a simple experimental method. The composites exhibit high dielectric constant (relative dielectric constant is 4) after the composites are coated with insulated Al2O3 particles, and the dielectric constant gets further improved for composites with ST particles (dielectric constant reaches 15.5); a lower dielectric loss (tanδ= 0.05) is also found at the same time which makes co-filler composites suitable for electrical insulation products, and makes the experimental method more interesting in modern teaching.

Giant dielectric response and low dielectric loss in Al{sub 2}O{sub 3} grafted CaCu{sub 3}Ti{sub 4}O{sub 12} ceramics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rajabtabar-Darvishi, A.; Center for Surface and Nanoanalytics; Bayati, R., E-mail: reza.bayati@intel.com, E-mail: mbayati@ncsu.edu, E-mail: wdfei@hit.edu.cn

2015-03-07

This study sheds light on the effect of alumina on dielectric constant and dielectric loss of novel CaCu{sub 3}Ti{sub 4}O{sub 12} composite ceramics. Alumina, at several concentrations, was deposited on the surface of CaCu{sub 3}Ti{sub 4}O{sub 12} particles via sol-gel technique. The dielectric constant significantly increased for all frequencies and the dielectric loss substantially decreased for low and intermediate frequencies. These observations were attributed to the change in characteristics of grains and grain boundaries. It was found that the insulating properties of the grain boundaries are improved following the addition of Al{sub 2}O{sub 3}. The relative density of CaCu{sub 3}Ti{submore » 4}O{sub 12}/Al{sub 2}O{sub 3} composite ceramics decreased compared to the pure CaCu{sub 3}Ti{sub 4}O{sub 12} and the grain size was greatly changed with the alumina content affecting the dielectric properties. With the addition of alumina into CaCu{sub 3}Ti{sub 4}O{sub 12}, tighter interfaces formed. The 6%- and 10%-alumina ceramics showed the minimum dielectric loss and the maximum dielectric constant, respectively. Both the dielectric constant and loss tangent decreased in the 20%-alumina ceramic due to the formation of CuO secondary phase. It was revealed that Al serves as an electron acceptor decreasing the electron concentration, if Al{sup 3+} ions substitute for Ti{sup 4+} ions, and as an electron donor increasing the electron concentration, if Al{sup 3+} ions substitute for Ca{sup 2+} ions. We established a processing-microstructure-properties paradigm which opens new avenues for novel applications of CaCu{sub 3}Ti{sub 4}O{sub 12}/Al{sub 2}O{sub 3} composite ceramics.« less

Interface trapping in (2 ¯ 01 ) β-Ga2O3 MOS capacitors with deposited dielectrics

NASA Astrophysics Data System (ADS)

Jayawardena, Asanka; Ramamurthy, Rahul P.; Ahyi, Ayayi C.; Morisette, Dallas; Dhar, Sarit

2018-05-01

The electrical properties of interfaces and the impact of post-deposition annealing have been investigated in gate oxides formed by low pressure chemical vapor deposition (LPCVD SiO2) and atomic layer deposition (Al2O3) on ( 2 ¯ 01 ) oriented n-type β-Ga2O3 single crystals. Capacitance-voltage based methods have been used to extract the interface state densities, including densities of slow `border' traps at the dielectric-Ga2O3 interfaces. It was observed that SiO2-β-Ga2O3 has a higher interface and border trap density than the Al2O3-β-Ga2O3. An increase in shallow interface states was also observed at the Al2O3-β-Ga2O3 interface after post-deposition annealing at higher temperature suggesting the high temperature annealing to be detrimental for Al2O3-Ga2O3 interfaces. Among the different dielectrics studied, LPCVD SiO2 was found to have the lowest dielectric leakage and the highest breakdown field, consistent with a higher conduction band-offset. These results are important for the processing of high performance β-Ga2O3 MOS devices as these factors will critically impact channel transport, threshold voltage stability, and device reliability.

Al{sub 2}O{sub 3}/GeO{sub x} gate stack on germanium substrate fabricated by in situ cycling ozone oxidation method

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Xu; Zeng, Zhen-Hua; Microwave Device and IC Department, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029

2014-09-01

Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9 × 10{sup 11 }cm{sup −2 }eV{sup −1} have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al{sub 2}O{sub 3} with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al{sub 2}O{sub 3} is attributed to themore » sub-gap states, which may be correlated to the OH-related groups in Al{sub 2}O{sub 3} network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.« less

Microwave dielectric properties of CaCu{sub 3}Ti{sub 4}O{sub 12}-Al{sub 2}O{sub 3} composite

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rahman, Mohd Fariz Ab; Abu, Mohamad Johari; Zaman, Rosyaini Afindi

2016-07-19

(1-x)CaCu{sub 3}Ti{sub 4}O{sub 12} + (x)Al{sub 2}O{sub 3} composite (0 ≤ x ≤0.25) was prepared via conventional solid-state reaction method. The fabrication of sample was started with synthesizing stoichiometric CCTO from CaCO{sub 3}, CuO and TiO{sub 2} powders, then wet-mixed in deionized water for 24 h. The process was continued with calcined CCTO powder at 900 °C for 12 h before sintered at 1040 °C for 10 h. Next, the calcined CCTO powder with different amount of Al{sub 2}O{sub 3} were mixed for 24 h, then palletized and sintered at 1040 °C for 10. X-ray diffraction analysis on the sinteredmore » samples showed that CCTO powder was in a single phase, meanwhile the trace of secondary peaks which belong to CaAl{sub 2}O{sub 4} and Corundum (Al{sub 2}O{sub 3}) could be observed in the other samples Scanning electron microscopy analysis showed that the grain size of the sample is firstly increased with addition of Al{sub 2}O{sub 3} (x = 0.01), then become smaller with the x > 0.01. Microwave dielectric properties showed that the addition of Al{sub 2}O{sub 3} (x = 0.01) was remarkably reduced the dielectric loss while slightly increased the dielectric permittivity. However, further addition of Al{sub 2}O{sub 3} was reduced both dielectric loss and permittivity at least for an order of magnitude.« less

Impact of gate work-function on memory characteristics in Al2O3/HfOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Kim, Sungmin; Seo, David H.; Seo, Sunae; Won Kang, Tae; Wang, Kang L.

2012-01-01

Graphene-based non-volatile memory devices composed of a single-layer graphene channel and an Al2O3/HfOx/Al2O3 charge-storage layer exhibit memory functionality. The impact of the gate material's work-function (Φ) on the memory characteristics is investigated using different types of metals [Ti (ΦTi = 4.3 eV) and Ni (ΦNi = 5.2 eV)]. The ambipolar carrier conduction of graphene results in an enlargement of memory window (ΔVM), which is ˜4.5 V for the Ti-gate device and ˜9.1 V for the Ni-gate device. The increase in ΔVM is attributed to the change in the flat-band condition and the suppression of electron back-injection within the gate stack.

AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors using Sc2O3 as the gate oxide and surface passivation

NASA Astrophysics Data System (ADS)

Mehandru, R.; Luo, B.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2003-04-01

We demonstrated that Sc2O3 thin films deposited by plasma-assisted molecular-beam epitaxy can be used simultaneously as a gate oxide and as a surface passivation layer on AlGaN/GaN high electron mobility transistors (HEMTs). The maximum drain source current, IDS, reaches a value of over 0.8 A/mm and is ˜40% higher on Sc2O3/AlGaN/GaN transistors relative to conventional HEMTs fabricated on the same wafer. The metal-oxide-semiconductor HEMTs (MOS-HEMTs) threshold voltage is in good agreement with the theoretical value, indicating that Sc2O3 retains a low surface state density on the AlGaN/GaN structures and effectively eliminates the collapse in drain current seen in unpassivated devices. The MOS-HEMTs can be modulated to +6 V of gate voltage. In particular, Sc2O3 is a very promising candidate as a gate dielectric and surface passivant because it is more stable on GaN than is MgO.

TiN/Al2O3/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

NASA Astrophysics Data System (ADS)

Kato, Kimihiko; Matsui, Hiroaki; Tabata, Hitoshi; Takenaka, Mitsuru; Takagi, Shinichi

2018-04-01

Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO layer are defective just after the Al2O3 layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Pentacene-based low voltage organic field-effect transistors with anodized Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Jeong, Yeon Taek; Dodabalapur, Ananth

2007-11-01

Pentacene-based low voltage organic field-effect transistors were realized using an anodized Ta2O5 gate dielectric. The Ta2O5 gate dielectric layer with a surface roughness of 1.3Å was obtained by anodizing an e-beam evaporated Ta film. The device exhibited values of saturation mobility, threshold voltage, and Ion/Ioff ratio of 0.45cm2/Vs, 0.56V, and 7.5×101, respectively. The gate leakage current was reduced by more than 70% with a hexamethyldisilazane (HMDS) treatment on the Ta2O5 layer. The HMDS treatment also resulted in enhanced mobility values and a larger pentacene grain size.

FAST TRACK COMMUNICATION High mobility and low operating voltage ZnGaO and ZnGaLiO transistors with spin-coated Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Xia, D. X.; Xu, J. B.

2010-11-01

Spin-coated alumina serving as a gate dielectric in thin film transistors shows interesting dielectric properties for low-voltage applications, despite a moderate capacitance. With Ga singly doped and Ga, Li co-doped ZnO as the active channel layers, typical mobilities of 4.7 cm2 V-1 s-1 and 2.1 cm2 V-1 s-1 are achieved, respectively. At a given gate bias, the operation current is much smaller than the previously reported values in low-voltage thin film transistors, primarily relying on the giant-capacitive dielectric. The reported devices combine advantages of high mobility, low power consumption, low cost and ease of fabrication. In addition to the transparent nature of both the dielectric and semiconducting active channels, the superior electrical properties of the devices may provide a new avenue for future transparent electronics.

Gate bias stress stability under light irradiation for indium zinc oxide thin-film transistors based on anodic aluminium oxide gate dielectrics

NASA Astrophysics Data System (ADS)

Li, Min; Lan, Linfeng; Xu, Miao; Wang, Lei; Xu, Hua; Luo, Dongxiang; Zou, Jianhua; Tao, Hong; Yao, Rihui; Peng, Junbiao

2011-11-01

Thin-film transistors (TFTs) using indium zinc oxide as the active layer and anodic aluminium oxide (Al2O3) as the gate dielectric layer were fabricated. The device showed an electron mobility of as high as 10.1 cm2 V-1 s-1, an on/off current ratio of as high as ~108, and a turn-on voltage (Von) of only -0.5 V. Furthermore, this kind of TFTs was very stable under positive bias illumination stress. However, when the device experienced negative bias illumination stress, the threshold voltage shifted to the positive direction. It was found that the instability under negative bias illumination stress (NBIS) was due to the electrons from the Al gate trapping into the Al2O3 dielectric when exposed to the illuminated light. Using a stacked structure of Al2O3/SiO2 dielectrics, the device became more stable under NBIS.

Polycrystalline diamond RF MOSFET with MoO3 gate dielectric

NASA Astrophysics Data System (ADS)

Ren, Zeyang; Zhang, Jinfeng; Zhang, Jincheng; Zhang, Chunfu; Chen, Dazheng; Quan, Rudai; Yang, Jiayin; Lin, Zhiyu; Hao, Yue

2017-12-01

We report the radio frequency characteristics of the diamond metal-oxide-semiconductor field effect transistor with MoO3 gate dielectric for the first time. The device with 2-μm gate length was fabricated on high quality polycrystalline diamond. The maximum drain current of 150 mA/mm at VGS = -5 V and the maximum transconductance of 27 mS/mm were achieved. The extrinsic cutoff frequency of 1.2 GHz and the maximum oscillation frequency of 1.9 GHz have been measured. The moderate frequency characteristics are attributed to the moderate transconductance limited by the series resistance along the channel. We expect that the frequency characteristics of the device can be improved by increasing the magnitude of gm, or fundamentally decreasing the gate-controlled channel resistance and series resistance along the channel, and down-scaling the gate length.

Schottky barrier SOI-MOSFETs with high-k La2O3/ZrO2 gate dielectrics

PubMed Central

Henkel, C.; Abermann, S.; Bethge, O.; Pozzovivo, G.; Klang, P.; Stöger-Pollach, M.; Bertagnolli, E.

2011-01-01

Schottky barrier SOI-MOSFETs incorporating a La2O3/ZrO2 high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 1011 eV−1 cm−2, a low subthreshold slope of 70-80 mV/decade, and an ION/IOFF current ratio greater than 2 × 106 are obtained. PMID:21461054

Dielectric characterization of TiO2, Al2O3 - Nanoparticle loaded epoxy resin

NASA Astrophysics Data System (ADS)

Thakor, S. G.; Rana, V. A.; Vankar, H. P.

2018-05-01

In present work, the dielectric properties of two different nanoparticle loaded Bisphenol A-epoxy resin were carried out at room temperature. Sample of the neat epoxy resin and nanoparticle loaded epoxy resin in the form of disc were prepared of different weight fraction (i.e 0.5 wt%,0.7 wt%,1 wt%,1.5 wt%,1.7 wt%,2 wt%). TiO2 and Al2O3 nanoparticles were taken as filler in the epoxy resin. Complex permittivity of the prepared samples was measured using Agilent E4980A precision LCR meter in frequency range of 103 Hz to 106 Hz. The dependency of dielectric behavior on type and concentration of nanoparticle in considered frequency range are discussed in detail.

Microstructure, Thermal, Mechanical, and Dielectric Properties of BaO-CaO-Al2O3-B2O3-SiO2 Glass-Ceramics

NASA Astrophysics Data System (ADS)

Li, Bo; Bian, Haibo; Fang, Yi

2017-12-01

BaO-CaO-Al2O3-B2O3-SiO2 (BCABS) glass-ceramics were prepared via the method of controlled crystallization. The effect of CaO modification on the microstructure, phase evolution, as well as thermal, mechanical, and dielectric properties was investigated. XRD identified that quartz is the major crystal phase; cristobalite and bazirite are the minor crystal phases. Moreover, the increase of CaO could inhibit the phase transformation from quartz to cristobalite, but excessive CaO would increase the porosity of the ceramics. Additionally, with increasing the amount of CaO, the thermal expansion curve tends to be linear, and subsequently the CTE value decreases gradually, which is attributed to the decrease of cristobalite with high CTE and the formation of CaSiO3 with low CTE. The results indicated that a moderate amount of CaO helps attaining excellent mechanical, thermal, and dielectric properties, that is, the specimen with 9 wt% CaO sintered at 950 °C has a high CTE value (11.5 × 10-6/°C), a high flexural strength (165.7 MPa), and good dielectric properties (ɛr = 6.2, tanδ = 1.8 × 10-4, ρ = 4.6 × 1011 Ω•cm).

Comparison of structural and electrical properties of Lu{sub 2}O{sub 3} and Lu{sub 2}TiO{sub 5} gate dielectrics for α-InGaZnO thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pan, Tung-Ming, E-mail: tmpan@mail.cgu.edu.tw; Chen, Ching-Hung; Her, Jim-Long

We compared the structural properties and electrical characteristics of high-κ Lu{sub 2}O{sub 3} and Lu{sub 2}TiO{sub 5} gate dielectrics for amorphous indium-gallium-zinc oxide (α-InGaZnO) thin-film transistor (TFT) applications. The Lu{sub 2}O{sub 3} film has a strong Lu{sub 2}O{sub 3} (400) peak in the X-ray diffraction pattern, while the Lu{sub 2}TiO{sub 5} sample shows a relatively weak Lu{sub 2}TiO{sub 5} (102) peak. Atomic force microscopy reveals that the Lu{sub 2}O{sub 3} dielectric exhibits a rougher surface (about three times) than Lu{sub 2}TiO{sub 5} one. In X-ray photoelectron spectroscopy analysis, we found that the intensity of the O 1s peak corresponding tomore » Lu(OH){sub x} for Lu{sub 2}O{sub 3} film was higher than that of Lu{sub 2}TiO{sub 5} film. Furthermore, compared with the Lu{sub 2}O{sub 3} dielectric, the α-InGaZnO TFT using the Lu{sub 2}TiO{sub 5} gate dielectric exhibited a lower threshold voltage (from 0.43 to 0.25 V), a higher I{sub on}/I{sub off} current ratio (from 3.5 × 10{sup 6} to 1.3 × 10{sup 8}), a smaller subthreshold swing (from 276 to 130 mV/decade), and a larger field-effect mobility (from 14.5 to 24.4 cm{sup 2}/V s). These results are probably due to the incorporation of TiO{sub x} into the Lu{sub 2}O{sub 3} film to form a Lu{sub 2}TiO{sub 5} structure featuring a smooth surface, a low moisture absorption, a high dielectric constant, and a low interface state density at the oxide/channel interface. Furthermore, the stability of Lu{sub 2}O{sub 3} and Lu{sub 2}TiO{sub 5} α-InGaZnO TFTs was investigated under positive gate-bias stress (PGBS) and negative gate-bias stress (NGBS). The threshold voltage of the TFT performed under NGBS is more degradation than that under PGBS. This behavior may be attributed to the electron charge trapping at the dielectric–channel interface under PGBS, whereas the oxygen vacancies occurred in the InGaZnO under NGBS.« less

Transparent and flexible capacitors based on nanolaminate Al2O3/TiO2/Al2O3.

PubMed

Zhang, Guozhen; Wu, Hao; Chen, Chao; Wang, Ti; Yue, Jin; Liu, Chang

2015-01-01

Transparent and flexible capacitors based on nanolaminate Al2O3/TiO2/Al2O3 dielectrics have been fabricated on indium tin oxide-coated polyethylene naphthalate substrates by atomic layer deposition. A capacitance density of 7.8 fF/μm(2) at 10 KHz was obtained, corresponding to a dielectric constant of 26.3. Moreover, a low leakage current density of 3.9 × 10(-8) A/cm(2) at 1 V has been realized. Bending test shows that the capacitors have better performances in concave conditions than in convex conditions. The capacitors exhibit an average optical transmittance of about 70% in visible range and thus open the door for applications in transparent and flexible integrated circuits.

Temperature- and frequency-dependent dielectric behaviors of insulator/semiconductor (Al2O3/ZnO) nanolaminates with various ZnO thicknesses

NASA Astrophysics Data System (ADS)

Li, Jin; Bi, Xiaofang

2016-07-01

Al2O3/ZnO nanolaminates (NLs) with various ZnO sublayer thicknesses were prepared by atomic layer deposition. The Al2O3 sublayers are characterized as amorphous and the ZnO sublayers have an oriented polycrystalline structure. As the ZnO thickness decreases to a certain value, each NL exhibits a critical temperature at which its dielectric constant starts to rise quickly. Moreover, this temperature increases as the ZnO thickness is decreased further. On the other hand, the permittivity demonstrates a large value of several hundred at a frequency  ⩽1000 Hz, followed by a steplike decrease at a higher frequency. The change in the cut-off frequency with ZnO thickness is characterized by a hook function. It is revealed that the Coulomb confinement effect becomes predominant in the dielectric behaviors of the NLs with very thin ZnO. As the ZnO thickness decreases to about the same as or even smaller than the Bohr radius of ZnO, a great change in the carrier concentration and effective mass of ZnO is induced, which is shown to be responsible for the peculiar dielectric behaviors of Al2O3/ZnO with very thin ZnO. These findings provide insight into the prevailing mechanisms to optimize the dielectric properties of semiconductor/insulator laminates with nanoscale sublayer thickness.

Giant dielectric constant dominated by Maxwell-Wagner relaxation in Al{sub 2}O{sub 3}/TiO{sub 2} nanolaminates synthesized by atomic layer deposition.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, W.; Auciello, O.; Premnath, R. N.

2010-01-01

Nanolaminates consisting of Al{sub 2}O{sub 3} and TiO{sub 2} oxide sublayers were synthesized by using atomic layer deposition to produce individual layers with atomic scale thickness control. The sublayer thicknesses were kept constant for each multilayer structure, and were changed from 50 to 0.2 nm for a series of different samples. Giant dielectric constant ({approx}1000) was observed when the sublayer thickness is less than 0.5 nm, which is significantly larger than that of Al{sub 2}O{sub 3} and TiO{sub 2} dielectrics. Detailed investigation revealed that the observed giant dielectric constant is originated from the Maxwell-Wagner type dielectric relaxation.

Highly stable organic field-effect transistors with engineered gate dielectrics (Conference Presentation)

NASA Astrophysics Data System (ADS)

Kippelen, Bernard; Wang, Cheng-Yin; Fuentes-Hernandez, Canek; Yun, Minseong; Singh, Ankit K.; Dindar, Amir; Choi, Sangmoo; Graham, Samuel

2016-11-01

Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

Stability and band offsets between c-plane ZnO semiconductor and LaAlO3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Jianli; Chen, Xinfeng; Wu, Shuyin; Tang, Gang; Zhang, Junting; Stampfl, C.

2018-03-01

Wurtzite-perovskite heterostructures composed of a high dielectric constant oxide and a wide bandgap semiconductor envision promising applications in field-effect transistors. In the present paper, the structural and electronic properties of LaAlO3/ZnO heterojunctions are investigated by first-principles calculations. We study the initial adsorption of La, Al, and oxygen atoms on ZnO (0001) and (000 1 ¯ ) surfaces and find that La atoms may occupy interstitial sites during the growth of stoichiometric ZnO (0001). The band gap of the stoichiometric ZnO (0001) surface is smaller than that of the stoichiometric ZnO (000 1 ¯ ) surface. The surface formation energy indicates that La or Al atoms may substitute Zn atoms at the nonstoichiometric ZnO (0001) surface. The atomic charges, electronic density of states, and band offsets are analyzed for the optimized LaAlO3/ZnO heterojunctions. There is a band gap for the LaAlO3/ZnO (000 1 ¯ ) heterostructures, and the largest variation in charge occurs at the surface or interface. Our results suggest that the Al-terminated LaAlO3/ZnO (000 1 ¯ ) interfaces are suitable for the design of metal oxide semiconductor devices because the valence and conduction band offsets are both larger than 1 eV and the interface does not produce any in-gap states.

Comparison of Multilayer Dielectric Thin Films for Future Metal-Insulator-Metal Capacitors: Al2O3/HfO2/Al2O3 versus SiO2/HfO2/SiO2

NASA Astrophysics Data System (ADS)

Park, Sang-Uk; Kwon, Hyuk-Min; Han, In-Shik; Jung, Yi-Jung; Kwak, Ho-Young; Choi, Woon-Il; Ha, Man-Lyun; Lee, Ju-Il; Kang, Chang-Yong; Lee, Byoung-Hun; Jammy, Raj; Lee, Hi-Deok

2011-10-01

In this paper, two kinds of multilayered metal-insulator-metal (MIM) capacitors using Al2O3/HfO2/Al2O3 (AHA) and SiO2/HfO2/SiO2 (SHS) were fabricated and characterized for radio frequency (RF) and analog mixed signal (AMS) applications. The experimental results indicate that the AHA MIM capacitor (8.0 fF/µm2) is able to provide a higher capacitance density than the SHS MIM capacitor (5.1 fF/µm2), while maintaining a low leakage current of about 50 nA/cm2 at 1 V. The quadratic voltage coefficient of capacitance, α gradually decreases as a function of stress time under constant voltage stress (CVS). The parameter variation of SHS MIM capacitors is smaller than that of AHA MIM capacitors. The effects of CVS on voltage linearity and time-dependent dielectric breakdown (TDDB) characteristics were also investigated.

Effects of HfO2 encapsulation on electrical performances of few-layered MoS2 transistor with ALD HfO2 as back-gate dielectric.

PubMed

Xu, Jingping; Wen, Ming; Zhao, Xinyuan; Liu, Lu; Song, Xingjuan; Lai, Pui-To; Tang, Wing-Man

2018-08-24

The carrier mobility of MoS 2 transistors can be greatly improved by the screening role of high-k gate dielectric. In this work, atomic-layer deposited (ALD) HfO 2 annealed in NH 3 is used to replace SiO 2 as the gate dielectric to fabricate back-gated few-layered MoS 2 transistors, and good electrical properties are achieved with field-effect mobility (μ) of 19.1 cm 2 V -1 s -1 , subthreshold swing (SS) of 123.6 mV dec -1 and on/off ratio of 3.76 × 10 5 . Furthermore, enhanced device performance is obtained when the surface of the MoS 2 channel is coated by an ALD HfO 2 layer with different thicknesses (10, 15 and 20 nm), where the transistor with a 15 nm HfO 2 encapsulation layer exhibits the best overall electrical properties: μ = 42.1 cm 2 V -1 s -1 , SS = 87.9 mV dec -1 and on/off ratio of 2.72 × 10 6 . These improvements should be associated with the enhanced screening effect on charged-impurity scattering and protection from absorption of environmental gas molecules by the high-k encapsulation. The capacitance equivalent thickness of the back-gate dielectric (HfO 2 ) is only 6.58 nm, which is conducive to scaling of the MoS 2 transistors.

Effects of HfO2/Al2O3 gate stacks on electrical performance of planar In x Ga1- x As tunneling field-effect transistors

NASA Astrophysics Data System (ADS)

Ahn, Dae-Hwan; Yoon, Sang-Hee; Takenaka, Mitsuru; Takagi, Shinichi

2017-08-01

We study the impact of gate stacks on the electrical characteristics of Zn-diffused source In x Ga1- x As tunneling field-effect transistors (TFETs) with Al2O3 or HfO2/Al2O3 gate insulators. Ta and W gate electrodes are compared in terms of the interface trap density (D it) of InGaAs MOS interfaces. It is found that D it is lower at the W/HfO2/Al2O3 InGaAs MOS interface than at the Ta/HfO2/Al2O3 interface. The In0.53Ga0.47As TFET with a W/HfO2 (2.7 nm)/Al2O3 (0.3 nm) gate stack of 1.4-nm-thick capacitance equivalent thickness (CET) has a steep minimum subthreshold swing (SS) of 57 mV/dec, which is attributed to the thin CET and low D it. Also, the In0.53Ga0.47As (2.6 nm)/In0.67Ga0.33As (3.2 nm)/In0.53Ga0.47As (96.5 nm) quantum-well (QW) TFET supplemented with this 1.4-nm-thick CET gate stack exhibits a steeper minimum SS of 54 mV/dec and a higher on-current (I on) than those of the In0.53Ga0.47As TFET.

Comparative Study of HfTa-based gate-dielectric Ge metal-oxide-semiconductor capacitors with and without AlON interlayer

NASA Astrophysics Data System (ADS)

Xu, J. P.; Zhang, X. F.; Li, C. X.; Chan, C. L.; Lai, P. T.

2010-04-01

The electrical properties and high-field reliability of HfTa-based gate-dielectric metal-oxide-semiconductor (MOS) devices with and without AlON interlayer on Ge substrate are investigated. Experimental results show that the MOS capacitor with HfTaON/AlON stack gate dielectric exhibits low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent thickness (˜1.1 nm), and high dielectric constant (˜20). All of these should be attributed to the blocking role of the ultrathin AlON interlayer against interdiffusions of Ge, Hf, and Ta and penetration of O into the Ge substrate, with the latter effectively suppressing the unintentional formation of unstable poor-quality low- k GeO x and giving a superior AlON/Ge interface. Moreover, incorporation of N into both the interlayer and high- k dielectric further improves the device reliability under high-field stress through the formation of strong N-related bonds.

Small signal measurement of Sc 2O 3 AlGaN/GaN moshemts

NASA Astrophysics Data System (ADS)

Luo, B.; Mehandru, R.; Kang, B. S.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J. K.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2004-02-01

The rf performance of 1 × 200 μm 2 AlGaN/GaN MOS-HEMTs with Sc 2O 3 used as both the gate dielectric and as a surface passivation layer is reported. A maximum fT of ˜11 GHz and fMAX of 19 GHz were obtained. The equivalent device parameters were extracted by fitting this data to obtain the transconductance, drain resistance, drain-source resistance, transfer time and gate-drain and gate-source capacitance as a function of gate voltage. The transfer time is in the order 0.5-1 ps and decreases with increasing gate voltage.

Improvement in dielectric and mechanical performance of CaCu3.1Ti4O12.1 by addition of Al2O3 nanoparticles

PubMed Central

2012-01-01

The properties of CaCu3.1Ti4O12.1 [CC3.1TO] ceramics with the addition of Al2O3 nanoparticles, prepared via a solid-state reaction technique, were investigated. The nanoparticle additive was found to inhibit grain growth with the average grain size decreasing from approximately 7.5 μm for CC3.1TO to approximately 2.0 μm for the unmodified samples, while the Knoop hardness value was found to improve with a maximum value of 9.8 GPa for the 1 vol.% Al2O3 sample. A very high dielectric constant > 60,000 with a low loss tangent (approximately 0.09) was observed for the 0.5 vol.% Al2O3 sample at 1 kHz and at room temperature. These data suggest that nanocomposites have a great potential for dielectric applications. PMID:22221316

Thickness engineering of atomic layer deposited Al2O3 films to suppress interfacial reaction and diffusion of Ni/Au gate metal in AlGaN/GaN HEMTs up to 600 °C in air

NASA Astrophysics Data System (ADS)

Suria, Ateeq J.; Yalamarthy, Ananth Saran; Heuser, Thomas A.; Bruefach, Alexandra; Chapin, Caitlin A.; So, Hongyun; Senesky, Debbie G.

2017-06-01

In this paper, we describe the use of 50 nm atomic layer deposited (ALD) Al2O3 to suppress the interfacial reaction and inter-diffusion between the gate metal and semiconductor interface, to extend the operation limit up to 600 °C in air. Suppression of diffusion is verified through Auger electron spectroscopy (AES) depth profiling and X-ray diffraction (XRD) and is further supported with electrical characterization. An ALD Al2O3 thin film (10 nm and 50 nm), which functions as a dielectric layer, was inserted between the gate metal (Ni/Au) and heterostructure-based semiconductor material (AlGaN/GaN) to form a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). This extended the 50 nm ALD Al2O3 MIS-HEMT (50-MIS) current-voltage (Ids-Vds) and gate leakage (Ig,leakage) characteristics up to 600 °C. Both, the 10 nm ALD Al2O3 MIS-HEMT (10-MIS) and HEMT, failed above 350 °C, as evidenced by a sudden increase of approximately 50 times and 5.3 × 106 times in Ig,leakage, respectively. AES on the HEMT revealed the formation of a Ni-Au alloy and Ni present in the active region. Additionally, XRD showed existence of metal gallides in the HEMT. The 50-MIS enables the operation of AlGaN/GaN based electronics in oxidizing high-temperature environments, by suppressing interfacial reaction and inter-diffusion of the gate metal with the semiconductor.

Characterization of ZrO2 and (ZrO2)x(Al2O3)1-X thin films on Si substrates: effect of the Al2O3 component

NASA Astrophysics Data System (ADS)

Vitanov, P.; Harizanova, A.; Ivanova, T.

2014-05-01

ZrO2 and (ZrO2)x(Al2O3)1-x films were deposited by the sol-gel technique on Si substrates. The effect of the Al2O3 additive on the film surface morphology was studied by atomic force microscopy (AFM). The mixed oxide films showed a smoother morphology and lower values of the root-mean-square (RMS) roughness compared to ZrO2. Further, FTIR spectra indicated that ZrO2 underwent crystallization. The electrical measurements of the MIS structure revealed that the presence of Al2O3 and the amorphization affects its dielectric properties. The MIS structure with (ZrO2)x(Al2O3)1-x showed a lower fixed charge (~ 6×1010 cm-2) and an interface state density in the middle of the band gap of 6×1011 eV-1 cm-2). The dielectric constant measured was 22, with the leakage current density decreasing to 2×10-8 A cm-2 at 1×106 V cm-1.

Low-temperature fabrication of sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors

NASA Astrophysics Data System (ADS)

Yao, Rihui; Zheng, Zeke; Xiong, Mei; Zhang, Xiaochen; Li, Xiaoqing; Ning, Honglong; Fang, Zhiqiang; Xie, Weiguang; Lu, Xubing; Peng, Junbiao

2018-03-01

In this work, low temperature fabrication of a sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors (TFTs) on polyimide substrates was investigated. The effects of Ar-pressure during the sputtering process and then especially the post-annealing treatments at low temperature (≤200 °C) for HfO2 on reducing the density of defects in the bulk and on the surface were systematically studied. X-ray reflectivity, UV-vis and X-ray photoelectron spectroscopy, and micro-wave photoconductivity decay measurements were carried out and indicated that the high quality of optimized HfO2 film and its high dielectric properties contributed to the low concentration of structural defects and shallow localized defects such as oxygen vacancies. As a result, the well-structured HfO2 gate dielectric exhibited a high density of 9.7 g/cm3, a high dielectric constant of 28.5, a wide optical bandgap of 4.75 eV, and relatively low leakage current. The corresponding flexible a-IGZO TFT on polyimide exhibited an optimal device performance with a saturation mobility of 10.3 cm2 V-1 s-1, an Ion/Ioff ratio of 4.3 × 107, a SS value of 0.28 V dec-1, and a threshold voltage (Vth) of 1.1 V, as well as favorable stability under NBS/PBS gate bias and bending stress.

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

NASA Astrophysics Data System (ADS)

Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

2017-02-01

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

Anomalous bias-stress-induced unstable phenomena of InZnO thin-film transistors using Ta2O5 gate dielectric

NASA Astrophysics Data System (ADS)

Xu, Wangying; Dai, Mingzhi; Liang, Lingyan; Liu, Zhimin; Sun, Xilian; Wan, Qing; Cao, Hongtao

2012-05-01

InZnO thin-film transistors using high-κ Ta2O5 gate dielectric are presented and analysed. The large capacitance coupling effect of amorphous Ta2O5 results in fabricated devices with good electrical properties. However, an anomalous negative threshold voltage (Vth) shift under positive bias stress is observed. It is suggested that electron detrapping from the high-κ Ta2O5 dielectric to the gate electrode is responsible for this Vth shift, which is supported both by the logarithmical dependence of the Vth change on the duration of the bias stress and device simulation extracted trapped charges involved.

The effect of Al segregation on Schottky barrier height and effective work function in TiAl/TiN/HfO2 gate stacks

NASA Astrophysics Data System (ADS)

Kim, Geun-Myeong; Oh, Young Jun; Chang, K. J.

2016-07-01

We perform first-principles density functional calculations to investigate the effects of Al incorporation on the p-type Schottky barrier height ≤ft({φ\\text{p}}\\right) and the effective work function for various high-k/metal gate stacks, such as TiN/HfO2 with interface Al impurities, Ti1-x Al x N/HfO2, and TiAl/TiN/HfO2. When Al atoms substitute for the interface Ti atoms at TiN/HfO2 interface, interface dipole fields become stronger, leading to the increase of {φ\\text{p}} and thereby the n-type shift of effective work function. In Ti1-x Al x N/HfO2 interface, {φ\\text{p}} linearly increases with the Al content, attributed to the presence of interface Al atoms. On the other hand, in TiAl/TiN/HfO2 interface, where Al is assumed not to segregate from TiAl to TiN, {φ\\text{p}} is nearly independent of the thickness of TiAl. Our results indicate that Al impurities at the metal/dielectric interface play an important role in controlling the effective work function, and provide a clue to understanding the n-type shift of the effective work function observed in TiAl/TiN/HfO2 gate stacks fabricated by using thegate-last process.

Study of interfacial strain at the α-Al2O3/monolayer MoS2 interface by first principle calculations

NASA Astrophysics Data System (ADS)

Yu, Sheng; Ran, Shunjie; Zhu, Hao; Eshun, Kwesi; Shi, Chen; Jiang, Kai; Gu, Kunming; Seo, Felix Jaetae; Li, Qiliang

2018-01-01

With the advances in two-dimensional (2D) transition metal dichalcogenides (TMDCs) based metal-oxide-semiconductor field-effect transistor (MOSFET), the interface between the semiconductor channel and gate dielectrics has received considerable attention due to its significant impacts on the morphology and charge transport of the devices. In this study, first principle calculations were utilized to investigate the strain effect induced by the interface between crystalline α-Al2O3 (0001)/h-MoS2 monolayer. The results indicate that the 1.3 nm Al2O3 can induce a 0.3% tensile strain on the MoS2 monolayer. The strain monotonically increases with thicker dielectric layers, inducing more significant impact on the properties of MoS2. In addition, the study on temperature effect indicates that the increasing temperature induces monotonic lattice expansion. This study clearly indicates that the dielectric engineering can effectively tune the properties of 2D TMDCs, which is very attractive for nanoelectronics.

Top gating control of superconductivity at the LaAlO3 /SrTiO3 interfaces

NASA Astrophysics Data System (ADS)

Jouan, Alexis; Hurand, Simon; Feuillet-Palma, Cheryl; Singh, Gyanendra; Lesueur, Jerome; Bergeal, Nicolas; Lesne, Edouard; Reyren, Nicolas

2015-03-01

Transition metal oxides display a great variety of quantum electronic behaviors. Epitaxial interfaces involving such materials give a unique opportunity to engineer artificial materials where new electronic orders take place. It has been shown that a superconducting two-dimensional electron gas could form at the interface of two insulators such as LaAlO3 and SrTiO3 [1], or LaTiO3 and SrTiO3 [2]. An important feature of these interfaces lies in the possibility to control their electronic properties, including superconductivity and spin-orbit coupling (SOC) with field effect [3-5]. However, experiments have been performed almost exclusively with a metallic gate on the back of the sample. In this presentation, we will report on the realization of a top-gated LaAlO3/SrTiO3 device whose physical properties, including superconductivity and SOC, can be tuned over a wide range of electrostatic doping. In particular, we will present a phase diagram of the interface and compare the effect of the top-gate and back-gate. Finally, we will discuss the field-effect modulation of the Rashba spin-splitting energy extracted from the analysis of magneto-transport measurements. Our result paves the way for the realization of mesoscopic devices where both superconductivity and SOC can be tuned locally.

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

PubMed

Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

2016-12-01

Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

Enhanced carrier mobility of multilayer MoS2 thin-film transistors by Al2O3 encapsulation

NASA Astrophysics Data System (ADS)

Kim, Seong Yeoul; Park, Seonyoung; Choi, Woong

2016-10-01

We report the effect of Al2O3 encapsulation on the carrier mobility and contact resistance of multilayer MoS2 thin-film transistors by statistically investigating 70 devices with SiO2 bottom-gate dielectric. After Al2O3 encapsulation by atomic layer deposition, calculation based on Y-function method indicates that the enhancement of carrier mobility from 24.3 cm2 V-1 s-1 to 41.2 cm2 V-1 s-1 occurs independently from the reduction of contact resistance from 276 kΩ.μm to 118 kΩ.μm. Furthermore, contrary to the previous literature, we observe a negligible effect of thermal annealing on contact resistance and carrier mobility during the atomic layer deposition of Al2O3. These results demonstrate that Al2O3 encapsulation is a useful method of improving the carrier mobility of multilayer MoS2 transistors, providing important implications on the application of MoS2 and other two-dimensional materials into high-performance transistors.

Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

2017-05-01

Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low- k). To supplement low- k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high- k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high- k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3. [Figure not available: see fulltext.

Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for AdvancedCMOS Devices

PubMed Central

Suzuki, Masamichi

2012-01-01

A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3) high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT) of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al) atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process. PMID:28817057

Electrical Characteristics of Organic Field Effect Transistor Formed by Gas Treatment of High-k Al2O3 at Low Temperature

NASA Astrophysics Data System (ADS)

Lee, Sunwoo; Yoon, Seungki; Park, In-Sung; Ahn, Jinho

2009-04-01

We studied the electrical characteristics of an organic field effect transistor (OFET) formed by the hydrogen (H2) and nitrogen (N2) mixed gas treatment of a gate dielectric layer. We also investigated how device mobility is related to the length and width variations of the channel. Aluminum oxide (Al2O3) was used as the gate dielectric layer. After the treatment, the mobility and subthreshold swing were observed to be significantly improved by the decreased hole carrier localization at the interfacial layer between the gate oxide and pentacene channel layers. H2 gas plays an important role in removing the defects of the gate oxide layer at temperatures below 100 °C.

Effect of Al2O3 encapsulation on multilayer MoSe2 thin-film transistors

NASA Astrophysics Data System (ADS)

Lee, Hyun Ah; Yeoul Kim, Seong; Kim, Jiyoung; Choi, Woong

2017-03-01

We report the effect of Al2O3 encapsulation on the device performance of multilayer MoSe2 thin-film transistors based on statistical investigation of 29 devices with a SiO2 bottom-gate dielectric. On average, Al2O3 encapsulation by atomic layer deposition increased the field-effect mobility from 10.1 cm2 V-1 s-1 to 14.8 cm2 V-1 s-1, decreased the on/off-current ratio from 8.5  ×  105 to 2.3  ×  105 and negatively shifted the threshold voltage from  -1.1 V to  -8.1 V. Calculation based on the Y-function method indicated that the enhancement of intrinsic carrier mobility occurred independently of the reduction of contact resistance after Al2O3 encapsulation. Furthermore, contrary to previous reports in the literature, we observe a negligible effect of thermal annealing on contact resistance and carrier mobility during the atomic layer deposition of Al2O3. These results demonstrate that Al2O3 encapsulation is a useful method for improving the carrier mobility of multilayer MoSe2 transistors, providing important implications on the application of MoSe2 and other 2D materials into high-performance transistors.

Synchrotron radiation x-ray photoelectron spectroscopy study on the interface chemistry of high-k PrxAl2-xO3 (x=0-2) dielectrics on TiN for dynamic random access memory applications

NASA Astrophysics Data System (ADS)

Schroeder, T.; Lupina, G.; Sohal, R.; Lippert, G.; Wenger, Ch.; Seifarth, O.; Tallarida, M.; Schmeisser, D.

2007-07-01

Engineered dielectrics combined with compatible metal electrodes are important materials science approaches to scale three-dimensional trench dynamic random access memory (DRAM) cells. Highly insulating dielectrics with high dielectric constants were engineered in this study on TiN metal electrodes by partly substituting Al in the wide band gap insulator Al2O3 by Pr cations. High quality PrAlO3 metal-insulator-metal capacitors were processed with a dielectric constant of 19, three times higher than in the case of Al2O3 reference cells. As a parasitic low dielectric constant interface layer between PrAlO3 and TiN limits the total performance gain, a systematic nondestructive synchrotron x-ray photoelectron spectroscopy study on the interface chemistry of PrxAl2-xO3 (x =0-2) dielectrics on TiN layers was applied to unveil its chemical origin. The interface layer results from the decreasing chemical reactivity of PrxAl2-xO3 dielectrics with increasing Pr content x to reduce native Ti oxide compounds present on unprotected TiN films. Accordingly, PrAlO3 based DRAM capacitors require strict control of the surface chemistry of the TiN electrode, a parameter furthermore of importance to engineer the band offsets of PrxAl2-xO3/TiN heterojunctions.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

NASA Astrophysics Data System (ADS)

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-09-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

PubMed Central

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-01-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

Post-deposition-annealing effect on current conduction in Al2O3 films formed by atomic layer deposition with H2O oxidant

NASA Astrophysics Data System (ADS)

Hiraiwa, Atsushi; Matsumura, Daisuke; Okubo, Satoshi; Kawarada, Hiroshi

2017-02-01

Atomic-layer-deposition (ALD) Al2O3 films are promising as gate insulators of non-Si semiconductor devices. Although they allow relatively small leakage currents just after deposition, ALD Al2O3 films formed at low temperatures are subject to high temperature during fabrication or operation of devices. Therefore, the effect of post-deposition annealing (PDA) on the properties of Al2O3 films is investigated in this study. ALD Al2O3 films formed using H2O oxidant at low temperatures are compacted by PDA, but their mass density and dielectric constant remain approximately unchanged or slightly decrease owing to the desorption of methyl groups contained in the films as impurities. In accordance with these results, the wet etching rate of Al2O3 films is not much reduced by PDA. The conduction current in ALD Al2O3 films formed on Si is reduced by PDA and becomes smaller than that in films formed at the same ALD temperatures as those of PDA. The conduction current for PDA temperatures above 250 °C, however, increases and, accordingly, spoils the merit of low-temperature ALD. Therefore, given that the dielectric constant of annealed films remains low, high-temperature ALD is practically more significant than applying PDA to low-temperature ALD Al2O3 films from the viewpoint of leakage current under the same thermal budget. Space-charge-controlled field emission analysis revealed that, at the aforementioned threshold temperature, PDA abruptly increases the Al2O3/SiO2 interfacial dipoles and simultaneously reduces the amount of the positive charge near the interface. The so-called negative-charge buildup by PDA might be caused by this decrease in the positive charge.

Normally-off Al2O3/GaN MOSFET: Role of border traps on the device transport characteristics

NASA Astrophysics Data System (ADS)

Wang, Hongyue; Wang, Jinyan; Liu, Jingqian; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang

2018-03-01

Based on the self-terminating gate recess technique, two different processes featuring gate-recess-first (GF) and ohmic-contact-first (OF) were proposed for E-mode Al2O3/GaN MOSFETs. Increased maximum drain current (Idmax) ∼30% (420 vs 325 mA/mm), field-effect mobility (μFEmax) ∼67% (150 vs 90 cm2/Vs) and reduced on-state resistance (Ron) ∼42% (9.7 vs 16.8 Ω·mm) were observed in the devices fabricated by GF process. Such significant performance difference of GF- and OF-devices resulted from the presence of border traps at Al2O3/GaN interface with a time constant ∼7 × 10-6 s. Experimental results indicated that: (1) the near interface border traps in Al2O3 dielectric significantly affect device channel mobility; (2) a high temperature post-deposition annealing process could effective suppress generation of border traps.

Solution processed lanthanum aluminate gate dielectrics for use in metal oxide-based thin film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Esro, M.; Adamopoulos, G., E-mail: g.adamopoulos@lancaster.ac.uk; Mazzocco, R.

2015-05-18

We report on ZnO-based thin-film transistors (TFTs) employing lanthanum aluminate gate dielectrics (La{sub x}Al{sub 1−x}O{sub y}) grown by spray pyrolysis in ambient atmosphere at 440 °C. The structural, electronic, optical, morphological, and electrical properties of the La{sub x}Al{sub 1−x}O{sub y} films and devices as a function of the lanthanum to aluminium atomic ratio were investigated using a wide range of characterization techniques such as UV-visible absorption spectroscopy, impedance spectroscopy, spectroscopic ellipsometry, atomic force microscopy, x-ray diffraction, and field-effect measurements. As-deposited LaAlO{sub y} dielectrics exhibit a wide band gap (∼6.18 eV), high dielectric constant (k ∼ 16), low roughness (∼1.9 nm), and very low leakage currentsmore » (<3 nA/cm{sup 2}). TFTs employing solution processed LaAlO{sub y} gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with hysteresis-free operation, low operation voltages (∼10 V), high on/off current modulation ratio of >10{sup 6}, subthreshold swing of ∼650 mV dec{sup −1}, and electron mobility of ∼12 cm{sup 2} V{sup −1} s{sup −1}.« less

Influence of B2O3 content on sintering behaviour and dielectric properties of La2O3-B2O3-CaO/Al2O3 glass-ceramic composites for LTCC applications

NASA Astrophysics Data System (ADS)

Wang, F. L.; Zhang, Y. W.; Chen, X. Y.; Mao, H. J.; Zhang, W. J.

2018-01-01

La2O3-B2O3-CaO glasses with different B2O3 content were synthesized by melting method to produce glass/ceramic composites in this work. XRD and DSC results revealed that the diminution of B2O3 content was beneficial to increase the crystallization tendency of glass and improve the quality of crystalline phase, while decreasing the effect of glass during sintering process as sintering aids. The choice of glass/ceramic mass ratio was also influenced by the B2O3 content of glass. Dense samples sintered at 875 ºC showed good dielectric properties which meet the requirement of LTCC applications: moderate dielectric constant (7.8-9.4) and low dielectric loss (2.0×10-3).

Temperature dependence of trapping effects in metal gates/Al2O3/InGaAs stacks

NASA Astrophysics Data System (ADS)

Palumbo, F.; Pazos, S.; Aguirre, F.; Winter, R.; Krylov, I.; Eizenberg, M.

2017-06-01

The influence of the temperature on Metal Gate/Al2O3/n-InGaAs stacks has been studied by means of capacitance-voltage (C-V) hysteresis and flat band voltage as function of both negative and positive stress fields. It was found that the de-trapping effect decreases at low-temperature, indicating that the de-trapping of trapped electrons from oxide traps may be performed via Al2O3/InGaAs interface defects. The dependence of the C-V hysteresis on the stress field at different temperatures in our InGaAs stacks can be explained in terms of the defect spatial distribution. An oxide defect distribution can be found very close to the metal gate/Al2O3 interface. On the other side, the Al2O3/InGaAs interface presents defects distributed from the interface into the bulk of the oxide, showing the influence of InGaAs on Al2O3 in terms of the spatial defect distribution. At the present, he is a research staff of the National Council of Science and Technology (CONICET), working in the National Commission of Atomic Energy (CNEA) in Buenos Aires, Argentina, well embedded within international research collaboration. Since 2008, he is Professor at the National Technological University (UTN) in Buenos Aires, Argentina. Dr. Palumbo has received research fellowships from: Marie Curie Fellowship within the 7th European Community Framework Programme, Abdus Salam International Centre for Theoretical Physics (ICTP) Italy, National Council of Science and Technology (CONICET) Argentina, and Consiglio Nazionale delle Ricerche (CNR) Italy. He is also a frequent scientific visitor of academic institutions as IMM-CNR-Italy, Minatec Grenoble-France, the Autonomous University of Barcelona-Spain, and the Israel Institute of Technology-Technion. He has authored and co-authored more than 50 papers in international conferences and journals.

Alternative Dielectric Films for rf MEMS Capacitive Switches Deposited using Atomic Layer Deposited Al2O3/ZnO Alloys

DTIC Science & Technology

2006-07-02

A s c c s r t h s l © K 1 b c A a e t s C t o 0 d Sensors and Actuators A 135 (2007) 262–272 Alternative dielectric films for rf MEMS capacitive...Zn concentrations in the alloy films , which was lower than expected. Atomic force microscopy images evealed an average surface roughness of 0.27 nm...that was independent of deposition temperature and film composition. The dielectric constants of he Al2O3/ZnO ALD alloys films were calculated to be

Time-dependent dielectric breakdown in pure and lightly Al-doped Ta2O5 stacks

NASA Astrophysics Data System (ADS)

Atanassova, E.; Stojadinović, N.; Spassov, D.; Manić, I.; Paskaleva, A.

2013-05-01

The time-dependent dielectric breakdown (TDDB) characteristics of 7 nm pure and lightly Al-doped Ta2O5 (equivalent oxide thickness of 2.2 and 1.5 nm, respectively) with W gate electrodes in MOS capacitor configuration are studied using gate injection and constant voltage stress. The effect of both the process-induced defects and the dopant on the breakdown distribution, and on the extracted Weibull slope values, are discussed. The pre-existing traps which provoke weak spots dictate early breakdowns. Their effect is compounded of both the stress-induced new traps generation (percolation model is valid) and the inevitable lower-k interface layer in the region with long time-to-breakdown. The domination of one of these competitive effects defines the mechanism of degradation: the trapping at pre-existing traps appears to dominate in Ta2O5; Al doping reduces defects in Ta2O5, the generation of new traps prevails over the charge trapping in the doped samples, and the mechanism of breakdown is more adequate to the percolation concept. The doping of high-k Ta2O5 even with small amount (5 at.%) may serve as an engineering solution for improving its TDDB characteristics and reliability.

Dielectric properties and nonlinear I-V electrical behavior of (Li1+, Al3+) co-doped CaCu3Ti4O12 ceramics

NASA Astrophysics Data System (ADS)

Sun, Li; Ni, Qing; Guo, Jianqin; Cao, Ensi; Hao, Wentao; Zhang, Yongjia; Ju, Lin

2018-06-01

(Li1+, Al3+) co-doped CaCu3Ti4O12 ceramics (CaCu3-2 x Li x Al x Ti4O12, x = 0.05, 0.1, 0.15) were prepared by a sol-gel method and were sintered at 1020-1080 °C for 8 h to improve the geometric microstructure, dielectric and nonlinear I-V electrical properties. Notably, very high dielectric constant of 1 × 105 with good dielectric-frequency as well as dielectric-temperature stability can be achieved in CaCu2.8Li0.1Al0.1Ti4O12 ceramic sintered at 1060 °C. The average grain sizes, resistivity and the non-Ohmic properties are also improved compared to pure CaCu3Ti4O12. These results indicate that (Li1+, Al3+) co-doping at the Cu2+ site can improve the dielectric properties of CaCu3Ti4O12, supporting the internal barrier layer capacitance effect of Schottky barriers at grain boundaries.

Reaching state-of-the art requirements for MIM capacitors with a single-layer anodic Al2O3 dielectric and imprinted electrodes

NASA Astrophysics Data System (ADS)

Hourdakis, Emmanouel; Nassiopoulou, Androula G.

2017-07-01

Metal-Insulator-Metal (MIM) capacitors with a high capacitance density and low non-linearity coefficient using a single-layer dielectric of barrier-type anodic alumina (Al2O3) and an imprinted bottom Al electrode are presented. Imprinting of the bottom electrode aimed at increasing the capacitor effective surface area by creating a three-dimensional MIM capacitor architecture. The bottom Al electrode was only partly nanopatterned so as to ensure low series resistance of the MIM capacitor. With a 3 nm thick anodic Al2O3 dielectric, the capacitor with the imprinted electrode showed a 280% increase in capacitance density compared to the flat electrode capacitor, reaching a value of 20.5 fF/μm2. On the other hand, with a 30 nm thick anodic Al2O3 layer, the capacitance density was 7.9 fF/μm2 and the non-linearity coefficient was as low as 196 ppm/V2. These values are very close to reaching all requirements of the last International Technology Roadmap for Semiconductors for MIM capacitors [ITRS, http://www.itrs2.net/2013-itrs.html for ITRS Roadmap (2013)], and they are achieved by a single-layer dielectric instead of the complicated dielectric stacks of the literature. The obtained results constitute a real progress compared to previously reported results by our group for MIM capacitors using imprinted electrodes.

Effect of Dielectric Interface on the Performance of MoS2 Transistors.

PubMed

Li, Xuefei; Xiong, Xiong; Li, Tiaoyang; Li, Sichao; Zhang, Zhenfeng; Wu, Yanqing

2017-12-27

Because of their wide bandgap and ultrathin body properties, two-dimensional materials are currently being pursued for next-generation electronic and optoelectronic applications. Although there have been increasing numbers of studies on improving the performance of MoS 2 field-effect transistors (FETs) using various methods, the dielectric interface, which plays a decisive role in determining the mobility, interface traps, and thermal transport of MoS 2 FETs, has not been well explored and understood. In this article, we present a comprehensive experimental study on the effect of high-k dielectrics on the performance of few-layer MoS 2 FETs from 300 to 4.3 K. Results show that Al 2 O 3 /HfO 2 could boost the mobility and drain current. Meanwhile, MoS 2 transistors with Al 2 O 3 /HfO 2 demonstrate a 2× reduction in oxide trap density compared to that of the devices with the conventional SiO 2 substrate. Also, we observe a negative differential resistance effect on the device with 1 μm-channel length when using conventional SiO 2 as the gate dielectric due to self-heating, and this is effectively eliminated by using the Al 2 O 3 /HfO 2 gate dielectric. This dielectric engineering provides a highly viable route to realizing high-performance transition metal dichalcogenide-based FETs.

Microstructural, Optical and Dielectric Properties of Al-Incorporated SnO2 Nanoparticles

NASA Astrophysics Data System (ADS)

Ahmed, Ateeq; Tripathi, P.; Naseem Siddique, M.; Ali, Tinku

2017-08-01

In this work, Pure SnO2 and Al doped SnO2 nanoparticles with the composition Sn1-xAlxO2 (x = 0, and 0.05) have been successfully prepared using sol-gel technique. The effect of Al dopant on microstructural, optical and dielectric properties has been investigated by X-ray diffraction (XRD), Scanning electron microscopy (SEM), Ultraviolet (UV-Visible) absorption spectroscopy andImpedance spectroscopy (LCR meter)respectively. The XRD patterns indicated tetragonal rutile structure with single phase without any detectable impurity for all samples and incorporation of Al ions into the SnO2 lattice. Crystalline size decreased with aluminum content. The results of SEM confirm nanoparticles size decreases with Al dopant. UV-Visible results showed that optical band also decreases when Al is doped into pure SnO2 lattice. Frequency dependent dielectric properties of pure and doped SnO2 nanoparticles have been also studied.

Capacitance-voltage characteristics of sub-nanometric Al2O3 / TiO2 laminates: dielectric and interface charge densities.

PubMed

Kahouli, Abdelkader; Elbahri, Marwa Ben; Lebedev, Oleg; Lüders, Ulrike

2017-07-12

Advanced amorphous sub-nanometric laminates based on TiO 2 and Al 2 O 3 were deposited by atomic layer deposition at low temperature. Low densities of 'slow' and 'fast' interface states are achieved with values of 3.96 · 10 10 cm -2 and 4.85 · 10 -9 eV -1 cm -2 , respectively, by using a 40 nm laminate constituted of 0.7 nm TiO 2 and 0.8 nm Al 2 O 3 . The sub-nanometric laminate shows a low hysteresis width of 20 mV due to the low oxide charge density of about 3.72 · 10 11 cm -2 . Interestingly, such properties are required for stable and reliable performance of MOS capacitors and transistor operation. Thus, decreasing the individual layer thickness to the sub-nanometric range and combining two dielectric materials with oppositely charged defects may play a major role in the electrical response, highly promising for the application in future micro and nano-electronics applications.

Millimeter distance effects of surface plasmon polaritons in electroformed Al-Al2O3-Ag diodes

NASA Astrophysics Data System (ADS)

Hickmott, T. W.

2017-02-01

Electroforming of metal-insulator-metal diodes is a soft dielectric breakdown that changes the high resistance of as-prepared diodes to a low resistance state. Electroforming of Al-Al2O3-metal diodes with anodic Al2O3 results in voltage-controlled negative resistance in the current-voltage (I-V) characteristics, electroluminescence (EL), and electron emission into vacuum (EM). EL is due to electrons injected at the Al-Al2O3 interface combining with radiative defects in Al2O3. Surface plasmon polaritons (SPPs) are electromagnetic waves that can be excited by photons or electrons. SPPs are confined to a metal-dielectric interface, cause large electric fields in the metal and dielectric, and have ranges of micrometers. The temperature dependence of I-V curves, EL, and EM of a group of electroformed Al-Al2O3-Ag diodes with Al2O3 thicknesses between 12 nm and 20 nm, group A, was measured between 200 K and 300 K. After a sequence of temperature measurements, the Al-Al2O3-Ag diodes, the Al-Al2O3 regions between diodes, and portions of the Ag on the glass region that provides contacts to the diodes are darkened. The range of darkening is >7 mm in a diode with 12 nm of Al2O3 and 2.0-3.5 mm in diodes with Al2O3 thicknesses between 14 nm and 20 nm. Darkening is attributed to the occurrence of SPPs generated by EL photons at the Ag-Al2O3 and Al-Al2O3 interfaces. The results are compared to a second group of Al-Al2O3-Ag diodes with identical Al2O3 thicknesses, group B, that were prepared in the same way as the diodes of group A except for a difference in the deposition of Al films for the two groups. Al-Al2O3-Ag diodes of group B exhibit enhanced EL, which is attributed to spontaneous emission of recombination centers in Al2O3 being enhanced by large electromagnetic fields that are due to SPPs that are generated by EL photons.

Impact of La{sub 2}O{sub 3} interfacial layers on InGaAs metal-oxide-semiconductor interface properties in Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks deposited by atomic-layer-deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, C.-Y., E-mail: cychang@mosfet.t.u-tokyo.ac.jp; Takenaka, M.; Takagi, S.

We examine the electrical properties of atomic layer deposition (ALD) La{sub 2}O{sub 3}/InGaAs and Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs metal-oxide-semiconductor (MOS) capacitors. It is found that the thick ALD La{sub 2}O{sub 3}/InGaAs interface provides low interface state density (D{sub it}) with the minimum value of ∼3 × 10{sup 11} cm{sup −2} eV{sup −1}, which is attributable to the excellent La{sub 2}O{sub 3} passivation effect for InGaAs surfaces. It is observed, on the other hand, that there are a large amount of slow traps and border traps in La{sub 2}O{sub 3}. In order to simultaneously satisfy low D{sub it} and small hysteresis, the effectivenessmore » of Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks with ultrathin La{sub 2}O{sub 3} interfacial layers is in addition evaluated. The reduction of the La{sub 2}O{sub 3} thickness to 0.4 nm in Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs gate stacks leads to the decrease in hysteresis. On the other hand, D{sub it} of the Al{sub 2}O{sub 3}/La{sub 2}O{sub 3}/InGaAs interfaces becomes higher than that of the La{sub 2}O{sub 3}/InGaAs ones, attributable to the diffusion of Al{sub 2}O{sub 3} through La{sub 2}O{sub 3} into InGaAs and resulting modification of the La{sub 2}O{sub 3}/InGaAs interface structure. As a result of the effective passivation effect of La{sub 2}O{sub 3} on InGaAs, however, the Al{sub 2}O{sub 3}/10 cycle (0.4 nm) La{sub 2}O{sub 3}/InGaAs gate stacks can realize still lower D{sub it} with maintaining small hysteresis and low leakage current than the conventional Al{sub 2}O{sub 3}/InGaAs MOS interfaces.« less

Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

NASA Astrophysics Data System (ADS)

Lv, Yuanjie; Mo, Jianghui; Song, Xubo; He, Zezhao; Wang, Yuangang; Tan, Xin; Zhou, Xingye; Gu, Guodong; Guo, Hongyu; Feng, Zhihong

2018-05-01

Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10-10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

Effect of Al gate on the electrical behaviour of Al-doped Ta2O5 stacks

NASA Astrophysics Data System (ADS)

Skeparovski, A.; Novkovski, N.; Atanassova, E.; Paskaleva, A.; Lazarov, V. K.

2011-06-01

The electrical behaviour of Al-doped Ta2O5 films on nitrided silicon and implemented in Al-gated MIS capacitors has been studied. The dopant was introduced into the Ta2O5 through its surface by deposing a thin Al layer on the top of Ta2O5 followed by an annealing process. The HRTEM images reveal that the initial double-layer structure of the stacks composed of doped Ta2O5 and interfacial SiON layer undergoes changes during the formation of the Al gate and transforms into a three-layer structure with an additional layer between the Al electrode and the doped Ta2O5. This layer, being a result of reaction between the Al gate and the Al-doped Ta2O5, affects the overall electrical properties of the stacks. Strong charge trapping/detrapping processes have been established in the vicinity of the doped Ta2O5/SiON interface resulting in a large C-V hysteresis effect. The charge trapping also influences the current conduction in the layers keeping the current density level rather low even at high electric fields (J < 10-6 A cm-2 at 7 MV cm-1). By employing a three-layer model of the stack, the permittivity of both, the Al-doped Ta2O5 and the additional layer, has been estimated and the corresponding conduction mechanisms identified.

Compositional and gate tuning of the interfacial conductivity in LaAlO3/LaTiO3/SrTiO3 heterostructures

NASA Astrophysics Data System (ADS)

Hosoda, Masayuki; Bell, Christopher; Hikita, Yasuyuki; Hwang, Harold Y.

2013-03-01

We investigate the effect of LaTiO3 insertion at the interface between LaAlO3 and TiO2 terminated {100} SrTiO3 for a series of LaAlO3 and LaTiO3 thicknesses. A clear increase of the carrier density was observed while the Hall mobility was largely unchanged. In structures with LaAlO3 thickness ˜3 unit cells, close to the critical thickness for conductivity, as little as 0.25 unit cells of LaTiO3 drives an insulator-to-metal transition. These samples show a strong dependence of the conductivity on voltage with electrostatic back-gating, which can be understood in a two-carrier picture, and dominated by the change in carrier density at the interface.

Hydrogen-induced reversible changes in drain current in Sc2O3/AlGaN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Kang, B. S.; Mehandru, R.; Kim, S.; Ren, F.; Fitch, R. C.; Gillespie, J. K.; Moser, N.; Jessen, G.; Jenkins, T.; Dettmer, R.; Via, D.; Crespo, A.; Gila, B. P.; Abernathy, C. R.; Pearton, S. J.

2004-06-01

Pt contacted AlGaN/GaN high electron mobility transistors with Sc2O3 gate dielectrics show reversible changes in drain-source current upon exposure to H2-containing ambients, even at room temperature. The changes in current (as high as 3 mA for relatively low gate voltage and drain-source voltage) are approximately an order of magnitude larger than for Pt/GaN Schottky diodes and a factor of 5 larger than Sc2O3/AlGaN/GaN metal-oxide-semiconductor (MOS) diodes exposed under the same conditions. This shows the advantage of using a transistor structure in which the gain produces larger current changes upon exposure to hydrogen-containing ambients. The increase in current is the result of a decrease in effective barrier height of the MOS gate of 30-50 mV at 25 °C for 10% H2/90% N2 ambients relative to pure N2 and is due to catalytic dissociation of the H2 on the Pt contact, followed by diffusion to the Sc2O3/AlGaN interface.

Study on the dielectric properties of Al2O3/TiO2 sub-nanometric laminates: effect of the bottom electrode and the total thickness

NASA Astrophysics Data System (ADS)

Ben Elbahri, M.; Kahouli, A.; Mercey, B.; Lebedev, O.; Donner, W.; Lüders, U.

2018-02-01

Dielectrics based on amorphous sub-nanometric laminates of TiO2 and Al2O3 are subject to elevated dielectric losses and leakage currents, in large parts due to the extremely thin individual layer thickness chosen for the creation of the Maxwell-Wagner relaxation and therefore the high apparent dielectric constants. The optimization of performances of the laminate itself being strongly limited by this contradiction concerning its internal structure, we will show in this study that modifications of the dielectric stack of capacitors based on these sub-nanometric laminates can positively influence the dielectric losses and the leakage, as for example the nature of the electrodes, the introduction of thick insulating layers at the laminate/electrode interfaces and the modification of the total laminate thickness. The optimization of the dielectric stack leads to the demonstration of a capacitor with an apparent dielectric constant of 90, combined with low dielectric loss (tan δ) of 7 · 10-2 and with leakage currents smaller than 1  ×  10-6 A cm-2 at 10 MV m-1.

The electrical and interfacial properties of metal-high-k oxide-semiconductor field effect transistors with CeO2/HfO2 laminated gate dielectrics

NASA Astrophysics Data System (ADS)

Chang, Ingram Yin-ku; Chen, Chun-Heng; Chiu, Fu-Chien; Lee, Joseph Ya-min

2007-11-01

Metal-oxide-semiconductor field-effect transistors with CeO2/HfO2 laminated gate dielectrics were fabricated. The transistors have a subthreshold slope of 74.9mV/decade. The interfacial properties were measured using gated diodes. The surface state density Dit was 9.78×1011cm-2eV-1. The surface-recombination velocity (s0) and the minority carrier lifetime in the field-induced depletion region (τ0,FIJ) measured from the gated diode were about 6.11×103cm /s and 1.8×10-8s, respectively. The effective capture cross section of surface state (σs) extracted using the subthreshold-swing measurement and the gated diode was about 7.69×10-15cm2. The effective electron mobility of CeO2/HfO2 laminated gated transistors was determined to be 212cm2/Vs.

Accurate characterization and understanding of interface trap density trends between atomic layer deposited dielectrics and AlGaN/GaN with bonding constraint theory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramanan, Narayanan; Lee, Bongmook; Misra, Veena, E-mail: vmisra@ncsu.edu

2015-06-15

Many dielectrics have been proposed for the gate stack or passivation of AlGaN/GaN based metal oxide semiconductor heterojunction field effect transistors, to reduce gate leakage and current collapse, both for power and RF applications. Atomic Layer Deposition (ALD) is preferred for dielectric deposition as it provides uniform, conformal, and high quality films with precise monolayer control of film thickness. Identification of the optimum ALD dielectric for the gate stack or passivation requires a critical investigation of traps created at the dielectric/AlGaN interface. In this work, a pulsed-IV traps characterization method has been used for accurate characterization of interface traps withmore » a variety of ALD dielectrics. High-k dielectrics (HfO{sub 2}, HfAlO, and Al{sub 2}O{sub 3}) are found to host a high density of interface traps with AlGaN. In contrast, ALD SiO{sub 2} shows the lowest interface trap density (<2 × 10{sup 12 }cm{sup −2}) after annealing above 600 °C in N{sub 2} for 60 s. The trend in observed trap densities is subsequently explained with bonding constraint theory, which predicts a high density of interface traps due to a higher coordination state and bond strain in high-k dielectrics.« less

Low-voltage organic thin film transistors (OTFTs) using crosslinked polyvinyl alcohol (PVA)/neodymium oxide (Nd2O3) bilayer gate dielectrics

NASA Astrophysics Data System (ADS)

Khound, Sagarika; Sarma, Ranjit

2018-01-01

We have reported here on the design, processing and dielectric properties of pentacene-based organic thin film transitors (OTFTs) with a bilayer gate dilectrics of crosslinked PVA/Nd2O3 which enables low-voltage organic thin film operations. The dielectric characteristics of PVA/Nd2O3 bilayer films are studied by capacitance-voltage ( C- V) and current-voltage ( I- V) curves in the metal-insulator-metal (MIM) structure. We have analysed the output electrical responses and transfer characteristics of the OTFT devices to determine their performance of OTFT parameters. The mobility of 0.94 cm2/Vs, the threshold voltage of - 2.8 V, the current on-off ratio of 6.2 × 105, the subthreshold slope of 0.61 V/decade are evaluated. Low leakage current of the device is observed from current density-electric field ( J- E) curve. The structure and the morphology of the device are studied using X-ray diffraction (XRD) and atomic force microscope (AFM), respectively. The study demonstrates an effective way to realize low-voltage, high-performance OTFTs at low cost.

Fabrication of amorphous InGaZnO thin-film transistor with solution processed SrZrO3 gate insulator

NASA Astrophysics Data System (ADS)

Takahashi, Takanori; Oikawa, Kento; Hoga, Takeshi; Uraoka, Yukiharu; Uchiyama, Kiyoshi

2017-10-01

In this paper, we describe a method of fabrication of thin film transistors (TFTs) with high dielectric constant (high-k) gate insulator by a solution deposition. We chose a solution processed SrZrO3 as a gate insulator material, which possesses a high dielectric constant of 21 with smooth surface. The IGZO-TFT with solution processed SrZrO3 showed good switching property and enough saturation features, i.e. field effect mobility of 1.7cm2/Vs, threshold voltage of 4.8V, sub-threshold swing of 147mV/decade, and on/off ratio of 2.3×107. Comparing to the TFTs with conventional SiO2 gate insulator, the sub-threshold swing was improved by smooth surface and high field effect due to the high dielectric constant of SrZrO3. These results clearly showed that use of solution processed high-k SrZrO3 gate insulator could improve sub-threshold swing. In addition, the residual carbon originated from organic precursors makes TFT performances degraded.

Fully patterned p-channel SnO TFTs using transparent Al2O3 gate insulator and ITO as source and drain contacts

NASA Astrophysics Data System (ADS)

Guzmán-Caballero, D. E.; Quevedo-López, M. A.; De la Cruz, W.; Ramírez-Bon, R.

2018-03-01

SnO p-type was used as active layer to fabricate thin film transistors (TFTs) through photolithography and dry etching processes. The SnO p-type thin films (25 nm) were deposited by DC reactive sputtering with variable oxygen (O2) flow rate to then be annealed in air at 250 ◦C. Al2O3 gate dielectric (15 nm) was deposited by atomic layer deposition. Hall measurements showed p-type carrier concentration (N h ) of around 1 × 1018 cm-3 and Hall mobilities (μ Hall) between 0.35 and 2.64 cm2 V-1 s-1, depending on the O2 flow rate during deposition. The hole transport was dominated by variable-range hopping conduction. A change in the preferred crystalline orientation in the SnO films from (101) to (110) was associated with the increase in μ Hall. In addition, Raman vibrational modes at 110 and 209 cm-1 of polycrystalline SnO films showed certain dependence with the grain orientation. The SnO-based TFTs showed p-type behavior with low threshold voltages (V T ) and low sub threshold swing (SS) in the range from 1.76 to 3.50 V and 1.63 to 3.24 V/dec., respectively. The TFTs mobilities in the saturation regime (μ sat) were in the range of 0.12 and 1.32 cm2 V-1 s-1. The current on/off ratio (I ON/I OFF) was in the order of 102, approximately. The large values of the interface trap density (D IT) contributed to the high I OFF and the low I ON/I OFF of the TFTs.

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

NASA Astrophysics Data System (ADS)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Atomic layer deposition of dielectrics on graphene using reversibly physisorbed ozone.

PubMed

Jandhyala, Srikar; Mordi, Greg; Lee, Bongki; Lee, Geunsik; Floresca, Carlo; Cha, Pil-Ryung; Ahn, Jinho; Wallace, Robert M; Chabal, Yves J; Kim, Moon J; Colombo, Luigi; Cho, Kyeongjae; Kim, Jiyoung

2012-03-27

Integration of graphene field-effect transistors (GFETs) requires the ability to grow or deposit high-quality, ultrathin dielectric insulators on graphene to modulate the channel potential. Here, we study a novel and facile approach based on atomic layer deposition through ozone functionalization to deposit high-κ dielectrics (such as Al(2)O(3)) without breaking vacuum. The underlying mechanisms of functionalization have been studied theoretically using ab initio calculations and experimentally using in situ monitoring of transport properties. It is found that ozone molecules are physisorbed on the surface of graphene, which act as nucleation sites for dielectric deposition. The physisorbed ozone molecules eventually react with the metal precursor, trimethylaluminum to form Al(2)O(3). Additionally, we successfully demonstrate the performance of dual-gated GFETs with Al(2)O(3) of sub-5 nm physical thickness as a gate dielectric. Back-gated GFETs with mobilities of ~19,000 cm(2)/(V·s) are also achieved after Al(2)O(3) deposition. These results indicate that ozone functionalization is a promising pathway to achieve scaled gate dielectrics on graphene without leaving a residual nucleation layer. © 2012 American Chemical Society

Terahertz characterization of Y2O3-added AlN ceramics

NASA Astrophysics Data System (ADS)

Kang, Seung Beom; Chung, Dong Chul; Kim, Sung-Jin; Chung, Jun-Ki; Park, Sang-Yeup; Kim, Ki-Chul; Kwak, Min Hwan

2016-12-01

Terahertz optical and dielectric properties of AlN ceramics fabricated by hot pressed sintering are investigated by THz time-domain spectroscopy in the frequency range of 0.2-3.5 THz. The measured properties of the pure AlN ceramic are compared with those of Y2O3-added AlN ceramic. Two prominent resonance modes, which are essentially responsible for the dielectric properties of the Y2O3-added AlN in terahertz regime, are characterized at ωTO1/(2π) = 2.76 THz (92 cm-1) and ωTO2/(2π) = 18.2 THz (605 cm-1) and are well described by the pseudo-harmonic oscillator model through theoretical fitting. The resonance ωTO1 at 2.76 THz is proposed to be due to the formation of a YAG (Y3Al5O12) secondary phase in Y2O3-added AlN ceramic. From the experimental results, good correlation is observed between the prominent peak of YAG secondary phase at 2.76 THz and thermal conductivity. Additionally, there is a high correlation between densification and refractive index of AlN ceramics fabricated by hot pressed sintering.

Highly Mobile Two-Dimensional Electron Gases with a Strong Gating Effect at the Amorphous LaAlO3/KTaO3 Interface.

PubMed

Zhang, Hui; Zhang, Hongrui; Yan, Xi; Zhang, Xuejing; Zhang, Qinghua; Zhang, Jing; Han, Furong; Gu, Lin; Liu, Banggui; Chen, Yuansha; Shen, Baogen; Sun, Jirong

2017-10-18

Two-dimensional electron gas (2DEG) at the perovskite oxide interface exhibits a lot of exotic properties, presenting a promising platform for the exploration of emergent phenomena. While most of the previous works focused on SrTiO 3 -based 2DEG, here we report on the fabrication of high-quality 2DEGs by growing an amorphous LaAlO 3 layer on a (001)-orientated KTaO 3 substrate, which is a 5d metal oxide with a polar surface, at a high temperature that is usually adopted for crystalline LaAlO 3 . Metallic 2DEGs with a Hall mobility as high as ∼2150 cm 2 /(V s) and a sheet carrier density as low as 2 × 10 12 cm -2 are obtained. For the first time, the gating effect on the transport process is studied, and its influence on spin relaxation and inelastic and elastic scattering is determined. Remarkably, the spin relaxation time can be strongly tuned by a back gate. It is reduced by a factor of ∼69 while the gate voltage is swept from -25 to +100 V. The mechanism that dominates the spin relaxation is elucidated.

Top-gated field-effect LaAlO{sub 3}/SrTiO{sub 3} devices made by ion-irradiation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hurand, S.; Jouan, A.; Feuillet-Palma, C.

2016-02-01

We present a method to fabricate top-gated field-effect devices in a LaAlO{sub 3}/SrTiO{sub 3} two-dimensional electron gas (2-DEG). Prior to the gate deposition, the realisation of micron size conducting channels in the 2-DEG is achieved by an ion-irradiation with high-energy oxygen ions. After identifying the ion fluence as the key parameter that determines the electrical transport properties of the channels, we demonstrate the field-effect operation. At low temperature, the normal state resistance and the superconducting T{sub c} can be tuned over a wide range by a top-gate voltage without any leakage. A superconductor-to-insulator quantum phase transition is observed for amore » strong depletion of the 2-DEG.« less

Dependence of Pentacene Crystal Growth on Dielectric Roughness for Fabrication of Flexible Field-Effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, H.; Yang, C; Kim, S

2010-01-01

The dependence of pentacene nanostructures on gate dielectric surfaces were investigated for flexible organic field-effect transistor (OFET) applications. Two bilayer types of polymer/aluminum oxide (Al{sub 2}O{sub 3}) gate dielectrics were fabricated on commercial Al foils laminated onto a polymer back plate. Some Al foils were directly used as gate electrodes, and others were smoothly polished by an electrolytic etching. These Al surfaces were then anodized and coated with poly({alpha}-methyl styrene) (PAMS). For PAMS/Al{sub 2}O{sub 3} dielectrics onto etched Al foils, surface roughness up to 1 nm could be reached, although isolated dimples with a lateral diameter of several micrometers weremore » still present. On PAMS/Al{sub 2}O{sub 3} dielectrics (surface roughness >40 nm) containing mechanical grooves of Al foil, average hole mobility ({mu}FET) of 50 nm thick pentacene-FETs under the low operating voltages (|V| < 6 V) was {approx}0.15 cm{sup 2} V{sup -1} s{sup -1}. In contrast, pentacene-FETs employing the etched Al gates exhibited {mu}FET of 0.39 cm{sup 2} V{sup -1} s{sup -1}, which was comparable to that of reference samples with PAMS/Al{sub 2}O{sub 3} dielectrics onto flat sputtered Al gates. Conducting-probe atomic force microscopy and two-dimensional X-ray diffraction of pentacene films with various thicknesses revealed different out-of-plane and in-plane crystal orderings of pentacene, depending on the surface roughness of the gate dielectrics.« less

Structural and Electrical Characterization of SiO2 Gate Dielectrics Deposited from Solutions at Moderate Temperatures in Air.

PubMed

Esro, Mazran; Kolosov, Oleg; Jones, Peter J; Milne, William I; Adamopoulos, George

2017-01-11

Silicon dioxide (SiO 2 ) is the most widely used dielectric for electronic applications. It is usually produced by thermal oxidation of silicon or by using a wide range of vacuum-based techniques. By default, the growth of SiO 2 by thermal oxidation of silicon requires the use of Si substrates whereas the other deposition techniques either produce low quality or poor interface material and mostly require high deposition or annealing temperatures. Recent investigations therefore have focused on the development of alternative deposition paradigms based on solutions. Here, we report the deposition of SiO 2 thin film dielectrics deposited by spray pyrolysis in air at moderate temperatures of ≈350 °C from pentane-2,4-dione solutions of SiCl 4 . SiO 2 dielectrics were investigated by means of UV-vis absorption spectroscopy, spectroscopic ellipsometry, XPS, XRD, UFM/AFM, admittance spectroscopy, and field-effect measurements. Data analysis reveals smooth (R RMS < 1 nm) amorphous films with a dielectric constant of about 3.8, an optical band gap of ≈8.1 eV, leakage current densities in the order of ≈10 -7 A/cm 2 at 1 MV/cm, and high dielectric strength in excess of 5 MV/cm. XPS measurements confirm the SiO 2 stoichiometry and FTIR spectra reveal features related to SiO 2 only. Thin film transistors implementing spray-coated SiO 2 gate dielectrics and C 60 and pentacene semiconducting channels exhibit excellent transport characteristics, i.e., negligible hysteresis, low leakage currents, high on/off current modulation ratio on the order of 10 6 , and high carrier mobility.

Magneto-transport study of top- and back-gated LaAlO{sub 3}/SrTiO{sub 3} heterostructures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, W., E-mail: W.Liu@unige.ch; Gariglio, S.; Fête, A.

2015-06-01

We report a detailed analysis of magneto-transport properties of top- and back-gated LaAlO{sub 3}/SrTiO{sub 3} heterostructures. Efficient modulation in magneto-resistance, carrier density, and mobility of the two-dimensional electron liquid present at the interface is achieved by sweeping top and back gate voltages. Analyzing those changes with respect to the carrier density tuning, we observe that the back gate strongly modifies the electron mobility while the top gate mainly varies the carrier density. The evolution of the spin-orbit interaction is also followed as a function of top and back gating.

Effect of atomic layer deposition temperature on current conduction in Al2O3 films formed using H2O oxidant

NASA Astrophysics Data System (ADS)

Hiraiwa, Atsushi; Matsumura, Daisuke; Kawarada, Hiroshi

2016-08-01

To develop high-performance, high-reliability gate insulation and surface passivation technologies for wide-bandgap semiconductor devices, the effect of atomic layer deposition (ALD) temperature on current conduction in Al2O3 films is investigated based on the recently proposed space-charge-controlled field emission model. Leakage current measurement shows that Al2O3 metal-insulator-semiconductor capacitors formed on the Si substrates underperform thermally grown SiO2 capacitors at the same average field. However, using equivalent oxide field as a more practical measure, the Al2O3 capacitors are found to outperform the SiO2 capacitors in the cases where the capacitors are negatively biased and the gate material is adequately selected to reduce virtual dipoles at the gate/Al2O3 interface. The Al2O3 electron affinity increases with the increasing ALD temperature, but the gate-side virtual dipoles are not affected. Therefore, the leakage current of negatively biased Al2O3 capacitors is approximately independent of the ALD temperature because of the compensation of the opposite effects of increased electron affinity and permittivity in Al2O3. By contrast, the substrate-side sheet of charge increases with increasing ALD temperature above 210 °C and hence enhances the current of positively biased Al2O3 capacitors more significantly at high temperatures. Additionally, an anomalous oscillatory shift of the current-voltage characteristics with ALD temperature was observed in positively biased capacitors formed by low-temperature (≤210 °C) ALD. This shift is caused by dipoles at the Al2O3/underlying SiO2 interface. Although they have a minimal positive-bias leakage current, the low-temperature-grown Al2O3 films cause the so-called blisters problem when heated above 400 °C. Therefore, because of the absence of blistering, a 450 °C ALD process is presently the most promising technology for growing high-reliability Al2O3 films.

High kappa Dielectrics on InGaAs and GaN - Growth, Interfacial Structural Studies, and Surface Fermi Level Unpinning

DTIC Science & Technology

2011-04-20

ALD-Al2O3 and in-situ MBE-Al2O3/ Ga2O3 (Gd2O3) [GGO] as the gate dielectrics. The advances of the InGaAs MOSFETs achieved will enable future CMOS...and GaN MOSFETs:  High-performance self-aligned inversion-channel In0.53Ga0.47As and In0.75Ga0.25As MOSFET’s with Al2O3/ Ga2O3 (Gd2O3) as gate... Ga2O3 (Gd2O3) as gate dielectrics Key accomplishments in devices of 1m gate length: High drain current of 1.23 mA/m High transcoductance of 714

Deposition temperature dependent optical and electrical properties of ALD HfO{sub 2} gate dielectrics pretreated with tetrakisethylmethylamino hafnium

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, J.; School of Sciences, Anhui University of Science and Technology, Huainan 232001; He, G., E-mail: hegang@ahu.edu.cn

2015-10-15

Highlights: • ALD-derived HfO{sub 2} gate dielectrics have been deposited on Si substrates. • The leakage current mechanism for different deposition temperature was discussed. • Different emission at different field region has been determined precisely. - Abstract: The effect of deposition temperature on the growth rate, band gap energy and electrical properties of HfO{sub 2} thin film deposited by atomic layer deposition (ALD) has been investigated. By means of characterization of spectroscopy ellipsometry and ultraviolet–visible spectroscopy, the growth rate and optical constant of ALD-derived HfO{sub 2} gate dielectrics are determined precisely. The deposition temperature dependent electrical properties of HfO{sub 2}more » films were determined by capacitance–voltage (C–V) and leakage current density–voltage (J–V) measurements. The leakage current mechanism for different deposition temperature has been discussed systematically. As a result, the optimized deposition temperature has been obtained to achieve HfO{sub 2} thin film with high quality.« less

Electrical characterization of 4H-SiC metal-oxide-semiconductor structure with Al2O3 stacking layers as dielectric

NASA Astrophysics Data System (ADS)

Chang, P. K.; Hwu, J. G.

2018-02-01

Interface defects and oxide bulk traps conventionally play important roles in the electrical performance of SiC MOS device. Introducing the Al2O3 stack grown by repeated anodization of Al films can notably lower the leakage current in comparison to the SiO2 structure, and enhance the minority carrier response at low frequency when the number of Al2O3 layers increase. In addition, the interface quality is not deteriorated by the stacking of Al2O3 layers because the stacked Al2O3 structure grown by anodization possesses good uniformity. In this work, the capacitance equivalent thickness (CET) of stacking Al2O3 will be up to 19.5 nm and the oxidation process can be carried out at room temperature. For the Al2O3 gate stack with CET 19.5 nm on n-SiC substrate, the leakage current at 2 V is 2.76 × 10-10 A/cm2, the interface trap density at the flatband voltage is 3.01 × 1011 eV-1 cm-2, and the effective breakdown field is 11.8 MV/cm. Frequency dispersion and breakdown characteristics may thus be improved as a result of the reduction in trap density. The Al2O3 stacking layers are capable of maintaining the leakage current as low as possible even after constant voltage stress test, which will further ameliorate reliability characteristics.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

PubMed

Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

2012-08-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

PubMed Central

2012-01-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials. PMID:22853458

Low temperature solution processed high-κ ZrO2 gate dielectrics for nanoelectonics

NASA Astrophysics Data System (ADS)

Kumar, Arvind; Mondal, Sandip; Rao, K. S. R. Koteswara

2016-05-01

The high-κ gate dielectrics, specifically amorphous films offer salient features such as exceptional mechanical flexibility, smooth surfaces and better uniformity associated with low leakage current density. In this work, ∼35 nm thick amorphous ZrO2 films were deposited on silicon substrate at low temperature (300 °C, 1 h) from facile spin-coating method and characterized by various analytical techniques. The X-ray diffraction and X-ray photoelectron spectroscopy reveal the formation of amorphous phase ZrO2, while ellipsometry analysis together with the Atomic Force Microscope suggest the formation of dense film with surface roughness of 1.5 Å, respectively. The fabricated films were integrated in metal-oxide-semiconductor (MOS) structures to check the electrical capabilities. The oxide capacitance (Cox), flat band capacitance (CFB), flat band voltage (VFB), dielectric constant (κ) and oxide trapped charges (Qot) extracted from high frequency (1 MHz) C-V curve are 186 pF, 104 pF, 0.37 V, 15 and 2 × 10-11 C, respectively. The small flat band voltage 0.37 V, narrow hysteresis and very little frequency dispersion between 10 kHz-1 MHz suggest an excellent a-ZrO2/Si interface with very less trapped charges in the oxide. The films exhibit a low leakage current density 4.7 × 10-9 A/cm2 at 1 V. In addition, the charge transport mechanism across the MOSC is analyzed and found to have a strong bias dependence. The space charge limited conduction mechanism is dominant in the high electric field region (1.3-5 V) due to the presence of traps, while the trap-supported tunneling is prevailed in the intermediate region (0.35-1.3 V). Low temperature solution processed ZrO2 thin films obtained are of high quality and find their importance as a potential dielectric layer on Si and polymer based flexible electronics.

InP MOS capacitor and E-mode n-channel FET with ALD Al2O3-based high- k dielectric

NASA Astrophysics Data System (ADS)

Yen, Chih-Feng; Yeh, Min-Yen; Chong, Kwok-Keung; Hsu, Chun-Fa; Lee, Ming-Kwei

2016-07-01

The electrical characteristics of atomic-layer-deposited Al2O3/TiO2/Al2O3 on (NH4)2S-treated InP MOS capacitor and related MOSFET were studied. The electrical characteristics were improved from the reduction of native oxides and sulfur passivation on InP by (NH4)2S treatment. The high bandgap Al2O3 on TiO2 can reduce the thermionic emission, and the Al2O3 under TiO2 improves the interface-state density by self-cleaning. The high dielectric constant TiO2 is used to lower the equivalent oxide thickness. The leakage currents can reach 2.3 × 10-8 and 2.2 × 10-7 A/cm2 at ±2 MV/cm, respectively. The lowest interface-state density is 4.6 × 1011 cm-2 eV-1 with a low-frequency dispersion of 15 %. The fabricated enhancement-mode n-channel sulfur-treated InP MOSFET exhibits good electrical characteristics with a maximum transconductance of 146 mS/mm and effective mobility of 1760 cm2/V s. The subthreshold swing and threshold voltage are 117 mV/decade and 0.44 V, respectively.

Temperature-dependent field-effect carrier mobility in organic thin-film transistors with a gate SiO2 dielectric modified by H2O2 treatment

NASA Astrophysics Data System (ADS)

Lin, Yow-Jon; Hung, Cheng-Chun

2018-02-01

The effect of the modification of a gate SiO2 dielectric using an H2O2 solution on the temperature-dependent behavior of carrier transport for pentacene-based organic thin-film transistors (OTFTs) is studied. H2O2 treatment leads to the formation of Si(-OH) x (i.e., the formation of a hydroxylated layer) on the SiO2 surface that serves to reduce the SiO2 capacitance and weaken the pentacene-SiO2 interaction, thus increasing the field-effect carrier mobility ( µ) in OTFTs. The temperature-dependent behavior of carrier transport is dominated by the multiple trapping model. Note that H2O2 treatment leads to a reduction in the activation energy. The increased value of µ is also attributed to the weakening of the interactions of the charge carriers with the SiO2 dielectric that serves to reduce the activation energy.

Comparison of the physical, chemical and electrical properties of ALD Al 2 O 3 on c- and m- plane GaN: Comparison of the physical, chemical and electrical properties of ALD Al 2 O 3 on c- and m- plane GaN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, D.; Hossain, T.; Nepal, N.

2014-02-01

Our study compares the physical, chemical and electrical properties of Al 2O 3 thin films deposited on gallium polar c- and nonpolar m -plane GaN substrates by atomic layer deposition (ALD). Correlations were sought between the film's structure, composition, and electrical properties. The thickness of the Al 2O 3 films was 19.2 nm as determined from a Si witness sample by spectroscopic ellipsometry. We measured the gate dielectric was slightly aluminum-rich (Al:O=1:1.3) from X-ray photoelectron spectroscopy (XPS) depth profile, and the oxide-semiconductor interface carbon concentration was lower on c -plane GaN. The oxide's surface morphology was similar on both substrates,more » but was smoothest on c -plane GaN as determined by atomic force microscopy (AFM). Circular capacitors (50-300 μm diameter) with Ni/Au (20/100 nm) metal contacts on top of the oxide were created by standard photolithography and e-beam evaporation methods to form metal-oxide-semiconductor capacitors (MOSCAPs). Moreover, the alumina deposited on c -plane GaN showed less hysteresis (0.15 V) than on m -plane GaN (0.24 V) in capacitance-voltage (CV) characteristics, consistent with its better quality of this dielectric as evidenced by negligible carbon contamination and smooth oxide surface. These results demonstrate the promising potential of ALD Al 2O 3 on c -plane GaN, but further optimization of ALD is required to realize the best properties of Al 2O 3 on m -plane GaN.« less

Growth and characterization of Al2O3 films on fluorine functionalized epitaxial graphene

NASA Astrophysics Data System (ADS)

Robinson, Zachary R.; Jernigan, Glenn G.; Wheeler, Virginia D.; Hernández, Sandra C.; Eddy, Charles R.; Mowll, Tyler R.; Ong, Eng Wen; Ventrice, Carl A.; Geisler, Heike; Pletikosic, Ivo; Yang, Hongbo; Valla, Tonica

2016-08-01

Intelligent engineering of graphene-based electronic devices on SiC(0001) requires a better understanding of processes used to deposit gate-dielectric materials on graphene. Recently, Al2O3 dielectrics have been shown to form conformal, pinhole-free thin films by functionalizing the top surface of the graphene with fluorine prior to atomic layer deposition (ALD) of the Al2O3 using a trimethylaluminum (TMA) precursor. In this work, the functionalization and ALD-precursor adsorption processes have been studied with angle-resolved photoelectron spectroscopy, low energy electron diffraction, and X-ray photoelectron spectroscopy. It has been found that the functionalization process has a negligible effect on the electronic structure of the graphene, and that it results in a twofold increase in the adsorption of the ALD-precursor. In situ TMA-dosing and XPS studies were also performed on three different Si(100) substrates that were terminated with H, OH, or dangling Si-bonds. This dosing experiment revealed that OH is required for TMA adsorption. Based on those data along with supportive in situ measurements that showed F-functionalization increases the amount of oxygen (in the form of adsorbed H2O) on the surface of the graphene, a model for TMA-adsorption on graphene is proposed that is based on a reaction of a TMA molecule with OH.

Hydrogen sensors based on Sc2O3/AlGaN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Kang, B. S.; Mehandru, R.; Kim, S.; Ren, F.; Fitch, R. C.; Gillespie, J. K.; Moser, N.; Jessen, G.; Jenkins, T.; Dettmer, R.; Via, D.; Crespo, A.; Baik, K. H.; Gila, B. P.; Abernathy, C. R.; Pearton, S. J.

2005-05-01

Pt contacted AlGaN/GaN high electron mobility transistors with Sc2O3 gate dielectrics show reversible changes in drain-source current upon exposure to H2-containing ambients, even at room temperature. The changes in current (as high as 3 mA for relatively low gate voltage and drain-source voltage at 25 °C for the HEMTs and a change in forward current of 40 μA at a bias of 2.5 V was obtained for the MOS-diodes in response to a change in ambient from pure N2 to 10% H2/90% N2. The current changes in the latter case are almost linearly proportional to the testing temperature and reach around 400 μA at 400 °C. These signals are approximately an order of magnitude larger than for Pt /GaN Schottky diodes and a factor of 5 larger than Sc2O3/AlGaN/GaN metal-oxide semiconductor (MOS) diodes exposed under the same conditions. This shows the advantage of using a transistor structure in which the gain produces larger current changes upon exposure to hydrogen-containing ambients. The increase in current is the result of a decrease in effective barrier height of the MOS gate of 30-50 mV at 25 °C for 10%H2/90%N₂ ambients relative to pure N₂ and is due to catalytic dissociation of the H₂ on the Pt contact, followed by diffusion to the Sc₂O₃/AlGaN interface.

Miscibility of amorphous ZrO2-Al2O3 binary alloy

NASA Astrophysics Data System (ADS)

Zhao, C.; Richard, O.; Bender, H.; Caymax, M.; De Gendt, S.; Heyns, M.; Young, E.; Roebben, G.; Van Der Biest, O.; Haukka, S.

2002-04-01

Miscibility is a key factor for maintaining the homogeneity of the amorphous structure in a ZrO2-Al2O3 binary alloy high-k dielectric layer. In the present work, a ZrO2/Al2O3 laminate thin layer has been prepared by atomic layer chemical vapor deposition on a Si (100) wafer. This layer, with artificially induced inhomogeneity (lamination), enables one to study the change in homogeneity of the amorphous phase in the ZrO2/Al2O3 system during annealing. High temperature grazing incidence x-ray diffraction (HT-XRD) was used to investigate the change in intensity of the constructive interference peak of the x-ray beams which are reflected from the interfaces of ZrO2/Al2O3 laminae. The HT-XRD spectra show that the intensity of the peak decreases with an increase in the anneal temperature, and at 800 °C, the peak disappears. The same samples were annealed by a rapid thermal process (RTP) at temperatures between 700 and 1000 °C for 60 s. Room temperature XRD of the RTP annealed samples shows a similar decrease in peak intensity. Transmission electronic microscope images confirm that the laminate structure is destroyed by RTP anneals and, just below the crystallization onset temperature, a homogeneous amorphous ZrAlxOy phase forms. The results demonstrate that the two artificially separated phases, ZrO2 and Al2O3 laminae, tend to mix into a homogeneous amorphous phase before crystallization. This observation indicates that the thermal stability of ZrO2-Al2O3 amorphous phase is suitable for high-k applications.

The effect of Cr2O3 doping on structures and dielectric constants of SiO2-Bi2O3-B2O3-Na2CO3 glass based on silica gel of natural sand

NASA Astrophysics Data System (ADS)

Diantoro, M.; Zaini, M. B.; Muniroh, Z.; Nasikhudin; Hidayat, A.

2017-05-01

One of the abundant natural resources along the coastal lines of Indonesia is silica sand. One of the beaches which has a lot of silica content is Bancar-Tuban beach. Silica can be used as a raw material of glass that has multiple properties in optic, dielectric, and other physical properties by introducing specific dopants. Some oxides have been used as dopant e.g. Al2O3, Fe3O4, and NiO. However, there has not been any comprehensive study discussing the multiple properties of natural silica-sand-based glass with Cr2O3 dopant so far. A series of samples have been prepared, which mean two solid steps to state melting technique. Cr2O3 was selected as a dopant due to its potential to control its color and to increase the dielectric constant of the glass. The synthesis of silica (SiO2) sand from BancarTuban beach was conducted through the sol-gel process. The composition varied as the addition of Cr2O3on 50SiO2-25B2O3-(6.5-x) Bi2O3-18.5Na2CO3-xCr2O3 (x = 0, 0.02, 0.04, 0.06 and 0.08mol), later called SBBN glass. The samples’ characterizations of the structure and morphology were conducted through the use of XRD, and SEM-EDX. The measurements were done by using a DC capacitance meter in order to investigate the dielectric properties of the sample, under the influence of light. It is shown that addition of Cr2O3 did not alter the crystal structure but changed the structure of the functional bond formation. It is also revealed that the dielectric constant increased along with the increasing of Cr2O3. An interesting result was that the dielectric constant of the glass was quantized decreasingly as the increase of light.

Comparing electrical characteristics of in situ and ex situ Al2O3/GaN interfaces formed by metalorganic chemical vapor deposition

NASA Astrophysics Data System (ADS)

Chan, Silvia H.; Bisi, Davide; Tahhan, Maher; Gupta, Chirag; DenBaars, Steven P.; Keller, Stacia; Zanoni, Enrico; Mishra, Umesh K.

2018-04-01

Al2O3/n-GaN MOS-capacitors grown by metalorganic chemical vapor deposition with in-situ- and ex-situ-formed Al2O3/GaN interfaces were characterized. Capacitors grown entirely in situ exhibited ˜4 × 1012 cm-2 fewer positive fixed charges and up to ˜1 × 1013 cm-2 eV-1 lower interface-state density near the band-edge than did capacitors with ex situ oxides. When in situ Al2O3/GaN interfaces were reformed via the insertion of a 10-nm-thick GaN layer, devices exhibited behavior between the in situ and ex situ limits. These results illustrate the extent to which an in-situ-formed dielectric/GaN gate stack improves the interface quality and breakdown performance.

Nanostructured bilayer anodic TiO2/Al2O3 metal-insulator-metal capacitor.

PubMed

Karthik, R; Kannadassan, D; Baghini, Maryam Shojaei; Mallick, P S

2013-10-01

This paper presents the fabrication of high performance bilayer TiO2/Al2O3 Metal-Insulator-Metal capacitor using anodization technique. A high capacitance density of 7 fF/microm2, low quadratic voltage coefficient of capacitance of 150 ppm/V2 and a low leakage current density of 9.1 nA/cm2 at 3 V are achieved which are suitable for Analog and Mixed signal applications. The influence of anodization voltage on structural and electrical properties of dielectric stack is studied in detail. At higher anodization voltages, we have observed the transformation of amorphous to crystalline state of TiO2/Al2O3 and improvement of electrical properties.

Physical understanding of trends in current collapse with atomic layer deposited dielectrics in AlGaN/GaN MOS heterojunction FETs

NASA Astrophysics Data System (ADS)

Ramanan, Narayanan; Lee, Bongmook; Misra, Veena

2016-03-01

Many passivation dielectrics are pursued for suppressing current collapse due to trapping/detrapping of access-region surface traps in AlGaN/GaN based metal oxide semiconductor heterojuction field effect transistors (MOS-HFETs). The suppression of current collapse can potentially be achieved either by reducing the interaction of surface traps with the gate via surface leakage current reduction, or by eliminating surface traps that can interact with the gate. But, the latter is undesirable since a high density of surface donor traps is required to sustain a high 2D electron gas density at the AlGaN/GaN heterointerface and provide a low ON-resistance. This presents a practical trade-off wherein a passivation dielectric with the optimal surface trap characteristics and minimal surface leakage is to be chosen. In this work, we compare MOS-HFETs fabricated with popular ALD gate/passivation dielectrics like SiO2, Al2O3, HfO2 and HfAlO along with an additional thick plasma-enhanced chemical vapor deposition SiO2 passivation. It is found that after annealing in N2 at 700 °C, the stack containing ALD HfAlO provides a combination of low surface leakage and a high density of shallow donor traps. Physics-based TCAD simulations confirm that this combination of properties helps quick de-trapping and minimal current collapse along with a low ON resistance.

Effect of an Interfacial Layer on Electron Tunneling through Atomically Thin Al2O3 Tunnel Barriers.

PubMed

Wilt, Jamie; Sakidja, Ridwan; Goul, Ryan; Wu, Judy Z

2017-10-25

Electron tunneling through high-quality, atomically thin dielectric films can provide a critical enabling technology for future microelectronics, bringing enhanced quantum coherent transport, fast speed, small size, and high energy efficiency. A fundamental challenge is in controlling the interface between the dielectric and device electrodes. An interfacial layer (IL) will contain defects and introduce defects in the dielectric film grown atop, preventing electron tunneling through the formation of shorts. In this work, we present the first systematic investigation of the IL in Al 2 O 3 dielectric films of 1-6 Å's in thickness on an Al electrode. We integrated several advanced approaches: molecular dynamics to simulate IL formation, in situ high vacuum sputtering atomic layer deposition (ALD) to synthesize Al 2 O 3 on Al films, and in situ ultrahigh vacuum scanning tunneling spectroscopy to probe the electron tunneling through the Al 2 O 3 . The IL had a profound effect on electron tunneling. We observed a reduced tunnel barrier height and soft-type dielectric breakdown which indicate that defects are present in both the IL and in the Al 2 O 3 . The IL forms primarily due to exposure of the Al to trace O 2 and/or H 2 O during the pre-ALD heating step of fabrication. As the IL was systematically reduced, by controlling the pre-ALD sample heating, we observed an increase of the ALD Al 2 O 3 barrier height from 0.9 to 1.5 eV along with a transition from soft to hard dielectric breakdown. This work represents a key step toward the realization of high-quality, atomically thin dielectrics with electron tunneling for the next generation of microelectronics.

Determining oxide trapped charges in Al2O3 insulating films on recessed AlGaN/GaN heterostructures by gate capacitance transients measurements

NASA Astrophysics Data System (ADS)

Fiorenza, Patrick; Greco, Giuseppe; Schilirò, Emanuela; Iucolano, Ferdinando; Lo Nigro, Raffaella; Roccaforte, Fabrizio

2018-05-01

This letter presents time-dependent gate-capacitance transient measurements (C–t) to determine the oxide trapped charges (N ot) in Al2O3 films deposited on recessed AlGaN/GaN heterostructures. The C–t transients acquired at different temperatures under strong accumulation allowed to accurately monitor the gradual electron trapping, while hindering the re-emission by fast traps that may affect conventional C–V hysteresis measurements. Using this method, an increase of N ot from 2 to 6 × 1012 cm‑2 was estimated between 25 and 150 °C. The electron trapping is ruled by an Arrhenius dependence with an activation energy of 0.12 eV which was associated to points defects present in the Al2O3 films.

The electrical performance and gate bias stability of an amorphous InGaZnO thin-film transistor with HfO2 high-k dielectrics

NASA Astrophysics Data System (ADS)

Wang, Ruo Zheng; Wu, Sheng Li; Li, Xin Yu; Zhang, Jin Tao

2017-07-01

In this study, we set out to fabricate an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with SiNx/HfO2/SiNx (SHS) sandwiched dielectrics. The J-V and C-V of this SHS film were extracted by the Au/p-Si/SHS/Ti structure. At room temperature the a-IGZO with SHS dielectrics showed the following electrical properties: a threshold voltage of 2.9 V, a subthreshold slope of 0.35 V/decade, an on/off current ratio of 3.5 × 107, and a mobility of 12.8 cm2 V-1 s-1. Finally, we tested the influence of gate bias stress on the TFT, and the result showed that the threshold voltage shifted to a positive voltage when applying a positive gate voltage to the TFT.

Atomic-layer-deposited Al2O3 and HfO2 on InAlAs: A comparative study of interfacial and electrical characteristics

NASA Astrophysics Data System (ADS)

Wu, Li-Fan; Zhang, Yu-Ming; Lv, Hong-Liang; Zhang, Yi-Men

2016-10-01

Al2O3 and HfO2 thin films are separately deposited on n-type InAlAs epitaxial layers by using atomic layer deposition (ALD). The interfacial properties are revealed by angle-resolved x-ray photoelectron spectroscopy (AR-XPS). It is demonstrated that the Al2O3 layer can reduce interfacial oxidation and trap charge formation. The gate leakage current densities are 1.37 × 10-6 A/cm2 and 3.22 × 10-6 A/cm2 at +1 V for the Al2O3/InAlAs and HfO2/InAlAs MOS capacitors respectively. Compared with the HfO2/InAlAs metal-oxide-semiconductor (MOS) capacitor, the Al2O3/InAlAs MOS capacitor exhibits good electrical properties in reducing gate leakage current, narrowing down the hysteresis loop, shrinking stretch-out of the C-V characteristics, and significantly reducing the oxide trapped charge (Q ot) value and the interface state density (D it). Project supported by the National Basic Research Program of China (Grant No. 2010CB327505), the Advanced Research Foundation of China (Grant No. 914xxx803-051xxx111), the National Defense Advance Research Project, China (Grant No. 513xxxxx306), the National Natural Science Foundation of China (Grant No. 51302215), the Scientific Research Program Funded by Shaanxi Provincial Education Department, China (Grant No. 14JK1656), and the Science and Technology Project of Shaanxi Province, China (Grant No. 2016KRM029).

Development of Al2O3 fiber-reinforced Al2O3-based ceramics.

PubMed

Tanimoto, Yasuhiro; Nemoto, Kimiya

2004-09-01

The purpose of this study was to use a tape casting technique to develop an Al2O3 fiber-reinforced Al2O3-based ceramic material (Al2O3-fiber/Al2O3 composite) into a new type of dental ceramic. The Al2O3-based ceramic used a matrix consisting of 60 wt% Al2O3 powder and 40 wt% SiO2-B2O3 powder. The prepreg sheets of Al2O3-fiber/Al2O3 composite (in which uniaxially aligned Al2O3 fibers were infiltrated with the Al2O3-based matrix) were fabricated continuously using tape casting technique with a doctor blade system. Multilayer preforms of Al2O3-fiber/Al2O3 composite sheets were then sintered at a maximum temperature of 1000 degrees C under an atmospheric pressure in a furnace. The results showed that the shrinkage and bending properties of Al2O3-fiber/Al2O3 composite exceeded those of unreinforced Al2O3--hence demonstrating the positive effects of fiber reinforcement. In conclusion, the tape casting technique has been utilized to successfully develop a new type of dental ceramic material.

Effect of DC bias on dielectric properties of nanocrystalline CuAlO2

NASA Astrophysics Data System (ADS)

Prakash, T.; Ramasamy, S.; Murty, B. S.

2013-03-01

Grain boundary effect on the room temperature dielectric behavior in mechanically alloyed nanocrystalline CuAlO2 has been investigated using impedance spectroscopy under the applied DC bias voltages 0 V to 4.8 V in a periodic interval of 0.2 V. Analysis of impedance data confirms the existence of double Schottky potential barrier heights ( Φ b ) between two adjacent grains (left and right side) with grain boundary and its influences in dielectric relaxation time ( τ), dielectric constant ( ɛ') and dielectric loss (tan δ) factor. Also, clear evidence on the suppression of Φ b was demonstrated in the higher applied bias voltages with the parameter τ. At equilibrium state, τ is 0.63 ms and it was reduced to 0.13 ms after the 3.2 V applied DC bias. These observed DC bias voltage effects are obeying `brick layer model' and also elucidates Φ b is playing a crucial role in controlling dielectric properties of nanomaterials.

Colossal dielectric permittivity in (Al + Nb) co-doped rutile SnO2 ceramics with low loss at room temperature

NASA Astrophysics Data System (ADS)

Song, Yongli; Wang, Xianjie; Zhang, Xingquan; Qi, Xudong; Liu, Zhiguo; Zhang, Lingli; Zhang, Yu; Wang, Yang; Sui, Yu; Song, Bo

2016-10-01

The exploration of colossal dielectric permittivity (CP) materials with low dielectric loss in a wide range of frequencies/temperatures continues to attract considerable interest. In this paper, we report CP in (Al + Nb) co-doped rutile SnO2 ceramics with a low dielectric loss at room temperature. Al0.02Nb0.05Sn0.93O2 and Al0.03Nb0.05Sn0.92O2 ceramics exhibit high relative dielectric permittivities (above 103) and low dielectric losses (0.015 < tan δ < 0.1) in a wide range of frequencies and at temperatures from 140 to 400 K. Al doping can effectively modulate the dielectric behavior by increasing the grain and grain boundary resistances. The large differences in the resistance and conductive activation energy of the grains and grain boundaries suggest that the CP in co-doped SnO2 ceramics can be attributed to the internal barrier layer capacitor effect.

Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates.

PubMed

Zhang, Liangliang; Guo, Yuzheng; Hassan, Vinayak Vishwanath; Tang, Kechao; Foad, Majeed A; Woicik, Joseph C; Pianetta, Piero; Robertson, John; McIntyre, Paul C

2016-07-27

Optimization of the interface between high-k dielectrics and SiGe substrates is a challenging topic due to the complexity arising from the coexistence of Si and Ge interfacial oxides. Defective high-k/SiGe interfaces limit future applications of SiGe as a channel material for electronic devices. In this paper, we identify the surface layer structure of as-received SiGe and Al2O3/SiGe structures based on soft and hard X-ray photoelectron spectroscopy. As-received SiGe substrates have native SiOx/GeOx surface layers, where the GeOx-rich layer is beneath a SiOx-rich surface. Silicon oxide regrows on the SiGe surface during Al2O3 atomic layer deposition, and both SiOx and GeOx regrow during forming gas anneal in the presence of a Pt gate metal. The resulting mixed SiOx-GeOx interface layer causes large interface trap densities (Dit) due to distorted Ge-O bonds across the interface. In contrast, we observe that oxygen-scavenging Al top gates decompose the underlying SiOx/GeOx, in a selective fashion, leaving an ultrathin SiOx interfacial layer that exhibits dramatically reduced Dit.

Biosensor properties of SOI nanowire transistors with a PEALD Al{sub 2}O{sub 3} dielectric protective layer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Popov, V. P., E-mail: popov@isp.nsc.ru; Ilnitskii, M. A.; Zhanaev, E. D.

2016-05-15

The properties of protective dielectric layers of aluminum oxide Al{sub 2}O{sub 3} applied to prefabricated silicon-nanowire transistor biochips by the plasma enhanced atomic layer deposition (PEALD) method before being housed are studied depending on the deposition and annealing modes. Coating the natural silicon oxide with a nanometer Al{sub 2}O{sub 3} layer insignificantly decreases the femtomole sensitivity of biosensors, but provides their stability in bioliquids. In deionized water, transistors with annealed aluminum oxide are closed due to the trapping of negative charges of <(1–10) × 10{sup 11} cm{sup −2} at surface states. The application of a positive potential to the substratemore » (V{sub sub} > 25 V) makes it possible to eliminate the negative charge and to perform multiple measurements in liquid at least for half a year.« less

Electrical Performance and Reliability Improvement of Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors with HfO2 Gate Dielectrics by CF4 Plasma Treatment

PubMed Central

Fan, Ching-Lin; Tseng, Fan-Ping; Tseng, Chiao-Yuan

2018-01-01

In this work, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a HfO2 gate insulator and CF4 plasma treatment was demonstrated for the first time. Through the plasma treatment, both the electrical performance and reliability of the a-IGZO TFT with HfO2 gate dielectric were improved. The carrier mobility significantly increased by 80.8%, from 30.2 cm2/V∙s (without treatment) to 54.6 cm2/V∙s (with CF4 plasma treatment), which is due to the incorporated fluorine not only providing an extra electron to the IGZO, but also passivating the interface trap density. In addition, the reliability of the a-IGZO TFT with HfO2 gate dielectric has also been improved by the CF4 plasma treatment. By applying the CF4 plasma treatment to the a-IGZO TFT, the hysteresis effect of the device has been improved and the device’s immunity against moisture from the ambient atmosphere has been enhanced. It is believed that the CF4 plasma treatment not only significantly improves the electrical performance of a-IGZO TFT with HfO2 gate dielectric, but also enhances the device’s reliability. PMID:29772767

Limitations of threshold voltage engineering of AlGaN/GaN heterostructures by dielectric interface charge density and manipulation by oxygen plasma surface treatments

NASA Astrophysics Data System (ADS)

Lükens, G.; Yacoub, H.; Kalisch, H.; Vescan, A.

2016-05-01

The interface charge density between the gate dielectric and an AlGaN/GaN heterostructure has a significant impact on the absolute value and stability of the threshold voltage Vth of metal-insulator-semiconductor (MIS) heterostructure field effect transistor. It is shown that a dry-etching step (as typically necessary for normally off devices engineered by gate-recessing) before the Al2O3 gate dielectric deposition introduces a high positive interface charge density. Its origin is most likely donor-type trap states shifting Vth to large negative values, which is detrimental for normally off devices. We investigate the influence of oxygen plasma annealing techniques of the dry-etched AlGaN/GaN surface by capacitance-voltage measurements and demonstrate that the positive interface charge density can be effectively compensated. Furthermore, only a low Vth hysteresis is observable making this approach suitable for threshold voltage engineering. Analysis of the electrostatics in the investigated MIS structures reveals that the maximum Vth shift to positive voltages achievable is fundamentally limited by the onset of accumulation of holes at the dielectric/barrier interface. In the case of the Al2O3/Al0.26Ga0.74N/GaN material system, this maximum threshold voltage shift is limited to 2.3 V.

Evolution of subband structure with gate-tuning at LaAlO3/SrTiO3 interfaces

NASA Astrophysics Data System (ADS)

Tang, Lucas; Smink, Sander; van Heeringen, Linde; Geessinck, Jaap; Rana, Abimanuya; Rastogi, Ankur; Maan, Jan Kees; Brinkman, Alexander; Zeitler, Uli; Hilgenkamp, Hans; McCollam, Alix

The outstanding characteristic of LaAlO3/SrTiO3 heterostructures is the formation of a high mobility 2D electron gas (2DEG) at the interface. The additional presence of superconductivity, magnetism and large spin-orbit coupling in these systems suggests that strong correlations play an important role in the electronic properties, in contrast to conventional semiconductor-based 2DEGs. Knowledge of the electronic bandstructure, and the interdependence of conduction electron density and properties is therefore essential for our understanding of these materials. We present new results of low temperature transport measurements in a high mobility LaAlO3/SrTiO3-based heterostructure, in magnetic fields up to 33 T. Shubnikov de-Haas oscillations are observed, revealing several subbands with different carrier densities. By application of an electric field in the back gate geometry, the Fermi level is tuned and thus we are able to map the smooth evolution of the subbands and their properties with carrier density. These results are in good agreement with recent theoretical work, such that we can disentangle the complex band structure, and quantify aspects such as Rashba spin-splitting and the mixing of orbital character.

Surface morphological properties of Ag-Al2O3 nanocermet layers using dip-coating technique

NASA Astrophysics Data System (ADS)

Muhammad, Nor Adhila; Suhaimi, Siti Fatimah; Zubir, Zuhana Ahmad; Daud, Sahhidan

2017-12-01

Ag-Al2O3 nanocermet layer was deposited on Cu coated glass substrate using dip-coating technique. The aim of this study was to observe the surface morphology properties of Ag-Al2O3 nanocermet layers after annealing process at 350°C in H2. The surface morphology of Ag-Al2O3 nanocermet will be characterized by Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM) and X-Ray Diffractometer (XRD), respectively. The results show that nearly isolated Ag particles having a large and small size were present in the Al2O3 dielectric matrix after annealing process. The face centered cubic crystalline structure of Ag nanoparticles inclusion in the amorphous alumina dielectric matrix was confirmed using XRD pattern and supported by EDX spectra analysis.

Ambipolar transport in CVD grown MoSe2 monolayer using an ionic liquid gel gate dielectric

NASA Astrophysics Data System (ADS)

Ortiz, Deliris N.; Ramos, Idalia; Pinto, Nicholas J.; Zhao, Meng-Qiang; Kumar, Vinayak; Johnson, A. T. Charlie

2018-03-01

CVD grown MoSe2 monolayers were electrically characterized at room temperature in a field effect transistor (FET) configuration using an ionic liquid (IL) as the gate dielectric. During the growth, instead of using MoO3 powder, ammonium heptamolybdate was used for better Mo control of the source and sodium cholate added for lager MoSe2 growth areas. In addition, a high specific capacitance (˜7 μF/cm2) IL was used as the gate dielectric to significantly reduce the operating voltage. The device exhibited ambipolar charge transport at low voltages with enhanced parameters during n- and p-FET operation. IL gating thins the Schottky barrier at the metal/semiconductor interface permitting efficient charge injection into the channel and reduces the effects of contact resistance on device performance. The large specific capacitance of the IL was also responsible for a much higher induced charge density compared to the standard SiO2 dielectric. The device was successfully tested as an inverter with a gain of ˜2. Using a common metal for contacts simplifies fabrication of this ambipolar device, and the possibility of radiative recombination of holes and electrons could further extend its use in low power optoelectronic applications.

Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

NASA Astrophysics Data System (ADS)

Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

2015-06-01

High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

Surfactant-assisted morphological studies of α-Al2O3 nanoparticles

NASA Astrophysics Data System (ADS)

Shah, Janki; Ranjan, Mukesh; Gupta, Sanjeev K.; Sonvane, Yogesh

2018-05-01

The present study deals with the synthesis and characterization of aluminum oxide (Al2O3) nanopowders, it is very useful material as dielectric, ceramic and catalyst. The high-quality nanopowders were obtained by adding surfactants urea and sodium acetate. Further, all characterizations are done for with (urea and sodium acetate) and without surfactant. X-ray diffraction was used to characterize phase formation and the crystallite size of powder while, FTIR gives information about the particle composition and surface intermediates. X-ray diffraction spectra revealed the synthesized nanoparticles phase transformation were γ-Al2O3 to α-Al2O3 phase. Furthermore, the addition of urea and sodium acetate significantly reduced the crystalline size of α-Al2O3 nanoparticles from 43.94 nm to 35.12 nm respectively.

Effect of atomic layer deposition temperature on current conduction in Al{sub 2}O{sub 3} films formed using H{sub 2}O oxidant

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hiraiwa, Atsushi, E-mail: hiraiwa@aoni.waseda.jp, E-mail: qs4a-hriw@asahi-net.or.jp; Matsumura, Daisuke; Kawarada, Hiroshi, E-mail: kawarada@waseda.jp

To develop high-performance, high-reliability gate insulation and surface passivation technologies for wide-bandgap semiconductor devices, the effect of atomic layer deposition (ALD) temperature on current conduction in Al{sub 2}O{sub 3} films is investigated based on the recently proposed space-charge-controlled field emission model. Leakage current measurement shows that Al{sub 2}O{sub 3} metal-insulator-semiconductor capacitors formed on the Si substrates underperform thermally grown SiO{sub 2} capacitors at the same average field. However, using equivalent oxide field as a more practical measure, the Al{sub 2}O{sub 3} capacitors are found to outperform the SiO{sub 2} capacitors in the cases where the capacitors are negatively biased andmore » the gate material is adequately selected to reduce virtual dipoles at the gate/Al{sub 2}O{sub 3} interface. The Al{sub 2}O{sub 3} electron affinity increases with the increasing ALD temperature, but the gate-side virtual dipoles are not affected. Therefore, the leakage current of negatively biased Al{sub 2}O{sub 3} capacitors is approximately independent of the ALD temperature because of the compensation of the opposite effects of increased electron affinity and permittivity in Al{sub 2}O{sub 3}. By contrast, the substrate-side sheet of charge increases with increasing ALD temperature above 210 °C and hence enhances the current of positively biased Al{sub 2}O{sub 3} capacitors more significantly at high temperatures. Additionally, an anomalous oscillatory shift of the current-voltage characteristics with ALD temperature was observed in positively biased capacitors formed by low-temperature (≤210 °C) ALD. This shift is caused by dipoles at the Al{sub 2}O{sub 3}/underlying SiO{sub 2} interface. Although they have a minimal positive-bias leakage current, the low-temperature-grown Al{sub 2}O{sub 3} films cause the so-called blisters problem when heated above 400 °C. Therefore, because of the absence of blistering

Medium band gap polymer based solution-processed high-κ composite gate dielectrics for ambipolar OFET

NASA Astrophysics Data System (ADS)

Canımkurbey, Betül; Unay, Hande; Çakırlar, Çiğdem; Büyükköse, Serkan; Çırpan, Ali; Berber, Savas; Altürk Parlak, Elif

2018-03-01

The authors present a novel ambipolar organic filed-effect transistors (OFETs) composed of a hybrid dielectric thin film of Ta2O5:PMMA nanocomposite material, and solution processed poly(selenophene, benzotriazole and dialkoxy substituted [1,2-b:4, 5-b‧] dithiophene (P-SBTBDT)-based organic semiconducting material as the active layer of the device. We find that the Ta2O5:PMMA insulator shows n-type conduction character, and its combination with the p-type P-SBTBDT organic semiconductor leads to an ambipolar OFET device. Top-gated OFETs were fabricated on glass substrate consisting of interdigitated ITO electrodes. P-SBTBDT-based material was spin coated on the interdigitated ITO electrodes. Subsequently, a solution processed Ta2O5:PMMA nanocomposite material was spin coated, thereby creating the gate dielectric layer. Finally, as a gate metal, an aluminum layer was deposited by thermal evaporation. The fabricated OFETs exhibited an ambipolar performance with good air-stability, high field-induced current and relatively high electron and hole mobilities although Ta2O5:PMMA nanocomposite films have slightly higher leakage current compared to the pure Ta2O5 films. Dielectric properties of the devices with different ratios of Ta2O5:PMMA were also investigated. The dielectric constant varied between 3.6 and 5.3 at 100 Hz, depending on the Ta2O5:PMMA ratio.

Preparation of magnetron sputtered ZrO2 films on Si for gate dielectric application

NASA Astrophysics Data System (ADS)

Kondaiah, P.; Mohan Rao, G.; Uthanna, S.

2012-11-01

Zirconium oxide (ZrO2) thin films were deposited on to p - Si and quartz substrates by sputtering of zirconium target at an oxygen partial pressure of 4x10-2 Pa and sputter pressure of 0.4 Pa by using DC reactive magnetron sputtering technique. The effect of annealing temperature on structural, optical, electrical and dielectric properties of the ZrO2 films was systematically studied. The as-deposited films were mixed phases of monoclinic and orthorhombic ZrO2. As the annealing temperature increased to 1073 K, the films were transformed in to single phase orthorhombic ZrO2. Fourier transform infrared studies conform the presence of interfacial layer between Si and ZrO2. The optical band gap and refractive index of the as-deposited films were 5.82 eV and 1.81. As the annealing temperature increased to 1073 K the optical band gap and refractive index increased to 5.92 eV and 2.10 respectively. The structural changes were influenced the capacitance-voltage and current-voltage characteristics of Al/ZrO2/p-Si capacitors. The dielectric constant was increased from 11.6 to 24.5 and the leakage current was decreased from 1.65×10-7 to 3.30×10-9 A/ cm2 for the as-deposited and annealed at 1073 K respectively.

Dielectric Properties of BST/(Y 2O 3) x(ZrO 2) 1-x/BST Trilayer Films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sahoo, Santosh K.; Misra, D.

2011-01-31

Thin films of Ba1-xSrxTiO3 (BST) are being actively investigated for applications in dynamic random access memories (DRAM) because of their properties such as high dielectric constant, low leakage current, and high dielectric breakdown strength. Various approaches have been used to improve the dielectric properties of BST thin films such as doping, graded compositions, and multilayer structures. We have found that inserting a ZrO2 layer in between two BST layers results in a significant reduction in dielectric constant as well as dielectric loss. In this work the effect of Y2O3 doped ZrO2 on the dielectric properties of BST/ZrO2/BST trilayer structure ismore » studied. The structure Ba0.8Sr0.2TiO3/(Y2O3)x(ZrO2)1-x/Ba0.8Sr0.2TiO3 is deposited by a sol-gel process on platinized Si substrate. The composition (x) of the middle layer is varied while keeping the total thickness of the trilayer film constant. The dielectric constant of the multilayer film decreases with the increase of Y2O3 amount in the film whereas there is a slight variation in dielectric loss. In Y2O3 doped multilayer thin films, the dielectric loss is lower in comparison to other films and also there is good frequency stability in the loss in the measured frequency range and hence very suitable for microwave device applications.« less

Performance and Stability Enhancement of In-Sn-Zn-O TFTs Using SiO2 Gate Dielectrics Grown by Low Temperature Atomic Layer Deposition.

PubMed

Sheng, Jiazhen; Han, Ju-Hwan; Choi, Wan-Ho; Park, Jozeph; Park, Jin-Seong

2017-12-13

Silicon dioxide (SiO 2 ) films were synthesized by plasma-enhanced atomic layer deposition (PEALD) using BTBAS [bis(tertiarybutylamino) silane] as the precursor and O 2 plasma as the reactant, at a temperature range from 50 to 200 °C. While dielectric constant values larger than 3.7 are obtained at all deposition temperatures, the leakage current levels are drastically reduced to below 10 -12 A at temperatures above 150 °C, which are similar to those obtained in thermally oxidized and PECVD grown SiO 2 . Thin film transistors (TFTs) based on In-Sn-Zn-O (ITZO) semiconductors were fabricated using thermal SiO 2 , PECVD SiO 2 , and PEALD SiO 2 grown at 150 °C as the gate dielectrics, and superior device performance and stability are observed in the last case. A linear field effect mobility of 68.5 cm 2 /(V s) and a net threshold voltage shift (ΔV th ) of approximately 1.2 V under positive bias stress (PBS) are obtained using the PEALD SiO 2 as the gate insulator. The relatively high concentration of hydrogen in the PEALD SiO 2 is suggested to induce a high carrier density in the ITZO layer deposited onto it, which results in enhanced charge transport properties. Also, it is most likely that the hydrogen atoms have passivated the electron traps related to interstitial oxygen defects, thus resulting in improved stability under PBS. Although the PECVD SiO 2 contains a hydrogen concentration similar to that of PEALD SiO 2 , its relatively large surface roughness appears to induce scattering effects and the generation of electron traps, which result in inferior device performance and stability.

SnO2-gated AlGaN/GaN high electron mobility transistors based oxygen sensors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hung, S.T.; Chung, Chi-Jung; Chen, Chin Ching

2012-01-01

Hydrothermally grown SnO2 was integrated with AlGaN/GaN high electron mobility transistor (HEMT) sensor as the gate electrode for oxygen detection. The crystalline of the SnO2 was improved after annealing at 400 C. The grain growth kinetics of the SnO2 nanomaterials, together with the O2 gas sensing properties and sensing mechanism of the SnO2 gated HEMT sensors were investigated. Detection of 1% oxygen in nitrogen at 100 C was possible. A low operation temperature and low power consumption oxygen sensor can be achieved by combining the SnO2 films with the AlGaN/GaN HEMT structure

Field-effect control of superconductivity and Rashba spin-orbit coupling in top-gated LaAlO3/SrTiO3 devices

PubMed Central

Hurand, S.; Jouan, A.; Feuillet-Palma, C.; Singh, G.; Biscaras, J.; Lesne, E.; Reyren, N.; Barthélémy, A.; Bibes, M.; Villegas, J. E.; Ulysse, C.; Lafosse, X.; Pannetier-Lecoeur, M.; Caprara, S.; Grilli, M.; Lesueur, J.; Bergeal, N.

2015-01-01

The recent development in the fabrication of artificial oxide heterostructures opens new avenues in the field of quantum materials by enabling the manipulation of the charge, spin and orbital degrees of freedom. In this context, the discovery of two-dimensional electron gases (2-DEGs) at LaAlO3/SrTiO3 interfaces, which exhibit both superconductivity and strong Rashba spin-orbit coupling (SOC), represents a major breakthrough. Here, we report on the realisation of a field-effect LaAlO3/SrTiO3 device, whose physical properties, including superconductivity and SOC, can be tuned over a wide range by a top-gate voltage. We derive a phase diagram, which emphasises a field-effect-induced superconductor-to-insulator quantum phase transition. Magneto-transport measurements show that the Rashba coupling constant increases linearly with the interfacial electric field. Our results pave the way for the realisation of mesoscopic devices, where these two properties can be manipulated on a local scale by means of top-gates. PMID:26244916

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11,000 cm(2)/V·s.

PubMed

Smith, Casey; Qaisi, Ramy; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance.

Designing hybrid gate dielectric for fully printing high-performance carbon nanotube thin film transistors

NASA Astrophysics Data System (ADS)

Li, Qian; Li, Shilong; Yang, Dehua; Su, Wei; Wang, Yanchun; Zhou, Weiya; Liu, Huaping; Xie, Sishen

2017-10-01

The electrical characteristics of carbon nanotube (CNT) thin-film transistors (TFTs) strongly depend on the properties of the gate dielectric that is in direct contact with the semiconducting CNT channel materials. Here, we systematically investigated the dielectric effects on the electrical characteristics of fully printed semiconducting CNT-TFTs by introducing the organic dielectrics of poly(methyl methacrylate) (PMMA) and octadecyltrichlorosilane (OTS) to modify SiO2 dielectric. The results showed that the organic-modified SiO2 dielectric formed a favorable interface for the efficient charge transport in s-SWCNT-TFTs. Compared to single-layer SiO2 dielectric, the use of organic-inorganic hybrid bilayer dielectrics dramatically improved the performances of SWCNT-TFTs such as mobility, threshold voltage, hysteresis and on/off ratio due to the suppress of charge scattering, gate leakage current and charge trapping. The transport mechanism is related that the dielectric with few charge trapping provided efficient percolation pathways for charge carriers, while reduced the charge scattering. High density of charge traps which could directly act as physical transport barriers and significantly restrict the charge carrier transport and, thus, result in decreased mobile carriers and low device performance. Moreover, the gate leakage phenomenon is caused by conduction through charge traps. So, as a component of TFTs, the gate dielectric is of crucial importance to the manufacture of high quality TFTs from the aspects of affecting the gate leakage current and device operation voltage, as well as the charge carrier transport. Interestingly, the OTS-modified SiO2 allows to directly print horizontally aligned CNT film, and the corresponding devices exhibited a higher mobility than that of the devices with the hybrid PMMA/SiO2 dielectric although the thickness of OTS layer is only ˜2.5 nm. Our present result may provide key guidance for the further development of printed

Oxygen vacancy defect engineering using atomic layer deposited HfAlO{sub x} in multi-layered gate stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bhuyian, M. N., E-mail: mnb3@njit.edu; Misra, D.; Sengupta, R.

2016-05-02

This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlO{sub x} with extremely low Al (<3% Al/(Al + Hf)) incorporation in the Hf based high-k dielectrics. The defect activation energy estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V{sup +}/V{sup 2+}, are the primary source of defects in these dielectrics. When Al is added in HfO{sub 2}, the V{sup +} type defects with a defect activation energy of E{sub a} ∼ 0.2 eV modify to V{sup 2+} type to E{sub a} ∼ 0.1 eV with reference to the Si conduction band. When devices were stressedmore » in the gate injection mode for 1000 s, more V{sup +} type defects are generated and E{sub a} reverts back to ∼0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO{sub 2} contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C.« less

A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr x Si1- x O2 Gate dielectric and improved electrical and hysteresis performance

NASA Astrophysics Data System (ADS)

Hung, Chien-Hsiung; Wang, Shui-Jinn; Liu, Pang-Yi; Wu, Chien-Hung; Wu, Nai-Sheng; Yan, Hao-Ping; Lin, Tseng-Hsing

2017-04-01

The use of co-sputtered zirconium silicon oxide (Zr x Si1- x O2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150 W and with that of the ZrO2 target kept at 100 W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr x Si1- x O2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103 mV/dec) and field effect mobility (33.76 cm2 V-1 s-1).

Isotope analysis of diamond-surface passivation effect of high-temperature H{sub 2}O-grown atomic layer deposition-Al{sub 2}O{sub 3} films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hiraiwa, Atsushi, E-mail: hiraiwa@aoni.waseda.jp, E-mail: qs4a-hriw@asahi-net.or.jp; Saito, Tatsuya; Matsumura, Daisuke

2015-06-07

The Al{sub 2}O{sub 3} film formed using an atomic layer deposition (ALD) method with trimethylaluminum as Al precursor and H{sub 2}O as oxidant at a high temperature (450 °C) effectively passivates the p-type surface conduction (SC) layer specific to a hydrogen-terminated diamond surface, leading to a successful operation of diamond SC field-effect transistors at 400 °C. In order to investigate this excellent passivation effect, we carried out an isotope analysis using D{sub 2}O instead of H{sub 2}O in the ALD and found that the Al{sub 2}O{sub 3} film formed at a conventional temperature (100 °C) incorporates 50 times more CH{sub 3} groups thanmore » the high-temperature film. This CH{sub 3} is supposed to dissociate from the film when heated afterwards at a higher temperature (550 °C) and causes peeling patterns on the H-terminated surface. The high-temperature film is free from this problem and has the largest mass density and dielectric constant among those investigated in this study. The isotope analysis also unveiled a relatively active H-exchange reaction between the diamond H-termination and H{sub 2}O oxidant during the high-temperature ALD, the SC still being kept intact. This dynamic and yet steady H termination is realized by the suppressed oxidation due to the endothermic reaction with H{sub 2}O. Additionally, we not only observed the kinetic isotope effect in the form of reduced growth rate of D{sub 2}O-oxidant ALD but found that the mass density and dielectric constant of D{sub 2}O-grown Al{sub 2}O{sub 3} films are smaller than those of H{sub 2}O-grown films. This is a new type of isotope effect, which is not caused by the presence of isotopes in the films unlike the traditional isotope effects that originate from the presence of isotopes itself. Hence, the high-temperature ALD is very effective in forming Al{sub 2}O{sub 3} films as a passivation and/or gate-insulation layer of high-temperature-operation diamond SC devices, and the

Bi-layer channel structure-based oxide thin-film transistors consisting of ZnO and Al-doped ZnO with different Al compositions and stacking sequences

NASA Astrophysics Data System (ADS)

Cho, Sung Woon; Yun, Myeong Gu; Ahn, Cheol Hyoun; Kim, So Hee; Cho, Hyung Koun

2015-03-01

Zinc oxide (ZnO)-based bi-layers, consisting of ZnO and Al-doped ZnO (AZO) layers grown by atomic layer deposition, were utilized as the channels of oxide thin-film transistors (TFTs). Thin AZO layers (5 nm) with different Al compositions (5 and 14 at. %) were deposited on top of and beneath the ZnO layers in a bi-layer channel structure. All of the bi-layer channel TFTs that included the AZO layers showed enhanced stability (Δ V Th ≤ 3.2 V) under a positive bias stress compared to the ZnO single-layer channel TFT (Δ V Th = 4.0 V). However, the AZO/ZnO bi-layer channel TFTs with an AZO interlayer between the gate dielectric and the ZnO showed a degraded field effect mobility (0.3 cm2/V·s for 5 at. % and 1.8 cm2/V·s for 14 at. %) compared to the ZnO single-layer channel TFT (5.5 cm2/V·s) due to increased scattering caused by Al-related impurities near the gate dielectric/channel interface. In contrast, the ZnO/AZO bi-layer channel TFTs with an AZO layer on top of the ZnO layer exhibited an improved field effect mobility (7.8 cm2/V·s for 14 at. %) and better stability. [Figure not available: see fulltext.

Localized surface plasmon enhanced deep UV-emitting of AlGaN based multi-quantum wells by Al nanoparticles on SiO2 dielectric interlayer

NASA Astrophysics Data System (ADS)

He, Ju; Wang, Shuai; Chen, Jingwen; Wu, Feng; Dai, Jiangnan; Long, Hanling; Zhang, Yi; Zhang, Wei; Feng, Zhe Chuan; Zhang, Jun; Du, Shida; Ye, Lei; Chen, Changqing

2018-05-01

In this paper, we report a 2.6-fold deep ultraviolet emission enhancement of integrated photoluminescence (PL) intensity in AlGaN-based multi-quantum wells (MQWs) by introducing the coupling of local surface plasmons from Al nanoparticles (NPs) on a SiO2 dielectric interlayer with excitons and photons in MQWs at room temperature. In comparison to bare AlGaN MQWs, a significant 2.3-fold enhancement of the internal quantum efficiency, from 16% to 37%, as well as a 13% enhancement of photon extraction efficiency have been observed in the MQWs decorated with Al NPs on SiO2 dielectric interlayer. Polarization-dependent PL measurement showed that both the transverse electric and transverse magnetic mode were stronger than the original intensity in bare AlGaN MQWs, indicating a strong LSPs coupling process and vigorous scattering ability of the Al/SiO2 composite structure. These results were confirmed by the activation energy of non-radiative recombination from temperature-dependent PL measurement and the theoretical three dimensional finite difference time domain calculations.

Localized surface plasmon enhanced deep UV-emitting of AlGaN based multi-quantum wells by Al nanoparticles on SiO2 dielectric interlayer.

PubMed

He, Ju; Wang, Shuai; Chen, Jingwen; Wu, Feng; Dai, Jiangnan; Long, Hanling; Zhang, Yi; Zhang, Wei; Feng, Zhe Chuan; Zhang, Jun; Du, Shida; Ye, Lei; Chen, Changqing

2018-05-11

In this paper, we report a 2.6-fold deep ultraviolet emission enhancement of integrated photoluminescence (PL) intensity in AlGaN-based multi-quantum wells (MQWs) by introducing the coupling of local surface plasmons from Al nanoparticles (NPs) on a SiO 2 dielectric interlayer with excitons and photons in MQWs at room temperature. In comparison to bare AlGaN MQWs, a significant 2.3-fold enhancement of the internal quantum efficiency, from 16% to 37%, as well as a 13% enhancement of photon extraction efficiency have been observed in the MQWs decorated with Al NPs on SiO 2 dielectric interlayer. Polarization-dependent PL measurement showed that both the transverse electric and transverse magnetic mode were stronger than the original intensity in bare AlGaN MQWs, indicating a strong LSPs coupling process and vigorous scattering ability of the Al/SiO 2 composite structure. These results were confirmed by the activation energy of non-radiative recombination from temperature-dependent PL measurement and the theoretical three dimensional finite difference time domain calculations.

Enhanced self-repairing capability of sol-gel derived SrTiO3/nano Al2O3 composite films

NASA Astrophysics Data System (ADS)

Yao, Manwen; Peng, Yong; Xiao, Ruihua; Li, Qiuxia; Yao, Xi

2016-08-01

SrTiO3/nano Al2O3 inorganic nanocomposites were prepared by using a conventional sol-gel spin coating process. For comparison, SrTiO3 films doped by equivalent amount of sol-Al2O3 have also been investigated. Aluminum deposited by using vacuum evaporation was used as the top electrode. The nanocomposites exhibited a significantly enhanced dielectric strength of 506.9 MV/m, which was increased by 97.4% as compared with the SrTiO3 films doped with sol-Al2O3. The leakage current maintained of the same order of microampere until the ultimate breakdown of the nanocomposites. The excellent electrical performances are ascribed to the anodic oxidation reaction in origin, which can repair the internal and/or surface defects of the films.

High-κ gate dielectrics: Current status and materials properties considerations

NASA Astrophysics Data System (ADS)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

PubMed

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

“Thermal Stabilization Effect” of Al2O3 nano-dopants improves the high-temperature dielectric performance of polyimide

PubMed Central

Yang, Yang; He, Jinliang; Wu, Guangning; Hu, Jun

2015-01-01

Insulation performance of the dielectrics under extreme conditions always attracts widespread attention in electrical and electronic field. How to improve the high-temperature dielectric properties of insulation materials is one of the key issues in insulation system design of electrical devices. This paper studies the temperature-dependent corona resistance of polyimide (PI)/Al2O3 nanocomposite films under high-frequency square-wave pulse conditions. Extended corona resistant lifetime under high-temperature conditions is experimentally observed in the 2 wt% nanocomposite samples. The “thermal stabilization effect” is proposed to explain this phenomenon which attributes to a new kind of trap band caused by nanoparticles. This effect brings about superior space charge characteristics and corona resistance under high temperature with certain nano-doping concentration. The proposed theory is experimentally demonstrated by space charge analysis and thermally stimulated current (TSC) tests. This discovered effect is of profound significance on improving high-temperature dielectric properties of nanocomposites towards various applications. PMID:26597981

Volatile organic compounds emission control in industrial pollution source using plasma technology coupled with F-TiO2/γ-Al2O3.

PubMed

Zhu, Tao; Chen, Rui; Xia, Ni; Li, Xiaoyang; He, Xianxian; Zhao, Wenjuan; Carr, Tim

2015-01-01

Volatile organic compounds' (VOCs) effluents, which come from many industries, are triggering serious environmental problems. As an emerging technology, non-thermal plasma (NTP) technology is a potential technology for VOCs emission control. NTP coupled with F-TiO2/γ-Al2O3 is used for toluene removal from a gaseous influent at normal temperature and atmospheric pressure. NTP is generated by dielectric barrier discharge, and F-TiO2/γ-Al2O3 can be prepared by sol-gel method in the laboratory. In the experiment, the different packed materials were packed into the plasma reactor, including γ-Al2O3, TiO2/γ-Al2O3 and F-TiO2/γ-Al2O3. Through a series of characterization methods such as X-ray diffraction, scanning electronic microscopy and Brunner-Emmet-Teller measurements, the results show that the particle size distribution of F-TiO2 is relatively smaller than that of TiO2, and the pore distribution of F-TiO2 is more uniformly distributed than that of TiO2. The relationships among toluene removal efficiency, reactor input energy density, and the equivalent capacitances of air gap and dielectric barrier layer were investigated. The results show that the synergistic technology NTP with F-TiO2/γ-Al2O3 resulted in greater enhancement of toluene removal efficiency and energy efficiency. Especially, when packing with F-TiO2/γ-Al2O3 in NTP reactor, toluene removal efficiency reaches 99% and higher. Based on the data analysis of Fourier Transform Infrared Spectroscopy, the experimental results showed that NTP reactor packed with F-TiO2/γ-Al2O3 resulted in a better inhibition for by-products formation effectively in the gas exhaust.

Electrically programmable-erasable In-Ga-Zn-O thin-film transistor memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Qian, Shi-Bing; Zhang, Wen-Peng; Liu, Wen-Jun

Amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) memory is very promising for transparent and flexible system-on-panel displays; however, electrical erasability has always been a severe challenge for this memory. In this article, we demonstrated successfully an electrically programmable-erasable memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack under a maximal processing temperature of 300 {sup o}C. As the programming voltage was enhanced from 14 to 19 V for a constant pulse of 0.2 ms, the threshold voltage shift increased significantly from 0.89 to 4.67 V. When the programmed device was subjected to an appropriate pulse under negative gatemore » bias, it could return to the original state with a superior erasing efficiency. The above phenomena could be attributed to Fowler-Nordheim tunnelling of electrons from the IGZO channel to the Pt nanocrystals during programming, and inverse tunnelling of the trapped electrons during erasing. In terms of 0.2-ms programming at 16 V and 350-ms erasing at −17 V, a large memory window of 3.03 V was achieved successfully. Furthermore, the memory exhibited stable repeated programming/erasing (P/E) characteristics and good data retention, i.e., for 2-ms programming at 14 V and 250-ms erasing at −14 V, a memory window of 2.08 V was still maintained after 10{sup 3} P/E cycles, and a memory window of 1.1 V was retained after 10{sup 5} s retention time.« less

Transferred wrinkled Al2O3 for highly stretchable and transparent graphene-carbon nanotube transistors

NASA Astrophysics Data System (ADS)

Chae, Sang Hoon; Yu, Woo Jong; Bae, Jung Jun; Duong, Dinh Loc; Perello, David; Jeong, Hye Yun; Ta, Quang Huy; Ly, Thuc Hue; Vu, Quoc An; Yun, Minhee; Duan, Xiangfeng; Lee, Young Hee

2013-05-01

Despite recent progress in producing transparent and bendable thin-film transistors using graphene and carbon nanotubes, the development of stretchable devices remains limited either by fragile inorganic oxides or polymer dielectrics with high leakage current. Here we report the fabrication of highly stretchable and transparent field-effect transistors combining graphene/single-walled carbon nanotube (SWCNT) electrodes and a SWCNT-network channel with a geometrically wrinkled inorganic dielectric layer. The wrinkled Al2O3 layer contained effective built-in air gaps with a small gate leakage current of 10-13 A. The resulting devices exhibited an excellent on/off ratio of ~105, a high mobility of ~40 cm2 V-1 s-1 and a low operating voltage of less than 1 V. Importantly, because of the wrinkled dielectric layer, the transistors retained performance under strains as high as 20% without appreciable leakage current increases or physical degradation. No significant performance loss was observed after stretching and releasing the devices for over 1,000 times. The sustainability and performance advances demonstrated here are promising for the adoption of stretchable electronics in a wide variety of future applications.

Phase Transitions of KIO3 Ferroelectrics in Al2O3-Based Nanoporous Matrices

NASA Astrophysics Data System (ADS)

Milinskii, A. Yu.; Baryshnikov, S. V.

2018-03-01

Temperature dependences of the linear permittivity ɛ' and the third harmonic amplitude γ3ω of composites prepared by introducing ferroelectrics KIO3 into matrices of porous aluminum oxide Al2O3 with pore sizes of 240 nm were studied. It is found that the IV → III and III → II structural transition temperatures of potassium iodide in Al2O3 pores decrease by 5 K and 24 K, respectively, with respect to bulk KIO3. The measurements of the dielectric properties do not reveal V → IV and II → I phase transitions in the composite samples.

Correlation between border traps and exposed surface properties in gate recessed normally-off Al2O3/GaN MOSFET

NASA Astrophysics Data System (ADS)

Yin, Ruiyuan; Li, Yue; Sun, Yu; Wen, Cheng P.; Hao, Yilong; Wang, Maojun

2018-06-01

We report the effect of the gate recess process and the surface of as-etched GaN on the gate oxide quality and first reveal the correlation between border traps and exposed surface properties in normally-off Al2O3/GaN MOSFET. The inductively coupled plasma (ICP) dry etching gate recess with large damage presents a rough and active surface that is prone to form detrimental GaxO validated by atomic force microscopy and X-ray photoelectron spectroscopy. Lower drain current noise spectral density of the 1/f form and less dispersive ac transconductance are observed in GaN MOSFETs fabricated with oxygen assisted wet etching compared with devices based on ICP dry etching. One decade lower density of border traps is extracted in devices with wet etching according to the carrier number fluctuation model, which is consistent with the result from the ac transconductance method. Both methods show that the density of border traps is skewed towards the interface, indicating that GaxO is of higher trap density than the bulk gate oxide. GaxO located close to the interface is the major location of border traps. The damage-free oxidation assisted wet etching gate recess technique presents a relatively smooth and stable surface, resulting in lower border trap density, which would lead to better MOS channel quality and improved device reliability.

Four-Element Composite Triangular Dielectric Resonator Antenna Using Li2O-1.94MgO-0.02Al2O3-P2O5 Ceramic for Wideband Applications

NASA Astrophysics Data System (ADS)

Kumari, Preeti; Tripathi, Pankaj; Sahu, B.; Singh, S. P.; Kumar, Devendra

2018-05-01

A simulation and fabrication study of a coaxial probe-fed four-element composite triangular dielectric resonator antenna (TDRA) using low loss Li2O-1.94MgO-0.02Al2O3-P2O5 (LMAP) ceramic and Teflon. LMAP ceramic was carried out and the ceramic was synthesized using a solid-state sintering route. The phase, microstructure and microwave dielectric properties of LMAP were investigated using x-ray diffraction pattern, scanning electron microscopy and a network analyzer. A coaxial probe-fed four-element composite TDRA was designed and fabricated using LMAP as one section of each composite element of the proposed antenna. Each triangular element of the proposed dielectric resonator antenna (DRA) consists of two sections of different dielectric constant materials. The inner triangular section touching the coaxial probe at one of its corners is made of the LMAP ceramic (ɛ r = 6.2) while othe uter section is made of Teflon (ɛ r = 2.1). Four triangular DRA elements are excited bya centrally located 50-Ω coaxial probe. The parametric study of the proposed antenna was performed through simulation using Ansys High Frequency Structure Simulator software by varying the dimensions and dielectric constants of both sections of each triangular element of the TDRA to optimize the results for obtaining a wideband antenna. The simulated resonant frequency of 9.30 GHz with a percentage bandwidth of 61.65% for the proposed antenna is obtained within its operating frequency range of 7.82-14.8 GHz. Monopole-like radiation patterns with low cross-polarization levels and a peak gain of 5.63 dB are obtained for the proposed antenna through simulation. The antenna prototype having optimized dimensions has also been fabricated. The experimental resonant frequency of 9.10 GHz with a percentage bandwidth of 66.09% is obtained within its operating frequency range of 7.70-15.30 GHz. It is found that the simulation results for the proposed antenna are in close agreement with the measured data. The

Top and Split Gating Control of the Electrical Characteristics of a Two-dimensional Electron Gas in a LaAlO3/SrTiO3 Perovskite

NASA Astrophysics Data System (ADS)

Kwak, Yongsu; Song, Jonghyun; Kim, Jihwan; Kim, Jinhee

2018-04-01

A top gate field effect transistor was fabricated using polymethyl methacrylate (PMMA) as a gate insulator on a LaAlO3 (LAO)/SrTiO3 (STO) hetero-interface. It showed n-type behavior, and a depletion mode was observed at low temperature. The electronic properties of the 2-dimensional electron gas at the LAO/STO hetero-interface were not changed by covering LAO with PMMA following the Au top gate electrode. A split gate device was also fabricated to construct depletion mode by using a narrow constriction between the LAO/STO conduction interface. The depletion mode, as well as superconducting critical current, could be controlled by applying a split gate voltage. Noticeably, the superconducting critical current tended to decrease with decreasing the split gate voltage and finally became zero. These results indicate that a weak-linked Josephson junction can be constructed and destroyed by split gating. This observation opens the possibility of gate-voltage-adjustable quantum devices.

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al{sub 2}O{sub 3} gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aoki, Takeshi, E-mail: aokit@sc.sumitomo-chem.co.jp; Fukuhara, Noboru; Osada, Takenori

2015-08-15

This paper presents a compressive study on the fabrication and optimization of GaAs metal–oxide–semiconductor (MOS) structures comprising a Al{sub 2}O{sub 3} gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal–organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al{sub 2}O{sub 3} in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al{sub 2}O{sub 3} layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resultingmore » MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance–voltage (C–V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (D{sub it}) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce D{sub it} to below 2 × 10{sup 12} cm{sup −2} eV{sup −1}. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.« less

Lanthanide-based oxides and silicates for high-kappa gate dielectric applications

NASA Astrophysics Data System (ADS)

Jur, Jesse Stephen

The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high current leakage between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high-kappa dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-kappa dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. In this work, lanthanum oxide films have been deposited by thermal evaporation on to a pre-grown chemical oxide layer on silicon. It is observed that the SiO2 interfacial layer can be consumed by a low-temperature reaction with lanthanum oxide to produce a high-quality silicate. This is opposed to depositing lanthanum oxide directly on silicon, which can possibly favor silicide formation. The importance of oxygen regulation in the surrounding environment of the La2O3-SiO2 reaction-anneal is observed. By controlling the oxygen available during the reaction, SiO2 growth can be limited to achieve high stoichiometric ratios of La2O 3 to SiO2. As a result, MOS devices with an equivalent oxide thickness (EOT) of 5 A and a leakage current density of 5.0 A/cm 2 are attained. This data equals the best value achieved in this field and is a

Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S.

Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer intomore » the IGZO and resulted in higher resistivity films.« less

Impact of bimetal electrodes on dielectric properties of TiO2 and Al-doped TiO2 films.

PubMed

Kim, Seong Keun; Han, Sora; Jeon, Woojin; Yoon, Jung Ho; Han, Jeong Hwan; Lee, Woongkyu; Hwang, Cheol Seong

2012-09-26

Rutile structured Al-doped TiO(2) (ATO) and TiO(2) films were grown on bimetal electrodes (thin Ru/thick TiN, Pt, and Ir) for high-performance capacitors. The work function of the top Ru layer decreased on TiN and increased on Pt and Ir when it was thinner than ~2 nm, suggesting that the lower metal within the electrodes influences the work function of the very thin Ru layer. The use of the lower electrode with a high work function for bottom electrode eventually improves the leakage current properties of the capacitor at a very thin Ru top layer (≤2 nm) because of the increased Schottky barrier height at the interface between the dielectric and the bottom electrode. The thin Ru layer was necessary to achieve the rutile structured ATO and TiO(2) dielectric films.

Effect of the addition of B{sub 2}O{sub 3} and BaO-B{sub 2}O{sub 3}-SiO{sub 2} glasses on the microstructure and dielectric properties of giant dielectric constant material CaCu{sub 3}Ti{sub 4}O{sub 12}

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shri Prakash, B.; Varma, K.B.R.

2007-06-15

The effect of the addition of glassy phases on the microstructure and dielectric properties of CaCu{sub 3}Ti{sub 4}O{sub 12} (CCTO) ceramics was investigated. Both single-component (B{sub 2}O{sub 3}) and multi-component (30 wt% BaO-60 wt% B{sub 2}O{sub 3}-10 wt% SiO{sub 2} (BBS)) glass systems were chosen to study their effect on the density, microstructure and dielectric properties of CCTO. Addition of an optimum amount of B{sub 2}O{sub 3} glass facilitated grain growth and an increase in dielectric constant. However, further increase in the B{sub 2}O{sub 3} content resulted in its segregation at the grain boundaries associated with a reduction in themore » grain size. In contrast, BBS glass addition resulted in well-faceted grains and increase in the dielectric constant and decrease in the dielectric loss. An internal barrier layer capacitance (IBLC) model was invoked to correlate the dielectric constant with the grain size in these samples. - Graphical abstract: Scanning electron micrograph of 30 wt% BaO-60 wt% B{sub 2}O{sub 3}-10 wt% SiO{sub 2} (BBS) glass-added CaCu{sub 3}Ti{sub 4}O{sub 12} ceramic on sintering.« less

Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

NASA Astrophysics Data System (ADS)

Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

2018-01-01

Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

Frequency-Stable Ionic-Type Hybrid Gate Dielectrics for High Mobility Solution-Processed Metal-Oxide Thin-Film Transistors

PubMed Central

Heo, Jae Sang; Choi, Seungbeom; Jo, Jeong-Wan; Kang, Jingu; Park, Ho-Hyun; Kim, Yong-Hoon; Park, Sung Kyu

2017-01-01

In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs) by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD). The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx) and poly(4-vinylphenol) (PVP), exhibited high dielectric constant (ε~8.15) and high-frequency-stable characteristics (1 MHz). Using the ionic-type HGD as a gate dielectric layer, an minimal electron-double-layer (EDL) can be formed at the gate dielectric/InOx interface, enhancing the field-effect mobility of the TFTs. Particularly, using the ionic-type HGD gate dielectrics annealed at 350 °C, InOx TFTs having an average field-effect mobility of 16.1 cm2/Vs were achieved (maximum mobility of 24 cm2/Vs). Furthermore, the ionic-type HGD gate dielectrics can be processed at a low temperature of 150 °C, which may enable their applications in low-thermal-budget plastic and elastomeric substrates. In addition, we systematically studied the operational stability of the InOx TFTs using the HGD gate dielectric, and it was observed that the HGD gate dielectric effectively suppressed the negative threshold voltage shift during the negative-illumination-bias stress possibly owing to the recombination of hole carriers injected in the gate dielectric with the negatively charged ionic species in the HGD gate dielectric. PMID:28772972

Temperature-dependent degradation mechanisms of threshold voltage in La2O3-gated n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Ming-Tsong; Hsu, De-Cheng; Juan, Pi-Chun; Wang, Y. L.; Lee, Joseph Ya-min

2010-09-01

Metal-oxide-semiconductor capacitors and n-channel metal-oxide-semiconductor field-effect transistors with La2O3 gate dielectric were fabricated. The positive bias temperature instability was studied. The degradation of threshold voltage (ΔVT) showed an exponential dependence on the stress time in the temperature range from 25 to 75 °C. The degradation of subthreshold slope (ΔS) and gate leakage (IG) with stress voltage was also measured. The degradation of VT is attributed to the oxide trap charges Qot. The extracted activation energy of 0.2 eV is related to a degradation dominated by the release of atomic hydrogen in La2O3 thin films.

Temperature compensation effects of TiO2 on Ca[(Li1/3Nb2/3)0.8Sn0.2]O3-δ microwave dielectric ceramic

NASA Astrophysics Data System (ADS)

Hu, Mingzhe; Wei, Huanghe; Xiao, Lihua; Zhang, Kesheng; Hao, Yongde

2017-10-01

The crystal structure and dielectric properties of TiO2-modified Ca[(Li1/3Nb2/3)0.8Sn0.2]O3-δ microwave ceramics are investigated in the present paper. The crystal structure is probed by XRD patterns and their Rietveld refinement, results show that a single perovskite phase is formed in TiO2-modified Ca[(Li1/3Nb2/3)0.8Sn0.2]O3-δ ceramics with the crystal structure belonging to the orthorhombic Pbnm 62 space group. Raman spectra results indicate that the B-site order-disorder structure transition is a key point to the dielectric loss of TiO2-modified Ca[(Li1/3Nb2/3)0.8Sn0.2]O3-δ ceramics at microwave frequencies. After properly modified by TiO2, the large negative temperature coefficient of Ca[(Li1/3Nb2/3)0.8Sn0.2]O3-δ ceramic can be compensated and the optimal microwave dielectric properties can reach 𝜀r = 25.66, Qf = 18,894 GHz and TCF = -6.3 ppm/∘C when sintered at 1170∘C for 2.5 h, which manifests itself for potential use in microwave dielectric devices for modern wireless communication.

Electrical hysteresis in p-GaN metal-oxide-semiconductor capacitor with atomic-layer-deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Zhang, Kexiong; Liao, Meiyong; Imura, Masataka; Nabatame, Toshihide; Ohi, Akihiko; Sumiya, Masatomo; Koide, Yasuo; Sang, Liwen

2016-12-01

The electrical hysteresis in current-voltage (I-V) and capacitance-voltage characteristics was observed in an atomic-layer-deposited Al2O3/p-GaN metal-oxide-semiconductor capacitor (PMOSCAP). The absolute minimum leakage currents of the PMOSCAP for forward and backward I-V scans occurred not at 0 V but at -4.4 and +4.4 V, respectively. A negative flat-band voltage shift of 5.5 V was acquired with a capacitance step from +4.4 to +6.1 V during the forward scan. Mg surface accumulation on p-GaN was demonstrated to induce an Mg-Ga-Al-O oxidized layer with a trap density on the order of 1013 cm-2. The electrical hysteresis is attributed to the hole trapping and detrapping process in the traps of the Mg-Ga-Al-O layer via the Poole-Frenkel mechanism.

Impacts of Annealing Conditions on the Flat Band Voltage of Alternate La2O3/Al2O3 Multilayer Stack Structures.

PubMed

Feng, Xing-Yao; Liu, Hong-Xia; Wang, Xing; Zhao, Lu; Fei, Chen-Xi; Liu, He-Lei

2016-12-01

The mechanism of flat band voltage (VFB) shift for alternate La2O3/Al2O3 multilayer stack structures in different annealing condition is investigated. The samples were prepared for alternate multilayer structures, which were annealed in different conditions. The capacitance-voltage (C-V) measuring results indicate that the VFB of samples shift negatively for thinner bottom Al2O3 layer, increasing annealing temperature or longer annealing duration. Simultaneously, the diffusion of high-k material to interfaces in different multilayer structures and annealing conditions is observed by X-ray photoelectron spectroscopy (XPS). Based on the dipole theory, a correlation between the diffusion effect of La towards bottom Al2O3/Si interface and VFB shift is found. Without changing the dielectric constant k of films, VFB shift can be manipulated by controlling the single-layer cycles and annealing conditions of alternate high-k multilayer stack.

A comparative study of photoconductivity in LaTiO3/SrTiO3 and LaAlO3/SrTiO3 2-DEG heterostructures

NASA Astrophysics Data System (ADS)

Rastogi, A.; Hossain, Z.; Budhani, R. C.

2013-02-01

Here we compare the growth temperature dependence of the response of LaTiO3/SrTiO3 and LaAlO3/SrTiO3 2D-electron gas (2-DEG) field effect structure to the optical radiation of near ultraviolet frequency and electrostatic gate field. For both the films the resistance of the channel increases significantly as growth temperature is lowered from 800 to 700 °C. These heterostructures show the photoconductivity (PC) simulated by UV light of λ ≤ 400 nm. The PC follows the stretched exponential dynamics. It is found that photo-response of the LaTiO3 films is prominent and has larger decay time constant as compare to LaAlO3 films. The effect of electric field on the photo-induced conducting state is also studied.